1*14b24e2bSVaishali Kulkarni /*
2*14b24e2bSVaishali Kulkarni * CDDL HEADER START
3*14b24e2bSVaishali Kulkarni *
4*14b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the
5*14b24e2bSVaishali Kulkarni * Common Development and Distribution License, v.1,  (the "License").
6*14b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License.
7*14b24e2bSVaishali Kulkarni *
8*14b24e2bSVaishali Kulkarni * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9*14b24e2bSVaishali Kulkarni * or http://opensource.org/licenses/CDDL-1.0.
10*14b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions
11*14b24e2bSVaishali Kulkarni * and limitations under the License.
12*14b24e2bSVaishali Kulkarni *
13*14b24e2bSVaishali Kulkarni * When distributing Covered Code, include this CDDL HEADER in each
14*14b24e2bSVaishali Kulkarni * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15*14b24e2bSVaishali Kulkarni * If applicable, add the following below this CDDL HEADER, with the
16*14b24e2bSVaishali Kulkarni * fields enclosed by brackets "[]" replaced with your own identifying
17*14b24e2bSVaishali Kulkarni * information: Portions Copyright [yyyy] [name of copyright owner]
18*14b24e2bSVaishali Kulkarni *
19*14b24e2bSVaishali Kulkarni * CDDL HEADER END
20*14b24e2bSVaishali Kulkarni */
21*14b24e2bSVaishali Kulkarni 
22*14b24e2bSVaishali Kulkarni /*
23*14b24e2bSVaishali Kulkarni * Copyright 2014-2017 Cavium, Inc.
24*14b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the Common Development
25*14b24e2bSVaishali Kulkarni * and Distribution License, v.1,  (the "License").
26*14b24e2bSVaishali Kulkarni 
27*14b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License.
28*14b24e2bSVaishali Kulkarni 
29*14b24e2bSVaishali Kulkarni * You can obtain a copy of the License at available
30*14b24e2bSVaishali Kulkarni * at http://opensource.org/licenses/CDDL-1.0
31*14b24e2bSVaishali Kulkarni 
32*14b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions and
33*14b24e2bSVaishali Kulkarni * limitations under the License.
34*14b24e2bSVaishali Kulkarni */
35*14b24e2bSVaishali Kulkarni 
36*14b24e2bSVaishali Kulkarni #ifndef __ECORE_HSI_ROCE__
37*14b24e2bSVaishali Kulkarni #define __ECORE_HSI_ROCE__
38*14b24e2bSVaishali Kulkarni /************************************************************************/
39*14b24e2bSVaishali Kulkarni /* Add include to ecore hsi rdma target for both roce and iwarp ecore driver */
40*14b24e2bSVaishali Kulkarni /************************************************************************/
41*14b24e2bSVaishali Kulkarni #include "ecore_hsi_rdma.h"
42*14b24e2bSVaishali Kulkarni /************************************************************************/
43*14b24e2bSVaishali Kulkarni /* Add include to common roce target for both eCore and protocol roce driver */
44*14b24e2bSVaishali Kulkarni /************************************************************************/
45*14b24e2bSVaishali Kulkarni #include "roce_common.h"
46*14b24e2bSVaishali Kulkarni 
47*14b24e2bSVaishali Kulkarni /*
48*14b24e2bSVaishali Kulkarni  * The roce storm context of Mstorm
49*14b24e2bSVaishali Kulkarni  */
50*14b24e2bSVaishali Kulkarni struct mstorm_roce_conn_st_ctx
51*14b24e2bSVaishali Kulkarni {
52*14b24e2bSVaishali Kulkarni 	struct regpair temp[6];
53*14b24e2bSVaishali Kulkarni };
54*14b24e2bSVaishali Kulkarni 
55*14b24e2bSVaishali Kulkarni 
56*14b24e2bSVaishali Kulkarni /*
57*14b24e2bSVaishali Kulkarni  * The roce storm context of Mstorm
58*14b24e2bSVaishali Kulkarni  */
59*14b24e2bSVaishali Kulkarni struct pstorm_roce_conn_st_ctx
60*14b24e2bSVaishali Kulkarni {
61*14b24e2bSVaishali Kulkarni 	struct regpair temp[16];
62*14b24e2bSVaishali Kulkarni };
63*14b24e2bSVaishali Kulkarni 
64*14b24e2bSVaishali Kulkarni 
65*14b24e2bSVaishali Kulkarni /*
66*14b24e2bSVaishali Kulkarni  * The roce storm context of Ystorm
67*14b24e2bSVaishali Kulkarni  */
68*14b24e2bSVaishali Kulkarni struct ystorm_roce_conn_st_ctx
69*14b24e2bSVaishali Kulkarni {
70*14b24e2bSVaishali Kulkarni 	struct regpair temp[2];
71*14b24e2bSVaishali Kulkarni };
72*14b24e2bSVaishali Kulkarni 
73*14b24e2bSVaishali Kulkarni /*
74*14b24e2bSVaishali Kulkarni  * The roce storm context of Xstorm
75*14b24e2bSVaishali Kulkarni  */
76*14b24e2bSVaishali Kulkarni struct xstorm_roce_conn_st_ctx
77*14b24e2bSVaishali Kulkarni {
78*14b24e2bSVaishali Kulkarni 	struct regpair temp[24];
79*14b24e2bSVaishali Kulkarni };
80*14b24e2bSVaishali Kulkarni 
81*14b24e2bSVaishali Kulkarni /*
82*14b24e2bSVaishali Kulkarni  * The roce storm context of Tstorm
83*14b24e2bSVaishali Kulkarni  */
84*14b24e2bSVaishali Kulkarni struct tstorm_roce_conn_st_ctx
85*14b24e2bSVaishali Kulkarni {
86*14b24e2bSVaishali Kulkarni 	struct regpair temp[30];
87*14b24e2bSVaishali Kulkarni };
88*14b24e2bSVaishali Kulkarni 
89*14b24e2bSVaishali Kulkarni /*
90*14b24e2bSVaishali Kulkarni  * The roce storm context of Ystorm
91*14b24e2bSVaishali Kulkarni  */
92*14b24e2bSVaishali Kulkarni struct ustorm_roce_conn_st_ctx
93*14b24e2bSVaishali Kulkarni {
94*14b24e2bSVaishali Kulkarni 	struct regpair temp[12];
95*14b24e2bSVaishali Kulkarni };
96*14b24e2bSVaishali Kulkarni 
97*14b24e2bSVaishali Kulkarni /*
98*14b24e2bSVaishali Kulkarni  * roce connection context
99*14b24e2bSVaishali Kulkarni  */
100*14b24e2bSVaishali Kulkarni struct roce_conn_context
101*14b24e2bSVaishali Kulkarni {
102*14b24e2bSVaishali Kulkarni 	struct ystorm_roce_conn_st_ctx ystorm_st_context /* ystorm storm context */;
103*14b24e2bSVaishali Kulkarni 	struct regpair ystorm_st_padding[2] /* padding */;
104*14b24e2bSVaishali Kulkarni 	struct pstorm_roce_conn_st_ctx pstorm_st_context /* pstorm storm context */;
105*14b24e2bSVaishali Kulkarni 	struct xstorm_roce_conn_st_ctx xstorm_st_context /* xstorm storm context */;
106*14b24e2bSVaishali Kulkarni 	struct regpair xstorm_st_padding[2] /* padding */;
107*14b24e2bSVaishali Kulkarni 	struct e4_xstorm_rdma_conn_ag_ctx xstorm_ag_context /* xstorm aggregative context */;
108*14b24e2bSVaishali Kulkarni 	struct e4_tstorm_rdma_conn_ag_ctx tstorm_ag_context /* tstorm aggregative context */;
109*14b24e2bSVaishali Kulkarni 	struct timers_context timer_context /* timer context */;
110*14b24e2bSVaishali Kulkarni 	struct e4_ustorm_rdma_conn_ag_ctx ustorm_ag_context /* ustorm aggregative context */;
111*14b24e2bSVaishali Kulkarni 	struct tstorm_roce_conn_st_ctx tstorm_st_context /* tstorm storm context */;
112*14b24e2bSVaishali Kulkarni 	struct mstorm_roce_conn_st_ctx mstorm_st_context /* mstorm storm context */;
113*14b24e2bSVaishali Kulkarni 	struct ustorm_roce_conn_st_ctx ustorm_st_context /* ustorm storm context */;
114*14b24e2bSVaishali Kulkarni 	struct regpair ustorm_st_padding[2] /* padding */;
115*14b24e2bSVaishali Kulkarni };
116*14b24e2bSVaishali Kulkarni 
117*14b24e2bSVaishali Kulkarni 
118*14b24e2bSVaishali Kulkarni /*
119*14b24e2bSVaishali Kulkarni  * roce create qp requester ramrod data
120*14b24e2bSVaishali Kulkarni  */
121*14b24e2bSVaishali Kulkarni struct roce_create_qp_req_ramrod_data
122*14b24e2bSVaishali Kulkarni {
123*14b24e2bSVaishali Kulkarni 	__le16 flags;
124*14b24e2bSVaishali Kulkarni #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK          0x3 /* Use roce_flavor enum */
125*14b24e2bSVaishali Kulkarni #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_SHIFT         0
126*14b24e2bSVaishali Kulkarni #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK  0x1
127*14b24e2bSVaishali Kulkarni #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 2
128*14b24e2bSVaishali Kulkarni #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_MASK        0x1
129*14b24e2bSVaishali Kulkarni #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_SHIFT       3
130*14b24e2bSVaishali Kulkarni #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_MASK                  0x7
131*14b24e2bSVaishali Kulkarni #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_SHIFT                 4
132*14b24e2bSVaishali Kulkarni #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_MASK             0x1
133*14b24e2bSVaishali Kulkarni #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_SHIFT            7
134*14b24e2bSVaishali Kulkarni #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK        0xF
135*14b24e2bSVaishali Kulkarni #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT       8
136*14b24e2bSVaishali Kulkarni #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK          0xF
137*14b24e2bSVaishali Kulkarni #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT         12
138*14b24e2bSVaishali Kulkarni 	u8 max_ord;
139*14b24e2bSVaishali Kulkarni 	u8 traffic_class /* In case of RRoCE on IPv4 will be used as TOS */;
140*14b24e2bSVaishali Kulkarni 	u8 hop_limit /* In case of RRoCE on IPv4 will be used as TTL */;
141*14b24e2bSVaishali Kulkarni 	u8 orq_num_pages;
142*14b24e2bSVaishali Kulkarni 	__le16 p_key;
143*14b24e2bSVaishali Kulkarni 	__le32 flow_label;
144*14b24e2bSVaishali Kulkarni 	__le32 dst_qp_id;
145*14b24e2bSVaishali Kulkarni 	__le32 ack_timeout_val;
146*14b24e2bSVaishali Kulkarni 	__le32 initial_psn;
147*14b24e2bSVaishali Kulkarni 	__le16 mtu;
148*14b24e2bSVaishali Kulkarni 	__le16 pd;
149*14b24e2bSVaishali Kulkarni 	__le16 sq_num_pages;
150*14b24e2bSVaishali Kulkarni 	__le16 low_latency_phy_queue;
151*14b24e2bSVaishali Kulkarni 	struct regpair sq_pbl_addr;
152*14b24e2bSVaishali Kulkarni 	struct regpair orq_pbl_addr;
153*14b24e2bSVaishali Kulkarni 	__le16 local_mac_addr[3] /* BE order */;
154*14b24e2bSVaishali Kulkarni 	__le16 remote_mac_addr[3] /* BE order */;
155*14b24e2bSVaishali Kulkarni 	__le16 vlan_id;
156*14b24e2bSVaishali Kulkarni 	__le16 udp_src_port /* Only relevant in RRoCE */;
157*14b24e2bSVaishali Kulkarni 	__le32 src_gid[4] /* BE order. In case of RRoCE on IPv4 the high register will hold the address. Low registers must be zero! */;
158*14b24e2bSVaishali Kulkarni 	__le32 dst_gid[4] /* BE order. In case of RRoCE on IPv4 the high register will hold the address. Low registers must be zero! */;
159*14b24e2bSVaishali Kulkarni 	struct regpair qp_handle_for_cqe;
160*14b24e2bSVaishali Kulkarni 	struct regpair qp_handle_for_async;
161*14b24e2bSVaishali Kulkarni 	u8 stats_counter_id /* Statistics counter ID to use */;
162*14b24e2bSVaishali Kulkarni 	u8 reserved3[7];
163*14b24e2bSVaishali Kulkarni 	__le32 cq_cid;
164*14b24e2bSVaishali Kulkarni 	__le16 regular_latency_phy_queue;
165*14b24e2bSVaishali Kulkarni 	__le16 dpi;
166*14b24e2bSVaishali Kulkarni };
167*14b24e2bSVaishali Kulkarni 
168*14b24e2bSVaishali Kulkarni 
169*14b24e2bSVaishali Kulkarni /*
170*14b24e2bSVaishali Kulkarni  * roce create qp responder ramrod data
171*14b24e2bSVaishali Kulkarni  */
172*14b24e2bSVaishali Kulkarni struct roce_create_qp_resp_ramrod_data
173*14b24e2bSVaishali Kulkarni {
174*14b24e2bSVaishali Kulkarni 	__le16 flags;
175*14b24e2bSVaishali Kulkarni #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK          0x3 /* Use roce_flavor enum */
176*14b24e2bSVaishali Kulkarni #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_SHIFT         0
177*14b24e2bSVaishali Kulkarni #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK           0x1
178*14b24e2bSVaishali Kulkarni #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT          2
179*14b24e2bSVaishali Kulkarni #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK           0x1
180*14b24e2bSVaishali Kulkarni #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT          3
181*14b24e2bSVaishali Kulkarni #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK            0x1
182*14b24e2bSVaishali Kulkarni #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT           4
183*14b24e2bSVaishali Kulkarni #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_MASK              0x1
184*14b24e2bSVaishali Kulkarni #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_SHIFT             5
185*14b24e2bSVaishali Kulkarni #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_MASK  0x1
186*14b24e2bSVaishali Kulkarni #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_SHIFT 6
187*14b24e2bSVaishali Kulkarni #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_MASK      0x1
188*14b24e2bSVaishali Kulkarni #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_SHIFT     7
189*14b24e2bSVaishali Kulkarni #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_MASK                  0x7
190*14b24e2bSVaishali Kulkarni #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_SHIFT                 8
191*14b24e2bSVaishali Kulkarni #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK    0x1F
192*14b24e2bSVaishali Kulkarni #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT   11
193*14b24e2bSVaishali Kulkarni 	u8 max_ird;
194*14b24e2bSVaishali Kulkarni 	u8 traffic_class /* In case of RRoCE on IPv4 will be used as TOS */;
195*14b24e2bSVaishali Kulkarni 	u8 hop_limit /* In case of RRoCE on IPv4 will be used as TTL */;
196*14b24e2bSVaishali Kulkarni 	u8 irq_num_pages;
197*14b24e2bSVaishali Kulkarni 	__le16 p_key;
198*14b24e2bSVaishali Kulkarni 	__le32 flow_label;
199*14b24e2bSVaishali Kulkarni 	__le32 dst_qp_id;
200*14b24e2bSVaishali Kulkarni 	u8 stats_counter_id /* Statistics counter ID to use */;
201*14b24e2bSVaishali Kulkarni 	u8 reserved1;
202*14b24e2bSVaishali Kulkarni 	__le16 mtu;
203*14b24e2bSVaishali Kulkarni 	__le32 initial_psn;
204*14b24e2bSVaishali Kulkarni 	__le16 pd;
205*14b24e2bSVaishali Kulkarni 	__le16 rq_num_pages;
206*14b24e2bSVaishali Kulkarni 	struct rdma_srq_id srq_id;
207*14b24e2bSVaishali Kulkarni 	struct regpair rq_pbl_addr;
208*14b24e2bSVaishali Kulkarni 	struct regpair irq_pbl_addr;
209*14b24e2bSVaishali Kulkarni 	__le16 local_mac_addr[3] /* BE order */;
210*14b24e2bSVaishali Kulkarni 	__le16 remote_mac_addr[3] /* BE order */;
211*14b24e2bSVaishali Kulkarni 	__le16 vlan_id;
212*14b24e2bSVaishali Kulkarni 	__le16 udp_src_port /* Only relevant in RRoCE */;
213*14b24e2bSVaishali Kulkarni 	__le32 src_gid[4] /* BE order. In case of RRoCE on IPv4 the lower register will hold the address. High registers must be zero! */;
214*14b24e2bSVaishali Kulkarni 	__le32 dst_gid[4] /* BE order. In case of RRoCE on IPv4 the lower register will hold the address. High registers must be zero! */;
215*14b24e2bSVaishali Kulkarni 	struct regpair qp_handle_for_cqe;
216*14b24e2bSVaishali Kulkarni 	struct regpair qp_handle_for_async;
217*14b24e2bSVaishali Kulkarni 	__le16 low_latency_phy_queue;
218*14b24e2bSVaishali Kulkarni 	u8 reserved2[6];
219*14b24e2bSVaishali Kulkarni 	__le32 cq_cid;
220*14b24e2bSVaishali Kulkarni 	__le16 regular_latency_phy_queue;
221*14b24e2bSVaishali Kulkarni 	__le16 dpi;
222*14b24e2bSVaishali Kulkarni };
223*14b24e2bSVaishali Kulkarni 
224*14b24e2bSVaishali Kulkarni 
225*14b24e2bSVaishali Kulkarni /*
226*14b24e2bSVaishali Kulkarni  * RoCE destroy qp requester output params
227*14b24e2bSVaishali Kulkarni  */
228*14b24e2bSVaishali Kulkarni struct roce_destroy_qp_req_output_params
229*14b24e2bSVaishali Kulkarni {
230*14b24e2bSVaishali Kulkarni 	__le32 num_bound_mw;
231*14b24e2bSVaishali Kulkarni 	__le32 cq_prod /* Completion producer value at destroy QP */;
232*14b24e2bSVaishali Kulkarni };
233*14b24e2bSVaishali Kulkarni 
234*14b24e2bSVaishali Kulkarni 
235*14b24e2bSVaishali Kulkarni /*
236*14b24e2bSVaishali Kulkarni  * RoCE destroy qp requester ramrod data
237*14b24e2bSVaishali Kulkarni  */
238*14b24e2bSVaishali Kulkarni struct roce_destroy_qp_req_ramrod_data
239*14b24e2bSVaishali Kulkarni {
240*14b24e2bSVaishali Kulkarni 	struct regpair output_params_addr;
241*14b24e2bSVaishali Kulkarni };
242*14b24e2bSVaishali Kulkarni 
243*14b24e2bSVaishali Kulkarni 
244*14b24e2bSVaishali Kulkarni /*
245*14b24e2bSVaishali Kulkarni  * RoCE destroy qp responder output params
246*14b24e2bSVaishali Kulkarni  */
247*14b24e2bSVaishali Kulkarni struct roce_destroy_qp_resp_output_params
248*14b24e2bSVaishali Kulkarni {
249*14b24e2bSVaishali Kulkarni 	__le32 num_invalidated_mw;
250*14b24e2bSVaishali Kulkarni 	__le32 cq_prod /* Completion producer value at destroy QP */;
251*14b24e2bSVaishali Kulkarni };
252*14b24e2bSVaishali Kulkarni 
253*14b24e2bSVaishali Kulkarni 
254*14b24e2bSVaishali Kulkarni /*
255*14b24e2bSVaishali Kulkarni  * RoCE destroy qp responder ramrod data
256*14b24e2bSVaishali Kulkarni  */
257*14b24e2bSVaishali Kulkarni struct roce_destroy_qp_resp_ramrod_data
258*14b24e2bSVaishali Kulkarni {
259*14b24e2bSVaishali Kulkarni 	struct regpair output_params_addr;
260*14b24e2bSVaishali Kulkarni };
261*14b24e2bSVaishali Kulkarni 
262*14b24e2bSVaishali Kulkarni 
263*14b24e2bSVaishali Kulkarni /*
264*14b24e2bSVaishali Kulkarni  * roce func init ramrod data
265*14b24e2bSVaishali Kulkarni  */
266*14b24e2bSVaishali Kulkarni struct roce_events_stats
267*14b24e2bSVaishali Kulkarni {
268*14b24e2bSVaishali Kulkarni 	__le16 silent_drops;
269*14b24e2bSVaishali Kulkarni 	__le16 rnr_naks_sent;
270*14b24e2bSVaishali Kulkarni 	__le32 retransmit_count;
271*14b24e2bSVaishali Kulkarni 	__le32 icrc_error_count;
272*14b24e2bSVaishali Kulkarni 	__le32 reserved;
273*14b24e2bSVaishali Kulkarni };
274*14b24e2bSVaishali Kulkarni 
275*14b24e2bSVaishali Kulkarni 
276*14b24e2bSVaishali Kulkarni /*
277*14b24e2bSVaishali Kulkarni  * ROCE slow path EQ cmd IDs
278*14b24e2bSVaishali Kulkarni  */
279*14b24e2bSVaishali Kulkarni enum roce_event_opcode
280*14b24e2bSVaishali Kulkarni {
281*14b24e2bSVaishali Kulkarni 	ROCE_EVENT_CREATE_QP=11,
282*14b24e2bSVaishali Kulkarni 	ROCE_EVENT_MODIFY_QP,
283*14b24e2bSVaishali Kulkarni 	ROCE_EVENT_QUERY_QP,
284*14b24e2bSVaishali Kulkarni 	ROCE_EVENT_DESTROY_QP,
285*14b24e2bSVaishali Kulkarni 	ROCE_EVENT_CREATE_UD_QP,
286*14b24e2bSVaishali Kulkarni 	ROCE_EVENT_DESTROY_UD_QP,
287*14b24e2bSVaishali Kulkarni 	MAX_ROCE_EVENT_OPCODE
288*14b24e2bSVaishali Kulkarni };
289*14b24e2bSVaishali Kulkarni 
290*14b24e2bSVaishali Kulkarni 
291*14b24e2bSVaishali Kulkarni /*
292*14b24e2bSVaishali Kulkarni  * roce func init ramrod data
293*14b24e2bSVaishali Kulkarni  */
294*14b24e2bSVaishali Kulkarni struct roce_init_func_params
295*14b24e2bSVaishali Kulkarni {
296*14b24e2bSVaishali Kulkarni 	u8 ll2_queue_id /* This ll2 queue ID is used for Unreliable Datagram QP */;
297*14b24e2bSVaishali Kulkarni 	u8 cnp_vlan_priority /* VLAN priority of DCQCN CNP packet */;
298*14b24e2bSVaishali Kulkarni 	u8 cnp_dscp /* The value of DSCP field in IP header for CNP packets */;
299*14b24e2bSVaishali Kulkarni 	u8 reserved;
300*14b24e2bSVaishali Kulkarni 	__le32 cnp_send_timeout /* The minimal difference of send time between CNP packets for specific QP. Units are in microseconds */;
301*14b24e2bSVaishali Kulkarni };
302*14b24e2bSVaishali Kulkarni 
303*14b24e2bSVaishali Kulkarni 
304*14b24e2bSVaishali Kulkarni /*
305*14b24e2bSVaishali Kulkarni  * roce func init ramrod data
306*14b24e2bSVaishali Kulkarni  */
307*14b24e2bSVaishali Kulkarni struct roce_init_func_ramrod_data
308*14b24e2bSVaishali Kulkarni {
309*14b24e2bSVaishali Kulkarni 	struct rdma_init_func_ramrod_data rdma;
310*14b24e2bSVaishali Kulkarni 	struct roce_init_func_params roce;
311*14b24e2bSVaishali Kulkarni };
312*14b24e2bSVaishali Kulkarni 
313*14b24e2bSVaishali Kulkarni 
314*14b24e2bSVaishali Kulkarni /*
315*14b24e2bSVaishali Kulkarni  * roce modify qp requester ramrod data
316*14b24e2bSVaishali Kulkarni  */
317*14b24e2bSVaishali Kulkarni struct roce_modify_qp_req_ramrod_data
318*14b24e2bSVaishali Kulkarni {
319*14b24e2bSVaishali Kulkarni 	__le16 flags;
320*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK      0x1
321*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT     0
322*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_MASK      0x1
323*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_SHIFT     1
324*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_MASK  0x1
325*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_SHIFT 2
326*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_MASK            0x1
327*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_SHIFT           3
328*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK   0x1
329*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT  4
330*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_MASK          0x1
331*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_SHIFT         5
332*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_MASK      0x1
333*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_SHIFT     6
334*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_MASK    0x1
335*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_SHIFT   7
336*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_MASK      0x1
337*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_SHIFT     8
338*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_MASK              0x1
339*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_SHIFT             9
340*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_MASK                  0x7
341*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_SHIFT                 10
342*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK            0x7
343*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_SHIFT           13
344*14b24e2bSVaishali Kulkarni 	u8 fields;
345*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK        0xF
346*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT       0
347*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK          0xF
348*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT         4
349*14b24e2bSVaishali Kulkarni 	u8 max_ord;
350*14b24e2bSVaishali Kulkarni 	u8 traffic_class;
351*14b24e2bSVaishali Kulkarni 	u8 hop_limit;
352*14b24e2bSVaishali Kulkarni 	__le16 p_key;
353*14b24e2bSVaishali Kulkarni 	__le32 flow_label;
354*14b24e2bSVaishali Kulkarni 	__le32 ack_timeout_val;
355*14b24e2bSVaishali Kulkarni 	__le16 mtu;
356*14b24e2bSVaishali Kulkarni 	__le16 reserved2;
357*14b24e2bSVaishali Kulkarni 	__le32 reserved3[3];
358*14b24e2bSVaishali Kulkarni 	__le32 src_gid[4] /* BE order. In case of IPv4 the higher register will hold the address. Low registers must be zero! */;
359*14b24e2bSVaishali Kulkarni 	__le32 dst_gid[4] /* BE order. In case of IPv4 the higher register will hold the address. Low registers must be zero! */;
360*14b24e2bSVaishali Kulkarni };
361*14b24e2bSVaishali Kulkarni 
362*14b24e2bSVaishali Kulkarni 
363*14b24e2bSVaishali Kulkarni /*
364*14b24e2bSVaishali Kulkarni  * roce modify qp responder ramrod data
365*14b24e2bSVaishali Kulkarni  */
366*14b24e2bSVaishali Kulkarni struct roce_modify_qp_resp_ramrod_data
367*14b24e2bSVaishali Kulkarni {
368*14b24e2bSVaishali Kulkarni 	__le16 flags;
369*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK        0x1
370*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT       0
371*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK             0x1
372*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT            1
373*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK             0x1
374*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT            2
375*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK              0x1
376*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT             3
377*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_MASK              0x1
378*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_SHIFT             4
379*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK     0x1
380*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT    5
381*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_MASK            0x1
382*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_SHIFT           6
383*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_MASK                0x1
384*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_SHIFT               7
385*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_MASK  0x1
386*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_SHIFT 8
387*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK        0x1
388*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT       9
389*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_MASK              0x3F
390*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_SHIFT             10
391*14b24e2bSVaishali Kulkarni 	u8 fields;
392*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_MASK                    0x7
393*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_SHIFT                   0
394*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK      0x1F
395*14b24e2bSVaishali Kulkarni #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT     3
396*14b24e2bSVaishali Kulkarni 	u8 max_ird;
397*14b24e2bSVaishali Kulkarni 	u8 traffic_class;
398*14b24e2bSVaishali Kulkarni 	u8 hop_limit;
399*14b24e2bSVaishali Kulkarni 	__le16 p_key;
400*14b24e2bSVaishali Kulkarni 	__le32 flow_label;
401*14b24e2bSVaishali Kulkarni 	__le16 mtu;
402*14b24e2bSVaishali Kulkarni 	__le16 reserved2;
403*14b24e2bSVaishali Kulkarni 	__le32 src_gid[4] /* BE order. In case of IPv4 the higher register will hold the address. Low registers must be zero! */;
404*14b24e2bSVaishali Kulkarni 	__le32 dst_gid[4] /* BE order. In case of IPv4 the higher register will hold the address. Low registers must be zero! */;
405*14b24e2bSVaishali Kulkarni };
406*14b24e2bSVaishali Kulkarni 
407*14b24e2bSVaishali Kulkarni 
408*14b24e2bSVaishali Kulkarni /*
409*14b24e2bSVaishali Kulkarni  * RoCE query qp requester output params
410*14b24e2bSVaishali Kulkarni  */
411*14b24e2bSVaishali Kulkarni struct roce_query_qp_req_output_params
412*14b24e2bSVaishali Kulkarni {
413*14b24e2bSVaishali Kulkarni 	__le32 psn /* send next psn */;
414*14b24e2bSVaishali Kulkarni 	__le32 flags;
415*14b24e2bSVaishali Kulkarni #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK          0x1
416*14b24e2bSVaishali Kulkarni #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_SHIFT         0
417*14b24e2bSVaishali Kulkarni #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_MASK  0x1
418*14b24e2bSVaishali Kulkarni #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_SHIFT 1
419*14b24e2bSVaishali Kulkarni #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_MASK        0x3FFFFFFF
420*14b24e2bSVaishali Kulkarni #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_SHIFT       2
421*14b24e2bSVaishali Kulkarni };
422*14b24e2bSVaishali Kulkarni 
423*14b24e2bSVaishali Kulkarni 
424*14b24e2bSVaishali Kulkarni /*
425*14b24e2bSVaishali Kulkarni  * RoCE query qp requester ramrod data
426*14b24e2bSVaishali Kulkarni  */
427*14b24e2bSVaishali Kulkarni struct roce_query_qp_req_ramrod_data
428*14b24e2bSVaishali Kulkarni {
429*14b24e2bSVaishali Kulkarni 	struct regpair output_params_addr;
430*14b24e2bSVaishali Kulkarni };
431*14b24e2bSVaishali Kulkarni 
432*14b24e2bSVaishali Kulkarni 
433*14b24e2bSVaishali Kulkarni /*
434*14b24e2bSVaishali Kulkarni  * RoCE query qp responder output params
435*14b24e2bSVaishali Kulkarni  */
436*14b24e2bSVaishali Kulkarni struct roce_query_qp_resp_output_params
437*14b24e2bSVaishali Kulkarni {
438*14b24e2bSVaishali Kulkarni 	__le32 psn /* send next psn */;
439*14b24e2bSVaishali Kulkarni 	__le32 err_flag;
440*14b24e2bSVaishali Kulkarni #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_MASK  0x1
441*14b24e2bSVaishali Kulkarni #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0
442*14b24e2bSVaishali Kulkarni #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_MASK  0x7FFFFFFF
443*14b24e2bSVaishali Kulkarni #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_SHIFT 1
444*14b24e2bSVaishali Kulkarni };
445*14b24e2bSVaishali Kulkarni 
446*14b24e2bSVaishali Kulkarni 
447*14b24e2bSVaishali Kulkarni /*
448*14b24e2bSVaishali Kulkarni  * RoCE query qp responder ramrod data
449*14b24e2bSVaishali Kulkarni  */
450*14b24e2bSVaishali Kulkarni struct roce_query_qp_resp_ramrod_data
451*14b24e2bSVaishali Kulkarni {
452*14b24e2bSVaishali Kulkarni 	struct regpair output_params_addr;
453*14b24e2bSVaishali Kulkarni };
454*14b24e2bSVaishali Kulkarni 
455*14b24e2bSVaishali Kulkarni 
456*14b24e2bSVaishali Kulkarni /*
457*14b24e2bSVaishali Kulkarni  * ROCE ramrod command IDs
458*14b24e2bSVaishali Kulkarni  */
459*14b24e2bSVaishali Kulkarni enum roce_ramrod_cmd_id
460*14b24e2bSVaishali Kulkarni {
461*14b24e2bSVaishali Kulkarni 	ROCE_RAMROD_CREATE_QP=11,
462*14b24e2bSVaishali Kulkarni 	ROCE_RAMROD_MODIFY_QP,
463*14b24e2bSVaishali Kulkarni 	ROCE_RAMROD_QUERY_QP,
464*14b24e2bSVaishali Kulkarni 	ROCE_RAMROD_DESTROY_QP,
465*14b24e2bSVaishali Kulkarni 	ROCE_RAMROD_CREATE_UD_QP,
466*14b24e2bSVaishali Kulkarni 	ROCE_RAMROD_DESTROY_UD_QP,
467*14b24e2bSVaishali Kulkarni 	MAX_ROCE_RAMROD_CMD_ID
468*14b24e2bSVaishali Kulkarni };
469*14b24e2bSVaishali Kulkarni 
470*14b24e2bSVaishali Kulkarni 
471*14b24e2bSVaishali Kulkarni 
472*14b24e2bSVaishali Kulkarni 
473*14b24e2bSVaishali Kulkarni 
474*14b24e2bSVaishali Kulkarni 
475*14b24e2bSVaishali Kulkarni struct e4_mstorm_roce_req_conn_ag_ctx
476*14b24e2bSVaishali Kulkarni {
477*14b24e2bSVaishali Kulkarni 	u8 byte0 /* cdu_validation */;
478*14b24e2bSVaishali Kulkarni 	u8 byte1 /* state */;
479*14b24e2bSVaishali Kulkarni 	u8 flags0;
480*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK     0x1 /* exist_in_qm0 */
481*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT    0
482*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK     0x1 /* exist_in_qm1 */
483*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT    1
484*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK      0x3 /* cf0 */
485*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT     2
486*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK      0x3 /* cf1 */
487*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT     4
488*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK      0x3 /* cf2 */
489*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT     6
490*14b24e2bSVaishali Kulkarni 	u8 flags1;
491*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK    0x1 /* cf0en */
492*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT   0
493*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK    0x1 /* cf1en */
494*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT   1
495*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK    0x1 /* cf2en */
496*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT   2
497*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK  0x1 /* rule0en */
498*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3
499*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK  0x1 /* rule1en */
500*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4
501*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK  0x1 /* rule2en */
502*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5
503*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK  0x1 /* rule3en */
504*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6
505*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK  0x1 /* rule4en */
506*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7
507*14b24e2bSVaishali Kulkarni 	__le16 word0 /* word0 */;
508*14b24e2bSVaishali Kulkarni 	__le16 word1 /* word1 */;
509*14b24e2bSVaishali Kulkarni 	__le32 reg0 /* reg0 */;
510*14b24e2bSVaishali Kulkarni 	__le32 reg1 /* reg1 */;
511*14b24e2bSVaishali Kulkarni };
512*14b24e2bSVaishali Kulkarni 
513*14b24e2bSVaishali Kulkarni 
514*14b24e2bSVaishali Kulkarni struct e4_mstorm_roce_resp_conn_ag_ctx
515*14b24e2bSVaishali Kulkarni {
516*14b24e2bSVaishali Kulkarni 	u8 byte0 /* cdu_validation */;
517*14b24e2bSVaishali Kulkarni 	u8 byte1 /* state */;
518*14b24e2bSVaishali Kulkarni 	u8 flags0;
519*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK     0x1 /* exist_in_qm0 */
520*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT    0
521*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK     0x1 /* exist_in_qm1 */
522*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT    1
523*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK      0x3 /* cf0 */
524*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT     2
525*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK      0x3 /* cf1 */
526*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT     4
527*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK      0x3 /* cf2 */
528*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT     6
529*14b24e2bSVaishali Kulkarni 	u8 flags1;
530*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK    0x1 /* cf0en */
531*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT   0
532*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK    0x1 /* cf1en */
533*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT   1
534*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK    0x1 /* cf2en */
535*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT   2
536*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK  0x1 /* rule0en */
537*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3
538*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK  0x1 /* rule1en */
539*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4
540*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK  0x1 /* rule2en */
541*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5
542*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK  0x1 /* rule3en */
543*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6
544*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK  0x1 /* rule4en */
545*14b24e2bSVaishali Kulkarni #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7
546*14b24e2bSVaishali Kulkarni 	__le16 word0 /* word0 */;
547*14b24e2bSVaishali Kulkarni 	__le16 word1 /* word1 */;
548*14b24e2bSVaishali Kulkarni 	__le32 reg0 /* reg0 */;
549*14b24e2bSVaishali Kulkarni 	__le32 reg1 /* reg1 */;
550*14b24e2bSVaishali Kulkarni };
551*14b24e2bSVaishali Kulkarni 
552*14b24e2bSVaishali Kulkarni 
553*14b24e2bSVaishali Kulkarni struct e4_tstorm_roce_req_conn_ag_ctx
554*14b24e2bSVaishali Kulkarni {
555*14b24e2bSVaishali Kulkarni 	u8 reserved0 /* cdu_validation */;
556*14b24e2bSVaishali Kulkarni 	u8 state /* state */;
557*14b24e2bSVaishali Kulkarni 	u8 flags0;
558*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK                0x1 /* exist_in_qm0 */
559*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT               0
560*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_MASK            0x1 /* exist_in_qm1 */
561*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_SHIFT           1
562*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_MASK        0x1 /* bit2 */
563*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_SHIFT       2
564*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK                        0x1 /* bit3 */
565*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_SHIFT                       3
566*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK                0x1 /* bit4 */
567*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_SHIFT               4
568*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK                  0x1 /* bit5 */
569*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_SHIFT                 5
570*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK                    0x3 /* timer0cf */
571*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_SHIFT                   6
572*14b24e2bSVaishali Kulkarni 	u8 flags1;
573*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK                         0x3 /* timer1cf */
574*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT                        0
575*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK                 0x3 /* timer2cf */
576*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_SHIFT                2
577*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK           0x3 /* timer_stop_all */
578*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT          4
579*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK                 0x3 /* cf4 */
580*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT                6
581*14b24e2bSVaishali Kulkarni 	u8 flags2;
582*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK             0x3 /* cf5 */
583*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT            0
584*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK                0x3 /* cf6 */
585*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_SHIFT               2
586*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK           0x3 /* cf7 */
587*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_SHIFT          4
588*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK               0x3 /* cf8 */
589*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_SHIFT              6
590*14b24e2bSVaishali Kulkarni 	u8 flags3;
591*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK     0x3 /* cf9 */
592*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT    0
593*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK       0x3 /* cf10 */
594*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_SHIFT      2
595*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK                 0x1 /* cf0en */
596*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_SHIFT                4
597*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK                       0x1 /* cf1en */
598*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT                      5
599*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK              0x1 /* cf2en */
600*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_SHIFT             6
601*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK        0x1 /* cf3en */
602*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT       7
603*14b24e2bSVaishali Kulkarni 	u8 flags4;
604*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK              0x1 /* cf4en */
605*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT             0
606*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK          0x1 /* cf5en */
607*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT         1
608*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK             0x1 /* cf6en */
609*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_SHIFT            2
610*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK        0x1 /* cf7en */
611*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_SHIFT       3
612*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK            0x1 /* cf8en */
613*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_SHIFT           4
614*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK  0x1 /* cf9en */
615*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_SHIFT 5
616*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK    0x1 /* cf10en */
617*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_SHIFT   6
618*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK                     0x1 /* rule0en */
619*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT                    7
620*14b24e2bSVaishali Kulkarni 	u8 flags5;
621*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK                     0x1 /* rule1en */
622*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT                    0
623*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK                     0x1 /* rule2en */
624*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT                    1
625*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK                     0x1 /* rule3en */
626*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT                    2
627*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK                     0x1 /* rule4en */
628*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT                    3
629*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK                     0x1 /* rule5en */
630*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT                    4
631*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK              0x1 /* rule6en */
632*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_SHIFT             5
633*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK                     0x1 /* rule7en */
634*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT                    6
635*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK                     0x1 /* rule8en */
636*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT                    7
637*14b24e2bSVaishali Kulkarni 	__le32 reg0 /* reg0 */;
638*14b24e2bSVaishali Kulkarni 	__le32 snd_nxt_psn /* reg1 */;
639*14b24e2bSVaishali Kulkarni 	__le32 snd_max_psn /* reg2 */;
640*14b24e2bSVaishali Kulkarni 	__le32 orq_prod /* reg3 */;
641*14b24e2bSVaishali Kulkarni 	__le32 reg4 /* reg4 */;
642*14b24e2bSVaishali Kulkarni 	__le32 reg5 /* reg5 */;
643*14b24e2bSVaishali Kulkarni 	__le32 reg6 /* reg6 */;
644*14b24e2bSVaishali Kulkarni 	__le32 reg7 /* reg7 */;
645*14b24e2bSVaishali Kulkarni 	__le32 reg8 /* reg8 */;
646*14b24e2bSVaishali Kulkarni 	u8 tx_cqe_error_type /* byte2 */;
647*14b24e2bSVaishali Kulkarni 	u8 orq_cache_idx /* byte3 */;
648*14b24e2bSVaishali Kulkarni 	__le16 snd_sq_cons_th /* word0 */;
649*14b24e2bSVaishali Kulkarni 	u8 byte4 /* byte4 */;
650*14b24e2bSVaishali Kulkarni 	u8 byte5 /* byte5 */;
651*14b24e2bSVaishali Kulkarni 	__le16 snd_sq_cons /* word1 */;
652*14b24e2bSVaishali Kulkarni 	__le16 word2 /* conn_dpi */;
653*14b24e2bSVaishali Kulkarni 	__le16 word3 /* word3 */;
654*14b24e2bSVaishali Kulkarni 	__le32 reg9 /* reg9 */;
655*14b24e2bSVaishali Kulkarni 	__le32 reg10 /* reg10 */;
656*14b24e2bSVaishali Kulkarni };
657*14b24e2bSVaishali Kulkarni 
658*14b24e2bSVaishali Kulkarni 
659*14b24e2bSVaishali Kulkarni struct e4_tstorm_roce_resp_conn_ag_ctx
660*14b24e2bSVaishali Kulkarni {
661*14b24e2bSVaishali Kulkarni 	u8 byte0 /* cdu_validation */;
662*14b24e2bSVaishali Kulkarni 	u8 state /* state */;
663*14b24e2bSVaishali Kulkarni 	u8 flags0;
664*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK               0x1 /* exist_in_qm0 */
665*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT              0
666*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_MASK  0x1 /* exist_in_qm1 */
667*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_SHIFT 1
668*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK                       0x1 /* bit2 */
669*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_SHIFT                      2
670*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK                       0x1 /* bit3 */
671*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_SHIFT                      3
672*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK               0x1 /* bit4 */
673*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT              4
674*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK                       0x1 /* bit5 */
675*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_SHIFT                      5
676*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK                        0x3 /* timer0cf */
677*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT                       6
678*14b24e2bSVaishali Kulkarni 	u8 flags1;
679*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK                0x3 /* timer1cf */
680*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT               0
681*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK                0x3 /* timer2cf */
682*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_SHIFT               2
683*14b24e2bSVaishali Kulkarni #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK                        0x3 /* timer_stop_all */
684