1*14b24e2bSVaishali Kulkarni /*
2*14b24e2bSVaishali Kulkarni * CDDL HEADER START
3*14b24e2bSVaishali Kulkarni *
4*14b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the
5*14b24e2bSVaishali Kulkarni * Common Development and Distribution License, v.1,  (the "License").
6*14b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License.
7*14b24e2bSVaishali Kulkarni *
8*14b24e2bSVaishali Kulkarni * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9*14b24e2bSVaishali Kulkarni * or http://opensource.org/licenses/CDDL-1.0.
10*14b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions
11*14b24e2bSVaishali Kulkarni * and limitations under the License.
12*14b24e2bSVaishali Kulkarni *
13*14b24e2bSVaishali Kulkarni * When distributing Covered Code, include this CDDL HEADER in each
14*14b24e2bSVaishali Kulkarni * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15*14b24e2bSVaishali Kulkarni * If applicable, add the following below this CDDL HEADER, with the
16*14b24e2bSVaishali Kulkarni * fields enclosed by brackets "[]" replaced with your own identifying
17*14b24e2bSVaishali Kulkarni * information: Portions Copyright [yyyy] [name of copyright owner]
18*14b24e2bSVaishali Kulkarni *
19*14b24e2bSVaishali Kulkarni * CDDL HEADER END
20*14b24e2bSVaishali Kulkarni */
21*14b24e2bSVaishali Kulkarni 
22*14b24e2bSVaishali Kulkarni /*
23*14b24e2bSVaishali Kulkarni * Copyright 2014-2017 Cavium, Inc.
24*14b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the Common Development
25*14b24e2bSVaishali Kulkarni * and Distribution License, v.1,  (the "License").
26*14b24e2bSVaishali Kulkarni 
27*14b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License.
28*14b24e2bSVaishali Kulkarni 
29*14b24e2bSVaishali Kulkarni * You can obtain a copy of the License at available
30*14b24e2bSVaishali Kulkarni * at http://opensource.org/licenses/CDDL-1.0
31*14b24e2bSVaishali Kulkarni 
32*14b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions and
33*14b24e2bSVaishali Kulkarni * limitations under the License.
34*14b24e2bSVaishali Kulkarni */
35*14b24e2bSVaishali Kulkarni 
36*14b24e2bSVaishali Kulkarni #ifndef __ECORE_HSI_RDMA__
37*14b24e2bSVaishali Kulkarni #define __ECORE_HSI_RDMA__
38*14b24e2bSVaishali Kulkarni /************************************************************************/
39*14b24e2bSVaishali Kulkarni /* Add include to common rdma target for both eCore and protocol rdma driver */
40*14b24e2bSVaishali Kulkarni /************************************************************************/
41*14b24e2bSVaishali Kulkarni #include "rdma_common.h"
42*14b24e2bSVaishali Kulkarni 
43*14b24e2bSVaishali Kulkarni /*
44*14b24e2bSVaishali Kulkarni  * The roce task context of Mstorm
45*14b24e2bSVaishali Kulkarni  */
46*14b24e2bSVaishali Kulkarni struct mstorm_rdma_task_st_ctx
47*14b24e2bSVaishali Kulkarni {
48*14b24e2bSVaishali Kulkarni 	struct regpair temp[4];
49*14b24e2bSVaishali Kulkarni };
50*14b24e2bSVaishali Kulkarni 
51*14b24e2bSVaishali Kulkarni 
52*14b24e2bSVaishali Kulkarni /*
53*14b24e2bSVaishali Kulkarni  * rdma function init ramrod data
54*14b24e2bSVaishali Kulkarni  */
55*14b24e2bSVaishali Kulkarni struct rdma_close_func_ramrod_data
56*14b24e2bSVaishali Kulkarni {
57*14b24e2bSVaishali Kulkarni 	u8 cnq_start_offset;
58*14b24e2bSVaishali Kulkarni 	u8 num_cnqs;
59*14b24e2bSVaishali Kulkarni 	u8 vf_id /* This field should be assigned to Virtual Function ID if vf_valid == 1. Otherwise its dont care */;
60*14b24e2bSVaishali Kulkarni 	u8 vf_valid;
61*14b24e2bSVaishali Kulkarni 	u8 reserved[4];
62*14b24e2bSVaishali Kulkarni };
63*14b24e2bSVaishali Kulkarni 
64*14b24e2bSVaishali Kulkarni 
65*14b24e2bSVaishali Kulkarni /*
66*14b24e2bSVaishali Kulkarni  * rdma function init CNQ parameters
67*14b24e2bSVaishali Kulkarni  */
68*14b24e2bSVaishali Kulkarni struct rdma_cnq_params
69*14b24e2bSVaishali Kulkarni {
70*14b24e2bSVaishali Kulkarni 	__le16 sb_num /* Status block number used by the queue */;
71*14b24e2bSVaishali Kulkarni 	u8 sb_index /* Status block index used by the queue */;
72*14b24e2bSVaishali Kulkarni 	u8 num_pbl_pages /* Number of pages in the PBL allocated for this queue */;
73*14b24e2bSVaishali Kulkarni 	__le32 reserved;
74*14b24e2bSVaishali Kulkarni 	struct regpair pbl_base_addr /* Address to the first entry of the queue PBL */;
75*14b24e2bSVaishali Kulkarni 	__le16 queue_zone_num /* Queue Zone ID used for CNQ consumer update */;
76*14b24e2bSVaishali Kulkarni 	u8 reserved1[6];
77*14b24e2bSVaishali Kulkarni };
78*14b24e2bSVaishali Kulkarni 
79*14b24e2bSVaishali Kulkarni 
80*14b24e2bSVaishali Kulkarni /*
81*14b24e2bSVaishali Kulkarni  * rdma create cq ramrod data
82*14b24e2bSVaishali Kulkarni  */
83*14b24e2bSVaishali Kulkarni struct rdma_create_cq_ramrod_data
84*14b24e2bSVaishali Kulkarni {
85*14b24e2bSVaishali Kulkarni 	struct regpair cq_handle;
86*14b24e2bSVaishali Kulkarni 	struct regpair pbl_addr;
87*14b24e2bSVaishali Kulkarni 	__le32 max_cqes;
88*14b24e2bSVaishali Kulkarni 	__le16 pbl_num_pages;
89*14b24e2bSVaishali Kulkarni 	__le16 dpi;
90*14b24e2bSVaishali Kulkarni 	u8 is_two_level_pbl;
91*14b24e2bSVaishali Kulkarni 	u8 cnq_id;
92*14b24e2bSVaishali Kulkarni 	u8 pbl_log_page_size;
93*14b24e2bSVaishali Kulkarni 	u8 toggle_bit;
94*14b24e2bSVaishali Kulkarni 	__le16 int_timeout /* Timeout used for interrupt moderation */;
95*14b24e2bSVaishali Kulkarni 	__le16 reserved1;
96*14b24e2bSVaishali Kulkarni };
97*14b24e2bSVaishali Kulkarni 
98*14b24e2bSVaishali Kulkarni 
99*14b24e2bSVaishali Kulkarni /*
100*14b24e2bSVaishali Kulkarni  * rdma deregister tid ramrod data
101*14b24e2bSVaishali Kulkarni  */
102*14b24e2bSVaishali Kulkarni struct rdma_deregister_tid_ramrod_data
103*14b24e2bSVaishali Kulkarni {
104*14b24e2bSVaishali Kulkarni 	__le32 itid;
105*14b24e2bSVaishali Kulkarni 	__le32 reserved;
106*14b24e2bSVaishali Kulkarni };
107*14b24e2bSVaishali Kulkarni 
108*14b24e2bSVaishali Kulkarni 
109*14b24e2bSVaishali Kulkarni /*
110*14b24e2bSVaishali Kulkarni  * rdma destroy cq output params
111*14b24e2bSVaishali Kulkarni  */
112*14b24e2bSVaishali Kulkarni struct rdma_destroy_cq_output_params
113*14b24e2bSVaishali Kulkarni {
114*14b24e2bSVaishali Kulkarni 	__le16 cnq_num /* Sequence number of completion notification sent for the cq on the associated CNQ */;
115*14b24e2bSVaishali Kulkarni 	__le16 reserved0;
116*14b24e2bSVaishali Kulkarni 	__le32 reserved1;
117*14b24e2bSVaishali Kulkarni };
118*14b24e2bSVaishali Kulkarni 
119*14b24e2bSVaishali Kulkarni 
120*14b24e2bSVaishali Kulkarni /*
121*14b24e2bSVaishali Kulkarni  * rdma destroy cq ramrod data
122*14b24e2bSVaishali Kulkarni  */
123*14b24e2bSVaishali Kulkarni struct rdma_destroy_cq_ramrod_data
124*14b24e2bSVaishali Kulkarni {
125*14b24e2bSVaishali Kulkarni 	struct regpair output_params_addr;
126*14b24e2bSVaishali Kulkarni };
127*14b24e2bSVaishali Kulkarni 
128*14b24e2bSVaishali Kulkarni 
129*14b24e2bSVaishali Kulkarni /*
130*14b24e2bSVaishali Kulkarni  * RDMA slow path EQ cmd IDs
131*14b24e2bSVaishali Kulkarni  */
132*14b24e2bSVaishali Kulkarni enum rdma_event_opcode
133*14b24e2bSVaishali Kulkarni {
134*14b24e2bSVaishali Kulkarni 	RDMA_EVENT_UNUSED,
135*14b24e2bSVaishali Kulkarni 	RDMA_EVENT_FUNC_INIT,
136*14b24e2bSVaishali Kulkarni 	RDMA_EVENT_FUNC_CLOSE,
137*14b24e2bSVaishali Kulkarni 	RDMA_EVENT_REGISTER_MR,
138*14b24e2bSVaishali Kulkarni 	RDMA_EVENT_DEREGISTER_MR,
139*14b24e2bSVaishali Kulkarni 	RDMA_EVENT_CREATE_CQ,
140*14b24e2bSVaishali Kulkarni 	RDMA_EVENT_RESIZE_CQ,
141*14b24e2bSVaishali Kulkarni 	RDMA_EVENT_DESTROY_CQ,
142*14b24e2bSVaishali Kulkarni 	RDMA_EVENT_CREATE_SRQ,
143*14b24e2bSVaishali Kulkarni 	RDMA_EVENT_MODIFY_SRQ,
144*14b24e2bSVaishali Kulkarni 	RDMA_EVENT_DESTROY_SRQ,
145*14b24e2bSVaishali Kulkarni 	MAX_RDMA_EVENT_OPCODE
146*14b24e2bSVaishali Kulkarni };
147*14b24e2bSVaishali Kulkarni 
148*14b24e2bSVaishali Kulkarni 
149*14b24e2bSVaishali Kulkarni /*
150*14b24e2bSVaishali Kulkarni  * RDMA FW return code for slow path ramrods
151*14b24e2bSVaishali Kulkarni  */
152*14b24e2bSVaishali Kulkarni enum rdma_fw_return_code
153*14b24e2bSVaishali Kulkarni {
154*14b24e2bSVaishali Kulkarni 	RDMA_RETURN_OK=0,
155*14b24e2bSVaishali Kulkarni 	RDMA_RETURN_REGISTER_MR_BAD_STATE_ERR,
156*14b24e2bSVaishali Kulkarni 	RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR,
157*14b24e2bSVaishali Kulkarni 	RDMA_RETURN_RESIZE_CQ_ERR,
158*14b24e2bSVaishali Kulkarni 	RDMA_RETURN_NIG_DRAIN_REQ,
159*14b24e2bSVaishali Kulkarni 	MAX_RDMA_FW_RETURN_CODE
160*14b24e2bSVaishali Kulkarni };
161*14b24e2bSVaishali Kulkarni 
162*14b24e2bSVaishali Kulkarni 
163*14b24e2bSVaishali Kulkarni /*
164*14b24e2bSVaishali Kulkarni  * rdma function init header
165*14b24e2bSVaishali Kulkarni  */
166*14b24e2bSVaishali Kulkarni struct rdma_init_func_hdr
167*14b24e2bSVaishali Kulkarni {
168*14b24e2bSVaishali Kulkarni 	u8 cnq_start_offset /* First RDMA CNQ */;
169*14b24e2bSVaishali Kulkarni 	u8 num_cnqs /* Number of CNQs */;
170*14b24e2bSVaishali Kulkarni 	u8 cq_ring_mode /* 0 for 32 bit cq producer and consumer counters and 1 for 16 bit */;
171*14b24e2bSVaishali Kulkarni 	u8 vf_id /* This field should be assigned to Virtual Function ID if vf_valid == 1. Otherwise its dont care */;
172*14b24e2bSVaishali Kulkarni 	u8 vf_valid;
173*14b24e2bSVaishali Kulkarni 	u8 reserved[3];
174*14b24e2bSVaishali Kulkarni };
175*14b24e2bSVaishali Kulkarni 
176*14b24e2bSVaishali Kulkarni 
177*14b24e2bSVaishali Kulkarni /*
178*14b24e2bSVaishali Kulkarni  * rdma function init ramrod data
179*14b24e2bSVaishali Kulkarni  */
180*14b24e2bSVaishali Kulkarni struct rdma_init_func_ramrod_data
181*14b24e2bSVaishali Kulkarni {
182*14b24e2bSVaishali Kulkarni 	struct rdma_init_func_hdr params_header;
183*14b24e2bSVaishali Kulkarni 	struct rdma_cnq_params cnq_params[NUM_OF_GLOBAL_QUEUES];
184*14b24e2bSVaishali Kulkarni };
185*14b24e2bSVaishali Kulkarni 
186*14b24e2bSVaishali Kulkarni 
187*14b24e2bSVaishali Kulkarni /*
188*14b24e2bSVaishali Kulkarni  * RDMA ramrod command IDs
189*14b24e2bSVaishali Kulkarni  */
190*14b24e2bSVaishali Kulkarni enum rdma_ramrod_cmd_id
191*14b24e2bSVaishali Kulkarni {
192*14b24e2bSVaishali Kulkarni 	RDMA_RAMROD_UNUSED,
193*14b24e2bSVaishali Kulkarni 	RDMA_RAMROD_FUNC_INIT,
194*14b24e2bSVaishali Kulkarni 	RDMA_RAMROD_FUNC_CLOSE,
195*14b24e2bSVaishali Kulkarni 	RDMA_RAMROD_REGISTER_MR,
196*14b24e2bSVaishali Kulkarni 	RDMA_RAMROD_DEREGISTER_MR,
197*14b24e2bSVaishali Kulkarni 	RDMA_RAMROD_CREATE_CQ,
198*14b24e2bSVaishali Kulkarni 	RDMA_RAMROD_RESIZE_CQ,
199*14b24e2bSVaishali Kulkarni 	RDMA_RAMROD_DESTROY_CQ,
200*14b24e2bSVaishali Kulkarni 	RDMA_RAMROD_CREATE_SRQ,
201*14b24e2bSVaishali Kulkarni 	RDMA_RAMROD_MODIFY_SRQ,
202*14b24e2bSVaishali Kulkarni 	RDMA_RAMROD_DESTROY_SRQ,
203*14b24e2bSVaishali Kulkarni 	MAX_RDMA_RAMROD_CMD_ID
204*14b24e2bSVaishali Kulkarni };
205*14b24e2bSVaishali Kulkarni 
206*14b24e2bSVaishali Kulkarni 
207*14b24e2bSVaishali Kulkarni /*
208*14b24e2bSVaishali Kulkarni  * rdma register tid ramrod data
209*14b24e2bSVaishali Kulkarni  */
210*14b24e2bSVaishali Kulkarni struct rdma_register_tid_ramrod_data
211*14b24e2bSVaishali Kulkarni {
212*14b24e2bSVaishali Kulkarni 	__le32 flags;
213*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_MAX_ID_MASK             0x3FFFF
214*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_MAX_ID_SHIFT            0
215*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_MASK      0x1F
216*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_SHIFT     18
217*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_MASK      0x1
218*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_SHIFT     23
219*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_MASK         0x1
220*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_SHIFT        24
221*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_MASK             0x1
222*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_SHIFT            25
223*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_MASK        0x1
224*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_SHIFT       26
225*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_MASK       0x1
226*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_SHIFT      27
227*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_MASK      0x1
228*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_SHIFT     28
229*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_MASK        0x1
230*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_SHIFT       29
231*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_MASK         0x1
232*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_SHIFT        30
233*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_MASK     0x1
234*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_SHIFT    31
235*14b24e2bSVaishali Kulkarni 	u8 flags1;
236*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_MASK  0x1F
237*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_SHIFT 0
238*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_MASK           0x7
239*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_SHIFT          5
240*14b24e2bSVaishali Kulkarni 	u8 flags2;
241*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_MASK             0x1 /* Bit indicating that this MR is DMA_MR meaning SGEs that use it have the physical address on them */
242*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_SHIFT            0
243*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_MASK    0x1 /* Bit indicating that this MR has DIF protection enabled. */
244*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_SHIFT   1
245*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_MASK          0x3F
246*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_SHIFT         2
247*14b24e2bSVaishali Kulkarni 	u8 key;
248*14b24e2bSVaishali Kulkarni 	u8 length_hi;
249*14b24e2bSVaishali Kulkarni 	u8 vf_id /* This field should be assigned to Virtual Function ID if vf_valid == 1. Otherwise its dont care */;
250*14b24e2bSVaishali Kulkarni 	u8 vf_valid;
251*14b24e2bSVaishali Kulkarni 	__le16 pd;
252*14b24e2bSVaishali Kulkarni 	__le32 length_lo /* lower 32 bits of the registered MR length. */;
253*14b24e2bSVaishali Kulkarni 	__le32 itid;
254*14b24e2bSVaishali Kulkarni 	__le32 reserved2;
255*14b24e2bSVaishali Kulkarni 	struct regpair va;
256*14b24e2bSVaishali Kulkarni 	struct regpair pbl_base;
257*14b24e2bSVaishali Kulkarni 	struct regpair dif_error_addr /* DIF TX IO writes error information to this location when memory region is invalidated. */;
258*14b24e2bSVaishali Kulkarni 	struct regpair dif_runt_addr /* DIF RX IO writes runt value to this location when last RDMA Read of the IO has completed. */;
259*14b24e2bSVaishali Kulkarni 	__le32 reserved3[2];
260*14b24e2bSVaishali Kulkarni };
261*14b24e2bSVaishali Kulkarni 
262*14b24e2bSVaishali Kulkarni 
263*14b24e2bSVaishali Kulkarni /*
264*14b24e2bSVaishali Kulkarni  * rdma resize cq output params
265*14b24e2bSVaishali Kulkarni  */
266*14b24e2bSVaishali Kulkarni struct rdma_resize_cq_output_params
267*14b24e2bSVaishali Kulkarni {
268*14b24e2bSVaishali Kulkarni 	__le32 old_cq_cons /* cq consumer value on old PBL */;
269*14b24e2bSVaishali Kulkarni 	__le32 old_cq_prod /* cq producer value on old PBL */;
270*14b24e2bSVaishali Kulkarni };
271*14b24e2bSVaishali Kulkarni 
272*14b24e2bSVaishali Kulkarni 
273*14b24e2bSVaishali Kulkarni /*
274*14b24e2bSVaishali Kulkarni  * rdma resize cq ramrod data
275*14b24e2bSVaishali Kulkarni  */
276*14b24e2bSVaishali Kulkarni struct rdma_resize_cq_ramrod_data
277*14b24e2bSVaishali Kulkarni {
278*14b24e2bSVaishali Kulkarni 	u8 flags;
279*14b24e2bSVaishali Kulkarni #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_MASK        0x1
280*14b24e2bSVaishali Kulkarni #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_SHIFT       0
281*14b24e2bSVaishali Kulkarni #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_MASK  0x1
282*14b24e2bSVaishali Kulkarni #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_SHIFT 1
283*14b24e2bSVaishali Kulkarni #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK          0x3F
284*14b24e2bSVaishali Kulkarni #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_SHIFT         2
285*14b24e2bSVaishali Kulkarni 	u8 pbl_log_page_size;
286*14b24e2bSVaishali Kulkarni 	__le16 pbl_num_pages;
287*14b24e2bSVaishali Kulkarni 	__le32 max_cqes;
288*14b24e2bSVaishali Kulkarni 	struct regpair pbl_addr;
289*14b24e2bSVaishali Kulkarni 	struct regpair output_params_addr;
290*14b24e2bSVaishali Kulkarni };
291*14b24e2bSVaishali Kulkarni 
292*14b24e2bSVaishali Kulkarni 
293*14b24e2bSVaishali Kulkarni /*
294*14b24e2bSVaishali Kulkarni  * The rdma storm context of Mstorm
295*14b24e2bSVaishali Kulkarni  */
296*14b24e2bSVaishali Kulkarni struct rdma_srq_context
297*14b24e2bSVaishali Kulkarni {
298*14b24e2bSVaishali Kulkarni 	struct regpair temp[8];
299*14b24e2bSVaishali Kulkarni };
300*14b24e2bSVaishali Kulkarni 
301*14b24e2bSVaishali Kulkarni 
302*14b24e2bSVaishali Kulkarni /*
303*14b24e2bSVaishali Kulkarni  * rdma create qp requester ramrod data
304*14b24e2bSVaishali Kulkarni  */
305*14b24e2bSVaishali Kulkarni struct rdma_srq_create_ramrod_data
306*14b24e2bSVaishali Kulkarni {
307*14b24e2bSVaishali Kulkarni 	struct regpair pbl_base_addr /* SRQ PBL base address */;
308*14b24e2bSVaishali Kulkarni 	__le16 pages_in_srq_pbl /* Number of pages in PBL */;
309*14b24e2bSVaishali Kulkarni 	__le16 pd_id;
310*14b24e2bSVaishali Kulkarni 	struct rdma_srq_id srq_id /* SRQ Index */;
311*14b24e2bSVaishali Kulkarni 	__le16 page_size /* Page size in SGEs(16 bytes) elements. Supports up to 2M bytes page size */;
312*14b24e2bSVaishali Kulkarni 	__le16 reserved1;
313*14b24e2bSVaishali Kulkarni 	__le32 reserved2;
314*14b24e2bSVaishali Kulkarni 	struct regpair producers_addr /* SRQ PBL base address */;
315*14b24e2bSVaishali Kulkarni };
316*14b24e2bSVaishali Kulkarni 
317*14b24e2bSVaishali Kulkarni 
318*14b24e2bSVaishali Kulkarni /*
319*14b24e2bSVaishali Kulkarni  * rdma create qp requester ramrod data
320*14b24e2bSVaishali Kulkarni  */
321*14b24e2bSVaishali Kulkarni struct rdma_srq_destroy_ramrod_data
322*14b24e2bSVaishali Kulkarni {
323*14b24e2bSVaishali Kulkarni 	struct rdma_srq_id srq_id /* SRQ Index */;
324*14b24e2bSVaishali Kulkarni 	__le32 reserved;
325*14b24e2bSVaishali Kulkarni };
326*14b24e2bSVaishali Kulkarni 
327*14b24e2bSVaishali Kulkarni 
328*14b24e2bSVaishali Kulkarni /*
329*14b24e2bSVaishali Kulkarni  * rdma create qp requester ramrod data
330*14b24e2bSVaishali Kulkarni  */
331*14b24e2bSVaishali Kulkarni struct rdma_srq_modify_ramrod_data
332*14b24e2bSVaishali Kulkarni {
333*14b24e2bSVaishali Kulkarni 	struct rdma_srq_id srq_id /* SRQ Index */;
334*14b24e2bSVaishali Kulkarni 	__le32 wqe_limit;
335*14b24e2bSVaishali Kulkarni };
336*14b24e2bSVaishali Kulkarni 
337*14b24e2bSVaishali Kulkarni 
338*14b24e2bSVaishali Kulkarni /*
339*14b24e2bSVaishali Kulkarni  * The rdma task context of Mstorm
340*14b24e2bSVaishali Kulkarni  */
341*14b24e2bSVaishali Kulkarni struct ystorm_rdma_task_st_ctx
342*14b24e2bSVaishali Kulkarni {
343*14b24e2bSVaishali Kulkarni 	struct regpair temp[4];
344*14b24e2bSVaishali Kulkarni };
345*14b24e2bSVaishali Kulkarni 
346*14b24e2bSVaishali Kulkarni struct e4_ystorm_rdma_task_ag_ctx
347*14b24e2bSVaishali Kulkarni {
348*14b24e2bSVaishali Kulkarni 	u8 reserved /* cdu_validation */;
349*14b24e2bSVaishali Kulkarni 	u8 byte1 /* state */;
350*14b24e2bSVaishali Kulkarni 	__le16 msem_ctx_upd_seq /* icid */;
351*14b24e2bSVaishali Kulkarni 	u8 flags0;
352*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK  0xF /* connection_type */
353*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
354*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK     0x1 /* exist_in_qm0 */
355*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT    4
356*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK             0x1 /* exist_in_qm1 */
357*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT            5
358*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_MASK            0x1 /* bit2 */
359*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT           6
360*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT3_MASK             0x1 /* bit3 */
361*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT            7
362*14b24e2bSVaishali Kulkarni 	u8 flags1;
363*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_MASK              0x3 /* cf0 */
364*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT             0
365*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_MASK              0x3 /* cf1 */
366*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT             2
367*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK       0x3 /* cf2special */
368*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT      4
369*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK            0x1 /* cf0en */
370*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT           6
371*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK            0x1 /* cf1en */
372*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT           7
373*14b24e2bSVaishali Kulkarni 	u8 flags2;
374*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK             0x1 /* bit4 */
375*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT            0
376*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK          0x1 /* rule0en */
377*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT         1
378*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK          0x1 /* rule1en */
379*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT         2
380*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK          0x1 /* rule2en */
381*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT         3
382*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK          0x1 /* rule3en */
383*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT         4
384*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK          0x1 /* rule4en */
385*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT         5
386*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK          0x1 /* rule5en */
387*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT         6
388*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK          0x1 /* rule6en */
389*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT         7
390*14b24e2bSVaishali Kulkarni 	u8 key /* byte2 */;
391*14b24e2bSVaishali Kulkarni 	__le32 mw_cnt /* reg0 */;
392*14b24e2bSVaishali Kulkarni 	u8 ref_cnt_seq /* byte3 */;
393*14b24e2bSVaishali Kulkarni 	u8 ctx_upd_seq /* byte4 */;
394*14b24e2bSVaishali Kulkarni 	__le16 dif_flags /* word1 */;
395*14b24e2bSVaishali Kulkarni 	__le16 tx_ref_count /* word2 */;
396*14b24e2bSVaishali Kulkarni 	__le16 last_used_ltid /* word3 */;
397*14b24e2bSVaishali Kulkarni 	__le16 parent_mr_lo /* word4 */;
398*14b24e2bSVaishali Kulkarni 	__le16 parent_mr_hi /* word5 */;
399*14b24e2bSVaishali Kulkarni 	__le32 fbo_lo /* reg1 */;
400*14b24e2bSVaishali Kulkarni 	__le32 fbo_hi /* reg2 */;
401*14b24e2bSVaishali Kulkarni };
402*14b24e2bSVaishali Kulkarni 
403*14b24e2bSVaishali Kulkarni struct e4_mstorm_rdma_task_ag_ctx
404*14b24e2bSVaishali Kulkarni {
405*14b24e2bSVaishali Kulkarni 	u8 reserved /* cdu_validation */;
406*14b24e2bSVaishali Kulkarni 	u8 byte1 /* state */;
407*14b24e2bSVaishali Kulkarni 	__le16 icid /* icid */;
408*14b24e2bSVaishali Kulkarni 	u8 flags0;
409*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK  0xF /* connection_type */
410*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
411*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK     0x1 /* exist_in_qm0 */
412*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT    4
413*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK             0x1 /* exist_in_qm1 */
414*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT            5
415*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK             0x1 /* bit2 */
416*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT            6
417*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT3_MASK             0x1 /* bit3 */
418*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT            7
419*14b24e2bSVaishali Kulkarni 	u8 flags1;
420*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_MASK              0x3 /* cf0 */
421*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT             0
422*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_MASK              0x3 /* cf1 */
423*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT             2
424*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_MASK              0x3 /* cf2 */
425*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT             4
426*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK            0x1 /* cf0en */
427*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT           6
428*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK            0x1 /* cf1en */
429*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT           7
430*14b24e2bSVaishali Kulkarni 	u8 flags2;
431*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK            0x1 /* cf2en */
432*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT           0
433*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK          0x1 /* rule0en */
434*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT         1
435*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK          0x1 /* rule1en */
436*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT         2
437*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK          0x1 /* rule2en */
438*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT         3
439*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK          0x1 /* rule3en */
440*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT         4
441*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK          0x1 /* rule4en */
442*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT         5
443*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK          0x1 /* rule5en */
444*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT         6
445*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK          0x1 /* rule6en */
446*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT         7
447*14b24e2bSVaishali Kulkarni 	u8 key /* byte2 */;
448*14b24e2bSVaishali Kulkarni 	__le32 mw_cnt /* reg0 */;
449*14b24e2bSVaishali Kulkarni 	u8 ref_cnt_seq /* byte3 */;
450*14b24e2bSVaishali Kulkarni 	u8 ctx_upd_seq /* byte4 */;
451*14b24e2bSVaishali Kulkarni 	__le16 dif_flags /* word1 */;
452*14b24e2bSVaishali Kulkarni 	__le16 tx_ref_count /* word2 */;
453*14b24e2bSVaishali Kulkarni 	__le16 last_used_ltid /* word3 */;
454*14b24e2bSVaishali Kulkarni 	__le16 parent_mr_lo /* word4 */;
455*14b24e2bSVaishali Kulkarni 	__le16 parent_mr_hi /* word5 */;
456*14b24e2bSVaishali Kulkarni 	__le32 fbo_lo /* reg1 */;
457*14b24e2bSVaishali Kulkarni 	__le32 fbo_hi /* reg2 */;
458*14b24e2bSVaishali Kulkarni };
459*14b24e2bSVaishali Kulkarni 
460*14b24e2bSVaishali Kulkarni /*
461*14b24e2bSVaishali Kulkarni  * The roce task context of Ustorm
462*14b24e2bSVaishali Kulkarni  */
463*14b24e2bSVaishali Kulkarni struct ustorm_rdma_task_st_ctx
464*14b24e2bSVaishali Kulkarni {
465*14b24e2bSVaishali Kulkarni 	struct regpair temp[2];
466*14b24e2bSVaishali Kulkarni };
467*14b24e2bSVaishali Kulkarni 
468*14b24e2bSVaishali Kulkarni struct e4_ustorm_rdma_task_ag_ctx
469*14b24e2bSVaishali Kulkarni {
470*14b24e2bSVaishali Kulkarni 	u8 reserved /* cdu_validation */;
471*14b24e2bSVaishali Kulkarni 	u8 byte1 /* state */;
472*14b24e2bSVaishali Kulkarni 	__le16 icid /* icid */;
473*14b24e2bSVaishali Kulkarni 	u8 flags0;
474*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK         0xF /* connection_type */
475*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT        0
476*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK            0x1 /* exist_in_qm0 */
477*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT           4
478*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_MASK          0x1 /* exist_in_qm1 */
479*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_SHIFT         5
480*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK     0x3 /* timer0cf */
481*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT    6
482*14b24e2bSVaishali Kulkarni 	u8 flags1;
483*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK   0x3 /* timer1cf */
484*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT  0
485*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK           0x3 /* timer2cf */
486*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT          2
487*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_CF3_MASK                     0x3 /* timer_stop_all */
488*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_CF3_SHIFT                    4
489*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK            0x3 /* cf4 */
490*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT           6
491*14b24e2bSVaishali Kulkarni 	u8 flags2;
492*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK  0x1 /* cf0en */
493*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0
494*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK               0x1 /* cf1en */
495*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT              1
496*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK               0x1 /* cf2en */
497*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT              2
498*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_CF3EN_MASK                   0x1 /* cf3en */
499*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT                  3
500*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK         0x1 /* cf4en */
501*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT        4
502*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK                 0x1 /* rule0en */
503*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT                5
504*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK                 0x1 /* rule1en */
505*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT                6
506*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK                 0x1 /* rule2en */
507*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT                7
508*14b24e2bSVaishali Kulkarni 	u8 flags3;
509*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK                 0x1 /* rule3en */
510*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT                0
511*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK                 0x1 /* rule4en */
512*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT                1
513*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK                 0x1 /* rule5en */
514*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT                2
515*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK                 0x1 /* rule6en */
516*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT                3
517*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK          0xF /* nibble1 */
518*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT         4
519*14b24e2bSVaishali Kulkarni 	__le32 dif_err_intervals /* reg0 */;
520*14b24e2bSVaishali Kulkarni 	__le32 dif_error_1st_interval /* reg1 */;
521*14b24e2bSVaishali Kulkarni 	__le32 reg2 /* reg2 */;
522*14b24e2bSVaishali Kulkarni 	__le32 dif_runt_value /* reg3 */;
523*14b24e2bSVaishali Kulkarni 	__le32 reg4 /* reg4 */;
524*14b24e2bSVaishali Kulkarni 	__le32 reg5 /* reg5 */;
525*14b24e2bSVaishali Kulkarni };
526*14b24e2bSVaishali Kulkarni 
527*14b24e2bSVaishali Kulkarni /*
528*14b24e2bSVaishali Kulkarni  * RDMA task context
529*14b24e2bSVaishali Kulkarni  */
530*14b24e2bSVaishali Kulkarni struct rdma_task_context
531*14b24e2bSVaishali Kulkarni {
532*14b24e2bSVaishali Kulkarni 	struct ystorm_rdma_task_st_ctx ystorm_st_context /* ystorm storm context */;
533*14b24e2bSVaishali Kulkarni 	struct e4_ystorm_rdma_task_ag_ctx ystorm_ag_context /* ystorm aggregative context */;
534*14b24e2bSVaishali Kulkarni 	struct tdif_task_context tdif_context /* tdif context */;
535*14b24e2bSVaishali Kulkarni 	struct e4_mstorm_rdma_task_ag_ctx mstorm_ag_context /* mstorm aggregative context */;
536*14b24e2bSVaishali Kulkarni 	struct mstorm_rdma_task_st_ctx mstorm_st_context /* mstorm storm context */;
537*14b24e2bSVaishali Kulkarni 	struct rdif_task_context rdif_context /* rdif context */;
538*14b24e2bSVaishali Kulkarni 	struct ustorm_rdma_task_st_ctx ustorm_st_context /* ustorm storm context */;
539*14b24e2bSVaishali Kulkarni 	struct regpair ustorm_st_padding[2] /* padding */;
540*14b24e2bSVaishali Kulkarni 	struct e4_ustorm_rdma_task_ag_ctx ustorm_ag_context /* ustorm aggregative context */;
541*14b24e2bSVaishali Kulkarni };
542*14b24e2bSVaishali Kulkarni 
543*14b24e2bSVaishali Kulkarni 
544*14b24e2bSVaishali Kulkarni /*
545*14b24e2bSVaishali Kulkarni  * RDMA Tid type enumeration (for register_tid ramrod)
546*14b24e2bSVaishali Kulkarni  */
547*14b24e2bSVaishali Kulkarni enum rdma_tid_type
548*14b24e2bSVaishali Kulkarni {
549*14b24e2bSVaishali Kulkarni 	RDMA_TID_REGISTERED_MR,
550*14b24e2bSVaishali Kulkarni 	RDMA_TID_FMR,
551*14b24e2bSVaishali Kulkarni 	RDMA_TID_MW_TYPE1,
552*14b24e2bSVaishali Kulkarni 	RDMA_TID_MW_TYPE2A,
553*14b24e2bSVaishali Kulkarni 	MAX_RDMA_TID_TYPE
554*14b24e2bSVaishali Kulkarni };
555*14b24e2bSVaishali Kulkarni 
556*14b24e2bSVaishali Kulkarni 
557*14b24e2bSVaishali Kulkarni 
558*14b24e2bSVaishali Kulkarni 
559*14b24e2bSVaishali Kulkarni struct E4XstormRoceConnAgCtxDqExtLdPart
560*14b24e2bSVaishali Kulkarni {
561*14b24e2bSVaishali Kulkarni 	u8 reserved0 /* cdu_validation */;
562*14b24e2bSVaishali Kulkarni 	u8 state /* state */;
563*14b24e2bSVaishali Kulkarni 	u8 flags0;
564*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK      0x1 /* exist_in_qm0 */
565*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT     0
566*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK              0x1 /* exist_in_qm1 */
567*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_SHIFT             1
568*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK              0x1 /* exist_in_qm2 */
569*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_SHIFT             2
570*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK      0x1 /* exist_in_qm3 */
571*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT     3
572*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK              0x1 /* bit4 */
573*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_SHIFT             4
574*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK              0x1 /* cf_array_active */
575*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_SHIFT             5
576*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK              0x1 /* bit6 */
577*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_SHIFT             6
578*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK              0x1 /* bit7 */
579*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_SHIFT             7
580*14b24e2bSVaishali Kulkarni 	u8 flags1;
581*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK              0x1 /* bit8 */
582*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_SHIFT             0
583*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK              0x1 /* bit9 */
584*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_SHIFT             1
585*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK             0x1 /* bit10 */
586*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT            2
587*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK             0x1 /* bit11 */
588*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT            3
589*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_MASK             0x1 /* bit12 */
590*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_SHIFT            4
591*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSTORM_FLUSH_MASK      0x1 /* bit13 */
592*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSTORM_FLUSH_SHIFT     5
593*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_MASK             0x1 /* bit14 */
594*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_SHIFT            6
595*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK      0x1 /* bit15 */
596*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT     7
597*14b24e2bSVaishali Kulkarni 	u8 flags2;
598*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK               0x3 /* timer0cf */
599*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT              0
600*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK               0x3 /* timer1cf */
601*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT              2
602*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK               0x3 /* timer2cf */
603*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT              4
604*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK               0x3 /* timer_stop_all */
605*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT              6
606*14b24e2bSVaishali Kulkarni 	u8 flags3;
607*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK               0x3 /* cf4 */
608*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_SHIFT              0
609*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK               0x3 /* cf5 */
610*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_SHIFT              2
611*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK               0x3 /* cf6 */
612*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_SHIFT              4
613*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK       0x3 /* cf7 */
614*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT      6
615*14b24e2bSVaishali Kulkarni 	u8 flags4;
616*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK               0x3 /* cf8 */
617*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT              0
618*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK               0x3 /* cf9 */
619*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT              2
620*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK              0x3 /* cf10 */
621*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT             4
622*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK              0x3 /* cf11 */
623*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT             6
624*14b24e2bSVaishali Kulkarni 	u8 flags5;
625*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK              0x3 /* cf12 */
626*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT             0
627*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK              0x3 /* cf13 */
628*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT             2
629*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK              0x3 /* cf14 */
630*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_SHIFT             4
631*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK              0x3 /* cf15 */
632*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT             6
633*14b24e2bSVaishali Kulkarni 	u8 flags6;
634*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK              0x3 /* cf16 */
635*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT             0
636*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK              0x3 /* cf_array_cf */
637*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT             2
638*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK              0x3 /* cf18 */
639*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT             4
640*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK              0x3 /* cf19 */
641*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT             6
642*14b24e2bSVaishali Kulkarni 	u8 flags7;
643*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK              0x3 /* cf20 */
644*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT             0
645*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK              0x3 /* cf21 */
646*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT             2
647*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK         0x3 /* cf22 */
648*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT        4
649*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK             0x1 /* cf0en */
650*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT            6
651*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK             0x1 /* cf1en */
652*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT            7
653*14b24e2bSVaishali Kulkarni 	u8 flags8;
654*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK             0x1 /* cf2en */
655*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT            0
656*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK             0x1 /* cf3en */
657*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT            1
658*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK             0x1 /* cf4en */
659*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_SHIFT            2
660*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK             0x1 /* cf5en */
661*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_SHIFT            3
662*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK             0x1 /* cf6en */
663*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_SHIFT            4
664*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK    0x1 /* cf7en */
665*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT   5
666*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK             0x1 /* cf8en */
667*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT            6
668*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK             0x1 /* cf9en */
669*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT            7
670*14b24e2bSVaishali Kulkarni 	u8 flags9;
671*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK            0x1 /* cf10en */
672*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT           0
673*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK            0x1 /* cf11en */
674*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT           1
675*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK            0x1 /* cf12en */
676*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT           2
677*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK            0x1 /* cf13en */
678*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT           3
679*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK            0x1 /* cf14en */
680*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_SHIFT           4
681*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK            0x1 /* cf15en */
682*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT           5
683*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK            0x1 /* cf16en */
684*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT           6
685*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK            0x1 /* cf_array_cf_en */
686*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT           7
687*14b24e2bSVaishali Kulkarni 	u8 flags10;
688*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK            0x1 /* cf18en */
689*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT           0
690*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK            0x1 /* cf19en */
691*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT           1
692*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK            0x1 /* cf20en */
693*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT           2
694*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK            0x1 /* cf21en */
695*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT           3
696*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK      0x1 /* cf22en */
697*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT     4
698*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK            0x1 /* cf23en */
699*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT           5
700*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK           0x1 /* rule0en */
701*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT          6
702*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK           0x1 /* rule1en */
703*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT          7
704*14b24e2bSVaishali Kulkarni 	u8 flags11;
705*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK           0x1 /* rule2en */
706*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT          0
707*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK           0x1 /* rule3en */
708*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_SHIFT          1
709*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK           0x1 /* rule4en */
710*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_SHIFT          2
711*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK           0x1 /* rule5en */
712*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_SHIFT          3
713*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK           0x1 /* rule6en */
714*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_SHIFT          4
715*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_MASK           0x1 /* rule7en */
716*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_SHIFT          5
717*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK      0x1 /* rule8en */
718*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT     6
719*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK           0x1 /* rule9en */
720*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_SHIFT          7
721*14b24e2bSVaishali Kulkarni 	u8 flags12;
722*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_MASK          0x1 /* rule10en */
723*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_SHIFT         0
724*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK          0x1 /* rule11en */
725*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_SHIFT         1
726*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK      0x1 /* rule12en */
727*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT     2
728*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK      0x1 /* rule13en */
729*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT     3
730*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_MASK          0x1 /* rule14en */
731*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_SHIFT         4
732*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK          0x1 /* rule15en */
733*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_SHIFT         5
734*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_MASK          0x1 /* rule16en */
735*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_SHIFT         6
736*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_MASK          0x1 /* rule17en */
737*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_SHIFT         7
738*14b24e2bSVaishali Kulkarni 	u8 flags13;
739*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK          0x1 /* rule18en */
740*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT         0
741*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK          0x1 /* rule19en */
742*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_SHIFT         1
743*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK      0x1 /* rule20en */
744*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT     2
745*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK      0x1 /* rule21en */
746*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT     3
747*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK      0x1 /* rule22en */
748*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT     4
749*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK      0x1 /* rule23en */
750*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT     5
751*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK      0x1 /* rule24en */
752*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT     6
753*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK      0x1 /* rule25en */
754*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT     7
755*14b24e2bSVaishali Kulkarni 	u8 flags14;
756*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_MASK         0x1 /* bit16 */
757*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_SHIFT        0
758*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK             0x1 /* bit17 */
759*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_SHIFT            1
760*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK      0x3 /* bit18 */
761*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_SHIFT     2
762*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK          0x1 /* bit20 */
763*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_SHIFT         4
764*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK  0x1 /* bit21 */
765*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5
766*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK              0x3 /* cf23 */
767*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_SHIFT             6
768*14b24e2bSVaishali Kulkarni 	u8 byte2 /* byte2 */;
769*14b24e2bSVaishali Kulkarni 	__le16 physical_q0 /* physical_q0 */;
770*14b24e2bSVaishali Kulkarni 	__le16 word1 /* physical_q1 */;
771*14b24e2bSVaishali Kulkarni 	__le16 word2 /* physical_q2 */;
772*14b24e2bSVaishali Kulkarni 	__le16 word3 /* word3 */;
773*14b24e2bSVaishali Kulkarni 	__le16 word4 /* word4 */;
774*14b24e2bSVaishali Kulkarni 	__le16 word5 /* word5 */;
775*14b24e2bSVaishali Kulkarni 	__le16 conn_dpi /* conn_dpi */;
776*14b24e2bSVaishali Kulkarni 	u8 byte3 /* byte3 */;
777*14b24e2bSVaishali Kulkarni 	u8 byte4 /* byte4 */;
778*14b24e2bSVaishali Kulkarni 	u8 byte5 /* byte5 */;
779*14b24e2bSVaishali Kulkarni 	u8 byte6 /* byte6 */;
780*14b24e2bSVaishali Kulkarni 	__le32 reg0 /* reg0 */;
781*14b24e2bSVaishali Kulkarni 	__le32 reg1 /* reg1 */;
782*14b24e2bSVaishali Kulkarni 	__le32 reg2 /* reg2 */;
783*14b24e2bSVaishali Kulkarni 	__le32 snd_nxt_psn /* reg3 */;
784*14b24e2bSVaishali Kulkarni 	__le32 reg4 /* reg4 */;
785*14b24e2bSVaishali Kulkarni };
786*14b24e2bSVaishali Kulkarni 
787*14b24e2bSVaishali Kulkarni 
788*14b24e2bSVaishali Kulkarni struct e4_mstorm_rdma_conn_ag_ctx
789*14b24e2bSVaishali Kulkarni {
790*14b24e2bSVaishali Kulkarni 	u8 byte0 /* cdu_validation */;
791*14b24e2bSVaishali Kulkarni 	u8 byte1 /* state */;
792*14b24e2bSVaishali Kulkarni 	u8 flags0;
793*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_CONN_AG_CTX_BIT0_MASK     0x1 /* exist_in_qm0 */
794*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT    0
795*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_CONN_AG_CTX_BIT1_MASK     0x1 /* exist_in_qm1 */
796*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT    1
797*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_CONN_AG_CTX_CF0_MASK      0x3 /* cf0 */
798*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT     2
799*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_CONN_AG_CTX_CF1_MASK      0x3 /* cf1 */
800*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT     4
801*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_CONN_AG_CTX_CF2_MASK      0x3 /* cf2 */
802*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT     6
803*14b24e2bSVaishali Kulkarni 	u8 flags1;
804*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK    0x1 /* cf0en */
805*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT   0
806*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK    0x1 /* cf1en */
807*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT   1
808*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK    0x1 /* cf2en */
809*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT   2
810*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK  0x1 /* rule0en */
811*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3
812*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK  0x1 /* rule1en */
813*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4
814*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK  0x1 /* rule2en */
815*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5
816*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK  0x1 /* rule3en */
817*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6
818*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK  0x1 /* rule4en */
819*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7
820*14b24e2bSVaishali Kulkarni 	__le16 word0 /* word0 */;
821*14b24e2bSVaishali Kulkarni 	__le16 word1 /* word1 */;
822*14b24e2bSVaishali Kulkarni 	__le32 reg0 /* reg0 */;
823*14b24e2bSVaishali Kulkarni 	__le32 reg1 /* reg1 */;
824*14b24e2bSVaishali Kulkarni };
825*14b24e2bSVaishali Kulkarni 
826*14b24e2bSVaishali Kulkarni 
827*14b24e2bSVaishali Kulkarni 
828*14b24e2bSVaishali Kulkarni struct e4_tstorm_rdma_conn_ag_ctx
829*14b24e2bSVaishali Kulkarni {
830*14b24e2bSVaishali Kulkarni 	u8 reserved0 /* cdu_validation */;
831*14b24e2bSVaishali Kulkarni 	u8 byte1 /* state */;
832*14b24e2bSVaishali Kulkarni 	u8 flags0;
833*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK          0x1 /* exist_in_qm0 */
834*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT         0
835*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT1_MASK                  0x1 /* exist_in_qm1 */
836*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT                 1
837*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT2_MASK                  0x1 /* bit2 */
838*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT                 2
839*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT3_MASK                  0x1 /* bit3 */
840*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT3_SHIFT                 3
841*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT4_MASK                  0x1 /* bit4 */
842*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT                 4
843*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT5_MASK                  0x1 /* bit5 */
844*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT                 5
845*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_CF0_MASK                   0x3 /* timer0cf */
846*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT                  6
847*14b24e2bSVaishali Kulkarni 	u8 flags1;
848*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_CF1_MASK                   0x3 /* timer1cf */
849*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT                  0
850*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_CF2_MASK                   0x3 /* timer2cf */
851*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT                  2
852*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK     0x3 /* timer_stop_all */
853*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT    4
854*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK           0x3 /* cf4 */
855*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT          6
856*14b24e2bSVaishali Kulkarni 	u8 flags2;
857*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK       0x3 /* cf5 */
858*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT      0
859*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_CF6_MASK                   0x3 /* cf6 */
860*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT                  2
861*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_CF7_MASK                   0x3 /* cf7 */
862*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_CF7_SHIFT                  4
863*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_CF8_MASK                   0x3 /* cf8 */
864*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT                  6
865*14b24e2bSVaishali Kulkarni 	u8 flags3;
866*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_CF9_MASK                   0x3 /* cf9 */
867*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT                  0
868*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_CF10_MASK                  0x3 /* cf10 */
869*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT                 2
870*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK                 0x1 /* cf0en */
871*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT                4
872*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK                 0x1 /* cf1en */
873*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT                5
874*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK                 0x1 /* cf2en */
875*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT                6
876*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK  0x1 /* cf3en */
877*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
878*14b24e2bSVaishali Kulkarni 	u8 flags4;
879*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK        0x1 /* cf4en */
880*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT       0
881*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK    0x1 /* cf5en */
882*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT   1
883*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK                 0x1 /* cf6en */
884*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT                2
885*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_CF7EN_MASK                 0x1 /* cf7en */
886*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_CF7EN_SHIFT                3
887*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK                 0x1 /* cf8en */
888*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT                4
889*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK                 0x1 /* cf9en */
890*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT                5
891*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK                0x1 /* cf10en */
892*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT               6
893*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK               0x1 /* rule0en */
894*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT              7
895*14b24e2bSVaishali Kulkarni 	u8 flags5;
896*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK               0x1 /* rule1en */
897*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT              0
898*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK               0x1 /* rule2en */
899*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT              1
900*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK               0x1 /* rule3en */
901*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT              2
902*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK               0x1 /* rule4en */
903*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT              3
904*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK               0x1 /* rule5en */
905*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT              4
906*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK               0x1 /* rule6en */
907*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT              5
908*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK               0x1 /* rule7en */
909*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT              6
910*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK               0x1 /* rule8en */
911*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT              7
912*14b24e2bSVaishali Kulkarni 	__le32 reg0 /* reg0 */;
913*14b24e2bSVaishali Kulkarni 	__le32 reg1 /* reg1 */;
914*14b24e2bSVaishali Kulkarni 	__le32 reg2 /* reg2 */;
915*14b24e2bSVaishali Kulkarni 	__le32 reg3 /* reg3 */;
916*14b24e2bSVaishali Kulkarni 	__le32 reg4 /* reg4 */;
917*14b24e2bSVaishali Kulkarni 	__le32 reg5 /* reg5 */;
918*14b24e2bSVaishali Kulkarni 	__le32 reg6 /* reg6 */;
919*14b24e2bSVaishali Kulkarni 	__le32 reg7 /* reg7 */;
920*14b24e2bSVaishali Kulkarni 	__le32 reg8 /* reg8 */;
921*14b24e2bSVaishali Kulkarni 	u8 byte2 /* byte2 */;
922*14b24e2bSVaishali Kulkarni 	u8 byte3 /* byte3 */;
923*14b24e2bSVaishali Kulkarni 	__le16 word0 /* word0 */;
924*14b24e2bSVaishali Kulkarni 	u8 byte4 /* byte4 */;
925*14b24e2bSVaishali Kulkarni 	u8 byte5 /* byte5 */;
926*14b24e2bSVaishali Kulkarni 	__le16 word1 /* word1 */;
927*14b24e2bSVaishali Kulkarni 	__le16 word2 /* conn_dpi */;
928*14b24e2bSVaishali Kulkarni 	__le16 word3 /* word3 */;
929*14b24e2bSVaishali Kulkarni 	__le32 reg9 /* reg9 */;
930*14b24e2bSVaishali Kulkarni 	__le32 reg10 /* reg10 */;
931*14b24e2bSVaishali Kulkarni };
932*14b24e2bSVaishali Kulkarni 
933*14b24e2bSVaishali Kulkarni 
934*14b24e2bSVaishali Kulkarni struct e4_tstorm_rdma_task_ag_ctx
935*14b24e2bSVaishali Kulkarni {
936*14b24e2bSVaishali Kulkarni 	u8 byte0 /* cdu_validation */;
937*14b24e2bSVaishali Kulkarni 	u8 byte1 /* state */;
938*14b24e2bSVaishali Kulkarni 	__le16 word0 /* icid */;
939*14b24e2bSVaishali Kulkarni 	u8 flags0;
940*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK  0xF /* connection_type */
941*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT 0
942*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK     0x1 /* exist_in_qm0 */
943*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT    4
944*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK     0x1 /* exist_in_qm1 */
945*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT    5
946*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK     0x1 /* bit2 */
947*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT    6
948*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK     0x1 /* bit3 */
949*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT    7
950*14b24e2bSVaishali Kulkarni 	u8 flags1;
951*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK     0x1 /* bit4 */
952*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT    0
953*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK     0x1 /* bit5 */
954*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT    1
955*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_MASK      0x3 /* timer0cf */
956*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT     2
957*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_MASK      0x3 /* timer1cf */
958*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT     4
959*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_MASK      0x3 /* timer2cf */
960*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT     6
961*14b24e2bSVaishali Kulkarni 	u8 flags2;
962*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_MASK      0x3 /* timer_stop_all */
963*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT     0
964*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_MASK      0x3 /* cf4 */
965*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT     2
966*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_MASK      0x3 /* cf5 */
967*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT     4
968*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_MASK      0x3 /* cf6 */
969*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT     6
970*14b24e2bSVaishali Kulkarni 	u8 flags3;
971*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_MASK      0x3 /* cf7 */
972*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT     0
973*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK    0x1 /* cf0en */
974*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT   2
975*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK    0x1 /* cf1en */
976*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT   3
977*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK    0x1 /* cf2en */
978*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT   4
979*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK    0x1 /* cf3en */
980*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT   5
981*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK    0x1 /* cf4en */
982*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT   6
983*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK    0x1 /* cf5en */
984*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT   7
985*14b24e2bSVaishali Kulkarni 	u8 flags4;
986*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK    0x1 /* cf6en */
987*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT   0
988*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK    0x1 /* cf7en */
989*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT   1
990*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK  0x1 /* rule0en */
991*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 2
992*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK  0x1 /* rule1en */
993*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 3
994*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK  0x1 /* rule2en */
995*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 4
996*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK  0x1 /* rule3en */
997*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 5
998*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK  0x1 /* rule4en */
999*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 6
1000*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK  0x1 /* rule5en */
1001*14b24e2bSVaishali Kulkarni #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 7
1002*14b24e2bSVaishali Kulkarni 	u8 byte2 /* byte2 */;
1003*14b24e2bSVaishali Kulkarni 	__le16 word1 /* word1 */;
1004*14b24e2bSVaishali Kulkarni 	__le32 reg0 /* reg0 */;
1005*14b24e2bSVaishali Kulkarni 	u8 byte3 /* byte3 */;
1006*14b24e2bSVaishali Kulkarni 	u8 byte4 /* byte4 */;
1007*14b24e2bSVaishali Kulkarni 	__le16 word2 /* word2 */;
1008*14b24e2bSVaishali Kulkarni 	__le16 word3 /* word3 */;
1009*14b24e2bSVaishali Kulkarni 	__le16 word4 /* word4 */;
1010*14b24e2bSVaishali Kulkarni 	__le32 reg1 /* reg1 */;
1011*14b24e2bSVaishali Kulkarni 	__le32 reg2 /* reg2 */;
1012*14b24e2bSVaishali Kulkarni };
1013*14b24e2bSVaishali Kulkarni 
1014*14b24e2bSVaishali Kulkarni 
1015*14b24e2bSVaishali Kulkarni struct e4_ustorm_rdma_conn_ag_ctx
1016*14b24e2bSVaishali Kulkarni {
1017*14b24e2bSVaishali Kulkarni 	u8 reserved /* cdu_validation */;
1018*14b24e2bSVaishali Kulkarni 	u8 byte1 /* state */;
1019*14b24e2bSVaishali Kulkarni 	u8 flags0;
1020*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK     0x1 /* exist_in_qm0 */
1021*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT    0
1022*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_BIT1_MASK             0x1 /* exist_in_qm1 */
1023*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT            1
1024*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK      0x3 /* timer0cf */
1025*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT     2
1026*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_CF1_MASK              0x3 /* timer1cf */
1027*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT             4
1028*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_CF2_MASK              0x3 /* timer2cf */
1029*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT             6
1030*14b24e2bSVaishali Kulkarni 	u8 flags1;
1031*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_CF3_MASK              0x3 /* timer_stop_all */
1032*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT             0
1033*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK     0x3 /* cf4 */
1034*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT    2
1035*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK        0x3 /* cf5 */
1036*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT       4
1037*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_CF6_MASK              0x3 /* cf6 */
1038*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT             6
1039*14b24e2bSVaishali Kulkarni 	u8 flags2;
1040*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK   0x1 /* cf0en */
1041*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT  0
1042*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK            0x1 /* cf1en */
1043*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT           1
1044*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK            0x1 /* cf2en */
1045*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT           2
1046*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK            0x1 /* cf3en */
1047*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT           3
1048*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK  0x1 /* cf4en */
1049*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4
1050*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK     0x1 /* cf5en */
1051*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT    5
1052*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK            0x1 /* cf6en */
1053*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT           6
1054*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK         0x1 /* rule0en */
1055*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT        7
1056*14b24e2bSVaishali Kulkarni 	u8 flags3;
1057*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK            0x1 /* rule1en */
1058*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT           0
1059*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK          0x1 /* rule2en */
1060*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT         1
1061*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK          0x1 /* rule3en */
1062*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT         2
1063*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK          0x1 /* rule4en */
1064*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT         3
1065*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK          0x1 /* rule5en */
1066*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT         4
1067*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK          0x1 /* rule6en */
1068*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT         5
1069*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK          0x1 /* rule7en */
1070*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT         6
1071*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK          0x1 /* rule8en */
1072*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT         7
1073*14b24e2bSVaishali Kulkarni 	u8 byte2 /* byte2 */;
1074*14b24e2bSVaishali Kulkarni 	u8 byte3 /* byte3 */;
1075*14b24e2bSVaishali Kulkarni 	__le16 conn_dpi /* conn_dpi */;
1076*14b24e2bSVaishali Kulkarni 	__le16 word1 /* word1 */;
1077*14b24e2bSVaishali Kulkarni 	__le32 cq_cons /* reg0 */;
1078*14b24e2bSVaishali Kulkarni 	__le32 cq_se_prod /* reg1 */;
1079*14b24e2bSVaishali Kulkarni 	__le32 cq_prod /* reg2 */;
1080*14b24e2bSVaishali Kulkarni 	__le32 reg3 /* reg3 */;
1081*14b24e2bSVaishali Kulkarni 	__le16 int_timeout /* word2 */;
1082*14b24e2bSVaishali Kulkarni 	__le16 word3 /* word3 */;
1083*14b24e2bSVaishali Kulkarni };
1084*14b24e2bSVaishali Kulkarni 
1085*14b24e2bSVaishali Kulkarni 
1086*14b24e2bSVaishali Kulkarni 
1087*14b24e2bSVaishali Kulkarni struct e4_xstorm_rdma_conn_ag_ctx
1088*14b24e2bSVaishali Kulkarni {
1089*14b24e2bSVaishali Kulkarni 	u8 reserved0 /* cdu_validation */;
1090*14b24e2bSVaishali Kulkarni 	u8 state /* state */;
1091*14b24e2bSVaishali Kulkarni 	u8 flags0;
1092*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK      0x1 /* exist_in_qm0 */
1093*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT     0
1094*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT1_MASK              0x1 /* exist_in_qm1 */
1095*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT             1
1096*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT2_MASK              0x1 /* exist_in_qm2 */
1097*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT             2
1098*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_MASK      0x1 /* exist_in_qm3 */
1099*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_SHIFT     3
1100*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT4_MASK              0x1 /* bit4 */
1101*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT             4
1102*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT5_MASK              0x1 /* cf_array_active */
1103*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT             5
1104*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT6_MASK              0x1 /* bit6 */
1105*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT6_SHIFT             6
1106*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT7_MASK              0x1 /* bit7 */
1107*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT7_SHIFT             7
1108*14b24e2bSVaishali Kulkarni 	u8 flags1;
1109*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT8_MASK              0x1 /* bit8 */
1110*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT8_SHIFT             0
1111*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT9_MASK              0x1 /* bit9 */
1112*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT9_SHIFT             1
1113*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT10_MASK             0x1 /* bit10 */
1114*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT10_SHIFT            2
1115*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT11_MASK             0x1 /* bit11 */
1116*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT11_SHIFT            3
1117*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT12_MASK             0x1 /* bit12 */
1118*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT12_SHIFT            4
1119*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_MASK      0x1 /* bit13 */
1120*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_SHIFT     5
1121*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT14_MASK             0x1 /* bit14 */
1122*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT14_SHIFT            6
1123*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_MASK      0x1 /* bit15 */
1124*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_SHIFT     7
1125*14b24e2bSVaishali Kulkarni 	u8 flags2;
1126*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF0_MASK               0x3 /* timer0cf */
1127*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT              0
1128*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF1_MASK               0x3 /* timer1cf */
1129*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT              2
1130*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF2_MASK               0x3 /* timer2cf */
1131*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT              4
1132*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF3_MASK               0x3 /* timer_stop_all */
1133*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF3_SHIFT              6
1134*14b24e2bSVaishali Kulkarni 	u8 flags3;
1135*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF4_MASK               0x3 /* cf4 */
1136*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF4_SHIFT              0
1137*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF5_MASK               0x3 /* cf5 */
1138*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF5_SHIFT              2
1139*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF6_MASK               0x3 /* cf6 */
1140*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT              4
1141*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK       0x3 /* cf7 */
1142*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT      6
1143*14b24e2bSVaishali Kulkarni 	u8 flags4;
1144*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF8_MASK               0x3 /* cf8 */
1145*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT              0
1146*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF9_MASK               0x3 /* cf9 */
1147*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT              2
1148*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF10_MASK              0x3 /* cf10 */
1149*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT             4
1150*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF11_MASK              0x3 /* cf11 */
1151*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF11_SHIFT             6
1152*14b24e2bSVaishali Kulkarni 	u8 flags5;
1153*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF12_MASK              0x3 /* cf12 */
1154*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF12_SHIFT             0
1155*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF13_MASK              0x3 /* cf13 */
1156*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF13_SHIFT             2
1157*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF14_MASK              0x3 /* cf14 */
1158*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF14_SHIFT             4
1159*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF15_MASK              0x3 /* cf15 */
1160*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF15_SHIFT             6
1161*14b24e2bSVaishali Kulkarni 	u8 flags6;
1162*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF16_MASK              0x3 /* cf16 */
1163*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF16_SHIFT             0
1164*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF17_MASK              0x3 /* cf_array_cf */
1165*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF17_SHIFT             2
1166*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF18_MASK              0x3 /* cf18 */
1167*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF18_SHIFT             4
1168*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF19_MASK              0x3 /* cf19 */
1169*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF19_SHIFT             6
1170*14b24e2bSVaishali Kulkarni 	u8 flags7;
1171*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF20_MASK              0x3 /* cf20 */
1172*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF20_SHIFT             0
1173*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF21_MASK              0x3 /* cf21 */
1174*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF21_SHIFT             2
1175*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_MASK         0x3 /* cf22 */
1176*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_SHIFT        4
1177*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK             0x1 /* cf0en */
1178*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT            6
1179*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK             0x1 /* cf1en */
1180*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT            7
1181*14b24e2bSVaishali Kulkarni 	u8 flags8;
1182*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK             0x1 /* cf2en */
1183*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT            0
1184*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF3EN_MASK             0x1 /* cf3en */
1185*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT            1
1186*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF4EN_MASK             0x1 /* cf4en */
1187*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF4EN_SHIFT            2
1188*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF5EN_MASK             0x1 /* cf5en */
1189*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF5EN_SHIFT            3
1190*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK             0x1 /* cf6en */
1191*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT            4
1192*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK    0x1 /* cf7en */
1193*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT   5
1194*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK             0x1 /* cf8en */
1195*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT            6
1196*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK             0x1 /* cf9en */
1197*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT            7
1198*14b24e2bSVaishali Kulkarni 	u8 flags9;
1199*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK            0x1 /* cf10en */
1200*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT           0
1201*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF11EN_MASK            0x1 /* cf11en */
1202*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF11EN_SHIFT           1
1203*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF12EN_MASK            0x1 /* cf12en */
1204*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF12EN_SHIFT           2
1205*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF13EN_MASK            0x1 /* cf13en */
1206*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF13EN_SHIFT           3
1207*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF14EN_MASK            0x1 /* cf14en */
1208*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF14EN_SHIFT           4
1209*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF15EN_MASK            0x1 /* cf15en */
1210*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF15EN_SHIFT           5
1211*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF16EN_MASK            0x1 /* cf16en */
1212*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF16EN_SHIFT           6
1213*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF17EN_MASK            0x1 /* cf_array_cf_en */
1214*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF17EN_SHIFT           7
1215*14b24e2bSVaishali Kulkarni 	u8 flags10;
1216*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF18EN_MASK            0x1 /* cf18en */
1217*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF18EN_SHIFT           0
1218*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF19EN_MASK            0x1 /* cf19en */
1219*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF19EN_SHIFT           1
1220*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF20EN_MASK            0x1 /* cf20en */
1221*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF20EN_SHIFT           2
1222*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF21EN_MASK            0x1 /* cf21en */
1223*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF21EN_SHIFT           3
1224*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_MASK      0x1 /* cf22en */
1225*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_SHIFT     4
1226*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF23EN_MASK            0x1 /* cf23en */
1227*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF23EN_SHIFT           5
1228*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK           0x1 /* rule0en */
1229*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT          6
1230*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK           0x1 /* rule1en */
1231*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT          7
1232*14b24e2bSVaishali Kulkarni 	u8 flags11;
1233*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK           0x1 /* rule2en */
1234*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT          0
1235*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK           0x1 /* rule3en */
1236*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT          1
1237*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK           0x1 /* rule4en */
1238*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT          2
1239*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK           0x1 /* rule5en */
1240*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT          3
1241*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK           0x1 /* rule6en */
1242*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT          4
1243*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK           0x1 /* rule7en */
1244*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT          5
1245*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_MASK      0x1 /* rule8en */
1246*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_SHIFT     6
1247*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE9EN_MASK           0x1 /* rule9en */
1248*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE9EN_SHIFT          7
1249*14b24e2bSVaishali Kulkarni 	u8 flags12;
1250*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE10EN_MASK          0x1 /* rule10en */
1251*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE10EN_SHIFT         0
1252*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE11EN_MASK          0x1 /* rule11en */
1253*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE11EN_SHIFT         1
1254*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_MASK      0x1 /* rule12en */
1255*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_SHIFT     2
1256*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_MASK      0x1 /* rule13en */
1257*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_SHIFT     3
1258*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE14EN_MASK          0x1 /* rule14en */
1259*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE14EN_SHIFT         4
1260*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE15EN_MASK          0x1 /* rule15en */
1261*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE15EN_SHIFT         5
1262*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE16EN_MASK          0x1 /* rule16en */
1263*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE16EN_SHIFT         6
1264*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE17EN_MASK          0x1 /* rule17en */
1265*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE17EN_SHIFT         7
1266*14b24e2bSVaishali Kulkarni 	u8 flags13;
1267*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE18EN_MASK          0x1 /* rule18en */
1268*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE18EN_SHIFT         0
1269*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE19EN_MASK          0x1 /* rule19en */
1270*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE19EN_SHIFT         1
1271*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_MASK      0x1 /* rule20en */
1272*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_SHIFT     2
1273*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_MASK      0x1 /* rule21en */
1274*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_SHIFT     3
1275*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_MASK      0x1 /* rule22en */
1276*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_SHIFT     4
1277*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_MASK      0x1 /* rule23en */
1278*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_SHIFT     5
1279*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_MASK      0x1 /* rule24en */
1280*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_SHIFT     6
1281*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_MASK      0x1 /* rule25en */
1282*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_SHIFT     7
1283*14b24e2bSVaishali Kulkarni 	u8 flags14;
1284*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_MIGRATION_MASK         0x1 /* bit16 */
1285*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_MIGRATION_SHIFT        0
1286*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT17_MASK             0x1 /* bit17 */
1287*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT17_SHIFT            1
1288*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_MASK      0x3 /* bit18 */
1289*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_SHIFT     2
1290*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_RESERVED_MASK          0x1 /* bit20 */
1291*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_RESERVED_SHIFT         4
1292*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK  0x1 /* bit21 */
1293*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
1294*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF23_MASK              0x3 /* cf23 */
1295*14b24e2bSVaishali Kulkarni #define E4_XSTORM_RDMA_CONN_AG_CTX_CF23_SHIFT             6
1296*14b24e2bSVaishali Kulkarni 	u8 byte2 /* byte2 */;
1297*14b24e2bSVaishali Kulkarni 	__le16 physical_q0 /* physical_q0 */;
1298*14b24e2bSVaishali Kulkarni 	__le16 word1 /* physical_q1 */;
1299*14b24e2bSVaishali Kulkarni 	__le16 word2 /* physical_q2 */;
1300*14b24e2bSVaishali Kulkarni 	__le16 word3 /* word3 */;
1301*14b24e2bSVaishali Kulkarni 	__le16 word4 /* word4 */;
1302*14b24e2bSVaishali Kulkarni 	__le16 word5 /* word5 */;
1303*14b24e2bSVaishali Kulkarni 	__le16 conn_dpi /* conn_dpi */;
1304*14b24e2bSVaishali Kulkarni 	u8 byte3 /* byte3 */;
1305*14b24e2bSVaishali Kulkarni 	u8 byte4 /* byte4 */;
1306*14b24e2bSVaishali Kulkarni 	u8 byte5 /* byte5 */;
1307*14b24e2bSVaishali Kulkarni 	u8 byte6 /* byte6 */;
1308*14b24e2bSVaishali Kulkarni 	__le32 reg0 /* reg0 */;
1309*14b24e2bSVaishali Kulkarni 	__le32 reg1 /* reg1 */;
1310*14b24e2bSVaishali Kulkarni 	__le32 reg2 /* reg2 */;
1311*14b24e2bSVaishali Kulkarni 	__le32 snd_nxt_psn /* reg3 */;
1312*14b24e2bSVaishali Kulkarni 	__le32 reg4 /* reg4 */;
1313*14b24e2bSVaishali Kulkarni 	__le32 reg5 /* cf_array0 */;
1314*14b24e2bSVaishali Kulkarni 	__le32 reg6 /* cf_array1 */;
1315*14b24e2bSVaishali Kulkarni };
1316*14b24e2bSVaishali Kulkarni 
1317*14b24e2bSVaishali Kulkarni 
1318*14b24e2bSVaishali Kulkarni struct e4_ystorm_rdma_conn_ag_ctx
1319*14b24e2bSVaishali Kulkarni {
1320*14b24e2bSVaishali Kulkarni 	u8 byte0 /* cdu_validation */;
1321*14b24e2bSVaishali Kulkarni 	u8 byte1 /* state */;
1322*14b24e2bSVaishali Kulkarni 	u8 flags0;
1323*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_CONN_AG_CTX_BIT0_MASK     0x1 /* exist_in_qm0 */
1324*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT    0
1325*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_CONN_AG_CTX_BIT1_MASK     0x1 /* exist_in_qm1 */
1326*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT    1
1327*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_CONN_AG_CTX_CF0_MASK      0x3 /* cf0 */
1328*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT     2
1329*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_CONN_AG_CTX_CF1_MASK      0x3 /* cf1 */
1330*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT     4
1331*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_CONN_AG_CTX_CF2_MASK      0x3 /* cf2 */
1332*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT     6
1333*14b24e2bSVaishali Kulkarni 	u8 flags1;
1334*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK    0x1 /* cf0en */
1335*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT   0
1336*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK    0x1 /* cf1en */
1337*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT   1
1338*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK    0x1 /* cf2en */
1339*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT   2
1340*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK  0x1 /* rule0en */
1341*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3
1342*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK  0x1 /* rule1en */
1343*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4
1344*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK  0x1 /* rule2en */
1345*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5
1346*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK  0x1 /* rule3en */
1347*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6
1348*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK  0x1 /* rule4en */
1349*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7
1350*14b24e2bSVaishali Kulkarni 	u8 byte2 /* byte2 */;
1351*14b24e2bSVaishali Kulkarni 	u8 byte3 /* byte3 */;
1352*14b24e2bSVaishali Kulkarni 	__le16 word0 /* word0 */;
1353*14b24e2bSVaishali Kulkarni 	__le32 reg0 /* reg0 */;
1354*14b24e2bSVaishali Kulkarni 	__le32 reg1 /* reg1 */;
1355*14b24e2bSVaishali Kulkarni 	__le16 word1 /* word1 */;
1356*14b24e2bSVaishali Kulkarni 	__le16 word2 /* word2 */;
1357*14b24e2bSVaishali Kulkarni 	__le16 word3 /* word3 */;
1358*14b24e2bSVaishali Kulkarni 	__le16 word4 /* word4 */;
1359*14b24e2bSVaishali Kulkarni 	__le32 reg2 /* reg2 */;
1360*14b24e2bSVaishali Kulkarni 	__le32 reg3 /* reg3 */;
1361*14b24e2bSVaishali Kulkarni };
1362*14b24e2bSVaishali Kulkarni 
1363*14b24e2bSVaishali Kulkarni 
1364*14b24e2bSVaishali Kulkarni 
1365*14b24e2bSVaishali Kulkarni struct e5_mstorm_rdma_conn_ag_ctx
1366*14b24e2bSVaishali Kulkarni {
1367*14b24e2bSVaishali Kulkarni 	u8 byte0 /* cdu_validation */;
1368*14b24e2bSVaishali Kulkarni 	u8 byte1 /* state_and_core_id */;
1369*14b24e2bSVaishali Kulkarni 	u8 flags0;
1370*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_CONN_AG_CTX_BIT0_MASK     0x1 /* exist_in_qm0 */
1371*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT    0
1372*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_CONN_AG_CTX_BIT1_MASK     0x1 /* exist_in_qm1 */
1373*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT    1
1374*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_CONN_AG_CTX_CF0_MASK      0x3 /* cf0 */
1375*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT     2
1376*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_CONN_AG_CTX_CF1_MASK      0x3 /* cf1 */
1377*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT     4
1378*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_CONN_AG_CTX_CF2_MASK      0x3 /* cf2 */
1379*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT     6
1380*14b24e2bSVaishali Kulkarni 	u8 flags1;
1381*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK    0x1 /* cf0en */
1382*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT   0
1383*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK    0x1 /* cf1en */
1384*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT   1
1385*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK    0x1 /* cf2en */
1386*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT   2
1387*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK  0x1 /* rule0en */
1388*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3
1389*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK  0x1 /* rule1en */
1390*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4
1391*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK  0x1 /* rule2en */
1392*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5
1393*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK  0x1 /* rule3en */
1394*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6
1395*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK  0x1 /* rule4en */
1396*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7
1397*14b24e2bSVaishali Kulkarni 	__le16 word0 /* word0 */;
1398*14b24e2bSVaishali Kulkarni 	__le16 word1 /* word1 */;
1399*14b24e2bSVaishali Kulkarni 	__le32 reg0 /* reg0 */;
1400*14b24e2bSVaishali Kulkarni 	__le32 reg1 /* reg1 */;
1401*14b24e2bSVaishali Kulkarni };
1402*14b24e2bSVaishali Kulkarni 
1403*14b24e2bSVaishali Kulkarni 
1404*14b24e2bSVaishali Kulkarni struct e5_mstorm_rdma_task_ag_ctx
1405*14b24e2bSVaishali Kulkarni {
1406*14b24e2bSVaishali Kulkarni 	u8 reserved /* cdu_validation */;
1407*14b24e2bSVaishali Kulkarni 	u8 byte1 /* state_and_core_id */;
1408*14b24e2bSVaishali Kulkarni 	__le16 icid /* icid */;
1409*14b24e2bSVaishali Kulkarni 	u8 flags0;
1410*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK  0xF /* connection_type */
1411*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
1412*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK     0x1 /* exist_in_qm0 */
1413*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT    4
1414*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK             0x1 /* exist_in_qm1 */
1415*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT            5
1416*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK             0x1 /* bit2 */
1417*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT            6
1418*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_BIT3_MASK             0x1 /* bit3 */
1419*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT            7
1420*14b24e2bSVaishali Kulkarni 	u8 flags1;
1421*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_CF0_MASK              0x3 /* cf0 */
1422*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT             0
1423*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_CF1_MASK              0x3 /* cf1 */
1424*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT             2
1425*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_CF2_MASK              0x3 /* cf2 */
1426*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT             4
1427*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK            0x1 /* cf0en */
1428*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT           6
1429*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK            0x1 /* cf1en */
1430*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT           7
1431*14b24e2bSVaishali Kulkarni 	u8 flags2;
1432*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK            0x1 /* cf2en */
1433*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT           0
1434*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK          0x1 /* rule0en */
1435*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT         1
1436*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK          0x1 /* rule1en */
1437*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT         2
1438*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK          0x1 /* rule2en */
1439*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT         3
1440*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK          0x1 /* rule3en */
1441*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT         4
1442*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK          0x1 /* rule4en */
1443*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT         5
1444*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK          0x1 /* rule5en */
1445*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT         6
1446*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK          0x1 /* rule6en */
1447*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT         7
1448*14b24e2bSVaishali Kulkarni 	u8 flags3;
1449*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_MASK     0x1 /* bit4 */
1450*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_SHIFT    0
1451*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_MASK     0x3 /* cf3 */
1452*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_SHIFT    1
1453*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_MASK     0x3 /* cf4 */
1454*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_SHIFT    3
1455*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_MASK     0x1 /* cf3en */
1456*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_SHIFT    5
1457*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_MASK     0x1 /* cf4en */
1458*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_SHIFT    6
1459*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_MASK     0x1 /* rule7en */
1460*14b24e2bSVaishali Kulkarni #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_SHIFT    7
1461*14b24e2bSVaishali Kulkarni 	__le32 mw_cnt /* reg0 */;
1462*14b24e2bSVaishali Kulkarni 	u8 key /* byte2 */;
1463*14b24e2bSVaishali Kulkarni 	u8 ref_cnt_seq /* byte3 */;
1464*14b24e2bSVaishali Kulkarni 	u8 ctx_upd_seq /* byte4 */;
1465*14b24e2bSVaishali Kulkarni 	u8 e4_reserved7 /* byte5 */;
1466*14b24e2bSVaishali Kulkarni 	__le16 dif_flags /* regpair0 */;
1467*14b24e2bSVaishali Kulkarni 	__le16 tx_ref_count /* word2 */;
1468*14b24e2bSVaishali Kulkarni 	__le16 last_used_ltid /* word3 */;
1469*14b24e2bSVaishali Kulkarni 	__le16 parent_mr_lo /* word4 */;
1470*14b24e2bSVaishali Kulkarni 	__le16 parent_mr_hi /* regpair1 */;
1471*14b24e2bSVaishali Kulkarni 	__le16 e4_reserved8 /* word6 */;
1472*14b24e2bSVaishali Kulkarni 	__le32 fbo_lo /* reg1 */;
1473*14b24e2bSVaishali Kulkarni };
1474*14b24e2bSVaishali Kulkarni 
1475*14b24e2bSVaishali Kulkarni 
1476*14b24e2bSVaishali Kulkarni struct e5_tstorm_rdma_conn_ag_ctx
1477*14b24e2bSVaishali Kulkarni {
1478*14b24e2bSVaishali Kulkarni 	u8 reserved0 /* cdu_validation */;
1479*14b24e2bSVaishali Kulkarni 	u8 byte1 /* state_and_core_id */;
1480*14b24e2bSVaishali Kulkarni 	u8 flags0;
1481*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK          0x1 /* exist_in_qm0 */
1482*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT         0
1483*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT1_MASK                  0x1 /* exist_in_qm1 */
1484*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT                 1
1485*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT2_MASK                  0x1 /* bit2 */
1486*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT                 2
1487*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT3_MASK                  0x1 /* bit3 */
1488*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT3_SHIFT                 3
1489*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT4_MASK                  0x1 /* bit4 */
1490*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT                 4
1491*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT5_MASK                  0x1 /* bit5 */
1492*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT                 5
1493*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_CF0_MASK                   0x3 /* timer0cf */
1494*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT                  6
1495*14b24e2bSVaishali Kulkarni 	u8 flags1;
1496*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_CF1_MASK                   0x3 /* timer1cf */
1497*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT                  0
1498*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_CF2_MASK                   0x3 /* timer2cf */
1499*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT                  2
1500*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK     0x3 /* timer_stop_all */
1501*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT    4
1502*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK           0x3 /* cf4 */
1503*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT          6
1504*14b24e2bSVaishali Kulkarni 	u8 flags2;
1505*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK       0x3 /* cf5 */
1506*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT      0
1507*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_CF6_MASK                   0x3 /* cf6 */
1508*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT                  2
1509*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_CF7_MASK                   0x3 /* cf7 */
1510*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_CF7_SHIFT                  4
1511*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_CF8_MASK                   0x3 /* cf8 */
1512*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT                  6
1513*14b24e2bSVaishali Kulkarni 	u8 flags3;
1514*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_CF9_MASK                   0x3 /* cf9 */
1515*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT                  0
1516*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_CF10_MASK                  0x3 /* cf10 */
1517*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT                 2
1518*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK                 0x1 /* cf0en */
1519*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT                4
1520*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK                 0x1 /* cf1en */
1521*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT                5
1522*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK                 0x1 /* cf2en */
1523*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT                6
1524*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK  0x1 /* cf3en */
1525*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
1526*14b24e2bSVaishali Kulkarni 	u8 flags4;
1527*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK        0x1 /* cf4en */
1528*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT       0
1529*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK    0x1 /* cf5en */
1530*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT   1
1531*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK                 0x1 /* cf6en */
1532*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT                2
1533*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_CF7EN_MASK                 0x1 /* cf7en */
1534*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_CF7EN_SHIFT                3
1535*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK                 0x1 /* cf8en */
1536*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT                4
1537*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK                 0x1 /* cf9en */
1538*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT                5
1539*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK                0x1 /* cf10en */
1540*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT               6
1541*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK               0x1 /* rule0en */
1542*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT              7
1543*14b24e2bSVaishali Kulkarni 	u8 flags5;
1544*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK               0x1 /* rule1en */
1545*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT              0
1546*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK               0x1 /* rule2en */
1547*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT              1
1548*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK               0x1 /* rule3en */
1549*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT              2
1550*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK               0x1 /* rule4en */
1551*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT              3
1552*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK               0x1 /* rule5en */
1553*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT              4
1554*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK               0x1 /* rule6en */
1555*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT              5
1556*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK               0x1 /* rule7en */
1557*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT              6
1558*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK               0x1 /* rule8en */
1559*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT              7
1560*14b24e2bSVaishali Kulkarni 	u8 flags6;
1561*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED1_MASK          0x1 /* bit6 */
1562*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED1_SHIFT         0
1563*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED2_MASK          0x1 /* bit7 */
1564*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED2_SHIFT         1
1565*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED3_MASK          0x1 /* bit8 */
1566*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED3_SHIFT         2
1567*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED4_MASK          0x3 /* cf11 */
1568*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED4_SHIFT         3
1569*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED5_MASK          0x1 /* cf11en */
1570*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED5_SHIFT         5
1571*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED6_MASK          0x1 /* rule9en */
1572*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED6_SHIFT         6
1573*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED7_MASK          0x1 /* rule10en */
1574*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED7_SHIFT         7
1575*14b24e2bSVaishali Kulkarni 	u8 byte2 /* byte2 */;
1576*14b24e2bSVaishali Kulkarni 	__le16 word0 /* word0 */;
1577*14b24e2bSVaishali Kulkarni 	__le32 reg0 /* reg0 */;
1578*14b24e2bSVaishali Kulkarni 	__le32 reg1 /* reg1 */;
1579*14b24e2bSVaishali Kulkarni 	__le32 reg2 /* reg2 */;
1580*14b24e2bSVaishali Kulkarni 	__le32 reg3 /* reg3 */;
1581*14b24e2bSVaishali Kulkarni 	__le32 reg4 /* reg4 */;
1582*14b24e2bSVaishali Kulkarni 	__le32 reg5 /* reg5 */;
1583*14b24e2bSVaishali Kulkarni 	__le32 reg6 /* reg6 */;
1584*14b24e2bSVaishali Kulkarni 	__le32 reg7 /* reg7 */;
1585*14b24e2bSVaishali Kulkarni 	__le32 reg8 /* reg8 */;
1586*14b24e2bSVaishali Kulkarni 	u8 byte3 /* byte3 */;
1587*14b24e2bSVaishali Kulkarni 	u8 byte4 /* byte4 */;
1588*14b24e2bSVaishali Kulkarni 	u8 byte5 /* byte5 */;
1589*14b24e2bSVaishali Kulkarni 	u8 e4_reserved8 /* byte6 */;
1590*14b24e2bSVaishali Kulkarni 	__le16 word1 /* word1 */;
1591*14b24e2bSVaishali Kulkarni 	__le16 word2 /* conn_dpi */;
1592*14b24e2bSVaishali Kulkarni 	__le32 reg9 /* reg9 */;
1593*14b24e2bSVaishali Kulkarni 	__le16 word3 /* word3 */;
1594*14b24e2bSVaishali Kulkarni 	__le16 e4_reserved9 /* word4 */;
1595*14b24e2bSVaishali Kulkarni };
1596*14b24e2bSVaishali Kulkarni 
1597*14b24e2bSVaishali Kulkarni 
1598*14b24e2bSVaishali Kulkarni struct e5_tstorm_rdma_task_ag_ctx
1599*14b24e2bSVaishali Kulkarni {
1600*14b24e2bSVaishali Kulkarni 	u8 byte0 /* cdu_validation */;
1601*14b24e2bSVaishali Kulkarni 	u8 byte1 /* state_and_core_id */;
1602*14b24e2bSVaishali Kulkarni 	__le16 word0 /* icid */;
1603*14b24e2bSVaishali Kulkarni 	u8 flags0;
1604*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK  0xF /* connection_type */
1605*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT 0
1606*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK     0x1 /* exist_in_qm0 */
1607*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT    4
1608*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK     0x1 /* exist_in_qm1 */
1609*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT    5
1610*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK     0x1 /* bit2 */
1611*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT    6
1612*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK     0x1 /* bit3 */
1613*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT    7
1614*14b24e2bSVaishali Kulkarni 	u8 flags1;
1615*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK     0x1 /* bit4 */
1616*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT    0
1617*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK     0x1 /* bit5 */
1618*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT    1
1619*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_CF0_MASK      0x3 /* timer0cf */
1620*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT     2
1621*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_CF1_MASK      0x3 /* timer1cf */
1622*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT     4
1623*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_CF2_MASK      0x3 /* timer2cf */
1624*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT     6
1625*14b24e2bSVaishali Kulkarni 	u8 flags2;
1626*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_CF3_MASK      0x3 /* timer_stop_all */
1627*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT     0
1628*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_CF4_MASK      0x3 /* cf4 */
1629*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT     2
1630*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_CF5_MASK      0x3 /* cf5 */
1631*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT     4
1632*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_CF6_MASK      0x3 /* cf6 */
1633*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT     6
1634*14b24e2bSVaishali Kulkarni 	u8 flags3;
1635*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_CF7_MASK      0x3 /* cf7 */
1636*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT     0
1637*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK    0x1 /* cf0en */
1638*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT   2
1639*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK    0x1 /* cf1en */
1640*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT   3
1641*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK    0x1 /* cf2en */
1642*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT   4
1643*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK    0x1 /* cf3en */
1644*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT   5
1645*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK    0x1 /* cf4en */
1646*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT   6
1647*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK    0x1 /* cf5en */
1648*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT   7
1649*14b24e2bSVaishali Kulkarni 	u8 flags4;
1650*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK    0x1 /* cf6en */
1651*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT   0
1652*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK    0x1 /* cf7en */
1653*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT   1
1654*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK  0x1 /* rule0en */
1655*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 2
1656*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK  0x1 /* rule1en */
1657*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 3
1658*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK  0x1 /* rule2en */
1659*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 4
1660*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK  0x1 /* rule3en */
1661*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 5
1662*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK  0x1 /* rule4en */
1663*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 6
1664*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK  0x1 /* rule5en */
1665*14b24e2bSVaishali Kulkarni #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 7
1666*14b24e2bSVaishali Kulkarni 	u8 byte2 /* byte2 */;
1667*14b24e2bSVaishali Kulkarni 	__le16 word1 /* word1 */;
1668*14b24e2bSVaishali Kulkarni 	__le32 reg0 /* reg0 */;
1669*14b24e2bSVaishali Kulkarni 	u8 byte3 /* regpair0 */;
1670*14b24e2bSVaishali Kulkarni 	u8 byte4 /* byte4 */;
1671*14b24e2bSVaishali Kulkarni 	__le16 word2 /* word2 */;
1672*14b24e2bSVaishali Kulkarni 	__le16 word3 /* word3 */;
1673*14b24e2bSVaishali Kulkarni 	__le16 word4 /* word4 */;
1674*14b24e2bSVaishali Kulkarni 	__le32 reg1 /* regpair1 */;
1675*14b24e2bSVaishali Kulkarni 	__le32 reg2 /* reg2 */;
1676*14b24e2bSVaishali Kulkarni };
1677*14b24e2bSVaishali Kulkarni 
1678*14b24e2bSVaishali Kulkarni 
1679*14b24e2bSVaishali Kulkarni struct e5_ustorm_rdma_conn_ag_ctx
1680*14b24e2bSVaishali Kulkarni {
1681*14b24e2bSVaishali Kulkarni 	u8 reserved /* cdu_validation */;
1682*14b24e2bSVaishali Kulkarni 	u8 byte1 /* state_and_core_id */;
1683*14b24e2bSVaishali Kulkarni 	u8 flags0;
1684*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK     0x1 /* exist_in_qm0 */
1685*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT    0
1686*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_BIT1_MASK             0x1 /* exist_in_qm1 */
1687*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT            1
1688*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK      0x3 /* timer0cf */
1689*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT     2
1690*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_CF1_MASK              0x3 /* timer1cf */
1691*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT             4
1692*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_CF2_MASK              0x3 /* timer2cf */
1693*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT             6
1694*14b24e2bSVaishali Kulkarni 	u8 flags1;
1695*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_CF3_MASK              0x3 /* timer_stop_all */
1696*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT             0
1697*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK     0x3 /* cf4 */
1698*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT    2
1699*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK        0x3 /* cf5 */
1700*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT       4
1701*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_CF6_MASK              0x3 /* cf6 */
1702*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT             6
1703*14b24e2bSVaishali Kulkarni 	u8 flags2;
1704*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK   0x1 /* cf0en */
1705*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT  0
1706*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK            0x1 /* cf1en */
1707*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT           1
1708*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK            0x1 /* cf2en */
1709*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT           2
1710*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK            0x1 /* cf3en */
1711*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT           3
1712*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK  0x1 /* cf4en */
1713*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4
1714*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK     0x1 /* cf5en */
1715*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT    5
1716*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK            0x1 /* cf6en */
1717*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT           6
1718*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK         0x1 /* rule0en */
1719*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT        7
1720*14b24e2bSVaishali Kulkarni 	u8 flags3;
1721*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK            0x1 /* rule1en */
1722*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT           0
1723*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK          0x1 /* rule2en */
1724*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT         1
1725*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK          0x1 /* rule3en */
1726*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT         2
1727*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK          0x1 /* rule4en */
1728*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT         3
1729*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK          0x1 /* rule5en */
1730*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT         4
1731*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK          0x1 /* rule6en */
1732*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT         5
1733*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK          0x1 /* rule7en */
1734*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT         6
1735*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK          0x1 /* rule8en */
1736*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT         7
1737*14b24e2bSVaishali Kulkarni 	u8 flags4;
1738*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED1_MASK     0x1 /* bit2 */
1739*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED1_SHIFT    0
1740*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED2_MASK     0x1 /* bit3 */
1741*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED2_SHIFT    1
1742*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED3_MASK     0x3 /* cf7 */
1743*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED3_SHIFT    2
1744*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED4_MASK     0x3 /* cf8 */
1745*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED4_SHIFT    4
1746*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED5_MASK     0x1 /* cf7en */
1747*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED5_SHIFT    6
1748*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED6_MASK     0x1 /* cf8en */
1749*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED6_SHIFT    7
1750*14b24e2bSVaishali Kulkarni 	u8 byte2 /* byte2 */;
1751*14b24e2bSVaishali Kulkarni 	__le16 conn_dpi /* conn_dpi */;
1752*14b24e2bSVaishali Kulkarni 	__le16 word1 /* word1 */;
1753*14b24e2bSVaishali Kulkarni 	__le32 cq_cons /* reg0 */;
1754*14b24e2bSVaishali Kulkarni 	__le32 cq_se_prod /* reg1 */;
1755*14b24e2bSVaishali Kulkarni 	__le32 cq_prod /* reg2 */;
1756*14b24e2bSVaishali Kulkarni 	__le32 reg3 /* reg3 */;
1757*14b24e2bSVaishali Kulkarni 	__le16 int_timeout /* word2 */;
1758*14b24e2bSVaishali Kulkarni 	__le16 word3 /* word3 */;
1759*14b24e2bSVaishali Kulkarni };
1760*14b24e2bSVaishali Kulkarni 
1761*14b24e2bSVaishali Kulkarni 
1762*14b24e2bSVaishali Kulkarni struct e5_ustorm_rdma_task_ag_ctx
1763*14b24e2bSVaishali Kulkarni {
1764*14b24e2bSVaishali Kulkarni 	u8 reserved /* cdu_validation */;
1765*14b24e2bSVaishali Kulkarni 	u8 byte1 /* state_and_core_id */;
1766*14b24e2bSVaishali Kulkarni 	__le16 icid /* icid */;
1767*14b24e2bSVaishali Kulkarni 	u8 flags0;
1768*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK         0xF /* connection_type */
1769*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT        0
1770*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK            0x1 /* exist_in_qm0 */
1771*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT           4
1772*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_MASK          0x1 /* exist_in_qm1 */
1773*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_SHIFT         5
1774*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK     0x3 /* timer0cf */
1775*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT    6
1776*14b24e2bSVaishali Kulkarni 	u8 flags1;
1777*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK   0x3 /* timer1cf */
1778*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT  0
1779*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK           0x3 /* timer2cf */
1780*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT          2
1781*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_CF3_MASK                     0x3 /* timer_stop_all */
1782*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_CF3_SHIFT                    4
1783*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK            0x3 /* dif_error_cf */
1784*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT           6
1785*14b24e2bSVaishali Kulkarni 	u8 flags2;
1786*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK  0x1 /* cf0en */
1787*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0
1788*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK               0x1 /* cf1en */
1789*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT              1
1790*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK               0x1 /* cf2en */
1791*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT              2
1792*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_CF3EN_MASK                   0x1 /* cf3en */
1793*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT                  3
1794*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK         0x1 /* cf4en */
1795*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT        4
1796*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK                 0x1 /* rule0en */
1797*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT                5
1798*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK                 0x1 /* rule1en */
1799*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT                6
1800*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK                 0x1 /* rule2en */
1801*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT                7
1802*14b24e2bSVaishali Kulkarni 	u8 flags3;
1803*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK                 0x1 /* rule3en */
1804*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT                0
1805*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK                 0x1 /* rule4en */
1806*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT                1
1807*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK                 0x1 /* rule5en */
1808*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT                2
1809*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK                 0x1 /* rule6en */
1810*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT                3
1811*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_MASK            0x1 /* bit2 */
1812*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_SHIFT           4
1813*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_MASK            0x1 /* bit3 */
1814*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_SHIFT           5
1815*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_MASK            0x1 /* bit4 */
1816*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_SHIFT           6
1817*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_MASK            0x1 /* rule7en */
1818*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_SHIFT           7
1819*14b24e2bSVaishali Kulkarni 	u8 flags4;
1820*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_MASK            0x3 /* cf5 */
1821*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_SHIFT           0
1822*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_MASK            0x1 /* cf5en */
1823*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_SHIFT           2
1824*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED7_MASK            0x1 /* rule8en */
1825*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED7_SHIFT           3
1826*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK          0xF /* dif_error_type */
1827*14b24e2bSVaishali Kulkarni #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT         4
1828*14b24e2bSVaishali Kulkarni 	u8 byte2 /* byte2 */;
1829*14b24e2bSVaishali Kulkarni 	u8 byte3 /* byte3 */;
1830*14b24e2bSVaishali Kulkarni 	u8 e4_reserved8 /* byte4 */;
1831*14b24e2bSVaishali Kulkarni 	__le32 dif_err_intervals /* dif_err_intervals */;
1832*14b24e2bSVaishali Kulkarni 	__le32 dif_error_1st_interval /* dif_error_1st_interval */;
1833*14b24e2bSVaishali Kulkarni 	__le32 reg2 /* reg2 */;
1834*14b24e2bSVaishali Kulkarni 	__le32 dif_runt_value /* reg3 */;
1835*14b24e2bSVaishali Kulkarni 	__le32 reg4 /* reg4 */;
1836*14b24e2bSVaishali Kulkarni };
1837*14b24e2bSVaishali Kulkarni 
1838*14b24e2bSVaishali Kulkarni 
1839*14b24e2bSVaishali Kulkarni struct e5_xstorm_rdma_conn_ag_ctx
1840*14b24e2bSVaishali Kulkarni {
1841*14b24e2bSVaishali Kulkarni 	u8 reserved0 /* cdu_validation */;
1842*14b24e2bSVaishali Kulkarni 	u8 state_and_core_id /* state_and_core_id */;
1843*14b24e2bSVaishali Kulkarni 	u8 flags0;
1844*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK      0x1 /* exist_in_qm0 */
1845*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT     0
1846*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT1_MASK              0x1 /* exist_in_qm1 */
1847*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT             1
1848*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT2_MASK              0x1 /* exist_in_qm2 */
1849*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT             2
1850*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_MASK      0x1 /* exist_in_qm3 */
1851*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_SHIFT     3
1852*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT4_MASK              0x1 /* bit4 */
1853*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT             4
1854*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT5_MASK              0x1 /* cf_array_active */
1855*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT             5
1856*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT6_MASK              0x1 /* bit6 */
1857*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT6_SHIFT             6
1858*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT7_MASK              0x1 /* bit7 */
1859*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT7_SHIFT             7
1860*14b24e2bSVaishali Kulkarni 	u8 flags1;
1861*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT8_MASK              0x1 /* bit8 */
1862*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT8_SHIFT             0
1863*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT9_MASK              0x1 /* bit9 */
1864*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT9_SHIFT             1
1865*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT10_MASK             0x1 /* bit10 */
1866*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT10_SHIFT            2
1867*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT11_MASK             0x1 /* bit11 */
1868*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT11_SHIFT            3
1869*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT12_MASK             0x1 /* bit12 */
1870*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT12_SHIFT            4
1871*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT13_MASK             0x1 /* bit13 */
1872*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT13_SHIFT            5
1873*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT14_MASK             0x1 /* bit14 */
1874*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT14_SHIFT            6
1875*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_MASK      0x1 /* bit15 */
1876*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_SHIFT     7
1877*14b24e2bSVaishali Kulkarni 	u8 flags2;
1878*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF0_MASK               0x3 /* timer0cf */
1879*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT              0
1880*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF1_MASK               0x3 /* timer1cf */
1881*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT              2
1882*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF2_MASK               0x3 /* timer2cf */
1883*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT              4
1884*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF3_MASK               0x3 /* timer_stop_all */
1885*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF3_SHIFT              6
1886*14b24e2bSVaishali Kulkarni 	u8 flags3;
1887*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF4_MASK               0x3 /* cf4 */
1888*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF4_SHIFT              0
1889*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF5_MASK               0x3 /* cf5 */
1890*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF5_SHIFT              2
1891*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF6_MASK               0x3 /* cf6 */
1892*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT              4
1893*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK       0x3 /* cf7 */
1894*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT      6
1895*14b24e2bSVaishali Kulkarni 	u8 flags4;
1896*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF8_MASK               0x3 /* cf8 */
1897*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT              0
1898*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF9_MASK               0x3 /* cf9 */
1899*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT              2
1900*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF10_MASK              0x3 /* cf10 */
1901*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT             4
1902*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF11_MASK              0x3 /* cf11 */
1903*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF11_SHIFT             6
1904*14b24e2bSVaishali Kulkarni 	u8 flags5;
1905*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF12_MASK              0x3 /* cf12 */
1906*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF12_SHIFT             0
1907*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF13_MASK              0x3 /* cf13 */
1908*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF13_SHIFT             2
1909*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF14_MASK              0x3 /* cf14 */
1910*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF14_SHIFT             4
1911*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF15_MASK              0x3 /* cf15 */
1912*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF15_SHIFT             6
1913*14b24e2bSVaishali Kulkarni 	u8 flags6;
1914*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF16_MASK              0x3 /* cf16 */
1915*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF16_SHIFT             0
1916*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF17_MASK              0x3 /* cf_array_cf */
1917*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF17_SHIFT             2
1918*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF18_MASK              0x3 /* cf18 */
1919*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF18_SHIFT             4
1920*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF19_MASK              0x3 /* cf19 */
1921*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF19_SHIFT             6
1922*14b24e2bSVaishali Kulkarni 	u8 flags7;
1923*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF20_MASK              0x3 /* cf20 */
1924*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF20_SHIFT             0
1925*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF21_MASK              0x3 /* cf21 */
1926*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF21_SHIFT             2
1927*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_MASK         0x3 /* cf22 */
1928*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_SHIFT        4
1929*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK             0x1 /* cf0en */
1930*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT            6
1931*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK             0x1 /* cf1en */
1932*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT            7
1933*14b24e2bSVaishali Kulkarni 	u8 flags8;
1934*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK             0x1 /* cf2en */
1935*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT            0
1936*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF3EN_MASK             0x1 /* cf3en */
1937*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT            1
1938*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF4EN_MASK             0x1 /* cf4en */
1939*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF4EN_SHIFT            2
1940*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF5EN_MASK             0x1 /* cf5en */
1941*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF5EN_SHIFT            3
1942*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK             0x1 /* cf6en */
1943*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT            4
1944*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK    0x1 /* cf7en */
1945*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT   5
1946*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK             0x1 /* cf8en */
1947*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT            6
1948*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK             0x1 /* cf9en */
1949*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT            7
1950*14b24e2bSVaishali Kulkarni 	u8 flags9;
1951*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK            0x1 /* cf10en */
1952*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT           0
1953*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF11EN_MASK            0x1 /* cf11en */
1954*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF11EN_SHIFT           1
1955*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF12EN_MASK            0x1 /* cf12en */
1956*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF12EN_SHIFT           2
1957*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF13EN_MASK            0x1 /* cf13en */
1958*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF13EN_SHIFT           3
1959*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF14EN_MASK            0x1 /* cf14en */
1960*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF14EN_SHIFT           4
1961*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF15EN_MASK            0x1 /* cf15en */
1962*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF15EN_SHIFT           5
1963*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF16EN_MASK            0x1 /* cf16en */
1964*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF16EN_SHIFT           6
1965*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF17EN_MASK            0x1 /* cf_array_cf_en */
1966*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF17EN_SHIFT           7
1967*14b24e2bSVaishali Kulkarni 	u8 flags10;
1968*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF18EN_MASK            0x1 /* cf18en */
1969*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF18EN_SHIFT           0
1970*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF19EN_MASK            0x1 /* cf19en */
1971*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF19EN_SHIFT           1
1972*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF20EN_MASK            0x1 /* cf20en */
1973*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF20EN_SHIFT           2
1974*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF21EN_MASK            0x1 /* cf21en */
1975*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF21EN_SHIFT           3
1976*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_MASK      0x1 /* cf22en */
1977*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_SHIFT     4
1978*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF23EN_MASK            0x1 /* cf23en */
1979*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF23EN_SHIFT           5
1980*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK           0x1 /* rule0en */
1981*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT          6
1982*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK           0x1 /* rule1en */
1983*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT          7
1984*14b24e2bSVaishali Kulkarni 	u8 flags11;
1985*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK           0x1 /* rule2en */
1986*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT          0
1987*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK           0x1 /* rule3en */
1988*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT          1
1989*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK           0x1 /* rule4en */
1990*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT          2
1991*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK           0x1 /* rule5en */
1992*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT          3
1993*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK           0x1 /* rule6en */
1994*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT          4
1995*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK           0x1 /* rule7en */
1996*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT          5
1997*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_MASK      0x1 /* rule8en */
1998*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_SHIFT     6
1999*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE9EN_MASK           0x1 /* rule9en */
2000*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE9EN_SHIFT          7
2001*14b24e2bSVaishali Kulkarni 	u8 flags12;
2002*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE10EN_MASK          0x1 /* rule10en */
2003*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE10EN_SHIFT         0
2004*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE11EN_MASK          0x1 /* rule11en */
2005*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE11EN_SHIFT         1
2006*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_MASK      0x1 /* rule12en */
2007*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_SHIFT     2
2008*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_MASK      0x1 /* rule13en */
2009*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_SHIFT     3
2010*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE14EN_MASK          0x1 /* rule14en */
2011*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE14EN_SHIFT         4
2012*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE15EN_MASK          0x1 /* rule15en */
2013*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE15EN_SHIFT         5
2014*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE16EN_MASK          0x1 /* rule16en */
2015*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE16EN_SHIFT         6
2016*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE17EN_MASK          0x1 /* rule17en */
2017*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE17EN_SHIFT         7
2018*14b24e2bSVaishali Kulkarni 	u8 flags13;
2019*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE18EN_MASK          0x1 /* rule18en */
2020*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE18EN_SHIFT         0
2021*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE19EN_MASK          0x1 /* rule19en */
2022*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE19EN_SHIFT         1
2023*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_MASK      0x1 /* rule20en */
2024*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_SHIFT     2
2025*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_MASK      0x1 /* rule21en */
2026*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_SHIFT     3
2027*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_MASK      0x1 /* rule22en */
2028*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_SHIFT     4
2029*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_MASK      0x1 /* rule23en */
2030*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_SHIFT     5
2031*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_MASK      0x1 /* rule24en */
2032*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_SHIFT     6
2033*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_MASK      0x1 /* rule25en */
2034*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_SHIFT     7
2035*14b24e2bSVaishali Kulkarni 	u8 flags14;
2036*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_MIGRATION_MASK         0x1 /* bit16 */
2037*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_MIGRATION_SHIFT        0
2038*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT17_MASK             0x1 /* bit17 */
2039*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT17_SHIFT            1
2040*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_MASK      0x3 /* bit18 */
2041*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_SHIFT     2
2042*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_RESERVED_MASK          0x1 /* bit20 */
2043*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_RESERVED_SHIFT         4
2044*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK  0x1 /* bit21 */
2045*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
2046*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF23_MASK              0x3 /* cf23 */
2047*14b24e2bSVaishali Kulkarni #define E5_XSTORM_RDMA_CONN_AG_CTX_CF23_SHIFT             6
2048*14b24e2bSVaishali Kulkarni 	u8 byte2 /* byte2 */;
2049*14b24e2bSVaishali Kulkarni 	__le16 physical_q0 /* physical_q0 */;
2050*14b24e2bSVaishali Kulkarni 	__le16 word1 /* physical_q1 */;
2051*14b24e2bSVaishali Kulkarni 	__le16 word2 /* physical_q2 */;
2052*14b24e2bSVaishali Kulkarni 	__le16 word3 /* word3 */;
2053*14b24e2bSVaishali Kulkarni 	__le16 word4 /* word4 */;
2054*14b24e2bSVaishali Kulkarni 	__le16 word5 /* word5 */;
2055*14b24e2bSVaishali Kulkarni 	__le16 conn_dpi /* conn_dpi */;
2056*14b24e2bSVaishali Kulkarni 	u8 byte3 /* byte3 */;
2057*14b24e2bSVaishali Kulkarni 	u8 byte4 /* byte4 */;
2058*14b24e2bSVaishali Kulkarni 	u8 byte5 /* byte5 */;
2059*14b24e2bSVaishali Kulkarni 	u8 byte6 /* byte6 */;
2060*14b24e2bSVaishali Kulkarni 	__le32 reg0 /* reg0 */;
2061*14b24e2bSVaishali Kulkarni 	__le32 reg1 /* reg1 */;
2062*14b24e2bSVaishali Kulkarni 	__le32 reg2 /* reg2 */;
2063*14b24e2bSVaishali Kulkarni 	__le32 snd_nxt_psn /* reg3 */;
2064*14b24e2bSVaishali Kulkarni 	__le32 reg4 /* reg4 */;
2065*14b24e2bSVaishali Kulkarni 	__le32 reg5 /* cf_array0 */;
2066*14b24e2bSVaishali Kulkarni 	__le32 reg6 /* cf_array1 */;
2067*14b24e2bSVaishali Kulkarni };
2068*14b24e2bSVaishali Kulkarni 
2069*14b24e2bSVaishali Kulkarni 
2070*14b24e2bSVaishali Kulkarni struct e5_ystorm_rdma_conn_ag_ctx
2071*14b24e2bSVaishali Kulkarni {
2072*14b24e2bSVaishali Kulkarni 	u8 byte0 /* cdu_validation */;
2073*14b24e2bSVaishali Kulkarni 	u8 byte1 /* state_and_core_id */;
2074*14b24e2bSVaishali Kulkarni 	u8 flags0;
2075*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_CONN_AG_CTX_BIT0_MASK     0x1 /* exist_in_qm0 */
2076*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT    0
2077*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_CONN_AG_CTX_BIT1_MASK     0x1 /* exist_in_qm1 */
2078*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT    1
2079*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_CONN_AG_CTX_CF0_MASK      0x3 /* cf0 */
2080*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT     2
2081*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_CONN_AG_CTX_CF1_MASK      0x3 /* cf1 */
2082*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT     4
2083*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_CONN_AG_CTX_CF2_MASK      0x3 /* cf2 */
2084*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT     6
2085*14b24e2bSVaishali Kulkarni 	u8 flags1;
2086*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK    0x1 /* cf0en */
2087*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT   0
2088*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK    0x1 /* cf1en */
2089*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT   1
2090*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK    0x1 /* cf2en */
2091*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT   2
2092*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK  0x1 /* rule0en */
2093*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3
2094*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK  0x1 /* rule1en */
2095*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4
2096*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK  0x1 /* rule2en */
2097*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5
2098*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK  0x1 /* rule3en */
2099*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6
2100*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK  0x1 /* rule4en */
2101*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7
2102*14b24e2bSVaishali Kulkarni 	u8 byte2 /* byte2 */;
2103*14b24e2bSVaishali Kulkarni 	u8 byte3 /* byte3 */;
2104*14b24e2bSVaishali Kulkarni 	__le16 word0 /* word0 */;
2105*14b24e2bSVaishali Kulkarni 	__le32 reg0 /* reg0 */;
2106*14b24e2bSVaishali Kulkarni 	__le32 reg1 /* reg1 */;
2107*14b24e2bSVaishali Kulkarni 	__le16 word1 /* word1 */;
2108*14b24e2bSVaishali Kulkarni 	__le16 word2 /* word2 */;
2109*14b24e2bSVaishali Kulkarni 	__le16 word3 /* word3 */;
2110*14b24e2bSVaishali Kulkarni 	__le16 word4 /* word4 */;
2111*14b24e2bSVaishali Kulkarni 	__le32 reg2 /* reg2 */;
2112*14b24e2bSVaishali Kulkarni 	__le32 reg3 /* reg3 */;
2113*14b24e2bSVaishali Kulkarni };
2114*14b24e2bSVaishali Kulkarni 
2115*14b24e2bSVaishali Kulkarni 
2116*14b24e2bSVaishali Kulkarni struct e5_ystorm_rdma_task_ag_ctx
2117*14b24e2bSVaishali Kulkarni {
2118*14b24e2bSVaishali Kulkarni 	u8 reserved /* cdu_validation */;
2119*14b24e2bSVaishali Kulkarni 	u8 byte1 /* state_and_core_id */;
2120*14b24e2bSVaishali Kulkarni 	__le16 msem_ctx_upd_seq /* icid */;
2121*14b24e2bSVaishali Kulkarni 	u8 flags0;
2122*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK  0xF /* connection_type */
2123*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
2124*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK     0x1 /* exist_in_qm0 */
2125*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT    4
2126*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK             0x1 /* exist_in_qm1 */
2127*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT            5
2128*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_VALID_MASK            0x1 /* bit2 */
2129*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT           6
2130*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_BIT3_MASK             0x1 /* bit3 */
2131*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT            7
2132*14b24e2bSVaishali Kulkarni 	u8 flags1;
2133*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_CF0_MASK              0x3 /* cf0 */
2134*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT             0
2135*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_CF1_MASK              0x3 /* cf1 */
2136*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT             2
2137*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK       0x3 /* cf2special */
2138*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT      4
2139*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK            0x1 /* cf0en */
2140*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT           6
2141*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK            0x1 /* cf1en */
2142*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT           7
2143*14b24e2bSVaishali Kulkarni 	u8 flags2;
2144*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK             0x1 /* bit4 */
2145*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT            0
2146*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK          0x1 /* rule0en */
2147*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT         1
2148*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK          0x1 /* rule1en */
2149*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT         2
2150*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK          0x1 /* rule2en */
2151*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT         3
2152*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK          0x1 /* rule3en */
2153*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT         4
2154*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK          0x1 /* rule4en */
2155*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT         5
2156*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK          0x1 /* rule5en */
2157*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT         6
2158*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK          0x1 /* rule6en */
2159*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT         7
2160*14b24e2bSVaishali Kulkarni 	u8 flags3;
2161*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_MASK     0x1 /* bit5 */
2162*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_SHIFT    0
2163*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_MASK     0x3 /* cf3 */
2164*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_SHIFT    1
2165*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_MASK     0x3 /* cf4 */
2166*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_SHIFT    3
2167*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_MASK     0x1 /* cf3en */
2168*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_SHIFT    5
2169*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_MASK     0x1 /* cf4en */
2170*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_SHIFT    6
2171*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_MASK     0x1 /* rule7en */
2172*14b24e2bSVaishali Kulkarni #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_SHIFT    7
2173*14b24e2bSVaishali Kulkarni 	__le32 mw_cnt /* reg0 */;
2174*14b24e2bSVaishali Kulkarni 	u8 key /* byte2 */;
2175*14b24e2bSVaishali Kulkarni 	u8 ref_cnt_seq /* byte3 */;
2176*14b24e2bSVaishali Kulkarni 	u8 ctx_upd_seq /* byte4 */;
2177*14b24e2bSVaishali Kulkarni 	u8 e4_reserved7 /* byte5 */;
2178*14b24e2bSVaishali Kulkarni 	__le16 dif_flags /* word1 */;
2179*14b24e2bSVaishali Kulkarni 	__le16 tx_ref_count /* word2 */;
2180*14b24e2bSVaishali Kulkarni 	__le16 last_used_ltid /* word3 */;
2181*14b24e2bSVaishali Kulkarni 	__le16 parent_mr_lo /* word4 */;
2182*14b24e2bSVaishali Kulkarni 	__le16 parent_mr_hi /* word5 */;
2183*14b24e2bSVaishali Kulkarni 	__le16 e4_reserved8 /* word6 */;
2184*14b24e2bSVaishali Kulkarni 	__le32 fbo_lo /* reg1 */;
2185*14b24e2bSVaishali Kulkarni };
2186*14b24e2bSVaishali Kulkarni 
2187*14b24e2bSVaishali Kulkarni #endif /* __ECORE_HSI_RDMA__ */
2188