xref: /illumos-gate/usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_hsi_rdma.h (revision 14b24e2b)

/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, v.1,  (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* or http://opensource.org/licenses/CDDL-1.0.
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/

/*
* Copyright 2014-2017 Cavium, Inc.
* The contents of this file are subject to the terms of the Common Development
* and Distribution License, v.1,  (the "License").

* You may not use this file except in compliance with the License.

* You can obtain a copy of the License at available
* at http://opensource.org/licenses/CDDL-1.0

* See the License for the specific language governing permissions and
* limitations under the License.
*/

#ifndef __ECORE_HSI_RDMA__
#define __ECORE_HSI_RDMA__
/************************************************************************/
/* Add include to common rdma target for both eCore and protocol rdma driver */
/************************************************************************/
#include "rdma_common.h"

/*
 * The roce task context of Mstorm
 */
struct mstorm_rdma_task_st_ctx
{
	struct regpair temp[4];
};


/*
 * rdma function init ramrod data
 */
struct rdma_close_func_ramrod_data
{
	u8 cnq_start_offset;
	u8 num_cnqs;
	u8 vf_id /* This field should be assigned to Virtual Function ID if vf_valid == 1. Otherwise its dont care */;
	u8 vf_valid;
	u8 reserved[4];
};


/*
 * rdma function init CNQ parameters
 */
struct rdma_cnq_params
{
	__le16 sb_num /* Status block number used by the queue */;
	u8 sb_index /* Status block index used by the queue */;
	u8 num_pbl_pages /* Number of pages in the PBL allocated for this queue */;
	__le32 reserved;
	struct regpair pbl_base_addr /* Address to the first entry of the queue PBL */;
	__le16 queue_zone_num /* Queue Zone ID used for CNQ consumer update */;
	u8 reserved1[6];
};


/*
 * rdma create cq ramrod data
 */
struct rdma_create_cq_ramrod_data
{
	struct regpair cq_handle;
	struct regpair pbl_addr;
	__le32 max_cqes;
	__le16 pbl_num_pages;
	__le16 dpi;
	u8 is_two_level_pbl;
	u8 cnq_id;
	u8 pbl_log_page_size;
	u8 toggle_bit;
	__le16 int_timeout /* Timeout used for interrupt moderation */;
	__le16 reserved1;
};


/*
 * rdma deregister tid ramrod data
 */
struct rdma_deregister_tid_ramrod_data
{
	__le32 itid;
	__le32 reserved;
};


/*
 * rdma destroy cq output params
 */
struct rdma_destroy_cq_output_params
{
	__le16 cnq_num /* Sequence number of completion notification sent for the cq on the associated CNQ */;
	__le16 reserved0;
	__le32 reserved1;
};


/*
 * rdma destroy cq ramrod data
 */
struct rdma_destroy_cq_ramrod_data
{
	struct regpair output_params_addr;
};


/*
 * RDMA slow path EQ cmd IDs
 */
enum rdma_event_opcode
{
	RDMA_EVENT_UNUSED,
	RDMA_EVENT_FUNC_INIT,
	RDMA_EVENT_FUNC_CLOSE,
	RDMA_EVENT_REGISTER_MR,
	RDMA_EVENT_DEREGISTER_MR,
	RDMA_EVENT_CREATE_CQ,
	RDMA_EVENT_RESIZE_CQ,
	RDMA_EVENT_DESTROY_CQ,
	RDMA_EVENT_CREATE_SRQ,
	RDMA_EVENT_MODIFY_SRQ,
	RDMA_EVENT_DESTROY_SRQ,
	MAX_RDMA_EVENT_OPCODE
};


/*
 * RDMA FW return code for slow path ramrods
 */
enum rdma_fw_return_code
{
	RDMA_RETURN_OK=0,
	RDMA_RETURN_REGISTER_MR_BAD_STATE_ERR,
	RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR,
	RDMA_RETURN_RESIZE_CQ_ERR,
	RDMA_RETURN_NIG_DRAIN_REQ,
	MAX_RDMA_FW_RETURN_CODE
};


/*
 * rdma function init header
 */
struct rdma_init_func_hdr
{
	u8 cnq_start_offset /* First RDMA CNQ */;
	u8 num_cnqs /* Number of CNQs */;
	u8 cq_ring_mode /* 0 for 32 bit cq producer and consumer counters and 1 for 16 bit */;
	u8 vf_id /* This field should be assigned to Virtual Function ID if vf_valid == 1. Otherwise its dont care */;
	u8 vf_valid;
	u8 reserved[3];
};


/*
 * rdma function init ramrod data
 */
struct rdma_init_func_ramrod_data
{
	struct rdma_init_func_hdr params_header;
	struct rdma_cnq_params cnq_params[NUM_OF_GLOBAL_QUEUES];
};


/*
 * RDMA ramrod command IDs
 */
enum rdma_ramrod_cmd_id
{
	RDMA_RAMROD_UNUSED,
	RDMA_RAMROD_FUNC_INIT,
	RDMA_RAMROD_FUNC_CLOSE,
	RDMA_RAMROD_REGISTER_MR,
	RDMA_RAMROD_DEREGISTER_MR,
	RDMA_RAMROD_CREATE_CQ,
	RDMA_RAMROD_RESIZE_CQ,
	RDMA_RAMROD_DESTROY_CQ,
	RDMA_RAMROD_CREATE_SRQ,
	RDMA_RAMROD_MODIFY_SRQ,
	RDMA_RAMROD_DESTROY_SRQ,
	MAX_RDMA_RAMROD_CMD_ID
};


/*
 * rdma register tid ramrod data
 */
struct rdma_register_tid_ramrod_data
{
	__le32 flags;
#define RDMA_REGISTER_TID_RAMROD_DATA_MAX_ID_MASK             0x3FFFF
#define RDMA_REGISTER_TID_RAMROD_DATA_MAX_ID_SHIFT            0
#define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_MASK      0x1F
#define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_SHIFT     18
#define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_MASK      0x1
#define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_SHIFT     23
#define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_MASK         0x1
#define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_SHIFT        24
#define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_MASK             0x1
#define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_SHIFT            25
#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_MASK        0x1
#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_SHIFT       26
#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_MASK       0x1
#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_SHIFT      27
#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_MASK      0x1
#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_SHIFT     28
#define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_MASK        0x1
#define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_SHIFT       29
#define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_MASK         0x1
#define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_SHIFT        30
#define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_MASK     0x1
#define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_SHIFT    31
	u8 flags1;
#define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_MASK  0x1F
#define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_SHIFT 0
#define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_MASK           0x7
#define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_SHIFT          5
	u8 flags2;
#define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_MASK             0x1 /* Bit indicating that this MR is DMA_MR meaning SGEs that use it have the physical address on them */
#define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_SHIFT            0
#define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_MASK    0x1 /* Bit indicating that this MR has DIF protection enabled. */
#define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_SHIFT   1
#define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_MASK          0x3F
#define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_SHIFT         2
	u8 key;
	u8 length_hi;
	u8 vf_id /* This field should be assigned to Virtual Function ID if vf_valid == 1. Otherwise its dont care */;
	u8 vf_valid;
	__le16 pd;
	__le32 length_lo /* lower 32 bits of the registered MR length. */;
	__le32 itid;
	__le32 reserved2;
	struct regpair va;
	struct regpair pbl_base;
	struct regpair dif_error_addr /* DIF TX IO writes error information to this location when memory region is invalidated. */;
	struct regpair dif_runt_addr /* DIF RX IO writes runt value to this location when last RDMA Read of the IO has completed. */;
	__le32 reserved3[2];
};


/*
 * rdma resize cq output params
 */
struct rdma_resize_cq_output_params
{
	__le32 old_cq_cons /* cq consumer value on old PBL */;
	__le32 old_cq_prod /* cq producer value on old PBL */;
};


/*
 * rdma resize cq ramrod data
 */
struct rdma_resize_cq_ramrod_data
{
	u8 flags;
#define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_MASK        0x1
#define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_SHIFT       0
#define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_MASK  0x1
#define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_SHIFT 1
#define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK          0x3F
#define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_SHIFT         2
	u8 pbl_log_page_size;
	__le16 pbl_num_pages;
	__le32 max_cqes;
	struct regpair pbl_addr;
	struct regpair output_params_addr;
};


/*
 * The rdma storm context of Mstorm
 */
struct rdma_srq_context
{
	struct regpair temp[8];
};


/*
 * rdma create qp requester ramrod data
 */
struct rdma_srq_create_ramrod_data
{
	struct regpair pbl_base_addr /* SRQ PBL base address */;
	__le16 pages_in_srq_pbl /* Number of pages in PBL */;
	__le16 pd_id;
	struct rdma_srq_id srq_id /* SRQ Index */;
	__le16 page_size /* Page size in SGEs(16 bytes) elements. Supports up to 2M bytes page size */;
	__le16 reserved1;
	__le32 reserved2;
	struct regpair producers_addr /* SRQ PBL base address */;
};


/*
 * rdma create qp requester ramrod data
 */
struct rdma_srq_destroy_ramrod_data
{
	struct rdma_srq_id srq_id /* SRQ Index */;
	__le32 reserved;
};


/*
 * rdma create qp requester ramrod data
 */
struct rdma_srq_modify_ramrod_data
{
	struct rdma_srq_id srq_id /* SRQ Index */;
	__le32 wqe_limit;
};


/*
 * The rdma task context of Mstorm
 */
struct ystorm_rdma_task_st_ctx
{
	struct regpair temp[4];
};

struct e4_ystorm_rdma_task_ag_ctx
{
	u8 reserved /* cdu_validation */;
	u8 byte1 /* state */;
	__le16 msem_ctx_upd_seq /* icid */;
	u8 flags0;
#define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK  0xF /* connection_type */
#define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
#define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK     0x1 /* exist_in_qm0 */
#define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT    4
#define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK             0x1 /* exist_in_qm1 */
#define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT            5
#define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_MASK            0x1 /* bit2 */
#define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT           6
#define E4_YSTORM_RDMA_TASK_AG_CTX_BIT3_MASK             0x1 /* bit3 */
#define E4_YSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT            7
	u8 flags1;
#define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_MASK              0x3 /* cf0 */
#define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT             0
#define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_MASK              0x3 /* cf1 */
#define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT             2
#define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK       0x3 /* cf2special */
#define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT      4
#define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK            0x1 /* cf0en */
#define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT           6
#define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK            0x1 /* cf1en */
#define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT           7
	u8 flags2;
#define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK             0x1 /* bit4 */
#define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT            0
#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK          0x1 /* rule0en */
#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT         1
#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK          0x1 /* rule1en */
#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT         2
#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK          0x1 /* rule2en */
#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT         3
#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK          0x1 /* rule3en */
#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT         4
#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK          0x1 /* rule4en */
#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT         5
#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK          0x1 /* rule5en */
#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT         6
#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK          0x1 /* rule6en */
#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT         7
	u8 key /* byte2 */;
	__le32 mw_cnt /* reg0 */;
	u8 ref_cnt_seq /* byte3 */;
	u8 ctx_upd_seq /* byte4 */;
	__le16 dif_flags /* word1 */;
	__le16 tx_ref_count /* word2 */;
	__le16 last_used_ltid /* word3 */;
	__le16 parent_mr_lo /* word4 */;
	__le16 parent_mr_hi /* word5 */;
	__le32 fbo_lo /* reg1 */;
	__le32 fbo_hi /* reg2 */;
};

struct e4_mstorm_rdma_task_ag_ctx
{
	u8 reserved /* cdu_validation */;
	u8 byte1 /* state */;
	__le16 icid /* icid */;
	u8 flags0;
#define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK  0xF /* connection_type */
#define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
#define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK     0x1 /* exist_in_qm0 */
#define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT    4
#define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK             0x1 /* exist_in_qm1 */
#define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT            5
#define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK             0x1 /* bit2 */
#define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT            6
#define E4_MSTORM_RDMA_TASK_AG_CTX_BIT3_MASK             0x1 /* bit3 */
#define E4_MSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT            7
	u8 flags1;
#define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_MASK              0x3 /* cf0 */
#define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT             0
#define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_MASK              0x3 /* cf1 */
#define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT             2
#define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_MASK              0x3 /* cf2 */
#define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT             4
#define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK            0x1 /* cf0en */
#define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT           6
#define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK            0x1 /* cf1en */
#define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT           7
	u8 flags2;
#define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK            0x1 /* cf2en */
#define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT           0
#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK          0x1 /* rule0en */
#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT         1
#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK          0x1 /* rule1en */
#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT         2
#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK          0x1 /* rule2en */
#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT         3
#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK          0x1 /* rule3en */
#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT         4
#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK          0x1 /* rule4en */
#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT         5
#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK          0x1 /* rule5en */
#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT         6
#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK          0x1 /* rule6en */
#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT         7
	u8 key /* byte2 */;
	__le32 mw_cnt /* reg0 */;
	u8 ref_cnt_seq /* byte3 */;
	u8 ctx_upd_seq /* byte4 */;
	__le16 dif_flags /* word1 */;
	__le16 tx_ref_count /* word2 */;
	__le16 last_used_ltid /* word3 */;
	__le16 parent_mr_lo /* word4 */;
	__le16 parent_mr_hi /* word5 */;
	__le32 fbo_lo /* reg1 */;
	__le32 fbo_hi /* reg2 */;
};

/*
 * The roce task context of Ustorm
 */
struct ustorm_rdma_task_st_ctx
{
	struct regpair temp[2];
};

struct e4_ustorm_rdma_task_ag_ctx
{
	u8 reserved /* cdu_validation */;
	u8 byte1 /* state */;
	__le16 icid /* icid */;
	u8 flags0;
#define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK         0xF /* connection_type */
#define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT        0
#define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK            0x1 /* exist_in_qm0 */
#define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT           4
#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_MASK          0x1 /* exist_in_qm1 */
#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_SHIFT         5
#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK     0x3 /* timer0cf */
#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT    6
	u8 flags1;
#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK   0x3 /* timer1cf */
#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT  0
#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK           0x3 /* timer2cf */
#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT          2
#define E4_USTORM_RDMA_TASK_AG_CTX_CF3_MASK                     0x3 /* timer_stop_all */
#define E4_USTORM_RDMA_TASK_AG_CTX_CF3_SHIFT                    4
#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK            0x3 /* cf4 */
#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT           6
	u8 flags2;
#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK  0x1 /* cf0en */
#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0
#define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK               0x1 /* cf1en */
#define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT              1
#define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK               0x1 /* cf2en */
#define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT              2
#define E4_USTORM_RDMA_TASK_AG_CTX_CF3EN_MASK                   0x1 /* cf3en */
#define E4_USTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT                  3
#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK         0x1 /* cf4en */
#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT        4
#define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK                 0x1 /* rule0en */
#define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT                5
#define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK                 0x1 /* rule1en */
#define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT                6
#define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK                 0x1 /* rule2en */
#define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT                7
	u8 flags3;
#define E4_USTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK                 0x1 /* rule3en */
#define E4_USTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT                0
#define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK                 0x1 /* rule4en */
#define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT                1
#define E4_USTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK                 0x1 /* rule5en */
#define E4_USTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT                2
#define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK                 0x1 /* rule6en */
#define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT                3
#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK          0xF /* nibble1 */
#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT         4
	__le32 dif_err_intervals /* reg0 */;
	__le32 dif_error_1st_interval /* reg1 */;
	__le32 reg2 /* reg2 */;
	__le32 dif_runt_value /* reg3 */;
	__le32 reg4 /* reg4 */;
	__le32 reg5 /* reg5 */;
};

/*
 * RDMA task context
 */
struct rdma_task_context
{
	struct ystorm_rdma_task_st_ctx ystorm_st_context /* ystorm storm context */;
	struct e4_ystorm_rdma_task_ag_ctx ystorm_ag_context /* ystorm aggregative context */;
	struct tdif_task_context tdif_context /* tdif context */;
	struct e4_mstorm_rdma_task_ag_ctx mstorm_ag_context /* mstorm aggregative context */;
	struct mstorm_rdma_task_st_ctx mstorm_st_context /* mstorm storm context */;
	struct rdif_task_context rdif_context /* rdif context */;
	struct ustorm_rdma_task_st_ctx ustorm_st_context /* ustorm storm context */;
	struct regpair ustorm_st_padding[2] /* padding */;
	struct e4_ustorm_rdma_task_ag_ctx ustorm_ag_context /* ustorm aggregative context */;
};


/*
 * RDMA Tid type enumeration (for register_tid ramrod)
 */
enum rdma_tid_type
{
	RDMA_TID_REGISTERED_MR,
	RDMA_TID_FMR,
	RDMA_TID_MW_TYPE1,
	RDMA_TID_MW_TYPE2A,
	MAX_RDMA_TID_TYPE
};




struct E4XstormRoceConnAgCtxDqExtLdPart
{
	u8 reserved0 /* cdu_validation */;
	u8 state /* state */;
	u8 flags0;
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK      0x1 /* exist_in_qm0 */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT     0
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK              0x1 /* exist_in_qm1 */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_SHIFT             1
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK              0x1 /* exist_in_qm2 */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_SHIFT             2
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK      0x1 /* exist_in_qm3 */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT     3
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK              0x1 /* bit4 */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_SHIFT             4
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK              0x1 /* cf_array_active */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_SHIFT             5
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK              0x1 /* bit6 */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_SHIFT             6
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK              0x1 /* bit7 */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_SHIFT             7
	u8 flags1;
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK              0x1 /* bit8 */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_SHIFT             0
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK              0x1 /* bit9 */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_SHIFT             1
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK             0x1 /* bit10 */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT            2
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK             0x1 /* bit11 */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT            3
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_MASK             0x1 /* bit12 */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_SHIFT            4
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSTORM_FLUSH_MASK      0x1 /* bit13 */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSTORM_FLUSH_SHIFT     5
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_MASK             0x1 /* bit14 */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_SHIFT            6
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK      0x1 /* bit15 */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT     7
	u8 flags2;
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK               0x3 /* timer0cf */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT              0
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK               0x3 /* timer1cf */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT              2
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK               0x3 /* timer2cf */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT              4
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK               0x3 /* timer_stop_all */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT              6
	u8 flags3;
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK               0x3 /* cf4 */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_SHIFT              0
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK               0x3 /* cf5 */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_SHIFT              2
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK               0x3 /* cf6 */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_SHIFT              4
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK       0x3 /* cf7 */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT      6
	u8 flags4;
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK               0x3 /* cf8 */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT              0
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK               0x3 /* cf9 */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT              2
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK              0x3 /* cf10 */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT             4
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK              0x3 /* cf11 */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT             6
	u8 flags5;
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK              0x3 /* cf12 */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT             0
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK              0x3 /* cf13 */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT             2
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK              0x3 /* cf14 */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_SHIFT             4
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK              0x3 /* cf15 */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT             6
	u8 flags6;
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK              0x3 /* cf16 */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT             0
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK              0x3 /* cf_array_cf */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT             2
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK              0x3 /* cf18 */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT             4
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK              0x3 /* cf19 */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT             6
	u8 flags7;
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK              0x3 /* cf20 */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT             0
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK              0x3 /* cf21 */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT             2
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK         0x3 /* cf22 */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT        4
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK             0x1 /* cf0en */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT            6
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK             0x1 /* cf1en */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT            7
	u8 flags8;
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK             0x1 /* cf2en */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT            0
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK             0x1 /* cf3en */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT            1
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK             0x1 /* cf4en */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_SHIFT            2
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK             0x1 /* cf5en */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_SHIFT            3
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK             0x1 /* cf6en */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_SHIFT            4
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK    0x1 /* cf7en */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT   5
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK             0x1 /* cf8en */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT            6
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK             0x1 /* cf9en */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT            7
	u8 flags9;
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK            0x1 /* cf10en */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT           0
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK            0x1 /* cf11en */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT           1
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK            0x1 /* cf12en */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT           2
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK            0x1 /* cf13en */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT           3
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK            0x1 /* cf14en */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_SHIFT           4
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK            0x1 /* cf15en */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT           5
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK            0x1 /* cf16en */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT           6
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK            0x1 /* cf_array_cf_en */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT           7
	u8 flags10;
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK            0x1 /* cf18en */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT           0
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK            0x1 /* cf19en */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT           1
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK            0x1 /* cf20en */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT           2
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK            0x1 /* cf21en */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT           3
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK      0x1 /* cf22en */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT     4
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK            0x1 /* cf23en */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT           5
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK           0x1 /* rule0en */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT          6
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK           0x1 /* rule1en */
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT          7
	u8 flags11;
#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK           0x1 /* rule2en */