1*14b24e2bSVaishali Kulkarni /*
2*14b24e2bSVaishali Kulkarni * CDDL HEADER START
3*14b24e2bSVaishali Kulkarni *
4*14b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the
5*14b24e2bSVaishali Kulkarni * Common Development and Distribution License, v.1,  (the "License").
6*14b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License.
7*14b24e2bSVaishali Kulkarni *
8*14b24e2bSVaishali Kulkarni * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9*14b24e2bSVaishali Kulkarni * or http://opensource.org/licenses/CDDL-1.0.
10*14b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions
11*14b24e2bSVaishali Kulkarni * and limitations under the License.
12*14b24e2bSVaishali Kulkarni *
13*14b24e2bSVaishali Kulkarni * When distributing Covered Code, include this CDDL HEADER in each
14*14b24e2bSVaishali Kulkarni * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15*14b24e2bSVaishali Kulkarni * If applicable, add the following below this CDDL HEADER, with the
16*14b24e2bSVaishali Kulkarni * fields enclosed by brackets "[]" replaced with your own identifying
17*14b24e2bSVaishali Kulkarni * information: Portions Copyright [yyyy] [name of copyright owner]
18*14b24e2bSVaishali Kulkarni *
19*14b24e2bSVaishali Kulkarni * CDDL HEADER END
20*14b24e2bSVaishali Kulkarni */
21*14b24e2bSVaishali Kulkarni 
22*14b24e2bSVaishali Kulkarni /*
23*14b24e2bSVaishali Kulkarni * Copyright 2014-2017 Cavium, Inc.
24*14b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the Common Development
25*14b24e2bSVaishali Kulkarni * and Distribution License, v.1,  (the "License").
26*14b24e2bSVaishali Kulkarni 
27*14b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License.
28*14b24e2bSVaishali Kulkarni 
29*14b24e2bSVaishali Kulkarni * You can obtain a copy of the License at available
30*14b24e2bSVaishali Kulkarni * at http://opensource.org/licenses/CDDL-1.0
31*14b24e2bSVaishali Kulkarni 
32*14b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions and
33*14b24e2bSVaishali Kulkarni * limitations under the License.
34*14b24e2bSVaishali Kulkarni */
35*14b24e2bSVaishali Kulkarni 
36*14b24e2bSVaishali Kulkarni #ifndef __ECORE_HSI_RDMA__
37*14b24e2bSVaishali Kulkarni #define __ECORE_HSI_RDMA__
38*14b24e2bSVaishali Kulkarni /************************************************************************/
39*14b24e2bSVaishali Kulkarni /* Add include to common rdma target for both eCore and protocol rdma driver */
40*14b24e2bSVaishali Kulkarni /************************************************************************/
41*14b24e2bSVaishali Kulkarni #include "rdma_common.h"
42*14b24e2bSVaishali Kulkarni 
43*14b24e2bSVaishali Kulkarni /*
44*14b24e2bSVaishali Kulkarni  * The roce task context of Mstorm
45*14b24e2bSVaishali Kulkarni  */
46*14b24e2bSVaishali Kulkarni struct mstorm_rdma_task_st_ctx
47*14b24e2bSVaishali Kulkarni {
48*14b24e2bSVaishali Kulkarni 	struct regpair temp[4];
49*14b24e2bSVaishali Kulkarni };
50*14b24e2bSVaishali Kulkarni 
51*14b24e2bSVaishali Kulkarni 
52*14b24e2bSVaishali Kulkarni /*
53*14b24e2bSVaishali Kulkarni  * rdma function init ramrod data
54*14b24e2bSVaishali Kulkarni  */
55*14b24e2bSVaishali Kulkarni struct rdma_close_func_ramrod_data
56*14b24e2bSVaishali Kulkarni {
57*14b24e2bSVaishali Kulkarni 	u8 cnq_start_offset;
58*14b24e2bSVaishali Kulkarni 	u8 num_cnqs;
59*14b24e2bSVaishali Kulkarni 	u8 vf_id /* This field should be assigned to Virtual Function ID if vf_valid == 1. Otherwise its dont care */;
60*14b24e2bSVaishali Kulkarni 	u8 vf_valid;
61*14b24e2bSVaishali Kulkarni 	u8 reserved[4];
62*14b24e2bSVaishali Kulkarni };
63*14b24e2bSVaishali Kulkarni 
64*14b24e2bSVaishali Kulkarni 
65*14b24e2bSVaishali Kulkarni /*
66*14b24e2bSVaishali Kulkarni  * rdma function init CNQ parameters
67*14b24e2bSVaishali Kulkarni  */
68*14b24e2bSVaishali Kulkarni struct rdma_cnq_params
69*14b24e2bSVaishali Kulkarni {
70*14b24e2bSVaishali Kulkarni 	__le16 sb_num /* Status block number used by the queue */;
71*14b24e2bSVaishali Kulkarni 	u8 sb_index /* Status block index used by the queue */;
72*14b24e2bSVaishali Kulkarni 	u8 num_pbl_pages /* Number of pages in the PBL allocated for this queue */;
73*14b24e2bSVaishali Kulkarni 	__le32 reserved;
74*14b24e2bSVaishali Kulkarni 	struct regpair pbl_base_addr /* Address to the first entry of the queue PBL */;
75*14b24e2bSVaishali Kulkarni 	__le16 queue_zone_num /* Queue Zone ID used for CNQ consumer update */;
76*14b24e2bSVaishali Kulkarni 	u8 reserved1[6];
77*14b24e2bSVaishali Kulkarni };
78*14b24e2bSVaishali Kulkarni 
79*14b24e2bSVaishali Kulkarni 
80*14b24e2bSVaishali Kulkarni /*
81*14b24e2bSVaishali Kulkarni  * rdma create cq ramrod data
82*14b24e2bSVaishali Kulkarni  */
83*14b24e2bSVaishali Kulkarni struct rdma_create_cq_ramrod_data
84*14b24e2bSVaishali Kulkarni {
85*14b24e2bSVaishali Kulkarni 	struct regpair cq_handle;
86*14b24e2bSVaishali Kulkarni 	struct regpair pbl_addr;
87*14b24e2bSVaishali Kulkarni 	__le32 max_cqes;
88*14b24e2bSVaishali Kulkarni 	__le16 pbl_num_pages;
89*14b24e2bSVaishali Kulkarni 	__le16 dpi;
90*14b24e2bSVaishali Kulkarni 	u8 is_two_level_pbl;
91*14b24e2bSVaishali Kulkarni 	u8 cnq_id;
92*14b24e2bSVaishali Kulkarni 	u8 pbl_log_page_size;
93*14b24e2bSVaishali Kulkarni 	u8 toggle_bit;
94*14b24e2bSVaishali Kulkarni 	__le16 int_timeout /* Timeout used for interrupt moderation */;
95*14b24e2bSVaishali Kulkarni 	__le16 reserved1;
96*14b24e2bSVaishali Kulkarni };
97*14b24e2bSVaishali Kulkarni 
98*14b24e2bSVaishali Kulkarni 
99*14b24e2bSVaishali Kulkarni /*
100*14b24e2bSVaishali Kulkarni  * rdma deregister tid ramrod data
101*14b24e2bSVaishali Kulkarni  */
102*14b24e2bSVaishali Kulkarni struct rdma_deregister_tid_ramrod_data
103*14b24e2bSVaishali Kulkarni {
104*14b24e2bSVaishali Kulkarni 	__le32 itid;
105*14b24e2bSVaishali Kulkarni 	__le32 reserved;
106*14b24e2bSVaishali Kulkarni };
107*14b24e2bSVaishali Kulkarni 
108*14b24e2bSVaishali Kulkarni 
109*14b24e2bSVaishali Kulkarni /*
110*14b24e2bSVaishali Kulkarni  * rdma destroy cq output params
111*14b24e2bSVaishali Kulkarni  */
112*14b24e2bSVaishali Kulkarni struct rdma_destroy_cq_output_params
113*14b24e2bSVaishali Kulkarni {
114*14b24e2bSVaishali Kulkarni 	__le16 cnq_num /* Sequence number of completion notification sent for the cq on the associated CNQ */;
115*14b24e2bSVaishali Kulkarni 	__le16 reserved0;
116*14b24e2bSVaishali Kulkarni 	__le32 reserved1;
117*14b24e2bSVaishali Kulkarni };
118*14b24e2bSVaishali Kulkarni 
119*14b24e2bSVaishali Kulkarni 
120*14b24e2bSVaishali Kulkarni /*
121*14b24e2bSVaishali Kulkarni  * rdma destroy cq ramrod data
122*14b24e2bSVaishali Kulkarni  */
123*14b24e2bSVaishali Kulkarni struct rdma_destroy_cq_ramrod_data
124*14b24e2bSVaishali Kulkarni {
125*14b24e2bSVaishali Kulkarni 	struct regpair output_params_addr;
126*14b24e2bSVaishali Kulkarni };
127*14b24e2bSVaishali Kulkarni 
128*14b24e2bSVaishali Kulkarni 
129*14b24e2bSVaishali Kulkarni /*
130*14b24e2bSVaishali Kulkarni  * RDMA slow path EQ cmd IDs
131*14b24e2bSVaishali Kulkarni  */
132*14b24e2bSVaishali Kulkarni enum rdma_event_opcode
133*14b24e2bSVaishali Kulkarni {
134*14b24e2bSVaishali Kulkarni 	RDMA_EVENT_UNUSED,
135*14b24e2bSVaishali Kulkarni 	RDMA_EVENT_FUNC_INIT,
136*14b24e2bSVaishali Kulkarni 	RDMA_EVENT_FUNC_CLOSE,
137*14b24e2bSVaishali Kulkarni 	RDMA_EVENT_REGISTER_MR,
138*14b24e2bSVaishali Kulkarni 	RDMA_EVENT_DEREGISTER_MR,
139*14b24e2bSVaishali Kulkarni 	RDMA_EVENT_CREATE_CQ,
140*14b24e2bSVaishali Kulkarni 	RDMA_EVENT_RESIZE_CQ,
141*14b24e2bSVaishali Kulkarni 	RDMA_EVENT_DESTROY_CQ,
142*14b24e2bSVaishali Kulkarni 	RDMA_EVENT_CREATE_SRQ,
143*14b24e2bSVaishali Kulkarni 	RDMA_EVENT_MODIFY_SRQ,
144*14b24e2bSVaishali Kulkarni 	RDMA_EVENT_DESTROY_SRQ,
145*14b24e2bSVaishali Kulkarni 	MAX_RDMA_EVENT_OPCODE
146*14b24e2bSVaishali Kulkarni };
147*14b24e2bSVaishali Kulkarni 
148*14b24e2bSVaishali Kulkarni 
149*14b24e2bSVaishali Kulkarni /*
150*14b24e2bSVaishali Kulkarni  * RDMA FW return code for slow path ramrods
151*14b24e2bSVaishali Kulkarni  */
152*14b24e2bSVaishali Kulkarni enum rdma_fw_return_code
153*14b24e2bSVaishali Kulkarni {
154*14b24e2bSVaishali Kulkarni 	RDMA_RETURN_OK=0,
155*14b24e2bSVaishali Kulkarni 	RDMA_RETURN_REGISTER_MR_BAD_STATE_ERR,
156*14b24e2bSVaishali Kulkarni 	RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR,
157*14b24e2bSVaishali Kulkarni 	RDMA_RETURN_RESIZE_CQ_ERR,
158*14b24e2bSVaishali Kulkarni 	RDMA_RETURN_NIG_DRAIN_REQ,
159*14b24e2bSVaishali Kulkarni 	MAX_RDMA_FW_RETURN_CODE
160*14b24e2bSVaishali Kulkarni };
161*14b24e2bSVaishali Kulkarni 
162*14b24e2bSVaishali Kulkarni 
163*14b24e2bSVaishali Kulkarni /*
164*14b24e2bSVaishali Kulkarni  * rdma function init header
165*14b24e2bSVaishali Kulkarni  */
166*14b24e2bSVaishali Kulkarni struct rdma_init_func_hdr
167*14b24e2bSVaishali Kulkarni {
168*14b24e2bSVaishali Kulkarni 	u8 cnq_start_offset /* First RDMA CNQ */;
169*14b24e2bSVaishali Kulkarni 	u8 num_cnqs /* Number of CNQs */;
170*14b24e2bSVaishali Kulkarni 	u8 cq_ring_mode /* 0 for 32 bit cq producer and consumer counters and 1 for 16 bit */;
171*14b24e2bSVaishali Kulkarni 	u8 vf_id /* This field should be assigned to Virtual Function ID if vf_valid == 1. Otherwise its dont care */;
172*14b24e2bSVaishali Kulkarni 	u8 vf_valid;
173*14b24e2bSVaishali Kulkarni 	u8 reserved[3];
174*14b24e2bSVaishali Kulkarni };
175*14b24e2bSVaishali Kulkarni 
176*14b24e2bSVaishali Kulkarni 
177*14b24e2bSVaishali Kulkarni /*
178*14b24e2bSVaishali Kulkarni  * rdma function init ramrod data
179*14b24e2bSVaishali Kulkarni  */
180*14b24e2bSVaishali Kulkarni struct rdma_init_func_ramrod_data
181*14b24e2bSVaishali Kulkarni {
182*14b24e2bSVaishali Kulkarni 	struct rdma_init_func_hdr params_header;
183*14b24e2bSVaishali Kulkarni 	struct rdma_cnq_params cnq_params[NUM_OF_GLOBAL_QUEUES];
184*14b24e2bSVaishali Kulkarni };
185*14b24e2bSVaishali Kulkarni 
186*14b24e2bSVaishali Kulkarni 
187*14b24e2bSVaishali Kulkarni /*
188*14b24e2bSVaishali Kulkarni  * RDMA ramrod command IDs
189*14b24e2bSVaishali Kulkarni  */
190*14b24e2bSVaishali Kulkarni enum rdma_ramrod_cmd_id
191*14b24e2bSVaishali Kulkarni {
192*14b24e2bSVaishali Kulkarni 	RDMA_RAMROD_UNUSED,
193*14b24e2bSVaishali Kulkarni 	RDMA_RAMROD_FUNC_INIT,
194*14b24e2bSVaishali Kulkarni 	RDMA_RAMROD_FUNC_CLOSE,
195*14b24e2bSVaishali Kulkarni 	RDMA_RAMROD_REGISTER_MR,
196*14b24e2bSVaishali Kulkarni 	RDMA_RAMROD_DEREGISTER_MR,
197*14b24e2bSVaishali Kulkarni 	RDMA_RAMROD_CREATE_CQ,
198*14b24e2bSVaishali Kulkarni 	RDMA_RAMROD_RESIZE_CQ,
199*14b24e2bSVaishali Kulkarni 	RDMA_RAMROD_DESTROY_CQ,
200*14b24e2bSVaishali Kulkarni 	RDMA_RAMROD_CREATE_SRQ,
201*14b24e2bSVaishali Kulkarni 	RDMA_RAMROD_MODIFY_SRQ,
202*14b24e2bSVaishali Kulkarni 	RDMA_RAMROD_DESTROY_SRQ,
203*14b24e2bSVaishali Kulkarni 	MAX_RDMA_RAMROD_CMD_ID
204*14b24e2bSVaishali Kulkarni };
205*14b24e2bSVaishali Kulkarni 
206*14b24e2bSVaishali Kulkarni 
207*14b24e2bSVaishali Kulkarni /*
208*14b24e2bSVaishali Kulkarni  * rdma register tid ramrod data
209*14b24e2bSVaishali Kulkarni  */
210*14b24e2bSVaishali Kulkarni struct rdma_register_tid_ramrod_data
211*14b24e2bSVaishali Kulkarni {
212*14b24e2bSVaishali Kulkarni 	__le32 flags;
213*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_MAX_ID_MASK             0x3FFFF
214*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_MAX_ID_SHIFT            0
215*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_MASK      0x1F
216*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_SHIFT     18
217*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_MASK      0x1
218*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_SHIFT     23
219*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_MASK         0x1
220*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_SHIFT        24
221*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_MASK             0x1
222*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_SHIFT            25
223*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_MASK        0x1
224*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_SHIFT       26
225*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_MASK       0x1
226*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_SHIFT      27
227*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_MASK      0x1
228*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_SHIFT     28
229*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_MASK        0x1
230*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_SHIFT       29
231*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_MASK         0x1
232*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_SHIFT        30
233*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_MASK     0x1
234*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_SHIFT    31
235*14b24e2bSVaishali Kulkarni 	u8 flags1;
236*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_MASK  0x1F
237*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_SHIFT 0
238*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_MASK           0x7
239*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_SHIFT          5
240*14b24e2bSVaishali Kulkarni 	u8 flags2;
241*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_MASK             0x1 /* Bit indicating that this MR is DMA_MR meaning SGEs that use it have the physical address on them */
242*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_SHIFT            0
243*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_MASK    0x1 /* Bit indicating that this MR has DIF protection enabled. */
244*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_SHIFT   1
245*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_MASK          0x3F
246*14b24e2bSVaishali Kulkarni #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_SHIFT         2
247*14b24e2bSVaishali Kulkarni 	u8 key;
248*14b24e2bSVaishali Kulkarni 	u8 length_hi;
249*14b24e2bSVaishali Kulkarni 	u8 vf_id /* This field should be assigned to Virtual Function ID if vf_valid == 1. Otherwise its dont care */;
250*14b24e2bSVaishali Kulkarni 	u8 vf_valid;
251*14b24e2bSVaishali Kulkarni 	__le16 pd;
252*14b24e2bSVaishali Kulkarni 	__le32 length_lo /* lower 32 bits of the registered MR length. */;
253*14b24e2bSVaishali Kulkarni 	__le32 itid;
254*14b24e2bSVaishali Kulkarni 	__le32 reserved2;
255*14b24e2bSVaishali Kulkarni 	struct regpair va;
256*14b24e2bSVaishali Kulkarni 	struct regpair pbl_base;
257*14b24e2bSVaishali Kulkarni 	struct regpair dif_error_addr /* DIF TX IO writes error information to this location when memory region is invalidated. */;
258*14b24e2bSVaishali Kulkarni 	struct regpair dif_runt_addr /* DIF RX IO writes runt value to this location when last RDMA Read of the IO has completed. */;
259*14b24e2bSVaishali Kulkarni 	__le32 reserved3[2];
260*14b24e2bSVaishali Kulkarni };
261*14b24e2bSVaishali Kulkarni 
262*14b24e2bSVaishali Kulkarni 
263*14b24e2bSVaishali Kulkarni /*
264*14b24e2bSVaishali Kulkarni  * rdma resize cq output params
265*14b24e2bSVaishali Kulkarni  */
266*14b24e2bSVaishali Kulkarni struct rdma_resize_cq_output_params
267*14b24e2bSVaishali Kulkarni {
268*14b24e2bSVaishali Kulkarni 	__le32 old_cq_cons /* cq consumer value on old PBL */;
269*14b24e2bSVaishali Kulkarni 	__le32 old_cq_prod /* cq producer value on old PBL */;
270*14b24e2bSVaishali Kulkarni };
271*14b24e2bSVaishali Kulkarni 
272*14b24e2bSVaishali Kulkarni 
273*14b24e2bSVaishali Kulkarni /*
274*14b24e2bSVaishali Kulkarni  * rdma resize cq ramrod data
275*14b24e2bSVaishali Kulkarni  */
276*14b24e2bSVaishali Kulkarni struct rdma_resize_cq_ramrod_data
277*14b24e2bSVaishali Kulkarni {
278*14b24e2bSVaishali Kulkarni 	u8 flags;
279*14b24e2bSVaishali Kulkarni #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_MASK        0x1
280*14b24e2bSVaishali Kulkarni #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_SHIFT       0
281*14b24e2bSVaishali Kulkarni #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_MASK  0x1
282*14b24e2bSVaishali Kulkarni #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_SHIFT 1
283*14b24e2bSVaishali Kulkarni #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK          0x3F
284*14b24e2bSVaishali Kulkarni #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_SHIFT         2
285*14b24e2bSVaishali Kulkarni 	u8 pbl_log_page_size;
286*14b24e2bSVaishali Kulkarni 	__le16 pbl_num_pages;
287*14b24e2bSVaishali Kulkarni 	__le32 max_cqes;
288*14b24e2bSVaishali Kulkarni 	struct regpair pbl_addr;
289*14b24e2bSVaishali Kulkarni 	struct regpair output_params_addr;
290*14b24e2bSVaishali Kulkarni };
291*14b24e2bSVaishali Kulkarni 
292*14b24e2bSVaishali Kulkarni 
293*14b24e2bSVaishali Kulkarni /*
294*14b24e2bSVaishali Kulkarni  * The rdma storm context of Mstorm
295*14b24e2bSVaishali Kulkarni  */
296*14b24e2bSVaishali Kulkarni struct rdma_srq_context
297*14b24e2bSVaishali Kulkarni {
298*14b24e2bSVaishali Kulkarni 	struct regpair temp[8];
299*14b24e2bSVaishali Kulkarni };
300*14b24e2bSVaishali Kulkarni 
301*14b24e2bSVaishali Kulkarni 
302*14b24e2bSVaishali Kulkarni /*
303*14b24e2bSVaishali Kulkarni  * rdma create qp requester ramrod data
304*14b24e2bSVaishali Kulkarni  */
305*14b24e2bSVaishali Kulkarni struct rdma_srq_create_ramrod_data
306*14b24e2bSVaishali Kulkarni {
307*14b24e2bSVaishali Kulkarni 	struct regpair pbl_base_addr /* SRQ PBL base address */;
308*14b24e2bSVaishali Kulkarni 	__le16 pages_in_srq_pbl /* Number of pages in PBL */;
309*14b24e2bSVaishali Kulkarni 	__le16 pd_id;
310*14b24e2bSVaishali Kulkarni 	struct rdma_srq_id srq_id /* SRQ Index */;
311*14b24e2bSVaishali Kulkarni 	__le16 page_size /* Page size in SGEs(16 bytes) elements. Supports up to 2M bytes page size */;
312*14b24e2bSVaishali Kulkarni 	__le16 reserved1;
313*14b24e2bSVaishali Kulkarni 	__le32 reserved2;
314*14b24e2bSVaishali Kulkarni 	struct regpair producers_addr /* SRQ PBL base address */;
315*14b24e2bSVaishali Kulkarni };
316*14b24e2bSVaishali Kulkarni 
317*14b24e2bSVaishali Kulkarni 
318*14b24e2bSVaishali Kulkarni /*
319*14b24e2bSVaishali Kulkarni  * rdma create qp requester ramrod data
320*14b24e2bSVaishali Kulkarni  */
321*14b24e2bSVaishali Kulkarni struct rdma_srq_destroy_ramrod_data
322*14b24e2bSVaishali Kulkarni {
323*14b24e2bSVaishali Kulkarni 	struct rdma_srq_id srq_id /* SRQ Index */;
324*14b24e2bSVaishali Kulkarni 	__le32 reserved;
325*14b24e2bSVaishali Kulkarni };
326*14b24e2bSVaishali Kulkarni 
327*14b24e2bSVaishali Kulkarni 
328*14b24e2bSVaishali Kulkarni /*
329*14b24e2bSVaishali Kulkarni  * rdma create qp requester ramrod data
330*14b24e2bSVaishali Kulkarni  */
331*14b24e2bSVaishali Kulkarni struct rdma_srq_modify_ramrod_data
332*14b24e2bSVaishali Kulkarni {
333*14b24e2bSVaishali Kulkarni 	struct rdma_srq_id srq_id /* SRQ Index */;
334*14b24e2bSVaishali Kulkarni 	__le32 wqe_limit;
335*14b24e2bSVaishali Kulkarni };
336*14b24e2bSVaishali Kulkarni 
337*14b24e2bSVaishali Kulkarni 
338*14b24e2bSVaishali Kulkarni /*
339*14b24e2bSVaishali Kulkarni  * The rdma task context of Mstorm
340*14b24e2bSVaishali Kulkarni  */
341*14b24e2bSVaishali Kulkarni struct ystorm_rdma_task_st_ctx
342*14b24e2bSVaishali Kulkarni {
343*14b24e2bSVaishali Kulkarni 	struct regpair temp[4];
344*14b24e2bSVaishali Kulkarni };
345*14b24e2bSVaishali Kulkarni 
346*14b24e2bSVaishali Kulkarni struct e4_ystorm_rdma_task_ag_ctx
347*14b24e2bSVaishali Kulkarni {
348*14b24e2bSVaishali Kulkarni 	u8 reserved /* cdu_validation */;
349*14b24e2bSVaishali Kulkarni 	u8 byte1 /* state */;
350*14b24e2bSVaishali Kulkarni 	__le16 msem_ctx_upd_seq /* icid */;
351*14b24e2bSVaishali Kulkarni 	u8 flags0;
352*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK  0xF /* connection_type */
353*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
354*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK     0x1 /* exist_in_qm0 */
355*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT    4
356*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK             0x1 /* exist_in_qm1 */
357*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT            5
358*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_MASK            0x1 /* bit2 */
359*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT           6
360*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT3_MASK             0x1 /* bit3 */
361*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT            7
362*14b24e2bSVaishali Kulkarni 	u8 flags1;
363*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_MASK              0x3 /* cf0 */
364*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT             0
365*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_MASK              0x3 /* cf1 */
366*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT             2
367*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK       0x3 /* cf2special */
368*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT      4
369*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK            0x1 /* cf0en */
370*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT           6
371*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK            0x1 /* cf1en */
372*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT           7
373*14b24e2bSVaishali Kulkarni 	u8 flags2;
374*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK             0x1 /* bit4 */
375*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT            0
376*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK          0x1 /* rule0en */
377*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT         1
378*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK          0x1 /* rule1en */
379*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT         2
380*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK          0x1 /* rule2en */
381*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT         3
382*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK          0x1 /* rule3en */
383*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT         4
384*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK          0x1 /* rule4en */
385*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT         5
386*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK          0x1 /* rule5en */
387*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT         6
388*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK          0x1 /* rule6en */
389*14b24e2bSVaishali Kulkarni #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT         7
390*14b24e2bSVaishali Kulkarni 	u8 key /* byte2 */;
391*14b24e2bSVaishali Kulkarni 	__le32 mw_cnt /* reg0 */;
392*14b24e2bSVaishali Kulkarni 	u8 ref_cnt_seq /* byte3 */;
393*14b24e2bSVaishali Kulkarni 	u8 ctx_upd_seq /* byte4 */;
394*14b24e2bSVaishali Kulkarni 	__le16 dif_flags /* word1 */;
395*14b24e2bSVaishali Kulkarni 	__le16 tx_ref_count /* word2 */;
396*14b24e2bSVaishali Kulkarni 	__le16 last_used_ltid /* word3 */;
397*14b24e2bSVaishali Kulkarni 	__le16 parent_mr_lo /* word4 */;
398*14b24e2bSVaishali Kulkarni 	__le16 parent_mr_hi /* word5 */;
399*14b24e2bSVaishali Kulkarni 	__le32 fbo_lo /* reg1 */;
400*14b24e2bSVaishali Kulkarni 	__le32 fbo_hi /* reg2 */;
401*14b24e2bSVaishali Kulkarni };
402*14b24e2bSVaishali Kulkarni 
403*14b24e2bSVaishali Kulkarni struct e4_mstorm_rdma_task_ag_ctx
404*14b24e2bSVaishali Kulkarni {
405*14b24e2bSVaishali Kulkarni 	u8 reserved /* cdu_validation */;
406*14b24e2bSVaishali Kulkarni 	u8 byte1 /* state */;
407*14b24e2bSVaishali Kulkarni 	__le16 icid /* icid */;
408*14b24e2bSVaishali Kulkarni 	u8 flags0;
409*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK  0xF /* connection_type */
410*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
411*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK     0x1 /* exist_in_qm0 */
412*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT    4
413*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK             0x1 /* exist_in_qm1 */
414*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT            5
415*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK             0x1 /* bit2 */
416*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT            6
417*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT3_MASK             0x1 /* bit3 */
418*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT            7
419*14b24e2bSVaishali Kulkarni 	u8 flags1;
420*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_MASK              0x3 /* cf0 */
421*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT             0
422*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_MASK              0x3 /* cf1 */
423*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT             2
424*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_MASK              0x3 /* cf2 */
425*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT             4
426*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK            0x1 /* cf0en */
427*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT           6
428*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK            0x1 /* cf1en */
429*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT           7
430*14b24e2bSVaishali Kulkarni 	u8 flags2;
431*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK            0x1 /* cf2en */
432*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT           0
433*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK          0x1 /* rule0en */
434*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT         1
435*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK          0x1 /* rule1en */
436*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT         2
437*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK          0x1 /* rule2en */
438*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT         3
439*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK          0x1 /* rule3en */
440*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT         4
441*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK          0x1 /* rule4en */
442*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT         5
443*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK          0x1 /* rule5en */
444*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT         6
445*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK          0x1 /* rule6en */
446*14b24e2bSVaishali Kulkarni #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT         7
447*14b24e2bSVaishali Kulkarni 	u8 key /* byte2 */;
448*14b24e2bSVaishali Kulkarni 	__le32 mw_cnt /* reg0 */;
449*14b24e2bSVaishali Kulkarni 	u8 ref_cnt_seq /* byte3 */;
450*14b24e2bSVaishali Kulkarni 	u8 ctx_upd_seq /* byte4 */;
451*14b24e2bSVaishali Kulkarni 	__le16 dif_flags /* word1 */;
452*14b24e2bSVaishali Kulkarni 	__le16 tx_ref_count /* word2 */;
453*14b24e2bSVaishali Kulkarni 	__le16 last_used_ltid /* word3 */;
454*14b24e2bSVaishali Kulkarni 	__le16 parent_mr_lo /* word4 */;
455*14b24e2bSVaishali Kulkarni 	__le16 parent_mr_hi /* word5 */;
456*14b24e2bSVaishali Kulkarni 	__le32 fbo_lo /* reg1 */;
457*14b24e2bSVaishali Kulkarni 	__le32 fbo_hi /* reg2 */;
458*14b24e2bSVaishali Kulkarni };
459*14b24e2bSVaishali Kulkarni 
460*14b24e2bSVaishali Kulkarni /*
461*14b24e2bSVaishali Kulkarni  * The roce task context of Ustorm
462*14b24e2bSVaishali Kulkarni  */
463*14b24e2bSVaishali Kulkarni struct ustorm_rdma_task_st_ctx
464*14b24e2bSVaishali Kulkarni {
465*14b24e2bSVaishali Kulkarni 	struct regpair temp[2];
466*14b24e2bSVaishali Kulkarni };
467*14b24e2bSVaishali Kulkarni 
468*14b24e2bSVaishali Kulkarni struct e4_ustorm_rdma_task_ag_ctx
469*14b24e2bSVaishali Kulkarni {
470*14b24e2bSVaishali Kulkarni 	u8 reserved /* cdu_validation */;
471*14b24e2bSVaishali Kulkarni 	u8 byte1 /* state */;
472*14b24e2bSVaishali Kulkarni 	__le16 icid /* icid */;
473*14b24e2bSVaishali Kulkarni 	u8 flags0;
474*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK         0xF /* connection_type */
475*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT        0
476*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK            0x1 /* exist_in_qm0 */
477*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT           4
478*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_MASK          0x1 /* exist_in_qm1 */
479*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_SHIFT         5
480*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK     0x3 /* timer0cf */
481*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT    6
482*14b24e2bSVaishali Kulkarni 	u8 flags1;
483*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK   0x3 /* timer1cf */
484*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT  0
485*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK           0x3 /* timer2cf */
486*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT          2
487*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_CF3_MASK                     0x3 /* timer_stop_all */
488*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_CF3_SHIFT                    4
489*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK            0x3 /* cf4 */
490*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT           6
491*14b24e2bSVaishali Kulkarni 	u8 flags2;
492*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK  0x1 /* cf0en */
493*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0
494*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK               0x1 /* cf1en */
495*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT              1
496*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK               0x1 /* cf2en */
497*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT              2
498*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_CF3EN_MASK                   0x1 /* cf3en */
499*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT                  3
500*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK         0x1 /* cf4en */
501*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT        4
502*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK                 0x1 /* rule0en */
503*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT                5
504*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK                 0x1 /* rule1en */
505*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT                6
506*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK                 0x1 /* rule2en */
507*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT                7
508*14b24e2bSVaishali Kulkarni 	u8 flags3;
509*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK                 0x1 /* rule3en */
510*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT                0
511*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK                 0x1 /* rule4en */
512*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT                1
513*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK                 0x1 /* rule5en */
514*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT                2
515*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK                 0x1 /* rule6en */
516*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT                3
517*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK          0xF /* nibble1 */
518*14b24e2bSVaishali Kulkarni #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT         4
519*14b24e2bSVaishali Kulkarni 	__le32 dif_err_intervals /* reg0 */;
520*14b24e2bSVaishali Kulkarni 	__le32 dif_error_1st_interval /* reg1 */;
521*14b24e2bSVaishali Kulkarni 	__le32 reg2 /* reg2 */;
522*14b24e2bSVaishali Kulkarni 	__le32 dif_runt_value /* reg3 */;
523*14b24e2bSVaishali Kulkarni 	__le32 reg4 /* reg4 */;
524*14b24e2bSVaishali Kulkarni 	__le32 reg5 /* reg5 */;
525*14b24e2bSVaishali Kulkarni };
526*14b24e2bSVaishali Kulkarni 
527*14b24e2bSVaishali Kulkarni /*
528*14b24e2bSVaishali Kulkarni  * RDMA task context
529*14b24e2bSVaishali Kulkarni  */
530*14b24e2bSVaishali Kulkarni struct rdma_task_context
531*14b24e2bSVaishali Kulkarni {
532*14b24e2bSVaishali Kulkarni 	struct ystorm_rdma_task_st_ctx ystorm_st_context /* ystorm storm context */;
533*14b24e2bSVaishali Kulkarni 	struct e4_ystorm_rdma_task_ag_ctx ystorm_ag_context /* ystorm aggregative context */;
534*14b24e2bSVaishali Kulkarni 	struct tdif_task_context tdif_context /* tdif context */;
535*14b24e2bSVaishali Kulkarni 	struct e4_mstorm_rdma_task_ag_ctx mstorm_ag_context /* mstorm aggregative context */;
536*14b24e2bSVaishali Kulkarni 	struct mstorm_rdma_task_st_ctx mstorm_st_context /* mstorm storm context */;
537*14b24e2bSVaishali Kulkarni 	struct rdif_task_context rdif_context /* rdif context */;
538*14b24e2bSVaishali Kulkarni 	struct ustorm_rdma_task_st_ctx ustorm_st_context /* ustorm storm context */;
539*14b24e2bSVaishali Kulkarni 	struct regpair ustorm_st_padding[2] /* padding */;
540*14b24e2bSVaishali Kulkarni 	struct e4_ustorm_rdma_task_ag_ctx ustorm_ag_context /* ustorm aggregative context */;
541*14b24e2bSVaishali Kulkarni };
542*14b24e2bSVaishali Kulkarni 
543*14b24e2bSVaishali Kulkarni 
544*14b24e2bSVaishali Kulkarni /*
545*14b24e2bSVaishali Kulkarni  * RDMA Tid type enumeration (for register_tid ramrod)
546*14b24e2bSVaishali Kulkarni  */
547*14b24e2bSVaishali Kulkarni enum rdma_tid_type
548*14b24e2bSVaishali Kulkarni {
549*14b24e2bSVaishali Kulkarni 	RDMA_TID_REGISTERED_MR,
550*14b24e2bSVaishali Kulkarni 	RDMA_TID_FMR,
551*14b24e2bSVaishali Kulkarni 	RDMA_TID_MW_TYPE1,
552*14b24e2bSVaishali Kulkarni 	RDMA_TID_MW_TYPE2A,
553*14b24e2bSVaishali Kulkarni 	MAX_RDMA_TID_TYPE
554*14b24e2bSVaishali Kulkarni };
555*14b24e2bSVaishali Kulkarni 
556*14b24e2bSVaishali Kulkarni 
557*14b24e2bSVaishali Kulkarni 
558*14b24e2bSVaishali Kulkarni 
559*14b24e2bSVaishali Kulkarni struct E4XstormRoceConnAgCtxDqExtLdPart
560*14b24e2bSVaishali Kulkarni {
561*14b24e2bSVaishali Kulkarni 	u8 reserved0 /* cdu_validation */;
562*14b24e2bSVaishali Kulkarni 	u8 state /* state */;
563*14b24e2bSVaishali Kulkarni 	u8 flags0;
564*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK      0x1 /* exist_in_qm0 */
565*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT     0
566*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK              0x1 /* exist_in_qm1 */
567*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_SHIFT             1
568*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK              0x1 /* exist_in_qm2 */
569*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_SHIFT             2
570*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK      0x1 /* exist_in_qm3 */
571*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT     3
572*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK              0x1 /* bit4 */
573*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_SHIFT             4
574*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK              0x1 /* cf_array_active */
575*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_SHIFT             5
576*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK              0x1 /* bit6 */
577*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_SHIFT             6
578*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK              0x1 /* bit7 */
579*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_SHIFT             7
580*14b24e2bSVaishali Kulkarni 	u8 flags1;
581*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK              0x1 /* bit8 */
582*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_SHIFT             0
583*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK              0x1 /* bit9 */
584*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_SHIFT             1
585*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK             0x1 /* bit10 */
586*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT            2
587*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK             0x1 /* bit11 */
588*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT            3
589*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_MASK             0x1 /* bit12 */
590*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_SHIFT            4
591*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSTORM_FLUSH_MASK      0x1 /* bit13 */
592*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSTORM_FLUSH_SHIFT     5
593*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_MASK             0x1 /* bit14 */
594*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_SHIFT            6
595*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK      0x1 /* bit15 */
596*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT     7
597*14b24e2bSVaishali Kulkarni 	u8 flags2;
598*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK               0x3 /* timer0cf */
599*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT              0
600*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK               0x3 /* timer1cf */
601*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT              2
602*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK               0x3 /* timer2cf */
603*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT              4
604*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK               0x3 /* timer_stop_all */
605*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT              6
606*14b24e2bSVaishali Kulkarni 	u8 flags3;
607*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK               0x3 /* cf4 */
608*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_SHIFT              0
609*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK               0x3 /* cf5 */
610*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_SHIFT              2
611*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK               0x3 /* cf6 */
612*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_SHIFT              4
613*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK       0x3 /* cf7 */
614*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT      6
615*14b24e2bSVaishali Kulkarni 	u8 flags4;
616*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK               0x3 /* cf8 */
617*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT              0
618*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK               0x3 /* cf9 */
619*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT              2
620*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK              0x3 /* cf10 */
621*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT             4
622*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK              0x3 /* cf11 */
623*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT             6
624*14b24e2bSVaishali Kulkarni 	u8 flags5;
625*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK              0x3 /* cf12 */
626*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT             0
627*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK              0x3 /* cf13 */
628*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT             2
629*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK              0x3 /* cf14 */
630*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_SHIFT             4
631*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK              0x3 /* cf15 */
632*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT             6
633*14b24e2bSVaishali Kulkarni 	u8 flags6;
634*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK              0x3 /* cf16 */
635*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT             0
636*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK              0x3 /* cf_array_cf */
637*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT             2
638*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK              0x3 /* cf18 */
639*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT             4
640*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK              0x3 /* cf19 */
641*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT             6
642*14b24e2bSVaishali Kulkarni 	u8 flags7;
643*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK              0x3 /* cf20 */
644*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT             0
645*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK              0x3 /* cf21 */
646*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT             2
647*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK         0x3 /* cf22 */
648*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT        4
649*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK             0x1 /* cf0en */
650*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT            6
651*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK             0x1 /* cf1en */
652*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT            7
653*14b24e2bSVaishali Kulkarni 	u8 flags8;
654*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK             0x1 /* cf2en */
655*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT            0
656*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK             0x1 /* cf3en */
657*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT            1
658*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK             0x1 /* cf4en */
659*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_SHIFT            2
660*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK             0x1 /* cf5en */
661*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_SHIFT            3
662*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK             0x1 /* cf6en */
663*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_SHIFT            4
664*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK    0x1 /* cf7en */
665*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT   5
666*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK             0x1 /* cf8en */
667*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT            6
668*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK             0x1 /* cf9en */
669*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT            7
670*14b24e2bSVaishali Kulkarni 	u8 flags9;
671*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK            0x1 /* cf10en */
672*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT           0
673*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK            0x1 /* cf11en */
674*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT           1
675*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK            0x1 /* cf12en */
676*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT           2
677*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK            0x1 /* cf13en */
678*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT           3
679*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK            0x1 /* cf14en */
680*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_SHIFT           4
681*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK            0x1 /* cf15en */
682*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT           5
683*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK            0x1 /* cf16en */
684*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT           6
685*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK            0x1 /* cf_array_cf_en */
686*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT           7
687*14b24e2bSVaishali Kulkarni 	u8 flags10;
688*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK            0x1 /* cf18en */
689*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT           0
690*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK            0x1 /* cf19en */
691*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT           1
692*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK            0x1 /* cf20en */
693*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT           2
694*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK            0x1 /* cf21en */
695*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT           3
696*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK      0x1 /* cf22en */
697*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT     4
698*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK            0x1 /* cf23en */
699*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT           5
700*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK           0x1 /* rule0en */
701*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT          6
702*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK           0x1 /* rule1en */
703*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT          7
704*14b24e2bSVaishali Kulkarni 	u8 flags11;
705*14b24e2bSVaishali Kulkarni #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK           0x1 /* rule2en */
706*14b24e2b