1*14b24e2bSVaishali Kulkarni /* 2*14b24e2bSVaishali Kulkarni * CDDL HEADER START 3*14b24e2bSVaishali Kulkarni * 4*14b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the 5*14b24e2bSVaishali Kulkarni * Common Development and Distribution License, v.1, (the "License"). 6*14b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License. 7*14b24e2bSVaishali Kulkarni * 8*14b24e2bSVaishali Kulkarni * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*14b24e2bSVaishali Kulkarni * or http://opensource.org/licenses/CDDL-1.0. 10*14b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions 11*14b24e2bSVaishali Kulkarni * and limitations under the License. 12*14b24e2bSVaishali Kulkarni * 13*14b24e2bSVaishali Kulkarni * When distributing Covered Code, include this CDDL HEADER in each 14*14b24e2bSVaishali Kulkarni * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*14b24e2bSVaishali Kulkarni * If applicable, add the following below this CDDL HEADER, with the 16*14b24e2bSVaishali Kulkarni * fields enclosed by brackets "[]" replaced with your own identifying 17*14b24e2bSVaishali Kulkarni * information: Portions Copyright [yyyy] [name of copyright owner] 18*14b24e2bSVaishali Kulkarni * 19*14b24e2bSVaishali Kulkarni * CDDL HEADER END 20*14b24e2bSVaishali Kulkarni */ 21*14b24e2bSVaishali Kulkarni 22*14b24e2bSVaishali Kulkarni /* 23*14b24e2bSVaishali Kulkarni * Copyright 2014-2017 Cavium, Inc. 24*14b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the Common Development 25*14b24e2bSVaishali Kulkarni * and Distribution License, v.1, (the "License"). 26*14b24e2bSVaishali Kulkarni 27*14b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License. 28*14b24e2bSVaishali Kulkarni 29*14b24e2bSVaishali Kulkarni * You can obtain a copy of the License at available 30*14b24e2bSVaishali Kulkarni * at http://opensource.org/licenses/CDDL-1.0 31*14b24e2bSVaishali Kulkarni 32*14b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions and 33*14b24e2bSVaishali Kulkarni * limitations under the License. 34*14b24e2bSVaishali Kulkarni */ 35*14b24e2bSVaishali Kulkarni 36*14b24e2bSVaishali Kulkarni #ifndef __ECORE_HSI_INIT_TOOL__ 37*14b24e2bSVaishali Kulkarni #define __ECORE_HSI_INIT_TOOL__ 38*14b24e2bSVaishali Kulkarni /**************************************/ 39*14b24e2bSVaishali Kulkarni /* Init Tool HSI constants and macros */ 40*14b24e2bSVaishali Kulkarni /**************************************/ 41*14b24e2bSVaishali Kulkarni 42*14b24e2bSVaishali Kulkarni /* Width of GRC address in bits (addresses are specified in dwords) */ 43*14b24e2bSVaishali Kulkarni #define GRC_ADDR_BITS 23 44*14b24e2bSVaishali Kulkarni #define MAX_GRC_ADDR ((1 << GRC_ADDR_BITS) - 1) 45*14b24e2bSVaishali Kulkarni 46*14b24e2bSVaishali Kulkarni /* indicates an init that should be applied to any phase ID */ 47*14b24e2bSVaishali Kulkarni #define ANY_PHASE_ID 0xffff 48*14b24e2bSVaishali Kulkarni 49*14b24e2bSVaishali Kulkarni /* Max size in dwords of a zipped array */ 50*14b24e2bSVaishali Kulkarni #define MAX_ZIPPED_SIZE 8192 51*14b24e2bSVaishali Kulkarni 52*14b24e2bSVaishali Kulkarni 53*14b24e2bSVaishali Kulkarni enum chip_ids 54*14b24e2bSVaishali Kulkarni { 55*14b24e2bSVaishali Kulkarni CHIP_BB, 56*14b24e2bSVaishali Kulkarni CHIP_K2, 57*14b24e2bSVaishali Kulkarni CHIP_E5, 58*14b24e2bSVaishali Kulkarni MAX_CHIP_IDS 59*14b24e2bSVaishali Kulkarni }; 60*14b24e2bSVaishali Kulkarni 61*14b24e2bSVaishali Kulkarni 62*14b24e2bSVaishali Kulkarni struct fw_asserts_ram_section 63*14b24e2bSVaishali Kulkarni { 64*14b24e2bSVaishali Kulkarni __le16 section_ram_line_offset /* The offset of the section in the RAM in RAM lines (64-bit units) */; 65*14b24e2bSVaishali Kulkarni __le16 section_ram_line_size /* The size of the section in RAM lines (64-bit units) */; 66*14b24e2bSVaishali Kulkarni u8 list_dword_offset /* The offset of the asserts list within the section in dwords */; 67*14b24e2bSVaishali Kulkarni u8 list_element_dword_size /* The size of an assert list element in dwords */; 68*14b24e2bSVaishali Kulkarni u8 list_num_elements /* The number of elements in the asserts list */; 69*14b24e2bSVaishali Kulkarni u8 list_next_index_dword_offset /* The offset of the next list index field within the section in dwords */; 70*14b24e2bSVaishali Kulkarni }; 71*14b24e2bSVaishali Kulkarni 72*14b24e2bSVaishali Kulkarni 73*14b24e2bSVaishali Kulkarni struct fw_ver_num 74*14b24e2bSVaishali Kulkarni { 75*14b24e2bSVaishali Kulkarni u8 major /* Firmware major version number */; 76*14b24e2bSVaishali Kulkarni u8 minor /* Firmware minor version number */; 77*14b24e2bSVaishali Kulkarni u8 rev /* Firmware revision version number */; 78*14b24e2bSVaishali Kulkarni u8 eng /* Firmware engineering version number (for bootleg versions) */; 79*14b24e2bSVaishali Kulkarni }; 80*14b24e2bSVaishali Kulkarni 81*14b24e2bSVaishali Kulkarni struct fw_ver_info 82*14b24e2bSVaishali Kulkarni { 83*14b24e2bSVaishali Kulkarni __le16 tools_ver /* Tools version number */; 84*14b24e2bSVaishali Kulkarni u8 image_id /* FW image ID (e.g. main, l2b, kuku) */; 85*14b24e2bSVaishali Kulkarni u8 reserved1; 86*14b24e2bSVaishali Kulkarni struct fw_ver_num num /* FW version number */; 87*14b24e2bSVaishali Kulkarni __le32 timestamp /* FW Timestamp in unix time (sec. since 1970) */; 88*14b24e2bSVaishali Kulkarni __le32 reserved2; 89*14b24e2bSVaishali Kulkarni }; 90*14b24e2bSVaishali Kulkarni 91*14b24e2bSVaishali Kulkarni struct fw_info 92*14b24e2bSVaishali Kulkarni { 93*14b24e2bSVaishali Kulkarni struct fw_ver_info ver /* FW version information */; 94*14b24e2bSVaishali Kulkarni struct fw_asserts_ram_section fw_asserts_section /* Info regarding the FW asserts section in the Storm RAM */; 95*14b24e2bSVaishali Kulkarni }; 96*14b24e2bSVaishali Kulkarni 97*14b24e2bSVaishali Kulkarni 98*14b24e2bSVaishali Kulkarni struct fw_info_location 99*14b24e2bSVaishali Kulkarni { 100*14b24e2bSVaishali Kulkarni __le32 grc_addr /* GRC address where the fw_info struct is located. */; 101*14b24e2bSVaishali Kulkarni __le32 size /* Size of the fw_info structure (thats located at the grc_addr). */; 102*14b24e2bSVaishali Kulkarni }; 103*14b24e2bSVaishali Kulkarni 104*14b24e2bSVaishali Kulkarni 105*14b24e2bSVaishali Kulkarni 106*14b24e2bSVaishali Kulkarni 107*14b24e2bSVaishali Kulkarni enum init_modes 108*14b24e2bSVaishali Kulkarni { 109*14b24e2bSVaishali Kulkarni MODE_BB_A0_DEPRECATED, 110*14b24e2bSVaishali Kulkarni MODE_BB, 111*14b24e2bSVaishali Kulkarni MODE_K2, 112*14b24e2bSVaishali Kulkarni MODE_ASIC, 113*14b24e2bSVaishali Kulkarni MODE_EMUL_REDUCED, 114*14b24e2bSVaishali Kulkarni MODE_EMUL_FULL, 115*14b24e2bSVaishali Kulkarni MODE_FPGA, 116*14b24e2bSVaishali Kulkarni MODE_CHIPSIM, 117*14b24e2bSVaishali Kulkarni MODE_SF, 118*14b24e2bSVaishali Kulkarni MODE_MF_SD, 119*14b24e2bSVaishali Kulkarni MODE_MF_SI, 120*14b24e2bSVaishali Kulkarni MODE_PORTS_PER_ENG_1, 121*14b24e2bSVaishali Kulkarni MODE_PORTS_PER_ENG_2, 122*14b24e2bSVaishali Kulkarni MODE_PORTS_PER_ENG_4, 123*14b24e2bSVaishali Kulkarni MODE_100G, 124*14b24e2bSVaishali Kulkarni MODE_E5, 125*14b24e2bSVaishali Kulkarni MAX_INIT_MODES 126*14b24e2bSVaishali Kulkarni }; 127*14b24e2bSVaishali Kulkarni 128*14b24e2bSVaishali Kulkarni 129*14b24e2bSVaishali Kulkarni enum init_phases 130*14b24e2bSVaishali Kulkarni { 131*14b24e2bSVaishali Kulkarni PHASE_ENGINE, 132*14b24e2bSVaishali Kulkarni PHASE_PORT, 133*14b24e2bSVaishali Kulkarni PHASE_PF, 134*14b24e2bSVaishali Kulkarni PHASE_VF, 135*14b24e2bSVaishali Kulkarni PHASE_QM_PF, 136*14b24e2bSVaishali Kulkarni MAX_INIT_PHASES 137*14b24e2bSVaishali Kulkarni }; 138*14b24e2bSVaishali Kulkarni 139*14b24e2bSVaishali Kulkarni 140*14b24e2bSVaishali Kulkarni enum init_split_types 141*14b24e2bSVaishali Kulkarni { 142*14b24e2bSVaishali Kulkarni SPLIT_TYPE_NONE, 143*14b24e2bSVaishali Kulkarni SPLIT_TYPE_PORT, 144*14b24e2bSVaishali Kulkarni SPLIT_TYPE_PF, 145*14b24e2bSVaishali Kulkarni SPLIT_TYPE_PORT_PF, 146*14b24e2bSVaishali Kulkarni SPLIT_TYPE_VF, 147*14b24e2bSVaishali Kulkarni MAX_INIT_SPLIT_TYPES 148*14b24e2bSVaishali Kulkarni }; 149*14b24e2bSVaishali Kulkarni 150*14b24e2bSVaishali Kulkarni 151*14b24e2bSVaishali Kulkarni /* 152*14b24e2bSVaishali Kulkarni * Binary buffer header 153*14b24e2bSVaishali Kulkarni */ 154*14b24e2bSVaishali Kulkarni struct bin_buffer_hdr 155*14b24e2bSVaishali Kulkarni { 156*14b24e2bSVaishali Kulkarni __le32 offset /* buffer offset in bytes from the beginning of the binary file */; 157*14b24e2bSVaishali Kulkarni __le32 length /* buffer length in bytes */; 158*14b24e2bSVaishali Kulkarni }; 159*14b24e2bSVaishali Kulkarni 160*14b24e2bSVaishali Kulkarni 161*14b24e2bSVaishali Kulkarni /* 162*14b24e2bSVaishali Kulkarni * binary init buffer types 163*14b24e2bSVaishali Kulkarni */ 164*14b24e2bSVaishali Kulkarni enum bin_init_buffer_type 165*14b24e2bSVaishali Kulkarni { 166*14b24e2bSVaishali Kulkarni BIN_BUF_INIT_FW_VER_INFO /* fw_ver_info struct */, 167*14b24e2bSVaishali Kulkarni BIN_BUF_INIT_CMD /* init commands */, 168*14b24e2bSVaishali Kulkarni BIN_BUF_INIT_VAL /* init data */, 169*14b24e2bSVaishali Kulkarni BIN_BUF_INIT_MODE_TREE /* init modes tree */, 170*14b24e2bSVaishali Kulkarni BIN_BUF_INIT_IRO /* internal RAM offsets */, 171*14b24e2bSVaishali Kulkarni MAX_BIN_INIT_BUFFER_TYPE 172*14b24e2bSVaishali Kulkarni }; 173*14b24e2bSVaishali Kulkarni 174*14b24e2bSVaishali Kulkarni 175*14b24e2bSVaishali Kulkarni /* 176*14b24e2bSVaishali Kulkarni * init array header: raw 177*14b24e2bSVaishali Kulkarni */ 178*14b24e2bSVaishali Kulkarni struct init_array_raw_hdr 179*14b24e2bSVaishali Kulkarni { 180*14b24e2bSVaishali Kulkarni __le32 data; 181*14b24e2bSVaishali Kulkarni #define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF /* Init array type, from init_array_types enum */ 182*14b24e2bSVaishali Kulkarni #define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0 183*14b24e2bSVaishali Kulkarni #define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF /* init array params */ 184*14b24e2bSVaishali Kulkarni #define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4 185*14b24e2bSVaishali Kulkarni }; 186*14b24e2bSVaishali Kulkarni 187*14b24e2bSVaishali Kulkarni /* 188*14b24e2bSVaishali Kulkarni * init array header: standard 189*14b24e2bSVaishali Kulkarni */ 190*14b24e2bSVaishali Kulkarni struct init_array_standard_hdr 191*14b24e2bSVaishali Kulkarni { 192*14b24e2bSVaishali Kulkarni __le32 data; 193*14b24e2bSVaishali Kulkarni #define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF /* Init array type, from init_array_types enum */ 194*14b24e2bSVaishali Kulkarni #define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0 195*14b24e2bSVaishali Kulkarni #define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF /* Init array size (in dwords) */ 196*14b24e2bSVaishali Kulkarni #define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4 197*14b24e2bSVaishali Kulkarni }; 198*14b24e2bSVaishali Kulkarni 199*14b24e2bSVaishali Kulkarni /* 200*14b24e2bSVaishali Kulkarni * init array header: zipped 201*14b24e2bSVaishali Kulkarni */ 202*14b24e2bSVaishali Kulkarni struct init_array_zipped_hdr 203*14b24e2bSVaishali Kulkarni { 204*14b24e2bSVaishali Kulkarni __le32 data; 205*14b24e2bSVaishali Kulkarni #define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF /* Init array type, from init_array_types enum */ 206*14b24e2bSVaishali Kulkarni #define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0 207*14b24e2bSVaishali Kulkarni #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF /* Init array zipped size (in bytes) */ 208*14b24e2bSVaishali Kulkarni #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4 209*14b24e2bSVaishali Kulkarni }; 210*14b24e2bSVaishali Kulkarni 211*14b24e2bSVaishali Kulkarni /* 212*14b24e2bSVaishali Kulkarni * init array header: pattern 213*14b24e2bSVaishali Kulkarni */ 214*14b24e2bSVaishali Kulkarni struct init_array_pattern_hdr 215*14b24e2bSVaishali Kulkarni { 216*14b24e2bSVaishali Kulkarni __le32 data; 217*14b24e2bSVaishali Kulkarni #define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF /* Init array type, from init_array_types enum */ 218*14b24e2bSVaishali Kulkarni #define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0 219*14b24e2bSVaishali Kulkarni #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK 0xF /* pattern size in dword */ 220*14b24e2bSVaishali Kulkarni #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4 221*14b24e2bSVaishali Kulkarni #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK 0xFFFFFF /* pattern repetitions */ 222*14b24e2bSVaishali Kulkarni #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT 8 223*14b24e2bSVaishali Kulkarni }; 224*14b24e2bSVaishali Kulkarni 225*14b24e2bSVaishali Kulkarni /* 226*14b24e2bSVaishali Kulkarni * init array header union 227*14b24e2bSVaishali Kulkarni */ 228*14b24e2bSVaishali Kulkarni union init_array_hdr 229*14b24e2bSVaishali Kulkarni { 230*14b24e2bSVaishali Kulkarni struct init_array_raw_hdr raw /* raw init array header */; 231*14b24e2bSVaishali Kulkarni struct init_array_standard_hdr standard /* standard init array header */; 232*14b24e2bSVaishali Kulkarni struct init_array_zipped_hdr zipped /* zipped init array header */; 233*14b24e2bSVaishali Kulkarni struct init_array_pattern_hdr pattern /* pattern init array header */; 234*14b24e2bSVaishali Kulkarni }; 235*14b24e2bSVaishali Kulkarni 236*14b24e2bSVaishali Kulkarni 237*14b24e2bSVaishali Kulkarni 238*14b24e2bSVaishali Kulkarni 239*14b24e2bSVaishali Kulkarni 240*14b24e2bSVaishali Kulkarni /* 241*14b24e2bSVaishali Kulkarni * init array types 242*14b24e2bSVaishali Kulkarni */ 243*14b24e2bSVaishali Kulkarni enum init_array_types 244*14b24e2bSVaishali Kulkarni { 245*14b24e2bSVaishali Kulkarni INIT_ARR_STANDARD /* standard init array */, 246*14b24e2bSVaishali Kulkarni INIT_ARR_ZIPPED /* zipped init array */, 247*14b24e2bSVaishali Kulkarni INIT_ARR_PATTERN /* a repeated pattern */, 248*14b24e2bSVaishali Kulkarni MAX_INIT_ARRAY_TYPES 249*14b24e2bSVaishali Kulkarni }; 250*14b24e2bSVaishali Kulkarni 251*14b24e2bSVaishali Kulkarni 252*14b24e2bSVaishali Kulkarni 253*14b24e2bSVaishali Kulkarni /* 254*14b24e2bSVaishali Kulkarni * init operation: callback 255*14b24e2bSVaishali Kulkarni */ 256*14b24e2bSVaishali Kulkarni struct init_callback_op 257*14b24e2bSVaishali Kulkarni { 258*14b24e2bSVaishali Kulkarni __le32 op_data; 259*14b24e2bSVaishali Kulkarni #define INIT_CALLBACK_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */ 260*14b24e2bSVaishali Kulkarni #define INIT_CALLBACK_OP_OP_SHIFT 0 261*14b24e2bSVaishali Kulkarni #define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF 262*14b24e2bSVaishali Kulkarni #define INIT_CALLBACK_OP_RESERVED_SHIFT 4 263*14b24e2bSVaishali Kulkarni __le16 callback_id /* Callback ID */; 264*14b24e2bSVaishali Kulkarni __le16 block_id /* Blocks ID */; 265*14b24e2bSVaishali Kulkarni }; 266*14b24e2bSVaishali Kulkarni 267*14b24e2bSVaishali Kulkarni 268*14b24e2bSVaishali Kulkarni /* 269*14b24e2bSVaishali Kulkarni * init operation: delay 270*14b24e2bSVaishali Kulkarni */ 271*14b24e2bSVaishali Kulkarni struct init_delay_op 272*14b24e2bSVaishali Kulkarni { 273*14b24e2bSVaishali Kulkarni __le32 op_data; 274*14b24e2bSVaishali Kulkarni #define INIT_DELAY_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */ 275*14b24e2bSVaishali Kulkarni #define INIT_DELAY_OP_OP_SHIFT 0 276*14b24e2bSVaishali Kulkarni #define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF 277*14b24e2bSVaishali Kulkarni #define INIT_DELAY_OP_RESERVED_SHIFT 4 278*14b24e2bSVaishali Kulkarni __le32 delay /* delay in us */; 279*14b24e2bSVaishali Kulkarni }; 280*14b24e2bSVaishali Kulkarni 281*14b24e2bSVaishali Kulkarni 282*14b24e2bSVaishali Kulkarni /* 283*14b24e2bSVaishali Kulkarni * init operation: if_mode 284*14b24e2bSVaishali Kulkarni */ 285*14b24e2bSVaishali Kulkarni struct init_if_mode_op 286*14b24e2bSVaishali Kulkarni { 287*14b24e2bSVaishali Kulkarni __le32 op_data; 288*14b24e2bSVaishali Kulkarni #define INIT_IF_MODE_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */ 289*14b24e2bSVaishali Kulkarni #define INIT_IF_MODE_OP_OP_SHIFT 0 290*14b24e2bSVaishali Kulkarni #define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF 291*14b24e2bSVaishali Kulkarni #define INIT_IF_MODE_OP_RESERVED1_SHIFT 4 292*14b24e2bSVaishali Kulkarni #define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF /* Commands to skip if the modes dont match */ 293*14b24e2bSVaishali Kulkarni #define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16 294*14b24e2bSVaishali Kulkarni __le16 reserved2; 295*14b24e2bSVaishali Kulkarni __le16 modes_buf_offset /* offset (in bytes) in modes expression buffer */; 296*14b24e2bSVaishali Kulkarni }; 297*14b24e2bSVaishali Kulkarni 298*14b24e2bSVaishali Kulkarni 299*14b24e2bSVaishali Kulkarni /* 300*14b24e2bSVaishali Kulkarni * init operation: if_phase 301*14b24e2bSVaishali Kulkarni */ 302*14b24e2bSVaishali Kulkarni struct init_if_phase_op 303*14b24e2bSVaishali Kulkarni { 304*14b24e2bSVaishali Kulkarni __le32 op_data; 305*14b24e2bSVaishali Kulkarni #define INIT_IF_PHASE_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */ 306*14b24e2bSVaishali Kulkarni #define INIT_IF_PHASE_OP_OP_SHIFT 0 307*14b24e2bSVaishali Kulkarni #define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK 0x1 /* Indicates if DMAE is enabled in this phase */ 308*14b24e2bSVaishali Kulkarni #define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT 4 309*14b24e2bSVaishali Kulkarni #define INIT_IF_PHASE_OP_RESERVED1_MASK 0x7FF 310*14b24e2bSVaishali Kulkarni #define INIT_IF_PHASE_OP_RESERVED1_SHIFT 5 311*14b24e2bSVaishali Kulkarni #define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF /* Commands to skip if the phases dont match */ 312*14b24e2bSVaishali Kulkarni #define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT 16 313*14b24e2bSVaishali Kulkarni __le32 phase_data; 314*14b24e2bSVaishali Kulkarni #define INIT_IF_PHASE_OP_PHASE_MASK 0xFF /* Init phase */ 315*14b24e2bSVaishali Kulkarni #define INIT_IF_PHASE_OP_PHASE_SHIFT 0 316*14b24e2bSVaishali Kulkarni #define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF 317*14b24e2bSVaishali Kulkarni #define INIT_IF_PHASE_OP_RESERVED2_SHIFT 8 318*14b24e2bSVaishali Kulkarni #define INIT_IF_PHASE_OP_PHASE_ID_MASK 0xFFFF /* Init phase ID */ 319*14b24e2bSVaishali Kulkarni #define INIT_IF_PHASE_OP_PHASE_ID_SHIFT 16 320*14b24e2bSVaishali Kulkarni }; 321*14b24e2bSVaishali Kulkarni 322*14b24e2bSVaishali Kulkarni 323*14b24e2bSVaishali Kulkarni /* 324*14b24e2bSVaishali Kulkarni * init mode operators 325*14b24e2bSVaishali Kulkarni */ 326*14b24e2bSVaishali Kulkarni enum init_mode_ops 327*14b24e2bSVaishali Kulkarni { 328*14b24e2bSVaishali Kulkarni INIT_MODE_OP_NOT /* init mode not operator */, 329*14b24e2bSVaishali Kulkarni INIT_MODE_OP_OR /* init mode or operator */, 330*14b24e2bSVaishali Kulkarni INIT_MODE_OP_AND /* init mode and operator */, 331*14b24e2bSVaishali Kulkarni MAX_INIT_MODE_OPS 332*14b24e2bSVaishali Kulkarni }; 333*14b24e2bSVaishali Kulkarni 334*14b24e2bSVaishali Kulkarni 335*14b24e2bSVaishali Kulkarni /* 336*14b24e2bSVaishali Kulkarni * init operation: raw 337*14b24e2bSVaishali Kulkarni */ 338*14b24e2bSVaishali Kulkarni struct init_raw_op 339*14b24e2bSVaishali Kulkarni { 340*14b24e2bSVaishali Kulkarni __le32 op_data; 341*14b24e2bSVaishali Kulkarni #define INIT_RAW_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */ 342*14b24e2bSVaishali Kulkarni #define INIT_RAW_OP_OP_SHIFT 0 343*14b24e2bSVaishali Kulkarni #define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF /* init param 1 */ 344*14b24e2bSVaishali Kulkarni #define INIT_RAW_OP_PARAM1_SHIFT 4 345*14b24e2bSVaishali Kulkarni __le32 param2 /* Init param 2 */; 346*14b24e2bSVaishali Kulkarni }; 347*14b24e2bSVaishali Kulkarni 348*14b24e2bSVaishali Kulkarni /* 349*14b24e2bSVaishali Kulkarni * init array params 350*14b24e2bSVaishali Kulkarni */ 351*14b24e2bSVaishali Kulkarni struct init_op_array_params 352*14b24e2bSVaishali Kulkarni { 353*14b24e2bSVaishali Kulkarni __le16 size /* array size in dwords */; 354*14b24e2bSVaishali Kulkarni __le16 offset /* array start offset in dwords */; 355*14b24e2bSVaishali Kulkarni }; 356*14b24e2bSVaishali Kulkarni 357*14b24e2bSVaishali Kulkarni /* 358*14b24e2bSVaishali Kulkarni * Write init operation arguments 359*14b24e2bSVaishali Kulkarni */ 360*14b24e2bSVaishali Kulkarni union init_write_args 361*14b24e2bSVaishali Kulkarni { 362*14b24e2bSVaishali Kulkarni __le32 inline_val /* value to write, used when init source is INIT_SRC_INLINE */; 363*14b24e2bSVaishali Kulkarni __le32 zeros_count /* number of zeros to write, used when init source is INIT_SRC_ZEROS */; 364*14b24e2bSVaishali Kulkarni __le32 array_offset /* array offset to write, used when init source is INIT_SRC_ARRAY */; 365*14b24e2bSVaishali Kulkarni struct init_op_array_params runtime /* runtime array params to write, used when init source is INIT_SRC_RUNTIME */; 366*14b24e2bSVaishali Kulkarni }; 367*14b24e2bSVaishali Kulkarni 368*14b24e2bSVaishali Kulkarni /* 369*14b24e2bSVaishali Kulkarni * init operation: write 370*14b24e2bSVaishali Kulkarni */ 371*14b24e2bSVaishali Kulkarni struct init_write_op 372*14b24e2bSVaishali Kulkarni { 373*14b24e2bSVaishali Kulkarni __le32 data; 374*14b24e2bSVaishali Kulkarni #define INIT_WRITE_OP_OP_MASK 0xF /* init operation, from init_op_types enum */ 375*14b24e2bSVaishali Kulkarni #define INIT_WRITE_OP_OP_SHIFT 0 376*14b24e2bSVaishali Kulkarni #define INIT_WRITE_OP_SOURCE_MASK 0x7 /* init source type, taken from init_source_types enum */ 377*14b24e2bSVaishali Kulkarni #define INIT_WRITE_OP_SOURCE_SHIFT 4 378*14b24e2bSVaishali Kulkarni #define INIT_WRITE_OP_RESERVED_MASK 0x1 379*14b24e2bSVaishali Kulkarni #define INIT_WRITE_OP_RESERVED_SHIFT 7 380*14b24e2bSVaishali Kulkarni #define INIT_WRITE_OP_WIDE_BUS_MASK 0x1 /* indicates if the register is wide-bus */ 381*14b24e2bSVaishali Kulkarni #define INIT_WRITE_OP_WIDE_BUS_SHIFT 8 382*14b24e2bSVaishali Kulkarni #define INIT_WRITE_OP_ADDRESS_MASK 0x7FFFFF /* internal (absolute) GRC address, in dwords */ 383*14b24e2bSVaishali Kulkarni #define INIT_WRITE_OP_ADDRESS_SHIFT 9 384*14b24e2bSVaishali Kulkarni union init_write_args args /* Write init operation arguments */; 385*14b24e2bSVaishali Kulkarni }; 386*14b24e2bSVaishali Kulkarni 387*14b24e2bSVaishali Kulkarni /* 388*14b24e2bSVaishali Kulkarni * init operation: read 389*14b24e2bSVaishali Kulkarni */ 390*14b24e2bSVaishali Kulkarni struct init_read_op 391*14b24e2bSVaishali Kulkarni { 392*14b24e2bSVaishali Kulkarni __le32 op_data; 393*14b24e2bSVaishali Kulkarni #define INIT_READ_OP_OP_MASK 0xF /* init operation, from init_op_types enum */ 394*14b24e2bSVaishali Kulkarni #define INIT_READ_OP_OP_SHIFT 0 395*14b24e2bSVaishali Kulkarni #define INIT_READ_OP_POLL_TYPE_MASK 0xF /* polling type, from init_poll_types enum */ 396*14b24e2bSVaishali Kulkarni #define INIT_READ_OP_POLL_TYPE_SHIFT 4 397*14b24e2bSVaishali Kulkarni #define INIT_READ_OP_RESERVED_MASK 0x1 398*14b24e2bSVaishali Kulkarni #define INIT_READ_OP_RESERVED_SHIFT 8 399*14b24e2bSVaishali Kulkarni #define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF /* internal (absolute) GRC address, in dwords */ 400*14b24e2bSVaishali Kulkarni #define INIT_READ_OP_ADDRESS_SHIFT 9 401*14b24e2bSVaishali Kulkarni __le32 expected_val /* expected polling value, used only when polling is done */; 402*14b24e2bSVaishali Kulkarni }; 403*14b24e2bSVaishali Kulkarni 404*14b24e2bSVaishali Kulkarni /* 405*14b24e2bSVaishali Kulkarni * Init operations union 406*14b24e2bSVaishali Kulkarni */ 407*14b24e2bSVaishali Kulkarni union init_op 408*14b24e2bSVaishali Kulkarni { 409*14b24e2bSVaishali Kulkarni struct init_raw_op raw /* raw init operation */; 410*14b24e2bSVaishali Kulkarni struct init_write_op write /* write init operation */; 411*14b24e2bSVaishali Kulkarni struct init_read_op read /* read init operation */; 412*14b24e2bSVaishali Kulkarni struct init_if_mode_op if_mode /* if_mode init operation */; 413*14b24e2bSVaishali Kulkarni struct init_if_phase_op if_phase /* if_phase init operation */; 414*14b24e2bSVaishali Kulkarni struct init_callback_op callback /* callback init operation */; 415*14b24e2bSVaishali Kulkarni struct init_delay_op delay /* delay init operation */; 416*14b24e2bSVaishali Kulkarni }; 417*14b24e2bSVaishali Kulkarni 418*14b24e2bSVaishali Kulkarni 419*14b24e2bSVaishali Kulkarni 420*14b24e2bSVaishali Kulkarni /* 421*14b24e2bSVaishali Kulkarni * Init command operation types 422*14b24e2bSVaishali Kulkarni */ 423*14b24e2bSVaishali Kulkarni enum init_op_types 424*14b24e2bSVaishali Kulkarni { 425*14b24e2bSVaishali Kulkarni INIT_OP_READ /* GRC read init command */, 426*14b24e2bSVaishali Kulkarni INIT_OP_WRITE /* GRC write init command */, 427*14b24e2bSVaishali Kulkarni INIT_OP_IF_MODE /* Skip init commands if the init modes expression doesnt match */, 428*14b24e2bSVaishali Kulkarni INIT_OP_IF_PHASE /* Skip init commands if the init phase doesnt match */, 429*14b24e2bSVaishali Kulkarni INIT_OP_DELAY /* delay init command */, 430*14b24e2bSVaishali Kulkarni INIT_OP_CALLBACK /* callback init command */, 431*14b24e2bSVaishali Kulkarni MAX_INIT_OP_TYPES 432*14b24e2bSVaishali Kulkarni }; 433*14b24e2bSVaishali Kulkarni 434*14b24e2bSVaishali Kulkarni 435*14b24e2bSVaishali Kulkarni /* 436*14b24e2bSVaishali Kulkarni * init polling types 437*14b24e2bSVaishali Kulkarni */ 438*14b24e2bSVaishali Kulkarni enum init_poll_types 439*14b24e2bSVaishali Kulkarni { 440*14b24e2bSVaishali Kulkarni INIT_POLL_NONE /* No polling */, 441*14b24e2bSVaishali Kulkarni INIT_POLL_EQ /* init value is included in the init command */, 442*14b24e2bSVaishali Kulkarni INIT_POLL_OR /* init value is all zeros */, 443*14b24e2bSVaishali Kulkarni INIT_POLL_AND /* init value is an array of values */, 444*14b24e2bSVaishali Kulkarni MAX_INIT_POLL_TYPES 445*14b24e2bSVaishali Kulkarni }; 446*14b24e2bSVaishali Kulkarni 447*14b24e2bSVaishali Kulkarni 448*14b24e2bSVaishali Kulkarni 449*14b24e2bSVaishali Kulkarni 450*14b24e2bSVaishali Kulkarni /* 451*14b24e2bSVaishali Kulkarni * init source types 452*14b24e2bSVaishali Kulkarni */ 453*14b24e2bSVaishali Kulkarni enum init_source_types 454*14b24e2bSVaishali Kulkarni { 455*14b24e2bSVaishali Kulkarni INIT_SRC_INLINE /* init value is included in the init command */, 456*14b24e2bSVaishali Kulkarni INIT_SRC_ZEROS /* init value is all zeros */, 457*14b24e2bSVaishali Kulkarni INIT_SRC_ARRAY /* init value is an array of values */, 458*14b24e2bSVaishali Kulkarni INIT_SRC_RUNTIME /* init value is provided during runtime */, 459*14b24e2bSVaishali Kulkarni MAX_INIT_SOURCE_TYPES 460*14b24e2bSVaishali Kulkarni }; 461*14b24e2bSVaishali Kulkarni 462*14b24e2bSVaishali Kulkarni 463*14b24e2bSVaishali Kulkarni 464*14b24e2bSVaishali Kulkarni 465*14b24e2bSVaishali Kulkarni /* 466*14b24e2bSVaishali Kulkarni * Internal RAM Offsets macro data 467*14b24e2bSVaishali Kulkarni */ 468*14b24e2bSVaishali Kulkarni struct iro 469*14b24e2bSVaishali Kulkarni { 470*14b24e2bSVaishali Kulkarni __le32 base /* RAM field offset */; 471*14b24e2bSVaishali Kulkarni __le16 m1 /* multiplier 1 */; 472*14b24e2bSVaishali Kulkarni __le16 m2 /* multiplier 2 */; 473*14b24e2bSVaishali Kulkarni __le16 m3 /* multiplier 3 */; 474*14b24e2bSVaishali Kulkarni __le16 size /* RAM field size */; 475*14b24e2bSVaishali Kulkarni }; 476*14b24e2bSVaishali Kulkarni 477*14b24e2bSVaishali Kulkarni #endif /* __ECORE_HSI_INIT_TOOL__ */ 478