1*14b24e2bSVaishali Kulkarni /*
2*14b24e2bSVaishali Kulkarni * CDDL HEADER START
3*14b24e2bSVaishali Kulkarni *
4*14b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the
5*14b24e2bSVaishali Kulkarni * Common Development and Distribution License, v.1,  (the "License").
6*14b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License.
7*14b24e2bSVaishali Kulkarni *
8*14b24e2bSVaishali Kulkarni * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9*14b24e2bSVaishali Kulkarni * or http://opensource.org/licenses/CDDL-1.0.
10*14b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions
11*14b24e2bSVaishali Kulkarni * and limitations under the License.
12*14b24e2bSVaishali Kulkarni *
13*14b24e2bSVaishali Kulkarni * When distributing Covered Code, include this CDDL HEADER in each
14*14b24e2bSVaishali Kulkarni * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15*14b24e2bSVaishali Kulkarni * If applicable, add the following below this CDDL HEADER, with the
16*14b24e2bSVaishali Kulkarni * fields enclosed by brackets "[]" replaced with your own identifying
17*14b24e2bSVaishali Kulkarni * information: Portions Copyright [yyyy] [name of copyright owner]
18*14b24e2bSVaishali Kulkarni *
19*14b24e2bSVaishali Kulkarni * CDDL HEADER END
20*14b24e2bSVaishali Kulkarni */
21*14b24e2bSVaishali Kulkarni 
22*14b24e2bSVaishali Kulkarni /*
23*14b24e2bSVaishali Kulkarni * Copyright 2014-2017 Cavium, Inc.
24*14b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the Common Development
25*14b24e2bSVaishali Kulkarni * and Distribution License, v.1,  (the "License").
26*14b24e2bSVaishali Kulkarni 
27*14b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License.
28*14b24e2bSVaishali Kulkarni 
29*14b24e2bSVaishali Kulkarni * You can obtain a copy of the License at available
30*14b24e2bSVaishali Kulkarni * at http://opensource.org/licenses/CDDL-1.0
31*14b24e2bSVaishali Kulkarni 
32*14b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions and
33*14b24e2bSVaishali Kulkarni * limitations under the License.
34*14b24e2bSVaishali Kulkarni */
35*14b24e2bSVaishali Kulkarni 
36*14b24e2bSVaishali Kulkarni #ifndef __ECORE_HSI_FCOE__
37*14b24e2bSVaishali Kulkarni #define __ECORE_HSI_FCOE__
38*14b24e2bSVaishali Kulkarni /****************************************/
39*14b24e2bSVaishali Kulkarni /* Add include to common storage target */
40*14b24e2bSVaishali Kulkarni /****************************************/
41*14b24e2bSVaishali Kulkarni #include "storage_common.h"
42*14b24e2bSVaishali Kulkarni 
43*14b24e2bSVaishali Kulkarni /************************************************************************/
44*14b24e2bSVaishali Kulkarni /* Add include to common fcoe target for both eCore and protocol driver */
45*14b24e2bSVaishali Kulkarni /************************************************************************/
46*14b24e2bSVaishali Kulkarni #include "fcoe_common.h"
47*14b24e2bSVaishali Kulkarni 
48*14b24e2bSVaishali Kulkarni 
49*14b24e2bSVaishali Kulkarni /*
50*14b24e2bSVaishali Kulkarni  * The fcoe storm context of Ystorm
51*14b24e2bSVaishali Kulkarni  */
52*14b24e2bSVaishali Kulkarni struct ystorm_fcoe_conn_st_ctx
53*14b24e2bSVaishali Kulkarni {
54*14b24e2bSVaishali Kulkarni 	u8 func_mode /* Function mode */;
55*14b24e2bSVaishali Kulkarni 	u8 cos /* Transmission cos */;
56*14b24e2bSVaishali Kulkarni 	u8 conf_version /* Is dcb_version or vntag_version changed */;
57*14b24e2bSVaishali Kulkarni 	u8 eth_hdr_size /* Ethernet header size */;
58*14b24e2bSVaishali Kulkarni 	__le16 stat_ram_addr /* Statistics ram adderss */;
59*14b24e2bSVaishali Kulkarni 	__le16 mtu /* MTU limitation */;
60*14b24e2bSVaishali Kulkarni 	__le16 max_fc_payload_len /* Max payload length according to target limitation and mtu. 8 bytes aligned (required for protection fast-path) */;
61*14b24e2bSVaishali Kulkarni 	__le16 tx_max_fc_pay_len /* Max payload length according to target limitation */;
62*14b24e2bSVaishali Kulkarni 	u8 fcp_cmd_size /* FCP cmd size. for performance reasons */;
63*14b24e2bSVaishali Kulkarni 	u8 fcp_rsp_size /* FCP RSP size. for performance reasons */;
64*14b24e2bSVaishali Kulkarni 	__le16 mss /* MSS for PBF (MSS we negotiate with target - protection data per segment. If we are not in perf mode it will be according to worse case) */;
65*14b24e2bSVaishali Kulkarni 	struct regpair reserved;
66*14b24e2bSVaishali Kulkarni 	__le16 min_frame_size /* The minimum ETH frame size required for transmission (including ETH header) */;
67*14b24e2bSVaishali Kulkarni 	u8 protection_info_flags;
68*14b24e2bSVaishali Kulkarni #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK  0x1 /* Does this connection support protection (if couple of GOS share this connection it× â‚¬â„¢s enough that one of them support protection) */
69*14b24e2bSVaishali Kulkarni #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 0
70*14b24e2bSVaishali Kulkarni #define YSTORM_FCOE_CONN_ST_CTX_VALID_MASK               0x1 /* Are we in protection perf mode (there is only one protection mode for this connection and we manage to create mss that contain fixed amount of protection segment and we are only restrict by the target limitation and not line mss this is critical since if line mss restrict us we can× â‚¬â„¢t rely on this size × â‚¬â€œ it depends on vlan num) */
71*14b24e2bSVaishali Kulkarni #define YSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT              1
72*14b24e2bSVaishali Kulkarni #define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_MASK           0x3F
73*14b24e2bSVaishali Kulkarni #define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_SHIFT          2
74*14b24e2bSVaishali Kulkarni 	u8 dst_protection_per_mss /* Destination Protection data per mss (if we are not in perf mode it will be worse case). Destination is the data add/remove from the transmitted packet (as opposed to src which is data validate by the nic they might not be identical) */;
75*14b24e2bSVaishali Kulkarni 	u8 src_protection_per_mss /* Source Protection data per mss (if we are not in perf mode it will be worse case). Source  is the data validated by the nic  (as opposed to destination which is data add/remove from the transmitted packet they might not be identical) */;
76*14b24e2bSVaishali Kulkarni 	u8 ptu_log_page_size /* 0-4K, 1-8K, 2-16K, 3-32K... */;
77*14b24e2bSVaishali Kulkarni 	u8 flags;
78*14b24e2bSVaishali Kulkarni #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK     0x1 /* Inner Vlan flag */
79*14b24e2bSVaishali Kulkarni #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT    0
80*14b24e2bSVaishali Kulkarni #define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK     0x1 /* Outer Vlan flag */
81*14b24e2bSVaishali Kulkarni #define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT    1
82*14b24e2bSVaishali Kulkarni #define YSTORM_FCOE_CONN_ST_CTX_RSRV_MASK                0x3F
83*14b24e2bSVaishali Kulkarni #define YSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT               2
84*14b24e2bSVaishali Kulkarni 	u8 fcp_xfer_size /* FCP xfer size. for performance reasons */;
85*14b24e2bSVaishali Kulkarni };
86*14b24e2bSVaishali Kulkarni 
87*14b24e2bSVaishali Kulkarni /*
88*14b24e2bSVaishali Kulkarni  * FCoE 16-bits vlan structure
89*14b24e2bSVaishali Kulkarni  */
90*14b24e2bSVaishali Kulkarni struct fcoe_vlan_fields
91*14b24e2bSVaishali Kulkarni {
92*14b24e2bSVaishali Kulkarni 	__le16 fields;
93*14b24e2bSVaishali Kulkarni #define FCOE_VLAN_FIELDS_VID_MASK  0xFFF
94*14b24e2bSVaishali Kulkarni #define FCOE_VLAN_FIELDS_VID_SHIFT 0
95*14b24e2bSVaishali Kulkarni #define FCOE_VLAN_FIELDS_CLI_MASK  0x1
96*14b24e2bSVaishali Kulkarni #define FCOE_VLAN_FIELDS_CLI_SHIFT 12
97*14b24e2bSVaishali Kulkarni #define FCOE_VLAN_FIELDS_PRI_MASK  0x7
98*14b24e2bSVaishali Kulkarni #define FCOE_VLAN_FIELDS_PRI_SHIFT 13
99*14b24e2bSVaishali Kulkarni };
100*14b24e2bSVaishali Kulkarni 
101*14b24e2bSVaishali Kulkarni /*
102*14b24e2bSVaishali Kulkarni  * FCoE 16-bits vlan union
103*14b24e2bSVaishali Kulkarni  */
104*14b24e2bSVaishali Kulkarni union fcoe_vlan_field_union
105*14b24e2bSVaishali Kulkarni {
106*14b24e2bSVaishali Kulkarni 	struct fcoe_vlan_fields fields /* Parameters field */;
107*14b24e2bSVaishali Kulkarni 	__le16 val /* Global value */;
108*14b24e2bSVaishali Kulkarni };
109*14b24e2bSVaishali Kulkarni 
110*14b24e2bSVaishali Kulkarni /*
111*14b24e2bSVaishali Kulkarni  * FCoE 16-bits vlan, vif union
112*14b24e2bSVaishali Kulkarni  */
113*14b24e2bSVaishali Kulkarni union fcoe_vlan_vif_field_union
114*14b24e2bSVaishali Kulkarni {
115*14b24e2bSVaishali Kulkarni 	union fcoe_vlan_field_union vlan /* Vlan */;
116*14b24e2bSVaishali Kulkarni 	__le16 vif /* VIF */;
117*14b24e2bSVaishali Kulkarni };
118*14b24e2bSVaishali Kulkarni 
119*14b24e2bSVaishali Kulkarni /*
120*14b24e2bSVaishali Kulkarni  * Ethernet context section
121*14b24e2bSVaishali Kulkarni  */
122*14b24e2bSVaishali Kulkarni struct pstorm_fcoe_eth_context_section
123*14b24e2bSVaishali Kulkarni {
124*14b24e2bSVaishali Kulkarni 	u8 remote_addr_3 /* Remote Mac Address, used in PBF Header Builder Command */;
125*14b24e2bSVaishali Kulkarni 	u8 remote_addr_2 /* Remote Mac Address, used in PBF Header Builder Command */;
126*14b24e2bSVaishali Kulkarni 	u8 remote_addr_1 /* Remote Mac Address, used in PBF Header Builder Command */;
127*14b24e2bSVaishali Kulkarni 	u8 remote_addr_0 /* Remote Mac Address, used in PBF Header Builder Command */;
128*14b24e2bSVaishali Kulkarni 	u8 local_addr_1 /* Local Mac Address, used in PBF Header Builder Command */;
129*14b24e2bSVaishali Kulkarni 	u8 local_addr_0 /* Local Mac Address, used in PBF Header Builder Command */;
130*14b24e2bSVaishali Kulkarni 	u8 remote_addr_5 /* Remote Mac Address, used in PBF Header Builder Command */;
131*14b24e2bSVaishali Kulkarni 	u8 remote_addr_4 /* Remote Mac Address, used in PBF Header Builder Command */;
132*14b24e2bSVaishali Kulkarni 	u8 local_addr_5 /* Local Mac Address, used in PBF Header Builder Command */;
133*14b24e2bSVaishali Kulkarni 	u8 local_addr_4 /* Loca lMac Address, used in PBF Header Builder Command */;
134*14b24e2bSVaishali Kulkarni 	u8 local_addr_3 /* Local Mac Address, used in PBF Header Builder Command */;
135*14b24e2bSVaishali Kulkarni 	u8 local_addr_2 /* Local Mac Address, used in PBF Header Builder Command */;
136*14b24e2bSVaishali Kulkarni 	union fcoe_vlan_vif_field_union vif_outer_vlan /* Union of VIF and outer vlan */;
137*14b24e2bSVaishali Kulkarni 	__le16 vif_outer_eth_type /* reserved place for Ethernet type */;
138*14b24e2bSVaishali Kulkarni 	union fcoe_vlan_vif_field_union inner_vlan /* inner vlan tag */;
139*14b24e2bSVaishali Kulkarni 	__le16 inner_eth_type /* reserved place for Ethernet type */;
140*14b24e2bSVaishali Kulkarni };
141*14b24e2bSVaishali Kulkarni 
142*14b24e2bSVaishali Kulkarni /*
143*14b24e2bSVaishali Kulkarni  * The fcoe storm context of Pstorm
144*14b24e2bSVaishali Kulkarni  */
145*14b24e2bSVaishali Kulkarni struct pstorm_fcoe_conn_st_ctx
146*14b24e2bSVaishali Kulkarni {
147*14b24e2bSVaishali Kulkarni 	u8 func_mode /* Function mode */;
148*14b24e2bSVaishali Kulkarni 	u8 cos /* Transmission cos */;
149*14b24e2bSVaishali Kulkarni 	u8 conf_version /* Is dcb_version or vntag_version changed */;
150*14b24e2bSVaishali Kulkarni 	u8 rsrv;
151*14b24e2bSVaishali Kulkarni 	__le16 stat_ram_addr /* Statistics ram adderss */;
152*14b24e2bSVaishali Kulkarni 	__le16 mss /* MSS for PBF (MSS we negotiate with target - protection data per segment. If we are not in perf mode it will be according to worse case) */;
153*14b24e2bSVaishali Kulkarni 	struct regpair abts_cleanup_addr /* Host addr of ABTS /Cleanup info. since we pass it  through session context, we pass only the addr to save space */;
154*14b24e2bSVaishali Kulkarni 	struct pstorm_fcoe_eth_context_section eth /* Source mac */;
155*14b24e2bSVaishali Kulkarni 	u8 sid_2 /* SID FC address - Third byte that is sent to NW via PBF For example is SID is 01:02:03 then sid_2 is 0x03 */;
156*14b24e2bSVaishali Kulkarni 	u8 sid_1 /* SID FC address - Second byte that is sent to NW via PBF */;
157*14b24e2bSVaishali Kulkarni 	u8 sid_0 /* SID FC address - First byte that is sent to NW via PBF */;
158*14b24e2bSVaishali Kulkarni 	u8 flags;
159*14b24e2bSVaishali Kulkarni #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_MASK          0x1 /* Is inner vlan taken from vntag default vlan (in this case I have to update inner vlan each time the default change) */
160*14b24e2bSVaishali Kulkarni #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_SHIFT         0
161*14b24e2bSVaishali Kulkarni #define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_MASK  0x1 /* AreSupport rec_tov timer */
162*14b24e2bSVaishali Kulkarni #define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_SHIFT 1
163*14b24e2bSVaishali Kulkarni #define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK     0x1 /* Inner Vlan flag */
164*14b24e2bSVaishali Kulkarni #define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT    2
165*14b24e2bSVaishali Kulkarni #define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK     0x1 /* Outer Vlan flag */
166*14b24e2bSVaishali Kulkarni #define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT    3
167*14b24e2bSVaishali Kulkarni #define PSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK            0xF
168*14b24e2bSVaishali Kulkarni #define PSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT           4
169*14b24e2bSVaishali Kulkarni 	u8 did_2 /* DID FC address - Third byte that is sent to NW via PBF */;
170*14b24e2bSVaishali Kulkarni 	u8 did_1 /* DID FC address - Second byte that is sent to NW via PBF */;
171*14b24e2bSVaishali Kulkarni 	u8 did_0 /* DID FC address - First byte that is sent to NW via PBF */;
172*14b24e2bSVaishali Kulkarni 	u8 src_mac_index;
173*14b24e2bSVaishali Kulkarni 	__le16 rec_rr_tov_val /* REC_TOV value negotiated during PLOGI (in msec) */;
174*14b24e2bSVaishali Kulkarni 	u8 q_relative_offset /* CQ, RQ (and CMDQ) relative offset for connection */;
175*14b24e2bSVaishali Kulkarni 	u8 reserved1;
176*14b24e2bSVaishali Kulkarni };
177*14b24e2bSVaishali Kulkarni 
178*14b24e2bSVaishali Kulkarni /*
179*14b24e2bSVaishali Kulkarni  * The fcoe storm context of Xstorm
180*14b24e2bSVaishali Kulkarni  */
181*14b24e2bSVaishali Kulkarni struct xstorm_fcoe_conn_st_ctx
182*14b24e2bSVaishali Kulkarni {
183*14b24e2bSVaishali Kulkarni 	u8 func_mode /* Function mode */;
184*14b24e2bSVaishali Kulkarni 	u8 src_mac_index /* Index to the src_mac arr held in the xStorm RAM. Provided at the xStorm offload connection handler */;
185*14b24e2bSVaishali Kulkarni 	u8 conf_version /* Advance if vntag/dcb version advance */;
186*14b24e2bSVaishali Kulkarni 	u8 cached_wqes_avail /* Number of cached wqes available */;
187*14b24e2bSVaishali Kulkarni 	__le16 stat_ram_addr /* Statistics ram adderss */;
188*14b24e2bSVaishali Kulkarni 	u8 flags;
189*14b24e2bSVaishali Kulkarni #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_MASK             0x1 /* SQ deferred (happens when we wait for xfer wqe to complete cleanup/abts */
190*14b24e2bSVaishali Kulkarni #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_SHIFT            0
191*14b24e2bSVaishali Kulkarni #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK         0x1 /* Inner vlan flag † for calculating eth header size */
192*14b24e2bSVaishali Kulkarni #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT        1
193*14b24e2bSVaishali Kulkarni #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_MASK    0x1 /* Original vlan configuration. used when we switch from dcb enable to dcb disabled */
194*14b24e2bSVaishali Kulkarni #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_SHIFT   2
195*14b24e2bSVaishali Kulkarni #define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_MASK      0x3
196*14b24e2bSVaishali Kulkarni #define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_SHIFT     3
197*14b24e2bSVaishali Kulkarni #define XSTORM_FCOE_CONN_ST_CTX_RSRV_MASK                    0x7
198*14b24e2bSVaishali Kulkarni #define XSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT                   5
199*14b24e2bSVaishali Kulkarni 	u8 cached_wqes_offset /* Offset of first valid cached wqe */;
200*14b24e2bSVaishali Kulkarni 	u8 reserved2;
201*14b24e2bSVaishali Kulkarni 	u8 eth_hdr_size /* Ethernet header size */;
202*14b24e2bSVaishali Kulkarni 	u8 seq_id /* Sequence id */;
203*14b24e2bSVaishali Kulkarni 	u8 max_conc_seqs /* Max concurrent sequence id */;
204*14b24e2bSVaishali Kulkarni 	__le16 num_pages_in_pbl /* Num of pages in SQ/RESPQ/XFERQ Pbl */;
205*14b24e2bSVaishali Kulkarni 	__le16 reserved;
206*14b24e2bSVaishali Kulkarni 	struct regpair sq_pbl_addr /* SQ address */;
207*14b24e2bSVaishali Kulkarni 	struct regpair sq_curr_page_addr /* SQ current page address */;
208*14b24e2bSVaishali Kulkarni 	struct regpair sq_next_page_addr /* SQ next page address */;
209*14b24e2bSVaishali Kulkarni 	struct regpair xferq_pbl_addr /* XFERQ address */;
210*14b24e2bSVaishali Kulkarni 	struct regpair xferq_curr_page_addr /* XFERQ current page address */;
211*14b24e2bSVaishali Kulkarni 	struct regpair xferq_next_page_addr /* XFERQ next page address */;
212*14b24e2bSVaishali Kulkarni 	struct regpair respq_pbl_addr /* RESPQ address */;
213*14b24e2bSVaishali Kulkarni 	struct regpair respq_curr_page_addr /* RESPQ current page address */;
214*14b24e2bSVaishali Kulkarni 	struct regpair respq_next_page_addr /* RESPQ next page address */;
215*14b24e2bSVaishali Kulkarni 	__le16 mtu /* MTU limitation */;
216*14b24e2bSVaishali Kulkarni 	__le16 tx_max_fc_pay_len /* Max payload length according to target limitation */;
217*14b24e2bSVaishali Kulkarni 	__le16 max_fc_payload_len /* Max payload length according to target limitation and mtu. Aligned to 4 bytes. */;
218*14b24e2bSVaishali Kulkarni 	__le16 min_frame_size /* The minimum ETH frame size required for transmission (including ETH header, excluding ETH CRC */;
219*14b24e2bSVaishali Kulkarni 	__le16 sq_pbl_next_index /* Next index of SQ Pbl */;
220*14b24e2bSVaishali Kulkarni 	__le16 respq_pbl_next_index /* Next index of RESPQ Pbl */;
221*14b24e2bSVaishali Kulkarni 	u8 fcp_cmd_byte_credit /* Pre-calculated byte credit that single FCP command can consume */;
222*14b24e2bSVaishali Kulkarni 	u8 fcp_rsp_byte_credit /* Pre-calculated byte credit that single FCP RSP can consume. */;
223*14b24e2bSVaishali Kulkarni 	__le16 protection_info;
224*14b24e2bSVaishali Kulkarni #define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_MASK         0x1 /* Intend to accelerate the protection flows */
225*14b24e2bSVaishali Kulkarni #define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_SHIFT        0
226*14b24e2bSVaishali Kulkarni #define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK      0x1 /* Does this connection support protection (if couple of GOS share this connection is enough that one of them support protection) */
227*14b24e2bSVaishali Kulkarni #define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT     1
228*14b24e2bSVaishali Kulkarni #define XSTORM_FCOE_CONN_ST_CTX_VALID_MASK                   0x1 /* Are we in protection perf mode (there is only one protection mode for this connection and we manage to create mss that contain fixed amount of protection segment and we are only restrict by the target limitation and not line mss this is critical since if line mss restrict us we can’t rely on this size † it depends on vlan num) */
229*14b24e2bSVaishali Kulkarni #define XSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT                  2
230*14b24e2bSVaishali Kulkarni #define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_MASK      0x1 /* Is size of tx_max_pay_len_prot can be aligned to protection intervals. This means that pure data in each frame is 2k exactly, and protection intervals are no bigger than 2k */
231*14b24e2bSVaishali Kulkarni #define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_SHIFT     3
232*14b24e2bSVaishali Kulkarni #define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_MASK               0xF
233*14b24e2bSVaishali Kulkarni #define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_SHIFT              4
234*14b24e2bSVaishali Kulkarni #define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_MASK  0xFF /* Destination Pro tection data per mss (if we are not in perf mode it will be worse case). Destination is the data add/remove from the transmitted packet (as opposed to src which is data validate by the nic they might not be identical) */
235*14b24e2bSVaishali Kulkarni #define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_SHIFT 8
236*14b24e2bSVaishali Kulkarni 	__le16 xferq_pbl_next_index /* Next index of XFERQ Pbl */;
237*14b24e2bSVaishali Kulkarni 	__le16 page_size /* Page size (in bytes) */;
238*14b24e2bSVaishali Kulkarni 	u8 mid_seq /* Equals 1 for Middle sequence indication, otherwise 0 */;
239*14b24e2bSVaishali Kulkarni 	u8 fcp_xfer_byte_credit /* Pre-calculated byte credit that single FCP command can consume */;
240*14b24e2bSVaishali Kulkarni 	u8 reserved1[2];
241*14b24e2bSVaishali Kulkarni 	struct fcoe_wqe cached_wqes[16] /* cached wqe (8) = 8*8*8Bytes */;
242*14b24e2bSVaishali Kulkarni };
243*14b24e2bSVaishali Kulkarni 
244*14b24e2bSVaishali Kulkarni struct e4_xstorm_fcoe_conn_ag_ctx
245*14b24e2bSVaishali Kulkarni {
246*14b24e2bSVaishali Kulkarni 	u8 reserved0 /* cdu_validation */;
247*14b24e2bSVaishali Kulkarni 	u8 fcoe_state /* state */;
248*14b24e2bSVaishali Kulkarni 	u8 flags0;
249*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK       0x1 /* exist_in_qm0 */
250*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT      0
251*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_MASK          0x1 /* exist_in_qm1 */
252*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_SHIFT         1
253*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_MASK          0x1 /* exist_in_qm2 */
254*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_SHIFT         2
255*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_MASK       0x1 /* exist_in_qm3 */
256*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT      3
257*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_MASK          0x1 /* bit4 */
258*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_SHIFT         4
259*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_MASK          0x1 /* cf_array_active */
260*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_SHIFT         5
261*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_MASK          0x1 /* bit6 */
262*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_SHIFT         6
263*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_MASK          0x1 /* bit7 */
264*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_SHIFT         7
265*14b24e2bSVaishali Kulkarni 	u8 flags1;
266*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_MASK          0x1 /* bit8 */
267*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_SHIFT         0
268*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_MASK          0x1 /* bit9 */
269*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_SHIFT         1
270*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_MASK          0x1 /* bit10 */
271*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_SHIFT         2
272*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT11_MASK              0x1 /* bit11 */
273*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT11_SHIFT             3
274*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT12_MASK              0x1 /* bit12 */
275*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT12_SHIFT             4
276*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT13_MASK              0x1 /* bit13 */
277*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT13_SHIFT             5
278*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT14_MASK              0x1 /* bit14 */
279*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT14_SHIFT             6
280*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT15_MASK              0x1 /* bit15 */
281*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT15_SHIFT             7
282*14b24e2bSVaishali Kulkarni 	u8 flags2;
283*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0_MASK                0x3 /* timer0cf */
284*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT               0
285*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1_MASK                0x3 /* timer1cf */
286*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT               2
287*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2_MASK                0x3 /* timer2cf */
288*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT               4
289*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3_MASK                0x3 /* timer_stop_all */
290*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3_SHIFT               6
291*14b24e2bSVaishali Kulkarni 	u8 flags3;
292*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4_MASK                0x3 /* cf4 */
293*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT               0
294*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5_MASK                0x3 /* cf5 */
295*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT               2
296*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6_MASK                0x3 /* cf6 */
297*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT               4
298*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7_MASK                0x3 /* cf7 */
299*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT               6
300*14b24e2bSVaishali Kulkarni 	u8 flags4;
301*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8_MASK                0x3 /* cf8 */
302*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT               0
303*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9_MASK                0x3 /* cf9 */
304*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT               2
305*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10_MASK               0x3 /* cf10 */
306*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT              4
307*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11_MASK               0x3 /* cf11 */
308*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11_SHIFT              6
309*14b24e2bSVaishali Kulkarni 	u8 flags5;
310*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12_MASK               0x3 /* cf12 */
311*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12_SHIFT              0
312*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13_MASK               0x3 /* cf13 */
313*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13_SHIFT              2
314*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14_MASK               0x3 /* cf14 */
315*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14_SHIFT              4
316*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15_MASK               0x3 /* cf15 */
317*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15_SHIFT              6
318*14b24e2bSVaishali Kulkarni 	u8 flags6;
319*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16_MASK               0x3 /* cf16 */
320*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16_SHIFT              0
321*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17_MASK               0x3 /* cf_array_cf */
322*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17_SHIFT              2
323*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18_MASK               0x3 /* cf18 */
324*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18_SHIFT              4
325*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_MASK              0x3 /* cf19 */
326*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_SHIFT             6
327*14b24e2bSVaishali Kulkarni 	u8 flags7;
328*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_MASK           0x3 /* cf20 */
329*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_SHIFT          0
330*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED10_MASK         0x3 /* cf21 */
331*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED10_SHIFT        2
332*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_MASK          0x3 /* cf22 */
333*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_SHIFT         4
334*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK              0x1 /* cf0en */
335*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT             6
336*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK              0x1 /* cf1en */
337*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT             7
338*14b24e2bSVaishali Kulkarni 	u8 flags8;
339*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK              0x1 /* cf2en */
340*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT             0
341*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3EN_MASK              0x1 /* cf3en */
342*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT             1
343*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK              0x1 /* cf4en */
344*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT             2
345*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK              0x1 /* cf5en */
346*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT             3
347*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK              0x1 /* cf6en */
348*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT             4
349*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK              0x1 /* cf7en */
350*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT             5
351*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK              0x1 /* cf8en */
352*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT             6
353*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK              0x1 /* cf9en */
354*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT             7
355*14b24e2bSVaishali Kulkarni 	u8 flags9;
356*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK             0x1 /* cf10en */
357*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT            0
358*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11EN_MASK             0x1 /* cf11en */
359*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11EN_SHIFT            1
360*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12EN_MASK             0x1 /* cf12en */
361*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12EN_SHIFT            2
362*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13EN_MASK             0x1 /* cf13en */
363*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13EN_SHIFT            3
364*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14EN_MASK             0x1 /* cf14en */
365*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14EN_SHIFT            4
366*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15EN_MASK             0x1 /* cf15en */
367*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15EN_SHIFT            5
368*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16EN_MASK             0x1 /* cf16en */
369*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16EN_SHIFT            6
370*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17EN_MASK             0x1 /* cf_array_cf_en */
371*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17EN_SHIFT            7
372*14b24e2bSVaishali Kulkarni 	u8 flags10;
373*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18EN_MASK             0x1 /* cf18en */
374*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18EN_SHIFT            0
375*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_MASK           0x1 /* cf19en */
376*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_SHIFT          1
377*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK        0x1 /* cf20en */
378*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT       2
379*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_MASK         0x1 /* cf21en */
380*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_SHIFT        3
381*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_MASK       0x1 /* cf22en */
382*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT      4
383*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23EN_MASK             0x1 /* cf23en */
384*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23EN_SHIFT            5
385*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_MASK         0x1 /* rule0en */
386*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_SHIFT        6
387*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_MASK         0x1 /* rule1en */
388*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_SHIFT        7
389*14b24e2bSVaishali Kulkarni 	u8 flags11;
390*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_MASK         0x1 /* rule2en */
391*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_SHIFT        0
392*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_MASK         0x1 /* rule3en */
393*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_SHIFT        1
394*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_MASK         0x1 /* rule4en */
395*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_SHIFT        2
396*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK            0x1 /* rule5en */
397*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT           3
398*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK            0x1 /* rule6en */
399*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT           4
400*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK            0x1 /* rule7en */
401*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT           5
402*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_MASK       0x1 /* rule8en */
403*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_SHIFT      6
404*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_MASK  0x1 /* rule9en */
405*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_SHIFT 7
406*14b24e2bSVaishali Kulkarni 	u8 flags12;
407*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_MASK     0x1 /* rule10en */
408*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_SHIFT    0
409*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_MASK           0x1 /* rule11en */
410*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_SHIFT          1
411*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_MASK       0x1 /* rule12en */
412*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_SHIFT      2
413*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_MASK       0x1 /* rule13en */
414*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_SHIFT      3
415*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_MASK           0x1 /* rule14en */
416*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_SHIFT          4
417*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_MASK           0x1 /* rule15en */
418*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_SHIFT          5
419*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_MASK           0x1 /* rule16en */
420*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_SHIFT          6
421*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_MASK           0x1 /* rule17en */
422*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_SHIFT          7
423*14b24e2bSVaishali Kulkarni 	u8 flags13;
424*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_MASK  0x1 /* rule18en */
425*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_SHIFT 0
426*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_MASK           0x1 /* rule19en */
427*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_SHIFT          1
428*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_MASK       0x1 /* rule20en */
429*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_SHIFT      2
430*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_MASK       0x1 /* rule21en */
431*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_SHIFT      3
432*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_MASK       0x1 /* rule22en */
433*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_SHIFT      4
434*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_MASK       0x1 /* rule23en */
435*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_SHIFT      5
436*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_MASK       0x1 /* rule24en */
437*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_SHIFT      6
438*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_MASK       0x1 /* rule25en */
439*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_SHIFT      7
440*14b24e2bSVaishali Kulkarni 	u8 flags14;
441*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT16_MASK              0x1 /* bit16 */
442*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT16_SHIFT             0
443*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT17_MASK              0x1 /* bit17 */
444*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT17_SHIFT             1
445*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT18_MASK              0x1 /* bit18 */
446*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT18_SHIFT             2
447*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT19_MASK              0x1 /* bit19 */
448*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT19_SHIFT             3
449*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT20_MASK              0x1 /* bit20 */
450*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT20_SHIFT             4
451*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT21_MASK              0x1 /* bit21 */
452*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT21_SHIFT             5
453*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23_MASK               0x3 /* cf23 */
454*14b24e2bSVaishali Kulkarni #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23_SHIFT              6
455*14b24e2bSVaishali Kulkarni 	u8 byte2 /* byte2 */;
456*14b24e2bSVaishali Kulkarni 	__le16 physical_q0 /* physical_q0 */;
457*14b24e2bSVaishali Kulkarni 	__le16 word1 /* physical_q1 */;
458*14b24e2bSVaishali Kulkarni 	__le16 word2 /* physical_q2 */;
459*14b24e2bSVaishali Kulkarni 	__le16 sq_cons /* word3 */;
460*14b24e2bSVaishali Kulkarni 	__le16 sq_prod /* word4 */;
461*14b24e2bSVaishali Kulkarni 	__le16 xferq_prod /* word5 */;
462*14b24e2bSVaishali Kulkarni 	__le16 xferq_cons /* conn_dpi */;
463*14b24e2bSVaishali Kulkarni 	u8 byte3 /* byte3 */;
464*14b24e2bSVaishali Kulkarni 	u8 byte4 /* byte4 */;
465*14b24e2bSVaishali Kulkarni 	u8 byte5 /* byte5 */;
466*14b24e2bSVaishali Kulkarni 	u8 byte6 /* byte6 */;
467*14b24e2bSVaishali Kulkarni 	__le32 remain_io /* reg0 */;
468*14b24e2bSVaishali Kulkarni 	__le32 reg1 /* reg1 */;
469*14b24e2bSVaishali Kulkarni 	__le32 reg2 /* reg2 */;
470*14b24e2bSVaishali Kulkarni 	__le32 reg3 /* reg3 */;
471*14b24e2bSVaishali Kulkarni 	__le32 reg4 /* reg4 */;
472*14b24e2bSVaishali Kulkarni 	__le32 reg5 /* cf_array0 */;
473*14b24e2bSVaishali Kulkarni 	__le32 reg6 /* cf_array1 */;
474*14b24e2bSVaishali Kulkarni 	__le16 respq_prod /* word7 */;
475*14b24e2bSVaishali Kulkarni 	__le16 respq_cons /* word8 */;
476*14b24e2bSVaishali Kulkarni 	__le16 word9 /* word9 */;
477*14b24e2bSVaishali Kulkarni 	__le16 word10 /* word10 */;
478*14b24e2bSVaishali Kulkarni 	__le32 reg7 /* reg7 */;
479*14b24e2bSVaishali Kulkarni 	__le32 reg8 /* reg8 */;
480*14b24e2bSVaishali Kulkarni };
481*14b24e2bSVaishali Kulkarni 
482*14b24e2bSVaishali Kulkarni /*
483*14b24e2bSVaishali Kulkarni  * The fcoe storm context of Ustorm
484*14b24e2bSVaishali Kulkarni  */
485*14b24e2bSVaishali Kulkarni struct ustorm_fcoe_conn_st_ctx
486*14b24e2bSVaishali Kulkarni {
487*14b24e2bSVaishali Kulkarni 	struct regpair respq_pbl_addr /* RespQ Pbl base address */;
488*14b24e2bSVaishali Kulkarni 	__le16 num_pages_in_pbl /* Number of RespQ pbl pages (both have same wqe size) */;
489*14b24e2bSVaishali Kulkarni 	u8 ptu_log_page_size /* 0-4K, 1-8K, 2-16K, 3-32K... */;
490*14b24e2bSVaishali Kulkarni 	u8 log_page_size;
491*14b24e2bSVaishali Kulkarni 	__le16 respq_prod /* RespQ producer */;
492*14b24e2bSVaishali Kulkarni 	u8 reserved[2];
493*14b24e2bSVaishali Kulkarni };
494*14b24e2bSVaishali Kulkarni 
495*14b24e2bSVaishali Kulkarni struct e4_tstorm_fcoe_conn_ag_ctx
496*14b24e2bSVaishali Kulkarni {
497*14b24e2bSVaishali Kulkarni 	u8 reserved0 /* cdu_validation */;
498*14b24e2bSVaishali Kulkarni 	u8 fcoe_state /* state */;
499*14b24e2bSVaishali Kulkarni 	u8 flags0;
500*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK          0x1 /* exist_in_qm0 */
501*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT         0
502*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT1_MASK                  0x1 /* exist_in_qm1 */
503*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT                 1
504*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT2_MASK                  0x1 /* bit2 */
505*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT2_SHIFT                 2
506*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT3_MASK                  0x1 /* bit3 */
507*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT3_SHIFT                 3
508*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT4_MASK                  0x1 /* bit4 */
509*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT4_SHIFT                 4
510*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT5_MASK                  0x1 /* bit5 */
511*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT5_SHIFT                 5
512*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_MASK        0x3 /* timer0cf */
513*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_SHIFT       6
514*14b24e2bSVaishali Kulkarni 	u8 flags1;
515*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_MASK           0x3 /* timer1cf */
516*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT          0
517*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2_MASK                   0x3 /* timer2cf */
518*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT                  2
519*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK     0x3 /* timer_stop_all */
520*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT    4
521*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4_MASK                   0x3 /* cf4 */
522*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT                  6
523*14b24e2bSVaishali Kulkarni 	u8 flags2;
524*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5_MASK                   0x3 /* cf5 */
525*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT                  0
526*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6_MASK                   0x3 /* cf6 */
527*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT                  2
528*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7_MASK                   0x3 /* cf7 */
529*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT                  4
530*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8_MASK                   0x3 /* cf8 */
531*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT                  6
532*14b24e2bSVaishali Kulkarni 	u8 flags3;
533*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9_MASK                   0x3 /* cf9 */
534*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT                  0
535*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10_MASK                  0x3 /* cf10 */
536*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT                 2
537*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_MASK     0x1 /* cf0en */
538*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_SHIFT    4
539*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK        0x1 /* cf1en */
540*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT       5
541*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK                 0x1 /* cf2en */
542*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT                6
543*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK  0x1 /* cf3en */
544*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
545*14b24e2bSVaishali Kulkarni 	u8 flags4;
546*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK                 0x1 /* cf4en */
547*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT                0
548*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK                 0x1 /* cf5en */
549*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT                1
550*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK                 0x1 /* cf6en */
551*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT                2
552*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK                 0x1 /* cf7en */
553*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT                3
554*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK                 0x1 /* cf8en */
555*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT                4
556*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK                 0x1 /* cf9en */
557*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT                5
558*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK                0x1 /* cf10en */
559*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT               6
560*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK               0x1 /* rule0en */
561*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT              7
562*14b24e2bSVaishali Kulkarni 	u8 flags5;
563*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK               0x1 /* rule1en */
564*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT              0
565*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK               0x1 /* rule2en */
566*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT              1
567*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK               0x1 /* rule3en */
568*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT              2
569*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK               0x1 /* rule4en */
570*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT              3
571*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK               0x1 /* rule5en */
572*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT              4
573*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK               0x1 /* rule6en */
574*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT              5
575*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK               0x1 /* rule7en */
576*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT              6
577*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK               0x1 /* rule8en */
578*14b24e2bSVaishali Kulkarni #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT              7
579*14b24e2bSVaishali Kulkarni 	__le32 reg0 /* reg0 */;
580*14b24e2bSVaishali Kulkarni 	__le32 reg1 /* reg1 */;
581*14b24e2bSVaishali Kulkarni };
582*14b24e2bSVaishali Kulkarni 
583*14b24e2bSVaishali Kulkarni struct e4_ustorm_fcoe_conn_ag_ctx
584*14b24e2bSVaishali Kulkarni {
585*14b24e2bSVaishali Kulkarni 	u8 byte0 /* cdu_validation */;
586*14b24e2bSVaishali Kulkarni 	u8 byte1 /* state */;
587*14b24e2bSVaishali Kulkarni 	u8 flags0;
588*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_BIT0_MASK     0x1 /* exist_in_qm0 */
589*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT    0
590*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_BIT1_MASK     0x1 /* exist_in_qm1 */
591*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT    1
592*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_CF0_MASK      0x3 /* timer0cf */
593*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_CF0_SHIFT     2
594*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_CF1_MASK      0x3 /* timer1cf */
595*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_CF1_SHIFT     4
596*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_CF2_MASK      0x3 /* timer2cf */
597*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_CF2_SHIFT     6
598*14b24e2bSVaishali Kulkarni 	u8 flags1;
599*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_CF3_MASK      0x3 /* timer_stop_all */
600*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_CF3_SHIFT     0
601*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_CF4_MASK      0x3 /* cf4 */
602*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_CF4_SHIFT     2
603*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_CF5_MASK      0x3 /* cf5 */
604*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_CF5_SHIFT     4
605*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_CF6_MASK      0x3 /* cf6 */
606*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_CF6_SHIFT     6
607*14b24e2bSVaishali Kulkarni 	u8 flags2;
608*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_CF0EN_MASK    0x1 /* cf0en */
609*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT   0
610*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_CF1EN_MASK    0x1 /* cf1en */
611*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT   1
612*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_CF2EN_MASK    0x1 /* cf2en */
613*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT   2
614*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_CF3EN_MASK    0x1 /* cf3en */
615*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT   3
616*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_CF4EN_MASK    0x1 /* cf4en */
617*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT   4
618*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_CF5EN_MASK    0x1 /* cf5en */
619*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT   5
620*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_CF6EN_MASK    0x1 /* cf6en */
621*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT   6
622*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK  0x1 /* rule0en */
623*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7
624*14b24e2bSVaishali Kulkarni 	u8 flags3;
625*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK  0x1 /* rule1en */
626*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0
627*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK  0x1 /* rule2en */
628*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1
629*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK  0x1 /* rule3en */
630*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2
631*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK  0x1 /* rule4en */
632*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3
633*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK  0x1 /* rule5en */
634*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4
635*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK  0x1 /* rule6en */
636*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5
637*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK  0x1 /* rule7en */
638*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6
639*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK  0x1 /* rule8en */
640*14b24e2bSVaishali Kulkarni #define E4_USTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7
641*14b24e2bSVaishali Kulkarni 	u8 byte2 /* byte2 */;
642*14b24e2bSVaishali Kulkarni 	u8 byte3 /* byte3 */;
643*14b24e2bSVaishali Kulkarni 	__le16 word0 /* conn_dpi */;
644*14b24e2bSVaishali Kulkarni 	__le16 word1 /* word1 */;
645*14b24e2bSVaishali Kulkarni 	__le32 reg0 /* reg0 */;
646*14b24e2bSVaishali Kulkarni 	__le32 reg1 /* reg1 */;
647*14b24e2bSVaishali Kulkarni 	__le32 reg2 /* reg2 */;
648*14b24e2bSVaishali Kulkarni 	__le32 reg3 /* reg3 */;
649*14b24e2bSVaishali Kulkarni 	__le16 word2 /* word2 */;
650*14b24e2bSVaishali Kulkarni 	__le16 word3 /* word3 */;
651*14b24e2bSVaishali Kulkarni };
652*14b24e2bSVaishali Kulkarni 
653*14b24e2bSVaishali Kulkarni /*
654*14b24e2bSVaishali Kulkarni  * The fcoe storm context of Tstorm
655*14b24e2bSVaishali Kulkarni  */
656*14b24e2bSVaishali Kulkarni struct tstorm_fcoe_conn_st_ctx
657*14b24e2bSVaishali Kulkarni {
658*14b24e2bSVaishali Kulkarni 	__le16 stat_ram_addr /* Statistics ram adderss */;
659*14b24e2bSVaishali Kulkarni 	__le16 rx_max_fc_payload_len /* Max rx fc payload length. provided in ramrod */;
660*14b24e2bSVaishali Kulkarni 	__le16 e_d_tov_val /* E_D_TOV value negotiated during PLOGI (in msec) */;
661*14b24e2bSVaishali Kulkarni 	u8 flags;
662*14b24e2bSVaishali Kulkarni #define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_MASK   0x1 /* Does the target support increment sequence counter */
663*14b24e2bSVaishali Kulkarni #define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_SHIFT  0
664*14b24e2bSVaishali Kulkarni #define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_MASK  0x1 /* Does the connection support CONF REQ transmission */
665*14b24e2bSVaishali Kulkarni #define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_SHIFT 1
666*14b24e2bSVaishali Kulkarni #define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_MASK     0x3F /* Default queue index the connection associated to */
667*14b24e2bSVaishali Kulkarni #define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_SHIFT    2
668*14b24e2bSVaishali Kulkarni 	u8 timers_cleanup_invocation_cnt /* This variable is incremented each time the tStorm handler for timers cleanup is invoked within the same timers cleanup flow */;
669*14b24e2bSVaishali Kulkarni 	__le32 reserved1[2];
670*14b24e2bSVaishali Kulkarni 	__le32 dstMacAddressBytes0To3 /* destination MAC address: Bytes 0-3. */;
671*14b24e2bSVaishali Kulkarni 	__le16 dstMacAddressBytes4To5 /* destination MAC address: Bytes 4-5. */;
672*14b24e2bSVaishali Kulkarni 	__le16 ramrodEcho /* Saved ramrod echo - needed for 2nd round of terminate_conn (flush Q0) */;
673*14b24e2bSVaishali Kulkarni 	u8 flags1;
674*14b24e2bSVaishali Kulkarni #define TSTORM_FCOE_CONN_ST_CTX_MODE_MASK          0x3 /* Indicate the mode of the connection: Target or Initiator, use enum fcoe_mode_type */
675*14b24e2bSVaishali Kulkarni #define TSTORM_FCOE_CONN_ST_CTX_MODE_SHIFT         0
676*14b24e2bSVaishali Kulkarni #define TSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK      0x3F
677*14b24e2bSVaishali Kulkarni #define TSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT     2
678*14b24e2bSVaishali Kulkarni 	u8 q_relative_offset /* CQ, RQ and CMDQ relative offset for connection */;
679*14b24e2bSVaishali Kulkarni 	u8 bdq_resource_id /* The BDQ resource ID to which this function is mapped */;
680*14b24e2bSVaishali Kulkarni 	u8 reserved0[5] /* Alignment to 128b */;
681*14b24e2bSVaishali Kulkarni };
682*14b24e2bSVaishali Kulkarni 
683*14b24e2bSVaishali Kulkarni struct e4_mstorm_fcoe_conn_ag_ctx
684*14b24e2bSVaishali Kulkarni {
685*14b24e2bSVaishali Kulkarni 	u8 byte0 /* cdu_validation */;
686*14b24e2bSVaishali Kulkarni 	u8 byte1 /* state */;
687*14b24e2bSVaishali Kulkarni 	u8 flags0;
688*14b24e2bSVaishali Kulkarni #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT0_MASK     0x1 /* exist_in_qm0 */
689*14b24e2bSVaishali Kulkarni #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT    0
690*14b24e2bSVaishali Kulkarni #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT1_MASK     0x1 /* exist_in_qm1 */
691*14b24e2bSVaishali Kulkarni #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT    1
692*14b24e2bSVaishali Kulkarni #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0_MASK      0x3 /* cf0 */
693*14b24e2bSVaishali Kulkarni #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT     2
694*14b24e2bSVaishali Kulkarni #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1_MASK      0x3 /* cf1 */
695*14b24e2bSVaishali Kulkarni #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT     4
696*14b24e2bSVaishali Kulkarni #define E4_MSTORM_FCOE_CONN_AG_CTX_CF2_MASK      0x3 /* cf2 */