1*14b24e2bSVaishali Kulkarni /* 2*14b24e2bSVaishali Kulkarni * CDDL HEADER START 3*14b24e2bSVaishali Kulkarni * 4*14b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the 5*14b24e2bSVaishali Kulkarni * Common Development and Distribution License, v.1, (the "License"). 6*14b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License. 7*14b24e2bSVaishali Kulkarni * 8*14b24e2bSVaishali Kulkarni * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*14b24e2bSVaishali Kulkarni * or http://opensource.org/licenses/CDDL-1.0. 10*14b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions 11*14b24e2bSVaishali Kulkarni * and limitations under the License. 12*14b24e2bSVaishali Kulkarni * 13*14b24e2bSVaishali Kulkarni * When distributing Covered Code, include this CDDL HEADER in each 14*14b24e2bSVaishali Kulkarni * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*14b24e2bSVaishali Kulkarni * If applicable, add the following below this CDDL HEADER, with the 16*14b24e2bSVaishali Kulkarni * fields enclosed by brackets "[]" replaced with your own identifying 17*14b24e2bSVaishali Kulkarni * information: Portions Copyright [yyyy] [name of copyright owner] 18*14b24e2bSVaishali Kulkarni * 19*14b24e2bSVaishali Kulkarni * CDDL HEADER END 20*14b24e2bSVaishali Kulkarni */ 21*14b24e2bSVaishali Kulkarni 22*14b24e2bSVaishali Kulkarni /* 23*14b24e2bSVaishali Kulkarni * Copyright 2014-2017 Cavium, Inc. 24*14b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the Common Development 25*14b24e2bSVaishali Kulkarni * and Distribution License, v.1, (the "License"). 26*14b24e2bSVaishali Kulkarni 27*14b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License. 28*14b24e2bSVaishali Kulkarni 29*14b24e2bSVaishali Kulkarni * You can obtain a copy of the License at available 30*14b24e2bSVaishali Kulkarni * at http://opensource.org/licenses/CDDL-1.0 31*14b24e2bSVaishali Kulkarni 32*14b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions and 33*14b24e2bSVaishali Kulkarni * limitations under the License. 34*14b24e2bSVaishali Kulkarni */ 35*14b24e2bSVaishali Kulkarni 36*14b24e2bSVaishali Kulkarni #ifndef __ECORE_HSI_COMMON__ 37*14b24e2bSVaishali Kulkarni #define __ECORE_HSI_COMMON__ 38*14b24e2bSVaishali Kulkarni /********************************/ 39*14b24e2bSVaishali Kulkarni /* Add include to common target */ 40*14b24e2bSVaishali Kulkarni /********************************/ 41*14b24e2bSVaishali Kulkarni #include "common_hsi.h" 42*14b24e2bSVaishali Kulkarni 43*14b24e2bSVaishali Kulkarni 44*14b24e2bSVaishali Kulkarni /* 45*14b24e2bSVaishali Kulkarni * opcodes for the event ring 46*14b24e2bSVaishali Kulkarni */ 47*14b24e2bSVaishali Kulkarni enum common_event_opcode 48*14b24e2bSVaishali Kulkarni { 49*14b24e2bSVaishali Kulkarni COMMON_EVENT_PF_START, 50*14b24e2bSVaishali Kulkarni COMMON_EVENT_PF_STOP, 51*14b24e2bSVaishali Kulkarni COMMON_EVENT_VF_START, 52*14b24e2bSVaishali Kulkarni COMMON_EVENT_VF_STOP, 53*14b24e2bSVaishali Kulkarni COMMON_EVENT_VF_PF_CHANNEL, 54*14b24e2bSVaishali Kulkarni COMMON_EVENT_VF_FLR, 55*14b24e2bSVaishali Kulkarni COMMON_EVENT_PF_UPDATE, 56*14b24e2bSVaishali Kulkarni COMMON_EVENT_MALICIOUS_VF, 57*14b24e2bSVaishali Kulkarni COMMON_EVENT_RL_UPDATE, 58*14b24e2bSVaishali Kulkarni COMMON_EVENT_EMPTY, 59*14b24e2bSVaishali Kulkarni MAX_COMMON_EVENT_OPCODE 60*14b24e2bSVaishali Kulkarni }; 61*14b24e2bSVaishali Kulkarni 62*14b24e2bSVaishali Kulkarni 63*14b24e2bSVaishali Kulkarni /* 64*14b24e2bSVaishali Kulkarni * Common Ramrod Command IDs 65*14b24e2bSVaishali Kulkarni */ 66*14b24e2bSVaishali Kulkarni enum common_ramrod_cmd_id 67*14b24e2bSVaishali Kulkarni { 68*14b24e2bSVaishali Kulkarni COMMON_RAMROD_UNUSED, 69*14b24e2bSVaishali Kulkarni COMMON_RAMROD_PF_START /* PF Function Start Ramrod */, 70*14b24e2bSVaishali Kulkarni COMMON_RAMROD_PF_STOP /* PF Function Stop Ramrod */, 71*14b24e2bSVaishali Kulkarni COMMON_RAMROD_VF_START /* VF Function Start */, 72*14b24e2bSVaishali Kulkarni COMMON_RAMROD_VF_STOP /* VF Function Stop Ramrod */, 73*14b24e2bSVaishali Kulkarni COMMON_RAMROD_PF_UPDATE /* PF update Ramrod */, 74*14b24e2bSVaishali Kulkarni COMMON_RAMROD_RL_UPDATE /* QCN/DCQCN RL update Ramrod */, 75*14b24e2bSVaishali Kulkarni COMMON_RAMROD_EMPTY /* Empty Ramrod */, 76*14b24e2bSVaishali Kulkarni MAX_COMMON_RAMROD_CMD_ID 77*14b24e2bSVaishali Kulkarni }; 78*14b24e2bSVaishali Kulkarni 79*14b24e2bSVaishali Kulkarni 80*14b24e2bSVaishali Kulkarni /* 81*14b24e2bSVaishali Kulkarni * The core storm context for the Ystorm 82*14b24e2bSVaishali Kulkarni */ 83*14b24e2bSVaishali Kulkarni struct ystorm_core_conn_st_ctx 84*14b24e2bSVaishali Kulkarni { 85*14b24e2bSVaishali Kulkarni __le32 reserved[4]; 86*14b24e2bSVaishali Kulkarni }; 87*14b24e2bSVaishali Kulkarni 88*14b24e2bSVaishali Kulkarni /* 89*14b24e2bSVaishali Kulkarni * The core storm context for the Pstorm 90*14b24e2bSVaishali Kulkarni */ 91*14b24e2bSVaishali Kulkarni struct pstorm_core_conn_st_ctx 92*14b24e2bSVaishali Kulkarni { 93*14b24e2bSVaishali Kulkarni __le32 reserved[4]; 94*14b24e2bSVaishali Kulkarni }; 95*14b24e2bSVaishali Kulkarni 96*14b24e2bSVaishali Kulkarni /* 97*14b24e2bSVaishali Kulkarni * Core Slowpath Connection storm context of Xstorm 98*14b24e2bSVaishali Kulkarni */ 99*14b24e2bSVaishali Kulkarni struct xstorm_core_conn_st_ctx 100*14b24e2bSVaishali Kulkarni { 101*14b24e2bSVaishali Kulkarni __le32 spq_base_lo /* SPQ Ring Base Address low dword */; 102*14b24e2bSVaishali Kulkarni __le32 spq_base_hi /* SPQ Ring Base Address high dword */; 103*14b24e2bSVaishali Kulkarni struct regpair consolid_base_addr /* Consolidation Ring Base Address */; 104*14b24e2bSVaishali Kulkarni __le16 spq_cons /* SPQ Ring Consumer */; 105*14b24e2bSVaishali Kulkarni __le16 consolid_cons /* Consolidation Ring Consumer */; 106*14b24e2bSVaishali Kulkarni __le32 reserved0[55] /* Pad to 15 cycles */; 107*14b24e2bSVaishali Kulkarni }; 108*14b24e2bSVaishali Kulkarni 109*14b24e2bSVaishali Kulkarni struct e4_xstorm_core_conn_ag_ctx 110*14b24e2bSVaishali Kulkarni { 111*14b24e2bSVaishali Kulkarni u8 reserved0 /* cdu_validation */; 112*14b24e2bSVaishali Kulkarni u8 core_state /* state */; 113*14b24e2bSVaishali Kulkarni u8 flags0; 114*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 115*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 116*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 117*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT 1 118*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 119*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT 2 120*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 121*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 122*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 123*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT 4 124*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 125*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT 5 126*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 127*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT 6 128*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 129*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT 7 130*14b24e2bSVaishali Kulkarni u8 flags1; 131*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 132*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT 0 133*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 134*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT 1 135*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */ 136*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT 2 137*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 138*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT 3 139*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 140*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT 4 141*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 142*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT 5 143*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */ 144*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 145*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */ 146*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 147*14b24e2bSVaishali Kulkarni u8 flags2; 148*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 149*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 0 150*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 151*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 2 152*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 153*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 4 154*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 155*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 6 156*14b24e2bSVaishali Kulkarni u8 flags3; 157*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 158*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 0 159*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 160*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 2 161*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 162*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 4 163*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 164*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 6 165*14b24e2bSVaishali Kulkarni u8 flags4; 166*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 167*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 0 168*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 169*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 2 170*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 171*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 4 172*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 173*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT 6 174*14b24e2bSVaishali Kulkarni u8 flags5; 175*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 176*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT 0 177*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 178*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT 2 179*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 180*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT 4 181*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 182*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT 6 183*14b24e2bSVaishali Kulkarni u8 flags6; 184*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK 0x3 /* cf16 */ 185*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT 0 186*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 187*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT 2 188*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf18 */ 189*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT 4 190*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 /* cf19 */ 191*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 192*14b24e2bSVaishali Kulkarni u8 flags7; 193*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */ 194*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 195*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */ 196*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT 2 197*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 198*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT 4 199*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 200*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 6 201*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 202*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 7 203*14b24e2bSVaishali Kulkarni u8 flags8; 204*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 205*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 0 206*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 207*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 1 208*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 209*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 2 210*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 211*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 3 212*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 213*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 4 214*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 215*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 5 216*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 217*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 6 218*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 219*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 7 220*14b24e2bSVaishali Kulkarni u8 flags9; 221*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 222*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 0 223*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 224*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT 1 225*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 226*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT 2 227*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 228*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT 3 229*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 230*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT 4 231*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 232*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT 5 233*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK 0x1 /* cf16en */ 234*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT 6 235*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 236*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT 7 237*14b24e2bSVaishali Kulkarni u8 flags10; 238*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf18en */ 239*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 240*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 /* cf19en */ 241*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 242*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 243*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 244*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */ 245*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT 3 246*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 247*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 248*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 249*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT 5 250*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */ 251*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT 6 252*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */ 253*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT 7 254*14b24e2bSVaishali Kulkarni u8 flags11; 255*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */ 256*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT 0 257*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */ 258*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT 1 259*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */ 260*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 261*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 262*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 3 263*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 264*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 4 265*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 266*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 5 267*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 268*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 269*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 270*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT 7 271*14b24e2bSVaishali Kulkarni u8 flags12; 272*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */ 273*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT 0 274*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 275*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT 1 276*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 277*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 278*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 279*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 280*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 281*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT 4 282*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 283*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT 5 284*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 285*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT 6 286*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 287*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT 7 288*14b24e2bSVaishali Kulkarni u8 flags13; 289*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 290*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT 0 291*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 292*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT 1 293*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 294*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 295*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 296*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 297*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 298*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 299*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 300*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 301*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 302*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 303*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 304*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 305*14b24e2bSVaishali Kulkarni u8 flags14; 306*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_MASK 0x1 /* bit16 */ 307*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT 0 308*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 309*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT 1 310*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_BIT18_MASK 0x1 /* bit18 */ 311*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT 2 312*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_BIT19_MASK 0x1 /* bit19 */ 313*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT 3 314*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_BIT20_MASK 0x1 /* bit20 */ 315*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT 4 316*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_BIT21_MASK 0x1 /* bit21 */ 317*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT 5 318*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 319*14b24e2bSVaishali Kulkarni #define E4_XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT 6 320*14b24e2bSVaishali Kulkarni u8 byte2 /* byte2 */; 321*14b24e2bSVaishali Kulkarni __le16 physical_q0 /* physical_q0 */; 322*14b24e2bSVaishali Kulkarni __le16 consolid_prod /* physical_q1 */; 323*14b24e2bSVaishali Kulkarni __le16 reserved16 /* physical_q2 */; 324*14b24e2bSVaishali Kulkarni __le16 tx_bd_cons /* word3 */; 325*14b24e2bSVaishali Kulkarni __le16 tx_bd_or_spq_prod /* word4 */; 326*14b24e2bSVaishali Kulkarni __le16 word5 /* word5 */; 327*14b24e2bSVaishali Kulkarni __le16 conn_dpi /* conn_dpi */; 328*14b24e2bSVaishali Kulkarni u8 byte3 /* byte3 */; 329*14b24e2bSVaishali Kulkarni u8 byte4 /* byte4 */; 330*14b24e2bSVaishali Kulkarni u8 byte5 /* byte5 */; 331*14b24e2bSVaishali Kulkarni u8 byte6 /* byte6 */; 332*14b24e2bSVaishali Kulkarni __le32 reg0 /* reg0 */; 333*14b24e2bSVaishali Kulkarni __le32 reg1 /* reg1 */; 334*14b24e2bSVaishali Kulkarni __le32 reg2 /* reg2 */; 335*14b24e2bSVaishali Kulkarni __le32 reg3 /* reg3 */; 336*14b24e2bSVaishali Kulkarni __le32 reg4 /* reg4 */; 337*14b24e2bSVaishali Kulkarni __le32 reg5 /* cf_array0 */; 338*14b24e2bSVaishali Kulkarni __le32 reg6 /* cf_array1 */; 339*14b24e2bSVaishali Kulkarni __le16 word7 /* word7 */; 340*14b24e2bSVaishali Kulkarni __le16 word8 /* word8 */; 341*14b24e2bSVaishali Kulkarni __le16 word9 /* word9 */; 342*14b24e2bSVaishali Kulkarni __le16 word10 /* word10 */; 343*14b24e2bSVaishali Kulkarni __le32 reg7 /* reg7 */; 344*14b24e2bSVaishali Kulkarni __le32 reg8 /* reg8 */; 345*14b24e2bSVaishali Kulkarni __le32 reg9 /* reg9 */; 346*14b24e2bSVaishali Kulkarni u8 byte7 /* byte7 */; 347*14b24e2bSVaishali Kulkarni u8 byte8 /* byte8 */; 348*14b24e2bSVaishali Kulkarni u8 byte9 /* byte9 */; 349*14b24e2bSVaishali Kulkarni u8 byte10 /* byte10 */; 350*14b24e2bSVaishali Kulkarni u8 byte11 /* byte11 */; 351*14b24e2bSVaishali Kulkarni u8 byte12 /* byte12 */; 352*14b24e2bSVaishali Kulkarni u8 byte13 /* byte13 */; 353*14b24e2bSVaishali Kulkarni u8 byte14 /* byte14 */; 354*14b24e2bSVaishali Kulkarni u8 byte15 /* byte15 */; 355*14b24e2bSVaishali Kulkarni u8 e5_reserved /* e5_reserved */; 356*14b24e2bSVaishali Kulkarni __le16 word11 /* word11 */; 357*14b24e2bSVaishali Kulkarni __le32 reg10 /* reg10 */; 358*14b24e2bSVaishali Kulkarni __le32 reg11 /* reg11 */; 359*14b24e2bSVaishali Kulkarni __le32 reg12 /* reg12 */; 360*14b24e2bSVaishali Kulkarni __le32 reg13 /* reg13 */; 361*14b24e2bSVaishali Kulkarni __le32 reg14 /* reg14 */; 362*14b24e2bSVaishali Kulkarni __le32 reg15 /* reg15 */; 363*14b24e2bSVaishali Kulkarni __le32 reg16 /* reg16 */; 364*14b24e2bSVaishali Kulkarni __le32 reg17 /* reg17 */; 365*14b24e2bSVaishali Kulkarni __le32 reg18 /* reg18 */; 366*14b24e2bSVaishali Kulkarni __le32 reg19 /* reg19 */; 367*14b24e2bSVaishali Kulkarni __le16 word12 /* word12 */; 368*14b24e2bSVaishali Kulkarni __le16 word13 /* word13 */; 369*14b24e2bSVaishali Kulkarni __le16 word14 /* word14 */; 370*14b24e2bSVaishali Kulkarni __le16 word15 /* word15 */; 371*14b24e2bSVaishali Kulkarni }; 372*14b24e2bSVaishali Kulkarni 373*14b24e2bSVaishali Kulkarni struct e4_tstorm_core_conn_ag_ctx 374*14b24e2bSVaishali Kulkarni { 375*14b24e2bSVaishali Kulkarni u8 byte0 /* cdu_validation */; 376*14b24e2bSVaishali Kulkarni u8 byte1 /* state */; 377*14b24e2bSVaishali Kulkarni u8 flags0; 378*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 379*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 380*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 381*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 382*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 383*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT 2 384*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 385*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT 3 386*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 387*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT 4 388*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 389*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT 5 390*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 391*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 6 392*14b24e2bSVaishali Kulkarni u8 flags1; 393*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 394*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 0 395*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 396*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 2 397*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 398*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 4 399*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 400*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 6 401*14b24e2bSVaishali Kulkarni u8 flags2; 402*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 403*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 0 404*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 405*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 2 406*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 407*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 4 408*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 409*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 6 410*14b24e2bSVaishali Kulkarni u8 flags3; 411*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 412*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 0 413*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 414*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 2 415*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 416*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 4 417*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 418*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 5 419*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 420*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 6 421*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 422*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 7 423*14b24e2bSVaishali Kulkarni u8 flags4; 424*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 425*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 0 426*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 427*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 1 428*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 429*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 2 430*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 431*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 3 432*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 433*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 4 434*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 435*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 5 436*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 437*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 6 438*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 439*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7 440*14b24e2bSVaishali Kulkarni u8 flags5; 441*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 442*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0 443*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 444*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1 445*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 446*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2 447*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 448*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3 449*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 450*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4 451*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 452*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5 453*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 454*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6 455*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 456*14b24e2bSVaishali Kulkarni #define E4_TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7 457*14b24e2bSVaishali Kulkarni __le32 reg0 /* reg0 */; 458*14b24e2bSVaishali Kulkarni __le32 reg1 /* reg1 */; 459*14b24e2bSVaishali Kulkarni __le32 reg2 /* reg2 */; 460*14b24e2bSVaishali Kulkarni __le32 reg3 /* reg3 */; 461*14b24e2bSVaishali Kulkarni __le32 reg4 /* reg4 */; 462*14b24e2bSVaishali Kulkarni __le32 reg5 /* reg5 */; 463*14b24e2bSVaishali Kulkarni __le32 reg6 /* reg6 */; 464*14b24e2bSVaishali Kulkarni __le32 reg7 /* reg7 */; 465*14b24e2bSVaishali Kulkarni __le32 reg8 /* reg8 */; 466*14b24e2bSVaishali Kulkarni u8 byte2 /* byte2 */; 467*14b24e2bSVaishali Kulkarni u8 byte3 /* byte3 */; 468*14b24e2bSVaishali Kulkarni __le16 word0 /* word0 */; 469*14b24e2bSVaishali Kulkarni u8 byte4 /* byte4 */; 470*14b24e2bSVaishali Kulkarni u8 byte5 /* byte5 */; 471*14b24e2bSVaishali Kulkarni __le16 word1 /* word1 */; 472*14b24e2bSVaishali Kulkarni __le16 word2 /* conn_dpi */; 473*14b24e2bSVaishali Kulkarni __le16 word3 /* word3 */; 474*14b24e2bSVaishali Kulkarni __le32 reg9 /* reg9 */; 475*14b24e2bSVaishali Kulkarni __le32 reg10 /* reg10 */; 476*14b24e2bSVaishali Kulkarni }; 477*14b24e2bSVaishali Kulkarni 478*14b24e2bSVaishali Kulkarni struct e4_ustorm_core_conn_ag_ctx 479*14b24e2bSVaishali Kulkarni { 480*14b24e2bSVaishali Kulkarni u8 reserved /* cdu_validation */; 481*14b24e2bSVaishali Kulkarni u8 byte1 /* state */; 482*14b24e2bSVaishali Kulkarni u8 flags0; 483*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 484*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 485*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 486*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 487*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 488*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2 489*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 490*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4 491*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 492*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6 493*14b24e2bSVaishali Kulkarni u8 flags1; 494*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 495*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_CF3_SHIFT 0 496*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 497*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_CF4_SHIFT 2 498*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 499*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_CF5_SHIFT 4 500*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 501*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_CF6_SHIFT 6 502*14b24e2bSVaishali Kulkarni u8 flags2; 503*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 504*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0 505*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 506*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1 507*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 508*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2 509*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 510*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 3 511*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 512*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 4 513*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 514*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 5 515*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 516*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 6 517*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 518*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7 519*14b24e2bSVaishali Kulkarni u8 flags3; 520*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 521*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0 522*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 523*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1 524*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 525*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2 526*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 527*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3 528*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 529*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4 530*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 531*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5 532*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 533*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6 534*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 535*14b24e2bSVaishali Kulkarni #define E4_USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7 536*14b24e2bSVaishali Kulkarni u8 byte2 /* byte2 */; 537*14b24e2bSVaishali Kulkarni u8 byte3 /* byte3 */; 538*14b24e2bSVaishali Kulkarni __le16 word0 /* conn_dpi */; 539*14b24e2bSVaishali Kulkarni __le16 word1 /* word1 */; 540*14b24e2bSVaishali Kulkarni __le32 rx_producers /* reg0 */; 541*14b24e2bSVaishali Kulkarni __le32 reg1 /* reg1 */; 542*14b24e2bSVaishali Kulkarni __le32 reg2 /* reg2 */; 543*14b24e2bSVaishali Kulkarni __le32 reg3 /* reg3 */; 544*14b24e2bSVaishali Kulkarni __le16 word2 /* word2 */; 545*14b24e2bSVaishali Kulkarni __le16 word3 /* word3 */; 546*14b24e2bSVaishali Kulkarni }; 547*14b24e2bSVaishali Kulkarni 548*14b24e2bSVaishali Kulkarni /* 549*14b24e2bSVaishali Kulkarni * The core storm context for the Mstorm 550*14b24e2bSVaishali Kulkarni */ 551*14b24e2bSVaishali Kulkarni struct mstorm_core_conn_st_ctx 552*14b24e2bSVaishali Kulkarni { 553*14b24e2bSVaishali Kulkarni __le32 reserved[24]; 554*14b24e2bSVaishali Kulkarni }; 555*14b24e2bSVaishali Kulkarni 556*14b24e2bSVaishali Kulkarni /* 557*14b24e2bSVaishali Kulkarni * The core storm context for the Ustorm 558*14b24e2bSVaishali Kulkarni */ 559*14b24e2bSVaishali Kulkarni struct ustorm_core_conn_st_ctx 560*14b24e2bSVaishali Kulkarni { 561*14b24e2bSVaishali Kulkarni __le32 reserved[4]; 562*14b24e2bSVaishali Kulkarni }; 563*14b24e2bSVaishali Kulkarni 564*14b24e2bSVaishali Kulkarni /* 565*14b24e2bSVaishali Kulkarni * core connection context 566*14b24e2bSVaishali Kulkarni */ 567*14b24e2bSVaishali Kulkarni struct core_conn_context 568*14b24e2bSVaishali Kulkarni { 569*14b24e2bSVaishali Kulkarni struct ystorm_core_conn_st_ctx ystorm_st_context /* ystorm storm context */; 570*14b24e2bSVaishali Kulkarni struct regpair ystorm_st_padding[2] /* padding */; 571*14b24e2bSVaishali Kulkarni struct pstorm_core_conn_st_ctx pstorm_st_context /* pstorm storm context */; 572*14b24e2bSVaishali Kulkarni struct regpair pstorm_st_padding[2] /* padding */; 573*14b24e2bSVaishali Kulkarni struct xstorm_core_conn_st_ctx xstorm_st_context /* xstorm storm context */; 574*14b24e2bSVaishali Kulkarni struct e4_xstorm_core_conn_ag_ctx xstorm_ag_context /* xstorm aggregative context */; 575*14b24e2bSVaishali Kulkarni struct e4_tstorm_core_conn_ag_ctx tstorm_ag_context /* tstorm aggregative context */; 576*14b24e2bSVaishali Kulkarni struct e4_ustorm_core_conn_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 577*14b24e2bSVaishali Kulkarni struct mstorm_core_conn_st_ctx mstorm_st_context /* mstorm storm context */; 578*14b24e2bSVaishali Kulkarni struct ustorm_core_conn_st_ctx ustorm_st_context /* ustorm storm context */; 579*14b24e2bSVaishali Kulkarni struct regpair ustorm_st_padding[2] /* padding */; 580*14b24e2bSVaishali Kulkarni }; 581*14b24e2bSVaishali Kulkarni 582*14b24e2bSVaishali Kulkarni 583*14b24e2bSVaishali Kulkarni /* 584*14b24e2bSVaishali Kulkarni * How ll2 should deal with packet upon errors 585*14b24e2bSVaishali Kulkarni */ 586*14b24e2bSVaishali Kulkarni enum core_error_handle 587*14b24e2bSVaishali Kulkarni { 588*14b24e2bSVaishali Kulkarni LL2_DROP_PACKET /* If error occurs drop packet */, 589*14b24e2bSVaishali Kulkarni LL2_DO_NOTHING /* If error occurs do nothing */, 590*14b24e2bSVaishali Kulkarni LL2_ASSERT /* If error occurs assert */, 591*14b24e2bSVaishali Kulkarni MAX_CORE_ERROR_HANDLE 592*14b24e2bSVaishali Kulkarni }; 593*14b24e2bSVaishali Kulkarni 594*14b24e2bSVaishali Kulkarni 595*14b24e2bSVaishali Kulkarni /* 596*14b24e2bSVaishali Kulkarni * opcodes for the event ring 597*14b24e2bSVaishali Kulkarni */ 598*14b24e2bSVaishali Kulkarni enum core_event_opcode 599*14b24e2bSVaishali Kulkarni { 600*14b24e2bSVaishali Kulkarni CORE_EVENT_TX_QUEUE_START, 601*14b24e2bSVaishali Kulkarni CORE_EVENT_TX_QUEUE_STOP, 602*14b24e2bSVaishali Kulkarni CORE_EVENT_RX_QUEUE_START, 603*14b24e2bSVaishali Kulkarni CORE_EVENT_RX_QUEUE_STOP, 604*14b24e2bSVaishali Kulkarni CORE_EVENT_RX_QUEUE_FLUSH, 605*14b24e2bSVaishali Kulkarni MAX_CORE_EVENT_OPCODE 606*14b24e2bSVaishali Kulkarni }; 607*14b24e2bSVaishali Kulkarni 608*14b24e2bSVaishali Kulkarni 609*14b24e2bSVaishali Kulkarni /* 610*14b24e2bSVaishali Kulkarni * The L4 pseudo checksum mode for Core 611*14b24e2bSVaishali Kulkarni */ 612*14b24e2bSVaishali Kulkarni enum core_l4_pseudo_checksum_mode 613*14b24e2bSVaishali Kulkarni { 614*14b24e2bSVaishali Kulkarni CORE_L4_PSEUDO_CSUM_CORRECT_LENGTH /* Pseudo Checksum on packet is calculated with the correct packet length. */, 615*14b24e2bSVaishali Kulkarni CORE_L4_PSEUDO_CSUM_ZERO_LENGTH /* Pseudo Checksum on packet is calculated with zero length. */, 616*14b24e2bSVaishali Kulkarni MAX_CORE_L4_PSEUDO_CHECKSUM_MODE 617*14b24e2bSVaishali Kulkarni }; 618*14b24e2bSVaishali Kulkarni 619*14b24e2bSVaishali Kulkarni 620*14b24e2bSVaishali Kulkarni /* 621*14b24e2bSVaishali Kulkarni * Light-L2 RX Producers in Tstorm RAM 622*14b24e2bSVaishali Kulkarni */ 623*14b24e2bSVaishali Kulkarni struct core_ll2_port_stats 624*14b24e2bSVaishali Kulkarni { 625*14b24e2bSVaishali Kulkarni struct regpair gsi_invalid_hdr; 626*14b24e2bSVaishali Kulkarni struct regpair gsi_invalid_pkt_length; 627*14b24e2bSVaishali Kulkarni struct regpair gsi_unsupported_pkt_typ; 628*14b24e2bSVaishali Kulkarni struct regpair gsi_crcchksm_error; 629*14b24e2bSVaishali Kulkarni }; 630*14b24e2bSVaishali Kulkarni 631*14b24e2bSVaishali Kulkarni 632*14b24e2bSVaishali Kulkarni /* 633*14b24e2bSVaishali Kulkarni * Ethernet TX Per Queue Stats 634*14b24e2bSVaishali Kulkarni */ 635*14b24e2bSVaishali Kulkarni struct core_ll2_pstorm_per_queue_stat 636*14b24e2bSVaishali Kulkarni { 637*14b24e2bSVaishali Kulkarni struct regpair sent_ucast_bytes /* number of total bytes sent without errors */; 638*14b24e2bSVaishali Kulkarni struct regpair sent_mcast_bytes /* number of total bytes sent without errors */; 639*14b24e2bSVaishali Kulkarni struct regpair sent_bcast_bytes /* number of total bytes sent without errors */; 640*14b24e2bSVaishali Kulkarni struct regpair sent_ucast_pkts /* number of total packets sent without errors */; 641*14b24e2bSVaishali Kulkarni struct regpair sent_mcast_pkts /* number of total packets sent without errors */; 642*14b24e2bSVaishali Kulkarni struct regpair sent_bcast_pkts /* number of total packets sent without errors */; 643*14b24e2bSVaishali Kulkarni }; 644*14b24e2bSVaishali Kulkarni 645*14b24e2bSVaishali Kulkarni 646*14b24e2bSVaishali Kulkarni /* 647*14b24e2bSVaishali Kulkarni * Light-L2 RX Producers in Tstorm RAM 648*14b24e2bSVaishali Kulkarni */ 649*14b24e2bSVaishali Kulkarni struct core_ll2_rx_prod 650*14b24e2bSVaishali Kulkarni { 651*14b24e2bSVaishali Kulkarni __le16 bd_prod /* BD Producer */; 652*14b24e2bSVaishali Kulkarni __le16 cqe_prod /* CQE Producer */; 653*14b24e2bSVaishali Kulkarni __le32 reserved; 654*14b24e2bSVaishali Kulkarni }; 655*14b24e2bSVaishali Kulkarni 656*14b24e2bSVaishali Kulkarni 657*14b24e2bSVaishali Kulkarni struct core_ll2_tstorm_per_queue_stat 658*14b24e2bSVaishali Kulkarni { 659*14b24e2bSVaishali Kulkarni struct regpair packet_too_big_discard /* Number of packets discarded because they are bigger than MTU */; 660*14b24e2bSVaishali Kulkarni struct regpair no_buff_discard /* Number of packets discarded due to lack of host buffers */; 661*14b24e2bSVaishali Kulkarni }; 662*14b24e2bSVaishali Kulkarni 663*14b24e2bSVaishali Kulkarni 664*14b24e2bSVaishali Kulkarni struct core_ll2_ustorm_per_queue_stat 665*14b24e2bSVaishali Kulkarni { 666*14b24e2bSVaishali Kulkarni struct regpair rcv_ucast_bytes; 667*14b24e2bSVaishali Kulkarni struct regpair rcv_mcast_bytes; 668*14b24e2bSVaishali Kulkarni struct regpair rcv_bcast_bytes; 669*14b24e2bSVaishali Kulkarni struct regpair rcv_ucast_pkts; 670*14b24e2bSVaishali Kulkarni struct regpair rcv_mcast_pkts; 671*14b24e2bSVaishali Kulkarni struct regpair rcv_bcast_pkts; 672*14b24e2bSVaishali Kulkarni }; 673*14b24e2bSVaishali Kulkarni 674*14b24e2bSVaishali Kulkarni 675*14b24e2bSVaishali Kulkarni /* 676*14b24e2bSVaishali Kulkarni * Core Ramrod Command IDs (light L2) 677*14b24e2bSVaishali Kulkarni */ 678*14b24e2bSVaishali Kulkarni enum core_ramrod_cmd_id 679*14b24e2bSVaishali Kulkarni { 680*14b24e2bSVaishali Kulkarni CORE_RAMROD_UNUSED, 681*14b24e2bSVaishali Kulkarni CORE_RAMROD_RX_QUEUE_START /* RX Queue Start Ramrod */, 682*14b24e2bSVaishali Kulkarni CORE_RAMROD_TX_QUEUE_START /* TX Queue Start Ramrod */, 683*14b24e2bSVaishali Kulkarni CORE_RAMROD_RX_QUEUE_STOP /* RX Queue Stop Ramrod */, 684*14b24e2bSVaishali Kulkarni CORE_RAMROD_TX_QUEUE_STOP /* TX Queue Stop Ramrod */, 685*14b24e2bSVaishali Kulkarni CORE_RAMROD_RX_QUEUE_FLUSH /* RX Flush queue Ramrod */, 686*14b24e2bSVaishali Kulkarni MAX_CORE_RAMROD_CMD_ID 687*14b24e2bSVaishali Kulkarni }; 688*14b24e2bSVaishali Kulkarni 689*14b24e2bSVaishali Kulkarni 690*14b24e2bSVaishali Kulkarni /* 691*14b24e2bSVaishali Kulkarni * Core RX CQE Type for Light L2 692*14b24e2bSVaishali Kulkarni */ 693*14b24e2bSVaishali Kulkarni enum core_roce_flavor_type 694*14b24e2bSVaishali Kulkarni { 695*14b24e2bSVaishali Kulkarni CORE_ROCE, 696*14b24e2bSVaishali Kulkarni CORE_RROCE, 697*14b24e2bSVaishali Kulkarni MAX_CORE_ROCE_FLAVOR_TYPE 698*14b24e2bSVaishali Kulkarni }; 699*14b24e2bSVaishali Kulkarni 700*14b24e2bSVaishali Kulkarni 701*14b24e2bSVaishali Kulkarni /* 702*14b24e2bSVaishali Kulkarni * Specifies how ll2 should deal with packets errors: packet_too_big and no_buff 703*14b24e2bSVaishali Kulkarni */ 704*14b24e2bSVaishali Kulkarni struct core_rx_action_on_error 705*14b24e2bSVaishali Kulkarni { 706*14b24e2bSVaishali Kulkarni u8 error_type; 707*14b24e2bSVaishali Kulkarni #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK 0x3 /* ll2 how to handle error packet_too_big (use enum core_error_handle) */ 708*14b24e2bSVaishali Kulkarni #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT 0 709*14b24e2bSVaishali Kulkarni #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK 0x3 /* ll2 how to handle error with no_buff (use enum core_error_handle) */ 710*14b24e2bSVaishali Kulkarni #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_SHIFT 2 711*14b24e2bSVaishali Kulkarni #define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK 0xF 712*14b24e2bSVaishali Kulkarni #define