114b24e2bSVaishali Kulkarni /*
214b24e2bSVaishali Kulkarni * CDDL HEADER START
314b24e2bSVaishali Kulkarni *
414b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the
514b24e2bSVaishali Kulkarni * Common Development and Distribution License, v.1,  (the "License").
614b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License.
714b24e2bSVaishali Kulkarni *
814b24e2bSVaishali Kulkarni * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
914b24e2bSVaishali Kulkarni * or http://opensource.org/licenses/CDDL-1.0.
1014b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions
1114b24e2bSVaishali Kulkarni * and limitations under the License.
1214b24e2bSVaishali Kulkarni *
1314b24e2bSVaishali Kulkarni * When distributing Covered Code, include this CDDL HEADER in each
1414b24e2bSVaishali Kulkarni * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1514b24e2bSVaishali Kulkarni * If applicable, add the following below this CDDL HEADER, with the
1614b24e2bSVaishali Kulkarni * fields enclosed by brackets "[]" replaced with your own identifying
1714b24e2bSVaishali Kulkarni * information: Portions Copyright [yyyy] [name of copyright owner]
1814b24e2bSVaishali Kulkarni *
1914b24e2bSVaishali Kulkarni * CDDL HEADER END
2014b24e2bSVaishali Kulkarni */
2114b24e2bSVaishali Kulkarni 
2214b24e2bSVaishali Kulkarni /*
2314b24e2bSVaishali Kulkarni * Copyright 2014-2017 Cavium, Inc.
2414b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the Common Development
2514b24e2bSVaishali Kulkarni * and Distribution License, v.1,  (the "License").
2614b24e2bSVaishali Kulkarni 
2714b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License.
2814b24e2bSVaishali Kulkarni 
2914b24e2bSVaishali Kulkarni * You can obtain a copy of the License at available
3014b24e2bSVaishali Kulkarni * at http://opensource.org/licenses/CDDL-1.0
3114b24e2bSVaishali Kulkarni 
3214b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions and
3314b24e2bSVaishali Kulkarni * limitations under the License.
3414b24e2bSVaishali Kulkarni */
3514b24e2bSVaishali Kulkarni 
3614b24e2bSVaishali Kulkarni #include "bcm_osal.h"
3714b24e2bSVaishali Kulkarni #include "ecore.h"
3814b24e2bSVaishali Kulkarni #include "ecore_hw.h"
3914b24e2bSVaishali Kulkarni #include "ecore_mcp.h"
4014b24e2bSVaishali Kulkarni #include "spad_layout.h"
4114b24e2bSVaishali Kulkarni #include "nvm_map.h"
4214b24e2bSVaishali Kulkarni #include "reg_addr.h"
4314b24e2bSVaishali Kulkarni #include "ecore_hsi_common.h"
4414b24e2bSVaishali Kulkarni #include "ecore_hsi_debug_tools.h"
4514b24e2bSVaishali Kulkarni #include "mcp_public.h"
4614b24e2bSVaishali Kulkarni #include "nvm_map.h"
4714b24e2bSVaishali Kulkarni #ifndef USE_DBG_BIN_FILE
4814b24e2bSVaishali Kulkarni #include "ecore_dbg_values.h"
4914b24e2bSVaishali Kulkarni #endif
5014b24e2bSVaishali Kulkarni #include "ecore_dbg_fw_funcs.h"
5114b24e2bSVaishali Kulkarni 
5214b24e2bSVaishali Kulkarni /* Memory groups enum */
5314b24e2bSVaishali Kulkarni enum mem_groups {
5414b24e2bSVaishali Kulkarni 	MEM_GROUP_PXP_MEM,
5514b24e2bSVaishali Kulkarni 	MEM_GROUP_DMAE_MEM,
5614b24e2bSVaishali Kulkarni 	MEM_GROUP_CM_MEM,
5714b24e2bSVaishali Kulkarni 	MEM_GROUP_QM_MEM,
5814b24e2bSVaishali Kulkarni 	MEM_GROUP_TM_MEM,
5914b24e2bSVaishali Kulkarni 	MEM_GROUP_BRB_RAM,
6014b24e2bSVaishali Kulkarni 	MEM_GROUP_BRB_MEM,
6114b24e2bSVaishali Kulkarni 	MEM_GROUP_PRS_MEM,
6214b24e2bSVaishali Kulkarni 	MEM_GROUP_SDM_MEM,
6314b24e2bSVaishali Kulkarni 	MEM_GROUP_IOR,
6414b24e2bSVaishali Kulkarni 	MEM_GROUP_RAM,
6514b24e2bSVaishali Kulkarni 	MEM_GROUP_BTB_RAM,
6614b24e2bSVaishali Kulkarni 	MEM_GROUP_RDIF_CTX,
6714b24e2bSVaishali Kulkarni 	MEM_GROUP_TDIF_CTX,
6814b24e2bSVaishali Kulkarni 	MEM_GROUP_CFC_MEM,
6914b24e2bSVaishali Kulkarni 	MEM_GROUP_CONN_CFC_MEM,
7014b24e2bSVaishali Kulkarni 	MEM_GROUP_TASK_CFC_MEM,
7114b24e2bSVaishali Kulkarni 	MEM_GROUP_CAU_PI,
7214b24e2bSVaishali Kulkarni 	MEM_GROUP_CAU_MEM,
7314b24e2bSVaishali Kulkarni 	MEM_GROUP_PXP_ILT,
7414b24e2bSVaishali Kulkarni 	MEM_GROUP_PBUF,
7514b24e2bSVaishali Kulkarni 	MEM_GROUP_MULD_MEM,
7614b24e2bSVaishali Kulkarni 	MEM_GROUP_BTB_MEM,
7714b24e2bSVaishali Kulkarni 	MEM_GROUP_IGU_MEM,
7814b24e2bSVaishali Kulkarni 	MEM_GROUP_IGU_MSIX,
7914b24e2bSVaishali Kulkarni 	MEM_GROUP_CAU_SB,
8014b24e2bSVaishali Kulkarni 	MEM_GROUP_BMB_RAM,
8114b24e2bSVaishali Kulkarni 	MEM_GROUP_BMB_MEM,
8214b24e2bSVaishali Kulkarni 	MEM_GROUPS_NUM
8314b24e2bSVaishali Kulkarni };
8414b24e2bSVaishali Kulkarni 
8514b24e2bSVaishali Kulkarni /* Memory groups names */
8614b24e2bSVaishali Kulkarni static const char* s_mem_group_names[] = {
8714b24e2bSVaishali Kulkarni 	"PXP_MEM",
8814b24e2bSVaishali Kulkarni 	"DMAE_MEM",
8914b24e2bSVaishali Kulkarni 	"CM_MEM",
9014b24e2bSVaishali Kulkarni 	"QM_MEM",
9114b24e2bSVaishali Kulkarni 	"TM_MEM",
9214b24e2bSVaishali Kulkarni 	"BRB_RAM",
9314b24e2bSVaishali Kulkarni 	"BRB_MEM",
9414b24e2bSVaishali Kulkarni 	"PRS_MEM",
9514b24e2bSVaishali Kulkarni 	"SDM_MEM",
9614b24e2bSVaishali Kulkarni 	"IOR",
9714b24e2bSVaishali Kulkarni 	"RAM",
9814b24e2bSVaishali Kulkarni 	"BTB_RAM",
9914b24e2bSVaishali Kulkarni 	"RDIF_CTX",
10014b24e2bSVaishali Kulkarni 	"TDIF_CTX",
10114b24e2bSVaishali Kulkarni 	"CFC_MEM",
10214b24e2bSVaishali Kulkarni 	"CONN_CFC_MEM",
10314b24e2bSVaishali Kulkarni 	"TASK_CFC_MEM",
10414b24e2bSVaishali Kulkarni 	"CAU_PI",
10514b24e2bSVaishali Kulkarni 	"CAU_MEM",
10614b24e2bSVaishali Kulkarni 	"PXP_ILT",
10714b24e2bSVaishali Kulkarni 	"PBUF",
10814b24e2bSVaishali Kulkarni 	"MULD_MEM",
10914b24e2bSVaishali Kulkarni 	"BTB_MEM",
11014b24e2bSVaishali Kulkarni 	"IGU_MEM",
11114b24e2bSVaishali Kulkarni 	"IGU_MSIX",
11214b24e2bSVaishali Kulkarni 	"CAU_SB",
11314b24e2bSVaishali Kulkarni 	"BMB_RAM",
11414b24e2bSVaishali Kulkarni 	"BMB_MEM",
11514b24e2bSVaishali Kulkarni };
11614b24e2bSVaishali Kulkarni 
11714b24e2bSVaishali Kulkarni /* Idle check conditions */
11814b24e2bSVaishali Kulkarni 
11914b24e2bSVaishali Kulkarni #ifndef __PREVENT_COND_ARR__
12014b24e2bSVaishali Kulkarni 
cond5(const u32 * r,const u32 * imm)12114b24e2bSVaishali Kulkarni static u32 cond5(const u32 *r, const u32 *imm) {
12214b24e2bSVaishali Kulkarni 	return (((r[0] & imm[0]) != imm[1]) && ((r[1] & imm[2]) != imm[3]));
12314b24e2bSVaishali Kulkarni }
12414b24e2bSVaishali Kulkarni 
cond7(const u32 * r,const u32 * imm)12514b24e2bSVaishali Kulkarni static u32 cond7(const u32 *r, const u32 *imm) {
12614b24e2bSVaishali Kulkarni 	return (((r[0] >> imm[0]) & imm[1]) != imm[2]);
12714b24e2bSVaishali Kulkarni }
12814b24e2bSVaishali Kulkarni 
cond14(const u32 * r,const u32 * imm)12914b24e2bSVaishali Kulkarni static u32 cond14(const u32 *r, const u32 *imm) {
13014b24e2bSVaishali Kulkarni 	return ((r[0] != imm[0]) && (((r[1] >> imm[1]) & imm[2]) == imm[3]));
13114b24e2bSVaishali Kulkarni }
13214b24e2bSVaishali Kulkarni 
cond6(const u32 * r,const u32 * imm)13314b24e2bSVaishali Kulkarni static u32 cond6(const u32 *r, const u32 *imm) {
13414b24e2bSVaishali Kulkarni 	return ((r[0] & imm[0]) != imm[1]);
13514b24e2bSVaishali Kulkarni }
13614b24e2bSVaishali Kulkarni 
cond9(const u32 * r,const u32 * imm)13714b24e2bSVaishali Kulkarni static u32 cond9(const u32 *r, const u32 *imm) {
13814b24e2bSVaishali Kulkarni 	return ((r[0] & imm[0]) >> imm[1]) != (((r[0] & imm[2]) >> imm[3]) | ((r[1] & imm[4]) << imm[5]));
13914b24e2bSVaishali Kulkarni }
14014b24e2bSVaishali Kulkarni 
cond10(const u32 * r,const u32 * imm)14114b24e2bSVaishali Kulkarni static u32 cond10(const u32 *r, const u32 *imm) {
14214b24e2bSVaishali Kulkarni 	return ((r[0] & imm[0]) >> imm[1]) != (r[0] & imm[2]);
14314b24e2bSVaishali Kulkarni }
14414b24e2bSVaishali Kulkarni 
cond4(const u32 * r,const u32 * imm)14514b24e2bSVaishali Kulkarni static u32 cond4(const u32 *r, const u32 *imm) {
14614b24e2bSVaishali Kulkarni 	return ((r[0] & ~imm[0]) != imm[1]);
14714b24e2bSVaishali Kulkarni }
14814b24e2bSVaishali Kulkarni 
cond0(const u32 * r,const u32 * imm)14914b24e2bSVaishali Kulkarni static u32 cond0(const u32 *r, const u32 *imm) {
15014b24e2bSVaishali Kulkarni 	return ((r[0] & ~r[1]) != imm[0]);
15114b24e2bSVaishali Kulkarni }
15214b24e2bSVaishali Kulkarni 
cond1(const u32 * r,const u32 * imm)15314b24e2bSVaishali Kulkarni static u32 cond1(const u32 *r, const u32 *imm) {
15414b24e2bSVaishali Kulkarni 	return (r[0] != imm[0]);
15514b24e2bSVaishali Kulkarni }
15614b24e2bSVaishali Kulkarni 
cond11(const u32 * r,const u32 * imm)15714b24e2bSVaishali Kulkarni static u32 cond11(const u32 *r, const u32 *imm) {
15814b24e2bSVaishali Kulkarni 	return (r[0] != r[1] && r[2] == imm[0]);
15914b24e2bSVaishali Kulkarni }
16014b24e2bSVaishali Kulkarni 
cond12(const u32 * r,const u32 * imm)16114b24e2bSVaishali Kulkarni static u32 cond12(const u32 *r, const u32 *imm) {
16214b24e2bSVaishali Kulkarni 	return (r[0] != r[1] && r[2] > imm[0]);
16314b24e2bSVaishali Kulkarni }
16414b24e2bSVaishali Kulkarni 
cond3(const u32 * r,const u32 * imm)16514b24e2bSVaishali Kulkarni static u32 cond3(const u32 *r, const u32 *imm) {
16614b24e2bSVaishali Kulkarni 	return (r[0] != r[1]);
16714b24e2bSVaishali Kulkarni }
16814b24e2bSVaishali Kulkarni 
cond13(const u32 * r,const u32 * imm)16914b24e2bSVaishali Kulkarni static u32 cond13(const u32 *r, const u32 *imm) {
17014b24e2bSVaishali Kulkarni 	return (r[0] & imm[0]);
17114b24e2bSVaishali Kulkarni }
17214b24e2bSVaishali Kulkarni 
cond8(const u32 * r,const u32 * imm)17314b24e2bSVaishali Kulkarni static u32 cond8(const u32 *r, const u32 *imm) {
17414b24e2bSVaishali Kulkarni 	return (r[0] < (r[1] - imm[0]));
17514b24e2bSVaishali Kulkarni }
17614b24e2bSVaishali Kulkarni 
cond2(const u32 * r,const u32 * imm)17714b24e2bSVaishali Kulkarni static u32 cond2(const u32 *r, const u32 *imm) {
17814b24e2bSVaishali Kulkarni 	return (r[0] > imm[0]);
17914b24e2bSVaishali Kulkarni }
18014b24e2bSVaishali Kulkarni 
18114b24e2bSVaishali Kulkarni /* Array of Idle Check conditions */
18214b24e2bSVaishali Kulkarni static u32 (*cond_arr[])(const u32 *r, const u32 *imm) = {
18314b24e2bSVaishali Kulkarni 	cond0,
18414b24e2bSVaishali Kulkarni 	cond1,
18514b24e2bSVaishali Kulkarni 	cond2,
18614b24e2bSVaishali Kulkarni 	cond3,
18714b24e2bSVaishali Kulkarni 	cond4,
18814b24e2bSVaishali Kulkarni 	cond5,
18914b24e2bSVaishali Kulkarni 	cond6,
19014b24e2bSVaishali Kulkarni 	cond7,
19114b24e2bSVaishali Kulkarni 	cond8,
19214b24e2bSVaishali Kulkarni 	cond9,
19314b24e2bSVaishali Kulkarni 	cond10,
19414b24e2bSVaishali Kulkarni 	cond11,
19514b24e2bSVaishali Kulkarni 	cond12,
19614b24e2bSVaishali Kulkarni 	cond13,
19714b24e2bSVaishali Kulkarni 	cond14,
19814b24e2bSVaishali Kulkarni };
19914b24e2bSVaishali Kulkarni 
20014b24e2bSVaishali Kulkarni #endif /* __PREVENT_COND_ARR__ */
20114b24e2bSVaishali Kulkarni 
20214b24e2bSVaishali Kulkarni 
20314b24e2bSVaishali Kulkarni /******************************* Data Types **********************************/
20414b24e2bSVaishali Kulkarni 
20514b24e2bSVaishali Kulkarni enum platform_ids {
20614b24e2bSVaishali Kulkarni 	PLATFORM_ASIC,
20714b24e2bSVaishali Kulkarni 	PLATFORM_EMUL_FULL,
20814b24e2bSVaishali Kulkarni 	PLATFORM_EMUL_REDUCED,
20914b24e2bSVaishali Kulkarni 	PLATFORM_FPGA,
21014b24e2bSVaishali Kulkarni 	MAX_PLATFORM_IDS
21114b24e2bSVaishali Kulkarni };
21214b24e2bSVaishali Kulkarni 
21314b24e2bSVaishali Kulkarni struct chip_platform_defs {
21414b24e2bSVaishali Kulkarni 	u8 num_ports;
21514b24e2bSVaishali Kulkarni 	u8 num_pfs;
21614b24e2bSVaishali Kulkarni 	u8 num_vfs;
21714b24e2bSVaishali Kulkarni };
21814b24e2bSVaishali Kulkarni 
21914b24e2bSVaishali Kulkarni /* Chip constant definitions */
22014b24e2bSVaishali Kulkarni struct chip_defs {
22114b24e2bSVaishali Kulkarni 	const char *name;
22214b24e2bSVaishali Kulkarni 	struct chip_platform_defs per_platform[MAX_PLATFORM_IDS];
22314b24e2bSVaishali Kulkarni };
22414b24e2bSVaishali Kulkarni 
22514b24e2bSVaishali Kulkarni /* Platform constant definitions */
22614b24e2bSVaishali Kulkarni struct platform_defs {
22714b24e2bSVaishali Kulkarni 	const char *name;
22814b24e2bSVaishali Kulkarni 	u32 delay_factor;
22914b24e2bSVaishali Kulkarni };
23014b24e2bSVaishali Kulkarni 
23114b24e2bSVaishali Kulkarni /* Storm constant definitions.
23214b24e2bSVaishali Kulkarni  * Addresses are in bytes, sizes are in quad-regs.
23314b24e2bSVaishali Kulkarni  */
23414b24e2bSVaishali Kulkarni struct storm_defs {
23514b24e2bSVaishali Kulkarni 	char letter;
23614b24e2bSVaishali Kulkarni 	enum block_id block_id;
23714b24e2bSVaishali Kulkarni 	enum dbg_bus_clients dbg_client_id[MAX_CHIP_IDS];
23814b24e2bSVaishali Kulkarni 	bool has_vfc;
23914b24e2bSVaishali Kulkarni 	u32 sem_fast_mem_addr;
24014b24e2bSVaishali Kulkarni 	u32 sem_frame_mode_addr;
24114b24e2bSVaishali Kulkarni 	u32 sem_slow_enable_addr;
24214b24e2bSVaishali Kulkarni 	u32 sem_slow_mode_addr;
24314b24e2bSVaishali Kulkarni 	u32 sem_slow_mode1_conf_addr;
24414b24e2bSVaishali Kulkarni 	u32 sem_sync_dbg_empty_addr;
24514b24e2bSVaishali Kulkarni 	u32 sem_slow_dbg_empty_addr;
24614b24e2bSVaishali Kulkarni 	u32 cm_ctx_wr_addr;
24714b24e2bSVaishali Kulkarni 	u32 cm_conn_ag_ctx_lid_size;
24814b24e2bSVaishali Kulkarni 	u32 cm_conn_ag_ctx_rd_addr;
24914b24e2bSVaishali Kulkarni 	u32 cm_conn_st_ctx_lid_size;
25014b24e2bSVaishali Kulkarni 	u32 cm_conn_st_ctx_rd_addr;
25114b24e2bSVaishali Kulkarni 	u32 cm_task_ag_ctx_lid_size;
25214b24e2bSVaishali Kulkarni 	u32 cm_task_ag_ctx_rd_addr;
25314b24e2bSVaishali Kulkarni 	u32 cm_task_st_ctx_lid_size;
25414b24e2bSVaishali Kulkarni 	u32 cm_task_st_ctx_rd_addr;
25514b24e2bSVaishali Kulkarni };
25614b24e2bSVaishali Kulkarni 
25714b24e2bSVaishali Kulkarni /* Block constant definitions */
25814b24e2bSVaishali Kulkarni struct block_defs {
25914b24e2bSVaishali Kulkarni 	const char *name;
26014b24e2bSVaishali Kulkarni 	bool has_dbg_bus[MAX_CHIP_IDS];
26114b24e2bSVaishali Kulkarni 	bool associated_to_storm;
26214b24e2bSVaishali Kulkarni 
26314b24e2bSVaishali Kulkarni 	/* Valid only if associated_to_storm is true */
26414b24e2bSVaishali Kulkarni 	u32 storm_id;
26514b24e2bSVaishali Kulkarni 	enum dbg_bus_clients dbg_client_id[MAX_CHIP_IDS];
26614b24e2bSVaishali Kulkarni 	u32 dbg_select_addr;
26714b24e2bSVaishali Kulkarni 	u32 dbg_enable_addr;
26814b24e2bSVaishali Kulkarni 	u32 dbg_shift_addr;
26914b24e2bSVaishali Kulkarni 	u32 dbg_force_valid_addr;
27014b24e2bSVaishali Kulkarni 	u32 dbg_force_frame_addr;
27114b24e2bSVaishali Kulkarni 	bool has_reset_bit;
27214b24e2bSVaishali Kulkarni 
27314b24e2bSVaishali Kulkarni 	/* If true, block is taken out of reset before dump */
27414b24e2bSVaishali Kulkarni 	bool unreset;
27514b24e2bSVaishali Kulkarni 	enum dbg_reset_regs reset_reg;
27614b24e2bSVaishali Kulkarni 
27714b24e2bSVaishali Kulkarni 	/* Bit offset in reset register */
27814b24e2bSVaishali Kulkarni 	u8 reset_bit_offset;
27914b24e2bSVaishali Kulkarni };
28014b24e2bSVaishali Kulkarni 
28114b24e2bSVaishali Kulkarni /* Reset register definitions */
28214b24e2bSVaishali Kulkarni struct reset_reg_defs {
28314b24e2bSVaishali Kulkarni 	u32 addr;
28414b24e2bSVaishali Kulkarni 	u32 unreset_val;
28514b24e2bSVaishali Kulkarni 	bool exists[MAX_CHIP_IDS];
28614b24e2bSVaishali Kulkarni };
28714b24e2bSVaishali Kulkarni 
28814b24e2bSVaishali Kulkarni /* Debug Bus Constraint operation constant definitions */
28914b24e2bSVaishali Kulkarni struct dbg_bus_constraint_op_defs {
29014b24e2bSVaishali Kulkarni 	u8 hw_op_val;
29114b24e2bSVaishali Kulkarni 	bool is_cyclic;
29214b24e2bSVaishali Kulkarni };
29314b24e2bSVaishali Kulkarni 
29414b24e2bSVaishali Kulkarni /* Storm Mode definitions */
29514b24e2bSVaishali Kulkarni struct storm_mode_defs {
29614b24e2bSVaishali Kulkarni 	const char *name;
29714b24e2bSVaishali Kulkarni 	bool is_fast_dbg;
29814b24e2bSVaishali Kulkarni 	u8 id_in_hw;
29914b24e2bSVaishali Kulkarni };
30014b24e2bSVaishali Kulkarni 
30114b24e2bSVaishali Kulkarni struct grc_param_defs {
30214b24e2bSVaishali Kulkarni 	u32 default_val[MAX_CHIP_IDS];
30314b24e2bSVaishali Kulkarni 	u32 min;
30414b24e2bSVaishali Kulkarni 	u32 max;
30514b24e2bSVaishali Kulkarni 	bool is_preset;
30614b24e2bSVaishali Kulkarni 	u32 exclude_all_preset_val;
30714b24e2bSVaishali Kulkarni 	u32 crash_preset_val;
30814b24e2bSVaishali Kulkarni };
30914b24e2bSVaishali Kulkarni 
31014b24e2bSVaishali Kulkarni /* address is in 128b units. Width is in bits. */
31114b24e2bSVaishali Kulkarni struct rss_mem_defs {
31214b24e2bSVaishali Kulkarni 	const char *mem_name;
31314b24e2bSVaishali Kulkarni 	const char *type_name;
31414b24e2bSVaishali Kulkarni 	u32 addr;
31514b24e2bSVaishali Kulkarni 	u32 num_entries[MAX_CHIP_IDS];
31614b24e2bSVaishali Kulkarni 	u32 entry_width[MAX_CHIP_IDS];
31714b24e2bSVaishali Kulkarni };
31814b24e2bSVaishali Kulkarni 
31914b24e2bSVaishali Kulkarni struct vfc_ram_defs {
32014b24e2bSVaishali Kulkarni 	const char *mem_name;
32114b24e2bSVaishali Kulkarni 	const char *type_name;
32214b24e2bSVaishali Kulkarni 	u32 base_row;
32314b24e2bSVaishali Kulkarni 	u32 num_rows;
32414b24e2bSVaishali Kulkarni };
32514b24e2bSVaishali Kulkarni 
32614b24e2bSVaishali Kulkarni struct big_ram_defs {
32714b24e2bSVaishali Kulkarni 	const char *instance_name;
32814b24e2bSVaishali Kulkarni 	enum mem_groups mem_group_id;
32914b24e2bSVaishali Kulkarni 	enum mem_groups ram_mem_group_id;
33014b24e2bSVaishali Kulkarni 	enum dbg_grc_params grc_param;
33114b24e2bSVaishali Kulkarni 	u32 addr_reg_addr;
33214b24e2bSVaishali Kulkarni 	u32 data_reg_addr;
33314b24e2bSVaishali Kulkarni 	u32 num_of_blocks[MAX_CHIP_IDS];
33414b24e2bSVaishali Kulkarni };
33514b24e2bSVaishali Kulkarni 
33614b24e2bSVaishali Kulkarni struct phy_defs {
33714b24e2bSVaishali Kulkarni 	const char *phy_name;
33814b24e2bSVaishali Kulkarni 
33914b24e2bSVaishali Kulkarni 	/* PHY base GRC address */
34014b24e2bSVaishali Kulkarni 	u32 base_addr;
34114b24e2bSVaishali Kulkarni 
34214b24e2bSVaishali Kulkarni 	/* Relative address of indirect TBUS address register (bits 0..7) */
34314b24e2bSVaishali Kulkarni 	u32 tbus_addr_lo_addr;
34414b24e2bSVaishali Kulkarni 
34514b24e2bSVaishali Kulkarni 	/* Relative address of indirect TBUS address register (bits 8..10) */
34614b24e2bSVaishali Kulkarni 	u32 tbus_addr_hi_addr;
34714b24e2bSVaishali Kulkarni 
34814b24e2bSVaishali Kulkarni 	/* Relative address of indirect TBUS data register (bits 0..7) */
34914b24e2bSVaishali Kulkarni 	u32 tbus_data_lo_addr;
35014b24e2bSVaishali Kulkarni 
35114b24e2bSVaishali Kulkarni 	/* Relative address of indirect TBUS data register (bits 8..11) */
35214b24e2bSVaishali Kulkarni 	u32 tbus_data_hi_addr;
35314b24e2bSVaishali Kulkarni };
35414b24e2bSVaishali Kulkarni 
35514b24e2bSVaishali Kulkarni /******************************** Constants **********************************/
35614b24e2bSVaishali Kulkarni 
35714b24e2bSVaishali Kulkarni #define MAX_LCIDS			320
35814b24e2bSVaishali Kulkarni #define MAX_LTIDS			320
35914b24e2bSVaishali Kulkarni 
36014b24e2bSVaishali Kulkarni #define NUM_IOR_SETS			2
36114b24e2bSVaishali Kulkarni #define IORS_PER_SET			176
36214b24e2bSVaishali Kulkarni #define IOR_SET_OFFSET(set_id)		((set_id) * 256)
36314b24e2bSVaishali Kulkarni 
36414b24e2bSVaishali Kulkarni #define BYTES_IN_DWORD			sizeof(u32)
36514b24e2bSVaishali Kulkarni 
36614b24e2bSVaishali Kulkarni /* Cyclic  right */
36714b24e2bSVaishali Kulkarni #define SHR(val, val_width, amount)	(((val) | ((val) << (val_width))) 					>> (amount)) & ((1 << (val_width)) - 1)
36814b24e2bSVaishali Kulkarni 
36914b24e2bSVaishali Kulkarni /* In the macros below, size and offset are specified in bits */
37014b24e2bSVaishali Kulkarni #define CEIL_DWORDS(size)		DIV_ROUND_UP(size, 32)
37114b24e2bSVaishali Kulkarni #define FIELD_BIT_OFFSET(type, field)	type##_##field##_##OFFSET
37214b24e2bSVaishali Kulkarni #define FIELD_BIT_SIZE(type, field)	type##_##field##_##SIZE
37314b24e2bSVaishali Kulkarni #define FIELD_DWORD_OFFSET(type, field)		(int)(FIELD_BIT_OFFSET(type, field) / 32)
37414b24e2bSVaishali Kulkarni #define FIELD_DWORD_SHIFT(type, field)	(FIELD_BIT_OFFSET(type, field) % 32)
37514b24e2bSVaishali Kulkarni #define FIELD_BIT_MASK(type, field)		(((1 << FIELD_BIT_SIZE(type, field)) - 1) 	<< FIELD_DWORD_SHIFT(type, field))
37614b24e2bSVaishali Kulkarni 
37714b24e2bSVaishali Kulkarni #define SET_VAR_FIELD(var, type, field, val) 	var[FIELD_DWORD_OFFSET(type, field)] &= 		(~FIELD_BIT_MASK(type, field)); 	var[FIELD_DWORD_OFFSET(type, field)] |= 		(val) << FIELD_DWORD_SHIFT(type, field)
37814b24e2bSVaishali Kulkarni 
37914b24e2bSVaishali Kulkarni #define ARR_REG_WR(dev, ptt, addr, arr, arr_size) 	for (i = 0; i < (arr_size); i++) 		ecore_wr(dev, ptt, addr, (arr)[i])
38014b24e2bSVaishali Kulkarni 
38114b24e2bSVaishali Kulkarni #define ARR_REG_RD(dev, ptt, addr, arr, arr_size) 	for (i = 0; i < (arr_size); i++) 		(arr)[i] = ecore_rd(dev, ptt, addr)
38214b24e2bSVaishali Kulkarni 
38314b24e2bSVaishali Kulkarni #define CHECK_ARR_SIZE(arr, size) 	OSAL_BUILD_BUG_ON(!(OSAL_ARRAY_SIZE(arr) == size))
38414b24e2bSVaishali Kulkarni 
38514b24e2bSVaishali Kulkarni #ifndef DWORDS_TO_BYTES
38614b24e2bSVaishali Kulkarni #define DWORDS_TO_BYTES(dwords)		((dwords) * BYTES_IN_DWORD)
38714b24e2bSVaishali Kulkarni #endif
38814b24e2bSVaishali Kulkarni #ifndef BYTES_TO_DWORDS
38914b24e2bSVaishali Kulkarni #define BYTES_TO_DWORDS(bytes)		((bytes) / BYTES_IN_DWORD)
39014b24e2bSVaishali Kulkarni #endif
39114b24e2bSVaishali Kulkarni 
39214b24e2bSVaishali Kulkarni /* extra lines include a signature line + optional latency events line */
39314b24e2bSVaishali Kulkarni #ifndef NUM_DBG_LINES
39414b24e2bSVaishali Kulkarni #define NUM_EXTRA_DBG_LINES(block_desc)		(1 + (block_desc->has_latency_events ? 1 : 0))
39514b24e2bSVaishali Kulkarni #define NUM_DBG_LINES(block_desc)		(block_desc->num_of_lines + NUM_EXTRA_DBG_LINES(block_desc))
39614b24e2bSVaishali Kulkarni #endif
39714b24e2bSVaishali Kulkarni 
39814b24e2bSVaishali Kulkarni #define RAM_LINES_TO_DWORDS(lines)	((lines) * 2)
39914b24e2bSVaishali Kulkarni #define RAM_LINES_TO_BYTES(lines)		DWORDS_TO_BYTES(RAM_LINES_TO_DWORDS(lines))
40014b24e2bSVaishali Kulkarni 
40114b24e2bSVaishali Kulkarni #define REG_DUMP_LEN_SHIFT		24
40214b24e2bSVaishali Kulkarni #define MEM_DUMP_ENTRY_SIZE_DWORDS		BYTES_TO_DWORDS(sizeof(struct dbg_dump_mem))
40314b24e2bSVaishali Kulkarni 
40414b24e2bSVaishali Kulkarni #define IDLE_CHK_RULE_SIZE_DWORDS		BYTES_TO_DWORDS(sizeof(struct dbg_idle_chk_rule))
40514b24e2bSVaishali Kulkarni 
40614b24e2bSVaishali Kulkarni #define IDLE_CHK_RESULT_HDR_DWORDS		BYTES_TO_DWORDS(sizeof(struct dbg_idle_chk_result_hdr))
40714b24e2bSVaishali Kulkarni 
40814b24e2bSVaishali Kulkarni #define IDLE_CHK_RESULT_REG_HDR_DWORDS		BYTES_TO_DWORDS(sizeof(struct dbg_idle_chk_result_reg_hdr))
40914b24e2bSVaishali Kulkarni 
41014b24e2bSVaishali Kulkarni #define IDLE_CHK_MAX_ENTRIES_SIZE	32
41114b24e2bSVaishali Kulkarni 
41214b24e2bSVaishali Kulkarni /* The sizes and offsets below are specified in bits */
41314b24e2bSVaishali Kulkarni #define VFC_CAM_CMD_STRUCT_SIZE		64
41414b24e2bSVaishali Kulkarni #define VFC_CAM_CMD_ROW_OFFSET		48
41514b24e2bSVaishali Kulkarni #define VFC_CAM_CMD_ROW_SIZE		9
41614b24e2bSVaishali Kulkarni #define VFC_CAM_ADDR_STRUCT_SIZE	16
41714b24e2bSVaishali Kulkarni #define VFC_CAM_ADDR_OP_OFFSET		0
41814b24e2bSVaishali Kulkarni #define VFC_CAM_ADDR_OP_SIZE		4
41914b24e2bSVaishali Kulkarni #define VFC_CAM_RESP_STRUCT_SIZE	256
42014b24e2bSVaishali Kulkarni #define VFC_RAM_ADDR_STRUCT_SIZE	16
42114b24e2bSVaishali Kulkarni #define VFC_RAM_ADDR_OP_OFFSET		0
42214b24e2bSVaishali Kulkarni #define VFC_RAM_ADDR_OP_SIZE		2
42314b24e2bSVaishali Kulkarni #define VFC_RAM_ADDR_ROW_OFFSET		2
42414b24e2bSVaishali Kulkarni #define VFC_RAM_ADDR_ROW_SIZE		10
42514b24e2bSVaishali Kulkarni #define VFC_RAM_RESP_STRUCT_SIZE	256
42614b24e2bSVaishali Kulkarni 
42714b24e2bSVaishali Kulkarni #define VFC_CAM_CMD_DWORDS		CEIL_DWORDS(VFC_CAM_CMD_STRUCT_SIZE)
42814b24e2bSVaishali Kulkarni #define VFC_CAM_ADDR_DWORDS		CEIL_DWORDS(VFC_CAM_ADDR_STRUCT_SIZE)
42914b24e2bSVaishali Kulkarni #define VFC_CAM_RESP_DWORDS		CEIL_DWORDS(VFC_CAM_RESP_STRUCT_SIZE)
43014b24e2bSVaishali Kulkarni #define VFC_RAM_CMD_DWORDS		VFC_CAM_CMD_DWORDS
43114b24e2bSVaishali Kulkarni #define VFC_RAM_ADDR_DWORDS		CEIL_DWORDS(VFC_RAM_ADDR_STRUCT_SIZE)
43214b24e2bSVaishali Kulkarni #define VFC_RAM_RESP_DWORDS		CEIL_DWORDS(VFC_RAM_RESP_STRUCT_SIZE)
43314b24e2bSVaishali Kulkarni 
43414b24e2bSVaishali Kulkarni #define NUM_VFC_RAM_TYPES		4
43514b24e2bSVaishali Kulkarni 
43614b24e2bSVaishali Kulkarni #define VFC_CAM_NUM_ROWS		512
43714b24e2bSVaishali Kulkarni 
43814b24e2bSVaishali Kulkarni #define VFC_OPCODE_CAM_RD		14
43914b24e2bSVaishali Kulkarni #define VFC_OPCODE_RAM_RD		0
44014b24e2bSVaishali Kulkarni 
44114b24e2bSVaishali Kulkarni #define NUM_RSS_MEM_TYPES		5
44214b24e2bSVaishali Kulkarni 
44314b24e2bSVaishali Kulkarni #define NUM_BIG_RAM_TYPES		3
44414b24e2bSVaishali Kulkarni #define BIG_RAM_BLOCK_SIZE_BYTES	128
44514b24e2bSVaishali Kulkarni #define BIG_RAM_BLOCK_SIZE_DWORDS		BYTES_TO_DWORDS(BIG_RAM_BLOCK_SIZE_BYTES)
44614b24e2bSVaishali Kulkarni 
44714b24e2bSVaishali Kulkarni #define NUM_PHY_TBUS_ADDRESSES		2048
44814b24e2bSVaishali Kulkarni #define PHY_DUMP_SIZE_DWORDS		(NUM_PHY_TBUS_ADDRESSES / 2)
44914b24e2bSVaishali Kulkarni 
45014b24e2bSVaishali Kulkarni #define SEM_FAST_MODE6_SRC_ENABLE	0x10
45114b24e2bSVaishali Kulkarni #define SEM_FAST_MODE6_SRC_DISABLE	0x3f
45214b24e2bSVaishali Kulkarni 
45314b24e2bSVaishali Kulkarni #define SEM_SLOW_MODE1_DATA_ENABLE	0x1
45414b24e2bSVaishali Kulkarni 
45514b24e2bSVaishali Kulkarni #define VALUES_PER_CYCLE		4
45614b24e2bSVaishali Kulkarni #define MAX_CYCLE_VALUES_MASK		((1 << VALUES_PER_CYCLE) - 1)
45714b24e2bSVaishali Kulkarni 
45814b24e2bSVaishali Kulkarni #define MAX_DWORDS_PER_CYCLE		8
45914b24e2bSVaishali Kulkarni 
46014b24e2bSVaishali Kulkarni #define HW_ID_BITS			3
46114b24e2bSVaishali Kulkarni 
46214b24e2bSVaishali Kulkarni #define NUM_CALENDAR_SLOTS		16
46314b24e2bSVaishali Kulkarni 
46414b24e2bSVaishali Kulkarni #define MAX_TRIGGER_STATES		3
46514b24e2bSVaishali Kulkarni #define TRIGGER_SETS_PER_STATE		2
46614b24e2bSVaishali Kulkarni #define MAX_CONSTRAINTS			4
46714b24e2bSVaishali Kulkarni 
46814b24e2bSVaishali Kulkarni #define SEM_FILTER_CID_EN_MASK		0x008
46914b24e2bSVaishali Kulkarni #define SEM_FILTER_EID_MASK_EN_MASK	0x010
47014b24e2bSVaishali Kulkarni #define SEM_FILTER_EID_RANGE_EN_MASK	0x110
47114b24e2bSVaishali Kulkarni 
47214b24e2bSVaishali Kulkarni #define CHUNK_SIZE_IN_DWORDS		64
47314b24e2bSVaishali Kulkarni #define CHUNK_SIZE_IN_BYTES		DWORDS_TO_BYTES(CHUNK_SIZE_IN_DWORDS)
47414b24e2bSVaishali Kulkarni 
47514b24e2bSVaishali Kulkarni #define INT_BUF_NUM_OF_LINES		192
47614b24e2bSVaishali Kulkarni #define INT_BUF_LINE_SIZE_IN_DWORDS	16
47714b24e2bSVaishali Kulkarni #define INT_BUF_SIZE_IN_DWORDS			(INT_BUF_NUM_OF_LINES * INT_BUF_LINE_SIZE_IN_DWORDS)
47814b24e2bSVaishali Kulkarni #define INT_BUF_SIZE_IN_CHUNKS			(INT_BUF_SIZE_IN_DWORDS / CHUNK_SIZE_IN_DWORDS)
47914b24e2bSVaishali Kulkarni 
48014b24e2bSVaishali Kulkarni #define PCI_BUF_LINE_SIZE_IN_DWORDS	8
48114b24e2bSVaishali Kulkarni #define PCI_BUF_LINE_SIZE_IN_BYTES		DWORDS_TO_BYTES(PCI_BUF_LINE_SIZE_IN_DWORDS)
48214b24e2bSVaishali Kulkarni 
48314b24e2bSVaishali Kulkarni #define TARGET_EN_MASK_PCI		0x3
48414b24e2bSVaishali Kulkarni #define TARGET_EN_MASK_NIG		0x4
48514b24e2bSVaishali Kulkarni 
48614b24e2bSVaishali Kulkarni #define PCI_REQ_CREDIT			1
48714b24e2bSVaishali Kulkarni #define PCI_PHYS_ADDR_TYPE		0
48814b24e2bSVaishali Kulkarni 
48914b24e2bSVaishali Kulkarni #define OPAQUE_FID(pci_func)		((pci_func << 4) | 0xff00)
49014b24e2bSVaishali Kulkarni 
49114b24e2bSVaishali Kulkarni #define RESET_REG_UNRESET_OFFSET	4
49214b24e2bSVaishali Kulkarni 
49314b24e2bSVaishali Kulkarni #define PCI_PKT_SIZE_IN_CHUNKS		1
49414b24e2bSVaishali Kulkarni #define PCI_PKT_SIZE_IN_BYTES			(PCI_PKT_SIZE_IN_CHUNKS * CHUNK_SIZE_IN_BYTES)
49514b24e2bSVaishali Kulkarni 
49614b24e2bSVaishali Kulkarni #define NIG_PKT_SIZE_IN_CHUNKS		4
49714b24e2bSVaishali Kulkarni 
49814b24e2bSVaishali Kulkarni #define FLUSH_DELAY_MS			500
49914b24e2bSVaishali Kulkarni #define STALL_DELAY_MS			500
50014b24e2bSVaishali Kulkarni 
50114b24e2bSVaishali Kulkarni #define SRC_MAC_ADDR_LO16		0x0a0b
50214b24e2bSVaishali Kulkarni #define SRC_MAC_ADDR_HI32		0x0c0d0e0f
50314b24e2bSVaishali Kulkarni #define ETH_TYPE			0x1000
50414b24e2bSVaishali Kulkarni 
50514b24e2bSVaishali Kulkarni #define STATIC_DEBUG_LINE_DWORDS	9
50614b24e2bSVaishali Kulkarni 
50714b24e2bSVaishali Kulkarni #define NUM_COMMON_GLOBAL_PARAMS	8
50814b24e2bSVaishali Kulkarni 
50914b24e2bSVaishali Kulkarni #define FW_IMG_KUKU			0
51014b24e2bSVaishali Kulkarni #define FW_IMG_MAIN			1
51114b24e2bSVaishali Kulkarni #define FW_IMG_L2B			2
51214b24e2bSVaishali Kulkarni 
51314b24e2bSVaishali Kulkarni #ifndef REG_FIFO_ELEMENT_DWORDS
51414b24e2bSVaishali Kulkarni #define REG_FIFO_ELEMENT_DWORDS		2
51514b24e2bSVaishali Kulkarni #endif
51614b24e2bSVaishali Kulkarni #define REG_FIFO_DEPTH_ELEMENTS		32
51714b24e2bSVaishali Kulkarni #define REG_FIFO_DEPTH_DWORDS			(REG_FIFO_ELEMENT_DWORDS * REG_FIFO_DEPTH_ELEMENTS)
51814b24e2bSVaishali Kulkarni 
51914b24e2bSVaishali Kulkarni #ifndef IGU_FIFO_ELEMENT_DWORDS
52014b24e2bSVaishali Kulkarni #define IGU_FIFO_ELEMENT_DWORDS		4
52114b24e2bSVaishali Kulkarni #endif
52214b24e2bSVaishali Kulkarni #define IGU_FIFO_DEPTH_ELEMENTS		64
52314b24e2bSVaishali Kulkarni #define IGU_FIFO_DEPTH_DWORDS			(IGU_FIFO_ELEMENT_DWORDS * IGU_FIFO_DEPTH_ELEMENTS)
52414b24e2bSVaishali Kulkarni 
52514b24e2bSVaishali Kulkarni #define SEMI_SYNC_FIFO_POLLING_DELAY_MS	5
52614b24e2bSVaishali Kulkarni #define SEMI_SYNC_FIFO_POLLING_COUNT	20
52714b24e2bSVaishali Kulkarni 
52814b24e2bSVaishali Kulkarni #ifndef PROTECTION_OVERRIDE_ELEMENT_DWORDS
52914b24e2bSVaishali Kulkarni #define PROTECTION_OVERRIDE_ELEMENT_DWORDS 2
53014b24e2bSVaishali Kulkarni #endif
53114b24e2bSVaishali Kulkarni #define PROTECTION_OVERRIDE_DEPTH_ELEMENTS 20
53214b24e2bSVaishali Kulkarni #define PROTECTION_OVERRIDE_DEPTH_DWORDS   	(PROTECTION_OVERRIDE_DEPTH_ELEMENTS 	* PROTECTION_OVERRIDE_ELEMENT_DWORDS)
53314b24e2bSVaishali Kulkarni 
534*04443fdeSToomas Soome #define MCP_SPAD_TRACE_OFFSIZE_ADDR		(MCP_REG_SCRATCH + 	offsetof(struct static_init, sections[SPAD_SECTION_TRACE]))
53514b24e2bSVaishali Kulkarni 
53614b24e2bSVaishali Kulkarni #define EMPTY_FW_VERSION_STR		"???_???_???_???"
53714b24e2bSVaishali Kulkarni #define EMPTY_FW_IMAGE_STR		"???????????????"
53814b24e2bSVaishali Kulkarni 
53914b24e2bSVaishali Kulkarni 
54014b24e2bSVaishali Kulkarni /***************************** Constant Arrays *******************************/
54114b24e2bSVaishali Kulkarni 
54214b24e2bSVaishali Kulkarni struct dbg_array {
54314b24e2bSVaishali Kulkarni 	const u32 *ptr;
54414b24e2bSVaishali Kulkarni 	u32 size_in_dwords;
54514b24e2bSVaishali Kulkarni };
54614b24e2bSVaishali Kulkarni 
54714b24e2bSVaishali Kulkarni /* Debug arrays */
54814b24e2bSVaishali Kulkarni #ifdef USE_DBG_BIN_FILE
54914b24e2bSVaishali Kulkarni static struct dbg_array s_dbg_arrays[MAX_BIN_DBG_BUFFER_TYPE] = { { OSAL_NULL } };
55014b24e2bSVaishali Kulkarni #else
55114b24e2bSVaishali Kulkarni static struct dbg_array s_dbg_arrays[MAX_BIN_DBG_BUFFER_TYPE] = {
55214b24e2bSVaishali Kulkarni 
55314b24e2bSVaishali Kulkarni 	/* BIN_BUF_DBG_MODE_TREE */
55414b24e2bSVaishali Kulkarni 	{ (u32*)dbg_modes_tree_buf, OSAL_ARRAY_SIZE(dbg_modes_tree_buf)},
55514b24e2bSVaishali Kulkarni 
55614b24e2bSVaishali Kulkarni 	/* BIN_BUF_DBG_DUMP_REG */
55714b24e2bSVaishali Kulkarni 	{ dump_reg, OSAL_ARRAY_SIZE(dump_reg) },
55814b24e2bSVaishali Kulkarni 
55914b24e2bSVaishali Kulkarni 	/* BIN_BUF_DBG_DUMP_MEM */
56014b24e2bSVaishali Kulkarni 	{ dump_mem, OSAL_ARRAY_SIZE(dump_mem) },
56114b24e2bSVaishali Kulkarni 
56214b24e2bSVaishali Kulkarni 	/* BIN_BUF_DBG_IDLE_CHK_REGS */
56314b24e2bSVaishali Kulkarni 	{ idle_chk_regs, OSAL_ARRAY_SIZE(idle_chk_regs) },
56414b24e2bSVaishali Kulkarni 
56514b24e2bSVaishali Kulkarni 	/* BIN_BUF_DBG_IDLE_CHK_IMMS */
56614b24e2bSVaishali Kulkarni 	{ idle_chk_imms, OSAL_ARRAY_SIZE(idle_chk_imms) },
56714b24e2bSVaishali Kulkarni 
56814b24e2bSVaishali Kulkarni 	/* BIN_BUF_DBG_IDLE_CHK_RULES */
56914b24e2bSVaishali Kulkarni 	{ idle_chk_rules, OSAL_ARRAY_SIZE(idle_chk_rules) },
57014b24e2bSVaishali Kulkarni 
57114b24e2bSVaishali Kulkarni 	/* BIN_BUF_DBG_IDLE_CHK_PARSING_DATA */
57214b24e2bSVaishali Kulkarni 	{ OSAL_NULL, 0 },
57314b24e2bSVaishali Kulkarni 
57414b24e2bSVaishali Kulkarni 	/* BIN_BUF_DBG_ATTN_BLOCKS */
57514b24e2bSVaishali Kulkarni 	{ attn_block, OSAL_ARRAY_SIZE(attn_block) },
57614b24e2bSVaishali Kulkarni 
57714b24e2bSVaishali Kulkarni 	/* BIN_BUF_DBG_ATTN_REGSS */
57814b24e2bSVaishali Kulkarni 	{ attn_reg, OSAL_ARRAY_SIZE(attn_reg) },
57914b24e2bSVaishali Kulkarni 
58014b24e2bSVaishali Kulkarni 	/* BIN_BUF_DBG_ATTN_INDEXES */
58114b24e2bSVaishali Kulkarni 	{ OSAL_NULL, 0 },
58214b24e2bSVaishali Kulkarni 
58314b24e2bSVaishali Kulkarni 	/* BIN_BUF_DBG_ATTN_NAME_OFFSETS */
58414b24e2bSVaishali Kulkarni 	{ OSAL_NULL, 0 },
58514b24e2bSVaishali Kulkarni 
58614b24e2bSVaishali Kulkarni 	/* BIN_BUF_DBG_BUS_BLOCKS */
58714b24e2bSVaishali Kulkarni 	{ dbg_bus_blocks, OSAL_ARRAY_SIZE(dbg_bus_blocks) },
58814b24e2bSVaishali Kulkarni 
58914b24e2bSVaishali Kulkarni 	/* BIN_BUF_DBG_BUS_LINES */
59014b24e2bSVaishali Kulkarni 	{ dbg_bus_lines, OSAL_ARRAY_SIZE(dbg_bus_lines) },
59114b24e2bSVaishali Kulkarni 
59214b24e2bSVaishali Kulkarni 	/* BIN_BUF_DBG_BUS_BLOCKS_USER_DATA */
59314b24e2bSVaishali Kulkarni 	{ OSAL_NULL, 0 },
59414b24e2bSVaishali Kulkarni 
59514b24e2bSVaishali Kulkarni 	/* BIN_BUF_DBG_BUS_LINE_NAME_OFFSETS */
59614b24e2bSVaishali Kulkarni 	{ OSAL_NULL, 0 },
59714b24e2bSVaishali Kulkarni 
59814b24e2bSVaishali Kulkarni 	/* BIN_BUF_DBG_PARSING_STRINGS */
59914b24e2bSVaishali Kulkarni 	{ OSAL_NULL, 0 }
60014b24e2bSVaishali Kulkarni };
60114b24e2bSVaishali Kulkarni #endif
60214b24e2bSVaishali Kulkarni 
60314b24e2bSVaishali Kulkarni /* Chip constant definitions array */
60414b24e2bSVaishali Kulkarni static struct chip_defs s_chip_defs[MAX_CHIP_IDS] = {
60514b24e2bSVaishali Kulkarni 	{ "bb",
60614b24e2bSVaishali Kulkarni 
60714b24e2bSVaishali Kulkarni 		/* ASIC */
60814b24e2bSVaishali Kulkarni 		{ { MAX_NUM_PORTS_BB, MAX_NUM_PFS_BB, MAX_NUM_VFS_BB },
60914b24e2bSVaishali Kulkarni 
61014b24e2bSVaishali Kulkarni 		/* EMUL_FULL */
61114b24e2bSVaishali Kulkarni 		{ MAX_NUM_PORTS_BB, MAX_NUM_PFS_BB, MAX_NUM_VFS_BB },
61214b24e2bSVaishali Kulkarni 
61314b24e2bSVaishali Kulkarni 		/* EMUL_REDUCED */
61414b24e2bSVaishali Kulkarni 		{ MAX_NUM_PORTS_BB, MAX_NUM_PFS_BB, MAX_NUM_VFS_BB },
61514b24e2bSVaishali Kulkarni 
61614b24e2bSVaishali Kulkarni 		/* FPGA */
61714b24e2bSVaishali Kulkarni 		{ MAX_NUM_PORTS_BB, MAX_NUM_PFS_BB, MAX_NUM_VFS_BB } } },
61814b24e2bSVaishali Kulkarni 
61914b24e2bSVaishali Kulkarni 	{ "ah",
62014b24e2bSVaishali Kulkarni 
62114b24e2bSVaishali Kulkarni 		/* ASIC */
62214b24e2bSVaishali Kulkarni 		{ { MAX_NUM_PORTS_K2, MAX_NUM_PFS_K2, MAX_NUM_VFS_K2 },
62314b24e2bSVaishali Kulkarni 
62414b24e2bSVaishali Kulkarni 		/* EMUL_FULL */
62514b24e2bSVaishali Kulkarni 		{ MAX_NUM_PORTS_K2, MAX_NUM_PFS_K2, MAX_NUM_VFS_K2 },
62614b24e2bSVaishali Kulkarni 
62714b24e2bSVaishali Kulkarni 		/* EMUL_REDUCED */
62814b24e2bSVaishali Kulkarni 		{ MAX_NUM_PORTS_K2, MAX_NUM_PFS_K2, MAX_NUM_VFS_K2 },
62914b24e2bSVaishali Kulkarni 
63014b24e2bSVaishali Kulkarni 		/* FPGA */
63114b24e2bSVaishali Kulkarni 		{ MAX_NUM_PORTS_K2, 8, MAX_NUM_VFS_K2 } } }
63214b24e2bSVaishali Kulkarni };
63314b24e2bSVaishali Kulkarni 
63414b24e2bSVaishali Kulkarni /* Storm constant definitions array */
63514b24e2bSVaishali Kulkarni static struct storm_defs s_storm_defs[] = {
63614b24e2bSVaishali Kulkarni 
63714b24e2bSVaishali Kulkarni 	/* Tstorm */
63814b24e2bSVaishali Kulkarni 	{	'T', BLOCK_TSEM,
63914b24e2bSVaishali Kulkarni 		{ DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT }, true,
64014b24e2bSVaishali Kulkarni 		TSEM_REG_FAST_MEMORY,
64114b24e2bSVaishali Kulkarni 		TSEM_REG_DBG_FRAME_MODE_BB_K2, TSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
64214b24e2bSVaishali Kulkarni 		TSEM_REG_SLOW_DBG_MODE_BB_K2, TSEM_REG_DBG_MODE1_CFG_BB_K2,
64314b24e2bSVaishali Kulkarni 		TSEM_REG_SYNC_DBG_EMPTY, TSEM_REG_SLOW_DBG_EMPTY_BB_K2,
64414b24e2bSVaishali Kulkarni 		TCM_REG_CTX_RBC_ACCS,
64514b24e2bSVaishali Kulkarni 		4, TCM_REG_AGG_CON_CTX,
64614b24e2bSVaishali Kulkarni 		16, TCM_REG_SM_CON_CTX,
64714b24e2bSVaishali Kulkarni 		2, TCM_REG_AGG_TASK_CTX,
64814b24e2bSVaishali Kulkarni 		4, TCM_REG_SM_TASK_CTX },
64914b24e2bSVaishali Kulkarni 
65014b24e2bSVaishali Kulkarni 	/* Mstorm */
65114b24e2bSVaishali Kulkarni 	{	'M', BLOCK_MSEM,
65214b24e2bSVaishali Kulkarni 		{ DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM }, false,
65314b24e2bSVaishali Kulkarni 		MSEM_REG_FAST_MEMORY,
65414b24e2bSVaishali Kulkarni 		MSEM_REG_DBG_FRAME_MODE_BB_K2, MSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
65514b24e2bSVaishali Kulkarni 		MSEM_REG_SLOW_DBG_MODE_BB_K2, MSEM_REG_DBG_MODE1_CFG_BB_K2,
65614b24e2bSVaishali Kulkarni 		MSEM_REG_SYNC_DBG_EMPTY, MSEM_REG_SLOW_DBG_EMPTY_BB_K2,
65714b24e2bSVaishali Kulkarni 		MCM_REG_CTX_RBC_ACCS,
65814b24e2bSVaishali Kulkarni 		1, MCM_REG_AGG_CON_CTX,
65914b24e2bSVaishali Kulkarni 		10, MCM_REG_SM_CON_CTX,
66014b24e2bSVaishali Kulkarni 		2, MCM_REG_AGG_TASK_CTX,
66114b24e2bSVaishali Kulkarni 		7, MCM_REG_SM_TASK_CTX },
66214b24e2bSVaishali Kulkarni 
66314b24e2bSVaishali Kulkarni 	/* Ustorm */
66414b24e2bSVaishali Kulkarni 	{	'U', BLOCK_USEM,
66514b24e2bSVaishali Kulkarni 		{ DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU }, false,
66614b24e2bSVaishali Kulkarni 		USEM_REG_FAST_MEMORY,
66714b24e2bSVaishali Kulkarni 		USEM_REG_DBG_FRAME_MODE_BB_K2, USEM_REG_SLOW_DBG_ACTIVE_BB_K2,
66814b24e2bSVaishali Kulkarni 		USEM_REG_SLOW_DBG_MODE_BB_K2, USEM_REG_DBG_MODE1_CFG_BB_K2,
66914b24e2bSVaishali Kulkarni 		USEM_REG_SYNC_DBG_EMPTY, USEM_REG_SLOW_DBG_EMPTY_BB_K2,
67014b24e2bSVaishali Kulkarni 		UCM_REG_CTX_RBC_ACCS,
67114b24e2bSVaishali Kulkarni 		2, UCM_REG_AGG_CON_CTX,
67214b24e2bSVaishali Kulkarni 		13, UCM_REG_SM_CON_CTX,
67314b24e2bSVaishali Kulkarni 		3, UCM_REG_AGG_TASK_CTX,
67414b24e2bSVaishali Kulkarni 		3, UCM_REG_SM_TASK_CTX },
67514b24e2bSVaishali Kulkarni 
67614b24e2bSVaishali Kulkarni 	/* Xstorm */
67714b24e2bSVaishali Kulkarni 	{	'X', BLOCK_XSEM,
67814b24e2bSVaishali Kulkarni 		{ DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX }, false,
67914b24e2bSVaishali Kulkarni 		XSEM_REG_FAST_MEMORY,
68014b24e2bSVaishali Kulkarni 		XSEM_REG_DBG_FRAME_MODE_BB_K2, XSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
68114b24e2bSVaishali Kulkarni 		XSEM_REG_SLOW_DBG_MODE_BB_K2, XSEM_REG_DBG_MODE1_CFG_BB_K2,
68214b24e2bSVaishali Kulkarni 		XSEM_REG_SYNC_DBG_EMPTY, XSEM_REG_SLOW_DBG_EMPTY_BB_K2,
68314b24e2bSVaishali Kulkarni 		XCM_REG_CTX_RBC_ACCS,
68414b24e2bSVaishali Kulkarni 		9, XCM_REG_AGG_CON_CTX,
68514b24e2bSVaishali Kulkarni 		15, XCM_REG_SM_CON_CTX,
68614b24e2bSVaishali Kulkarni 		0, 0,
68714b24e2bSVaishali Kulkarni 		0, 0 },
68814b24e2bSVaishali Kulkarni 
68914b24e2bSVaishali Kulkarni 	/* Ystorm */
69014b24e2bSVaishali Kulkarni 	{	'Y', BLOCK_YSEM,
69114b24e2bSVaishali Kulkarni 		{ DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY }, false,
69214b24e2bSVaishali Kulkarni 		YSEM_REG_FAST_MEMORY,
69314b24e2bSVaishali Kulkarni 		YSEM_REG_DBG_FRAME_MODE_BB_K2, YSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
69414b24e2bSVaishali Kulkarni 		YSEM_REG_SLOW_DBG_MODE_BB_K2, YSEM_REG_DBG_MODE1_CFG_BB_K2,
69514b24e2bSVaishali Kulkarni 		YSEM_REG_SYNC_DBG_EMPTY, TSEM_REG_SLOW_DBG_EMPTY_BB_K2,
69614b24e2bSVaishali Kulkarni 		YCM_REG_CTX_RBC_ACCS,
69714b24e2bSVaishali Kulkarni 		2, YCM_REG_AGG_CON_CTX,
69814b24e2bSVaishali Kulkarni 		3, YCM_REG_SM_CON_CTX,
69914b24e2bSVaishali Kulkarni 		2, YCM_REG_AGG_TASK_CTX,
70014b24e2bSVaishali Kulkarni 		12, YCM_REG_SM_TASK_CTX },
70114b24e2bSVaishali Kulkarni 
70214b24e2bSVaishali Kulkarni 	/* Pstorm */
70314b24e2bSVaishali Kulkarni 	{	'P', BLOCK_PSEM,
70414b24e2bSVaishali Kulkarni 		{ DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS }, true,
70514b24e2bSVaishali Kulkarni 		PSEM_REG_FAST_MEMORY,
70614b24e2bSVaishali Kulkarni 		PSEM_REG_DBG_FRAME_MODE_BB_K2, PSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
70714b24e2bSVaishali Kulkarni 		PSEM_REG_SLOW_DBG_MODE_BB_K2, PSEM_REG_DBG_MODE1_CFG_BB_K2,
70814b24e2bSVaishali Kulkarni 		PSEM_REG_SYNC_DBG_EMPTY, PSEM_REG_SLOW_DBG_EMPTY_BB_K2,
70914b24e2bSVaishali Kulkarni 		PCM_REG_CTX_RBC_ACCS,
71014b24e2bSVaishali Kulkarni 		0, 0,
71114b24e2bSVaishali Kulkarni 		10, PCM_REG_SM_CON_CTX,
71214b24e2bSVaishali Kulkarni 		0, 0,
71314b24e2bSVaishali Kulkarni 		0, 0 }
71414b24e2bSVaishali Kulkarni };
71514b24e2bSVaishali Kulkarni 
71614b24e2bSVaishali Kulkarni /* Block definitions array */
71714b24e2bSVaishali Kulkarni 
71814b24e2bSVaishali Kulkarni static struct block_defs block_grc_defs = {
71914b24e2bSVaishali Kulkarni 	"grc", { true, true }, false, 0,
72014b24e2bSVaishali Kulkarni 	{ DBG_BUS_CLIENT_RBCN, DBG_BUS_CLIENT_RBCN },
72114b24e2bSVaishali Kulkarni 	GRC_REG_DBG_SELECT, GRC_REG_DBG_DWORD_ENABLE,
72214b24e2bSVaishali Kulkarni 	GRC_REG_DBG_SHIFT, GRC_REG_DBG_FORCE_VALID,
72314b24e2bSVaishali Kulkarni 	GRC_REG_DBG_FORCE_FRAME,
72414b24e2bSVaishali Kulkarni 	true, false, DBG_RESET_REG_MISC_PL_UA, 1 };
72514b24e2bSVaishali Kulkarni 
72614b24e2bSVaishali Kulkarni static struct block_defs block_miscs_defs = {
72714b24e2bSVaishali Kulkarni 	"miscs", { false, false }, false, 0,
72814b24e2bSVaishali Kulkarni 	{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
72914b24e2bSVaishali Kulkarni 	0, 0, 0, 0, 0,
73014b24e2bSVaishali Kulkarni 	false, false, MAX_DBG_RESET_REGS, 0 };
73114b24e2bSVaishali Kulkarni 
73214b24e2bSVaishali Kulkarni static struct block_defs block_misc_defs = {
73314b24e2bSVaishali Kulkarni 	"misc", { false, false }, false, 0,
73414b24e2bSVaishali Kulkarni 	{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
73514b24e2bSVaishali Kulkarni 	0, 0, 0, 0, 0,
73614b24e2bSVaishali Kulkarni 	false, false, MAX_DBG_RESET_REGS, 0 };
73714b24e2bSVaishali Kulkarni 
73814b24e2bSVaishali Kulkarni static struct block_defs block_dbu_defs = {
73914b24e2bSVaishali Kulkarni 	"dbu", { false, false }, false, 0,
74014b24e2bSVaishali Kulkarni 	{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
74114b24e2bSVaishali Kulkarni 	0, 0, 0, 0, 0,
74214b24e2bSVaishali Kulkarni 	false, false, MAX_DBG_RESET_REGS, 0 };
74314b24e2bSVaishali Kulkarni 
74414b24e2bSVaishali Kulkarni static struct block_defs block_pglue_b_defs = {
74514b24e2bSVaishali Kulkarni 	"pglue_b", { true, true }, false, 0,
74614b24e2bSVaishali Kulkarni 	{ DBG_BUS_CLIENT_RBCH, DBG_BUS_CLIENT_RBCH },
74714b24e2bSVaishali Kulkarni 	PGLUE_B_REG_DBG_SELECT, PGLUE_B_REG_DBG_DWORD_ENABLE,
74814b24e2bSVaishali Kulkarni 	PGLUE_B_REG_DBG_SHIFT, PGLUE_B_REG_DBG_FORCE_VALID,
74914b24e2bSVaishali Kulkarni 	PGLUE_B_REG_DBG_FORCE_FRAME,
75014b24e2bSVaishali Kulkarni 	true, false, DBG_RESET_REG_MISCS_PL_HV, 1 };
75114b24e2bSVaishali Kulkarni 
75214b24e2bSVaishali Kulkarni static struct block_defs block_cnig_defs = {
75314b24e2bSVaishali Kulkarni 	"cnig", { false, true }, false, 0,
75414b24e2bSVaishali Kulkarni 	{ MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW },
75514b24e2bSVaishali Kulkarni 	CNIG_REG_DBG_SELECT_K2_E5, CNIG_REG_DBG_DWORD_ENABLE_K2_E5,
75614b24e2bSVaishali Kulkarni 	CNIG_REG_DBG_SHIFT_K2_E5, CNIG_REG_DBG_FORCE_VALID_K2_E5,
75714b24e2bSVaishali Kulkarni 	CNIG_REG_DBG_FORCE_FRAME_K2_E5,
75814b24e2bSVaishali Kulkarni 	true, false, DBG_RESET_REG_MISCS_PL_HV, 0 };
75914b24e2bSVaishali Kulkarni 
76014b24e2bSVaishali Kulkarni static struct block_defs block_cpmu_defs = {
76114b24e2bSVaishali Kulkarni 	"cpmu", { false, false }, false, 0,
76214b24e2bSVaishali Kulkarni 	{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
76314b24e2bSVaishali Kulkarni 	0, 0, 0, 0, 0,
76414b24e2bSVaishali Kulkarni 	true, false, DBG_RESET_REG_MISCS_PL_HV, 8 };
76514b24e2bSVaishali Kulkarni 
76614b24e2bSVaishali Kulkarni static struct block_defs block_ncsi_defs = {
76714b24e2bSVaishali Kulkarni 	"ncsi", { true, true }, false, 0,
76814b24e2bSVaishali Kulkarni 	{ DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ },
76914b24e2bSVaishali Kulkarni 	NCSI_REG_DBG_SELECT, NCSI_REG_DBG_DWORD_ENABLE,
77014b24e2bSVaishali Kulkarni 	NCSI_REG_DBG_SHIFT, NCSI_REG_DBG_FORCE_VALID,
77114b24e2bSVaishali Kulkarni 	NCSI_REG_DBG_FORCE_FRAME,
77214b24e2bSVaishali Kulkarni 	true, false, DBG_RESET_REG_MISCS_PL_HV, 5 };
77314b24e2bSVaishali Kulkarni 
77414b24e2bSVaishali Kulkarni static struct block_defs block_opte_defs = {
77514b24e2bSVaishali Kulkarni 	"opte", { false, false }, false, 0,
77614b24e2bSVaishali Kulkarni 	{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
77714b24e2bSVaishali Kulkarni 	0, 0, 0, 0, 0,
77814b24e2bSVaishali Kulkarni 	true, false, DBG_RESET_REG_MISCS_PL_HV, 4 };
77914b24e2bSVaishali Kulkarni 
78014b24e2bSVaishali Kulkarni static struct block_defs block_bmb_defs = {
78114b24e2bSVaishali Kulkarni 	"bmb", { true, true }, false, 0,
78214b24e2bSVaishali Kulkarni 	{