1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License, v.1,  (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://opensource.org/licenses/CDDL-1.0.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 
22 /*
23 * Copyright 2014-2017 Cavium, Inc.
24 * The contents of this file are subject to the terms of the Common Development
25 * and Distribution License, v.1,  (the "License").
26 
27 * You may not use this file except in compliance with the License.
28 
29 * You can obtain a copy of the License at available
30 * at http://opensource.org/licenses/CDDL-1.0
31 
32 * See the License for the specific language governing permissions and
33 * limitations under the License.
34 */
35 
36 #include "bcm_osal.h"
37 #include "ecore.h"
38 #include "ecore_hw.h"
39 #include "ecore_mcp.h"
40 #include "spad_layout.h"
41 #include "nvm_map.h"
42 #include "reg_addr.h"
43 #include "ecore_hsi_common.h"
44 #include "ecore_hsi_debug_tools.h"
45 #include "mcp_public.h"
46 #include "nvm_map.h"
47 #ifndef USE_DBG_BIN_FILE
48 #include "ecore_dbg_values.h"
49 #endif
50 #include "ecore_dbg_fw_funcs.h"
51 
52 /* Memory groups enum */
53 enum mem_groups {
54 	MEM_GROUP_PXP_MEM,
55 	MEM_GROUP_DMAE_MEM,
56 	MEM_GROUP_CM_MEM,
57 	MEM_GROUP_QM_MEM,
58 	MEM_GROUP_TM_MEM,
59 	MEM_GROUP_BRB_RAM,
60 	MEM_GROUP_BRB_MEM,
61 	MEM_GROUP_PRS_MEM,
62 	MEM_GROUP_SDM_MEM,
63 	MEM_GROUP_IOR,
64 	MEM_GROUP_RAM,
65 	MEM_GROUP_BTB_RAM,
66 	MEM_GROUP_RDIF_CTX,
67 	MEM_GROUP_TDIF_CTX,
68 	MEM_GROUP_CFC_MEM,
69 	MEM_GROUP_CONN_CFC_MEM,
70 	MEM_GROUP_TASK_CFC_MEM,
71 	MEM_GROUP_CAU_PI,
72 	MEM_GROUP_CAU_MEM,
73 	MEM_GROUP_PXP_ILT,
74 	MEM_GROUP_PBUF,
75 	MEM_GROUP_MULD_MEM,
76 	MEM_GROUP_BTB_MEM,
77 	MEM_GROUP_IGU_MEM,
78 	MEM_GROUP_IGU_MSIX,
79 	MEM_GROUP_CAU_SB,
80 	MEM_GROUP_BMB_RAM,
81 	MEM_GROUP_BMB_MEM,
82 	MEM_GROUPS_NUM
83 };
84 
85 /* Memory groups names */
86 static const char* s_mem_group_names[] = {
87 	"PXP_MEM",
88 	"DMAE_MEM",
89 	"CM_MEM",
90 	"QM_MEM",
91 	"TM_MEM",
92 	"BRB_RAM",
93 	"BRB_MEM",
94 	"PRS_MEM",
95 	"SDM_MEM",
96 	"IOR",
97 	"RAM",
98 	"BTB_RAM",
99 	"RDIF_CTX",
100 	"TDIF_CTX",
101 	"CFC_MEM",
102 	"CONN_CFC_MEM",
103 	"TASK_CFC_MEM",
104 	"CAU_PI",
105 	"CAU_MEM",
106 	"PXP_ILT",
107 	"PBUF",
108 	"MULD_MEM",
109 	"BTB_MEM",
110 	"IGU_MEM",
111 	"IGU_MSIX",
112 	"CAU_SB",
113 	"BMB_RAM",
114 	"BMB_MEM",
115 };
116 
117 /* Idle check conditions */
118 
119 #ifndef __PREVENT_COND_ARR__
120 
cond5(const u32 * r,const u32 * imm)121 static u32 cond5(const u32 *r, const u32 *imm) {
122 	return (((r[0] & imm[0]) != imm[1]) && ((r[1] & imm[2]) != imm[3]));
123 }
124 
cond7(const u32 * r,const u32 * imm)125 static u32 cond7(const u32 *r, const u32 *imm) {
126 	return (((r[0] >> imm[0]) & imm[1]) != imm[2]);
127 }
128 
cond14(const u32 * r,const u32 * imm)129 static u32 cond14(const u32 *r, const u32 *imm) {
130 	return ((r[0] != imm[0]) && (((r[1] >> imm[1]) & imm[2]) == imm[3]));
131 }
132 
cond6(const u32 * r,const u32 * imm)133 static u32 cond6(const u32 *r, const u32 *imm) {
134 	return ((r[0] & imm[0]) != imm[1]);
135 }
136 
cond9(const u32 * r,const u32 * imm)137 static u32 cond9(const u32 *r, const u32 *imm) {
138 	return ((r[0] & imm[0]) >> imm[1]) != (((r[0] & imm[2]) >> imm[3]) | ((r[1] & imm[4]) << imm[5]));
139 }
140 
cond10(const u32 * r,const u32 * imm)141 static u32 cond10(const u32 *r, const u32 *imm) {
142 	return ((r[0] & imm[0]) >> imm[1]) != (r[0] & imm[2]);
143 }
144 
cond4(const u32 * r,const u32 * imm)145 static u32 cond4(const u32 *r, const u32 *imm) {
146 	return ((r[0] & ~imm[0]) != imm[1]);
147 }
148 
cond0(const u32 * r,const u32 * imm)149 static u32 cond0(const u32 *r, const u32 *imm) {
150 	return ((r[0] & ~r[1]) != imm[0]);
151 }
152 
cond1(const u32 * r,const u32 * imm)153 static u32 cond1(const u32 *r, const u32 *imm) {
154 	return (r[0] != imm[0]);
155 }
156 
cond11(const u32 * r,const u32 * imm)157 static u32 cond11(const u32 *r, const u32 *imm) {
158 	return (r[0] != r[1] && r[2] == imm[0]);
159 }
160 
cond12(const u32 * r,const u32 * imm)161 static u32 cond12(const u32 *r, const u32 *imm) {
162 	return (r[0] != r[1] && r[2] > imm[0]);
163 }
164 
cond3(const u32 * r,const u32 * imm)165 static u32 cond3(const u32 *r, const u32 *imm) {
166 	return (r[0] != r[1]);
167 }
168 
cond13(const u32 * r,const u32 * imm)169 static u32 cond13(const u32 *r, const u32 *imm) {
170 	return (r[0] & imm[0]);
171 }
172 
cond8(const u32 * r,const u32 * imm)173 static u32 cond8(const u32 *r, const u32 *imm) {
174 	return (r[0] < (r[1] - imm[0]));
175 }
176 
cond2(const u32 * r,const u32 * imm)177 static u32 cond2(const u32 *r, const u32 *imm) {
178 	return (r[0] > imm[0]);
179 }
180 
181 /* Array of Idle Check conditions */
182 static u32 (*cond_arr[])(const u32 *r, const u32 *imm) = {
183 	cond0,
184 	cond1,
185 	cond2,
186 	cond3,
187 	cond4,
188 	cond5,
189 	cond6,
190 	cond7,
191 	cond8,
192 	cond9,
193 	cond10,
194 	cond11,
195 	cond12,
196 	cond13,
197 	cond14,
198 };
199 
200 #endif /* __PREVENT_COND_ARR__ */
201 
202 
203 /******************************* Data Types **********************************/
204 
205 enum platform_ids {
206 	PLATFORM_ASIC,
207 	PLATFORM_EMUL_FULL,
208 	PLATFORM_EMUL_REDUCED,
209 	PLATFORM_FPGA,
210 	MAX_PLATFORM_IDS
211 };
212 
213 struct chip_platform_defs {
214 	u8 num_ports;
215 	u8 num_pfs;
216 	u8 num_vfs;
217 };
218 
219 /* Chip constant definitions */
220 struct chip_defs {
221 	const char *name;
222 	struct chip_platform_defs per_platform[MAX_PLATFORM_IDS];
223 };
224 
225 /* Platform constant definitions */
226 struct platform_defs {
227 	const char *name;
228 	u32 delay_factor;
229 };
230 
231 /* Storm constant definitions.
232  * Addresses are in bytes, sizes are in quad-regs.
233  */
234 struct storm_defs {
235 	char letter;
236 	enum block_id block_id;
237 	enum dbg_bus_clients dbg_client_id[MAX_CHIP_IDS];
238 	bool has_vfc;
239 	u32 sem_fast_mem_addr;
240 	u32 sem_frame_mode_addr;
241 	u32 sem_slow_enable_addr;
242 	u32 sem_slow_mode_addr;
243 	u32 sem_slow_mode1_conf_addr;
244 	u32 sem_sync_dbg_empty_addr;
245 	u32 sem_slow_dbg_empty_addr;
246 	u32 cm_ctx_wr_addr;
247 	u32 cm_conn_ag_ctx_lid_size;
248 	u32 cm_conn_ag_ctx_rd_addr;
249 	u32 cm_conn_st_ctx_lid_size;
250 	u32 cm_conn_st_ctx_rd_addr;
251 	u32 cm_task_ag_ctx_lid_size;
252 	u32 cm_task_ag_ctx_rd_addr;
253 	u32 cm_task_st_ctx_lid_size;
254 	u32 cm_task_st_ctx_rd_addr;
255 };
256 
257 /* Block constant definitions */
258 struct block_defs {
259 	const char *name;
260 	bool has_dbg_bus[MAX_CHIP_IDS];
261 	bool associated_to_storm;
262 
263 	/* Valid only if associated_to_storm is true */
264 	u32 storm_id;
265 	enum dbg_bus_clients dbg_client_id[MAX_CHIP_IDS];
266 	u32 dbg_select_addr;
267 	u32 dbg_enable_addr;
268 	u32 dbg_shift_addr;
269 	u32 dbg_force_valid_addr;
270 	u32 dbg_force_frame_addr;
271 	bool has_reset_bit;
272 
273 	/* If true, block is taken out of reset before dump */
274 	bool unreset;
275 	enum dbg_reset_regs reset_reg;
276 
277 	/* Bit offset in reset register */
278 	u8 reset_bit_offset;
279 };
280 
281 /* Reset register definitions */
282 struct reset_reg_defs {
283 	u32 addr;
284 	u32 unreset_val;
285 	bool exists[MAX_CHIP_IDS];
286 };
287 
288 /* Debug Bus Constraint operation constant definitions */
289 struct dbg_bus_constraint_op_defs {
290 	u8 hw_op_val;
291 	bool is_cyclic;
292 };
293 
294 /* Storm Mode definitions */
295 struct storm_mode_defs {
296 	const char *name;
297 	bool is_fast_dbg;
298 	u8 id_in_hw;
299 };
300 
301 struct grc_param_defs {
302 	u32 default_val[MAX_CHIP_IDS];
303 	u32 min;
304 	u32 max;
305 	bool is_preset;
306 	u32 exclude_all_preset_val;
307 	u32 crash_preset_val;
308 };
309 
310 /* address is in 128b units. Width is in bits. */
311 struct rss_mem_defs {
312 	const char *mem_name;
313 	const char *type_name;
314 	u32 addr;
315 	u32 num_entries[MAX_CHIP_IDS];
316 	u32 entry_width[MAX_CHIP_IDS];
317 };
318 
319 struct vfc_ram_defs {
320 	const char *mem_name;
321 	const char *type_name;
322 	u32 base_row;
323 	u32 num_rows;
324 };
325 
326 struct big_ram_defs {
327 	const char *instance_name;
328 	enum mem_groups mem_group_id;
329 	enum mem_groups ram_mem_group_id;
330 	enum dbg_grc_params grc_param;
331 	u32 addr_reg_addr;
332 	u32 data_reg_addr;
333 	u32 num_of_blocks[MAX_CHIP_IDS];
334 };
335 
336 struct phy_defs {
337 	const char *phy_name;
338 
339 	/* PHY base GRC address */
340 	u32 base_addr;
341 
342 	/* Relative address of indirect TBUS address register (bits 0..7) */
343 	u32 tbus_addr_lo_addr;
344 
345 	/* Relative address of indirect TBUS address register (bits 8..10) */
346 	u32 tbus_addr_hi_addr;
347 
348 	/* Relative address of indirect TBUS data register (bits 0..7) */
349 	u32 tbus_data_lo_addr;
350 
351 	/* Relative address of indirect TBUS data register (bits 8..11) */
352 	u32 tbus_data_hi_addr;
353 };
354 
355 /******************************** Constants **********************************/
356 
357 #define MAX_LCIDS			320
358 #define MAX_LTIDS			320
359 
360 #define NUM_IOR_SETS			2
361 #define IORS_PER_SET			176
362 #define IOR_SET_OFFSET(set_id)		((set_id) * 256)
363 
364 #define BYTES_IN_DWORD			sizeof(u32)
365 
366 /* Cyclic  right */
367 #define SHR(val, val_width, amount)	(((val) | ((val) << (val_width))) 					>> (amount)) & ((1 << (val_width)) - 1)
368 
369 /* In the macros below, size and offset are specified in bits */
370 #define CEIL_DWORDS(size)		DIV_ROUND_UP(size, 32)
371 #define FIELD_BIT_OFFSET(type, field)	type##_##field##_##OFFSET
372 #define FIELD_BIT_SIZE(type, field)	type##_##field##_##SIZE
373 #define FIELD_DWORD_OFFSET(type, field)		(int)(FIELD_BIT_OFFSET(type, field) / 32)
374 #define FIELD_DWORD_SHIFT(type, field)	(FIELD_BIT_OFFSET(type, field) % 32)
375 #define FIELD_BIT_MASK(type, field)		(((1 << FIELD_BIT_SIZE(type, field)) - 1) 	<< FIELD_DWORD_SHIFT(type, field))
376 
377 #define SET_VAR_FIELD(var, type, field, val) 	var[FIELD_DWORD_OFFSET(type, field)] &= 		(~FIELD_BIT_MASK(type, field)); 	var[FIELD_DWORD_OFFSET(type, field)] |= 		(val) << FIELD_DWORD_SHIFT(type, field)
378 
379 #define ARR_REG_WR(dev, ptt, addr, arr, arr_size) 	for (i = 0; i < (arr_size); i++) 		ecore_wr(dev, ptt, addr, (arr)[i])
380 
381 #define ARR_REG_RD(dev, ptt, addr, arr, arr_size) 	for (i = 0; i < (arr_size); i++) 		(arr)[i] = ecore_rd(dev, ptt, addr)
382 
383 #define CHECK_ARR_SIZE(arr, size) 	OSAL_BUILD_BUG_ON(!(OSAL_ARRAY_SIZE(arr) == size))
384 
385 #ifndef DWORDS_TO_BYTES
386 #define DWORDS_TO_BYTES(dwords)		((dwords) * BYTES_IN_DWORD)
387 #endif
388 #ifndef BYTES_TO_DWORDS
389 #define BYTES_TO_DWORDS(bytes)		((bytes) / BYTES_IN_DWORD)
390 #endif
391 
392 /* extra lines include a signature line + optional latency events line */
393 #ifndef NUM_DBG_LINES
394 #define NUM_EXTRA_DBG_LINES(block_desc)		(1 + (block_desc->has_latency_events ? 1 : 0))
395 #define NUM_DBG_LINES(block_desc)		(block_desc->num_of_lines + NUM_EXTRA_DBG_LINES(block_desc))
396 #endif
397 
398 #define RAM_LINES_TO_DWORDS(lines)	((lines) * 2)
399 #define RAM_LINES_TO_BYTES(lines)		DWORDS_TO_BYTES(RAM_LINES_TO_DWORDS(lines))
400 
401 #define REG_DUMP_LEN_SHIFT		24
402 #define MEM_DUMP_ENTRY_SIZE_DWORDS		BYTES_TO_DWORDS(sizeof(struct dbg_dump_mem))
403 
404 #define IDLE_CHK_RULE_SIZE_DWORDS		BYTES_TO_DWORDS(sizeof(struct dbg_idle_chk_rule))
405 
406 #define IDLE_CHK_RESULT_HDR_DWORDS		BYTES_TO_DWORDS(sizeof(struct dbg_idle_chk_result_hdr))
407 
408 #define IDLE_CHK_RESULT_REG_HDR_DWORDS		BYTES_TO_DWORDS(sizeof(struct dbg_idle_chk_result_reg_hdr))
409 
410 #define IDLE_CHK_MAX_ENTRIES_SIZE	32
411 
412 /* The sizes and offsets below are specified in bits */
413 #define VFC_CAM_CMD_STRUCT_SIZE		64
414 #define VFC_CAM_CMD_ROW_OFFSET		48
415 #define VFC_CAM_CMD_ROW_SIZE		9
416 #define VFC_CAM_ADDR_STRUCT_SIZE	16
417 #define VFC_CAM_ADDR_OP_OFFSET		0
418 #define VFC_CAM_ADDR_OP_SIZE		4
419 #define VFC_CAM_RESP_STRUCT_SIZE	256
420 #define VFC_RAM_ADDR_STRUCT_SIZE	16
421 #define VFC_RAM_ADDR_OP_OFFSET		0
422 #define VFC_RAM_ADDR_OP_SIZE		2
423 #define VFC_RAM_ADDR_ROW_OFFSET		2
424 #define VFC_RAM_ADDR_ROW_SIZE		10
425 #define VFC_RAM_RESP_STRUCT_SIZE	256
426 
427 #define VFC_CAM_CMD_DWORDS		CEIL_DWORDS(VFC_CAM_CMD_STRUCT_SIZE)
428 #define VFC_CAM_ADDR_DWORDS		CEIL_DWORDS(VFC_CAM_ADDR_STRUCT_SIZE)
429 #define VFC_CAM_RESP_DWORDS		CEIL_DWORDS(VFC_CAM_RESP_STRUCT_SIZE)
430 #define VFC_RAM_CMD_DWORDS		VFC_CAM_CMD_DWORDS
431 #define VFC_RAM_ADDR_DWORDS		CEIL_DWORDS(VFC_RAM_ADDR_STRUCT_SIZE)
432 #define VFC_RAM_RESP_DWORDS		CEIL_DWORDS(VFC_RAM_RESP_STRUCT_SIZE)
433 
434 #define NUM_VFC_RAM_TYPES		4
435 
436 #define VFC_CAM_NUM_ROWS		512
437 
438 #define VFC_OPCODE_CAM_RD		14
439 #define VFC_OPCODE_RAM_RD		0
440 
441 #define NUM_RSS_MEM_TYPES		5
442 
443 #define NUM_BIG_RAM_TYPES		3
444 #define BIG_RAM_BLOCK_SIZE_BYTES	128
445 #define BIG_RAM_BLOCK_SIZE_DWORDS		BYTES_TO_DWORDS(BIG_RAM_BLOCK_SIZE_BYTES)
446 
447 #define NUM_PHY_TBUS_ADDRESSES		2048
448 #define PHY_DUMP_SIZE_DWORDS		(NUM_PHY_TBUS_ADDRESSES / 2)
449 
450 #define SEM_FAST_MODE6_SRC_ENABLE	0x10
451 #define SEM_FAST_MODE6_SRC_DISABLE	0x3f
452 
453 #define SEM_SLOW_MODE1_DATA_ENABLE	0x1
454 
455 #define VALUES_PER_CYCLE		4
456 #define MAX_CYCLE_VALUES_MASK		((1 << VALUES_PER_CYCLE) - 1)
457 
458 #define MAX_DWORDS_PER_CYCLE		8
459 
460 #define HW_ID_BITS			3
461 
462 #define NUM_CALENDAR_SLOTS		16
463 
464 #define MAX_TRIGGER_STATES		3
465 #define TRIGGER_SETS_PER_STATE		2
466 #define MAX_CONSTRAINTS			4
467 
468 #define SEM_FILTER_CID_EN_MASK		0x008
469 #define SEM_FILTER_EID_MASK_EN_MASK	0x010
470 #define SEM_FILTER_EID_RANGE_EN_MASK	0x110
471 
472 #define CHUNK_SIZE_IN_DWORDS		64
473 #define CHUNK_SIZE_IN_BYTES		DWORDS_TO_BYTES(CHUNK_SIZE_IN_DWORDS)
474 
475 #define INT_BUF_NUM_OF_LINES		192
476 #define INT_BUF_LINE_SIZE_IN_DWORDS	16
477 #define INT_BUF_SIZE_IN_DWORDS			(INT_BUF_NUM_OF_LINES * INT_BUF_LINE_SIZE_IN_DWORDS)
478 #define INT_BUF_SIZE_IN_CHUNKS			(INT_BUF_SIZE_IN_DWORDS / CHUNK_SIZE_IN_DWORDS)
479 
480 #define PCI_BUF_LINE_SIZE_IN_DWORDS	8
481 #define PCI_BUF_LINE_SIZE_IN_BYTES		DWORDS_TO_BYTES(PCI_BUF_LINE_SIZE_IN_DWORDS)
482 
483 #define TARGET_EN_MASK_PCI		0x3
484 #define TARGET_EN_MASK_NIG		0x4
485 
486 #define PCI_REQ_CREDIT			1
487 #define PCI_PHYS_ADDR_TYPE		0
488 
489 #define OPAQUE_FID(pci_func)		((pci_func << 4) | 0xff00)
490 
491 #define RESET_REG_UNRESET_OFFSET	4
492 
493 #define PCI_PKT_SIZE_IN_CHUNKS		1
494 #define PCI_PKT_SIZE_IN_BYTES			(PCI_PKT_SIZE_IN_CHUNKS * CHUNK_SIZE_IN_BYTES)
495 
496 #define NIG_PKT_SIZE_IN_CHUNKS		4
497 
498 #define FLUSH_DELAY_MS			500
499 #define STALL_DELAY_MS			500
500 
501 #define SRC_MAC_ADDR_LO16		0x0a0b
502 #define SRC_MAC_ADDR_HI32		0x0c0d0e0f
503 #define ETH_TYPE			0x1000
504 
505 #define STATIC_DEBUG_LINE_DWORDS	9
506 
507 #define NUM_COMMON_GLOBAL_PARAMS	8
508 
509 #define FW_IMG_KUKU			0
510 #define FW_IMG_MAIN			1
511 #define FW_IMG_L2B			2
512 
513 #ifndef REG_FIFO_ELEMENT_DWORDS
514 #define REG_FIFO_ELEMENT_DWORDS		2
515 #endif
516 #define REG_FIFO_DEPTH_ELEMENTS		32
517 #define REG_FIFO_DEPTH_DWORDS			(REG_FIFO_ELEMENT_DWORDS * REG_FIFO_DEPTH_ELEMENTS)
518 
519 #ifndef IGU_FIFO_ELEMENT_DWORDS
520 #define IGU_FIFO_ELEMENT_DWORDS		4
521 #endif
522 #define IGU_FIFO_DEPTH_ELEMENTS		64
523 #define IGU_FIFO_DEPTH_DWORDS			(IGU_FIFO_ELEMENT_DWORDS * IGU_FIFO_DEPTH_ELEMENTS)
524 
525 #define SEMI_SYNC_FIFO_POLLING_DELAY_MS	5
526 #define SEMI_SYNC_FIFO_POLLING_COUNT	20
527 
528 #ifndef PROTECTION_OVERRIDE_ELEMENT_DWORDS
529 #define PROTECTION_OVERRIDE_ELEMENT_DWORDS 2
530 #endif
531 #define PROTECTION_OVERRIDE_DEPTH_ELEMENTS 20
532 #define PROTECTION_OVERRIDE_DEPTH_DWORDS   	(PROTECTION_OVERRIDE_DEPTH_ELEMENTS 	* PROTECTION_OVERRIDE_ELEMENT_DWORDS)
533 
534 #define MCP_SPAD_TRACE_OFFSIZE_ADDR		(MCP_REG_SCRATCH + 	offsetof(struct static_init, sections[SPAD_SECTION_TRACE]))
535 
536 #define EMPTY_FW_VERSION_STR		"???_???_???_???"
537 #define EMPTY_FW_IMAGE_STR		"???????????????"
538 
539 
540 /***************************** Constant Arrays *******************************/
541 
542 struct dbg_array {
543 	const u32 *ptr;
544 	u32 size_in_dwords;
545 };
546 
547 /* Debug arrays */
548 #ifdef USE_DBG_BIN_FILE
549 static struct dbg_array s_dbg_arrays[MAX_BIN_DBG_BUFFER_TYPE] = { { OSAL_NULL } };
550 #else
551 static struct dbg_array s_dbg_arrays[MAX_BIN_DBG_BUFFER_TYPE] = {
552 
553 	/* BIN_BUF_DBG_MODE_TREE */
554 	{ (u32*)dbg_modes_tree_buf, OSAL_ARRAY_SIZE(dbg_modes_tree_buf)},
555 
556 	/* BIN_BUF_DBG_DUMP_REG */
557 	{ dump_reg, OSAL_ARRAY_SIZE(dump_reg) },
558 
559 	/* BIN_BUF_DBG_DUMP_MEM */
560 	{ dump_mem, OSAL_ARRAY_SIZE(dump_mem) },
561 
562 	/* BIN_BUF_DBG_IDLE_CHK_REGS */
563 	{ idle_chk_regs, OSAL_ARRAY_SIZE(idle_chk_regs) },
564 
565 	/* BIN_BUF_DBG_IDLE_CHK_IMMS */
566 	{ idle_chk_imms, OSAL_ARRAY_SIZE(idle_chk_imms) },
567 
568 	/* BIN_BUF_DBG_IDLE_CHK_RULES */
569 	{ idle_chk_rules, OSAL_ARRAY_SIZE(idle_chk_rules) },
570 
571 	/* BIN_BUF_DBG_IDLE_CHK_PARSING_DATA */
572 	{ OSAL_NULL, 0 },
573 
574 	/* BIN_BUF_DBG_ATTN_BLOCKS */
575 	{ attn_block, OSAL_ARRAY_SIZE(attn_block) },
576 
577 	/* BIN_BUF_DBG_ATTN_REGSS */
578 	{ attn_reg, OSAL_ARRAY_SIZE(attn_reg) },
579 
580 	/* BIN_BUF_DBG_ATTN_INDEXES */
581 	{ OSAL_NULL, 0 },
582 
583 	/* BIN_BUF_DBG_ATTN_NAME_OFFSETS */
584 	{ OSAL_NULL, 0 },
585 
586 	/* BIN_BUF_DBG_BUS_BLOCKS */
587 	{ dbg_bus_blocks, OSAL_ARRAY_SIZE(dbg_bus_blocks) },
588 
589 	/* BIN_BUF_DBG_BUS_LINES */
590 	{ dbg_bus_lines, OSAL_ARRAY_SIZE(dbg_bus_lines) },
591 
592 	/* BIN_BUF_DBG_BUS_BLOCKS_USER_DATA */
593 	{ OSAL_NULL, 0 },
594 
595 	/* BIN_BUF_DBG_BUS_LINE_NAME_OFFSETS */
596 	{ OSAL_NULL, 0 },
597 
598 	/* BIN_BUF_DBG_PARSING_STRINGS */
599 	{ OSAL_NULL, 0 }
600 };
601 #endif
602 
603 /* Chip constant definitions array */
604 static struct chip_defs s_chip_defs[MAX_CHIP_IDS] = {
605 	{ "bb",
606 
607 		/* ASIC */
608 		{ { MAX_NUM_PORTS_BB, MAX_NUM_PFS_BB, MAX_NUM_VFS_BB },
609 
610 		/* EMUL_FULL */
611 		{ MAX_NUM_PORTS_BB, MAX_NUM_PFS_BB, MAX_NUM_VFS_BB },
612 
613 		/* EMUL_REDUCED */
614 		{ MAX_NUM_PORTS_BB, MAX_NUM_PFS_BB, MAX_NUM_VFS_BB },
615 
616 		/* FPGA */
617 		{ MAX_NUM_PORTS_BB, MAX_NUM_PFS_BB, MAX_NUM_VFS_BB } } },
618 
619 	{ "ah",
620 
621 		/* ASIC */
622 		{ { MAX_NUM_PORTS_K2, MAX_NUM_PFS_K2, MAX_NUM_VFS_K2 },
623 
624 		/* EMUL_FULL */
625 		{ MAX_NUM_PORTS_K2, MAX_NUM_PFS_K2, MAX_NUM_VFS_K2 },
626 
627 		/* EMUL_REDUCED */
628 		{ MAX_NUM_PORTS_K2, MAX_NUM_PFS_K2, MAX_NUM_VFS_K2 },
629 
630 		/* FPGA */
631 		{ MAX_NUM_PORTS_K2, 8, MAX_NUM_VFS_K2 } } }
632 };
633 
634 /* Storm constant definitions array */
635 static struct storm_defs s_storm_defs[] = {
636 
637 	/* Tstorm */
638 	{	'T', BLOCK_TSEM,
639 		{ DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT }, true,
640 		TSEM_REG_FAST_MEMORY,
641 		TSEM_REG_DBG_FRAME_MODE_BB_K2, TSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
642 		TSEM_REG_SLOW_DBG_MODE_BB_K2, TSEM_REG_DBG_MODE1_CFG_BB_K2,
643 		TSEM_REG_SYNC_DBG_EMPTY, TSEM_REG_SLOW_DBG_EMPTY_BB_K2,
644 		TCM_REG_CTX_RBC_ACCS,
645 		4, TCM_REG_AGG_CON_CTX,
646 		16, TCM_REG_SM_CON_CTX,
647 		2, TCM_REG_AGG_TASK_CTX,
648 		4, TCM_REG_SM_TASK_CTX },
649 
650 	/* Mstorm */
651 	{	'M', BLOCK_MSEM,
652 		{ DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM }, false,
653 		MSEM_REG_FAST_MEMORY,
654 		MSEM_REG_DBG_FRAME_MODE_BB_K2, MSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
655 		MSEM_REG_SLOW_DBG_MODE_BB_K2, MSEM_REG_DBG_MODE1_CFG_BB_K2,
656 		MSEM_REG_SYNC_DBG_EMPTY, MSEM_REG_SLOW_DBG_EMPTY_BB_K2,
657 		MCM_REG_CTX_RBC_ACCS,
658 		1, MCM_REG_AGG_CON_CTX,
659 		10, MCM_REG_SM_CON_CTX,
660 		2, MCM_REG_AGG_TASK_CTX,
661 		7, MCM_REG_SM_TASK_CTX },
662 
663 	/* Ustorm */
664 	{	'U', BLOCK_USEM,
665 		{ DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU }, false,
666 		USEM_REG_FAST_MEMORY,
667 		USEM_REG_DBG_FRAME_MODE_BB_K2, USEM_REG_SLOW_DBG_ACTIVE_BB_K2,
668 		USEM_REG_SLOW_DBG_MODE_BB_K2, USEM_REG_DBG_MODE1_CFG_BB_K2,
669 		USEM_REG_SYNC_DBG_EMPTY, USEM_REG_SLOW_DBG_EMPTY_BB_K2,
670 		UCM_REG_CTX_RBC_ACCS,
671 		2, UCM_REG_AGG_CON_CTX,
672 		13, UCM_REG_SM_CON_CTX,
673 		3, UCM_REG_AGG_TASK_CTX,
674 		3, UCM_REG_SM_TASK_CTX },
675 
676 	/* Xstorm */
677 	{	'X', BLOCK_XSEM,
678 		{ DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX }, false,
679 		XSEM_REG_FAST_MEMORY,
680 		XSEM_REG_DBG_FRAME_MODE_BB_K2, XSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
681 		XSEM_REG_SLOW_DBG_MODE_BB_K2, XSEM_REG_DBG_MODE1_CFG_BB_K2,
682 		XSEM_REG_SYNC_DBG_EMPTY, XSEM_REG_SLOW_DBG_EMPTY_BB_K2,
683 		XCM_REG_CTX_RBC_ACCS,
684 		9, XCM_REG_AGG_CON_CTX,
685 		15, XCM_REG_SM_CON_CTX,
686 		0, 0,
687 		0, 0 },
688 
689 	/* Ystorm */
690 	{	'Y', BLOCK_YSEM,
691 		{ DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY }, false,
692 		YSEM_REG_FAST_MEMORY,
693 		YSEM_REG_DBG_FRAME_MODE_BB_K2, YSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
694 		YSEM_REG_SLOW_DBG_MODE_BB_K2, YSEM_REG_DBG_MODE1_CFG_BB_K2,
695 		YSEM_REG_SYNC_DBG_EMPTY, TSEM_REG_SLOW_DBG_EMPTY_BB_K2,
696 		YCM_REG_CTX_RBC_ACCS,
697 		2, YCM_REG_AGG_CON_CTX,
698 		3, YCM_REG_SM_CON_CTX,
699 		2, YCM_REG_AGG_TASK_CTX,
700 		12, YCM_REG_SM_TASK_CTX },
701 
702 	/* Pstorm */
703 	{	'P', BLOCK_PSEM,
704 		{ DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS }, true,
705 		PSEM_REG_FAST_MEMORY,
706 		PSEM_REG_DBG_FRAME_MODE_BB_K2, PSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
707 		PSEM_REG_SLOW_DBG_MODE_BB_K2, PSEM_REG_DBG_MODE1_CFG_BB_K2,
708 		PSEM_REG_SYNC_DBG_EMPTY, PSEM_REG_SLOW_DBG_EMPTY_BB_K2,
709 		PCM_REG_CTX_RBC_ACCS,
710 		0, 0,
711 		10, PCM_REG_SM_CON_CTX,
712 		0, 0,
713 		0, 0 }
714 };
715 
716 /* Block definitions array */
717 
718 static struct block_defs block_grc_defs = {
719 	"grc", { true, true }, false, 0,
720 	{ DBG_BUS_CLIENT_RBCN, DBG_BUS_CLIENT_RBCN },
721 	GRC_REG_DBG_SELECT, GRC_REG_DBG_DWORD_ENABLE,
722 	GRC_REG_DBG_SHIFT, GRC_REG_DBG_FORCE_VALID,
723 	GRC_REG_DBG_FORCE_FRAME,
724 	true, false, DBG_RESET_REG_MISC_PL_UA, 1 };
725 
726 static struct block_defs block_miscs_defs = {
727 	"miscs", { false, false }, false, 0,
728 	{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
729 	0, 0, 0, 0, 0,
730 	false, false, MAX_DBG_RESET_REGS, 0 };
731 
732 static struct block_defs block_misc_defs = {
733 	"misc", { false, false }, false, 0,
734 	{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
735 	0, 0, 0, 0, 0,
736 	false, false, MAX_DBG_RESET_REGS, 0 };
737 
738 static struct block_defs block_dbu_defs = {
739 	"dbu", { false, false }, false, 0,
740 	{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
741 	0, 0, 0, 0, 0,
742 	false, false, MAX_DBG_RESET_REGS, 0 };
743 
744 static struct block_defs block_pglue_b_defs = {
745 	"pglue_b", { true, true }, false, 0,
746 	{ DBG_BUS_CLIENT_RBCH, DBG_BUS_CLIENT_RBCH },
747 	PGLUE_B_REG_DBG_SELECT, PGLUE_B_REG_DBG_DWORD_ENABLE,
748 	PGLUE_B_REG_DBG_SHIFT, PGLUE_B_REG_DBG_FORCE_VALID,
749 	PGLUE_B_REG_DBG_FORCE_FRAME,
750 	true, false, DBG_RESET_REG_MISCS_PL_HV, 1 };
751 
752 static struct block_defs block_cnig_defs = {
753 	"cnig", { false, true }, false, 0,
754 	{ MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW },
755 	CNIG_REG_DBG_SELECT_K2_E5, CNIG_REG_DBG_DWORD_ENABLE_K2_E5,
756 	CNIG_REG_DBG_SHIFT_K2_E5, CNIG_REG_DBG_FORCE_VALID_K2_E5,
757 	CNIG_REG_DBG_FORCE_FRAME_K2_E5,
758 	true, false, DBG_RESET_REG_MISCS_PL_HV, 0 };
759 
760 static struct block_defs block_cpmu_defs = {
761 	"cpmu", { false, false }, false, 0,
762 	{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
763 	0, 0, 0, 0, 0,
764 	true, false, DBG_RESET_REG_MISCS_PL_HV, 8 };
765 
766 static struct block_defs block_ncsi_defs = {
767 	"ncsi", { true, true }, false, 0,
768 	{ DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ },
769 	NCSI_REG_DBG_SELECT, NCSI_REG_DBG_DWORD_ENABLE,
770 	NCSI_REG_DBG_SHIFT, NCSI_REG_DBG_FORCE_VALID,
771 	NCSI_REG_DBG_FORCE_FRAME,
772 	true, false, DBG_RESET_REG_MISCS_PL_HV, 5 };
773 
774 static struct block_defs block_opte_defs = {
775 	"opte", { false, false }, false, 0,
776 	{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
777 	0, 0, 0, 0, 0,
778 	true, false, DBG_RESET_REG_MISCS_PL_HV, 4 };
779 
780 static struct block_defs block_bmb_defs = {
781 	"bmb", { true, true }, false, 0,
782 	{ DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCB },
783 	BMB_REG_DBG_SELECT, BMB_REG_DBG_DWORD_ENABLE,
784 	BMB_REG_DBG_SHIFT, BMB_REG_DBG_FORCE_VALID,
785 	BMB_REG_DBG_FORCE_FRAME,
786 	true, false, DBG_RESET_REG_MISCS_PL_UA, 7 };
787 
788 static struct block_defs block_pcie_defs = {
789 	"pcie", { false, true }, false, 0,
790 	{ MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH },
791 	PCIE_REG_DBG_COMMON_SELECT_K2_E5, PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2_E5,
792 	PCIE_REG_DBG_COMMON_SHIFT_K2_E5, PCIE_REG_DBG_COMMON_FORCE_VALID_K2_E5,
793 	PCIE_REG_DBG_COMMON_FORCE_FRAME_K2_E5,
794 	false, false, MAX_DBG_RESET_REGS, 0 };
795 
796 static struct block_defs block_mcp_defs = {
797 	"mcp", { false, false }, false, 0,
798 	{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
799 	0, 0, 0, 0, 0,
800 	false, false, MAX_DBG_RESET_REGS, 0 };
801 
802 static struct block_defs block_mcp2_defs = {
803 	"mcp2", { true, true }, false, 0,
804 	{ DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ },
805 	MCP2_REG_DBG_SELECT, MCP2_REG_DBG_DWORD_ENABLE,
806 	MCP2_REG_DBG_SHIFT, MCP2_REG_DBG_FORCE_VALID,
807 	MCP2_REG_DBG_FORCE_FRAME,
808 	false, false, MAX_DBG_RESET_REGS, 0 };
809 
810 static struct block_defs block_pswhst_defs = {
811 	"pswhst", { true, true }, false, 0,
812 	{ DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP },
813 	PSWHST_REG_DBG_SELECT, PSWHST_REG_DBG_DWORD_ENABLE,
814 	PSWHST_REG_DBG_SHIFT, PSWHST_REG_DBG_FORCE_VALID,
815 	PSWHST_REG_DBG_FORCE_FRAME,
816 	true, false, DBG_RESET_REG_MISC_PL_HV, 0 };
817 
818 static struct block_defs block_pswhst2_defs = {
819 	"pswhst2", { true, true }, false, 0,
820 	{ DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP },
821 	PSWHST2_REG_DBG_SELECT, PSWHST2_REG_DBG_DWORD_ENABLE,
822 	PSWHST2_REG_DBG_SHIFT, PSWHST2_REG_DBG_FORCE_VALID,
823 	PSWHST2_REG_DBG_FORCE_FRAME,
824 	true, false, DBG_RESET_REG_MISC_PL_HV, 0 };
825 
826 static struct block_defs block_pswrd_defs = {
827 	"pswrd", { true, true }, false, 0,
828 	{ DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP },
829 	PSWRD_REG_DBG_SELECT, PSWRD_REG_DBG_DWORD_ENABLE,
830 	PSWRD_REG_DBG_SHIFT, PSWRD_REG_DBG_FORCE_VALID,
831 	PSWRD_REG_DBG_FORCE_FRAME,
832 	true, false, DBG_RESET_REG_MISC_PL_HV, 2 };
833 
834 static struct block_defs block_pswrd2_defs = {
835 	"pswrd2", { true, true }, false, 0,
836 	{ DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP },
837 	PSWRD2_REG_DBG_SELECT, PSWRD2_REG_DBG_DWORD_ENABLE,
838 	PSWRD2_REG_DBG_SHIFT,	PSWRD2_REG_DBG_FORCE_VALID,
839 	PSWRD2_REG_DBG_FORCE_FRAME,
840 	true, false, DBG_RESET_REG_MISC_PL_HV, 2 };
841 
842 static struct block_defs block_pswwr_defs = {
843 	"pswwr", { true, true }, false, 0,
844 	{ DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP },
845 	PSWWR_REG_DBG_SELECT, PSWWR_REG_DBG_DWORD_ENABLE,
846 	PSWWR_REG_DBG_SHIFT, PSWWR_REG_DBG_FORCE_VALID,
847 	PSWWR_REG_DBG_FORCE_FRAME,
848 	true, false, DBG_RESET_REG_MISC_PL_HV, 3 };
849 
850 static struct block_defs block_pswwr2_defs = {
851 	"pswwr2", { false, false }, false, 0,
852 	{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
853 	0, 0, 0, 0, 0,
854 	true, false, DBG_RESET_REG_MISC_PL_HV, 3 };
855 
856 static struct block_defs block_pswrq_defs = {
857 	"pswrq", { true, true }, false, 0,
858 	{ DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP },
859 	PSWRQ_REG_DBG_SELECT, PSWRQ_REG_DBG_DWORD_ENABLE,
860 	PSWRQ_REG_DBG_SHIFT, PSWRQ_REG_DBG_FORCE_VALID,
861 	PSWRQ_REG_DBG_FORCE_FRAME,
862 	true, false, DBG_RESET_REG_MISC_PL_HV, 1 };
863 
864 static struct block_defs block_pswrq2_defs = {
865 	"pswrq2", { true, true }, false, 0,
866 	{ DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP },
867 	PSWRQ2_REG_DBG_SELECT, PSWRQ2_REG_DBG_DWORD_ENABLE,
868 	PSWRQ2_REG_DBG_SHIFT, PSWRQ2_REG_DBG_FORCE_VALID,
869 	PSWRQ2_REG_DBG_FORCE_FRAME,
870 	true, false, DBG_RESET_REG_MISC_PL_HV, 1 };
871 
872 static struct block_defs block_pglcs_defs =	{
873 	"pglcs", { false, true }, false, 0,
874 	{ MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH },
875 	PGLCS_REG_DBG_SELECT_K2_E5, PGLCS_REG_DBG_DWORD_ENABLE_K2_E5,
876 	PGLCS_REG_DBG_SHIFT_K2_E5, PGLCS_REG_DBG_FORCE_VALID_K2_E5,
877 	PGLCS_REG_DBG_FORCE_FRAME_K2_E5,
878 	true, false, DBG_RESET_REG_MISCS_PL_HV, 2 };
879 
880 static struct block_defs block_ptu_defs ={
881 	"ptu", { true, true }, false, 0,
882 	{ DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP },
883 	PTU_REG_DBG_SELECT, PTU_REG_DBG_DWORD_ENABLE,
884 	PTU_REG_DBG_SHIFT, PTU_REG_DBG_FORCE_VALID,
885 	PTU_REG_DBG_FORCE_FRAME,
886 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 20 };
887 
888 static struct block_defs block_dmae_defs = {
889 	"dmae", { true, true }, false, 0,
890 	{ DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP },
891 	DMAE_REG_DBG_SELECT, DMAE_REG_DBG_DWORD_ENABLE,
892 	DMAE_REG_DBG_SHIFT, DMAE_REG_DBG_FORCE_VALID,
893 	DMAE_REG_DBG_FORCE_FRAME,
894 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 28 };
895 
896 static struct block_defs block_tcm_defs = {
897 	"tcm", { true, true }, true, DBG_TSTORM_ID,
898 	{ DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT },
899 	TCM_REG_DBG_SELECT, TCM_REG_DBG_DWORD_ENABLE,
900 	TCM_REG_DBG_SHIFT, TCM_REG_DBG_FORCE_VALID,
901 	TCM_REG_DBG_FORCE_FRAME,
902 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 5 };
903 
904 static struct block_defs block_mcm_defs = {
905 	"mcm", { true, true }, true, DBG_MSTORM_ID,
906 	{ DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM },
907 	MCM_REG_DBG_SELECT, MCM_REG_DBG_DWORD_ENABLE,
908 	MCM_REG_DBG_SHIFT, MCM_REG_DBG_FORCE_VALID,
909 	MCM_REG_DBG_FORCE_FRAME,
910 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 3 };
911 
912 static struct block_defs block_ucm_defs = {
913 	"ucm", { true, true }, true, DBG_USTORM_ID,
914 	{ DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU },
915 	UCM_REG_DBG_SELECT, UCM_REG_DBG_DWORD_ENABLE,
916 	UCM_REG_DBG_SHIFT, UCM_REG_DBG_FORCE_VALID,
917 	UCM_REG_DBG_FORCE_FRAME,
918 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 8 };
919 
920 static struct block_defs block_xcm_defs = {
921 	"xcm", { true, true }, true, DBG_XSTORM_ID,
922 	{ DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX },
923 	XCM_REG_DBG_SELECT, XCM_REG_DBG_DWORD_ENABLE,
924 	XCM_REG_DBG_SHIFT, XCM_REG_DBG_FORCE_VALID,
925 	XCM_REG_DBG_FORCE_FRAME,
926 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 19 };
927 
928 static struct block_defs block_ycm_defs = {
929 	"ycm", { true, true }, true, DBG_YSTORM_ID,
930 	{ DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY },
931 	YCM_REG_DBG_SELECT, YCM_REG_DBG_DWORD_ENABLE,
932 	YCM_REG_DBG_SHIFT, YCM_REG_DBG_FORCE_VALID,
933 	YCM_REG_DBG_FORCE_FRAME,
934 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 5 };
935 
936 static struct block_defs block_pcm_defs = {
937 	"pcm", { true, true }, true, DBG_PSTORM_ID,
938 	{ DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS },
939 	PCM_REG_DBG_SELECT, PCM_REG_DBG_DWORD_ENABLE,
940 	PCM_REG_DBG_SHIFT, PCM_REG_DBG_FORCE_VALID,
941 	PCM_REG_DBG_FORCE_FRAME,
942 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 4 };
943 
944 static struct block_defs block_qm_defs = {
945 	"qm", { true, true }, false, 0,
946 	{ DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCQ },
947 	QM_REG_DBG_SELECT, QM_REG_DBG_DWORD_ENABLE,
948 	QM_REG_DBG_SHIFT, QM_REG_DBG_FORCE_VALID,
949 	QM_REG_DBG_FORCE_FRAME,
950 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 16 };
951 
952 static struct block_defs block_tm_defs = {
953 	"tm", { true, true }, false, 0,
954 	{ DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS },
955 	TM_REG_DBG_SELECT, TM_REG_DBG_DWORD_ENABLE,
956 	TM_REG_DBG_SHIFT, TM_REG_DBG_FORCE_VALID,
957 	TM_REG_DBG_FORCE_FRAME,
958 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 17 };
959 
960 static struct block_defs block_dorq_defs = {
961 	"dorq", { true, true }, false, 0,
962 	{ DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY },
963 	DORQ_REG_DBG_SELECT, DORQ_REG_DBG_DWORD_ENABLE,
964 	DORQ_REG_DBG_SHIFT, DORQ_REG_DBG_FORCE_VALID,
965 	DORQ_REG_DBG_FORCE_FRAME,
966 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 18 };
967 
968 static struct block_defs block_brb_defs = {
969 	"brb", { true, true }, false, 0,
970 	{ DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCR },
971 	BRB_REG_DBG_SELECT, BRB_REG_DBG_DWORD_ENABLE,
972 	BRB_REG_DBG_SHIFT, BRB_REG_DBG_FORCE_VALID,
973 	BRB_REG_DBG_FORCE_FRAME,
974 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 0 };
975 
976 static struct block_defs block_src_defs = {
977 	"src", { true, true }, false, 0,
978 	{ DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF },
979 	SRC_REG_DBG_SELECT, SRC_REG_DBG_DWORD_ENABLE,
980 	SRC_REG_DBG_SHIFT, SRC_REG_DBG_FORCE_VALID,
981 	SRC_REG_DBG_FORCE_FRAME,
982 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 2 };
983 
984 static struct block_defs block_prs_defs = {
985 	"prs", { true, true }, false, 0,
986 	{ DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCR },
987 	PRS_REG_DBG_SELECT, PRS_REG_DBG_DWORD_ENABLE,
988 	PRS_REG_DBG_SHIFT, PRS_REG_DBG_FORCE_VALID,
989 	PRS_REG_DBG_FORCE_FRAME,
990 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 1 };
991 
992 static struct block_defs block_tsdm_defs = {
993 	"tsdm", { true, true }, true, DBG_TSTORM_ID,
994 	{ DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT },
995 	TSDM_REG_DBG_SELECT, TSDM_REG_DBG_DWORD_ENABLE,
996 	TSDM_REG_DBG_SHIFT, TSDM_REG_DBG_FORCE_VALID,
997 	TSDM_REG_DBG_FORCE_FRAME,
998 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 3 };
999 
1000 static struct block_defs block_msdm_defs = {
1001 	"msdm", { true, true }, true, DBG_MSTORM_ID,
1002 	{ DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM },
1003 	MSDM_REG_DBG_SELECT, MSDM_REG_DBG_DWORD_ENABLE,
1004 	MSDM_REG_DBG_SHIFT, MSDM_REG_DBG_FORCE_VALID,
1005 	MSDM_REG_DBG_FORCE_FRAME,
1006 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 6 };
1007 
1008 static struct block_defs block_usdm_defs = {
1009 	"usdm", { true, true }, true, DBG_USTORM_ID,
1010 	{ DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU },
1011 	USDM_REG_DBG_SELECT, USDM_REG_DBG_DWORD_ENABLE,
1012 	USDM_REG_DBG_SHIFT, USDM_REG_DBG_FORCE_VALID,
1013 	USDM_REG_DBG_FORCE_FRAME,
1014 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 7
1015 	};
1016 static struct block_defs block_xsdm_defs = {
1017 	"xsdm", { true, true }, true, DBG_XSTORM_ID,
1018 	{ DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX },
1019 	XSDM_REG_DBG_SELECT, XSDM_REG_DBG_DWORD_ENABLE,
1020 	XSDM_REG_DBG_SHIFT, XSDM_REG_DBG_FORCE_VALID,
1021 	XSDM_REG_DBG_FORCE_FRAME,
1022 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 20 };
1023 
1024 static struct block_defs block_ysdm_defs = {
1025 	"ysdm", { true, true }, true, DBG_YSTORM_ID,
1026 	{ DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY },
1027 	YSDM_REG_DBG_SELECT, YSDM_REG_DBG_DWORD_ENABLE,
1028 	YSDM_REG_DBG_SHIFT, YSDM_REG_DBG_FORCE_VALID,
1029 	YSDM_REG_DBG_FORCE_FRAME,
1030 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 8 };
1031 
1032 static struct block_defs block_psdm_defs = {
1033 	"psdm", { true, true }, true, DBG_PSTORM_ID,
1034 	{ DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS },
1035 	PSDM_REG_DBG_SELECT, PSDM_REG_DBG_DWORD_ENABLE,
1036 	PSDM_REG_DBG_SHIFT, PSDM_REG_DBG_FORCE_VALID,
1037 	PSDM_REG_DBG_FORCE_FRAME,
1038 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 7 };
1039 
1040 static struct block_defs block_tsem_defs = {
1041 	"tsem", { true, true }, true, DBG_TSTORM_ID,
1042 	{ DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT },
1043 	TSEM_REG_DBG_SELECT, TSEM_REG_DBG_DWORD_ENABLE,
1044 	TSEM_REG_DBG_SHIFT, TSEM_REG_DBG_FORCE_VALID,
1045 	TSEM_REG_DBG_FORCE_FRAME,
1046 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 4 };
1047 
1048 static struct block_defs block_msem_defs = {
1049 	"msem", { true, true }, true, DBG_MSTORM_ID,
1050 	{ DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM },
1051 	MSEM_REG_DBG_SELECT, MSEM_REG_DBG_DWORD_ENABLE,
1052 	MSEM_REG_DBG_SHIFT, MSEM_REG_DBG_FORCE_VALID,
1053 	MSEM_REG_DBG_FORCE_FRAME,
1054 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 9 };
1055 
1056 static struct block_defs block_usem_defs = {
1057 	"usem", { true, true }, true, DBG_USTORM_ID,
1058 	{ DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU },
1059 	USEM_REG_DBG_SELECT, USEM_REG_DBG_DWORD_ENABLE,
1060 	USEM_REG_DBG_SHIFT, USEM_REG_DBG_FORCE_VALID,
1061 	USEM_REG_DBG_FORCE_FRAME,
1062 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 9 };
1063 
1064 static struct block_defs block_xsem_defs = {
1065 	"xsem", { true, true }, true, DBG_XSTORM_ID,
1066 	{ DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX },
1067 	XSEM_REG_DBG_SELECT, XSEM_REG_DBG_DWORD_ENABLE,
1068 	XSEM_REG_DBG_SHIFT, XSEM_REG_DBG_FORCE_VALID,
1069 	XSEM_REG_DBG_FORCE_FRAME,
1070 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 21 };
1071 
1072 static struct block_defs block_ysem_defs = {
1073 	"ysem", { true, true }, true, DBG_YSTORM_ID,
1074 	{ DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY },
1075 	YSEM_REG_DBG_SELECT, YSEM_REG_DBG_DWORD_ENABLE,
1076 	YSEM_REG_DBG_SHIFT, YSEM_REG_DBG_FORCE_VALID,
1077 	YSEM_REG_DBG_FORCE_FRAME,
1078 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 11 };
1079 
1080 static struct block_defs block_psem_defs = {
1081 	"psem", { true, true }, true, DBG_PSTORM_ID,
1082 	{ DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS },
1083 	PSEM_REG_DBG_SELECT, PSEM_REG_DBG_DWORD_ENABLE,
1084 	PSEM_REG_DBG_SHIFT, PSEM_REG_DBG_FORCE_VALID,
1085 	PSEM_REG_DBG_FORCE_FRAME,
1086 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 10 };
1087 
1088 static struct block_defs block_rss_defs = {
1089 	"rss", { true, true }, false, 0,
1090 	{ DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT },
1091 	RSS_REG_DBG_SELECT, RSS_REG_DBG_DWORD_ENABLE,
1092 	RSS_REG_DBG_SHIFT, RSS_REG_DBG_FORCE_VALID,
1093 	RSS_REG_DBG_FORCE_FRAME,
1094 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 18 };
1095 
1096 static struct block_defs block_tmld_defs = {
1097 	"tmld", { true, true }, false, 0,
1098 	{ DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM },
1099 	TMLD_REG_DBG_SELECT, TMLD_REG_DBG_DWORD_ENABLE,
1100 	TMLD_REG_DBG_SHIFT, TMLD_REG_DBG_FORCE_VALID,
1101 	TMLD_REG_DBG_FORCE_FRAME,
1102 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 13 };
1103 
1104 static struct block_defs block_muld_defs = {
1105 	"muld", { true, true }, false, 0,
1106 	{ DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU },
1107 	MULD_REG_DBG_SELECT, MULD_REG_DBG_DWORD_ENABLE,
1108 	MULD_REG_DBG_SHIFT, MULD_REG_DBG_FORCE_VALID,
1109 	MULD_REG_DBG_FORCE_FRAME,
1110 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 14 };
1111 
1112 static struct block_defs block_yuld_defs = {
1113 	"yuld", { true, true }, false, 0,
1114 	{ DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU },
1115 	YULD_REG_DBG_SELECT_BB_K2, YULD_REG_DBG_DWORD_ENABLE_BB_K2,
1116 	YULD_REG_DBG_SHIFT_BB_K2, YULD_REG_DBG_FORCE_VALID_BB_K2,
1117 	YULD_REG_DBG_FORCE_FRAME_BB_K2,
1118 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 15 };
1119 
1120 static struct block_defs block_xyld_defs = {
1121 	"xyld", { true, true }, false, 0,
1122 	{ DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX },
1123 	XYLD_REG_DBG_SELECT, XYLD_REG_DBG_DWORD_ENABLE,
1124 	XYLD_REG_DBG_SHIFT, XYLD_REG_DBG_FORCE_VALID,
1125 	XYLD_REG_DBG_FORCE_FRAME,
1126 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 12 };
1127 
1128 static struct block_defs block_prm_defs = {
1129 	"prm", { true, true }, false, 0,
1130 	{ DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM },
1131 	PRM_REG_DBG_SELECT, PRM_REG_DBG_DWORD_ENABLE,
1132 	PRM_REG_DBG_SHIFT, PRM_REG_DBG_FORCE_VALID,
1133 	PRM_REG_DBG_FORCE_FRAME,
1134 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 21 };
1135 
1136 static struct block_defs block_pbf_pb1_defs = {
1137 	"pbf_pb1", { true, true }, false, 0,
1138 	{ DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCV },
1139 	PBF_PB1_REG_DBG_SELECT, PBF_PB1_REG_DBG_DWORD_ENABLE,
1140 	PBF_PB1_REG_DBG_SHIFT, PBF_PB1_REG_DBG_FORCE_VALID,
1141 	PBF_PB1_REG_DBG_FORCE_FRAME,
1142 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 11 };
1143 
1144 static struct block_defs block_pbf_pb2_defs = {
1145 	"pbf_pb2", { true, true }, false, 0,
1146 	{ DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCV },
1147 	PBF_PB2_REG_DBG_SELECT, PBF_PB2_REG_DBG_DWORD_ENABLE,
1148 	PBF_PB2_REG_DBG_SHIFT, PBF_PB2_REG_DBG_FORCE_VALID,
1149 	PBF_PB2_REG_DBG_FORCE_FRAME,
1150 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 12 };
1151 
1152 static struct block_defs block_rpb_defs = {
1153 	"rpb", { true, true }, false, 0,
1154 	{ DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM },
1155 	RPB_REG_DBG_SELECT, RPB_REG_DBG_DWORD_ENABLE,
1156 	RPB_REG_DBG_SHIFT, RPB_REG_DBG_FORCE_VALID,
1157 	RPB_REG_DBG_FORCE_FRAME,
1158 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 13 };
1159 
1160 static struct block_defs block_btb_defs = {
1161 	"btb", { true, true }, false, 0,
1162 	{ DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCV },
1163 	BTB_REG_DBG_SELECT, BTB_REG_DBG_DWORD_ENABLE,
1164 	BTB_REG_DBG_SHIFT, BTB_REG_DBG_FORCE_VALID,
1165 	BTB_REG_DBG_FORCE_FRAME,
1166 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 10 };
1167 
1168 static struct block_defs block_pbf_defs = {
1169 	"pbf", { true, true }, false, 0,
1170 	{ DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCV },
1171 	PBF_REG_DBG_SELECT, PBF_REG_DBG_DWORD_ENABLE,
1172 	PBF_REG_DBG_SHIFT, PBF_REG_DBG_FORCE_VALID,
1173 	PBF_REG_DBG_FORCE_FRAME,
1174 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 15 };
1175 
1176 static struct block_defs block_rdif_defs = {
1177 	"rdif", { true, true }, false, 0,
1178 	{ DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM },
1179 	RDIF_REG_DBG_SELECT, RDIF_REG_DBG_DWORD_ENABLE,
1180 	RDIF_REG_DBG_SHIFT, RDIF_REG_DBG_FORCE_VALID,
1181 	RDIF_REG_DBG_FORCE_FRAME,
1182 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 16 };
1183 
1184 static struct block_defs block_tdif_defs = {
1185 	"tdif", { true, true }, false, 0,
1186 	{ DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS },
1187 	TDIF_REG_DBG_SELECT, TDIF_REG_DBG_DWORD_ENABLE,
1188 	TDIF_REG_DBG_SHIFT, TDIF_REG_DBG_FORCE_VALID,
1189 	TDIF_REG_DBG_FORCE_FRAME,
1190 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 17 };
1191 
1192 static struct block_defs block_cdu_defs = {
1193 	"cdu", { true, true }, false, 0,
1194 	{ DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF },
1195 	CDU_REG_DBG_SELECT, CDU_REG_DBG_DWORD_ENABLE,
1196 	CDU_REG_DBG_SHIFT, CDU_REG_DBG_FORCE_VALID,
1197 	CDU_REG_DBG_FORCE_FRAME,
1198 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 23 };
1199 
1200 static struct block_defs block_ccfc_defs = {
1201 	"ccfc", { true, true }, false, 0,
1202 	{ DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF },
1203 	CCFC_REG_DBG_SELECT, CCFC_REG_DBG_DWORD_ENABLE,
1204 	CCFC_REG_DBG_SHIFT, CCFC_REG_DBG_FORCE_VALID,
1205 	CCFC_REG_DBG_FORCE_FRAME,
1206 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 24 };
1207 
1208 static struct block_defs block_tcfc_defs = {
1209 	"tcfc", { true, true }, false, 0,
1210 	{ DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF },
1211 	TCFC_REG_DBG_SELECT, TCFC_REG_DBG_DWORD_ENABLE,
1212 	TCFC_REG_DBG_SHIFT, TCFC_REG_DBG_FORCE_VALID,
1213 	TCFC_REG_DBG_FORCE_FRAME,
1214 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 25 };
1215 
1216 static struct block_defs block_igu_defs = {
1217 	"igu", { true, true }, false, 0,
1218 	{ DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP },
1219 	IGU_REG_DBG_SELECT, IGU_REG_DBG_DWORD_ENABLE,
1220 	IGU_REG_DBG_SHIFT, IGU_REG_DBG_FORCE_VALID,
1221 	IGU_REG_DBG_FORCE_FRAME,
1222 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 27 };
1223 
1224 static struct block_defs block_cau_defs = {
1225 	"cau", { true, true }, false, 0,
1226 	{ DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP },
1227 	CAU_REG_DBG_SELECT, CAU_REG_DBG_DWORD_ENABLE,
1228 	CAU_REG_DBG_SHIFT, CAU_REG_DBG_FORCE_VALID,
1229 	CAU_REG_DBG_FORCE_FRAME,
1230 	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 19 };
1231 
1232 static struct block_defs block_umac_defs = {
1233 	"umac", { false, true }, false, 0,
1234 	{ MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCZ },
1235 	UMAC_REG_DBG_SELECT_K2_E5, UMAC_REG_DBG_DWORD_ENABLE_K2_E5,
1236 	UMAC_REG_DBG_SHIFT_K2_E5, UMAC_REG_DBG_FORCE_VALID_K2_E5,
1237 	UMAC_REG_DBG_FORCE_FRAME_K2_E5,
1238 	true, false, DBG_RESET_REG_MISCS_PL_HV, 6 };
1239 
1240 static struct block_defs block_xmac_defs = {
1241 	"xmac", { false, false }, false, 0,
1242 	{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
1243 	0, 0, 0, 0, 0,
1244 	false, false, MAX_DBG_RESET_REGS, 0	};
1245 
1246 static struct block_defs block_dbg_defs = {
1247 	"dbg", { false, false }, false, 0,
1248 	{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
1249 	0, 0, 0, 0, 0,
1250 	true, true, DBG_RESET_REG_MISC_PL_PDA_VAUX, 3 };
1251 
1252 static struct block_defs block_nig_defs = {
1253 	"nig", { true, true }, false, 0,
1254 	{ DBG_BUS_CLIENT_RBCN, DBG_BUS_CLIENT_RBCN },
1255 	NIG_REG_DBG_SELECT, NIG_REG_DBG_DWORD_ENABLE,
1256 	NIG_REG_DBG_SHIFT, NIG_REG_DBG_FORCE_VALID,
1257 	NIG_REG_DBG_FORCE_FRAME,
1258 	true, true, DBG_RESET_REG_MISC_PL_PDA_VAUX, 0 };
1259 
1260 static struct block_defs block_wol_defs = {
1261 	"wol", { false, true }, false, 0,
1262 	{ MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCZ },
1263 	WOL_REG_DBG_SELECT_K2_E5, WOL_REG_DBG_DWORD_ENABLE_K2_E5,
1264 	WOL_REG_DBG_SHIFT_K2_E5, WOL_REG_DBG_FORCE_VALID_K2_E5,
1265 	WOL_REG_DBG_FORCE_FRAME_K2_E5,
1266 	true, true, DBG_RESET_REG_MISC_PL_PDA_VAUX, 7 };
1267 
1268 static struct block_defs block_bmbn_defs = {
1269 	"bmbn", { false, true }, false, 0,
1270 	{ MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCB },
1271 	BMBN_REG_DBG_SELECT_K2_E5, BMBN_REG_DBG_DWORD_ENABLE_K2_E5,
1272 	BMBN_REG_DBG_SHIFT_K2_E5, BMBN_REG_DBG_FORCE_VALID_K2_E5,
1273 	BMBN_REG_DBG_FORCE_FRAME_K2_E5,
1274 	false, false, MAX_DBG_RESET_REGS, 0 };
1275 
1276 static struct block_defs block_ipc_defs = {
1277 	"ipc", { false, false }, false, 0,
1278 	{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
1279 	0, 0, 0, 0, 0,
1280 	true, false, DBG_RESET_REG_MISCS_PL_UA, 8 };
1281 
1282 static struct block_defs block_nwm_defs = {
1283 	"nwm", { false, true }, false, 0,
1284 	{ MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW },
1285 	NWM_REG_DBG_SELECT_K2_E5, NWM_REG_DBG_DWORD_ENABLE_K2_E5,
1286 	NWM_REG_DBG_SHIFT_K2_E5, NWM_REG_DBG_FORCE_VALID_K2_E5,
1287 	NWM_REG_DBG_FORCE_FRAME_K2_E5,
1288 	true, false, DBG_RESET_REG_MISCS_PL_HV_2, 0 };
1289 
1290 static struct block_defs block_nws_defs = {
1291 	"nws", { false, true }, false, 0,
1292 	{ MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW },
1293 	NWS_REG_DBG_SELECT_K2_E5, NWS_REG_DBG_DWORD_ENABLE_K2_E5,
1294 	NWS_REG_DBG_SHIFT_K2_E5, NWS_REG_DBG_FORCE_VALID_K2_E5,
1295 	NWS_REG_DBG_FORCE_FRAME_K2_E5,
1296 	true, false, DBG_RESET_REG_MISCS_PL_HV, 12 };
1297 
1298 static struct block_defs block_ms_defs = {
1299 	"ms", { false, true }, false, 0,
1300 	{ MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCZ },
1301 	MS_REG_DBG_SELECT_K2_E5, MS_REG_DBG_DWORD_ENABLE_K2_E5,
1302 	MS_REG_DBG_SHIFT_K2_E5, MS_REG_DBG_FORCE_VALID_K2_E5,
1303 	MS_REG_DBG_FORCE_FRAME_K2_E5,
1304 	true, false, DBG_RESET_REG_MISCS_PL_HV, 13 };
1305 
1306 static struct block_defs block_phy_pcie_defs = {
1307 	"phy_pcie", { false, true }, false, 0,
1308 	{ MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH },
1309 	PCIE_REG_DBG_COMMON_SELECT_K2_E5, PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2_E5,
1310 	PCIE_REG_DBG_COMMON_SHIFT_K2_E5, PCIE_REG_DBG_COMMON_FORCE_VALID_K2_E5,
1311 	PCIE_REG_DBG_COMMON_FORCE_FRAME_K2_E5,
1312 	false, false, MAX_DBG_RESET_REGS, 0 };
1313 
1314 static struct block_defs block_led_defs = {
1315 	"led", { false, false }, false, 0,
1316 	{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
1317 	0, 0, 0, 0, 0,
1318 	true, false, DBG_RESET_REG_MISCS_PL_HV, 14 };
1319 
1320 static struct block_defs block_avs_wrap_defs = {
1321 	"avs_wrap", { false, false }, false, 0,
1322 	{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
1323 	0, 0, 0, 0, 0,
1324 	true, false, DBG_RESET_REG_MISCS_PL_UA, 11 };
1325 
1326 static struct block_defs block_rgfs_defs = {
1327 	"rgfs", { false, false }, false, 0,
1328 	{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
1329 	0, 0, 0, 0, 0,
1330 	false, false, MAX_DBG_RESET_REGS, 0 };
1331 
1332 static struct block_defs block_rgsrc_defs = {
1333 	"rgsrc", { false, false }, false, 0,
1334 	{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
1335 	0, 0, 0, 0, 0,
1336 	false, false, MAX_DBG_RESET_REGS, 0 };
1337 
1338 static struct block_defs block_tgfs_defs = {
1339 	"tgfs", { false, false }, false, 0,
1340 	{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
1341 	0, 0, 0, 0, 0,
1342 	false, false, MAX_DBG_RESET_REGS, 0 };
1343 
1344 static struct block_defs block_tgsrc_defs = {
1345 	"tgsrc", { false, false }, false, 0,
1346 	{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
1347 	0, 0, 0, 0, 0,
1348 	false, false, MAX_DBG_RESET_REGS, 0 };
1349 
1350 static struct block_defs block_ptld_defs = {
1351 	"ptld", { false, false }, false, 0,
1352 	{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
1353 	0, 0, 0, 0, 0,
1354 	false, false, MAX_DBG_RESET_REGS, 0 };
1355 
1356 static struct block_defs block_ypld_defs = {
1357 	"ypld", { false, false }, false, 0,
1358 	{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
1359 	0, 0, 0, 0, 0,
1360 	false, false, MAX_DBG_RESET_REGS, 0 };
1361 
1362 static struct block_defs block_misc_aeu_defs = {
1363 	"misc_aeu", { false, false }, false, 0,
1364 	{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
1365 	0, 0, 0, 0, 0,
1366 	false, false, MAX_DBG_RESET_REGS, 0 };
1367 
1368 static struct block_defs block_bar0_map_defs = {
1369 	"bar0_map", { false, false }, false, 0,
1370 	{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
1371 	0, 0, 0, 0, 0,
1372 	false, false, MAX_DBG_RESET_REGS, 0 };
1373 
1374 
1375 static struct block_defs* s_block_defs[MAX_BLOCK_ID] = {
1376 	&block_grc_defs,
1377  	&block_miscs_defs,
1378  	&block_misc_defs,
1379  	&block_dbu_defs,
1380  	&block_pglue_b_defs,
1381  	&block_cnig_defs,
1382  	&block_cpmu_defs,
1383  	&block_ncsi_defs,
1384  	&block_opte_defs,
1385  	&block_bmb_defs,
1386  	&block_pcie_defs,
1387  	&block_mcp_defs,
1388  	&block_mcp2_defs,
1389  	&block_pswhst_defs,
1390  	&block_pswhst2_defs,
1391  	&block_pswrd_defs,
1392  	&block_pswrd2_defs,
1393  	&block_pswwr_defs,
1394  	&block_pswwr2_defs,
1395  	&block_pswrq_defs,
1396  	&block_pswrq2_defs,
1397  	&block_pglcs_defs,
1398  	&block_dmae_defs,
1399  	&block_ptu_defs,
1400  	&block_tcm_defs,
1401  	&block_mcm_defs,
1402  	&block_ucm_defs,
1403  	&block_xcm_defs,
1404  	&block_ycm_defs,
1405  	&block_pcm_defs,
1406  	&block_qm_defs,
1407  	&block_tm_defs,
1408  	&block_dorq_defs,
1409  	&block_brb_defs,
1410  	&block_src_defs,
1411  	&block_prs_defs,
1412  	&block_tsdm_defs,
1413  	&block_msdm_defs,
1414  	&block_usdm_defs,
1415  	&block_xsdm_defs,
1416  	&block_ysdm_defs,
1417  	&block_psdm_defs,
1418  	&block_tsem_defs,
1419  	&block_msem_defs,
1420  	&block_usem_defs,
1421  	&block_xsem_defs,
1422  	&block_ysem_defs,
1423  	&block_psem_defs,
1424  	&block_rss_defs,
1425  	&block_tmld_defs,
1426  	&block_muld_defs,
1427  	&block_yuld_defs,
1428  	&block_xyld_defs,
1429  	&block_ptld_defs,
1430  	&block_ypld_defs,
1431  	&block_prm_defs,
1432  	&block_pbf_pb1_defs,
1433  	&block_pbf_pb2_defs,
1434  	&block_rpb_defs,
1435  	&block_btb_defs,
1436  	&block_pbf_defs,
1437  	&block_rdif_defs,
1438  	&block_tdif_defs,
1439  	&block_cdu_defs,
1440  	&block_ccfc_defs,
1441  	&block_tcfc_defs,
1442  	&block_igu_defs,
1443  	&block_cau_defs,
1444  	&block_rgfs_defs,
1445  	&block_rgsrc_defs,
1446  	&block_tgfs_defs,
1447  	&block_tgsrc_defs,
1448  	&block_umac_defs,
1449  	&block_xmac_defs,
1450  	&block_dbg_defs,
1451  	&block_nig_defs,
1452  	&block_wol_defs,
1453  	&block_bmbn_defs,
1454  	&block_ipc_defs,
1455  	&block_nwm_defs,
1456  	&block_nws_defs,
1457  	&block_ms_defs,
1458  	&block_phy_pcie_defs,
1459  	&block_led_defs,
1460  	&block_avs_wrap_defs,
1461  	&block_misc_aeu_defs,
1462  	&block_bar0_map_defs,
1463 
1464 };
1465 
1466 
1467 /* Constraint operation types */
1468 static struct dbg_bus_constraint_op_defs s_constraint_op_defs[] = {
1469 
1470 	/* DBG_BUS_CONSTRAINT_OP_EQ */
1471 	{ 0, false },
1472 
1473 	/* DBG_BUS_CONSTRAINT_OP_NE */
1474 	{ 5, false },
1475 
1476 	/* DBG_BUS_CONSTRAINT_OP_LT */
1477 	{ 1, false },
1478 
1479 	/* DBG_BUS_CONSTRAINT_OP_LTC */
1480 	{ 1, true },
1481 
1482 	/* DBG_BUS_CONSTRAINT_OP_LE */
1483 	{ 2, false },
1484 
1485 	/* DBG_BUS_CONSTRAINT_OP_LEC */
1486 	{ 2, true },
1487 
1488 	/* DBG_BUS_CONSTRAINT_OP_GT */
1489 	{ 4, false },
1490 
1491 	/* DBG_BUS_CONSTRAINT_OP_GTC */
1492 	{ 4, true },
1493 
1494 	/* DBG_BUS_CONSTRAINT_OP_GE */
1495 	{ 3, false },
1496 
1497 	/* DBG_BUS_CONSTRAINT_OP_GEC */
1498 	{ 3, true }
1499 };
1500 
1501 static const char* s_dbg_target_names[] = {
1502 
1503 	/* DBG_BUS_TARGET_ID_INT_BUF */
1504 	"int-buf",
1505 
1506 	/* DBG_BUS_TARGET_ID_NIG */
1507 	"nw",
1508 
1509 	/* DBG_BUS_TARGET_ID_PCI */
1510 	"pci-buf"
1511 };
1512 
1513 static struct storm_mode_defs s_storm_mode_defs[] = {
1514 
1515 	/* DBG_BUS_STORM_MODE_PRINTF */
1516 	{ "printf", true, 0 },
1517 
1518 	/* DBG_BUS_STORM_MODE_PRAM_ADDR */
1519 	{ "pram_addr", true, 1 },
1520 
1521 	/* DBG_BUS_STORM_MODE_DRA_RW */
1522 	{ "dra_rw", true, 2 },
1523 
1524 	/* DBG_BUS_STORM_MODE_DRA_W */
1525 	{ "dra_w", true, 3 },
1526 
1527 	/* DBG_BUS_STORM_MODE_LD_ST_ADDR */
1528 	{ "ld_st_addr", true, 4 },
1529 
1530 	/* DBG_BUS_STORM_MODE_DRA_FSM */
1531 	{ "dra_fsm", true, 5 },
1532 
1533 	/* DBG_BUS_STORM_MODE_RH */
1534 	{ "rh", true, 6 },
1535 
1536 	/* DBG_BUS_STORM_MODE_FOC */
1537 	{ "foc", false, 1 },
1538 
1539 	/* DBG_BUS_STORM_MODE_EXT_STORE */
1540 	{ "ext_store", false, 3 }
1541 };
1542 
1543 static struct platform_defs s_platform_defs[] = {
1544 
1545 	/* PLATFORM_ASIC */
1546 	{ "asic", 1 },
1547 
1548 	/* PLATFORM_EMUL_FULL */
1549 	{ "emul_full", 2000 },
1550 
1551 	/* PLATFORM_EMUL_REDUCED */
1552 	{ "emul_reduced", 2000 },
1553 
1554 	/* PLATFORM_FPGA */
1555 	{ "fpga", 200 }
1556 };
1557 
1558 static struct grc_param_defs s_grc_param_defs[] = {
1559 
1560 	/* DBG_GRC_PARAM_DUMP_TSTORM */
1561 	{ { 1, 1 }, 0, 1, false, 1, 1 },
1562 
1563 	/* DBG_GRC_PARAM_DUMP_MSTORM */
1564 	{ { 1, 1 }, 0, 1, false, 1, 1 },
1565 
1566 	/* DBG_GRC_PARAM_DUMP_USTORM */
1567 	{ { 1, 1 }, 0, 1, false, 1, 1 },
1568 
1569 	/* DBG_GRC_PARAM_DUMP_XSTORM */
1570 	{ { 1, 1 }, 0, 1, false, 1, 1 },
1571 
1572 	/* DBG_GRC_PARAM_DUMP_YSTORM */
1573 	{ { 1, 1 }, 0, 1, false, 1, 1 },
1574 
1575 	/* DBG_GRC_PARAM_DUMP_PSTORM */
1576 	{ { 1, 1 }, 0, 1, false, 1, 1 },
1577 
1578 	/* DBG_GRC_PARAM_DUMP_REGS */
1579 	{ { 1, 1 }, 0, 1, false, 0, 1 },
1580 
1581 	/* DBG_GRC_PARAM_DUMP_RAM */
1582 	{ { 1, 1 }, 0, 1, false, 0, 1 },
1583 
1584 	/* DBG_GRC_PARAM_DUMP_PBUF */
1585 	{ { 1, 1 }, 0, 1, false, 0, 1 },
1586 
1587 	/* DBG_GRC_PARAM_DUMP_IOR */
1588 	{ { 0, 0 }, 0, 1, false, 0, 1 },
1589 
1590 	/* DBG_GRC_PARAM_DUMP_VFC */
1591 	{ { 0, 0 }, 0, 1, false, 0, 1 },
1592 
1593 	/* DBG_GRC_PARAM_DUMP_CM_CTX */
1594 	{ { 1, 1 }, 0, 1, false, 0, 1 },
1595 
1596 	/* DBG_GRC_PARAM_DUMP_ILT */
1597 	{ { 1, 1 }, 0, 1, false, 0, 1 },
1598 
1599 	/* DBG_GRC_PARAM_DUMP_RSS */
1600 	{ { 1, 1 }, 0, 1, false, 0, 1 },
1601 
1602 	/* DBG_GRC_PARAM_DUMP_CAU */
1603 	{ { 1, 1 }, 0, 1, false, 0, 1 },
1604 
1605 	/* DBG_GRC_PARAM_DUMP_QM */
1606 	{ { 1, 1 }, 0, 1, false, 0, 1 },
1607 
1608 	/* DBG_GRC_PARAM_DUMP_MCP */
1609 	{ { 1, 1 }, 0, 1, false, 0, 1 },
1610 
1611 	/* DBG_GRC_PARAM_RESERVED */
1612 	{ { 1, 1 }, 0, 1, false, 0, 1 },
1613 
1614 	/* DBG_GRC_PARAM_DUMP_CFC */
1615 	{ { 1, 1 }, 0, 1, false, 0, 1 },
1616 
1617 	/* DBG_GRC_PARAM_DUMP_IGU */
1618 	{ { 1, 1 }, 0, 1, false, 0, 1 },
1619 
1620 	/* DBG_GRC_PARAM_DUMP_BRB */
1621 	{ { 0, 0 }, 0, 1, false, 0, 1 },
1622 
1623 	/* DBG_GRC_PARAM_DUMP_BTB */
1624 	{ { 0, 0 }, 0, 1, false, 0, 1 },
1625 
1626 	/* DBG_GRC_PARAM_DUMP_BMB */
1627 	{ { 0, 0 }, 0, 1, false, 0, 1 },
1628 
1629 	/* DBG_GRC_PARAM_DUMP_NIG */
1630 	{ { 1, 1 }, 0, 1, false, 0, 1 },
1631 
1632 	/* DBG_GRC_PARAM_DUMP_MULD */
1633 	{ { 1, 1 }, 0, 1, false, 0, 1 },
1634 
1635 	/* DBG_GRC_PARAM_DUMP_PRS */
1636 	{ { 1, 1 }, 0, 1, false, 0, 1 },
1637 
1638 	/* DBG_GRC_PARAM_DUMP_DMAE */
1639 	{ { 1, 1 }, 0, 1, false, 0, 1 },
1640 
1641 	/* DBG_GRC_PARAM_DUMP_TM */
1642 	{ { 1, 1 }, 0, 1, false, 0, 1 },
1643 
1644 	/* DBG_GRC_PARAM_DUMP_SDM */
1645 	{ { 1, 1 }, 0, 1, false, 0, 1 },
1646 
1647 	/* DBG_GRC_PARAM_DUMP_DIF */
1648 	{ { 1, 1 }, 0, 1, false, 0, 1 },
1649 
1650 	/* DBG_GRC_PARAM_DUMP_STATIC */
1651 	{ { 1, 1 }, 0, 1, false, 0, 1 },
1652 
1653 	/* DBG_GRC_PARAM_UNSTALL */
1654 	{ { 0, 0 }, 0, 1, false, 0, 0 },
1655 
1656 	/* DBG_GRC_PARAM_NUM_LCIDS */
1657 	{ { MAX_LCIDS, MAX_LCIDS }, 1, MAX_LCIDS, false, MAX_LCIDS, MAX_LCIDS },
1658 
1659 	/* DBG_GRC_PARAM_NUM_LTIDS */
1660 	{ { MAX_LTIDS, MAX_LTIDS }, 1, MAX_LTIDS, false, MAX_LTIDS, MAX_LTIDS },
1661 
1662 	/* DBG_GRC_PARAM_EXCLUDE_ALL */
1663 	{ { 0, 0 }, 0, 1, true, 0, 0 },
1664 
1665 	/* DBG_GRC_PARAM_CRASH */
1666 	{ { 0, 0 }, 0, 1, true, 0, 0 },
1667 
1668 	/* DBG_GRC_PARAM_PARITY_SAFE */
1669 	{ { 0, 0 }, 0, 1, false, 1, 0 },
1670 
1671 	/* DBG_GRC_PARAM_DUMP_CM */
1672 	{ { 1, 1 }, 0, 1, false, 0, 1 },
1673 
1674 	/* DBG_GRC_PARAM_DUMP_PHY */
1675 	{ { 1, 1 }, 0, 1, false, 0, 1 },
1676 
1677 	/* DBG_GRC_PARAM_NO_MCP */
1678 	{ { 0, 0 }, 0, 1, false, 0, 0 },
1679 
1680 	/* DBG_GRC_PARAM_NO_FW_VER */
1681 	{ { 0, 0 }, 0, 1, false, 0, 0 }
1682 };
1683 
1684 static struct rss_mem_defs s_rss_mem_defs[] = {
1685 	{ "rss_mem_cid", "rss_cid", 0,
1686 	{ 256, 320 },
1687 	{ 32, 32 } },
1688 
1689 	{ "rss_mem_key_msb", "rss_key", 1024,
1690 	{ 128, 208 },
1691 	{ 256, 256 } },
1692 
1693 	{ "rss_mem_key_lsb", "rss_key", 2048,
1694 	{ 128, 208 },
1695 	{ 64, 64 } },
1696 
1697 	{ "rss_mem_info", "rss_info", 3072,
1698 	{ 128, 208 },
1699 	{ 16, 16 } },
1700 
1701 	{ "rss_mem_ind", "rss_ind", 4096,
1702 	{ 16384, 26624 },
1703 	{ 16, 16 } }
1704 };
1705 
1706 static struct vfc_ram_defs s_vfc_ram_defs[] = {
1707 	{ "vfc_ram_tt1", "vfc_ram", 0, 512 },
1708 	{ "vfc_ram_mtt2", "vfc_ram", 512, 128 },
1709 	{ "vfc_ram_stt2", "vfc_ram", 640, 32 },
1710 	{ "vfc_ram_ro_vect", "vfc_ram", 672, 32 }
1711 };
1712 
1713 static struct big_ram_defs s_big_ram_defs[] = {
1714 	{ "BRB", MEM_GROUP_BRB_MEM, MEM_GROUP_BRB_RAM, DBG_GRC_PARAM_DUMP_BRB, BRB_REG_BIG_RAM_ADDRESS, BRB_REG_BIG_RAM_DATA,
1715 	  { 4800, 5632 } },
1716 
1717 	{ "BTB", MEM_GROUP_BTB_MEM, MEM_GROUP_BTB_RAM, DBG_GRC_PARAM_DUMP_BTB, BTB_REG_BIG_RAM_ADDRESS, BTB_REG_BIG_RAM_DATA,
1718 	  { 2880, 3680 } },
1719 
1720 	{ "BMB", MEM_GROUP_BMB_MEM, MEM_GROUP_BMB_RAM, DBG_GRC_PARAM_DUMP_BMB, BMB_REG_BIG_RAM_ADDRESS, BMB_REG_BIG_RAM_DATA,
1721 	  { 1152, 1152 } }
1722 };
1723 
1724 static struct reset_reg_defs s_reset_regs_defs[] = {
1725 
1726 	/* DBG_RESET_REG_MISCS_PL_UA */
1727 	{ MISCS_REG_RESET_PL_UA, 0x0, { true, true } },
1728 
1729 	/* DBG_RESET_REG_MISCS_PL_HV */
1730 	{ MISCS_REG_RESET_PL_HV, 0x0, { true, true } },
1731 
1732 	/* DBG_RESET_REG_MISCS_PL_HV_2 */
1733 	{ MISCS_REG_RESET_PL_HV_2_K2_E5, 0x0, { false, true } },
1734 
1735 	/* DBG_RESET_REG_MISC_PL_UA */
1736 	{ MISC_REG_RESET_PL_UA, 0x0, { true, true } },
1737 
1738 	/* DBG_RESET_REG_MISC_PL_HV */
1739 	{ MISC_REG_RESET_PL_HV, 0x0, { true, true } },
1740 
1741 	/* DBG_RESET_REG_MISC_PL_PDA_VMAIN_1 */
1742 	{ MISC_REG_RESET_PL_PDA_VMAIN_1, 0x4404040, { true, true } },
1743 
1744 	/* DBG_RESET_REG_MISC_PL_PDA_VMAIN_2 */
1745 	{ MISC_REG_RESET_PL_PDA_VMAIN_2, 0x7c00007, { true, true } },
1746 
1747 	/* DBG_RESET_REG_MISC_PL_PDA_VAUX */
1748 	{ MISC_REG_RESET_PL_PDA_VAUX, 0x2, { true, true } },
1749 };
1750 
1751 static struct phy_defs s_phy_defs[] = {
1752 	{ "nw_phy", NWS_REG_NWS_CMU_K2_E5, PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0_K2_E5, PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8_K2_E5, PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0_K2_E5, PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8_K2_E5 },
1753 	{ "sgmii_phy", MS_REG_MS_CMU_K2_E5, PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132_K2_E5, PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133_K2_E5, PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130_K2_E5, PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131_K2_E5 },
1754 	{ "pcie_phy0", PHY_PCIE_REG_PHY0_K2_E5, PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2_E5, PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2_E5, PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2_E5, PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2_E5 },
1755 	{ "pcie_phy1", PHY_PCIE_REG_PHY1_K2_E5, PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2_E5, PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2_E5, PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2_E5, PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2_E5 },
1756 };
1757 
1758 /* The order of indexes that should be applied to a PCI buffer line */
1759 static const u8 s_pci_buf_line_ind[PCI_BUF_LINE_SIZE_IN_DWORDS] = { 1, 0, 3, 2, 5, 4, 7, 6 };
1760 
1761 /******************************** Variables **********************************/
1762 
1763 /* The version of the calling app */
1764 static u32 s_app_ver;
1765 
1766 /**************************** Private Functions ******************************/
1767 
ecore_static_asserts(void)1768 static void ecore_static_asserts(void)
1769 {
1770 	CHECK_ARR_SIZE(s_dbg_arrays, MAX_BIN_DBG_BUFFER_TYPE);
1771 	CHECK_ARR_SIZE(s_big_ram_defs, NUM_BIG_RAM_TYPES);
1772 	CHECK_ARR_SIZE(s_vfc_ram_defs, NUM_VFC_RAM_TYPES);
1773 	CHECK_ARR_SIZE(s_rss_mem_defs, NUM_RSS_MEM_TYPES);
1774 	CHECK_ARR_SIZE(s_chip_defs, MAX_CHIP_IDS);
1775 	CHECK_ARR_SIZE(s_platform_defs, MAX_PLATFORM_IDS);
1776 	CHECK_ARR_SIZE(s_storm_defs, MAX_DBG_STORMS);
1777 	CHECK_ARR_SIZE(s_constraint_op_defs, MAX_DBG_BUS_CONSTRAINT_OPS);
1778 	CHECK_ARR_SIZE(s_dbg_target_names, MAX_DBG_BUS_TARGETS);
1779 	CHECK_ARR_SIZE(s_storm_mode_defs, MAX_DBG_BUS_STORM_MODES);
1780 	CHECK_ARR_SIZE(s_grc_param_defs, MAX_DBG_GRC_PARAMS);
1781 	CHECK_ARR_SIZE(s_reset_regs_defs, MAX_DBG_RESET_REGS);
1782 }
1783 
1784 /* Reads and returns a single dword from the specified unaligned buffer. */
ecore_read_unaligned_dword(u8 * buf)1785 static u32 ecore_read_unaligned_dword(u8 *buf)
1786 {
1787 	u32 dword;
1788 
1789 	OSAL_MEMCPY((u8*)&dword, buf, sizeof(dword));
1790 	return dword;
1791 }
1792 
1793 /* Returns the difference in bytes between the specified physical addresses.
1794  * Assumes that the first address is bigger then the second, and that the
1795  * difference is a 32-bit value.
1796  */
ecore_phys_addr_diff(struct dbg_bus_mem_addr * a,struct dbg_bus_mem_addr * b)1797 static u32 ecore_phys_addr_diff(struct dbg_bus_mem_addr *a,
1798 								struct dbg_bus_mem_addr *b)
1799 {
1800 	return a->hi == b->hi ? a->lo - b->lo : b->lo - a->lo;
1801 }
1802 
1803 /* Sets the value of the specified GRC param */
ecore_grc_set_param(struct ecore_hwfn * p_hwfn,enum dbg_grc_params grc_param,u32 val)1804 static void ecore_grc_set_param(struct ecore_hwfn *p_hwfn,
1805 				 enum dbg_grc_params grc_param,
1806 				 u32 val)
1807 {
1808 	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
1809 
1810 	dev_data->grc.param_val[grc_param] = val;
1811 }
1812 
1813 /* Returns the value of the specified GRC param */
ecore_grc_get_param(struct ecore_hwfn * p_hwfn,enum dbg_grc_params grc_param)1814 static u32 ecore_grc_get_param(struct ecore_hwfn *p_hwfn,
1815 							   enum dbg_grc_params grc_param)
1816 {
1817 	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
1818 
1819 	return dev_data->grc.param_val[grc_param];
1820 }
1821 
1822 /* Initializes the GRC parameters */
ecore_dbg_grc_init_params(struct ecore_hwfn * p_hwfn)1823 static void ecore_dbg_grc_init_params(struct ecore_hwfn *p_hwfn)
1824 {
1825 	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
1826 
1827 	if (!dev_data->grc.params_initialized) {
1828 		ecore_dbg_grc_set_params_default(p_hwfn);
1829 		dev_data->grc.params_initialized = 1;
1830 	}
1831 }
1832 
1833 /* Initializes debug data for the specified device */
ecore_dbg_dev_init(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt)1834 static enum dbg_status ecore_dbg_dev_init(struct ecore_hwfn *p_hwfn,
1835 										  struct ecore_ptt *p_ptt)
1836 {
1837 	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
1838 
1839 	if (dev_data->initialized)
1840 		return DBG_STATUS_OK;
1841 
1842 	if (!s_app_ver)
1843 		return DBG_STATUS_APP_VERSION_NOT_SET;
1844 
1845 	if (ECORE_IS_K2(p_hwfn->p_dev)) {
1846 		dev_data->chip_id = CHIP_K2;
1847 		dev_data->mode_enable[MODE_K2] = 1;
1848 	}
1849 	else if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
1850 		dev_data->chip_id = CHIP_BB;
1851 		dev_data->mode_enable[MODE_BB] = 1;
1852 	}
1853 	else {
1854 		return DBG_STATUS_UNKNOWN_CHIP;
1855 	}
1856 
1857 #ifdef ASIC_ONLY
1858 	dev_data->platform_id = PLATFORM_ASIC;
1859 	dev_data->mode_enable[MODE_ASIC] = 1;
1860 #else
1861 	if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
1862 		dev_data->platform_id = PLATFORM_ASIC;
1863 		dev_data->mode_enable[MODE_ASIC] = 1;
1864 	}
1865 	else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1866 		if (ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED) & 0x20000000) {
1867 			dev_data->platform_id = PLATFORM_EMUL_FULL;
1868 			dev_data->mode_enable[MODE_EMUL_FULL] = 1;
1869 		}
1870 		else {
1871 			dev_data->platform_id = PLATFORM_EMUL_REDUCED;
1872 			dev_data->mode_enable[MODE_EMUL_REDUCED] = 1;
1873 		}
1874 	}
1875 	else if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1876 		dev_data->platform_id = PLATFORM_FPGA;
1877 		dev_data->mode_enable[MODE_FPGA] = 1;
1878 	}
1879 	else {
1880 		return DBG_STATUS_UNKNOWN_CHIP;
1881 	}
1882 #endif
1883 
1884 	/* Initializes the GRC parameters */
1885 	ecore_dbg_grc_init_params(p_hwfn);
1886 
1887 	dev_data->initialized = true;
1888 
1889 	return DBG_STATUS_OK;
1890 }
1891 
get_dbg_bus_block_desc(struct ecore_hwfn * p_hwfn,enum block_id block_id)1892 static struct dbg_bus_block* get_dbg_bus_block_desc(struct ecore_hwfn *p_hwfn,
1893 														  enum block_id block_id)
1894 {
1895 	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
1896 
1897 	return (struct dbg_bus_block*)&dbg_bus_blocks[block_id * MAX_CHIP_IDS + dev_data->chip_id];
1898 }
1899 
1900 /* Returns OSAL_NULL for signature line, latency line and non-existing lines */
get_dbg_bus_line_desc(struct ecore_hwfn * p_hwfn,enum block_id block_id)1901 static struct dbg_bus_line* get_dbg_bus_line_desc(struct ecore_hwfn *p_hwfn,
1902 														enum block_id block_id)
1903 {
1904 	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
1905 	struct dbg_bus_block_data *block_bus;
1906 	struct dbg_bus_block *block_desc;
1907 
1908 	block_bus = &dev_data->bus.blocks[block_id];
1909 	block_desc = get_dbg_bus_block_desc(p_hwfn, block_id);
1910 
1911 	if (!block_bus->line_num ||
1912 		(block_bus->line_num == 1 && block_desc->has_latency_events) ||
1913 		block_bus->line_num >= NUM_DBG_LINES(block_desc))
1914 		return OSAL_NULL;
1915 
1916 	return (struct dbg_bus_line*)&dbg_bus_lines[block_desc->lines_offset + block_bus->line_num - NUM_EXTRA_DBG_LINES(block_desc)];
1917 }
1918 
1919 /* Reads the FW info structure for the specified Storm from the chip,
1920  * and writes it to the specified fw_info pointer.
1921  */
ecore_read_fw_info(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u8 storm_id,struct fw_info * fw_info)1922 static void ecore_read_fw_info(struct ecore_hwfn *p_hwfn,
1923 							   struct ecore_ptt *p_ptt,
1924 							   u8 storm_id,
1925 							   struct fw_info *fw_info)
1926 {
1927 	struct storm_defs *storm = &s_storm_defs[storm_id];
1928 	struct fw_info_location fw_info_location;
1929 	u32 addr, i, *dest;
1930 
1931 	OSAL_MEMSET(&fw_info_location, 0, sizeof(fw_info_location));
1932 	OSAL_MEMSET(fw_info, 0, sizeof(*fw_info));
1933 
1934 	/* Read first the address that points to fw_info location.
1935 	 * The address is located in the last line of the Storm RAM.
1936 	 */
1937 	addr = storm->sem_fast_mem_addr + SEM_FAST_REG_INT_RAM + DWORDS_TO_BYTES(SEM_FAST_REG_INT_RAM_SIZE) - sizeof(fw_info_location);
1938 	dest = (u32*)&fw_info_location;
1939 
1940 	for (i = 0; i < BYTES_TO_DWORDS(sizeof(fw_info_location)); i++, addr += BYTES_IN_DWORD)
1941 		dest[i] = ecore_rd(p_hwfn, p_ptt, addr);
1942 
1943 	/* Read FW version info from Storm RAM */
1944 	if (fw_info_location.size > 0 && fw_info_location.size <= sizeof(*fw_info)) {
1945 		addr = fw_info_location.grc_addr;
1946 		dest = (u32*)fw_info;
1947 		for (i = 0; i < BYTES_TO_DWORDS(fw_info_location.size); i++, addr += BYTES_IN_DWORD)
1948 			dest[i] = ecore_rd(p_hwfn, p_ptt, addr);
1949 	}
1950 }
1951 
1952 /* Dumps the specified string to the specified buffer.
1953  * Returns the dumped size in bytes.
1954  */
ecore_dump_str(char * dump_buf,bool dump,const char * str)1955 static u32 ecore_dump_str(char *dump_buf,
1956 						  bool dump,
1957 						  const char *str)
1958 {
1959 	if (dump)
1960 		OSAL_STRCPY(dump_buf, str);
1961 
1962 	return (u32)OSAL_STRLEN(str) + 1;
1963 }
1964 
1965 /* Dumps zeros to align the specified buffer to dwords.
1966  * Returns the dumped size in bytes.
1967  */
ecore_dump_align(char * dump_buf,bool dump,u32 byte_offset)1968 static u32 ecore_dump_align(char *dump_buf,
1969 							bool dump,
1970 							u32 byte_offset)
1971 {
1972 	u8 offset_in_dword, align_size;
1973 
1974 	offset_in_dword = (u8)(byte_offset & 0x3);
1975 	align_size = offset_in_dword ? BYTES_IN_DWORD - offset_in_dword : 0;
1976 
1977 	if (dump && align_size)
1978 		OSAL_MEMSET(dump_buf, 0, align_size);
1979 
1980 	return align_size;
1981 }
1982 
1983 /* Writes the specified string param to the specified buffer.
1984  * Returns the dumped size in dwords.
1985  */
ecore_dump_str_param(u32 * dump_buf,bool dump,const char * param_name,const char * param_val)1986 static u32 ecore_dump_str_param(u32 *dump_buf,
1987 								bool dump,
1988 								const char *param_name,
1989 								const char *param_val)
1990 {
1991 	char *char_buf = (char*)dump_buf;
1992 	u32 offset = 0;
1993 
1994 	/* Dump param name */
1995 	offset += ecore_dump_str(char_buf + offset, dump, param_name);
1996 
1997 	/* Indicate a string param value */
1998 	if (dump)
1999 		*(char_buf + offset) = 1;
2000 	offset++;
2001 
2002 	/* Dump param value */
2003 	offset += ecore_dump_str(char_buf + offset, dump, param_val);
2004 
2005 	/* Align buffer to next dword */
2006 	offset += ecore_dump_align(char_buf + offset, dump, offset);
2007 
2008 	return BYTES_TO_DWORDS(offset);
2009 }
2010 
2011 /* Writes the specified numeric param to the specified buffer.
2012  * Returns the dumped size in dwords.
2013  */
ecore_dump_num_param(u32 * dump_buf,bool dump,const char * param_name,u32 param_val)2014 static u32 ecore_dump_num_param(u32 *dump_buf,
2015 								bool dump,
2016 								const char *param_name,
2017 								u32 param_val)
2018 {
2019 	char *char_buf = (char*)dump_buf;
2020 	u32 offset = 0;
2021 
2022 	/* Dump param name */
2023 	offset += ecore_dump_str(char_buf + offset, dump, param_name);
2024 
2025 	/* Indicate a numeric param value */
2026 	if (dump)
2027 		*(char_buf + offset) = 0;
2028 	offset++;
2029 
2030 	/* Align buffer to next dword */
2031 	offset += ecore_dump_align(char_buf + offset, dump, offset);
2032 
2033 	/* Dump param value (and change offset from bytes to dwords) */
2034 	offset = BYTES_TO_DWORDS(offset);
2035 	if (dump)
2036 		*(dump_buf + offset) = param_val;
2037 	offset++;
2038 
2039 	return offset;
2040 }
2041 
2042 /* Reads the FW version and writes it as a param to the specified buffer.
2043  * Returns the dumped size in dwords.
2044  */
ecore_dump_fw_ver_param(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u32 * dump_buf,bool dump)2045 static u32 ecore_dump_fw_ver_param(struct ecore_hwfn *p_hwfn,
2046 								   struct ecore_ptt *p_ptt,
2047 								   u32 *dump_buf,
2048 								   bool dump)
2049 {
2050 	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
2051 	char fw_ver_str[16] = EMPTY_FW_VERSION_STR;
2052 	char fw_img_str[16] = EMPTY_FW_IMAGE_STR;
2053 	struct fw_info fw_info = { { 0 }, { 0 } };
2054 	u32 offset = 0;
2055 
2056 	if (dump && !ecore_grc_get_param(p_hwfn, DBG_GRC_PARAM_NO_FW_VER)) {
2057 		/* Read FW image/version from PRAM in a non-reset SEMI */
2058 		bool found = false;
2059 		u8 storm_id;
2060 
2061 		for (storm_id = 0; storm_id < MAX_DBG_STORMS && !found; storm_id++) {
2062 			struct storm_defs *storm = &s_storm_defs[storm_id];
2063 
2064 			/* Read FW version/image */
2065 			if (dev_data->block_in_reset[storm->block_id])
2066 				continue;
2067 
2068 			/* Read FW info for the current Storm */
2069 			ecore_read_fw_info(p_hwfn, p_ptt, storm_id, &fw_info);
2070 
2071 			/* Create FW version/image strings */
2072 			if (OSAL_SNPRINTF(fw_ver_str, sizeof(fw_ver_str), "%d_%d_%d_%d", fw_info.ver.num.major, fw_info.ver.num.minor, fw_info.ver.num.rev, fw_info.ver.num.eng) < 0)
2073 				DP_NOTICE(p_hwfn, true, "Unexpected debug error: invalid FW version string\n");
2074 			switch (fw_info.ver.image_id) {
2075 			case FW_IMG_KUKU: OSAL_STRCPY(fw_img_str, "kuku"); break;
2076 			case FW_IMG_MAIN: OSAL_STRCPY(fw_img_str, "main"); break;
2077 			case FW_IMG_L2B: OSAL_STRCPY(fw_img_str, "l2b"); break;
2078 			default: OSAL_STRCPY(fw_img_str, "unknown"); break;
2079 			}
2080 
2081 			found = true;
2082 		}
2083 	}
2084 
2085 	/* Dump FW version, image and timestamp */
2086 	offset += ecore_dump_str_param(dump_buf + offset, dump, "fw-version", fw_ver_str);
2087 	offset += ecore_dump_str_param(dump_buf + offset, dump, "fw-image", fw_img_str);
2088 	offset += ecore_dump_num_param(dump_buf + offset, dump, "fw-timestamp", fw_info.ver.timestamp);
2089 
2090 	return offset;
2091 }
2092 
2093 /* Reads the MFW version and writes it as a param to the specified buffer.
2094  * Returns the dumped size in dwords.
2095  */
ecore_dump_mfw_ver_param(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u32 * dump_buf,bool dump)2096 static u32 ecore_dump_mfw_ver_param(struct ecore_hwfn *p_hwfn,
2097 									struct ecore_ptt *p_ptt,
2098 									u32 *dump_buf,
2099 									bool dump)
2100 {
2101 	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
2102 	char mfw_ver_str[16] = EMPTY_FW_VERSION_STR;
2103 	bool is_emul;
2104 
2105 	is_emul = dev_data->platform_id == PLATFORM_EMUL_FULL || dev_data->platform_id == PLATFORM_EMUL_REDUCED;
2106 
2107 	if (dump && !is_emul && !ecore_grc_get_param(p_hwfn, DBG_GRC_PARAM_NO_FW_VER)) {
2108 		u32 public_data_addr, global_section_offsize_addr, global_section_offsize, global_section_addr, mfw_ver;
2109 
2110 		/* Find MCP public data GRC address. Needs to be ORed with
2111 		 * MCP_REG_SCRATCH due to a HW bug.
2112 		 */
2113 		public_data_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR) | MCP_REG_SCRATCH;
2114 
2115 		/* Find MCP public global section offset */
2116 		global_section_offsize_addr = public_data_addr + offsetof(struct mcp_public_data, sections) + sizeof(offsize_t) * PUBLIC_GLOBAL;
2117 		global_section_offsize = ecore_rd(p_hwfn, p_ptt, global_section_offsize_addr);
2118 		global_section_addr = MCP_REG_SCRATCH + (global_section_offsize & OFFSIZE_OFFSET_MASK) * 4;
2119 
2120 		/* Read MFW version from MCP public global section */
2121 		mfw_ver = ecore_rd(p_hwfn, p_ptt, global_section_addr + offsetof(struct public_global, mfw_ver));
2122 
2123 		/* Dump MFW version param */
2124 		if (OSAL_SNPRINTF(mfw_ver_str, sizeof(mfw_ver_str), "%d_%d_%d_%d", (u8)(mfw_ver >> 24), (u8)(mfw_ver >> 16), (u8)(mfw_ver >> 8), (u8)mfw_ver) < 0)
2125 			DP_NOTICE(p_hwfn, true, "Unexpected debug error: invalid MFW version string\n");
2126 	}
2127 
2128 	return ecore_dump_str_param(dump_buf, dump, "mfw-version", mfw_ver_str);
2129 }
2130 
2131 /* Writes a section header to the specified buffer.
2132  * Returns the dumped size in dwords.
2133  */
ecore_dump_section_hdr(u32 * dump_buf,bool dump,const char * name,u32 num_params)2134 static u32 ecore_dump_section_hdr(u32 *dump_buf,
2135 								  bool dump,
2136 								  const char *name,
2137 								  u32 num_params)
2138 {
2139 	return ecore_dump_num_param(dump_buf, dump, name, num_params);
2140 }
2141 
2142 /* Writes the common global params to the specified buffer.
2143  * Returns the dumped size in dwords.
2144  */
ecore_dump_common_global_params(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u32 * dump_buf,bool dump,u8 num_specific_global_params)2145 static u32 ecore_dump_common_global_params(struct ecore_hwfn *p_hwfn,
2146 										   struct ecore_ptt *p_ptt,
2147 										   u32 *dump_buf,
2148 										   bool dump,
2149 										   u8 num_specific_global_params)
2150 {
2151 	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
2152 	u32 offset = 0;
2153 	u8 num_params;
2154 
2155 	/* Dump global params section header */
2156 	num_params = NUM_COMMON_GLOBAL_PARAMS + num_specific_global_params;
2157 	offset += ecore_dump_section_hdr(dump_buf + offset, dump, "global_params", num_params);
2158 
2159 	/* Store params */
2160 	offset += ecore_dump_fw_ver_param(p_hwfn, p_ptt, dump_buf + offset, dump);
2161 	offset += ecore_dump_mfw_ver_param(p_hwfn, p_ptt, dump_buf + offset, dump);
2162 	offset += ecore_dump_num_param(dump_buf + offset, dump, "tools-version", TOOLS_VERSION);
2163 	offset += ecore_dump_str_param(dump_buf + offset, dump, "chip", s_chip_defs[dev_data->chip_id].name);
2164 	offset += ecore_dump_str_param(dump_buf + offset, dump, "platform", s_platform_defs[dev_data->platform_id].name);
2165 	offset += ecore_dump_num_param(dump_buf + offset, dump, "pci-func", p_hwfn->abs_pf_id);
2166 
2167 	return offset;
2168 }
2169 
2170 /* Writes the "last" section (including CRC) to the specified buffer at the
2171  * given offset. Returns the dumped size in dwords.
2172  */
ecore_dump_last_section(struct ecore_hwfn * p_hwfn,u32 * dump_buf,u32 offset,bool dump)2173 static u32 ecore_dump_last_section(struct ecore_hwfn *p_hwfn,
2174 								   u32 *dump_buf,
2175 								   u32 offset,
2176 								   bool dump)
2177 {
2178 	u32 start_offset = offset;
2179 
2180 	/* Dump CRC section header */
2181 	offset += ecore_dump_section_hdr(dump_buf + offset, dump, "last", 0);
2182 
2183 	/* Calculate CRC32 and add it to the dword after the "last" section */
2184 	if (dump)
2185 		*(dump_buf + offset) = ~OSAL_CRC32(0xffffffff, (u8*)dump_buf, DWORDS_TO_BYTES(offset));
2186 
2187 	offset++;
2188 
2189 	return offset - start_offset;
2190 }
2191 
2192 /* Update blocks reset state  */
ecore_update_blocks_reset_state(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt)2193 static void ecore_update_blocks_reset_state(struct ecore_hwfn *p_hwfn,
2194 											struct ecore_ptt *p_ptt)
2195 {
2196 	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
2197 	u32 reg_val[MAX_DBG_RESET_REGS] = { 0 };
2198 	u32 i;
2199 
2200 	/* Read reset registers */
2201 	for (i = 0; i < MAX_DBG_RESET_REGS; i++)
2202 		if (s_reset_regs_defs[i].exists[dev_data->chip_id])
2203 			reg_val[i] = ecore_rd(p_hwfn, p_ptt, s_reset_regs_defs[i].addr);
2204 
2205 	/* Check if blocks are in reset */
2206 	for (i = 0; i < MAX_BLOCK_ID; i++) {
2207 		struct block_defs *block = s_block_defs[i];
2208 
2209 		dev_data->block_in_reset[i] = block->has_reset_bit && !(reg_val[block->reset_reg] & (1 << block->reset_bit_offset));
2210 	}
2211 }
2212 
2213 /* Enable / disable the Debug block */
ecore_bus_enable_dbg_block(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,bool enable)2214 static void ecore_bus_enable_dbg_block(struct ecore_hwfn *p_hwfn,
2215 									   struct ecore_ptt *p_ptt,
2216 									   bool enable)
2217 {
2218 	ecore_wr(p_hwfn, p_ptt, DBG_REG_DBG_BLOCK_ON, enable ? 1 : 0);
2219 }
2220 
2221 /* Resets the Debug block */
ecore_bus_reset_dbg_block(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt)2222 static void ecore_bus_reset_dbg_block(struct ecore_hwfn *p_hwfn,
2223 									  struct ecore_ptt *p_ptt)
2224 {
2225 	u32 dbg_reset_reg_addr, old_reset_reg_val, new_reset_reg_val;
2226 	struct block_defs *dbg_block = s_block_defs[BLOCK_DBG];
2227 
2228 	dbg_reset_reg_addr = s_reset_regs_defs[dbg_block->reset_reg].addr;
2229 	old_reset_reg_val = ecore_rd(p_hwfn, p_ptt, dbg_reset_reg_addr);
2230 	new_reset_reg_val = old_reset_reg_val & ~(1 << dbg_block->reset_bit_offset);
2231 
2232 	ecore_wr(p_hwfn, p_ptt, dbg_reset_reg_addr, new_reset_reg_val);
2233 	ecore_wr(p_hwfn, p_ptt, dbg_reset_reg_addr, old_reset_reg_val);
2234 }
2235 
ecore_bus_set_framing_mode(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,enum dbg_bus_frame_modes mode)2236 static void ecore_bus_set_framing_mode(struct ecore_hwfn *p_hwfn,
2237 									   struct ecore_ptt *p_ptt,
2238 									   enum dbg_bus_frame_modes mode)
2239 {
2240 	ecore_wr(p_hwfn, p_ptt, DBG_REG_FRAMING_MODE, (u8)mode);
2241 }
2242 
2243 /* Enable / disable Debug Bus clients according to the specified mask
2244  * (1 = enable, 0 = disable).
2245  */
ecore_bus_enable_clients(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u32 client_mask)2246 static void ecore_bus_enable_clients(struct ecore_hwfn *p_hwfn,
2247 									 struct ecore_ptt *p_ptt,
2248 									 u32 client_mask)
2249 {
2250 	ecore_wr(p_hwfn, p_ptt, DBG_REG_CLIENT_ENABLE, client_mask);
2251 }
2252 
2253 /* Enables the specified Storm for Debug Bus. Assumes a valid Storm ID. */
ecore_bus_enable_storm(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,enum dbg_storms storm_id,enum dbg_bus_filter_types filter_type)2254 static void ecore_bus_enable_storm(struct ecore_hwfn *p_hwfn,
2255 								   struct ecore_ptt *p_ptt,
2256 								   enum dbg_storms storm_id,
2257 								   enum dbg_bus_filter_types filter_type)
2258 {
2259 	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
2260 	u32 base_addr, sem_filter_params = filter_type;
2261 	struct dbg_bus_storm_data *storm_bus;
2262 	struct storm_mode_defs *storm_mode;
2263 	struct storm_defs *storm;
2264 
2265 	storm = &s_storm_defs[storm_id];
2266 	storm_bus = &dev_data->bus.storms[storm_id];
2267 	storm_mode = &s_storm_mode_defs[storm_bus->mode];
2268 	base_addr = storm->sem_fast_mem_addr;
2269 
2270 	/* Config SEM */
2271 	if (storm_mode->is_fast_dbg) {
2272 
2273 		/* Enable fast debug */
2274 		ecore_wr(p_hwfn, p_ptt, storm->sem_frame_mode_addr, DBG_BUS_SEMI_FRAME_MODE_0SLOW_4FAST);
2275 		ecore_wr(p_hwfn, p_ptt, base_addr + SEM_FAST_REG_DEBUG_MODE, storm_mode->id_in_hw);
2276 		ecore_wr(p_hwfn, p_ptt, base_addr + SEM_FAST_REG_DEBUG_ACTIVE, 1);
2277 
2278 		/* Enable all messages except STORE. Must be done after
2279 		 * enabling SEM_FAST_REG_DEBUG_ACTIVE, otherwise messages will
2280 		 * be dropped after the SEMI sync fifo is filled.
2281 		 */
2282 		ecore_wr(p_hwfn, p_ptt, base_addr + SEM_FAST_REG_DBG_MODE6_SRC_DISABLE, SEM_FAST_MODE6_SRC_ENABLE);
2283 	}
2284 	else {
2285 
2286 		/* Ensable slow debug */
2287 		ecore_wr(p_hwfn, p_ptt, storm->sem_frame_mode_addr, DBG_BUS_SEMI_FRAME_MODE_4SLOW_0FAST);
2288 		ecore_wr(p_hwfn, p_ptt, storm->sem_slow_enable_addr, 1);
2289 		ecore_wr(p_hwfn, p_ptt, storm->sem_slow_mode_addr, storm_mode->id_in_hw);
2290 		ecore_wr(p_hwfn, p_ptt, storm->sem_slow_mode1_conf_addr, SEM_SLOW_MODE1_DATA_ENABLE);
2291 	}
2292 
2293 	/* Config SEM cid filter */
2294 	if (storm_bus->cid_filter_en) {
2295 		ecore_wr(p_hwfn, p_ptt, base_addr + SEM_FAST_REG_FILTER_CID, storm_bus->cid);
2296 		sem_filter_params |= SEM_FILTER_CID_EN_MASK;
2297 	}
2298 
2299 	/* Config SEM eid filter */
2300 	if (storm_bus->eid_filter_en) {
2301 		const union dbg_bus_storm_eid_params *eid_filter = &storm_bus->eid_filter_params;
2302 
2303 		if (storm_bus->eid_range_not_mask) {
2304 			ecore_wr(p_hwfn, p_ptt, base_addr + SEM_FAST_REG_EVENT_ID_RANGE_STRT, eid_filter->range.min);
2305 			ecore_wr(p_hwfn, p_ptt, base_addr + SEM_FAST_REG_EVENT_ID_RANGE_END, eid_filter->range.max);
2306 			sem_filter_params |= SEM_FILTER_EID_RANGE_EN_MASK;
2307 		}
2308 		else {
2309 			ecore_wr(p_hwfn, p_ptt, base_addr + SEM_FAST_REG_FILTER_EVENT_ID, eid_filter->mask.val);
2310 			ecore_wr(p_hwfn, p_ptt, base_addr + SEM_FAST_REG_EVENT_ID_MASK, ~eid_filter->mask.mask);
2311 			sem_filter_params |= SEM_FILTER_EID_MASK_EN_MASK;
2312 		}
2313 	}
2314 
2315 	/* Config accumulaed SEM filter parameters (if any) */
2316 	if (sem_filter_params)
2317 		ecore_wr(p_hwfn, p_ptt, base_addr + SEM_FAST_REG_RECORD_FILTER_ENABLE, sem_filter_params);
2318 }
2319 
2320 /* Disables Debug Bus block inputs */
ecore_bus_disable_inputs(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,bool empty_semi_fifos)2321 static enum dbg_status ecore_bus_disable_inputs(struct ecore_hwfn *p_hwfn,
2322 												struct ecore_ptt *p_ptt,
2323 												bool empty_semi_fifos)
2324 {
2325 	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
2326 	u8 storm_id, num_fifos_to_empty = MAX_DBG_STORMS;
2327 	bool is_fifo_empty[MAX_DBG_STORMS] = { false };
2328 	u32 block_id;
2329 
2330 	/* Disable messages output in all Storms */
2331 	for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) {
2332 		struct storm_defs *storm = &s_storm_defs[storm_id];
2333 
2334 		if (!dev_data->block_in_reset[storm->block_id])
2335 			ecore_wr(p_hwfn, p_ptt, storm->sem_fast_mem_addr + SEM_FAST_REG_DBG_MODE6_SRC_DISABLE, SEM_FAST_MODE6_SRC_DISABLE);
2336 	}
2337 
2338 	/* Try to empty the SEMI sync fifo. Must be done after messages output
2339 	 * were disabled in all Storms (i.e. SEM_FAST_REG_DBG_MODE6_SRC_DISABLE
2340 	 * was set to all 1's.
2341 	 */
2342 	while (num_fifos_to_empty) {
2343 		for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) {
2344 			struct storm_defs *storm = &s_storm_defs[storm_id];
2345 
2346 			if (is_fifo_empty[storm_id])
2347 				continue;
2348 
2349 			/* Check if sync fifo got empty */
2350 			if (dev_data->block_in_reset[storm->block_id] || ecore_rd(p_hwfn, p_ptt, storm->sem_sync_dbg_empty_addr)) {
2351 				is_fifo_empty[storm_id] = true;
2352 				num_fifos_to_empty--;
2353 			}
2354 		}
2355 
2356 		/* Check if need to continue polling */
2357 		if (num_fifos_to_empty) {
2358 			u32 polling_ms = SEMI_SYNC_FIFO_POLLING_DELAY_MS * s_platform_defs[dev_data->platform_id].delay_factor;
2359 			u32 polling_count = 0;
2360 
2361 			if (empty_semi_fifos && polling_count < SEMI_SYNC_FIFO_POLLING_COUNT) {
2362 				OSAL_MSLEEP(polling_ms);
2363 				polling_count++;
2364 			}
2365 			else {
2366 				DP_NOTICE(p_hwfn, false, "Warning: failed to empty the SEMI sync FIFO. It means that the last few messages from the SEMI could not be sent to the DBG block. This can happen when the DBG block is blocked (e.g. due to a PCI problem).\n");
2367 				break;
2368 			}
2369 		}
2370 	}
2371 
2372 	/* Disable debug in all Storms */
2373 	for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) {
2374 		struct storm_defs *storm = &s_storm_defs[storm_id];
2375 		u32 base_addr = storm->sem_fast_mem_addr;
2376 
2377 		if (dev_data->block_in_reset[storm->block_id])
2378 			continue;
2379 
2380 		ecore_wr(p_hwfn, p_ptt, base_addr + SEM_FAST_REG_DEBUG_ACTIVE, 0);
2381 		ecore_wr(p_hwfn, p_ptt, base_addr + SEM_FAST_REG_RECORD_FILTER_ENABLE, DBG_BUS_FILTER_TYPE_OFF);
2382 		ecore_wr(p_hwfn, p_ptt, storm->sem_frame_mode_addr, DBG_BUS_FRAME_MODE_4HW_0ST);
2383 		ecore_wr(p_hwfn, p_ptt, storm->sem_slow_enable_addr, 0);
2384 	}
2385 
2386 	/* Disable all clients */
2387 	ecore_bus_enable_clients(p_hwfn, p_ptt, 0);
2388 
2389 	/* Disable all blocks */
2390 	for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) {
2391 		struct block_defs *block = s_block_defs[block_id];
2392 
2393 		if (block->has_dbg_bus[dev_data->chip_id] && !dev_data->block_in_reset[block_id])
2394 			ecore_wr(p_hwfn, p_ptt, block->dbg_enable_addr, 0);
2395 	}
2396 
2397 	/* Disable timestamp */
2398 	ecore_wr(p_hwfn, p_ptt, DBG_REG_TIMESTAMP_VALID_EN, 0);
2399 
2400 	/* Disable filters and triggers */
2401 	ecore_wr(p_hwfn, p_ptt, DBG_REG_FILTER_ENABLE, DBG_BUS_FILTER_TYPE_OFF);
2402 	ecore_wr(p_hwfn, p_ptt, DBG_REG_TRIGGER_ENABLE, 0);
2403 
2404 	return DBG_STATUS_OK;
2405 }
2406 
2407 /* Sets a Debug Bus trigger/filter constraint */
ecore_bus_set_constraint(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,bool is_filter,u8 constraint_id,u8 hw_op_val,u32 data_val,u32 data_mask,u8 frame_bit,u8 frame_mask,u16 dword_offset,u16 range,u8 cyclic_bit,u8 must_bit)2408 static void ecore_bus_set_constraint(struct ecore_hwfn *p_hwfn,
2409 									 struct ecore_ptt *p_ptt,
2410 									 bool is_filter,
2411 									 u8 constraint_id,
2412 									 u8 hw_op_val,
2413 									 u32 data_val,
2414 									 u32 data_mask,
2415 									 u8 frame_bit,
2416 									 u8 frame_mask,
2417 									 u16 dword_offset,
2418 									 u16 range,
2419 									 u8 cyclic_bit,
2420 									 u8 must_bit)
2421 {
2422 	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
2423 	u32 reg_offset = constraint_id * BYTES_IN_DWORD;
2424 	u8 curr_trigger_state;
2425 
2426 	/* For trigger only - set register offset according to state */
2427 	if (!is_filter) {
2428 		curr_trigger_state = dev_data->bus.next_trigger_state - 1;
2429 		reg_offset += curr_trigger_state * TRIGGER_SETS_PER_STATE * MAX_CONSTRAINTS * BYTES_IN_DWORD;
2430 	}
2431 
2432 	ecore_wr(p_hwfn, p_ptt, (is_filter ? DBG_REG_FILTER_CNSTR_OPRTN_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_0) + reg_offset, hw_op_val);
2433 	ecore_wr(p_hwfn, p_ptt, (is_filter ? DBG_REG_FILTER_CNSTR_DATA_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_0) + reg_offset, data_val);
2434 	ecore_wr(p_hwfn, p_ptt, (is_filter ? DBG_REG_FILTER_CNSTR_DATA_MASK_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_0) + reg_offset, data_mask);
2435 	ecore_wr(p_hwfn, p_ptt, (is_filter ? DBG_REG_FILTER_CNSTR_FRAME_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_0) + reg_offset, frame_bit);
2436 	ecore_wr(p_hwfn, p_ptt, (is_filter ? DBG_REG_FILTER_CNSTR_FRAME_MASK_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_0) + reg_offset, frame_mask);
2437 	ecore_wr(p_hwfn, p_ptt, (is_filter ? DBG_REG_FILTER_CNSTR_OFFSET_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_0) + reg_offset, dword_offset);
2438 	ecore_wr(p_hwfn, p_ptt, (is_filter ? DBG_REG_FILTER_CNSTR_RANGE_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_0) + reg_offset, range);
2439 	ecore_wr(p_hwfn, p_ptt, (is_filter ? DBG_REG_FILTER_CNSTR_CYCLIC_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_0) + reg_offset, cyclic_bit);
2440 	ecore_wr(p_hwfn, p_ptt, (is_filter ? DBG_REG_FILTER_CNSTR_MUST_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_0) + reg_offset, must_bit);
2441 }
2442 
2443 /* Reads the specified DBG Bus internal buffer range and copy it to the
2444  * specified buffer. Returns the dumped size in dwords.
2445  */
ecore_bus_dump_int_buf_range(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u32 * dump_buf,bool dump,u32 start_line,u32 end_line)2446 static u32 ecore_bus_dump_int_buf_range(struct ecore_hwfn *p_hwfn,
2447 										struct ecore_ptt *p_ptt,
2448 										u32 *dump_buf,
2449 										bool dump,
2450 										u32 start_line,
2451 										u32 end_line)
2452 {
2453 	u32 line, reg_addr, i, offset = 0;
2454 
2455 	if (!dump)
2456 		return (end_line - start_line + 1) * INT_BUF_LINE_SIZE_IN_DWORDS;
2457 
2458 	for (line = start_line, reg_addr = DBG_REG_INTR_BUFFER + DWORDS_TO_BYTES(start_line * INT_BUF_LINE_SIZE_IN_DWORDS);
2459 		line <= end_line;
2460 		line++, offset += INT_BUF_LINE_SIZE_IN_DWORDS)
2461 		for (i = 0; i < INT_BUF_LINE_SIZE_IN_DWORDS; i++, reg_addr += BYTES_IN_DWORD)
2462 			dump_buf[offset + INT_BUF_LINE_SIZE_IN_DWORDS - 1 - i] = ecore_rd(p_hwfn, p_ptt, reg_addr);
2463 
2464 	return offset;
2465 }
2466 
2467 /* Reads the DBG Bus internal buffer and copy its contents to a buffer.
2468  * Returns the dumped size in dwords.
2469  */
ecore_bus_dump_int_buf(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u32 * dump_buf,bool dump)2470 static u32 ecore_bus_dump_int_buf(struct ecore_hwfn *p_hwfn,
2471 								  struct ecore_ptt *p_ptt,
2472 								  u32 *dump_buf,
2473 								  bool dump)
2474 {
2475 	u32 last_written_line, offset = 0;
2476 
2477 	last_written_line = ecore_rd(p_hwfn, p_ptt, DBG_REG_INTR_BUFFER_WR_PTR);
2478 
2479 	if (ecore_rd(p_hwfn, p_ptt, DBG_REG_WRAP_ON_INT_BUFFER)) {
2480 
2481 		/* Internal buffer was wrapped: first dump from write pointer
2482 		 * to buffer end, then dump from buffer start to write pointer.
2483 		 */
2484 		if (last_written_line < INT_BUF_NUM_OF_LINES - 1)
2485 			offset += ecore_bus_dump_int_buf_range(p_hwfn, p_ptt, dump_buf + offset, dump, last_written_line + 1, INT_BUF_NUM_OF_LINES - 1);
2486 		offset += ecore_bus_dump_int_buf_range(p_hwfn, p_ptt, dump_buf + offset, dump, 0, last_written_line);
2487 	}
2488 	else if (last_written_line) {
2489 
2490 		/* Internal buffer wasn't wrapped: dump from buffer start until
2491 		 *  write pointer.
2492 		 */
2493 		if (!ecore_rd(p_hwfn, p_ptt, DBG_REG_INTR_BUFFER_RD_PTR))
2494 			offset += ecore_bus_dump_int_buf_range(p_hwfn, p_ptt, dump_buf + offset, dump, 0, last_written_line);
2495 		else
2496 			DP_NOTICE(p_hwfn, true, "Unexpected Debug Bus error: internal buffer read pointer is not zero\n");
2497 	}
2498 
2499 	return offset;
2500 }
2501 
2502 /* Reads the specified DBG Bus PCI buffer range and copy it to the specified
2503  * buffer. Returns the dumped size in dwords.
2504  */
ecore_bus_dump_pci_buf_range(struct ecore_hwfn * p_hwfn,u32 * dump_buf,bool dump,u32 start_line,u32 end_line)2505 static u32 ecore_bus_dump_pci_buf_range(struct ecore_hwfn *p_hwfn,
2506 										u32 *dump_buf,
2507 										bool dump,
2508 										u32 start_line,
2509 										u32 end_line)
2510 {
2511 	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
2512 	u32 offset = 0;
2513 
2514 	/* Extract PCI buffer pointer from virtual address */
2515 	void *virt_addr_lo = &dev_data->bus.pci_buf.virt_addr.lo;
2516 	u32 *pci_buf_start = (u32*)(osal_uintptr_t)*((u64*)virt_addr_lo);
2517 	u32 *pci_buf, line, i;
2518 
2519 	if (!dump)
2520 		return (end_line - start_line + 1) * PCI_BUF_LINE_SIZE_IN_DWORDS;
2521 
2522 	for (line = start_line, pci_buf = pci_buf_start + start_line * PCI_BUF_LINE_SIZE_IN_DWORDS;
2523 	line <= end_line;
2524 		line++, offset += PCI_BUF_LINE_SIZE_IN_DWORDS)
2525 		for (i = 0; i < PCI_BUF_LINE_SIZE_IN_DWORDS; i++, pci_buf++)
2526 			dump_buf[offset + s_pci_buf_line_ind[i]] = *pci_buf;
2527 
2528 	return offset;
2529 }
2530 
2531 /* Copies the DBG Bus PCI buffer to the specified buffer.
2532  * Returns the dumped size in dwords.
2533  */
ecore_bus_dump_pci_buf(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u32 * dump_buf,bool dump)2534 static u32 ecore_bus_dump_pci_buf(struct ecore_hwfn *p_hwfn,
2535 								  struct ecore_ptt *p_ptt,
2536 								  u32 *dump_buf,
2537 								  bool dump)
2538 {
2539 	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
2540 	u32 next_wr_byte_offset, next_wr_line_offset;
2541 	struct dbg_bus_mem_addr next_wr_phys_addr;
2542 	u32 pci_buf_size_in_lines, offset = 0;
2543 
2544 	pci_buf_size_in_lines = dev_data->bus.pci_buf.size / PCI_BUF_LINE_SIZE_IN_BYTES;
2545 
2546 	/* Extract write pointer (physical address) */
2547 	next_wr_phys_addr.lo = ecore_rd(p_hwfn, p_ptt, DBG_REG_EXT_BUFFER_WR_PTR);
2548 	next_wr_phys_addr.hi = ecore_rd(p_hwfn, p_ptt, DBG_REG_EXT_BUFFER_WR_PTR + BYTES_IN_DWORD);
2549 
2550 	/* Convert write pointer to offset */
2551 	next_wr_byte_offset = ecore_phys_addr_diff(&next_wr_phys_addr, &dev_data->bus.pci_buf.phys_addr);
2552 	if ((next_wr_byte_offset % PCI_BUF_LINE_SIZE_IN_BYTES) || next_wr_byte_offset > dev_data->bus.pci_buf.size)
2553 		return 0;
2554 	next_wr_line_offset = next_wr_byte_offset / PCI_BUF_LINE_SIZE_IN_BYTES;
2555 
2556 	/* PCI buffer wrapped: first dump from write pointer to buffer end. */
2557 	if (ecore_rd(p_hwfn, p_ptt, DBG_REG_WRAP_ON_EXT_BUFFER))
2558 		offset += ecore_bus_dump_pci_buf_range(p_hwfn, dump_buf + offset, dump, next_wr_line_offset, pci_buf_size_in_lines - 1);
2559 
2560 	/* Dump from buffer start until write pointer */
2561 	if (next_wr_line_offset)
2562 		offset += ecore_bus_dump_pci_buf_range(p_hwfn, dump_buf + offset, dump, 0, next_wr_line_offset - 1);
2563 
2564 	return offset;
2565 }
2566 
2567 /* Copies the DBG Bus recorded data to the specified buffer.
2568  * Returns the dumped size in dwords.
2569  */
ecore_bus_dump_data(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u32 * dump_buf,bool dump)2570 static u32 ecore_bus_dump_data(struct ecore_hwfn *p_hwfn,
2571 							   struct ecore_ptt *p_ptt,
2572 							   u32 *dump_buf,
2573 							   bool dump)
2574 {
2575 	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
2576 
2577 	switch (dev_data->bus.target) {
2578 	case DBG_BUS_TARGET_ID_INT_BUF:
2579 		return ecore_bus_dump_int_buf(p_hwfn, p_ptt, dump_buf, dump);
2580 	case DBG_BUS_TARGET_ID_PCI:
2581 		return ecore_bus_dump_pci_buf(p_hwfn, p_ptt, dump_buf, dump);
2582 	default:
2583 		break;
2584 	}
2585 
2586 	return 0;
2587 }
2588 
2589 /* Frees the Debug Bus PCI buffer */
ecore_bus_free_pci_buf(struct ecore_hwfn * p_hwfn)2590 static void ecore_bus_free_pci_buf(struct ecore_hwfn *p_hwfn)
2591 {
2592 	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
2593 	dma_addr_t pci_buf_phys_addr;
2594 	void *virt_addr_lo;
2595 	u32 *pci_buf;
2596 
2597 	/* Extract PCI buffer pointer from virtual address */
2598 	virt_addr_lo = &dev_data->bus.pci_buf.virt_addr.lo;
2599 	pci_buf = (u32*)(osal_uintptr_t)*((u64*)virt_addr_lo);
2600 
2601 	if (!dev_data->bus.pci_buf.size)
2602 		return;
2603 
2604 	OSAL_MEMCPY(&pci_buf_phys_addr, &dev_data->bus.pci_buf.phys_addr, sizeof(pci_buf_phys_addr));
2605 
2606 	OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev, pci_buf, pci_buf_phys_addr, dev_data->bus.pci_buf.size);
2607 
2608 	dev_data->bus.pci_buf.size = 0;
2609 }
2610 
2611 /* Dumps the list of DBG Bus inputs (blocks/Storms) to the specified buffer.
2612  * Returns the dumped size in dwords.
2613  */
ecore_bus_dump_inputs(struct ecore_hwfn * p_hwfn,u32 * dump_buf,bool dump)2614 static u32 ecore_bus_dump_inputs(struct ecore_hwfn *p_hwfn,
2615 								 u32 *dump_buf,
2616 								 bool dump)
2617 {
2618 	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
2619 	char storm_name[8] = "?storm";
2620 	u32 block_id, offset = 0;
2621 	u8 storm_id;
2622 
2623 	/* Store storms */
2624 	for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) {
2625 		struct dbg_bus_storm_data *storm_bus = &dev_data->bus.storms[storm_id];
2626 		struct storm_defs *storm = &s_storm_defs[storm_id];
2627 
2628 		if (!dev_data->bus.storms[storm_id].enabled)
2629 			continue;
2630 
2631 		/* Dump section header */
2632 		storm_name[0] = storm->letter;
2633 		offset += ecore_dump_section_hdr(dump_buf + offset, dump, "bus_input", 3);
2634 		offset += ecore_dump_str_param(dump_buf + offset, dump, "name", storm_name);
2635 		offset += ecore_dump_num_param(dump_buf + offset, dump, "id", storm_bus->hw_id);
2636 		offset += ecore_dump_str_param(dump_buf + offset, dump, "mode", s_storm_mode_defs[storm_bus->mode].name);
2637 	}
2638 
2639 	/* Store blocks */
2640 	for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) {
2641 		struct dbg_bus_block_data *block_bus = &dev_data->bus.blocks[block_id];
2642 		struct block_defs *block = s_block_defs[block_id];
2643 
2644 		if (!GET_FIELD(block_bus->data, DBG_BUS_BLOCK_DATA_ENABLE_MASK))
2645 			continue;
2646 
2647 		/* Dump section header */
2648 		offset += ecore_dump_section_hdr(dump_buf + offset, dump, "bus_input", 4);
2649 		offset += ecore_dump_str_param(dump_buf + offset, dump, "name", block->name);
2650 		offset += ecore_dump_num_param(dump_buf + offset, dump, "line", block_bus->line_num);
2651 		offset += ecore_dump_num_param(dump_buf + offset, dump, "en", GET_FIELD(block_bus->data, DBG_BUS_BLOCK_DATA_ENABLE_MASK));
2652 		offset += ecore_dump_num_param(dump_buf + offset, dump, "shr", GET_FIELD(block_bus->data, DBG_BUS_BLOCK_DATA_RIGHT_SHIFT));
2653 	}
2654 
2655 	return offset;
2656 }
2657 
2658 /* Dumps the Debug Bus header (params, inputs, data header) to the specified
2659  * buffer. Returns the dumped size in dwords.
2660  */
ecore_bus_dump_hdr(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u32 * dump_buf,bool dump)2661 static u32 ecore_bus_dump_hdr(struct ecore_hwfn *p_hwfn,
2662 							  struct ecore_ptt *p_ptt,
2663 							  u32 *dump_buf,
2664 							  bool dump)
2665 {
2666 	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
2667 	char hw_id_mask_str[16];
2668 	u32 offset = 0;
2669 
2670 	if (OSAL_SNPRINTF(hw_id_mask_str, sizeof(hw_id_mask_str), "0x%x", dev_data->bus.hw_id_mask) < 0)
2671 		DP_NOTICE(p_hwfn, true, "Unexpected debug error: invalid HW ID mask\n");
2672 
2673 	/* Dump global params */
2674 	offset += ecore_dump_common_global_params(p_hwfn, p_ptt, dump_buf + offset, dump, 5);
2675 	offset += ecore_dump_str_param(dump_buf + offset, dump, "dump-type", "debug-bus");
2676 	offset += ecore_dump_str_param(dump_buf + offset, dump, "wrap-mode", dev_data->bus.one_shot_en ? "one-shot" : "wrap-around");
2677 	offset += ecore_dump_num_param(dump_buf + offset, dump, "hw-dwords", dev_data->bus.hw_dwords);
2678 	offset += ecore_dump_str_param(dump_buf + offset, dump, "hw-id-mask", hw_id_mask_str);
2679 	offset += ecore_dump_str_param(dump_buf + offset, dump, "target", s_dbg_target_names[dev_data->bus.target]);
2680 
2681 	offset += ecore_bus_dump_inputs(p_hwfn, dump_buf + offset, dump);
2682 
2683 	if (dev_data->bus.target != DBG_BUS_TARGET_ID_NIG) {
2684 		u32 recorded_dwords = 0;
2685 
2686 		if (dump)
2687 			recorded_dwords = ecore_bus_dump_data(p_hwfn, p_ptt, OSAL_NULL, false);
2688 
2689 		offset += ecore_dump_section_hdr(dump_buf + offset, dump, "bus_data", 1);
2690 		offset += ecore_dump_num_param(dump_buf + offset, dump, "size", recorded_dwords);
2691 	}
2692 
2693 	return offset;
2694 }
2695 
ecore_is_mode_match(struct ecore_hwfn * p_hwfn,u16 * modes_buf_offset)2696 static bool ecore_is_mode_match(struct ecore_hwfn *p_hwfn,
2697 								u16 *modes_buf_offset)
2698 {
2699 	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
2700 	bool arg1, arg2;
2701 	u8 tree_val;
2702 
2703 	/* Get next element from modes tree buffer */
2704 	tree_val = ((u8*)s_dbg_arrays[BIN_BUF_DBG_MODE_TREE].ptr)[(*modes_buf_offset)++];
2705 
2706 	switch (tree_val) {
2707 	case INIT_MODE_OP_NOT:
2708 		return !ecore_is_mode_match(p_hwfn, modes_buf_offset);
2709 	case INIT_MODE_OP_OR:
2710 	case INIT_MODE_OP_AND:
2711 		arg1 = ecore_is_mode_match(p_hwfn, modes_buf_offset);
2712 		arg2 = ecore_is_mode_match(p_hwfn, modes_buf_offset);
2713 		return (tree_val == INIT_MODE_OP_OR) ? (arg1 || arg2) : (arg1 && arg2);
2714 	default: return dev_data->mode_enable[tree_val - MAX_INIT_MODE_OPS] > 0;
2715 	}
2716 }
2717 
2718 /* Returns true if the specified entity (indicated by GRC param) should be
2719  * included in the dump, false otherwise.
2720  */
ecore_grc_is_included(struct ecore_hwfn * p_hwfn,enum dbg_grc_params grc_param)2721 static bool ecore_grc_is_included(struct ecore_hwfn *p_hwfn,
2722 								  enum dbg_grc_params grc_param)
2723 {
2724 	return ecore_grc_get_param(p_hwfn, grc_param) > 0;
2725 }
2726 
2727 /* Returns true of the specified Storm should be included in the dump, false
2728  * otherwise.
2729  */
ecore_grc_is_storm_included(struct ecore_hwfn * p_hwfn,enum dbg_storms storm)2730 static bool ecore_grc_is_storm_included(struct ecore_hwfn *p_hwfn,
2731 										enum dbg_storms storm)
2732 {
2733 	return ecore_grc_get_param(p_hwfn, (enum dbg_grc_params)storm) > 0;
2734 }
2735 
2736 /* Returns true if the specified memory should be included in the dump, false
2737  * otherwise.
2738  */
ecore_grc_is_mem_included(struct ecore_hwfn * p_hwfn,enum block_id block_id,u8 mem_group_id)2739 static bool ecore_grc_is_mem_included(struct ecore_hwfn *p_hwfn,
2740 									  enum block_id block_id,
2741 									  u8 mem_group_id)
2742 {
2743 	struct block_defs *block = s_block_defs[block_id];
2744 	u8 i;
2745 
2746 	/* Check Storm match */
2747 	if (block->associated_to_storm &&
2748 		!ecore_grc_is_storm_included(p_hwfn, (enum dbg_storms)block->storm_id))
2749 		return false;
2750 
2751 	for (i = 0; i < NUM_BIG_RAM_TYPES; i++) {
2752 		struct big_ram_defs *big_ram = &s_big_ram_defs[i];
2753 
2754 		if (mem_group_id == big_ram->mem_group_id || mem_group_id == big_ram->ram_mem_group_id)
2755 			return ecore_grc_is_included(p_hwfn, big_ram->grc_param);
2756 	}
2757 
2758 	switch (mem_group_id) {
2759 	case MEM_GROUP_PXP_ILT:
2760 	case MEM_GROUP_PXP_MEM:
2761 		return ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_PXP);
2762 	case MEM_GROUP_RAM:
2763 		return ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_RAM);
2764 	case MEM_GROUP_PBUF:
2765 		return ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_PBUF);
2766 	case MEM_GROUP_CAU_MEM:
2767 	case MEM_GROUP_CAU_SB:
2768 	case MEM_GROUP_CAU_PI:
2769 		return ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_CAU);
2770 	case MEM_GROUP_QM_MEM:
2771 		return ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_QM);
2772 	case MEM_GROUP_CFC_MEM:
2773 	case MEM_GROUP_CONN_CFC_MEM:
2774 	case MEM_GROUP_TASK_CFC_MEM:
2775 		return ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_CFC);
2776 	case MEM_GROUP_IGU_MEM:
2777 	case MEM_GROUP_IGU_MSIX:
2778 		return ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_IGU);
2779 	case MEM_GROUP_MULD_MEM:
2780 		return ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_MULD);
2781 	case MEM_GROUP_PRS_MEM:
2782 		return ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_PRS);
2783 	case MEM_GROUP_DMAE_MEM:
2784 		return ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_DMAE);
2785 	case MEM_GROUP_TM_MEM:
2786 		return ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_TM);
2787 	case MEM_GROUP_SDM_MEM:
2788 		return ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_SDM);
2789 	case MEM_GROUP_TDIF_CTX:
2790 	case MEM_GROUP_RDIF_CTX:
2791 		return ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_DIF);
2792 	case MEM_GROUP_CM_MEM:
2793 		return ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_CM);
2794 	case MEM_GROUP_IOR:
2795 		return ecore_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_IOR);
2796 	default:
2797 		return true;
2798 	}
2799 }
2800 
2801 /* Stalls all Storms */
ecore_grc_stall_storms(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,bool stall)2802 static void ecore_grc_stall_storms(struct ecore_hwfn *p_hwfn,
2803 								   struct ecore_ptt *p_ptt,
2804 								   bool stall)
2805 {
2806 	u32 reg_addr;
2807 	u8 storm_id;
2808 
2809 	for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) {
2810 		if (!ecore_grc_is_storm_included(p_hwfn, (enum dbg_storms)storm_id))
2811 			continue;
2812 
2813 		reg_addr = s_storm_defs[storm_id].sem_fast_mem_addr + SEM_FAST_REG_STALL_0_BB_K2;
2814 		ecore_wr(p_hwfn, p_ptt, reg_addr, stall ? 1 : 0);
2815 	}
2816 
2817 	OSAL_MSLEEP(STALL_DELAY_MS);
2818 }
2819 
2820 /* Takes all blocks out of reset */
ecore_grc_unreset_blocks(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt)2821 static void ecore_grc_unreset_blocks(struct ecore_hwfn *p_hwfn,
2822 									 struct ecore_ptt *p_ptt)
2823 {
2824 	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
2825 	u32 reg_val[MAX_DBG_RESET_REGS] = { 0 };
2826 	u32 block_id, i;
2827 
2828 	/* Fill reset regs values */
2829 	for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) {
2830 		struct block_defs *block = s_block_defs[block_id];
2831 
2832 		if (block->has_reset_bit && block->unreset)
2833 			reg_val[block->reset_reg] |= (1 << block->reset_bit_offset);
2834 	}
2835 
2836 	/* Write reset registers */
2837 	for (i = 0; i < MAX_DBG_RESET_REGS; i++) {
2838 		if (!s_reset_regs_defs[i].exists[dev_data->chip_id])
2839 			continue;
2840 
2841 		reg_val[i] |= s_reset_regs_defs[i].unreset_val;
2842 
2843 		if (reg_val[i])
2844 			ecore_wr(p_hwfn, p_ptt, s_reset_regs_defs[i].addr + RESET_REG_UNRESET_OFFSET, reg_val[i]);
2845 	}
2846 }
2847 
2848 /* Returns the attention block data of the specified block */
ecore_get_block_attn_data(enum block_id block_id,enum dbg_attn_type attn_type)2849 static const struct dbg_attn_block_type_data* ecore_get_block_attn_data(enum block_id block_id,
2850 																		enum dbg_attn_type attn_type)
2851 {
2852 	const struct dbg_attn_block *base_attn_block_arr = (const struct dbg_attn_block*)s_dbg_arrays[BIN_BUF_DBG_ATTN_BLOCKS].ptr;
2853 
2854 	return &base_attn_block_arr[block_id].per_type_data[attn_type];
2855 }
2856 
2857 /* Returns the attention registers of the specified block */
ecore_get_block_attn_regs(enum block_id block_id,enum dbg_attn_type attn_type,u8 * num_attn_regs)2858 static const struct dbg_attn_reg* ecore_get_block_attn_regs(enum block_id block_id,
2859 															enum dbg_attn_type attn_type,
2860 															u8 *num_attn_regs)
2861 {
2862 	const struct dbg_attn_block_type_data *block_type_data = ecore_get_block_attn_data(block_id, attn_type);
2863 
2864 	*num_attn_regs = block_type_data->num_regs;
2865 
2866 	return &((const struct dbg_attn_reg*)s_dbg_arrays[BIN_BUF_DBG_ATTN_REGS].ptr)[block_type_data->regs_offset];
2867 }
2868 
2869 /* For each block, clear the status of all parities */
ecore_grc_clear_all_prty(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt)2870 static void ecore_grc_clear_all_prty(struct ecore_hwfn *p_hwfn,
2871 									 struct ecore_ptt *p_ptt)
2872 {
2873 	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
2874 	const struct dbg_attn_reg *attn_reg_arr;
2875 	u8 reg_idx, num_attn_regs;
2876 	u32 block_id;
2877 
2878 	for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) {
2879 		if (dev_data->block_in_reset[block_id])
2880 			continue;
2881 
2882 		attn_reg_arr = ecore_get_block_attn_regs((enum block_id)block_id, ATTN_TYPE_PARITY, &num_attn_regs);
2883 
2884 		for (reg_idx = 0; reg_idx < num_attn_regs; reg_idx++) {
2885 			const struct dbg_attn_reg *reg_data = &attn_reg_arr[reg_idx];
2886 			u16 modes_buf_offset;
2887 			bool eval_mode;
2888 
2889 			/* Check mode */
2890 			eval_mode = GET_FIELD(reg_data->mode.data, DBG_MODE_HDR_EVAL_MODE) > 0;
2891 			modes_buf_offset = GET_FIELD(reg_data->mode.data, DBG_MODE_HDR_MODES_BUF_OFFSET);
2892 
2893 			/* If Mode match: clear parity status */
2894 			if (!eval_mode || ecore_is_mode_match(p_hwfn, &modes_buf_offset))
2895 				ecore_rd(p_hwfn, p_ptt, DWORDS_TO_BYTES(reg_data->sts_clr_address));
2896 		}
2897 	}
2898 }
2899 
2900 /* Dumps GRC registers section header. Returns the dumped size in dwords.
2901  * the following parameters are dumped:
2902  * - count:	 no. of dumped entries
2903  * - split:	 split type
2904  * - id:	 split ID (dumped only if split_id >= 0)
2905  * - param_name: user parameter value (dumped only if param_name != OSAL_NULL
2906  *		 and param_val != OSAL_NULL).
2907  */
ecore_grc_dump_regs_hdr(u32 * dump_buf,bool dump,u32 num_reg_entries,const char * split_type,int split_id,const char * param_name,const char * param_val)2908 static u32 ecore_grc_dump_regs_hdr(u32 *dump_buf,
2909 								   bool dump,
2910 								   u32 num_reg_entries,
2911 								   const char *split_type,
2912 								   int split_id,
2913 								   const char *param_name,
2914 								   const char *param_val)
2915 {
2916 	u8 num_params = 2 + (split_id >= 0 ? 1 : 0) + (param_name ? 1 : 0);
2917 	u32 offset = 0;
2918 
2919 	offset += ecore_dump_section_hdr(dump_buf + offset, dump, "grc_regs", num_params);
2920 	offset += ecore_dump_num_param(dump_buf + offset, dump, "count", num_reg_entries);
2921 	offset += ecore_dump_str_param(dump_buf + offset, dump, "split", split_type);
2922 	if (split_id >= 0)
2923 		offset += ecore_dump_num_param(dump_buf + offset, dump, "id", split_id);
2924 	if (param_name && param_val)
2925 		offset += ecore_dump_str_param(dump_buf + offset, dump, param_name, param_val);
2926 
2927 	return offset;
2928 }
2929 
2930 /* Dumps the GRC registers in the specified address range.
2931  * Returns the dumped size in dwords.
2932  * The addr and len arguments are specified in dwords.
2933  */
ecore_grc_dump_addr_range(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u32 * dump_buf,bool dump,u32 addr,u32 len,bool wide_bus)2934 static u32 ecore_grc_dump_addr_range(struct ecore_hwfn *p_hwfn,
2935 									 struct ecore_ptt *p_ptt,
2936 									 u32 *dump_buf,
2937 									 bool dump,
2938 									 u32 addr,
2939 									 u32 len,
2940 									 bool wide_bus)
2941 {
2942 	u32 byte_addr = DWORDS_TO_BYTES(addr), offset = 0, i;
2943 
2944 	if (!dump)
2945 		return len;
2946 
2947 	for (i = 0; i < len; i++, byte_addr += BYTES_IN_DWORD, offset++)
2948 		*(dump_buf + offset) = ecore_rd(p_hwfn, p_ptt, byte_addr);
2949 
2950 	return offset;
2951 }
2952 
2953 /* Dumps GRC registers sequence header. Returns the dumped size in dwords.
2954  * The addr and len arguments are specified in dwords.
2955  */
ecore_grc_dump_reg_entry_hdr(u32 * dump_buf,bool dump,u32 addr,u32 len)2956 static u32 ecore_grc_dump_reg_entry_hdr(u32 *dump_buf,
2957 										bool dump,
2958 										u32 addr,
2959 										u32 len)
2960 {
2961 	if (dump)
2962 		*dump_buf = addr | (len << REG_DUMP_LEN_SHIFT);
2963 
2964 	return 1;
2965 }
2966 
2967 /* Dumps GRC registers sequence. Returns the dumped size in dwords.
2968  * The addr and len arguments are specified in dwords.
2969  */
ecore_grc_dump_reg_entry(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u32 * dump_buf,bool dump,u32 addr,u32 len,bool wide_bus)2970 static u32 ecore_grc_dump_reg_entry(struct ecore_hwfn *p_hwfn,
2971 									struct ecore_ptt *p_ptt,
2972 									u32 *dump_buf,
2973 									bool dump,
2974 									u32 addr,
2975 									u32 len,
2976 									bool wide_bus)
2977 {
2978 	u32 offset = 0;
2979 
2980 	offset += ecore_grc_dump_reg_entry_hdr(dump_buf, dump, addr, len);
2981 	offset += ecore_grc_dump_addr_range(p_hwfn, p_ptt, dump_buf + offset, dump, addr, len, wide_bus);
2982 
2983 	return offset;
2984 }
2985 
2986 /* Dumps GRC registers sequence with skip cycle.
2987  * Returns the dumped size in dwords.
2988  * - addr:	start GRC address in dwords
2989  * - total_len:	total no. of dwords to dump
2990  * - read_len:	no. consecutive dwords to read
2991  * - skip_len:	no. of dwords to skip (and fill with zeros)
2992  */
ecore_grc_dump_reg_entry_skip(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u32 * dump_buf,bool dump,u32 addr,u32 total_len,u32 read_len,u32 skip_len)2993 static u32 ecore_grc_dump_reg_entry_skip(struct ecore_hwfn *p_hwfn,
2994 										 struct ecore_ptt *p_ptt,
2995 										 u32 *dump_buf,
2996 										 bool dump,
2997 										 u32 addr,
2998 										 u32 total_len,
2999 										 u32 read_len,
3000 										 u32 skip_len)
3001 {
3002 	u32 offset = 0, reg_offset = 0;
3003 
3004 	offset += ecore_grc_dump_reg_entry_hdr(dump_buf, dump, addr, total_len);
3005 
3006 	if (!dump)
3007 		return offset + total_len;
3008 
3009 	while (reg_offset < total_len) {
3010 		u32 curr_len = OSAL_MIN_T(u32, read_len, total_len - reg_offset);
3011 
3012 		offset += ecore_grc_dump_addr_range(p_hwfn, p_ptt, dump_buf + offset, dump, addr, curr_len, false);
3013 		reg_offset += curr_len;
3014 		addr += curr_len;
3015 
3016 		if (reg_offset < total_len) {
3017 			curr_len = OSAL_MIN_T(u32, skip_len, total_len - skip_len);
3018 			OSAL_MEMSET(dump_buf + offset, 0, DWORDS_TO_BYTES(curr_len));
3019 			offset += curr_len;
3020 			reg_offset += curr_len;
3021 			addr += curr_len;
3022 		}
3023 	}
3024 
3025 	return offset;
3026 }
3027 
3028 /* Dumps GRC registers entries. Returns the dumped size in dwords. */
ecore_grc_dump_regs_entries(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,struct dbg_array input_regs_arr,u32 * dump_buf,bool dump,bool block_enable[MAX_BLOCK_ID],u32 * num_dumped_reg_entries)3029 static u32 ecore_grc_dump_regs_entries(struct ecore_hwfn *p_hwfn,
3030 									   struct ecore_ptt *p_ptt,
3031 									   struct dbg_array input_regs_arr,
3032 									   u32 *dump_buf,
3033 									   bool dump,
3034 									   bool block_enable[MAX_BLOCK_ID],
3035 									   u32 *num_dumped_reg_entries)
3036 {
3037 	u32 i, offset = 0, input_offset = 0;
3038 	bool mode_match = true;
3039 
3040 	*num_dumped_reg_entries = 0;
3041 
3042 	while (input_offset < input_regs_arr.size_in_dwords) {
3043 		const struct dbg_dump_cond_hdr* cond_hdr = (const struct dbg_dump_cond_hdr*)&input_regs_arr.ptr[input_offset++];
3044 		u16 modes_buf_offset;
3045 		bool eval_mode;
3046 
3047 		/* Check mode/block */
3048 		eval_mode = GET_FIELD(cond_hdr->mode.data, DBG_MODE_HDR_EVAL_MODE) > 0;
3049 		if (eval_mode) {
3050 			modes_buf_offset = GET_FIELD(cond_hdr->mode.data, DBG_MODE_HDR_MODES_BUF_OFFSET);
3051 			mode_match = ecore_is_mode_match(p_hwfn, &modes_buf_offset);
3052 		}
3053 
3054 		if (!mode_match || !block_enable[cond_hdr->block_id]) {
3055 			input_offset += cond_hdr->data_size;
3056 			continue;
3057 		}
3058 
3059 		for (i = 0; i < cond_hdr->data_size; i++, input_offset++) {
3060 			const struct dbg_dump_reg *reg = (const struct dbg_dump_reg*)&input_regs_arr.ptr[input_offset];
3061 
3062 			offset += ecore_grc_dump_reg_entry(p_hwfn, p_ptt, dump_buf + offset, dump,
3063 												GET_FIELD(reg->data, DBG_DUMP_REG_ADDRESS),
3064 												GET_FIELD(reg->data, DBG_DUMP_REG_LENGTH),
3065 												GET_FIELD(reg->data, DBG_DUMP_REG_WIDE_BUS));
3066 			(*num_dumped_reg_entries)++;
3067 		}
3068 	}
3069 
3070 	return offset;
3071 }
3072 
3073 /* Dumps GRC registers entries. Returns the dumped size in dwords. */
ecore_grc_dump_split_data(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,struct dbg_array input_regs_arr,u32 * dump_buf,bool dump,bool block_enable[MAX_BLOCK_ID],const char * split_type_name,u32 split_id,const char * param_name,const char * param_val)3074 static u32 ecore_grc_dump_split_data(struct ecore_hwfn *p_hwfn,
3075 									 struct ecore_ptt *p_ptt,
3076 									 struct dbg_array input_regs_arr,
3077 									 u32 *dump_buf,
3078 									 bool dump,
3079 									 bool block_enable[MAX_BLOCK_ID],
3080 									 const char *split_type_name,
3081 									 u32 split_id,
3082 									 const char *param_name,
3083 									 const char *param_val)
3084 {
3085 	u32 num_dumped_reg_entries, offset;
3086 
3087 	/* Calculate register dump header size (and skip it for now) */
3088 	offset = ecore_grc_dump_regs_hdr(dump_buf, false, 0, split_type_name, split_id, param_name, param_val);
3089 
3090 	/* Dump registers */
3091 	offset += ecore_grc_dump_regs_entries(p_hwfn, p_ptt, input_regs_arr, dump_buf + offset, dump, block_enable, &num_dumped_reg_entries);
3092 
3093 	/* Write register dump header */
3094 	if (dump && num_dumped_reg_entries > 0)
3095 		ecore_grc_dump_regs_hdr(dump_buf, dump, num_dumped_reg_entries, split_type_name, split_id, param_name, param_val);
3096 
3097 	return num_dumped_reg_entries > 0 ? offset : 0;
3098 }
3099 
3100 /* Dumps registers according to the input registers array. Returns the dumped
3101  * size in dwords.
3102  */
ecore_grc_dump_registers(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u32 * dump_buf,bool dump,bool block_enable[MAX_BLOCK_ID],const char * param_name,const char * param_val)3103 static u32 ecore_grc_dump_registers(struct ecore_hwfn *p_hwfn,
3104 									struct ecore_ptt *p_ptt,
3105 									u32 *dump_buf,
3106 									bool dump,
3107 									bool block_enable[MAX_BLOCK_ID],
3108 									const char *param_name,
3109 									const char *param_val)
3110 {
3111 	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
3112 	struct chip_platform_defs *chip_platform;
3113 	u32 offset = 0, input_offset = 0;
3114 	u8 port_id, pf_id, vf_id;
3115 
3116 	chip_platform = &s_chip_defs[dev_data->chip_id].per_platform[dev_data->platform_id];
3117 
3118 	if (dump)
3119 		DP_VERBOSE(p_hwfn, ECORE_MSG_DEBUG, "Dumping registers...\n");
3120 
3121 	while (input_offset < s_dbg_arrays[BIN_BUF_DBG_DUMP_REG].size_in_dwords) {
3122 		const struct dbg_dump_split_hdr *split_hdr;
3123 		struct dbg_array curr_input_regs_arr;
3124 		u32 split_data_size;
3125 		u8 split_type_id;
3126 
3127 		split_hdr = (const struct dbg_dump_split_hdr*)&s_dbg_arrays[BIN_BUF_DBG_DUMP_REG].ptr[input_offset++];
3128 		split_type_id = GET_FIELD(split_hdr->hdr, DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID);
3129 		split_data_size = GET_FIELD(split_hdr->hdr, DBG_DUMP_SPLIT_HDR_DATA_SIZE);
3130 		curr_input_regs_arr.ptr = &s_dbg_arrays[BIN_BUF_DBG_DUMP_REG].ptr[input_offset];
3131 		curr_input_regs_arr.size_in_dwords = split_data_size;
3132 
3133 		switch(split_type_id) {
3134 		case SPLIT_TYPE_NONE:
3135 			offset += ecore_grc_dump_split_data(p_hwfn, p_ptt, curr_input_regs_arr, dump_buf + offset, dump, block_enable, "eng", (u32)(-1), param_name, param_val);
3136 			break;
3137 
3138 		case SPLIT_TYPE_PORT:
3139 			for (port_id = 0; port_id < chip_platform->num_ports; port_id++) {
3140 				if (dump)
3141 					ecore_port_pretend(p_hwfn, p_ptt, port_id);
3142 				offset += ecore_grc_dump_split_data(p_hwfn, p_ptt, curr_input_regs_arr,