1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved. 23 * Copyright (c) 2017, Joyent, Inc. 24 */ 25 26 #include <sys/sysmacros.h> 27 #include <sys/types.h> 28 #include <sys/kmem.h> 29 #include <sys/modctl.h> 30 #include <sys/ddi.h> 31 #include <sys/sunddi.h> 32 #include <sys/sunndi.h> 33 #include <sys/fm/protocol.h> 34 #include <sys/fm/util.h> 35 #include <sys/fm/io/ddi.h> 36 #include <sys/fm/io/pci.h> 37 #include <sys/promif.h> 38 #include <sys/disp.h> 39 #include <sys/atomic.h> 40 #include <sys/pcie.h> 41 #include <sys/pci_cap.h> 42 #include <sys/pcie_impl.h> 43 44 #define PF_PCIE_BDG_ERR (PCIE_DEVSTS_FE_DETECTED | PCIE_DEVSTS_NFE_DETECTED | \ 45 PCIE_DEVSTS_CE_DETECTED) 46 47 #define PF_PCI_BDG_ERR (PCI_STAT_S_SYSERR | PCI_STAT_S_TARG_AB | \ 48 PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB | PCI_STAT_S_PERROR) 49 50 #define PF_AER_FATAL_ERR (PCIE_AER_UCE_DLP | PCIE_AER_UCE_SD |\ 51 PCIE_AER_UCE_FCP | PCIE_AER_UCE_RO | PCIE_AER_UCE_MTLP) 52 #define PF_AER_NON_FATAL_ERR (PCIE_AER_UCE_PTLP | PCIE_AER_UCE_TO | \ 53 PCIE_AER_UCE_CA | PCIE_AER_UCE_ECRC | PCIE_AER_UCE_UR) 54 55 #define PF_SAER_FATAL_ERR (PCIE_AER_SUCE_USC_MSG_DATA_ERR | \ 56 PCIE_AER_SUCE_UC_ATTR_ERR | PCIE_AER_SUCE_UC_ADDR_ERR | \ 57 PCIE_AER_SUCE_SERR_ASSERT) 58 #define PF_SAER_NON_FATAL_ERR (PCIE_AER_SUCE_TA_ON_SC | \ 59 PCIE_AER_SUCE_MA_ON_SC | PCIE_AER_SUCE_RCVD_TA | \ 60 PCIE_AER_SUCE_RCVD_MA | PCIE_AER_SUCE_USC_ERR | \ 61 PCIE_AER_SUCE_UC_DATA_ERR | PCIE_AER_SUCE_TIMER_EXPIRED | \ 62 PCIE_AER_SUCE_PERR_ASSERT | PCIE_AER_SUCE_INTERNAL_ERR) 63 64 #define PF_PCI_PARITY_ERR (PCI_STAT_S_PERROR | PCI_STAT_PERROR) 65 66 #define PF_FIRST_AER_ERR(bit, adv) \ 67 (bit & (1 << (adv->pcie_adv_ctl & PCIE_AER_CTL_FST_ERR_PTR_MASK))) 68 69 #define HAS_AER_LOGS(pfd_p, bit) \ 70 (PCIE_HAS_AER(pfd_p->pe_bus_p) && \ 71 PF_FIRST_AER_ERR(bit, PCIE_ADV_REG(pfd_p))) 72 73 #define PF_FIRST_SAER_ERR(bit, adv) \ 74 (bit & (1 << (adv->pcie_sue_ctl & PCIE_AER_SCTL_FST_ERR_PTR_MASK))) 75 76 #define HAS_SAER_LOGS(pfd_p, bit) \ 77 (PCIE_HAS_AER(pfd_p->pe_bus_p) && \ 78 PF_FIRST_SAER_ERR(bit, PCIE_ADV_BDG_REG(pfd_p))) 79 80 #define GET_SAER_CMD(pfd_p) \ 81 ((PCIE_ADV_BDG_HDR(pfd_p, 1) >> \ 82 PCIE_AER_SUCE_HDR_CMD_LWR_SHIFT) & PCIE_AER_SUCE_HDR_CMD_LWR_MASK) 83 84 #define CE_ADVISORY(pfd_p) \ 85 (PCIE_ADV_REG(pfd_p)->pcie_ce_status & PCIE_AER_CE_AD_NFE) 86 87 /* PCIe Fault Fabric Error analysis table */ 88 typedef struct pf_fab_err_tbl { 89 uint32_t bit; /* Error bit */ 90 int (*handler)(); /* Error handling fuction */ 91 uint16_t affected_flags; /* Primary affected flag */ 92 /* 93 * Secondary affected flag, effective when the information 94 * indicated by the primary flag is not available, eg. 95 * PF_AFFECTED_AER/SAER/ADDR 96 */ 97 uint16_t sec_affected_flags; 98 } pf_fab_err_tbl_t; 99 100 static pcie_bus_t *pf_is_ready(dev_info_t *); 101 /* Functions for scanning errors */ 102 static int pf_default_hdl(dev_info_t *, pf_impl_t *); 103 static int pf_dispatch(dev_info_t *, pf_impl_t *, boolean_t); 104 static boolean_t pf_in_addr_range(pcie_bus_t *, uint64_t); 105 106 /* Functions for gathering errors */ 107 static void pf_pcix_ecc_regs_gather(pf_pcix_ecc_regs_t *pcix_ecc_regs, 108 pcie_bus_t *bus_p, boolean_t bdg); 109 static void pf_pcix_regs_gather(pf_data_t *pfd_p, pcie_bus_t *bus_p); 110 static void pf_pcie_regs_gather(pf_data_t *pfd_p, pcie_bus_t *bus_p); 111 static void pf_pci_regs_gather(pf_data_t *pfd_p, pcie_bus_t *bus_p); 112 static int pf_dummy_cb(dev_info_t *, ddi_fm_error_t *, const void *); 113 static void pf_en_dq(pf_data_t *pfd_p, pf_impl_t *impl_p); 114 115 /* Functions for analysing errors */ 116 static int pf_analyse_error(ddi_fm_error_t *, pf_impl_t *); 117 static void pf_adjust_for_no_aer(pf_data_t *); 118 static void pf_adjust_for_no_saer(pf_data_t *); 119 static pf_data_t *pf_get_pcie_bridge(pf_data_t *, pcie_req_id_t); 120 static pf_data_t *pf_get_parent_pcie_bridge(pf_data_t *); 121 static boolean_t pf_matched_in_rc(pf_data_t *, pf_data_t *, 122 uint32_t); 123 static int pf_analyse_error_tbl(ddi_fm_error_t *, pf_impl_t *, 124 pf_data_t *, const pf_fab_err_tbl_t *, uint32_t); 125 static int pf_analyse_ca_ur(ddi_fm_error_t *, uint32_t, 126 pf_data_t *, pf_data_t *); 127 static int pf_analyse_ma_ta(ddi_fm_error_t *, uint32_t, 128 pf_data_t *, pf_data_t *); 129 static int pf_analyse_pci(ddi_fm_error_t *, uint32_t, 130 pf_data_t *, pf_data_t *); 131 static int pf_analyse_perr_assert(ddi_fm_error_t *, uint32_t, 132 pf_data_t *, pf_data_t *); 133 static int pf_analyse_ptlp(ddi_fm_error_t *, uint32_t, 134 pf_data_t *, pf_data_t *); 135 static int pf_analyse_sc(ddi_fm_error_t *, uint32_t, 136 pf_data_t *, pf_data_t *); 137 static int pf_analyse_to(ddi_fm_error_t *, uint32_t, 138 pf_data_t *, pf_data_t *); 139 static int pf_analyse_uc(ddi_fm_error_t *, uint32_t, 140 pf_data_t *, pf_data_t *); 141 static int pf_analyse_uc_data(ddi_fm_error_t *, uint32_t, 142 pf_data_t *, pf_data_t *); 143 static int pf_no_panic(ddi_fm_error_t *, uint32_t, 144 pf_data_t *, pf_data_t *); 145 static int pf_panic(ddi_fm_error_t *, uint32_t, 146 pf_data_t *, pf_data_t *); 147 static void pf_send_ereport(ddi_fm_error_t *, pf_impl_t *); 148 static int pf_fm_callback(dev_info_t *dip, ddi_fm_error_t *derr); 149 150 /* PCIe Fabric Handle Lookup Support Functions. */ 151 static int pf_hdl_child_lookup(dev_info_t *, ddi_fm_error_t *, uint32_t, 152 uint64_t, pcie_req_id_t); 153 static int pf_hdl_compare(dev_info_t *, ddi_fm_error_t *, uint32_t, uint64_t, 154 pcie_req_id_t, ndi_fmc_t *); 155 static int pf_log_hdl_lookup(dev_info_t *, ddi_fm_error_t *, pf_data_t *, 156 boolean_t); 157 158 static int pf_handler_enter(dev_info_t *, pf_impl_t *); 159 static void pf_handler_exit(dev_info_t *); 160 static void pf_reset_pfd(pf_data_t *); 161 162 boolean_t pcie_full_scan = B_FALSE; /* Force to always do a full scan */ 163 int pcie_disable_scan = 0; /* Disable fabric scan */ 164 165 /* Inform interested parties that error handling is about to begin. */ 166 /* ARGSUSED */ 167 void 168 pf_eh_enter(pcie_bus_t *bus_p) 169 { 170 } 171 172 /* Inform interested parties that error handling has ended. */ 173 void 174 pf_eh_exit(pcie_bus_t *bus_p) 175 { 176 pcie_bus_t *rbus_p = PCIE_DIP2BUS(bus_p->bus_rp_dip); 177 pf_data_t *root_pfd_p = PCIE_BUS2PFD(rbus_p); 178 pf_data_t *pfd_p; 179 uint_t intr_type = PCIE_ROOT_EH_SRC(root_pfd_p)->intr_type; 180 181 pciev_eh_exit(root_pfd_p, intr_type); 182 183 /* Clear affected device info and INTR SRC */ 184 for (pfd_p = root_pfd_p; pfd_p; pfd_p = pfd_p->pe_next) { 185 PFD_AFFECTED_DEV(pfd_p)->pe_affected_flags = 0; 186 PFD_AFFECTED_DEV(pfd_p)->pe_affected_bdf = PCIE_INVALID_BDF; 187 if (PCIE_IS_ROOT(PCIE_PFD2BUS(pfd_p))) { 188 PCIE_ROOT_EH_SRC(pfd_p)->intr_type = PF_INTR_TYPE_NONE; 189 PCIE_ROOT_EH_SRC(pfd_p)->intr_data = NULL; 190 } 191 } 192 } 193 194 /* 195 * Scan Fabric is the entry point for PCI/PCIe IO fabric errors. The 196 * caller may create a local pf_data_t with the "root fault" 197 * information populated to either do a precise or full scan. More 198 * than one pf_data_t maybe linked together if there are multiple 199 * errors. Only a PCIe compliant Root Port device may pass in NULL 200 * for the root_pfd_p. 201 * 202 * "Root Complexes" such as NPE and PX should call scan_fabric using itself as 203 * the rdip. PCIe Root ports should call pf_scan_fabric using it's parent as 204 * the rdip. 205 * 206 * Scan fabric initiated from RCs are likely due to a fabric message, traps or 207 * any RC detected errors that propagated to/from the fabric. 208 * 209 * This code assumes that by the time pf_scan_fabric is 210 * called, pf_handler_enter has NOT been called on the rdip. 211 */ 212 int 213 pf_scan_fabric(dev_info_t *rdip, ddi_fm_error_t *derr, pf_data_t *root_pfd_p) 214 { 215 pf_impl_t impl; 216 pf_data_t *pfd_p, *pfd_head_p, *pfd_tail_p; 217 int scan_flag = PF_SCAN_SUCCESS; 218 int analyse_flag = PF_ERR_NO_ERROR; 219 boolean_t full_scan = pcie_full_scan; 220 221 if (pcie_disable_scan) 222 return (analyse_flag); 223 224 /* Find the head and tail of this link list */ 225 pfd_head_p = root_pfd_p; 226 for (pfd_tail_p = root_pfd_p; pfd_tail_p && pfd_tail_p->pe_next; 227 pfd_tail_p = pfd_tail_p->pe_next) 228 ; 229 230 /* Save head/tail */ 231 impl.pf_total = 0; 232 impl.pf_derr = derr; 233 impl.pf_dq_head_p = pfd_head_p; 234 impl.pf_dq_tail_p = pfd_tail_p; 235 236 /* If scan is initiated from RP then RP itself must be scanned. */ 237 if (PCIE_IS_RP(PCIE_DIP2BUS(rdip)) && pf_is_ready(rdip) && 238 !root_pfd_p) { 239 scan_flag = pf_handler_enter(rdip, &impl); 240 if (scan_flag & PF_SCAN_DEADLOCK) 241 goto done; 242 243 scan_flag = pf_default_hdl(rdip, &impl); 244 if (scan_flag & PF_SCAN_NO_ERR_IN_CHILD) 245 goto done; 246 } 247 248 /* 249 * Scan the fabric using the scan_bdf and scan_addr in error q. 250 * scan_bdf will be valid in the following cases: 251 * - Fabric message 252 * - Poisoned TLP 253 * - Signaled UR/CA 254 * - Received UR/CA 255 * - PIO load failures 256 */ 257 for (pfd_p = impl.pf_dq_head_p; pfd_p && PFD_IS_ROOT(pfd_p); 258 pfd_p = pfd_p->pe_next) { 259 impl.pf_fault = PCIE_ROOT_FAULT(pfd_p); 260 261 if (PFD_IS_RC(pfd_p)) 262 impl.pf_total++; 263 264 if (impl.pf_fault->full_scan) 265 full_scan = B_TRUE; 266 267 if (full_scan || 268 PCIE_CHECK_VALID_BDF(impl.pf_fault->scan_bdf) || 269 impl.pf_fault->scan_addr) 270 scan_flag |= pf_dispatch(rdip, &impl, full_scan); 271 272 if (full_scan) 273 break; 274 } 275 276 done: 277 /* 278 * If this is due to safe access, don't analyze the errors and return 279 * success regardless of how scan fabric went. 280 */ 281 if (derr->fme_flag != DDI_FM_ERR_UNEXPECTED) { 282 analyse_flag = PF_ERR_NO_PANIC; 283 } else { 284 analyse_flag = pf_analyse_error(derr, &impl); 285 } 286 287 pf_send_ereport(derr, &impl); 288 289 /* 290 * Check if any hardened driver's callback reported a panic. 291 * If so panic. 292 */ 293 if (scan_flag & PF_SCAN_CB_FAILURE) 294 analyse_flag |= PF_ERR_PANIC; 295 296 /* 297 * If a deadlock was detected, panic the system as error analysis has 298 * been compromised. 299 */ 300 if (scan_flag & PF_SCAN_DEADLOCK) 301 analyse_flag |= PF_ERR_PANIC_DEADLOCK; 302 303 derr->fme_status = PF_ERR2DDIFM_ERR(scan_flag); 304 305 return (analyse_flag); 306 } 307 308 void 309 pcie_force_fullscan(void) 310 { 311 pcie_full_scan = B_TRUE; 312 } 313 314 /* 315 * pf_dispatch walks the device tree and calls the pf_default_hdl if the device 316 * falls in the error path. 317 * 318 * Returns PF_SCAN_* flags 319 */ 320 static int 321 pf_dispatch(dev_info_t *pdip, pf_impl_t *impl, boolean_t full_scan) 322 { 323 dev_info_t *dip; 324 pcie_req_id_t rid = impl->pf_fault->scan_bdf; 325 pcie_bus_t *bus_p; 326 int scan_flag = PF_SCAN_SUCCESS; 327 328 for (dip = ddi_get_child(pdip); dip; dip = ddi_get_next_sibling(dip)) { 329 /* Make sure dip is attached and ready */ 330 if (!(bus_p = pf_is_ready(dip))) 331 continue; 332 333 scan_flag |= pf_handler_enter(dip, impl); 334 if (scan_flag & PF_SCAN_DEADLOCK) 335 break; 336 337 /* 338 * Handle this device if it is a: 339 * o Full Scan 340 * o PCI/PCI-X Device 341 * o Fault BDF = Device BDF 342 * o BDF/ADDR is in range of the Bridge/Switch 343 */ 344 if (full_scan || 345 (bus_p->bus_bdf == rid) || 346 pf_in_bus_range(bus_p, rid) || 347 pf_in_addr_range(bus_p, impl->pf_fault->scan_addr)) { 348 int hdl_flag = pf_default_hdl(dip, impl); 349 scan_flag |= hdl_flag; 350 351 /* 352 * A bridge may have detected no errors in which case 353 * there is no need to scan further down. 354 */ 355 if (hdl_flag & PF_SCAN_NO_ERR_IN_CHILD) 356 continue; 357 } else { 358 pf_handler_exit(dip); 359 continue; 360 } 361 362 /* match or in bridge bus-range */ 363 switch (bus_p->bus_dev_type) { 364 case PCIE_PCIECAP_DEV_TYPE_PCIE2PCI: 365 case PCIE_PCIECAP_DEV_TYPE_PCI2PCIE: 366 scan_flag |= pf_dispatch(dip, impl, B_TRUE); 367 break; 368 case PCIE_PCIECAP_DEV_TYPE_UP: 369 case PCIE_PCIECAP_DEV_TYPE_DOWN: 370 case PCIE_PCIECAP_DEV_TYPE_ROOT: 371 { 372 pf_data_t *pfd_p = PCIE_BUS2PFD(bus_p); 373 pf_pci_err_regs_t *err_p = PCI_ERR_REG(pfd_p); 374 pf_pci_bdg_err_regs_t *serr_p = PCI_BDG_ERR_REG(pfd_p); 375 /* 376 * Continue if the fault BDF != the switch or there is a 377 * parity error 378 */ 379 if ((bus_p->bus_bdf != rid) || 380 (err_p->pci_err_status & PF_PCI_PARITY_ERR) || 381 (serr_p->pci_bdg_sec_stat & PF_PCI_PARITY_ERR)) 382 scan_flag |= pf_dispatch(dip, impl, full_scan); 383 break; 384 } 385 case PCIE_PCIECAP_DEV_TYPE_PCIE_DEV: 386 case PCIE_PCIECAP_DEV_TYPE_PCI_DEV: 387 /* 388 * Reached a PCIe end point so stop. Note dev_type 389 * PCI_DEV is just a PCIe device that requires IO Space 390 */ 391 break; 392 case PCIE_PCIECAP_DEV_TYPE_PCI_PSEUDO: 393 if (PCIE_IS_BDG(bus_p)) 394 scan_flag |= pf_dispatch(dip, impl, B_TRUE); 395 break; 396 default: 397 ASSERT(B_FALSE); 398 } 399 } 400 return (scan_flag); 401 } 402 403 /* Returns whether the "bdf" is in the bus range of a switch/bridge */ 404 boolean_t 405 pf_in_bus_range(pcie_bus_t *bus_p, pcie_req_id_t bdf) 406 { 407 pci_bus_range_t *br_p = &bus_p->bus_bus_range; 408 uint8_t bus_no = (bdf & PCIE_REQ_ID_BUS_MASK) >> 409 PCIE_REQ_ID_BUS_SHIFT; 410 411 /* check if given bdf falls within bridge's bus range */ 412 if (PCIE_IS_BDG(bus_p) && 413 ((bus_no >= br_p->lo) && (bus_no <= br_p->hi))) 414 return (B_TRUE); 415 else 416 return (B_FALSE); 417 } 418 419 /* 420 * Return whether the "addr" is in the assigned addr of a device. 421 */ 422 boolean_t 423 pf_in_assigned_addr(pcie_bus_t *bus_p, uint64_t addr) 424 { 425 uint_t i; 426 uint64_t low, hi; 427 pci_regspec_t *assign_p = bus_p->bus_assigned_addr; 428 429 for (i = 0; i < bus_p->bus_assigned_entries; i++, assign_p++) { 430 low = assign_p->pci_phys_low; 431 hi = low + assign_p->pci_size_low; 432 if ((addr < hi) && (addr >= low)) 433 return (B_TRUE); 434 } 435 return (B_FALSE); 436 } 437 438 /* 439 * Returns whether the "addr" is in the addr range of a switch/bridge, or if the 440 * "addr" is in the assigned addr of a device. 441 */ 442 static boolean_t 443 pf_in_addr_range(pcie_bus_t *bus_p, uint64_t addr) 444 { 445 uint_t i; 446 uint64_t low, hi; 447 ppb_ranges_t *ranges_p = bus_p->bus_addr_ranges; 448 449 if (!addr) 450 return (B_FALSE); 451 452 /* check if given address belongs to this device */ 453 if (pf_in_assigned_addr(bus_p, addr)) 454 return (B_TRUE); 455 456 /* check if given address belongs to a child below this device */ 457 if (!PCIE_IS_BDG(bus_p)) 458 return (B_FALSE); 459 460 for (i = 0; i < bus_p->bus_addr_entries; i++, ranges_p++) { 461 switch (ranges_p->child_high & PCI_ADDR_MASK) { 462 case PCI_ADDR_IO: 463 case PCI_ADDR_MEM32: 464 low = ranges_p->child_low; 465 hi = ranges_p->size_low + low; 466 if ((addr < hi) && (addr >= low)) 467 return (B_TRUE); 468 break; 469 case PCI_ADDR_MEM64: 470 low = ((uint64_t)ranges_p->child_mid << 32) | 471 (uint64_t)ranges_p->child_low; 472 hi = (((uint64_t)ranges_p->size_high << 32) | 473 (uint64_t)ranges_p->size_low) + low; 474 if ((addr < hi) && (addr >= low)) 475 return (B_TRUE); 476 break; 477 } 478 } 479 return (B_FALSE); 480 } 481 482 static pcie_bus_t * 483 pf_is_ready(dev_info_t *dip) 484 { 485 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 486 if (!bus_p) 487 return (NULL); 488 489 if (!(bus_p->bus_fm_flags & PF_FM_READY)) 490 return (NULL); 491 return (bus_p); 492 } 493 494 static void 495 pf_pcix_ecc_regs_gather(pf_pcix_ecc_regs_t *pcix_ecc_regs, 496 pcie_bus_t *bus_p, boolean_t bdg) 497 { 498 if (bdg) { 499 pcix_ecc_regs->pcix_ecc_ctlstat = PCIX_CAP_GET(32, bus_p, 500 PCI_PCIX_BDG_ECC_STATUS); 501 pcix_ecc_regs->pcix_ecc_fstaddr = PCIX_CAP_GET(32, bus_p, 502 PCI_PCIX_BDG_ECC_FST_AD); 503 pcix_ecc_regs->pcix_ecc_secaddr = PCIX_CAP_GET(32, bus_p, 504 PCI_PCIX_BDG_ECC_SEC_AD); 505 pcix_ecc_regs->pcix_ecc_attr = PCIX_CAP_GET(32, bus_p, 506 PCI_PCIX_BDG_ECC_ATTR); 507 } else { 508 pcix_ecc_regs->pcix_ecc_ctlstat = PCIX_CAP_GET(32, bus_p, 509 PCI_PCIX_ECC_STATUS); 510 pcix_ecc_regs->pcix_ecc_fstaddr = PCIX_CAP_GET(32, bus_p, 511 PCI_PCIX_ECC_FST_AD); 512 pcix_ecc_regs->pcix_ecc_secaddr = PCIX_CAP_GET(32, bus_p, 513 PCI_PCIX_ECC_SEC_AD); 514 pcix_ecc_regs->pcix_ecc_attr = PCIX_CAP_GET(32, bus_p, 515 PCI_PCIX_ECC_ATTR); 516 } 517 } 518 519 520 static void 521 pf_pcix_regs_gather(pf_data_t *pfd_p, pcie_bus_t *bus_p) 522 { 523 /* 524 * For PCI-X device PCI-X Capability only exists for Type 0 Headers. 525 * PCI-X Bridge Capability only exists for Type 1 Headers. 526 * Both capabilities do not exist at the same time. 527 */ 528 if (PCIE_IS_BDG(bus_p)) { 529 pf_pcix_bdg_err_regs_t *pcix_bdg_regs; 530 531 pcix_bdg_regs = PCIX_BDG_ERR_REG(pfd_p); 532 533 pcix_bdg_regs->pcix_bdg_sec_stat = PCIX_CAP_GET(16, bus_p, 534 PCI_PCIX_SEC_STATUS); 535 pcix_bdg_regs->pcix_bdg_stat = PCIX_CAP_GET(32, bus_p, 536 PCI_PCIX_BDG_STATUS); 537 538 if (PCIX_ECC_VERSION_CHECK(bus_p)) { 539 /* 540 * PCI Express to PCI-X bridges only implement the 541 * secondary side of the PCI-X ECC registers, bit one is 542 * read-only so we make sure we do not write to it. 543 */ 544 if (!PCIE_IS_PCIE_BDG(bus_p)) { 545 PCIX_CAP_PUT(32, bus_p, PCI_PCIX_BDG_ECC_STATUS, 546 0); 547 pf_pcix_ecc_regs_gather( 548 PCIX_BDG_ECC_REG(pfd_p, 0), bus_p, B_TRUE); 549 PCIX_CAP_PUT(32, bus_p, PCI_PCIX_BDG_ECC_STATUS, 550 1); 551 } 552 pf_pcix_ecc_regs_gather(PCIX_BDG_ECC_REG(pfd_p, 0), 553 bus_p, B_TRUE); 554 } 555 } else { 556 pf_pcix_err_regs_t *pcix_regs = PCIX_ERR_REG(pfd_p); 557 558 pcix_regs->pcix_command = PCIX_CAP_GET(16, bus_p, 559 PCI_PCIX_COMMAND); 560 pcix_regs->pcix_status = PCIX_CAP_GET(32, bus_p, 561 PCI_PCIX_STATUS); 562 if (PCIX_ECC_VERSION_CHECK(bus_p)) 563 pf_pcix_ecc_regs_gather(PCIX_ECC_REG(pfd_p), bus_p, 564 B_TRUE); 565 } 566 } 567 568 static void 569 pf_pcie_regs_gather(pf_data_t *pfd_p, pcie_bus_t *bus_p) 570 { 571 pf_pcie_err_regs_t *pcie_regs = PCIE_ERR_REG(pfd_p); 572 pf_pcie_adv_err_regs_t *pcie_adv_regs = PCIE_ADV_REG(pfd_p); 573 574 pcie_regs->pcie_err_status = PCIE_CAP_GET(16, bus_p, PCIE_DEVSTS); 575 pcie_regs->pcie_err_ctl = PCIE_CAP_GET(16, bus_p, PCIE_DEVCTL); 576 pcie_regs->pcie_dev_cap = PCIE_CAP_GET(32, bus_p, PCIE_DEVCAP); 577 578 if (PCIE_IS_BDG(bus_p) && PCIE_IS_PCIX(bus_p)) 579 pf_pcix_regs_gather(pfd_p, bus_p); 580 581 if (PCIE_IS_ROOT(bus_p)) { 582 pf_pcie_rp_err_regs_t *pcie_rp_regs = PCIE_RP_REG(pfd_p); 583 584 pcie_rp_regs->pcie_rp_status = PCIE_CAP_GET(32, bus_p, 585 PCIE_ROOTSTS); 586 pcie_rp_regs->pcie_rp_ctl = PCIE_CAP_GET(16, bus_p, 587 PCIE_ROOTCTL); 588 } 589 590 if (!PCIE_HAS_AER(bus_p)) 591 return; 592 593 /* Gather UE AERs */ 594 pcie_adv_regs->pcie_adv_ctl = PCIE_AER_GET(32, bus_p, 595 PCIE_AER_CTL); 596 pcie_adv_regs->pcie_ue_status = PCIE_AER_GET(32, bus_p, 597 PCIE_AER_UCE_STS); 598 pcie_adv_regs->pcie_ue_mask = PCIE_AER_GET(32, bus_p, 599 PCIE_AER_UCE_MASK); 600 pcie_adv_regs->pcie_ue_sev = PCIE_AER_GET(32, bus_p, 601 PCIE_AER_UCE_SERV); 602 PCIE_ADV_HDR(pfd_p, 0) = PCIE_AER_GET(32, bus_p, 603 PCIE_AER_HDR_LOG); 604 PCIE_ADV_HDR(pfd_p, 1) = PCIE_AER_GET(32, bus_p, 605 PCIE_AER_HDR_LOG + 0x4); 606 PCIE_ADV_HDR(pfd_p, 2) = PCIE_AER_GET(32, bus_p, 607 PCIE_AER_HDR_LOG + 0x8); 608 PCIE_ADV_HDR(pfd_p, 3) = PCIE_AER_GET(32, bus_p, 609 PCIE_AER_HDR_LOG + 0xc); 610 611 /* Gather CE AERs */ 612 pcie_adv_regs->pcie_ce_status = PCIE_AER_GET(32, bus_p, 613 PCIE_AER_CE_STS); 614 pcie_adv_regs->pcie_ce_mask = PCIE_AER_GET(32, bus_p, 615 PCIE_AER_CE_MASK); 616 617 /* 618 * If pci express to pci bridge then grab the bridge 619 * error registers. 620 */ 621 if (PCIE_IS_PCIE_BDG(bus_p)) { 622 pf_pcie_adv_bdg_err_regs_t *pcie_bdg_regs = 623 PCIE_ADV_BDG_REG(pfd_p); 624 625 pcie_bdg_regs->pcie_sue_ctl = PCIE_AER_GET(32, bus_p, 626 PCIE_AER_SCTL); 627 pcie_bdg_regs->pcie_sue_status = PCIE_AER_GET(32, bus_p, 628 PCIE_AER_SUCE_STS); 629 pcie_bdg_regs->pcie_sue_mask = PCIE_AER_GET(32, bus_p, 630 PCIE_AER_SUCE_MASK); 631 pcie_bdg_regs->pcie_sue_sev = PCIE_AER_GET(32, bus_p, 632 PCIE_AER_SUCE_SERV); 633 PCIE_ADV_BDG_HDR(pfd_p, 0) = PCIE_AER_GET(32, bus_p, 634 PCIE_AER_SHDR_LOG); 635 PCIE_ADV_BDG_HDR(pfd_p, 1) = PCIE_AER_GET(32, bus_p, 636 PCIE_AER_SHDR_LOG + 0x4); 637 PCIE_ADV_BDG_HDR(pfd_p, 2) = PCIE_AER_GET(32, bus_p, 638 PCIE_AER_SHDR_LOG + 0x8); 639 PCIE_ADV_BDG_HDR(pfd_p, 3) = PCIE_AER_GET(32, bus_p, 640 PCIE_AER_SHDR_LOG + 0xc); 641 } 642 643 /* 644 * If PCI Express root port then grab the root port 645 * error registers. 646 */ 647 if (PCIE_IS_ROOT(bus_p)) { 648 pf_pcie_adv_rp_err_regs_t *pcie_rp_regs = 649 PCIE_ADV_RP_REG(pfd_p); 650 651 pcie_rp_regs->pcie_rp_err_cmd = PCIE_AER_GET(32, bus_p, 652 PCIE_AER_RE_CMD); 653 pcie_rp_regs->pcie_rp_err_status = PCIE_AER_GET(32, bus_p, 654 PCIE_AER_RE_STS); 655 pcie_rp_regs->pcie_rp_ce_src_id = PCIE_AER_GET(16, bus_p, 656 PCIE_AER_CE_SRC_ID); 657 pcie_rp_regs->pcie_rp_ue_src_id = PCIE_AER_GET(16, bus_p, 658 PCIE_AER_ERR_SRC_ID); 659 } 660 } 661 662 static void 663 pf_pci_regs_gather(pf_data_t *pfd_p, pcie_bus_t *bus_p) 664 { 665 pf_pci_err_regs_t *pci_regs = PCI_ERR_REG(pfd_p); 666 667 /* 668 * Start by reading all the error registers that are available for 669 * pci and pci express and for leaf devices and bridges/switches 670 */ 671 pci_regs->pci_err_status = PCIE_GET(16, bus_p, PCI_CONF_STAT); 672 pci_regs->pci_cfg_comm = PCIE_GET(16, bus_p, PCI_CONF_COMM); 673 674 /* 675 * If pci-pci bridge grab PCI bridge specific error registers. 676 */ 677 if (PCIE_IS_BDG(bus_p)) { 678 pf_pci_bdg_err_regs_t *pci_bdg_regs = PCI_BDG_ERR_REG(pfd_p); 679 pci_bdg_regs->pci_bdg_sec_stat = 680 PCIE_GET(16, bus_p, PCI_BCNF_SEC_STATUS); 681 pci_bdg_regs->pci_bdg_ctrl = 682 PCIE_GET(16, bus_p, PCI_BCNF_BCNTRL); 683 } 684 685 /* 686 * If pci express device grab pci express error registers and 687 * check for advanced error reporting features and grab them if 688 * available. 689 */ 690 if (PCIE_IS_PCIE(bus_p)) 691 pf_pcie_regs_gather(pfd_p, bus_p); 692 else if (PCIE_IS_PCIX(bus_p)) 693 pf_pcix_regs_gather(pfd_p, bus_p); 694 695 } 696 697 static void 698 pf_pcix_regs_clear(pf_data_t *pfd_p, pcie_bus_t *bus_p) 699 { 700 if (PCIE_IS_BDG(bus_p)) { 701 pf_pcix_bdg_err_regs_t *pcix_bdg_regs; 702 703 pcix_bdg_regs = PCIX_BDG_ERR_REG(pfd_p); 704 705 PCIX_CAP_PUT(16, bus_p, PCI_PCIX_SEC_STATUS, 706 pcix_bdg_regs->pcix_bdg_sec_stat); 707 708 PCIX_CAP_PUT(32, bus_p, PCI_PCIX_BDG_STATUS, 709 pcix_bdg_regs->pcix_bdg_stat); 710 711 if (PCIX_ECC_VERSION_CHECK(bus_p)) { 712 pf_pcix_ecc_regs_t *pcix_bdg_ecc_regs; 713 /* 714 * PCI Express to PCI-X bridges only implement the 715 * secondary side of the PCI-X ECC registers. For 716 * clearing, there is no need to "select" the ECC 717 * register, just write what was originally read. 718 */ 719 if (!PCIE_IS_PCIE_BDG(bus_p)) { 720 pcix_bdg_ecc_regs = PCIX_BDG_ECC_REG(pfd_p, 0); 721 PCIX_CAP_PUT(32, bus_p, PCI_PCIX_BDG_ECC_STATUS, 722 pcix_bdg_ecc_regs->pcix_ecc_ctlstat); 723 724 } 725 pcix_bdg_ecc_regs = PCIX_BDG_ECC_REG(pfd_p, 1); 726 PCIX_CAP_PUT(32, bus_p, PCI_PCIX_BDG_ECC_STATUS, 727 pcix_bdg_ecc_regs->pcix_ecc_ctlstat); 728 } 729 } else { 730 pf_pcix_err_regs_t *pcix_regs = PCIX_ERR_REG(pfd_p); 731 732 PCIX_CAP_PUT(32, bus_p, PCI_PCIX_STATUS, 733 pcix_regs->pcix_status); 734 735 if (PCIX_ECC_VERSION_CHECK(bus_p)) { 736 pf_pcix_ecc_regs_t *pcix_ecc_regs = PCIX_ECC_REG(pfd_p); 737 738 PCIX_CAP_PUT(32, bus_p, PCI_PCIX_ECC_STATUS, 739 pcix_ecc_regs->pcix_ecc_ctlstat); 740 } 741 } 742 } 743 744 static void 745 pf_pcie_regs_clear(pf_data_t *pfd_p, pcie_bus_t *bus_p) 746 { 747 pf_pcie_err_regs_t *pcie_regs = PCIE_ERR_REG(pfd_p); 748 pf_pcie_adv_err_regs_t *pcie_adv_regs = PCIE_ADV_REG(pfd_p); 749 750 PCIE_CAP_PUT(16, bus_p, PCIE_DEVSTS, pcie_regs->pcie_err_status); 751 752 if (PCIE_IS_BDG(bus_p) && PCIE_IS_PCIX(bus_p)) 753 pf_pcix_regs_clear(pfd_p, bus_p); 754 755 if (!PCIE_HAS_AER(bus_p)) 756 return; 757 758 PCIE_AER_PUT(32, bus_p, PCIE_AER_UCE_STS, 759 pcie_adv_regs->pcie_ue_status); 760 761 PCIE_AER_PUT(32, bus_p, PCIE_AER_CE_STS, 762 pcie_adv_regs->pcie_ce_status); 763 764 if (PCIE_IS_PCIE_BDG(bus_p)) { 765 pf_pcie_adv_bdg_err_regs_t *pcie_bdg_regs = 766 PCIE_ADV_BDG_REG(pfd_p); 767 768 PCIE_AER_PUT(32, bus_p, PCIE_AER_SUCE_STS, 769 pcie_bdg_regs->pcie_sue_status); 770 } 771 772 /* 773 * If PCI Express root complex then clear the root complex 774 * error registers. 775 */ 776 if (PCIE_IS_ROOT(bus_p)) { 777 pf_pcie_adv_rp_err_regs_t *pcie_rp_regs; 778 779 pcie_rp_regs = PCIE_ADV_RP_REG(pfd_p); 780 781 PCIE_AER_PUT(32, bus_p, PCIE_AER_RE_STS, 782 pcie_rp_regs->pcie_rp_err_status); 783 } 784 } 785 786 static void 787 pf_pci_regs_clear(pf_data_t *pfd_p, pcie_bus_t *bus_p) 788 { 789 if (PCIE_IS_PCIE(bus_p)) 790 pf_pcie_regs_clear(pfd_p, bus_p); 791 else if (PCIE_IS_PCIX(bus_p)) 792 pf_pcix_regs_clear(pfd_p, bus_p); 793 794 PCIE_PUT(16, bus_p, PCI_CONF_STAT, pfd_p->pe_pci_regs->pci_err_status); 795 796 if (PCIE_IS_BDG(bus_p)) { 797 pf_pci_bdg_err_regs_t *pci_bdg_regs = PCI_BDG_ERR_REG(pfd_p); 798 PCIE_PUT(16, bus_p, PCI_BCNF_SEC_STATUS, 799 pci_bdg_regs->pci_bdg_sec_stat); 800 } 801 } 802 803 /* ARGSUSED */ 804 void 805 pcie_clear_errors(dev_info_t *dip) 806 { 807 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 808 pf_data_t *pfd_p = PCIE_DIP2PFD(dip); 809 810 ASSERT(bus_p); 811 812 pf_pci_regs_gather(pfd_p, bus_p); 813 pf_pci_regs_clear(pfd_p, bus_p); 814 } 815 816 /* Find the fault BDF, fault Addr or full scan on a PCIe Root Port. */ 817 static void 818 pf_pci_find_rp_fault(pf_data_t *pfd_p, pcie_bus_t *bus_p) 819 { 820 pf_root_fault_t *root_fault = PCIE_ROOT_FAULT(pfd_p); 821 pf_pcie_adv_rp_err_regs_t *rp_regs = PCIE_ADV_RP_REG(pfd_p); 822 uint32_t root_err = rp_regs->pcie_rp_err_status; 823 uint32_t ue_err = PCIE_ADV_REG(pfd_p)->pcie_ue_status; 824 int num_faults = 0; 825 826 /* Since this data structure is reused, make sure to reset it */ 827 root_fault->full_scan = B_FALSE; 828 root_fault->scan_bdf = PCIE_INVALID_BDF; 829 root_fault->scan_addr = 0; 830 831 if (!PCIE_HAS_AER(bus_p) && 832 (PCI_BDG_ERR_REG(pfd_p)->pci_bdg_sec_stat & PF_PCI_BDG_ERR)) { 833 PCIE_ROOT_FAULT(pfd_p)->full_scan = B_TRUE; 834 return; 835 } 836 837 /* 838 * Check to see if an error has been received that 839 * requires a scan of the fabric. Count the number of 840 * faults seen. If MUL CE/FE_NFE that counts for 841 * atleast 2 faults, so just return with full_scan. 842 */ 843 if ((root_err & PCIE_AER_RE_STS_MUL_CE_RCVD) || 844 (root_err & PCIE_AER_RE_STS_MUL_FE_NFE_RCVD)) { 845 PCIE_ROOT_FAULT(pfd_p)->full_scan = B_TRUE; 846 return; 847 } 848 849 if (root_err & PCIE_AER_RE_STS_CE_RCVD) 850 num_faults++; 851 852 if (root_err & PCIE_AER_RE_STS_FE_NFE_RCVD) 853 num_faults++; 854 855 if (ue_err & PCIE_AER_UCE_CA) 856 num_faults++; 857 858 if (ue_err & PCIE_AER_UCE_UR) 859 num_faults++; 860 861 /* If no faults just return */ 862 if (num_faults == 0) 863 return; 864 865 /* If faults > 1 do full scan */ 866 if (num_faults > 1) { 867 PCIE_ROOT_FAULT(pfd_p)->full_scan = B_TRUE; 868 return; 869 } 870 871 /* By this point, there is only 1 fault detected */ 872 if (root_err & PCIE_AER_RE_STS_CE_RCVD) { 873 PCIE_ROOT_FAULT(pfd_p)->scan_bdf = rp_regs->pcie_rp_ce_src_id; 874 num_faults--; 875 } else if (root_err & PCIE_AER_RE_STS_FE_NFE_RCVD) { 876 PCIE_ROOT_FAULT(pfd_p)->scan_bdf = rp_regs->pcie_rp_ue_src_id; 877 num_faults--; 878 } else if ((HAS_AER_LOGS(pfd_p, PCIE_AER_UCE_CA) || 879 HAS_AER_LOGS(pfd_p, PCIE_AER_UCE_UR)) && 880 (pf_tlp_decode(PCIE_PFD2BUS(pfd_p), PCIE_ADV_REG(pfd_p)) == 881 DDI_SUCCESS)) { 882 PCIE_ROOT_FAULT(pfd_p)->scan_addr = 883 PCIE_ADV_REG(pfd_p)->pcie_ue_tgt_addr; 884 num_faults--; 885 } 886 887 /* 888 * This means an error did occur, but we couldn't extract the fault BDF 889 */ 890 if (num_faults > 0) 891 PCIE_ROOT_FAULT(pfd_p)->full_scan = B_TRUE; 892 893 } 894 895 896 /* 897 * Load PCIe Fault Data for PCI/PCIe devices into PCIe Fault Data Queue 898 * 899 * Returns a scan flag. 900 * o PF_SCAN_SUCCESS - Error gathered and cleared sucessfuly, data added to 901 * Fault Q 902 * o PF_SCAN_BAD_RESPONSE - Unable to talk to device, item added to fault Q 903 * o PF_SCAN_CB_FAILURE - A hardened device deemed that the error was fatal. 904 * o PF_SCAN_NO_ERR_IN_CHILD - Only applies to bridge to prevent further 905 * unnecessary scanning 906 * o PF_SCAN_IN_DQ - This device has already been scanned; it was skipped this 907 * time. 908 */ 909 static int 910 pf_default_hdl(dev_info_t *dip, pf_impl_t *impl) 911 { 912 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 913 pf_data_t *pfd_p = PCIE_DIP2PFD(dip); 914 int cb_sts, scan_flag = PF_SCAN_SUCCESS; 915 916 /* Make sure this device hasn't already been snapshotted and cleared */ 917 if (pfd_p->pe_valid == B_TRUE) { 918 scan_flag |= PF_SCAN_IN_DQ; 919 goto done; 920 } 921 922 /* 923 * Read vendor/device ID and check with cached data; if it doesn't 924 * match, it could very well mean that the device is no longer 925 * responding. In this case, we return PF_SCAN_BAD_RESPONSE; should 926 * the caller choose to panic in this case, we will have the basic 927 * info in the error queue for the purposes of postmortem debugging. 928 */ 929 if (PCIE_GET(32, bus_p, PCI_CONF_VENID) != bus_p->bus_dev_ven_id) { 930 char buf[FM_MAX_CLASS]; 931 932 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", 933 PCI_ERROR_SUBCLASS, PCI_NR); 934 ddi_fm_ereport_post(dip, buf, fm_ena_generate(0, FM_ENA_FMT1), 935 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, NULL); 936 937 /* 938 * For IOV/Hotplug purposes skip gathering info for this device, 939 * but populate affected info and severity. Clear out any data 940 * that maybe been saved in the last fabric scan. 941 */ 942 pf_reset_pfd(pfd_p); 943 pfd_p->pe_severity_flags = PF_ERR_BAD_RESPONSE; 944 PFD_AFFECTED_DEV(pfd_p)->pe_affected_flags = PF_AFFECTED_SELF; 945 946 /* Add the snapshot to the error q */ 947 pf_en_dq(pfd_p, impl); 948 pfd_p->pe_valid = B_TRUE; 949 950 return (PF_SCAN_BAD_RESPONSE); 951 } 952 953 pf_pci_regs_gather(pfd_p, bus_p); 954 pf_pci_regs_clear(pfd_p, bus_p); 955 if (PCIE_IS_RP(bus_p)) 956 pf_pci_find_rp_fault(pfd_p, bus_p); 957 958 cb_sts = pf_fm_callback(dip, impl->pf_derr); 959 960 if (cb_sts == DDI_FM_FATAL || cb_sts == DDI_FM_UNKNOWN) 961 scan_flag |= PF_SCAN_CB_FAILURE; 962 963 /* Add the snapshot to the error q */ 964 pf_en_dq(pfd_p, impl); 965 966 done: 967 /* 968 * If a bridge does not have any error no need to scan any further down. 969 * For PCIe devices, check the PCIe device status and PCI secondary 970 * status. 971 * - Some non-compliant PCIe devices do not utilize PCIe 972 * error registers. If so rely on legacy PCI error registers. 973 * For PCI devices, check the PCI secondary status. 974 */ 975 if (PCIE_IS_PCIE_BDG(bus_p) && 976 !(PCIE_ERR_REG(pfd_p)->pcie_err_status & PF_PCIE_BDG_ERR) && 977 !(PCI_BDG_ERR_REG(pfd_p)->pci_bdg_sec_stat & PF_PCI_BDG_ERR)) 978 scan_flag |= PF_SCAN_NO_ERR_IN_CHILD; 979 980 if (PCIE_IS_PCI_BDG(bus_p) && 981 !(PCI_BDG_ERR_REG(pfd_p)->pci_bdg_sec_stat & PF_PCI_BDG_ERR)) 982 scan_flag |= PF_SCAN_NO_ERR_IN_CHILD; 983 984 pfd_p->pe_valid = B_TRUE; 985 return (scan_flag); 986 } 987 988 /* 989 * Called during postattach to initialize a device's error handling 990 * capabilities. If the devices has already been hardened, then there isn't 991 * much needed. Otherwise initialize the device's default FMA capabilities. 992 * 993 * In a future project where PCIe support is removed from pcifm, several 994 * "properties" that are setup in ddi_fm_init and pci_ereport_setup need to be 995 * created here so that the PCI/PCIe eversholt rules will work properly. 996 */ 997 void 998 pf_init(dev_info_t *dip, ddi_iblock_cookie_t ibc, ddi_attach_cmd_t cmd) 999 { 1000 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 1001 struct i_ddi_fmhdl *fmhdl = DEVI(dip)->devi_fmhdl; 1002 boolean_t need_cb_register = B_FALSE; 1003 1004 if (!bus_p) { 1005 cmn_err(CE_WARN, "devi_bus information is not set for %s%d.\n", 1006 ddi_driver_name(dip), ddi_get_instance(dip)); 1007 return; 1008 } 1009 1010 if (fmhdl) { 1011 /* 1012 * If device is only ereport capable and not callback capable 1013 * make it callback capable. The only downside is that the 1014 * "fm-errcb-capable" property is not created for this device 1015 * which should be ok since it's not used anywhere. 1016 */ 1017 if (!(fmhdl->fh_cap & DDI_FM_ERRCB_CAPABLE)) 1018 need_cb_register = B_TRUE; 1019 } else { 1020 int cap; 1021 /* 1022 * fm-capable in driver.conf can be used to set fm_capabilities. 1023 * If fm-capable is not defined, set the default 1024 * DDI_FM_EREPORT_CAPABLE and DDI_FM_ERRCB_CAPABLE. 1025 */ 1026 cap = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 1027 DDI_PROP_DONTPASS, "fm-capable", 1028 DDI_FM_EREPORT_CAPABLE | DDI_FM_ERRCB_CAPABLE); 1029 cap &= (DDI_FM_EREPORT_CAPABLE | DDI_FM_ERRCB_CAPABLE); 1030 1031 bus_p->bus_fm_flags |= PF_FM_IS_NH; 1032 1033 if (cmd == DDI_ATTACH) { 1034 ddi_fm_init(dip, &cap, &ibc); 1035 pci_ereport_setup(dip); 1036 } 1037 1038 if (cap & DDI_FM_ERRCB_CAPABLE) 1039 need_cb_register = B_TRUE; 1040 1041 fmhdl = DEVI(dip)->devi_fmhdl; 1042 } 1043 1044 /* If ddi_fm_init fails for any reason RETURN */ 1045 if (!fmhdl) { 1046 bus_p->bus_fm_flags = 0; 1047 return; 1048 } 1049 1050 fmhdl->fh_cap |= DDI_FM_ERRCB_CAPABLE; 1051 if (cmd == DDI_ATTACH) { 1052 if (need_cb_register) 1053 ddi_fm_handler_register(dip, pf_dummy_cb, NULL); 1054 } 1055 1056 bus_p->bus_fm_flags |= PF_FM_READY; 1057 } 1058 1059 /* undo FMA lock, called at predetach */ 1060 void 1061 pf_fini(dev_info_t *dip, ddi_detach_cmd_t cmd) 1062 { 1063 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 1064 1065 if (!bus_p) 1066 return; 1067 1068 /* Don't fini anything if device isn't FM Ready */ 1069 if (!(bus_p->bus_fm_flags & PF_FM_READY)) 1070 return; 1071 1072 /* no other code should set the flag to false */ 1073 bus_p->bus_fm_flags &= ~PF_FM_READY; 1074 1075 /* 1076 * Grab the mutex to make sure device isn't in the middle of 1077 * error handling. Setting the bus_fm_flag to ~PF_FM_READY 1078 * should prevent this device from being error handled after 1079 * the mutex has been released. 1080 */ 1081 (void) pf_handler_enter(dip, NULL); 1082 pf_handler_exit(dip); 1083 1084 /* undo non-hardened drivers */ 1085 if (bus_p->bus_fm_flags & PF_FM_IS_NH) { 1086 if (cmd == DDI_DETACH) { 1087 bus_p->bus_fm_flags &= ~PF_FM_IS_NH; 1088 pci_ereport_teardown(dip); 1089 /* 1090 * ddi_fini itself calls ddi_handler_unregister, 1091 * so no need to explicitly call unregister. 1092 */ 1093 ddi_fm_fini(dip); 1094 } 1095 } 1096 } 1097 1098 /*ARGSUSED*/ 1099 static int 1100 pf_dummy_cb(dev_info_t *dip, ddi_fm_error_t *derr, const void *not_used) 1101 { 1102 return (DDI_FM_OK); 1103 } 1104 1105 /* 1106 * Add PFD to queue. If it is an RC add it to the beginning, 1107 * otherwise add it to the end. 1108 */ 1109 static void 1110 pf_en_dq(pf_data_t *pfd_p, pf_impl_t *impl) 1111 { 1112 pf_data_t *head_p = impl->pf_dq_head_p; 1113 pf_data_t *tail_p = impl->pf_dq_tail_p; 1114 1115 impl->pf_total++; 1116 1117 if (!head_p) { 1118 ASSERT(PFD_IS_ROOT(pfd_p)); 1119 impl->pf_dq_head_p = pfd_p; 1120 impl->pf_dq_tail_p = pfd_p; 1121 pfd_p->pe_prev = NULL; 1122 pfd_p->pe_next = NULL; 1123 return; 1124 } 1125 1126 /* Check if this is a Root Port eprt */ 1127 if (PFD_IS_ROOT(pfd_p)) { 1128 pf_data_t *root_p, *last_p = NULL; 1129 1130 /* The first item must be a RP */ 1131 root_p = head_p; 1132 for (last_p = head_p; last_p && PFD_IS_ROOT(last_p); 1133 last_p = last_p->pe_next) 1134 root_p = last_p; 1135 1136 /* root_p is the last RP pfd. last_p is the first non-RP pfd. */ 1137 root_p->pe_next = pfd_p; 1138 pfd_p->pe_prev = root_p; 1139 pfd_p->pe_next = last_p; 1140 1141 if (last_p) 1142 last_p->pe_prev = pfd_p; 1143 else 1144 tail_p = pfd_p; 1145 } else { 1146 tail_p->pe_next = pfd_p; 1147 pfd_p->pe_prev = tail_p; 1148 pfd_p->pe_next = NULL; 1149 tail_p = pfd_p; 1150 } 1151 1152 impl->pf_dq_head_p = head_p; 1153 impl->pf_dq_tail_p = tail_p; 1154 } 1155 1156 /* 1157 * Ignore: 1158 * - TRAINING: as leaves do not have children 1159 * - SD: as leaves do not have children 1160 */ 1161 const pf_fab_err_tbl_t pcie_pcie_tbl[] = { 1162 {PCIE_AER_UCE_DLP, pf_panic, 1163 PF_AFFECTED_PARENT, 0}, 1164 1165 {PCIE_AER_UCE_PTLP, pf_analyse_ptlp, 1166 PF_AFFECTED_SELF, 0}, 1167 1168 {PCIE_AER_UCE_FCP, pf_panic, 1169 PF_AFFECTED_PARENT, 0}, 1170 1171 {PCIE_AER_UCE_TO, pf_analyse_to, 1172 PF_AFFECTED_SELF, 0}, 1173 1174 {PCIE_AER_UCE_CA, pf_analyse_ca_ur, 1175 PF_AFFECTED_SELF, 0}, 1176 1177 {PCIE_AER_UCE_UC, pf_analyse_uc, 1178 0, 0}, 1179 1180 {PCIE_AER_UCE_RO, pf_panic, 1181 PF_AFFECTED_PARENT, 0}, 1182 1183 {PCIE_AER_UCE_MTLP, pf_panic, 1184 PF_AFFECTED_PARENT, 0}, 1185 1186 {PCIE_AER_UCE_ECRC, pf_panic, 1187 PF_AFFECTED_SELF, 0}, 1188 1189 {PCIE_AER_UCE_UR, pf_analyse_ca_ur, 1190 PF_AFFECTED_SELF, 0}, 1191 1192 {0, NULL, 0, 0} 1193 }; 1194 1195 const pf_fab_err_tbl_t pcie_rp_tbl[] = { 1196 {PCIE_AER_UCE_TRAINING, pf_no_panic, 1197 PF_AFFECTED_SELF | PF_AFFECTED_CHILDREN, 0}, 1198 1199 {PCIE_AER_UCE_DLP, pf_panic, 1200 PF_AFFECTED_SELF | PF_AFFECTED_CHILDREN, 0}, 1201 1202 {PCIE_AER_UCE_SD, pf_no_panic, 1203 PF_AFFECTED_SELF | PF_AFFECTED_CHILDREN, 0}, 1204 1205 {PCIE_AER_UCE_PTLP, pf_analyse_ptlp, 1206 PF_AFFECTED_AER, PF_AFFECTED_CHILDREN}, 1207 1208 {PCIE_AER_UCE_FCP, pf_panic, 1209 PF_AFFECTED_SELF | PF_AFFECTED_CHILDREN, 0}, 1210 1211 {PCIE_AER_UCE_TO, pf_panic, 1212 PF_AFFECTED_ADDR, PF_AFFECTED_CHILDREN}, 1213 1214 {PCIE_AER_UCE_CA, pf_no_panic, 1215 PF_AFFECTED_AER, PF_AFFECTED_CHILDREN}, 1216 1217 {PCIE_AER_UCE_UC, pf_analyse_uc, 1218 0, 0}, 1219 1220 {PCIE_AER_UCE_RO, pf_panic, 1221 PF_AFFECTED_SELF | PF_AFFECTED_CHILDREN, 0}, 1222 1223 {PCIE_AER_UCE_MTLP, pf_panic, 1224 PF_AFFECTED_SELF | PF_AFFECTED_AER, 1225 PF_AFFECTED_SELF | PF_AFFECTED_CHILDREN}, 1226 1227 {PCIE_AER_UCE_ECRC, pf_panic, 1228 PF_AFFECTED_AER, PF_AFFECTED_CHILDREN}, 1229 1230 {PCIE_AER_UCE_UR, pf_no_panic, 1231 PF_AFFECTED_AER, PF_AFFECTED_CHILDREN}, 1232 1233 {0, NULL, 0, 0} 1234 }; 1235 1236 const pf_fab_err_tbl_t pcie_sw_tbl[] = { 1237 {PCIE_AER_UCE_TRAINING, pf_no_panic, 1238 PF_AFFECTED_SELF | PF_AFFECTED_CHILDREN, 0}, 1239 1240 {PCIE_AER_UCE_DLP, pf_panic, 1241 PF_AFFECTED_SELF | PF_AFFECTED_CHILDREN, 0}, 1242 1243 {PCIE_AER_UCE_SD, pf_no_panic, 1244 PF_AFFECTED_SELF | PF_AFFECTED_CHILDREN, 0}, 1245 1246 {PCIE_AER_UCE_PTLP, pf_analyse_ptlp, 1247 PF_AFFECTED_AER, PF_AFFECTED_SELF | PF_AFFECTED_CHILDREN}, 1248 1249 {PCIE_AER_UCE_FCP, pf_panic, 1250 PF_AFFECTED_SELF | PF_AFFECTED_CHILDREN, 0}, 1251 1252 {PCIE_AER_UCE_TO, pf_analyse_to, 1253 PF_AFFECTED_CHILDREN, 0}, 1254 1255 {PCIE_AER_UCE_CA, pf_analyse_ca_ur, 1256 PF_AFFECTED_AER, PF_AFFECTED_SELF | PF_AFFECTED_CHILDREN}, 1257 1258 {PCIE_AER_UCE_UC, pf_analyse_uc, 1259 0, 0}, 1260 1261 {PCIE_AER_UCE_RO, pf_panic, 1262 PF_AFFECTED_SELF | PF_AFFECTED_CHILDREN, 0}, 1263 1264 {PCIE_AER_UCE_MTLP, pf_panic, 1265 PF_AFFECTED_SELF | PF_AFFECTED_AER, 1266 PF_AFFECTED_SELF | PF_AFFECTED_CHILDREN}, 1267 1268 {PCIE_AER_UCE_ECRC, pf_panic, 1269 PF_AFFECTED_AER, PF_AFFECTED_SELF | PF_AFFECTED_CHILDREN}, 1270 1271 {PCIE_AER_UCE_UR, pf_analyse_ca_ur, 1272 PF_AFFECTED_AER, PF_AFFECTED_SELF | PF_AFFECTED_CHILDREN}, 1273 1274 {0, NULL, 0, 0} 1275 }; 1276 1277 const pf_fab_err_tbl_t pcie_pcie_bdg_tbl[] = { 1278 {PCIE_AER_SUCE_TA_ON_SC, pf_analyse_sc, 1279 0, 0}, 1280 1281 {PCIE_AER_SUCE_MA_ON_SC, pf_analyse_sc, 1282 0, 0}, 1283 1284 {PCIE_AER_SUCE_RCVD_TA, pf_analyse_ma_ta, 1285 0, 0}, 1286 1287 {PCIE_AER_SUCE_RCVD_MA, pf_analyse_ma_ta, 1288 0, 0}, 1289 1290 {PCIE_AER_SUCE_USC_ERR, pf_panic, 1291 PF_AFFECTED_SAER, PF_AFFECTED_CHILDREN}, 1292 1293 {PCIE_AER_SUCE_USC_MSG_DATA_ERR, pf_analyse_ma_ta, 1294 PF_AFFECTED_SAER, PF_AFFECTED_CHILDREN}, 1295 1296 {PCIE_AER_SUCE_UC_DATA_ERR, pf_analyse_uc_data, 1297 PF_AFFECTED_SAER, PF_AFFECTED_CHILDREN}, 1298 1299 {PCIE_AER_SUCE_UC_ATTR_ERR, pf_panic, 1300 PF_AFFECTED_CHILDREN, 0}, 1301 1302 {PCIE_AER_SUCE_UC_ADDR_ERR, pf_panic, 1303 PF_AFFECTED_CHILDREN, 0}, 1304 1305 {PCIE_AER_SUCE_TIMER_EXPIRED, pf_panic, 1306 PF_AFFECTED_SELF | PF_AFFECTED_CHILDREN, 0}, 1307 1308 {PCIE_AER_SUCE_PERR_ASSERT, pf_analyse_perr_assert, 1309 0, 0}, 1310 1311 {PCIE_AER_SUCE_SERR_ASSERT, pf_no_panic, 1312 0, 0}, 1313 1314 {PCIE_AER_SUCE_INTERNAL_ERR, pf_panic, 1315 PF_AFFECTED_SELF | PF_AFFECTED_CHILDREN, 0}, 1316 1317 {0, NULL, 0, 0} 1318 }; 1319 1320 const pf_fab_err_tbl_t pcie_pci_bdg_tbl[] = { 1321 {PCI_STAT_PERROR, pf_analyse_pci, 1322 PF_AFFECTED_SELF, 0}, 1323 1324 {PCI_STAT_S_PERROR, pf_analyse_pci, 1325 PF_AFFECTED_SELF, 0}, 1326 1327 {PCI_STAT_S_SYSERR, pf_panic, 1328 PF_AFFECTED_SELF, 0}, 1329 1330 {PCI_STAT_R_MAST_AB, pf_analyse_pci, 1331 PF_AFFECTED_SELF, 0}, 1332 1333 {PCI_STAT_R_TARG_AB, pf_analyse_pci, 1334 PF_AFFECTED_SELF, 0}, 1335 1336 {PCI_STAT_S_TARG_AB, pf_analyse_pci, 1337 PF_AFFECTED_SELF, 0}, 1338 1339 {0, NULL, 0, 0} 1340 }; 1341 1342 const pf_fab_err_tbl_t pcie_pci_tbl[] = { 1343 {PCI_STAT_PERROR, pf_analyse_pci, 1344 PF_AFFECTED_SELF, 0}, 1345 1346 {PCI_STAT_S_PERROR, pf_analyse_pci, 1347 PF_AFFECTED_SELF, 0}, 1348 1349 {PCI_STAT_S_SYSERR, pf_panic, 1350 PF_AFFECTED_SELF, 0}, 1351 1352 {PCI_STAT_R_MAST_AB, pf_analyse_pci, 1353 PF_AFFECTED_SELF, 0}, 1354 1355 {PCI_STAT_R_TARG_AB, pf_analyse_pci, 1356 PF_AFFECTED_SELF, 0}, 1357 1358 {PCI_STAT_S_TARG_AB, pf_analyse_pci, 1359 PF_AFFECTED_SELF, 0}, 1360 1361 {0, NULL, 0, 0} 1362 }; 1363 1364 #define PF_MASKED_AER_ERR(pfd_p) \ 1365 (PCIE_ADV_REG(pfd_p)->pcie_ue_status & \ 1366 ((PCIE_ADV_REG(pfd_p)->pcie_ue_mask) ^ 0xFFFFFFFF)) 1367 #define PF_MASKED_SAER_ERR(pfd_p) \ 1368 (PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_status & \ 1369 ((PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_mask) ^ 0xFFFFFFFF)) 1370 /* 1371 * Analyse all the PCIe Fault Data (erpt) gathered during dispatch in the erpt 1372 * Queue. 1373 */ 1374 static int 1375 pf_analyse_error(ddi_fm_error_t *derr, pf_impl_t *impl) 1376 { 1377 int sts_flags, error_flags = 0; 1378 pf_data_t *pfd_p; 1379 1380 for (pfd_p = impl->pf_dq_head_p; pfd_p; pfd_p = pfd_p->pe_next) { 1381 sts_flags = 0; 1382 1383 /* skip analysing error when no error info is gathered */ 1384 if (pfd_p->pe_severity_flags == PF_ERR_BAD_RESPONSE) 1385 goto done; 1386 1387 switch (PCIE_PFD2BUS(pfd_p)->bus_dev_type) { 1388 case PCIE_PCIECAP_DEV_TYPE_PCIE_DEV: 1389 case PCIE_PCIECAP_DEV_TYPE_PCI_DEV: 1390 if (PCIE_DEVSTS_CE_DETECTED & 1391 PCIE_ERR_REG(pfd_p)->pcie_err_status) 1392 sts_flags |= PF_ERR_CE; 1393 1394 pf_adjust_for_no_aer(pfd_p); 1395 sts_flags |= pf_analyse_error_tbl(derr, impl, 1396 pfd_p, pcie_pcie_tbl, PF_MASKED_AER_ERR(pfd_p)); 1397 break; 1398 case PCIE_PCIECAP_DEV_TYPE_ROOT: 1399 pf_adjust_for_no_aer(pfd_p); 1400 sts_flags |= pf_analyse_error_tbl(derr, impl, 1401 pfd_p, pcie_rp_tbl, PF_MASKED_AER_ERR(pfd_p)); 1402 break; 1403 case PCIE_PCIECAP_DEV_TYPE_RC_PSEUDO: 1404 /* no adjust_for_aer for pseudo RC */ 1405 /* keep the severity passed on from RC if any */ 1406 sts_flags |= pfd_p->pe_severity_flags; 1407 sts_flags |= pf_analyse_error_tbl(derr, impl, pfd_p, 1408 pcie_rp_tbl, PF_MASKED_AER_ERR(pfd_p)); 1409 break; 1410 case PCIE_PCIECAP_DEV_TYPE_UP: 1411 case PCIE_PCIECAP_DEV_TYPE_DOWN: 1412 if (PCIE_DEVSTS_CE_DETECTED & 1413 PCIE_ERR_REG(pfd_p)->pcie_err_status) 1414 sts_flags |= PF_ERR_CE; 1415 1416 pf_adjust_for_no_aer(pfd_p); 1417 sts_flags |= pf_analyse_error_tbl(derr, impl, 1418 pfd_p, pcie_sw_tbl, PF_MASKED_AER_ERR(pfd_p)); 1419 break; 1420 case PCIE_PCIECAP_DEV_TYPE_PCIE2PCI: 1421 if (PCIE_DEVSTS_CE_DETECTED & 1422 PCIE_ERR_REG(pfd_p)->pcie_err_status) 1423 sts_flags |= PF_ERR_CE; 1424 1425 pf_adjust_for_no_aer(pfd_p); 1426 pf_adjust_for_no_saer(pfd_p); 1427 sts_flags |= pf_analyse_error_tbl(derr, 1428 impl, pfd_p, pcie_pcie_tbl, 1429 PF_MASKED_AER_ERR(pfd_p)); 1430 sts_flags |= pf_analyse_error_tbl(derr, 1431 impl, pfd_p, pcie_pcie_bdg_tbl, 1432 PF_MASKED_SAER_ERR(pfd_p)); 1433 /* 1434 * Some non-compliant PCIe devices do not utilize PCIe 1435 * error registers. So fallthrough and rely on legacy 1436 * PCI error registers. 1437 */ 1438 if ((PCIE_DEVSTS_NFE_DETECTED | PCIE_DEVSTS_FE_DETECTED) 1439 & PCIE_ERR_REG(pfd_p)->pcie_err_status) 1440 break; 1441 /* FALLTHROUGH */ 1442 case PCIE_PCIECAP_DEV_TYPE_PCI_PSEUDO: 1443 sts_flags |= pf_analyse_error_tbl(derr, impl, 1444 pfd_p, pcie_pci_tbl, 1445 PCI_ERR_REG(pfd_p)->pci_err_status); 1446 1447 if (!PCIE_IS_BDG(PCIE_PFD2BUS(pfd_p))) 1448 break; 1449 1450 sts_flags |= pf_analyse_error_tbl(derr, 1451 impl, pfd_p, pcie_pci_bdg_tbl, 1452 PCI_BDG_ERR_REG(pfd_p)->pci_bdg_sec_stat); 1453 } 1454 1455 pfd_p->pe_severity_flags = sts_flags; 1456 1457 done: 1458 pfd_p->pe_orig_severity_flags = pfd_p->pe_severity_flags; 1459 /* Have pciev_eh adjust the severity */ 1460 pfd_p->pe_severity_flags = pciev_eh(pfd_p, impl); 1461 1462 error_flags |= pfd_p->pe_severity_flags; 1463 } 1464 1465 return (error_flags); 1466 } 1467 1468 static int 1469 pf_analyse_error_tbl(ddi_fm_error_t *derr, pf_impl_t *impl, 1470 pf_data_t *pfd_p, const pf_fab_err_tbl_t *tbl, uint32_t err_reg) 1471 { 1472 const pf_fab_err_tbl_t *row; 1473 int err = 0; 1474 uint16_t flags; 1475 uint32_t bit; 1476 1477 for (row = tbl; err_reg && (row->bit != 0); row++) { 1478 bit = row->bit; 1479 if (!(err_reg & bit)) 1480 continue; 1481 err |= row->handler(derr, bit, impl->pf_dq_head_p, pfd_p); 1482 1483 flags = row->affected_flags; 1484 /* 1485 * check if the primary flag is valid; 1486 * if not, use the secondary flag 1487 */ 1488 if (flags & PF_AFFECTED_AER) { 1489 if (!HAS_AER_LOGS(pfd_p, bit)) { 1490 flags = row->sec_affected_flags; 1491 } 1492 } else if (flags & PF_AFFECTED_SAER) { 1493 if (!HAS_SAER_LOGS(pfd_p, bit)) { 1494 flags = row->sec_affected_flags; 1495 } 1496 } else if (flags & PF_AFFECTED_ADDR) { 1497 /* only Root has this flag */ 1498 if (PCIE_ROOT_FAULT(pfd_p)->scan_addr == 0) { 1499 flags = row->sec_affected_flags; 1500 } 1501 } 1502 1503 PFD_AFFECTED_DEV(pfd_p)->pe_affected_flags |= flags; 1504 } 1505 1506 if (!err) 1507 err = PF_ERR_NO_ERROR; 1508 1509 return (err); 1510 } 1511 1512 /* 1513 * PCIe Completer Abort and Unsupport Request error analyser. If a PCIe device 1514 * issues a CA/UR a corresponding Received CA/UR should have been seen in the 1515 * PCIe root complex. Check to see if RC did indeed receive a CA/UR, if so then 1516 * this error may be safely ignored. If not check the logs and see if an 1517 * associated handler for this transaction can be found. 1518 */ 1519 /* ARGSUSED */ 1520 static int 1521 pf_analyse_ca_ur(ddi_fm_error_t *derr, uint32_t bit, pf_data_t *dq_head_p, 1522 pf_data_t *pfd_p) 1523 { 1524 uint32_t abort_type; 1525 dev_info_t *rpdip = PCIE_PFD2BUS(pfd_p)->bus_rp_dip; 1526 1527 /* If UR's are masked forgive this error */ 1528 if ((pcie_get_aer_uce_mask() & PCIE_AER_UCE_UR) && 1529 (bit == PCIE_AER_UCE_UR)) 1530 return (PF_ERR_NO_PANIC); 1531 1532 /* 1533 * If a RP has an CA/UR it means a leaf sent a bad request to the RP 1534 * such as a config read or a bad DMA address. 1535 */ 1536 if (PCIE_IS_RP(PCIE_PFD2BUS(pfd_p))) 1537 goto handle_lookup; 1538 1539 if (bit == PCIE_AER_UCE_UR) 1540 abort_type = PCI_STAT_R_MAST_AB; 1541 else 1542 abort_type = PCI_STAT_R_TARG_AB; 1543 1544 if (pf_matched_in_rc(dq_head_p, pfd_p, abort_type)) 1545 return (PF_ERR_MATCHED_RC); 1546 1547 handle_lookup: 1548 if (HAS_AER_LOGS(pfd_p, bit) && 1549 pf_log_hdl_lookup(rpdip, derr, pfd_p, B_TRUE) == PF_HDL_FOUND) 1550 return (PF_ERR_MATCHED_DEVICE); 1551 1552 return (PF_ERR_PANIC); 1553 } 1554 1555 /* 1556 * PCIe-PCI Bridge Received Master Abort and Target error analyser. If a PCIe 1557 * Bridge receives a MA/TA a corresponding sent CA/UR should have been seen in 1558 * the PCIe root complex. Check to see if RC did indeed receive a CA/UR, if so 1559 * then this error may be safely ignored. If not check the logs and see if an 1560 * associated handler for this transaction can be found. 1561 */ 1562 /* ARGSUSED */ 1563 static int 1564 pf_analyse_ma_ta(ddi_fm_error_t *derr, uint32_t bit, pf_data_t *dq_head_p, 1565 pf_data_t *pfd_p) 1566 { 1567 dev_info_t *rpdip = PCIE_PFD2BUS(pfd_p)->bus_rp_dip; 1568 uint32_t abort_type; 1569 1570 /* If UR's are masked forgive this error */ 1571 if ((pcie_get_aer_uce_mask() & PCIE_AER_UCE_UR) && 1572 (bit == PCIE_AER_SUCE_RCVD_MA)) 1573 return (PF_ERR_NO_PANIC); 1574 1575 if (bit == PCIE_AER_SUCE_RCVD_MA) 1576 abort_type = PCI_STAT_R_MAST_AB; 1577 else 1578 abort_type = PCI_STAT_R_TARG_AB; 1579 1580 if (pf_matched_in_rc(dq_head_p, pfd_p, abort_type)) 1581 return (PF_ERR_MATCHED_RC); 1582 1583 if (!HAS_SAER_LOGS(pfd_p, bit)) 1584 return (PF_ERR_PANIC); 1585 1586 if (pf_log_hdl_lookup(rpdip, derr, pfd_p, B_FALSE) == PF_HDL_FOUND) 1587 return (PF_ERR_MATCHED_DEVICE); 1588 1589 return (PF_ERR_PANIC); 1590 } 1591 1592 /* 1593 * Generic PCI error analyser. This function is used for Parity Errors, 1594 * Received Master Aborts, Received Target Aborts, and Signaled Target Aborts. 1595 * In general PCI devices do not have error logs, it is very difficult to figure 1596 * out what transaction caused the error. Instead find the nearest PCIe-PCI 1597 * Bridge and check to see if it has logs and if it has an error associated with 1598 * this PCI Device. 1599 */ 1600 /* ARGSUSED */ 1601 static int 1602 pf_analyse_pci(ddi_fm_error_t *derr, uint32_t bit, pf_data_t *dq_head_p, 1603 pf_data_t *pfd_p) 1604 { 1605 pf_data_t *parent_pfd_p; 1606 uint16_t cmd; 1607 uint32_t aer_ue_status; 1608 pcie_bus_t *bus_p = PCIE_PFD2BUS(pfd_p); 1609 pf_pcie_adv_bdg_err_regs_t *parent_saer_p; 1610 1611 if (PCI_ERR_REG(pfd_p)->pci_err_status & PCI_STAT_S_SYSERR) 1612 return (PF_ERR_PANIC); 1613 1614 /* If UR's are masked forgive this error */ 1615 if ((pcie_get_aer_uce_mask() & PCIE_AER_UCE_UR) && 1616 (bit == PCI_STAT_R_MAST_AB)) 1617 return (PF_ERR_NO_PANIC); 1618 1619 1620 if (bit & (PCI_STAT_PERROR | PCI_STAT_S_PERROR)) { 1621 aer_ue_status = PCIE_AER_SUCE_PERR_ASSERT; 1622 } else { 1623 aer_ue_status = (PCIE_AER_SUCE_TA_ON_SC | 1624 PCIE_AER_SUCE_MA_ON_SC | PCIE_AER_SUCE_RCVD_TA | 1625 PCIE_AER_SUCE_RCVD_MA); 1626 } 1627 1628 parent_pfd_p = pf_get_parent_pcie_bridge(pfd_p); 1629 if (parent_pfd_p == NULL) 1630 return (PF_ERR_PANIC); 1631 1632 /* Check if parent bridge has seen this error */ 1633 parent_saer_p = PCIE_ADV_BDG_REG(parent_pfd_p); 1634 if (!(parent_saer_p->pcie_sue_status & aer_ue_status) || 1635 !HAS_SAER_LOGS(parent_pfd_p, aer_ue_status)) 1636 return (PF_ERR_PANIC); 1637 1638 /* 1639 * If the addr or bdf from the parent PCIe bridge logs belong to this 1640 * PCI device, assume the PCIe bridge's error handling has already taken 1641 * care of this PCI device's error. 1642 */ 1643 if (pf_pci_decode(parent_pfd_p, &cmd) != DDI_SUCCESS) 1644 return (PF_ERR_PANIC); 1645 1646 if ((parent_saer_p->pcie_sue_tgt_bdf == bus_p->bus_bdf) || 1647 pf_in_addr_range(bus_p, parent_saer_p->pcie_sue_tgt_addr)) 1648 return (PF_ERR_MATCHED_PARENT); 1649 1650 /* 1651 * If this device is a PCI-PCI bridge, check if the bdf in the parent 1652 * PCIe bridge logs is in the range of this PCI-PCI Bridge's bus ranges. 1653 * If they are, then assume the PCIe bridge's error handling has already 1654 * taken care of this PCI-PCI bridge device's error. 1655 */ 1656 if (PCIE_IS_BDG(bus_p) && 1657 pf_in_bus_range(bus_p, parent_saer_p->pcie_sue_tgt_bdf)) 1658 return (PF_ERR_MATCHED_PARENT); 1659 1660 return (PF_ERR_PANIC); 1661 } 1662 1663 /* 1664 * PCIe Bridge transactions associated with PERR. 1665 * o Bridge received a poisoned Non-Posted Write (CFG Writes) from PCIe 1666 * o Bridge received a poisoned Posted Write from (MEM Writes) from PCIe 1667 * o Bridge received a poisoned Completion on a Split Transction from PCIe 1668 * o Bridge received a poisoned Completion on a Delayed Transction from PCIe 1669 * 1670 * Check for non-poisoned PCIe transactions that got forwarded to the secondary 1671 * side and detects a PERR#. Except for delayed read completions, a poisoned 1672 * TLP will be forwarded to the secondary bus and PERR# will be asserted. 1673 */ 1674 /* ARGSUSED */ 1675 static int 1676 pf_analyse_perr_assert(ddi_fm_error_t *derr, uint32_t bit, pf_data_t *dq_head_p, 1677 pf_data_t *pfd_p) 1678 { 1679 dev_info_t *rpdip = PCIE_PFD2BUS(pfd_p)->bus_rp_dip; 1680 uint16_t cmd; 1681 int hdl_sts = PF_HDL_NOTFOUND; 1682 int err = PF_ERR_NO_ERROR; 1683 pf_pcie_adv_bdg_err_regs_t *saer_p; 1684 1685 1686 if (HAS_SAER_LOGS(pfd_p, bit)) { 1687 saer_p = PCIE_ADV_BDG_REG(pfd_p); 1688 if (pf_pci_decode(pfd_p, &cmd) != DDI_SUCCESS) 1689 return (PF_ERR_PANIC); 1690 1691 cmd_switch: 1692 switch (cmd) { 1693 case PCI_PCIX_CMD_IOWR: 1694 case PCI_PCIX_CMD_MEMWR: 1695 case PCI_PCIX_CMD_MEMWR_BL: 1696 case PCI_PCIX_CMD_MEMWRBL: 1697 /* Posted Writes Transactions */ 1698 if (saer_p->pcie_sue_tgt_trans == PF_ADDR_PIO) 1699 hdl_sts = pf_log_hdl_lookup(rpdip, derr, pfd_p, 1700 B_FALSE); 1701 break; 1702 case PCI_PCIX_CMD_CFWR: 1703 /* 1704 * Check to see if it is a non-posted write. If so, a 1705 * UR Completion would have been sent. 1706 */ 1707 if (pf_matched_in_rc(dq_head_p, pfd_p, 1708 PCI_STAT_R_MAST_AB)) { 1709 hdl_sts = PF_HDL_FOUND; 1710 err = PF_ERR_MATCHED_RC; 1711 goto done; 1712 } 1713 hdl_sts = pf_log_hdl_lookup(rpdip, derr, pfd_p, 1714 B_FALSE); 1715 break; 1716 case PCI_PCIX_CMD_SPL: 1717 hdl_sts = pf_log_hdl_lookup(rpdip, derr, pfd_p, 1718 B_FALSE); 1719 break; 1720 case PCI_PCIX_CMD_DADR: 1721 cmd = (PCIE_ADV_BDG_HDR(pfd_p, 1) >> 1722 PCIE_AER_SUCE_HDR_CMD_UP_SHIFT) & 1723 PCIE_AER_SUCE_HDR_CMD_UP_MASK; 1724 if (cmd != PCI_PCIX_CMD_DADR) 1725 goto cmd_switch; 1726 /* FALLTHROUGH */ 1727 default: 1728 /* Unexpected situation, panic */ 1729 hdl_sts = PF_HDL_NOTFOUND; 1730 } 1731 1732 if (hdl_sts == PF_HDL_FOUND) 1733 err = PF_ERR_MATCHED_DEVICE; 1734 else 1735 err = PF_ERR_PANIC; 1736 } else { 1737 /* 1738 * Check to see if it is a non-posted write. If so, a UR 1739 * Completion would have been sent. 1740 */ 1741 if ((PCIE_ERR_REG(pfd_p)->pcie_err_status & 1742 PCIE_DEVSTS_UR_DETECTED) && 1743 pf_matched_in_rc(dq_head_p, pfd_p, PCI_STAT_R_MAST_AB)) 1744 err = PF_ERR_MATCHED_RC; 1745 1746 /* Check for posted writes. Transaction is lost. */ 1747 if (PCI_BDG_ERR_REG(pfd_p)->pci_bdg_sec_stat & 1748 PCI_STAT_S_PERROR) 1749 err = PF_ERR_PANIC; 1750 1751 /* 1752 * All other scenarios are due to read completions. Check for 1753 * PERR on the primary side. If found the primary side error 1754 * handling will take care of this error. 1755 */ 1756 if (err == PF_ERR_NO_ERROR) { 1757 if (PCI_ERR_REG(pfd_p)->pci_err_status & 1758 PCI_STAT_PERROR) 1759 err = PF_ERR_MATCHED_PARENT; 1760 else 1761 err = PF_ERR_PANIC; 1762 } 1763 } 1764 1765 done: 1766 return (err); 1767 } 1768 1769 /* 1770 * PCIe Poisoned TLP error analyser. If a PCIe device receives a Poisoned TLP, 1771 * check the logs and see if an associated handler for this transaction can be 1772 * found. 1773 */ 1774 /* ARGSUSED */ 1775 static int 1776 pf_analyse_ptlp(ddi_fm_error_t *derr, uint32_t bit, pf_data_t *dq_head_p, 1777 pf_data_t *pfd_p) 1778 { 1779 dev_info_t *rpdip = PCIE_PFD2BUS(pfd_p)->bus_rp_dip; 1780 1781 /* 1782 * If AERs are supported find the logs in this device, otherwise look in 1783 * it's parent's logs. 1784 */ 1785 if (HAS_AER_LOGS(pfd_p, bit)) { 1786 pcie_tlp_hdr_t *hdr = (pcie_tlp_hdr_t *)&PCIE_ADV_HDR(pfd_p, 0); 1787 1788 /* 1789 * Double check that the log contains a poisoned TLP. 1790 * Some devices like PLX switch do not log poison TLP headers. 1791 */ 1792 if (hdr->ep) { 1793 if (pf_log_hdl_lookup(rpdip, derr, pfd_p, B_TRUE) == 1794 PF_HDL_FOUND) 1795 return (PF_ERR_MATCHED_DEVICE); 1796 } 1797 1798 /* 1799 * If an address is found and hdl lookup failed panic. 1800 * Otherwise check parents to see if there was enough 1801 * information recover. 1802 */ 1803 if (PCIE_ADV_REG(pfd_p)->pcie_ue_tgt_addr) 1804 return (PF_ERR_PANIC); 1805 } 1806 1807 /* 1808 * Check to see if the rc has already handled this error or a parent has 1809 * already handled this error. 1810 * 1811 * If the error info in the RC wasn't enough to find the fault device, 1812 * such as if the faulting device lies behind a PCIe-PCI bridge from a 1813 * poisoned completion, check to see if the PCIe-PCI bridge has enough 1814 * info to recover. For completion TLP's, the AER header logs only 1815 * contain the faulting BDF in the Root Port. For PCIe device the fault 1816 * BDF is the fault device. But if the fault device is behind a 1817 * PCIe-PCI bridge the fault BDF could turn out just to be a PCIe-PCI 1818 * bridge's secondary bus number. 1819 */ 1820 if (!PFD_IS_ROOT(pfd_p)) { 1821 dev_info_t *pdip = ddi_get_parent(PCIE_PFD2DIP(pfd_p)); 1822 pf_data_t *parent_pfd_p; 1823 1824 if (PCIE_PFD2BUS(pfd_p)->bus_rp_dip == pdip) { 1825 if (pf_matched_in_rc(dq_head_p, pfd_p, PCI_STAT_PERROR)) 1826 return (PF_ERR_MATCHED_RC); 1827 } 1828 1829 parent_pfd_p = PCIE_DIP2PFD(pdip); 1830 1831 if (HAS_AER_LOGS(parent_pfd_p, bit)) 1832 return (PF_ERR_MATCHED_PARENT); 1833 } else { 1834 pf_data_t *bdg_pfd_p; 1835 pcie_req_id_t secbus; 1836 1837 /* 1838 * Looking for a pcie bridge only makes sense if the BDF 1839 * Dev/Func = 0/0 1840 */ 1841 if (!PCIE_HAS_AER(PCIE_PFD2BUS(pfd_p))) 1842 goto done; 1843 1844 secbus = PCIE_ADV_REG(pfd_p)->pcie_ue_tgt_bdf; 1845 1846 if (!PCIE_CHECK_VALID_BDF(secbus) || (secbus & 0xFF)) 1847 goto done; 1848 1849 bdg_pfd_p = pf_get_pcie_bridge(pfd_p, secbus); 1850 1851 if (bdg_pfd_p && HAS_SAER_LOGS(bdg_pfd_p, 1852 PCIE_AER_SUCE_PERR_ASSERT)) { 1853 return pf_analyse_perr_assert(derr, 1854 PCIE_AER_SUCE_PERR_ASSERT, dq_head_p, pfd_p); 1855 } 1856 } 1857 done: 1858 return (PF_ERR_PANIC); 1859 } 1860 1861 /* 1862 * PCIe-PCI Bridge Received Master and Target abort error analyser on Split 1863 * Completions. If a PCIe Bridge receives a MA/TA check logs and see if an 1864 * associated handler for this transaction can be found. 1865 */ 1866 /* ARGSUSED */ 1867 static int 1868 pf_analyse_sc(ddi_fm_error_t *derr, uint32_t bit, pf_data_t *dq_head_p, 1869 pf_data_t *pfd_p) 1870 { 1871 dev_info_t *rpdip = PCIE_PFD2BUS(pfd_p)->bus_rp_dip; 1872 uint16_t cmd; 1873 int sts = PF_HDL_NOTFOUND; 1874 1875 if (!HAS_SAER_LOGS(pfd_p, bit)) 1876 return (PF_ERR_PANIC); 1877 1878 if (pf_pci_decode(pfd_p, &cmd) != DDI_SUCCESS) 1879 return (PF_ERR_PANIC); 1880 1881 if (cmd == PCI_PCIX_CMD_SPL) 1882 sts = pf_log_hdl_lookup(rpdip, derr, pfd_p, B_FALSE); 1883 1884 if (sts == PF_HDL_FOUND) 1885 return (PF_ERR_MATCHED_DEVICE); 1886 1887 return (PF_ERR_PANIC); 1888 } 1889 1890 /* 1891 * PCIe Timeout error analyser. This error can be forgiven if it is marked as 1892 * CE Advisory. If it is marked as advisory, this means the HW can recover 1893 * and/or retry the transaction automatically. 1894 */ 1895 /* ARGSUSED */ 1896 static int 1897 pf_analyse_to(ddi_fm_error_t *derr, uint32_t bit, pf_data_t *dq_head_p, 1898 pf_data_t *pfd_p) 1899 { 1900 if (HAS_AER_LOGS(pfd_p, bit) && CE_ADVISORY(pfd_p)) 1901 return (PF_ERR_NO_PANIC); 1902 1903 return (PF_ERR_PANIC); 1904 } 1905 1906 /* 1907 * PCIe Unexpected Completion. Check to see if this TLP was misrouted by 1908 * matching the device BDF with the TLP Log. If misrouting panic, otherwise 1909 * don't panic. 1910 */ 1911 /* ARGSUSED */ 1912 static int 1913 pf_analyse_uc(ddi_fm_error_t *derr, uint32_t bit, pf_data_t *dq_head_p, 1914 pf_data_t *pfd_p) 1915 { 1916 if (HAS_AER_LOGS(pfd_p, bit) && 1917 (PCIE_PFD2BUS(pfd_p)->bus_bdf == (PCIE_ADV_HDR(pfd_p, 2) >> 16))) 1918 return (PF_ERR_NO_PANIC); 1919 1920 /* 1921 * This is a case of mis-routing. Any of the switches above this 1922 * device could be at fault. 1923 */ 1924 PFD_AFFECTED_DEV(pfd_p)->pe_affected_flags = PF_AFFECTED_ROOT; 1925 1926 return (PF_ERR_PANIC); 1927 } 1928 1929 /* 1930 * PCIe-PCI Bridge Uncorrectable Data error analyser. All Uncorrectable Data 1931 * errors should have resulted in a PCIe Poisoned TLP to the RC, except for 1932 * Posted Writes. Check the logs for Posted Writes and if the RC did not see a 1933 * Poisoned TLP. 1934 * 1935 * Non-Posted Writes will also generate a UR in the completion status, which the 1936 * RC should also see. 1937 */ 1938 /* ARGSUSED */ 1939 static int 1940 pf_analyse_uc_data(ddi_fm_error_t *derr, uint32_t bit, pf_data_t *dq_head_p, 1941 pf_data_t *pfd_p) 1942 { 1943 dev_info_t *rpdip = PCIE_PFD2BUS(pfd_p)->bus_rp_dip; 1944 1945 if (!HAS_SAER_LOGS(pfd_p, bit)) 1946 return (PF_ERR_PANIC); 1947 1948 if (pf_matched_in_rc(dq_head_p, pfd_p, PCI_STAT_PERROR)) 1949 return (PF_ERR_MATCHED_RC); 1950 1951 if (pf_log_hdl_lookup(rpdip, derr, pfd_p, B_FALSE) == PF_HDL_FOUND) 1952 return (PF_ERR_MATCHED_DEVICE); 1953 1954 return (PF_ERR_PANIC); 1955 } 1956 1957 /* ARGSUSED */ 1958 static int 1959 pf_no_panic(ddi_fm_error_t *derr, uint32_t bit, pf_data_t *dq_head_p, 1960 pf_data_t *pfd_p) 1961 { 1962 return (PF_ERR_NO_PANIC); 1963 } 1964 1965 /* ARGSUSED */ 1966 static int 1967 pf_panic(ddi_fm_error_t *derr, uint32_t bit, pf_data_t *dq_head_p, 1968 pf_data_t *pfd_p) 1969 { 1970 return (PF_ERR_PANIC); 1971 } 1972 1973 /* 1974 * If a PCIe device does not support AER, assume all AER statuses have been set, 1975 * unless other registers do not indicate a certain error occuring. 1976 */ 1977 static void 1978 pf_adjust_for_no_aer(pf_data_t *pfd_p) 1979 { 1980 uint32_t aer_ue = 0; 1981 uint16_t status; 1982 1983 if (PCIE_HAS_AER(PCIE_PFD2BUS(pfd_p))) 1984 return; 1985 1986 if (PCIE_ERR_REG(pfd_p)->pcie_err_status & PCIE_DEVSTS_FE_DETECTED) 1987 aer_ue = PF_AER_FATAL_ERR; 1988 1989 if (PCIE_ERR_REG(pfd_p)->pcie_err_status & PCIE_DEVSTS_NFE_DETECTED) { 1990 aer_ue = PF_AER_NON_FATAL_ERR; 1991 status = PCI_ERR_REG(pfd_p)->pci_err_status; 1992 1993 /* Check if the device received a PTLP */ 1994 if (!(status & PCI_STAT_PERROR)) 1995 aer_ue &= ~PCIE_AER_UCE_PTLP; 1996 1997 /* Check if the device signaled a CA */ 1998 if (!(status & PCI_STAT_S_TARG_AB)) 1999 aer_ue &= ~PCIE_AER_UCE_CA; 2000 2001 /* Check if the device sent a UR */ 2002 if (!(PCIE_ERR_REG(pfd_p)->pcie_err_status & 2003 PCIE_DEVSTS_UR_DETECTED)) 2004 aer_ue &= ~PCIE_AER_UCE_UR; 2005 2006 /* 2007 * Ignore ECRCs as it is optional and will manefest itself as 2008 * another error like PTLP and MFP 2009 */ 2010 aer_ue &= ~PCIE_AER_UCE_ECRC; 2011 2012 /* 2013 * Generally if NFE is set, SERR should also be set. Exception: 2014 * When certain non-fatal errors are masked, and some of them 2015 * happened to be the cause of the NFE, SERR will not be set and 2016 * they can not be the source of this interrupt. 2017 * 2018 * On x86, URs are masked (NFE + UR can be set), if any other 2019 * non-fatal errors (i.e, PTLP, CTO, CA, UC, ECRC, ACS) did 2020 * occur, SERR should be set since they are not masked. So if 2021 * SERR is not set, none of them occurred. 2022 */ 2023 if (!(status & PCI_STAT_S_SYSERR)) 2024 aer_ue &= ~PCIE_AER_UCE_TO; 2025 } 2026 2027 if (!PCIE_IS_BDG(PCIE_PFD2BUS(pfd_p))) { 2028 aer_ue &= ~PCIE_AER_UCE_TRAINING; 2029 aer_ue &= ~PCIE_AER_UCE_SD; 2030 } 2031 2032 PCIE_ADV_REG(pfd_p)->pcie_ue_status = aer_ue; 2033 } 2034 2035 static void 2036 pf_adjust_for_no_saer(pf_data_t *pfd_p) 2037 { 2038 uint32_t s_aer_ue = 0; 2039 uint16_t status; 2040 2041 if (PCIE_HAS_AER(PCIE_PFD2BUS(pfd_p))) 2042 return; 2043 2044 if (PCIE_ERR_REG(pfd_p)->pcie_err_status & PCIE_DEVSTS_FE_DETECTED) 2045 s_aer_ue = PF_SAER_FATAL_ERR; 2046 2047 if (PCIE_ERR_REG(pfd_p)->pcie_err_status & PCIE_DEVSTS_NFE_DETECTED) { 2048 s_aer_ue = PF_SAER_NON_FATAL_ERR; 2049 status = PCI_BDG_ERR_REG(pfd_p)->pci_bdg_sec_stat; 2050 2051 /* Check if the device received a UC_DATA */ 2052 if (!(status & PCI_STAT_PERROR)) 2053 s_aer_ue &= ~PCIE_AER_SUCE_UC_DATA_ERR; 2054 2055 /* Check if the device received a RCVD_MA/MA_ON_SC */ 2056 if (!(status & (PCI_STAT_R_MAST_AB))) { 2057 s_aer_ue &= ~PCIE_AER_SUCE_RCVD_MA; 2058 s_aer_ue &= ~PCIE_AER_SUCE_MA_ON_SC; 2059 } 2060 2061 /* Check if the device received a RCVD_TA/TA_ON_SC */ 2062 if (!(status & (PCI_STAT_R_TARG_AB))) { 2063 s_aer_ue &= ~PCIE_AER_SUCE_RCVD_TA; 2064 s_aer_ue &= ~PCIE_AER_SUCE_TA_ON_SC; 2065 } 2066 } 2067 2068 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_status = s_aer_ue; 2069 } 2070 2071 /* Find the PCIe-PCI bridge based on secondary bus number */ 2072 static pf_data_t * 2073 pf_get_pcie_bridge(pf_data_t *pfd_p, pcie_req_id_t secbus) 2074 { 2075 pf_data_t *bdg_pfd_p; 2076 2077 /* Search down for the PCIe-PCI device. */ 2078 for (bdg_pfd_p = pfd_p->pe_next; bdg_pfd_p; 2079 bdg_pfd_p = bdg_pfd_p->pe_next) { 2080 if (PCIE_IS_PCIE_BDG(PCIE_PFD2BUS(bdg_pfd_p)) && 2081 PCIE_PFD2BUS(bdg_pfd_p)->bus_bdg_secbus == secbus) 2082 return (bdg_pfd_p); 2083 } 2084 2085 return (NULL); 2086 } 2087 2088 /* Find the PCIe-PCI bridge of a PCI device */ 2089 static pf_data_t * 2090 pf_get_parent_pcie_bridge(pf_data_t *pfd_p) 2091 { 2092 dev_info_t *dip, *rp_dip = PCIE_PFD2BUS(pfd_p)->bus_rp_dip; 2093 2094 /* This only makes sense if the device is a PCI device */ 2095 if (!PCIE_IS_PCI(PCIE_PFD2BUS(pfd_p))) 2096 return (NULL); 2097 2098 /* 2099 * Search up for the PCIe-PCI device. Watchout for x86 where pci 2100 * devices hang directly off of NPE. 2101 */ 2102 for (dip = PCIE_PFD2DIP(pfd_p); dip; dip = ddi_get_parent(dip)) { 2103 if (dip == rp_dip) 2104 dip = NULL; 2105 2106 if (PCIE_IS_PCIE_BDG(PCIE_DIP2BUS(dip))) 2107 return (PCIE_DIP2PFD(dip)); 2108 } 2109 2110 return (NULL); 2111 } 2112 2113 /* 2114 * See if a leaf error was bubbled up to the Root Complex (RC) and handled. 2115 * As of right now only RC's have enough information to have errors found in the 2116 * fabric to be matched to the RC. Note that Root Port's (RP) do not carry 2117 * enough information. Currently known RC's are SPARC Fire architecture and 2118 * it's equivalents, and x86's NPE. 2119 * SPARC Fire architectures have a plethora of error registers, while currently 2120 * NPE only have the address of a failed load. 2121 * 2122 * Check if the RC logged an error with the appropriate status type/abort type. 2123 * Ex: Parity Error, Received Master/Target Abort 2124 * Check if either the fault address found in the rc matches the device's 2125 * assigned address range (PIO's only) or the fault BDF in the rc matches the 2126 * device's BDF or Secondary Bus/Bus Range. 2127 */ 2128 static boolean_t 2129 pf_matched_in_rc(pf_data_t *dq_head_p, pf_data_t *pfd_p, 2130 uint32_t abort_type) 2131 { 2132 pcie_bus_t *bus_p = PCIE_PFD2BUS(pfd_p); 2133 pf_data_t *rc_pfd_p; 2134 pcie_req_id_t fault_bdf; 2135 2136 for (rc_pfd_p = dq_head_p; PFD_IS_ROOT(rc_pfd_p); 2137 rc_pfd_p = rc_pfd_p->pe_next) { 2138 /* Only root complex's have enough information to match */ 2139 if (!PCIE_IS_RC(PCIE_PFD2BUS(rc_pfd_p))) 2140 continue; 2141 2142 /* If device and rc abort type does not match continue */ 2143 if (!(PCI_BDG_ERR_REG(rc_pfd_p)->pci_bdg_sec_stat & abort_type)) 2144 continue; 2145 2146 fault_bdf = PCIE_ROOT_FAULT(rc_pfd_p)->scan_bdf; 2147 2148 /* The Fault BDF = Device's BDF */ 2149 if (fault_bdf == bus_p->bus_bdf) 2150 return (B_TRUE); 2151 2152 /* The Fault Addr is in device's address range */ 2153 if (pf_in_addr_range(bus_p, 2154 PCIE_ROOT_FAULT(rc_pfd_p)->scan_addr)) 2155 return (B_TRUE); 2156 2157 /* The Fault BDF is from PCIe-PCI Bridge's secondary bus */ 2158 if (PCIE_IS_PCIE_BDG(bus_p) && 2159 pf_in_bus_range(bus_p, fault_bdf)) 2160 return (B_TRUE); 2161 } 2162 2163 return (B_FALSE); 2164 } 2165 2166 /* 2167 * Check the RP and see if the error is PIO/DMA. If the RP also has a PERR then 2168 * it is a DMA, otherwise it's a PIO 2169 */ 2170 static void 2171 pf_pci_find_trans_type(pf_data_t *pfd_p, uint64_t *addr, uint32_t *trans_type, 2172 pcie_req_id_t *bdf) 2173 { 2174 pf_data_t *rc_pfd_p; 2175 2176 /* Could be DMA or PIO. Find out by look at error type. */ 2177 switch (PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_status) { 2178 case PCIE_AER_SUCE_TA_ON_SC: 2179 case PCIE_AER_SUCE_MA_ON_SC: 2180 *trans_type = PF_ADDR_DMA; 2181 return; 2182 case PCIE_AER_SUCE_RCVD_TA: 2183 case PCIE_AER_SUCE_RCVD_MA: 2184 *bdf = PCIE_INVALID_BDF; 2185 *trans_type = PF_ADDR_PIO; 2186 return; 2187 case PCIE_AER_SUCE_USC_ERR: 2188 case PCIE_AER_SUCE_UC_DATA_ERR: 2189 case PCIE_AER_SUCE_PERR_ASSERT: 2190 break; 2191 default: 2192 *addr = 0; 2193 *bdf = PCIE_INVALID_BDF; 2194 *trans_type = 0; 2195 return; 2196 } 2197 2198 *bdf = PCIE_INVALID_BDF; 2199 *trans_type = PF_ADDR_PIO; 2200 for (rc_pfd_p = pfd_p->pe_prev; rc_pfd_p; 2201 rc_pfd_p = rc_pfd_p->pe_prev) { 2202 if (PFD_IS_ROOT(rc_pfd_p) && 2203 (PCI_BDG_ERR_REG(rc_pfd_p)->pci_bdg_sec_stat & 2204 PCI_STAT_PERROR)) { 2205 *trans_type = PF_ADDR_DMA; 2206 return; 2207 } 2208 } 2209 } 2210 2211 /* 2212 * pf_pci_decode function decodes the secondary aer transaction logs in 2213 * PCIe-PCI bridges. 2214 * 2215 * The log is 128 bits long and arranged in this manner. 2216 * [0:35] Transaction Attribute (s_aer_h0-saer_h1) 2217 * [36:39] Transaction lower command (saer_h1) 2218 * [40:43] Transaction upper command (saer_h1) 2219 * [44:63] Reserved 2220 * [64:127] Address (saer_h2-saer_h3) 2221 */ 2222 /* ARGSUSED */ 2223 int 2224 pf_pci_decode(pf_data_t *pfd_p, uint16_t *cmd) 2225 { 2226 pcix_attr_t *attr; 2227 uint64_t addr; 2228 uint32_t trans_type; 2229 pcie_req_id_t bdf = PCIE_INVALID_BDF; 2230 2231 attr = (pcix_attr_t *)&PCIE_ADV_BDG_HDR(pfd_p, 0); 2232 *cmd = GET_SAER_CMD(pfd_p); 2233 2234 cmd_switch: 2235 switch (*cmd) { 2236 case PCI_PCIX_CMD_IORD: 2237 case PCI_PCIX_CMD_IOWR: 2238 /* IO Access should always be down stream */ 2239 addr = PCIE_ADV_BDG_HDR(pfd_p, 2); 2240 bdf = attr->rid; 2241 trans_type = PF_ADDR_PIO; 2242 break; 2243 case PCI_PCIX_CMD_MEMRD_DW: 2244 case PCI_PCIX_CMD_MEMRD_BL: 2245 case PCI_PCIX_CMD_MEMRDBL: 2246 case PCI_PCIX_CMD_MEMWR: 2247 case PCI_PCIX_CMD_MEMWR_BL: 2248 case PCI_PCIX_CMD_MEMWRBL: 2249 addr = ((uint64_t)PCIE_ADV_BDG_HDR(pfd_p, 3) << 2250 PCIE_AER_SUCE_HDR_ADDR_SHIFT) | PCIE_ADV_BDG_HDR(pfd_p, 2); 2251 bdf = attr->rid; 2252 2253 pf_pci_find_trans_type(pfd_p, &addr, &trans_type, &bdf); 2254 break; 2255 case PCI_PCIX_CMD_CFRD: 2256 case PCI_PCIX_CMD_CFWR: 2257 /* 2258 * CFG Access should always be down stream. Match the BDF in 2259 * the address phase. 2260 */ 2261 addr = 0; 2262 bdf = attr->rid; 2263 trans_type = PF_ADDR_CFG; 2264 break; 2265 case PCI_PCIX_CMD_SPL: 2266 /* 2267 * Check for DMA read completions. The requesting BDF is in the 2268 * Address phase. 2269 */ 2270 addr = 0; 2271 bdf = attr->rid; 2272 trans_type = PF_ADDR_DMA; 2273 break; 2274 case PCI_PCIX_CMD_DADR: 2275 /* 2276 * For Dual Address Cycles the transaction command is in the 2nd 2277 * address phase. 2278 */ 2279 *cmd = (PCIE_ADV_BDG_HDR(pfd_p, 1) >> 2280 PCIE_AER_SUCE_HDR_CMD_UP_SHIFT) & 2281 PCIE_AER_SUCE_HDR_CMD_UP_MASK; 2282 if (*cmd != PCI_PCIX_CMD_DADR) 2283 goto cmd_switch; 2284 /* FALLTHROUGH */ 2285 default: 2286 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_tgt_trans = 0; 2287 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_tgt_bdf = PCIE_INVALID_BDF; 2288 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_tgt_addr = 0; 2289 return (DDI_FAILURE); 2290 } 2291 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_tgt_trans = trans_type; 2292 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_tgt_bdf = bdf; 2293 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_tgt_addr = addr; 2294 return (DDI_SUCCESS); 2295 } 2296 2297 /* 2298 * Based on either the BDF/ADDR find and mark the faulting DMA/ACC handler. 2299 * Returns either PF_HDL_NOTFOUND or PF_HDL_FOUND. 2300 */ 2301 int 2302 pf_hdl_lookup(dev_info_t *dip, uint64_t ena, uint32_t flag, uint64_t addr, 2303 pcie_req_id_t bdf) 2304 { 2305 ddi_fm_error_t derr; 2306 2307 /* If we don't know the addr or rid just return with NOTFOUND */ 2308 if ((addr == 0) && !PCIE_CHECK_VALID_BDF(bdf)) 2309 return (PF_HDL_NOTFOUND); 2310 2311 /* 2312 * Disable DMA handle lookup until DMA errors can be handled and 2313 * reported synchronously. When enabled again, check for the 2314 * PF_ADDR_DMA flag 2315 */ 2316 if (!(flag & (PF_ADDR_PIO | PF_ADDR_CFG))) { 2317 return (PF_HDL_NOTFOUND); 2318 } 2319 2320 bzero(&derr, sizeof (ddi_fm_error_t)); 2321 derr.fme_version = DDI_FME_VERSION; 2322 derr.fme_flag = DDI_FM_ERR_UNEXPECTED; 2323 derr.fme_ena = ena; 2324 2325 return (pf_hdl_child_lookup(dip, &derr, flag, addr, bdf)); 2326 } 2327 2328 static int 2329 pf_hdl_child_lookup(dev_info_t *dip, ddi_fm_error_t *derr, uint32_t flag, 2330 uint64_t addr, pcie_req_id_t bdf) 2331 { 2332 int status = PF_HDL_NOTFOUND; 2333 ndi_fmc_t *fcp = NULL; 2334 struct i_ddi_fmhdl *fmhdl = DEVI(dip)->devi_fmhdl; 2335 pcie_req_id_t dip_bdf; 2336 boolean_t have_lock = B_FALSE; 2337 pcie_bus_t *bus_p; 2338 dev_info_t *cdip; 2339 2340 if (!(bus_p = pf_is_ready(dip))) { 2341 return (status); 2342 } 2343 2344 ASSERT(fmhdl); 2345 if (!i_ddi_fm_handler_owned(dip)) { 2346 /* 2347 * pf_handler_enter always returns SUCCESS if the 'impl' arg is 2348 * NULL. 2349 */ 2350 (void) pf_handler_enter(dip, NULL); 2351 have_lock = B_TRUE; 2352 } 2353 2354 dip_bdf = PCI_GET_BDF(dip); 2355 2356 /* Check if dip and BDF match, if not recurse to it's children. */ 2357 if (!PCIE_IS_RC(bus_p) && (!PCIE_CHECK_VALID_BDF(bdf) || 2358 dip_bdf == bdf)) { 2359 if ((flag & PF_ADDR_DMA) && DDI_FM_DMA_ERR_CAP(fmhdl->fh_cap)) 2360 fcp = fmhdl->fh_dma_cache; 2361 else 2362 fcp = NULL; 2363 2364 if (fcp) 2365 status = pf_hdl_compare(dip, derr, DMA_HANDLE, addr, 2366 bdf, fcp); 2367 2368 2369 if (((flag & PF_ADDR_PIO) || (flag & PF_ADDR_CFG)) && 2370 DDI_FM_ACC_ERR_CAP(fmhdl->fh_cap)) 2371 fcp = fmhdl->fh_acc_cache; 2372 else 2373 fcp = NULL; 2374 2375 if (fcp) 2376 status = pf_hdl_compare(dip, derr, ACC_HANDLE, addr, 2377 bdf, fcp); 2378 } 2379 2380 /* If we found the handler or know it's this device, we're done */ 2381 if (!PCIE_IS_RC(bus_p) && ((dip_bdf == bdf) || 2382 (status == PF_HDL_FOUND))) 2383 goto done; 2384 2385 /* 2386 * If the current devuce us a PCIe-PCI bridge need to check for special 2387 * cases: 2388 * 2389 * If it is a PIO and we don't have an address or this is a DMA, check 2390 * to see if the BDF = secondary bus. If so stop. The BDF isn't a real 2391 * BDF and the fault device could have come from any device in the PCI 2392 * bus. 2393 */ 2394 if (PCIE_IS_PCIE_BDG(bus_p) && 2395 ((flag & PF_ADDR_DMA || flag & PF_ADDR_PIO)) && 2396 ((bus_p->bus_bdg_secbus << PCIE_REQ_ID_BUS_SHIFT) == bdf)) 2397 goto done; 2398 2399 2400 /* If we can't find the handler check it's children */ 2401 for (cdip = ddi_get_child(dip); cdip; 2402 cdip = ddi_get_next_sibling(cdip)) { 2403 if ((bus_p = PCIE_DIP2BUS(cdip)) == NULL) 2404 continue; 2405 2406 if (pf_in_bus_range(bus_p, bdf) || 2407 pf_in_addr_range(bus_p, addr)) 2408 status = pf_hdl_child_lookup(cdip, derr, flag, addr, 2409 bdf); 2410 2411 if (status == PF_HDL_FOUND) 2412 goto done; 2413 } 2414 2415 done: 2416 if (have_lock == B_TRUE) 2417 pf_handler_exit(dip); 2418 2419 return (status); 2420 } 2421 2422 static int 2423 pf_hdl_compare(dev_info_t *dip, ddi_fm_error_t *derr, uint32_t flag, 2424 uint64_t addr, pcie_req_id_t bdf, ndi_fmc_t *fcp) 2425 { 2426 ndi_fmcentry_t *fep; 2427 int found = 0; 2428 int status; 2429 2430 mutex_enter(&fcp->fc_lock); 2431 for (fep = fcp->fc_head; fep != NULL; fep = fep->fce_next) { 2432 ddi_fmcompare_t compare_func; 2433 2434 /* 2435 * Compare captured error state with handle 2436 * resources. During the comparison and 2437 * subsequent error handling, we block 2438 * attempts to free the cache entry. 2439 */ 2440 if (flag == ACC_HANDLE) { 2441 compare_func = 2442 i_ddi_fm_acc_err_cf_get((ddi_acc_handle_t) 2443 fep->fce_resource); 2444 } else { 2445 compare_func = 2446 i_ddi_fm_dma_err_cf_get((ddi_dma_handle_t) 2447 fep->fce_resource); 2448 } 2449 2450 if (compare_func == NULL) /* unbound or not FLAGERR */ 2451 continue; 2452 2453 status = compare_func(dip, fep->fce_resource, 2454 (void *)&addr, (void *)&bdf); 2455 2456 if (status == DDI_FM_NONFATAL) { 2457 found++; 2458 2459 /* Set the error for this resource handle */ 2460 if (flag == ACC_HANDLE) { 2461 ddi_acc_handle_t ap = fep->fce_resource; 2462 2463 i_ddi_fm_acc_err_set(ap, derr->fme_ena, status, 2464 DDI_FM_ERR_UNEXPECTED); 2465 ddi_fm_acc_err_get(ap, derr, DDI_FME_VERSION); 2466 derr->fme_acc_handle = ap; 2467 } else { 2468 ddi_dma_handle_t dp = fep->fce_resource; 2469 2470 i_ddi_fm_dma_err_set(dp, derr->fme_ena, status, 2471 DDI_FM_ERR_UNEXPECTED); 2472 ddi_fm_dma_err_get(dp, derr, DDI_FME_VERSION); 2473 derr->fme_dma_handle = dp; 2474 } 2475 } 2476 } 2477 mutex_exit(&fcp->fc_lock); 2478 2479 /* 2480 * If a handler isn't found and we know this is the right device mark 2481 * them all failed. 2482 */ 2483 if ((addr != 0) && PCIE_CHECK_VALID_BDF(bdf) && (found == 0)) { 2484 status = pf_hdl_compare(dip, derr, flag, addr, bdf, fcp); 2485 if (status == PF_HDL_FOUND) 2486 found++; 2487 } 2488 2489 return ((found) ? PF_HDL_FOUND : PF_HDL_NOTFOUND); 2490 } 2491 2492 /* 2493 * Automatically decode AER header logs and does a handling look up based on the 2494 * AER header decoding. 2495 * 2496 * For this function only the Primary/Secondary AER Header Logs need to be valid 2497 * in the pfd (PCIe Fault Data) arg. 2498 * 2499 * Returns either PF_HDL_NOTFOUND or PF_HDL_FOUND. 2500 */ 2501 /* ARGSUSED */ 2502 static int 2503 pf_log_hdl_lookup(dev_info_t *rpdip, ddi_fm_error_t *derr, pf_data_t *pfd_p, 2504 boolean_t is_primary) 2505 { 2506 /* 2507 * Disabling this function temporarily until errors can be handled 2508 * synchronously. 2509 * 2510 * This function is currently only called during the middle of a fabric 2511 * scan. If the fabric scan is called synchronously with an error seen 2512 * in the RP/RC, then the related errors in the fabric will have a 2513 * PF_ERR_MATCHED_RC error severity. pf_log_hdl_lookup code will be by 2514 * passed when the severity is PF_ERR_MATCHED_RC. Handle lookup would 2515 * have already happened in RP/RC error handling in a synchronous 2516 * manner. Errors unrelated should panic, because they are being 2517 * handled asynchronously. 2518 * 2519 * If fabric scan is called asynchronously from any RP/RC error, then 2520 * DMA/PIO UE errors seen in the fabric should panic. pf_lop_hdl_lookup 2521 * will return PF_HDL_NOTFOUND to ensure that the system panics. 2522 */ 2523 return (PF_HDL_NOTFOUND); 2524 } 2525 2526 /* 2527 * Decodes the TLP and returns the BDF of the handler, address and transaction 2528 * type if known. 2529 * 2530 * Types of TLP logs seen in RC, and what to extract: 2531 * 2532 * Memory(DMA) - Requester BDF, address, PF_DMA_ADDR 2533 * Memory(PIO) - address, PF_PIO_ADDR 2534 * CFG - Should not occur and result in UR 2535 * Completion(DMA) - Requester BDF, PF_DMA_ADDR 2536 * Completion(PIO) - Requester BDF, PF_PIO_ADDR 2537 * 2538 * Types of TLP logs seen in SW/Leaf, and what to extract: 2539 * 2540 * Memory(DMA) - Requester BDF, address, PF_DMA_ADDR 2541 * Memory(PIO) - address, PF_PIO_ADDR 2542 * CFG - Destined BDF, address, PF_CFG_ADDR 2543 * Completion(DMA) - Requester BDF, PF_DMA_ADDR 2544 * Completion(PIO) - Requester BDF, PF_PIO_ADDR 2545 * 2546 * The adv_reg_p must be passed in separately for use with SPARC RPs. A 2547 * SPARC RP could have multiple AER header logs which cannot be directly 2548 * accessed via the bus_p. 2549 */ 2550 int 2551 pf_tlp_decode(pcie_bus_t *bus_p, pf_pcie_adv_err_regs_t *adv_reg_p) 2552 { 2553 pcie_tlp_hdr_t *tlp_hdr = (pcie_tlp_hdr_t *)adv_reg_p->pcie_ue_hdr; 2554 pcie_req_id_t my_bdf, tlp_bdf, flt_bdf = PCIE_INVALID_BDF; 2555 uint64_t flt_addr = 0; 2556 uint32_t flt_trans_type = 0; 2557 2558 adv_reg_p->pcie_ue_tgt_addr = 0; 2559 adv_reg_p->pcie_ue_tgt_bdf = PCIE_INVALID_BDF; 2560 adv_reg_p->pcie_ue_tgt_trans = 0; 2561 2562 my_bdf = bus_p->bus_bdf; 2563 switch (tlp_hdr->type) { 2564 case PCIE_TLP_TYPE_IO: 2565 case PCIE_TLP_TYPE_MEM: 2566 case PCIE_TLP_TYPE_MEMLK: 2567 /* Grab the 32/64bit fault address */ 2568 if (tlp_hdr->fmt & 0x1) { 2569 flt_addr = ((uint64_t)adv_reg_p->pcie_ue_hdr[2] << 32); 2570 flt_addr |= adv_reg_p->pcie_ue_hdr[3]; 2571 } else { 2572 flt_addr = adv_reg_p->pcie_ue_hdr[2]; 2573 } 2574 2575 tlp_bdf = (pcie_req_id_t)(adv_reg_p->pcie_ue_hdr[1] >> 16); 2576 2577 /* 2578 * If the req bdf >= this.bdf, then it means the request is this 2579 * device or came from a device below it. Unless this device is 2580 * a PCIe root port then it means is a DMA, otherwise PIO. 2581 */ 2582 if ((tlp_bdf >= my_bdf) && !PCIE_IS_ROOT(bus_p)) { 2583 flt_trans_type = PF_ADDR_DMA; 2584 flt_bdf = tlp_bdf; 2585 } else if (PCIE_IS_ROOT(bus_p) && 2586 (PF_FIRST_AER_ERR(PCIE_AER_UCE_PTLP, adv_reg_p) || 2587 (PF_FIRST_AER_ERR(PCIE_AER_UCE_CA, adv_reg_p)))) { 2588 flt_trans_type = PF_ADDR_DMA; 2589 flt_bdf = tlp_bdf; 2590 } else { 2591 flt_trans_type = PF_ADDR_PIO; 2592 flt_bdf = PCIE_INVALID_BDF; 2593 } 2594 break; 2595 case PCIE_TLP_TYPE_CFG0: 2596 case PCIE_TLP_TYPE_CFG1: 2597 flt_addr = 0; 2598 flt_bdf = (pcie_req_id_t)(adv_reg_p->pcie_ue_hdr[2] >> 16); 2599 flt_trans_type = PF_ADDR_CFG; 2600 break; 2601 case PCIE_TLP_TYPE_CPL: 2602 case PCIE_TLP_TYPE_CPLLK: 2603 { 2604 pcie_cpl_t *cpl_tlp = (pcie_cpl_t *)&adv_reg_p->pcie_ue_hdr[1]; 2605 2606 flt_addr = 0; 2607 flt_bdf = (cpl_tlp->rid > cpl_tlp->cid) ? cpl_tlp->rid : 2608 cpl_tlp->cid; 2609 2610 /* 2611 * If the cpl bdf < this.bdf, then it means the request is this 2612 * device or came from a device below it. Unless this device is 2613 * a PCIe root port then it means is a DMA, otherwise PIO. 2614 */ 2615 if (cpl_tlp->rid > cpl_tlp->cid) { 2616 flt_trans_type = PF_ADDR_DMA; 2617 } else { 2618 flt_trans_type = PF_ADDR_PIO | PF_ADDR_CFG; 2619 } 2620 break; 2621 } 2622 default: 2623 return (DDI_FAILURE); 2624 } 2625 2626 adv_reg_p->pcie_ue_tgt_addr = flt_addr; 2627 adv_reg_p->pcie_ue_tgt_bdf = flt_bdf; 2628 adv_reg_p->pcie_ue_tgt_trans = flt_trans_type; 2629 2630 return (DDI_SUCCESS); 2631 } 2632 2633 #define PCIE_EREPORT DDI_IO_CLASS "." PCI_ERROR_SUBCLASS "." PCIEX_FABRIC 2634 static int 2635 pf_ereport_setup(dev_info_t *dip, uint64_t ena, nvlist_t **ereport, 2636 nvlist_t **detector, errorq_elem_t **eqep) 2637 { 2638 struct i_ddi_fmhdl *fmhdl = DEVI(dip)->devi_fmhdl; 2639 char device_path[MAXPATHLEN]; 2640 nv_alloc_t *nva; 2641 2642 *eqep = errorq_reserve(fmhdl->fh_errorq); 2643 if (*eqep == NULL) { 2644 atomic_inc_64(&fmhdl->fh_kstat.fek_erpt_dropped.value.ui64); 2645 return (DDI_FAILURE); 2646 } 2647 2648 *ereport = errorq_elem_nvl(fmhdl->fh_errorq, *eqep); 2649 nva = errorq_elem_nva(fmhdl->fh_errorq, *eqep); 2650 2651 ASSERT(*ereport); 2652 ASSERT(nva); 2653 2654 /* 2655 * Use the dev_path/devid for this device instance. 2656 */ 2657 *detector = fm_nvlist_create(nva); 2658 if (dip == ddi_root_node()) { 2659 device_path[0] = '/'; 2660 device_path[1] = '\0'; 2661 } else { 2662 (void) ddi_pathname(dip, device_path); 2663 } 2664 2665 fm_fmri_dev_set(*detector, FM_DEV_SCHEME_VERSION, NULL, 2666 device_path, NULL, NULL); 2667 2668 if (ena == 0) 2669 ena = fm_ena_generate(0, FM_ENA_FMT1); 2670 2671 fm_ereport_set(*ereport, 0, PCIE_EREPORT, ena, *detector, NULL); 2672 2673 return (DDI_SUCCESS); 2674 } 2675 2676 /* ARGSUSED */ 2677 static void 2678 pf_ereport_post(dev_info_t *dip, nvlist_t **ereport, nvlist_t **detector, 2679 errorq_elem_t **eqep) 2680 { 2681 struct i_ddi_fmhdl *fmhdl = DEVI(dip)->devi_fmhdl; 2682 2683 errorq_commit(fmhdl->fh_errorq, *eqep, ERRORQ_ASYNC); 2684 } 2685 2686 static void 2687 pf_send_ereport(ddi_fm_error_t *derr, pf_impl_t *impl) 2688 { 2689 nvlist_t *ereport; 2690 nvlist_t *detector; 2691 errorq_elem_t *eqep; 2692 pcie_bus_t *bus_p; 2693 pf_data_t *pfd_p; 2694 uint32_t total = impl->pf_total; 2695 2696 /* 2697 * Ereports need to be sent in a top down fashion. The fabric translator 2698 * expects the ereports from the Root first. This is needed to tell if 2699 * the system contains a PCIe complaint RC/RP. 2700 */ 2701 for (pfd_p = impl->pf_dq_head_p; pfd_p; pfd_p = pfd_p->pe_next) { 2702 bus_p = PCIE_PFD2BUS(pfd_p); 2703 pfd_p->pe_valid = B_FALSE; 2704 2705 if (derr->fme_flag != DDI_FM_ERR_UNEXPECTED || 2706 !DDI_FM_EREPORT_CAP(ddi_fm_capable(PCIE_PFD2DIP(pfd_p)))) 2707 continue; 2708 2709 if (pf_ereport_setup(PCIE_BUS2DIP(bus_p), derr->fme_ena, 2710 &ereport, &detector, &eqep) != DDI_SUCCESS) 2711 continue; 2712 2713 if (PFD_IS_RC(pfd_p)) { 2714 fm_payload_set(ereport, 2715 "scan_bdf", DATA_TYPE_UINT16, 2716 PCIE_ROOT_FAULT(pfd_p)->scan_bdf, 2717 "scan_addr", DATA_TYPE_UINT64, 2718 PCIE_ROOT_FAULT(pfd_p)->scan_addr, 2719 "intr_src", DATA_TYPE_UINT16, 2720 PCIE_ROOT_EH_SRC(pfd_p)->intr_type, 2721 NULL); 2722 goto generic; 2723 } 2724 2725 /* Generic PCI device information */ 2726 fm_payload_set(ereport, 2727 "bdf", DATA_TYPE_UINT16, bus_p->bus_bdf, 2728 "device_id", DATA_TYPE_UINT16, 2729 (bus_p->bus_dev_ven_id >> 16), 2730 "vendor_id", DATA_TYPE_UINT16, 2731 (bus_p->bus_dev_ven_id & 0xFFFF), 2732 "rev_id", DATA_TYPE_UINT8, bus_p->bus_rev_id, 2733 "dev_type", DATA_TYPE_UINT16, bus_p->bus_dev_type, 2734 "pcie_off", DATA_TYPE_UINT16, bus_p->bus_pcie_off, 2735 "pcix_off", DATA_TYPE_UINT16, bus_p->bus_pcix_off, 2736 "aer_off", DATA_TYPE_UINT16, bus_p->bus_aer_off, 2737 "ecc_ver", DATA_TYPE_UINT16, bus_p->bus_ecc_ver, 2738 NULL); 2739 2740 /* PCI registers */ 2741 fm_payload_set(ereport, 2742 "pci_status", DATA_TYPE_UINT16, 2743 PCI_ERR_REG(pfd_p)->pci_err_status, 2744 "pci_command", DATA_TYPE_UINT16, 2745 PCI_ERR_REG(pfd_p)->pci_cfg_comm, 2746 NULL); 2747 2748 /* PCI bridge registers */ 2749 if (PCIE_IS_BDG(bus_p)) { 2750 fm_payload_set(ereport, 2751 "pci_bdg_sec_status", DATA_TYPE_UINT16, 2752 PCI_BDG_ERR_REG(pfd_p)->pci_bdg_sec_stat, 2753 "pci_bdg_ctrl", DATA_TYPE_UINT16, 2754 PCI_BDG_ERR_REG(pfd_p)->pci_bdg_ctrl, 2755 NULL); 2756 } 2757 2758 /* PCIx registers */ 2759 if (PCIE_IS_PCIX(bus_p) && !PCIE_IS_BDG(bus_p)) { 2760 fm_payload_set(ereport, 2761 "pcix_status", DATA_TYPE_UINT32, 2762 PCIX_ERR_REG(pfd_p)->pcix_status, 2763 "pcix_command", DATA_TYPE_UINT16, 2764 PCIX_ERR_REG(pfd_p)->pcix_command, 2765 NULL); 2766 } 2767 2768 /* PCIx ECC Registers */ 2769 if (PCIX_ECC_VERSION_CHECK(bus_p)) { 2770 pf_pcix_ecc_regs_t *ecc_bdg_reg; 2771 pf_pcix_ecc_regs_t *ecc_reg; 2772 2773 if (PCIE_IS_BDG(bus_p)) 2774 ecc_bdg_reg = PCIX_BDG_ECC_REG(pfd_p, 0); 2775 ecc_reg = PCIX_ECC_REG(pfd_p); 2776 fm_payload_set(ereport, 2777 "pcix_ecc_control_0", DATA_TYPE_UINT16, 2778 PCIE_IS_BDG(bus_p) ? 2779 (ecc_bdg_reg->pcix_ecc_ctlstat >> 16) : 2780 (ecc_reg->pcix_ecc_ctlstat >> 16), 2781 "pcix_ecc_status_0", DATA_TYPE_UINT16, 2782 PCIE_IS_BDG(bus_p) ? 2783 (ecc_bdg_reg->pcix_ecc_ctlstat & 0xFFFF) : 2784 (ecc_reg->pcix_ecc_ctlstat & 0xFFFF), 2785 "pcix_ecc_fst_addr_0", DATA_TYPE_UINT32, 2786 PCIE_IS_BDG(bus_p) ? 2787 ecc_bdg_reg->pcix_ecc_fstaddr : 2788 ecc_reg->pcix_ecc_fstaddr, 2789 "pcix_ecc_sec_addr_0", DATA_TYPE_UINT32, 2790 PCIE_IS_BDG(bus_p) ? 2791 ecc_bdg_reg->pcix_ecc_secaddr : 2792 ecc_reg->pcix_ecc_secaddr, 2793 "pcix_ecc_attr_0", DATA_TYPE_UINT32, 2794 PCIE_IS_BDG(bus_p) ? 2795 ecc_bdg_reg->pcix_ecc_attr : 2796 ecc_reg->pcix_ecc_attr, 2797 NULL); 2798 } 2799 2800 /* PCIx ECC Bridge Registers */ 2801 if (PCIX_ECC_VERSION_CHECK(bus_p) && PCIE_IS_BDG(bus_p)) { 2802 pf_pcix_ecc_regs_t *ecc_bdg_reg; 2803 2804 ecc_bdg_reg = PCIX_BDG_ECC_REG(pfd_p, 1); 2805 fm_payload_set(ereport, 2806 "pcix_ecc_control_1", DATA_TYPE_UINT16, 2807 (ecc_bdg_reg->pcix_ecc_ctlstat >> 16), 2808 "pcix_ecc_status_1", DATA_TYPE_UINT16, 2809 (ecc_bdg_reg->pcix_ecc_ctlstat & 0xFFFF), 2810 "pcix_ecc_fst_addr_1", DATA_TYPE_UINT32, 2811 ecc_bdg_reg->pcix_ecc_fstaddr, 2812 "pcix_ecc_sec_addr_1", DATA_TYPE_UINT32, 2813 ecc_bdg_reg->pcix_ecc_secaddr, 2814 "pcix_ecc_attr_1", DATA_TYPE_UINT32, 2815 ecc_bdg_reg->pcix_ecc_attr, 2816 NULL); 2817 } 2818 2819 /* PCIx Bridge */ 2820 if (PCIE_IS_PCIX(bus_p) && PCIE_IS_BDG(bus_p)) { 2821 fm_payload_set(ereport, 2822 "pcix_bdg_status", DATA_TYPE_UINT32, 2823 PCIX_BDG_ERR_REG(pfd_p)->pcix_bdg_stat, 2824 "pcix_bdg_sec_status", DATA_TYPE_UINT16, 2825 PCIX_BDG_ERR_REG(pfd_p)->pcix_bdg_sec_stat, 2826 NULL); 2827 } 2828 2829 /* PCIe registers */ 2830 if (PCIE_IS_PCIE(bus_p)) { 2831 fm_payload_set(ereport, 2832 "pcie_status", DATA_TYPE_UINT16, 2833 PCIE_ERR_REG(pfd_p)->pcie_err_status, 2834 "pcie_command", DATA_TYPE_UINT16, 2835 PCIE_ERR_REG(pfd_p)->pcie_err_ctl, 2836 "pcie_dev_cap", DATA_TYPE_UINT32, 2837 PCIE_ERR_REG(pfd_p)->pcie_dev_cap, 2838 NULL); 2839 } 2840 2841 /* PCIe AER registers */ 2842 if (PCIE_HAS_AER(bus_p)) { 2843 fm_payload_set(ereport, 2844 "pcie_adv_ctl", DATA_TYPE_UINT32, 2845 PCIE_ADV_REG(pfd_p)->pcie_adv_ctl, 2846 "pcie_ue_status", DATA_TYPE_UINT32, 2847 PCIE_ADV_REG(pfd_p)->pcie_ue_status, 2848 "pcie_ue_mask", DATA_TYPE_UINT32, 2849 PCIE_ADV_REG(pfd_p)->pcie_ue_mask, 2850 "pcie_ue_sev", DATA_TYPE_UINT32, 2851 PCIE_ADV_REG(pfd_p)->pcie_ue_sev, 2852 "pcie_ue_hdr0", DATA_TYPE_UINT32, 2853 PCIE_ADV_REG(pfd_p)->pcie_ue_hdr[0], 2854 "pcie_ue_hdr1", DATA_TYPE_UINT32, 2855 PCIE_ADV_REG(pfd_p)->pcie_ue_hdr[1], 2856 "pcie_ue_hdr2", DATA_TYPE_UINT32, 2857 PCIE_ADV_REG(pfd_p)->pcie_ue_hdr[2], 2858 "pcie_ue_hdr3", DATA_TYPE_UINT32, 2859 PCIE_ADV_REG(pfd_p)->pcie_ue_hdr[3], 2860 "pcie_ce_status", DATA_TYPE_UINT32, 2861 PCIE_ADV_REG(pfd_p)->pcie_ce_status, 2862 "pcie_ce_mask", DATA_TYPE_UINT32, 2863 PCIE_ADV_REG(pfd_p)->pcie_ce_mask, 2864 NULL); 2865 } 2866 2867 /* PCIe AER decoded header */ 2868 if (HAS_AER_LOGS(pfd_p, PCIE_ADV_REG(pfd_p)->pcie_ue_status)) { 2869 fm_payload_set(ereport, 2870 "pcie_ue_tgt_trans", DATA_TYPE_UINT32, 2871 PCIE_ADV_REG(pfd_p)->pcie_ue_tgt_trans, 2872 "pcie_ue_tgt_addr", DATA_TYPE_UINT64, 2873 PCIE_ADV_REG(pfd_p)->pcie_ue_tgt_addr, 2874 "pcie_ue_tgt_bdf", DATA_TYPE_UINT16, 2875 PCIE_ADV_REG(pfd_p)->pcie_ue_tgt_bdf, 2876 NULL); 2877 /* Clear these values as they no longer valid */ 2878 PCIE_ADV_REG(pfd_p)->pcie_ue_tgt_trans = 0; 2879 PCIE_ADV_REG(pfd_p)->pcie_ue_tgt_addr = 0; 2880 PCIE_ADV_REG(pfd_p)->pcie_ue_tgt_bdf = PCIE_INVALID_BDF; 2881 } 2882 2883 /* PCIe BDG AER registers */ 2884 if (PCIE_IS_PCIE_BDG(bus_p) && PCIE_HAS_AER(bus_p)) { 2885 fm_payload_set(ereport, 2886 "pcie_sue_adv_ctl", DATA_TYPE_UINT32, 2887 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_ctl, 2888 "pcie_sue_status", DATA_TYPE_UINT32, 2889 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_status, 2890 "pcie_sue_mask", DATA_TYPE_UINT32, 2891 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_mask, 2892 "pcie_sue_sev", DATA_TYPE_UINT32, 2893 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_sev, 2894 "pcie_sue_hdr0", DATA_TYPE_UINT32, 2895 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_hdr[0], 2896 "pcie_sue_hdr1", DATA_TYPE_UINT32, 2897 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_hdr[1], 2898 "pcie_sue_hdr2", DATA_TYPE_UINT32, 2899 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_hdr[2], 2900 "pcie_sue_hdr3", DATA_TYPE_UINT32, 2901 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_hdr[3], 2902 NULL); 2903 } 2904 2905 /* PCIe BDG AER decoded header */ 2906 if (PCIE_IS_PCIE_BDG(bus_p) && HAS_SAER_LOGS(pfd_p, 2907 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_status)) { 2908 fm_payload_set(ereport, 2909 "pcie_sue_tgt_trans", DATA_TYPE_UINT32, 2910 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_tgt_trans, 2911 "pcie_sue_tgt_addr", DATA_TYPE_UINT64, 2912 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_tgt_addr, 2913 "pcie_sue_tgt_bdf", DATA_TYPE_UINT16, 2914 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_tgt_bdf, 2915 NULL); 2916 /* Clear these values as they no longer valid */ 2917 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_tgt_trans = 0; 2918 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_tgt_addr = 0; 2919 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_tgt_bdf = 2920 PCIE_INVALID_BDF; 2921 } 2922 2923 /* PCIe RP registers */ 2924 if (PCIE_IS_RP(bus_p)) { 2925 fm_payload_set(ereport, 2926 "pcie_rp_status", DATA_TYPE_UINT32, 2927 PCIE_RP_REG(pfd_p)->pcie_rp_status, 2928 "pcie_rp_control", DATA_TYPE_UINT16, 2929 PCIE_RP_REG(pfd_p)->pcie_rp_ctl, 2930 NULL); 2931 } 2932 2933 /* PCIe RP AER registers */ 2934 if (PCIE_IS_RP(bus_p) && PCIE_HAS_AER(bus_p)) { 2935 fm_payload_set(ereport, 2936 "pcie_adv_rp_status", DATA_TYPE_UINT32, 2937 PCIE_ADV_RP_REG(pfd_p)->pcie_rp_err_status, 2938 "pcie_adv_rp_command", DATA_TYPE_UINT32, 2939 PCIE_ADV_RP_REG(pfd_p)->pcie_rp_err_cmd, 2940 "pcie_adv_rp_ce_src_id", DATA_TYPE_UINT16, 2941 PCIE_ADV_RP_REG(pfd_p)->pcie_rp_ce_src_id, 2942 "pcie_adv_rp_ue_src_id", DATA_TYPE_UINT16, 2943 PCIE_ADV_RP_REG(pfd_p)->pcie_rp_ue_src_id, 2944 NULL); 2945 } 2946 2947 generic: 2948 /* IOV related information */ 2949 if (!PCIE_BDG_IS_UNASSIGNED(PCIE_PFD2BUS(impl->pf_dq_head_p))) { 2950 fm_payload_set(ereport, 2951 "pcie_aff_flags", DATA_TYPE_UINT16, 2952 PFD_AFFECTED_DEV(pfd_p)->pe_affected_flags, 2953 "pcie_aff_bdf", DATA_TYPE_UINT16, 2954 PFD_AFFECTED_DEV(pfd_p)->pe_affected_bdf, 2955 "orig_sev", DATA_TYPE_UINT32, 2956 pfd_p->pe_orig_severity_flags, 2957 NULL); 2958 } 2959 2960 /* Misc ereport information */ 2961 fm_payload_set(ereport, 2962 "remainder", DATA_TYPE_UINT32, --total, 2963 "severity", DATA_TYPE_UINT32, pfd_p->pe_severity_flags, 2964 NULL); 2965 2966 pf_ereport_post(PCIE_BUS2DIP(bus_p), &ereport, &detector, 2967 &eqep); 2968 } 2969 2970 /* Unlock all the devices in the queue */ 2971 for (pfd_p = impl->pf_dq_tail_p; pfd_p; pfd_p = pfd_p->pe_prev) { 2972 if (pfd_p->pe_lock) { 2973 pf_handler_exit(PCIE_PFD2DIP(pfd_p)); 2974 } 2975 } 2976 } 2977 2978 /* 2979 * pf_handler_enter must be called to serial access to each device's pf_data_t. 2980 * Once error handling is finished with the device call pf_handler_exit to allow 2981 * other threads to access it. The same thread may call pf_handler_enter 2982 * several times without any consequences. 2983 * 2984 * The "impl" variable is passed in during scan fabric to double check that 2985 * there is not a recursive algorithm and to ensure only one thread is doing a 2986 * fabric scan at all times. 2987 * 2988 * In some cases "impl" is not available, such as "child lookup" being called 2989 * from outside of scan fabric, just pass in NULL for this variable and this 2990 * extra check will be skipped. 2991 */ 2992 static int 2993 pf_handler_enter(dev_info_t *dip, pf_impl_t *impl) 2994 { 2995 pf_data_t *pfd_p = PCIE_DIP2PFD(dip); 2996 2997 ASSERT(pfd_p); 2998 2999 /* 3000 * Check to see if the lock has already been taken by this 3001 * thread. If so just return and don't take lock again. 3002 */ 3003 if (!pfd_p->pe_lock || !impl) { 3004 i_ddi_fm_handler_enter(dip); 3005 pfd_p->pe_lock = B_TRUE; 3006 return (PF_SCAN_SUCCESS); 3007 } 3008 3009 /* Check to see that this dip is already in the "impl" error queue */ 3010 for (pfd_p = impl->pf_dq_head_p; pfd_p; pfd_p = pfd_p->pe_next) { 3011 if (PCIE_PFD2DIP(pfd_p) == dip) { 3012 return (PF_SCAN_SUCCESS); 3013 } 3014 } 3015 3016 return (PF_SCAN_DEADLOCK); 3017 } 3018 3019 static void 3020 pf_handler_exit(dev_info_t *dip) 3021 { 3022 pf_data_t *pfd_p = PCIE_DIP2PFD(dip); 3023 3024 ASSERT(pfd_p); 3025 3026 ASSERT(pfd_p->pe_lock == B_TRUE); 3027 i_ddi_fm_handler_exit(dip); 3028 pfd_p->pe_lock = B_FALSE; 3029 } 3030 3031 /* 3032 * This function calls the driver's callback function (if it's FMA hardened 3033 * and callback capable). This function relies on the current thread already 3034 * owning the driver's fmhdl lock. 3035 */ 3036 static int 3037 pf_fm_callback(dev_info_t *dip, ddi_fm_error_t *derr) 3038 { 3039 int cb_sts = DDI_FM_OK; 3040 3041 if (DDI_FM_ERRCB_CAP(ddi_fm_capable(dip))) { 3042 dev_info_t *pdip = ddi_get_parent(dip); 3043 struct i_ddi_fmhdl *hdl = DEVI(pdip)->devi_fmhdl; 3044 struct i_ddi_fmtgt *tgt = hdl->fh_tgts; 3045 struct i_ddi_errhdl *errhdl; 3046 while (tgt != NULL) { 3047 if (dip == tgt->ft_dip) { 3048 errhdl = tgt->ft_errhdl; 3049 cb_sts = errhdl->eh_func(dip, derr, 3050 errhdl->eh_impl); 3051 break; 3052 } 3053 tgt = tgt->ft_next; 3054 } 3055 } 3056 return (cb_sts); 3057 } 3058 3059 static void 3060 pf_reset_pfd(pf_data_t *pfd_p) 3061 { 3062 pcie_bus_t *bus_p = PCIE_PFD2BUS(pfd_p); 3063 3064 pfd_p->pe_severity_flags = 0; 3065 pfd_p->pe_orig_severity_flags = 0; 3066 /* pe_lock and pe_valid were reset in pf_send_ereport */ 3067 3068 PFD_AFFECTED_DEV(pfd_p)->pe_affected_flags = 0; 3069 PFD_AFFECTED_DEV(pfd_p)->pe_affected_bdf = PCIE_INVALID_BDF; 3070 3071 if (PCIE_IS_ROOT(bus_p)) { 3072 PCIE_ROOT_FAULT(pfd_p)->scan_bdf = PCIE_INVALID_BDF; 3073 PCIE_ROOT_FAULT(pfd_p)->scan_addr = 0; 3074 PCIE_ROOT_FAULT(pfd_p)->full_scan = B_FALSE; 3075 PCIE_ROOT_EH_SRC(pfd_p)->intr_type = PF_INTR_TYPE_NONE; 3076 PCIE_ROOT_EH_SRC(pfd_p)->intr_data = NULL; 3077 } 3078 3079 if (PCIE_IS_BDG(bus_p)) { 3080 bzero(PCI_BDG_ERR_REG(pfd_p), sizeof (pf_pci_bdg_err_regs_t)); 3081 } 3082 3083 PCI_ERR_REG(pfd_p)->pci_err_status = 0; 3084 PCI_ERR_REG(pfd_p)->pci_cfg_comm = 0; 3085 3086 if (PCIE_IS_PCIE(bus_p)) { 3087 if (PCIE_IS_ROOT(bus_p)) { 3088 bzero(PCIE_RP_REG(pfd_p), 3089 sizeof (pf_pcie_rp_err_regs_t)); 3090 bzero(PCIE_ADV_RP_REG(pfd_p), 3091 sizeof (pf_pcie_adv_rp_err_regs_t)); 3092 PCIE_ADV_RP_REG(pfd_p)->pcie_rp_ce_src_id = 3093 PCIE_INVALID_BDF; 3094 PCIE_ADV_RP_REG(pfd_p)->pcie_rp_ue_src_id = 3095 PCIE_INVALID_BDF; 3096 } else if (PCIE_IS_PCIE_BDG(bus_p)) { 3097 bzero(PCIE_ADV_BDG_REG(pfd_p), 3098 sizeof (pf_pcie_adv_bdg_err_regs_t)); 3099 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_tgt_bdf = 3100 PCIE_INVALID_BDF; 3101 } 3102 3103 if (PCIE_IS_PCIE_BDG(bus_p) && PCIE_IS_PCIX(bus_p)) { 3104 if (PCIX_ECC_VERSION_CHECK(bus_p)) { 3105 bzero(PCIX_BDG_ECC_REG(pfd_p, 0), 3106 sizeof (pf_pcix_ecc_regs_t)); 3107 bzero(PCIX_BDG_ECC_REG(pfd_p, 1), 3108 sizeof (pf_pcix_ecc_regs_t)); 3109 } 3110 PCIX_BDG_ERR_REG(pfd_p)->pcix_bdg_sec_stat = 0; 3111 PCIX_BDG_ERR_REG(pfd_p)->pcix_bdg_stat = 0; 3112 } 3113 3114 PCIE_ADV_REG(pfd_p)->pcie_adv_ctl = 0; 3115 PCIE_ADV_REG(pfd_p)->pcie_ue_status = 0; 3116 PCIE_ADV_REG(pfd_p)->pcie_ue_mask = 0; 3117 PCIE_ADV_REG(pfd_p)->pcie_ue_sev = 0; 3118 PCIE_ADV_HDR(pfd_p, 0) = 0; 3119 PCIE_ADV_HDR(pfd_p, 1) = 0; 3120 PCIE_ADV_HDR(pfd_p, 2) = 0; 3121 PCIE_ADV_HDR(pfd_p, 3) = 0; 3122 PCIE_ADV_REG(pfd_p)->pcie_ce_status = 0; 3123 PCIE_ADV_REG(pfd_p)->pcie_ce_mask = 0; 3124 PCIE_ADV_REG(pfd_p)->pcie_ue_tgt_trans = 0; 3125 PCIE_ADV_REG(pfd_p)->pcie_ue_tgt_addr = 0; 3126 PCIE_ADV_REG(pfd_p)->pcie_ue_tgt_bdf = PCIE_INVALID_BDF; 3127 3128 PCIE_ERR_REG(pfd_p)->pcie_err_status = 0; 3129 PCIE_ERR_REG(pfd_p)->pcie_err_ctl = 0; 3130 PCIE_ERR_REG(pfd_p)->pcie_dev_cap = 0; 3131 3132 } else if (PCIE_IS_PCIX(bus_p)) { 3133 if (PCIE_IS_BDG(bus_p)) { 3134 if (PCIX_ECC_VERSION_CHECK(bus_p)) { 3135 bzero(PCIX_BDG_ECC_REG(pfd_p, 0), 3136 sizeof (pf_pcix_ecc_regs_t)); 3137 bzero(PCIX_BDG_ECC_REG(pfd_p, 1), 3138 sizeof (pf_pcix_ecc_regs_t)); 3139 } 3140 PCIX_BDG_ERR_REG(pfd_p)->pcix_bdg_sec_stat = 0; 3141 PCIX_BDG_ERR_REG(pfd_p)->pcix_bdg_stat = 0; 3142 } else { 3143 if (PCIX_ECC_VERSION_CHECK(bus_p)) { 3144 bzero(PCIX_ECC_REG(pfd_p), 3145 sizeof (pf_pcix_ecc_regs_t)); 3146 } 3147 PCIX_ERR_REG(pfd_p)->pcix_command = 0; 3148 PCIX_ERR_REG(pfd_p)->pcix_status = 0; 3149 } 3150 } 3151 3152 pfd_p->pe_prev = NULL; 3153 pfd_p->pe_next = NULL; 3154 pfd_p->pe_rber_fatal = B_FALSE; 3155 } 3156 3157 pcie_bus_t * 3158 pf_find_busp_by_bdf(pf_impl_t *impl, pcie_req_id_t bdf) 3159 { 3160 pcie_bus_t *temp_bus_p; 3161 pf_data_t *temp_pfd_p; 3162 3163 for (temp_pfd_p = impl->pf_dq_head_p; 3164 temp_pfd_p; 3165 temp_pfd_p = temp_pfd_p->pe_next) { 3166 temp_bus_p = PCIE_PFD2BUS(temp_pfd_p); 3167 3168 if (bdf == temp_bus_p->bus_bdf) { 3169 return (temp_bus_p); 3170 } 3171 } 3172 3173 return (NULL); 3174 } 3175 3176 pcie_bus_t * 3177 pf_find_busp_by_addr(pf_impl_t *impl, uint64_t addr) 3178 { 3179 pcie_bus_t *temp_bus_p; 3180 pf_data_t *temp_pfd_p; 3181 3182 for (temp_pfd_p = impl->pf_dq_head_p; 3183 temp_pfd_p; 3184 temp_pfd_p = temp_pfd_p->pe_next) { 3185 temp_bus_p = PCIE_PFD2BUS(temp_pfd_p); 3186 3187 if (pf_in_assigned_addr(temp_bus_p, addr)) { 3188 return (temp_bus_p); 3189 } 3190 } 3191 3192 return (NULL); 3193 } 3194 3195 pcie_bus_t * 3196 pf_find_busp_by_aer(pf_impl_t *impl, pf_data_t *pfd_p) 3197 { 3198 pf_pcie_adv_err_regs_t *reg_p = PCIE_ADV_REG(pfd_p); 3199 pcie_bus_t *temp_bus_p = NULL; 3200 pcie_req_id_t bdf; 3201 uint64_t addr; 3202 pcie_tlp_hdr_t *tlp_hdr = (pcie_tlp_hdr_t *)reg_p->pcie_ue_hdr; 3203 uint32_t trans_type = reg_p->pcie_ue_tgt_trans; 3204 3205 if ((tlp_hdr->type == PCIE_TLP_TYPE_CPL) || 3206 (tlp_hdr->type == PCIE_TLP_TYPE_CPLLK)) { 3207 pcie_cpl_t *cpl_tlp = (pcie_cpl_t *)®_p->pcie_ue_hdr[1]; 3208 3209 bdf = (cpl_tlp->rid > cpl_tlp->cid) ? cpl_tlp->rid : 3210 cpl_tlp->cid; 3211 temp_bus_p = pf_find_busp_by_bdf(impl, bdf); 3212 } else if (trans_type == PF_ADDR_PIO) { 3213 addr = reg_p->pcie_ue_tgt_addr; 3214 temp_bus_p = pf_find_busp_by_addr(impl, addr); 3215 } else { 3216 /* PF_ADDR_DMA type */ 3217 bdf = reg_p->pcie_ue_tgt_bdf; 3218 temp_bus_p = pf_find_busp_by_bdf(impl, bdf); 3219 } 3220 3221 return (temp_bus_p); 3222 } 3223 3224 pcie_bus_t * 3225 pf_find_busp_by_saer(pf_impl_t *impl, pf_data_t *pfd_p) 3226 { 3227 pf_pcie_adv_bdg_err_regs_t *reg_p = PCIE_ADV_BDG_REG(pfd_p); 3228 pcie_bus_t *temp_bus_p = NULL; 3229 pcie_req_id_t bdf; 3230 uint64_t addr; 3231 3232 addr = reg_p->pcie_sue_tgt_addr; 3233 bdf = reg_p->pcie_sue_tgt_bdf; 3234 3235 if (addr != 0) { 3236 temp_bus_p = pf_find_busp_by_addr(impl, addr); 3237 } else if (PCIE_CHECK_VALID_BDF(bdf)) { 3238 temp_bus_p = pf_find_busp_by_bdf(impl, bdf); 3239 } 3240 3241 return (temp_bus_p); 3242 } 3243