1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved. 24 * Copyright (c) 2017, Joyent, Inc. 25 */ 26 27 #include <sys/sysmacros.h> 28 #include <sys/types.h> 29 #include <sys/kmem.h> 30 #include <sys/modctl.h> 31 #include <sys/ddi.h> 32 #include <sys/sunddi.h> 33 #include <sys/sunndi.h> 34 #include <sys/fm/protocol.h> 35 #include <sys/fm/util.h> 36 #include <sys/promif.h> 37 #include <sys/disp.h> 38 #include <sys/stat.h> 39 #include <sys/file.h> 40 #include <sys/pci_cap.h> 41 #include <sys/pci_impl.h> 42 #include <sys/pcie_impl.h> 43 #include <sys/hotplug/pci/pcie_hp.h> 44 #include <sys/hotplug/pci/pciehpc.h> 45 #include <sys/hotplug/pci/pcishpc.h> 46 #include <sys/hotplug/pci/pcicfg.h> 47 #include <sys/pci_cfgacc.h> 48 49 /* Local functions prototypes */ 50 static void pcie_init_pfd(dev_info_t *); 51 static void pcie_fini_pfd(dev_info_t *); 52 53 #if defined(__i386) || defined(__amd64) 54 static void pcie_check_io_mem_range(ddi_acc_handle_t, boolean_t *, boolean_t *); 55 #endif /* defined(__i386) || defined(__amd64) */ 56 57 #ifdef DEBUG 58 uint_t pcie_debug_flags = 0; 59 static void pcie_print_bus(pcie_bus_t *bus_p); 60 void pcie_dbg(char *fmt, ...); 61 #endif /* DEBUG */ 62 63 /* Variable to control default PCI-Express config settings */ 64 ushort_t pcie_command_default = 65 PCI_COMM_SERR_ENABLE | 66 PCI_COMM_WAIT_CYC_ENAB | 67 PCI_COMM_PARITY_DETECT | 68 PCI_COMM_ME | 69 PCI_COMM_MAE | 70 PCI_COMM_IO; 71 72 /* xxx_fw are bits that are controlled by FW and should not be modified */ 73 ushort_t pcie_command_default_fw = 74 PCI_COMM_SPEC_CYC | 75 PCI_COMM_MEMWR_INVAL | 76 PCI_COMM_PALETTE_SNOOP | 77 PCI_COMM_WAIT_CYC_ENAB | 78 0xF800; /* Reserved Bits */ 79 80 ushort_t pcie_bdg_command_default_fw = 81 PCI_BCNF_BCNTRL_ISA_ENABLE | 82 PCI_BCNF_BCNTRL_VGA_ENABLE | 83 0xF000; /* Reserved Bits */ 84 85 /* PCI-Express Base error defaults */ 86 ushort_t pcie_base_err_default = 87 PCIE_DEVCTL_CE_REPORTING_EN | 88 PCIE_DEVCTL_NFE_REPORTING_EN | 89 PCIE_DEVCTL_FE_REPORTING_EN | 90 PCIE_DEVCTL_UR_REPORTING_EN; 91 92 /* PCI-Express Device Control Register */ 93 uint16_t pcie_devctl_default = PCIE_DEVCTL_RO_EN | 94 PCIE_DEVCTL_MAX_READ_REQ_512; 95 96 /* PCI-Express AER Root Control Register */ 97 #define PCIE_ROOT_SYS_ERR (PCIE_ROOTCTL_SYS_ERR_ON_CE_EN | \ 98 PCIE_ROOTCTL_SYS_ERR_ON_NFE_EN | \ 99 PCIE_ROOTCTL_SYS_ERR_ON_FE_EN) 100 101 ushort_t pcie_root_ctrl_default = 102 PCIE_ROOTCTL_SYS_ERR_ON_CE_EN | 103 PCIE_ROOTCTL_SYS_ERR_ON_NFE_EN | 104 PCIE_ROOTCTL_SYS_ERR_ON_FE_EN; 105 106 /* PCI-Express Root Error Command Register */ 107 ushort_t pcie_root_error_cmd_default = 108 PCIE_AER_RE_CMD_CE_REP_EN | 109 PCIE_AER_RE_CMD_NFE_REP_EN | 110 PCIE_AER_RE_CMD_FE_REP_EN; 111 112 /* ECRC settings in the PCIe AER Control Register */ 113 uint32_t pcie_ecrc_value = 114 PCIE_AER_CTL_ECRC_GEN_ENA | 115 PCIE_AER_CTL_ECRC_CHECK_ENA; 116 117 /* 118 * If a particular platform wants to disable certain errors such as UR/MA, 119 * instead of using #defines have the platform's PCIe Root Complex driver set 120 * these masks using the pcie_get_XXX_mask and pcie_set_XXX_mask functions. For 121 * x86 the closest thing to a PCIe root complex driver is NPE. For SPARC the 122 * closest PCIe root complex driver is PX. 123 * 124 * pcie_serr_disable_flag : disable SERR only (in RCR and command reg) x86 125 * systems may want to disable SERR in general. For root ports, enabling SERR 126 * causes NMIs which are not handled and results in a watchdog timeout error. 127 */ 128 uint32_t pcie_aer_uce_mask = 0; /* AER UE Mask */ 129 uint32_t pcie_aer_ce_mask = 0; /* AER CE Mask */ 130 uint32_t pcie_aer_suce_mask = 0; /* AER Secondary UE Mask */ 131 uint32_t pcie_serr_disable_flag = 0; /* Disable SERR */ 132 133 /* Default severities needed for eversholt. Error handling doesn't care */ 134 uint32_t pcie_aer_uce_severity = PCIE_AER_UCE_MTLP | PCIE_AER_UCE_RO | \ 135 PCIE_AER_UCE_FCP | PCIE_AER_UCE_SD | PCIE_AER_UCE_DLP | \ 136 PCIE_AER_UCE_TRAINING; 137 uint32_t pcie_aer_suce_severity = PCIE_AER_SUCE_SERR_ASSERT | \ 138 PCIE_AER_SUCE_UC_ADDR_ERR | PCIE_AER_SUCE_UC_ATTR_ERR | \ 139 PCIE_AER_SUCE_USC_MSG_DATA_ERR; 140 141 int pcie_max_mps = PCIE_DEVCTL_MAX_PAYLOAD_4096 >> 5; 142 int pcie_disable_ari = 0; 143 144 static void pcie_scan_mps(dev_info_t *rc_dip, dev_info_t *dip, 145 int *max_supported); 146 static int pcie_get_max_supported(dev_info_t *dip, void *arg); 147 static int pcie_map_phys(dev_info_t *dip, pci_regspec_t *phys_spec, 148 caddr_t *addrp, ddi_acc_handle_t *handlep); 149 static void pcie_unmap_phys(ddi_acc_handle_t *handlep, pci_regspec_t *ph); 150 151 dev_info_t *pcie_get_rc_dip(dev_info_t *dip); 152 153 /* 154 * modload support 155 */ 156 157 static struct modlmisc modlmisc = { 158 &mod_miscops, /* Type of module */ 159 "PCI Express Framework Module" 160 }; 161 162 static struct modlinkage modlinkage = { 163 MODREV_1, 164 (void *)&modlmisc, 165 NULL 166 }; 167 168 /* 169 * Global Variables needed for a non-atomic version of ddi_fm_ereport_post. 170 * Currently used to send the pci.fabric ereports whose payload depends on the 171 * type of PCI device it is being sent for. 172 */ 173 char *pcie_nv_buf; 174 nv_alloc_t *pcie_nvap; 175 nvlist_t *pcie_nvl; 176 177 int 178 _init(void) 179 { 180 int rval; 181 182 pcie_nv_buf = kmem_alloc(ERPT_DATA_SZ, KM_SLEEP); 183 pcie_nvap = fm_nva_xcreate(pcie_nv_buf, ERPT_DATA_SZ); 184 pcie_nvl = fm_nvlist_create(pcie_nvap); 185 186 if ((rval = mod_install(&modlinkage)) != 0) { 187 fm_nvlist_destroy(pcie_nvl, FM_NVA_RETAIN); 188 fm_nva_xdestroy(pcie_nvap); 189 kmem_free(pcie_nv_buf, ERPT_DATA_SZ); 190 } 191 return (rval); 192 } 193 194 int 195 _fini() 196 { 197 int rval; 198 199 if ((rval = mod_remove(&modlinkage)) == 0) { 200 fm_nvlist_destroy(pcie_nvl, FM_NVA_RETAIN); 201 fm_nva_xdestroy(pcie_nvap); 202 kmem_free(pcie_nv_buf, ERPT_DATA_SZ); 203 } 204 return (rval); 205 } 206 207 int 208 _info(struct modinfo *modinfop) 209 { 210 return (mod_info(&modlinkage, modinfop)); 211 } 212 213 /* ARGSUSED */ 214 int 215 pcie_init(dev_info_t *dip, caddr_t arg) 216 { 217 int ret = DDI_SUCCESS; 218 219 /* 220 * Create a "devctl" minor node to support DEVCTL_DEVICE_* 221 * and DEVCTL_BUS_* ioctls to this bus. 222 */ 223 if ((ret = ddi_create_minor_node(dip, "devctl", S_IFCHR, 224 PCI_MINOR_NUM(ddi_get_instance(dip), PCI_DEVCTL_MINOR), 225 DDI_NT_NEXUS, 0)) != DDI_SUCCESS) { 226 PCIE_DBG("Failed to create devctl minor node for %s%d\n", 227 ddi_driver_name(dip), ddi_get_instance(dip)); 228 229 return (ret); 230 } 231 232 if ((ret = pcie_hp_init(dip, arg)) != DDI_SUCCESS) { 233 /* 234 * On some x86 platforms, we observed unexpected hotplug 235 * initialization failures in recent years. The known cause 236 * is a hardware issue: while the problem PCI bridges have 237 * the Hotplug Capable registers set, the machine actually 238 * does not implement the expected ACPI object. 239 * 240 * We don't want to stop PCI driver attach and system boot 241 * just because of this hotplug initialization failure. 242 * Continue with a debug message printed. 243 */ 244 PCIE_DBG("%s%d: Failed setting hotplug framework\n", 245 ddi_driver_name(dip), ddi_get_instance(dip)); 246 247 #if defined(__sparc) 248 ddi_remove_minor_node(dip, "devctl"); 249 250 return (ret); 251 #endif /* defined(__sparc) */ 252 } 253 254 return (DDI_SUCCESS); 255 } 256 257 /* ARGSUSED */ 258 int 259 pcie_uninit(dev_info_t *dip) 260 { 261 int ret = DDI_SUCCESS; 262 263 if (pcie_ari_is_enabled(dip) == PCIE_ARI_FORW_ENABLED) 264 (void) pcie_ari_disable(dip); 265 266 if ((ret = pcie_hp_uninit(dip)) != DDI_SUCCESS) { 267 PCIE_DBG("Failed to uninitialize hotplug for %s%d\n", 268 ddi_driver_name(dip), ddi_get_instance(dip)); 269 270 return (ret); 271 } 272 273 ddi_remove_minor_node(dip, "devctl"); 274 275 return (ret); 276 } 277 278 /* 279 * PCIe module interface for enabling hotplug interrupt. 280 * 281 * It should be called after pcie_init() is done and bus driver's 282 * interrupt handlers have being attached. 283 */ 284 int 285 pcie_hpintr_enable(dev_info_t *dip) 286 { 287 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 288 pcie_hp_ctrl_t *ctrl_p = PCIE_GET_HP_CTRL(dip); 289 290 if (PCIE_IS_PCIE_HOTPLUG_ENABLED(bus_p)) { 291 (void) (ctrl_p->hc_ops.enable_hpc_intr)(ctrl_p); 292 } else if (PCIE_IS_PCI_HOTPLUG_ENABLED(bus_p)) { 293 (void) pcishpc_enable_irqs(ctrl_p); 294 } 295 return (DDI_SUCCESS); 296 } 297 298 /* 299 * PCIe module interface for disabling hotplug interrupt. 300 * 301 * It should be called before pcie_uninit() is called and bus driver's 302 * interrupt handlers is dettached. 303 */ 304 int 305 pcie_hpintr_disable(dev_info_t *dip) 306 { 307 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 308 pcie_hp_ctrl_t *ctrl_p = PCIE_GET_HP_CTRL(dip); 309 310 if (PCIE_IS_PCIE_HOTPLUG_ENABLED(bus_p)) { 311 (void) (ctrl_p->hc_ops.disable_hpc_intr)(ctrl_p); 312 } else if (PCIE_IS_PCI_HOTPLUG_ENABLED(bus_p)) { 313 (void) pcishpc_disable_irqs(ctrl_p); 314 } 315 return (DDI_SUCCESS); 316 } 317 318 /* ARGSUSED */ 319 int 320 pcie_intr(dev_info_t *dip) 321 { 322 return (pcie_hp_intr(dip)); 323 } 324 325 /* ARGSUSED */ 326 int 327 pcie_open(dev_info_t *dip, dev_t *devp, int flags, int otyp, cred_t *credp) 328 { 329 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 330 331 /* 332 * Make sure the open is for the right file type. 333 */ 334 if (otyp != OTYP_CHR) 335 return (EINVAL); 336 337 /* 338 * Handle the open by tracking the device state. 339 */ 340 if ((bus_p->bus_soft_state == PCI_SOFT_STATE_OPEN_EXCL) || 341 ((flags & FEXCL) && 342 (bus_p->bus_soft_state != PCI_SOFT_STATE_CLOSED))) { 343 return (EBUSY); 344 } 345 346 if (flags & FEXCL) 347 bus_p->bus_soft_state = PCI_SOFT_STATE_OPEN_EXCL; 348 else 349 bus_p->bus_soft_state = PCI_SOFT_STATE_OPEN; 350 351 return (0); 352 } 353 354 /* ARGSUSED */ 355 int 356 pcie_close(dev_info_t *dip, dev_t dev, int flags, int otyp, cred_t *credp) 357 { 358 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 359 360 if (otyp != OTYP_CHR) 361 return (EINVAL); 362 363 bus_p->bus_soft_state = PCI_SOFT_STATE_CLOSED; 364 365 return (0); 366 } 367 368 /* ARGSUSED */ 369 int 370 pcie_ioctl(dev_info_t *dip, dev_t dev, int cmd, intptr_t arg, int mode, 371 cred_t *credp, int *rvalp) 372 { 373 struct devctl_iocdata *dcp; 374 uint_t bus_state; 375 int rv = DDI_SUCCESS; 376 377 /* 378 * We can use the generic implementation for devctl ioctl 379 */ 380 switch (cmd) { 381 case DEVCTL_DEVICE_GETSTATE: 382 case DEVCTL_DEVICE_ONLINE: 383 case DEVCTL_DEVICE_OFFLINE: 384 case DEVCTL_BUS_GETSTATE: 385 return (ndi_devctl_ioctl(dip, cmd, arg, mode, 0)); 386 default: 387 break; 388 } 389 390 /* 391 * read devctl ioctl data 392 */ 393 if (ndi_dc_allochdl((void *)arg, &dcp) != NDI_SUCCESS) 394 return (EFAULT); 395 396 switch (cmd) { 397 case DEVCTL_BUS_QUIESCE: 398 if (ndi_get_bus_state(dip, &bus_state) == NDI_SUCCESS) 399 if (bus_state == BUS_QUIESCED) 400 break; 401 (void) ndi_set_bus_state(dip, BUS_QUIESCED); 402 break; 403 case DEVCTL_BUS_UNQUIESCE: 404 if (ndi_get_bus_state(dip, &bus_state) == NDI_SUCCESS) 405 if (bus_state == BUS_ACTIVE) 406 break; 407 (void) ndi_set_bus_state(dip, BUS_ACTIVE); 408 break; 409 case DEVCTL_BUS_RESET: 410 case DEVCTL_BUS_RESETALL: 411 case DEVCTL_DEVICE_RESET: 412 rv = ENOTSUP; 413 break; 414 default: 415 rv = ENOTTY; 416 } 417 418 ndi_dc_freehdl(dcp); 419 return (rv); 420 } 421 422 /* ARGSUSED */ 423 int 424 pcie_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op, 425 int flags, char *name, caddr_t valuep, int *lengthp) 426 { 427 if (dev == DDI_DEV_T_ANY) 428 goto skip; 429 430 if (PCIE_IS_HOTPLUG_CAPABLE(dip) && 431 strcmp(name, "pci-occupant") == 0) { 432 int pci_dev = PCI_MINOR_NUM_TO_PCI_DEVNUM(getminor(dev)); 433 434 pcie_hp_create_occupant_props(dip, dev, pci_dev); 435 } 436 437 skip: 438 return (ddi_prop_op(dev, dip, prop_op, flags, name, valuep, lengthp)); 439 } 440 441 int 442 pcie_init_cfghdl(dev_info_t *cdip) 443 { 444 pcie_bus_t *bus_p; 445 ddi_acc_handle_t eh = NULL; 446 447 bus_p = PCIE_DIP2BUS(cdip); 448 if (bus_p == NULL) 449 return (DDI_FAILURE); 450 451 /* Create an config access special to error handling */ 452 if (pci_config_setup(cdip, &eh) != DDI_SUCCESS) { 453 cmn_err(CE_WARN, "Cannot setup config access" 454 " for BDF 0x%x\n", bus_p->bus_bdf); 455 return (DDI_FAILURE); 456 } 457 458 bus_p->bus_cfg_hdl = eh; 459 return (DDI_SUCCESS); 460 } 461 462 void 463 pcie_fini_cfghdl(dev_info_t *cdip) 464 { 465 pcie_bus_t *bus_p = PCIE_DIP2BUS(cdip); 466 467 pci_config_teardown(&bus_p->bus_cfg_hdl); 468 } 469 470 void 471 pcie_determine_serial(dev_info_t *dip) 472 { 473 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 474 ddi_acc_handle_t h; 475 uint16_t cap; 476 uchar_t serial[8]; 477 uint32_t low, high; 478 479 if (!PCIE_IS_PCIE(bus_p)) 480 return; 481 482 h = bus_p->bus_cfg_hdl; 483 484 if ((PCI_CAP_LOCATE(h, PCI_CAP_XCFG_SPC(PCIE_EXT_CAP_ID_SER), &cap)) == 485 DDI_FAILURE) 486 return; 487 488 high = PCI_XCAP_GET32(h, 0, cap, PCIE_SER_SID_UPPER_DW); 489 low = PCI_XCAP_GET32(h, 0, cap, PCIE_SER_SID_LOWER_DW); 490 491 /* 492 * Here, we're trying to figure out if we had an invalid PCIe read. From 493 * looking at the contents of the value, it can be hard to tell the 494 * difference between a value that has all 1s correctly versus if we had 495 * an error. In this case, we only assume it's invalid if both register 496 * reads are invalid. We also only use 32-bit reads as we're not sure if 497 * all devices will support these as 64-bit reads, while we know that 498 * they'll support these as 32-bit reads. 499 */ 500 if (high == PCI_EINVAL32 && low == PCI_EINVAL32) 501 return; 502 503 serial[0] = low & 0xff; 504 serial[1] = (low >> 8) & 0xff; 505 serial[2] = (low >> 16) & 0xff; 506 serial[3] = (low >> 24) & 0xff; 507 serial[4] = high & 0xff; 508 serial[5] = (high >> 8) & 0xff; 509 serial[6] = (high >> 16) & 0xff; 510 serial[7] = (high >> 24) & 0xff; 511 512 (void) ndi_prop_update_byte_array(DDI_DEV_T_NONE, dip, "pcie-serial", 513 serial, sizeof (serial)); 514 } 515 516 /* 517 * PCI-Express child device initialization. 518 * This function enables generic pci-express interrupts and error 519 * handling. 520 * 521 * @param pdip root dip (root nexus's dip) 522 * @param cdip child's dip (device's dip) 523 * @return DDI_SUCCESS or DDI_FAILURE 524 */ 525 /* ARGSUSED */ 526 int 527 pcie_initchild(dev_info_t *cdip) 528 { 529 uint16_t tmp16, reg16; 530 pcie_bus_t *bus_p; 531 uint32_t devid, venid; 532 533 bus_p = PCIE_DIP2BUS(cdip); 534 if (bus_p == NULL) { 535 PCIE_DBG("%s: BUS not found.\n", 536 ddi_driver_name(cdip)); 537 538 return (DDI_FAILURE); 539 } 540 541 if (pcie_init_cfghdl(cdip) != DDI_SUCCESS) 542 return (DDI_FAILURE); 543 544 /* 545 * Update pcie_bus_t with real Vendor Id Device Id. 546 * 547 * For assigned devices in IOV environment, the OBP will return 548 * faked device id/vendor id on configration read and for both 549 * properties in root domain. translate_devid() function will 550 * update the properties with real device-id/vendor-id on such 551 * platforms, so that we can utilize the properties here to get 552 * real device-id/vendor-id and overwrite the faked ids. 553 * 554 * For unassigned devices or devices in non-IOV environment, the 555 * operation below won't make a difference. 556 * 557 * The IOV implementation only supports assignment of PCIE 558 * endpoint devices. Devices under pci-pci bridges don't need 559 * operation like this. 560 */ 561 devid = ddi_prop_get_int(DDI_DEV_T_ANY, cdip, DDI_PROP_DONTPASS, 562 "device-id", -1); 563 venid = ddi_prop_get_int(DDI_DEV_T_ANY, cdip, DDI_PROP_DONTPASS, 564 "vendor-id", -1); 565 bus_p->bus_dev_ven_id = (devid << 16) | (venid & 0xffff); 566 567 /* Clear the device's status register */ 568 reg16 = PCIE_GET(16, bus_p, PCI_CONF_STAT); 569 PCIE_PUT(16, bus_p, PCI_CONF_STAT, reg16); 570 571 /* Setup the device's command register */ 572 reg16 = PCIE_GET(16, bus_p, PCI_CONF_COMM); 573 tmp16 = (reg16 & pcie_command_default_fw) | pcie_command_default; 574 575 #if defined(__i386) || defined(__amd64) 576 boolean_t empty_io_range = B_FALSE; 577 boolean_t empty_mem_range = B_FALSE; 578 /* 579 * Check for empty IO and Mem ranges on bridges. If so disable IO/Mem 580 * access as it can cause a hang if enabled. 581 */ 582 pcie_check_io_mem_range(bus_p->bus_cfg_hdl, &empty_io_range, 583 &empty_mem_range); 584 if ((empty_io_range == B_TRUE) && 585 (pcie_command_default & PCI_COMM_IO)) { 586 tmp16 &= ~PCI_COMM_IO; 587 PCIE_DBG("No I/O range found for %s, bdf 0x%x\n", 588 ddi_driver_name(cdip), bus_p->bus_bdf); 589 } 590 if ((empty_mem_range == B_TRUE) && 591 (pcie_command_default & PCI_COMM_MAE)) { 592 tmp16 &= ~PCI_COMM_MAE; 593 PCIE_DBG("No Mem range found for %s, bdf 0x%x\n", 594 ddi_driver_name(cdip), bus_p->bus_bdf); 595 } 596 #endif /* defined(__i386) || defined(__amd64) */ 597 598 if (pcie_serr_disable_flag && PCIE_IS_PCIE(bus_p)) 599 tmp16 &= ~PCI_COMM_SERR_ENABLE; 600 601 PCIE_PUT(16, bus_p, PCI_CONF_COMM, tmp16); 602 PCIE_DBG_CFG(cdip, bus_p, "COMMAND", 16, PCI_CONF_COMM, reg16); 603 604 /* 605 * If the device has a bus control register then program it 606 * based on the settings in the command register. 607 */ 608 if (PCIE_IS_BDG(bus_p)) { 609 /* Clear the device's secondary status register */ 610 reg16 = PCIE_GET(16, bus_p, PCI_BCNF_SEC_STATUS); 611 PCIE_PUT(16, bus_p, PCI_BCNF_SEC_STATUS, reg16); 612 613 /* Setup the device's secondary command register */ 614 reg16 = PCIE_GET(16, bus_p, PCI_BCNF_BCNTRL); 615 tmp16 = (reg16 & pcie_bdg_command_default_fw); 616 617 tmp16 |= PCI_BCNF_BCNTRL_SERR_ENABLE; 618 /* 619 * Workaround for this Nvidia bridge. Don't enable the SERR 620 * enable bit in the bridge control register as it could lead to 621 * bogus NMIs. 622 */ 623 if (bus_p->bus_dev_ven_id == 0x037010DE) 624 tmp16 &= ~PCI_BCNF_BCNTRL_SERR_ENABLE; 625 626 if (pcie_command_default & PCI_COMM_PARITY_DETECT) 627 tmp16 |= PCI_BCNF_BCNTRL_PARITY_ENABLE; 628 629 /* 630 * Enable Master Abort Mode only if URs have not been masked. 631 * For PCI and PCIe-PCI bridges, enabling this bit causes a 632 * Master Aborts/UR to be forwarded as a UR/TA or SERR. If this 633 * bit is masked, posted requests are dropped and non-posted 634 * requests are returned with -1. 635 */ 636 if (pcie_aer_uce_mask & PCIE_AER_UCE_UR) 637 tmp16 &= ~PCI_BCNF_BCNTRL_MAST_AB_MODE; 638 else 639 tmp16 |= PCI_BCNF_BCNTRL_MAST_AB_MODE; 640 PCIE_PUT(16, bus_p, PCI_BCNF_BCNTRL, tmp16); 641 PCIE_DBG_CFG(cdip, bus_p, "SEC CMD", 16, PCI_BCNF_BCNTRL, 642 reg16); 643 } 644 645 if (PCIE_IS_PCIE(bus_p)) { 646 /* Setup PCIe device control register */ 647 reg16 = PCIE_CAP_GET(16, bus_p, PCIE_DEVCTL); 648 /* note: MPS/MRRS are initialized in pcie_initchild_mps() */ 649 tmp16 = (reg16 & (PCIE_DEVCTL_MAX_READ_REQ_MASK | 650 PCIE_DEVCTL_MAX_PAYLOAD_MASK)) | 651 (pcie_devctl_default & ~(PCIE_DEVCTL_MAX_READ_REQ_MASK | 652 PCIE_DEVCTL_MAX_PAYLOAD_MASK)); 653 PCIE_CAP_PUT(16, bus_p, PCIE_DEVCTL, tmp16); 654 PCIE_DBG_CAP(cdip, bus_p, "DEVCTL", 16, PCIE_DEVCTL, reg16); 655 656 /* Enable PCIe errors */ 657 pcie_enable_errors(cdip); 658 659 pcie_determine_serial(cdip); 660 } 661 662 bus_p->bus_ari = B_FALSE; 663 if ((pcie_ari_is_enabled(ddi_get_parent(cdip)) 664 == PCIE_ARI_FORW_ENABLED) && (pcie_ari_device(cdip) 665 == PCIE_ARI_DEVICE)) { 666 bus_p->bus_ari = B_TRUE; 667 } 668 669 if (pcie_initchild_mps(cdip) == DDI_FAILURE) { 670 pcie_fini_cfghdl(cdip); 671 return (DDI_FAILURE); 672 } 673 674 return (DDI_SUCCESS); 675 } 676 677 static void 678 pcie_init_pfd(dev_info_t *dip) 679 { 680 pf_data_t *pfd_p = PCIE_ZALLOC(pf_data_t); 681 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 682 683 PCIE_DIP2PFD(dip) = pfd_p; 684 685 pfd_p->pe_bus_p = bus_p; 686 pfd_p->pe_severity_flags = 0; 687 pfd_p->pe_orig_severity_flags = 0; 688 pfd_p->pe_lock = B_FALSE; 689 pfd_p->pe_valid = B_FALSE; 690 691 /* Allocate the root fault struct for both RC and RP */ 692 if (PCIE_IS_ROOT(bus_p)) { 693 PCIE_ROOT_FAULT(pfd_p) = PCIE_ZALLOC(pf_root_fault_t); 694 PCIE_ROOT_FAULT(pfd_p)->scan_bdf = PCIE_INVALID_BDF; 695 PCIE_ROOT_EH_SRC(pfd_p) = PCIE_ZALLOC(pf_root_eh_src_t); 696 } 697 698 PCI_ERR_REG(pfd_p) = PCIE_ZALLOC(pf_pci_err_regs_t); 699 PFD_AFFECTED_DEV(pfd_p) = PCIE_ZALLOC(pf_affected_dev_t); 700 PFD_AFFECTED_DEV(pfd_p)->pe_affected_bdf = PCIE_INVALID_BDF; 701 702 if (PCIE_IS_BDG(bus_p)) 703 PCI_BDG_ERR_REG(pfd_p) = PCIE_ZALLOC(pf_pci_bdg_err_regs_t); 704 705 if (PCIE_IS_PCIE(bus_p)) { 706 PCIE_ERR_REG(pfd_p) = PCIE_ZALLOC(pf_pcie_err_regs_t); 707 708 if (PCIE_IS_RP(bus_p)) 709 PCIE_RP_REG(pfd_p) = 710 PCIE_ZALLOC(pf_pcie_rp_err_regs_t); 711 712 PCIE_ADV_REG(pfd_p) = PCIE_ZALLOC(pf_pcie_adv_err_regs_t); 713 PCIE_ADV_REG(pfd_p)->pcie_ue_tgt_bdf = PCIE_INVALID_BDF; 714 715 if (PCIE_IS_RP(bus_p)) { 716 PCIE_ADV_RP_REG(pfd_p) = 717 PCIE_ZALLOC(pf_pcie_adv_rp_err_regs_t); 718 PCIE_ADV_RP_REG(pfd_p)->pcie_rp_ce_src_id = 719 PCIE_INVALID_BDF; 720 PCIE_ADV_RP_REG(pfd_p)->pcie_rp_ue_src_id = 721 PCIE_INVALID_BDF; 722 } else if (PCIE_IS_PCIE_BDG(bus_p)) { 723 PCIE_ADV_BDG_REG(pfd_p) = 724 PCIE_ZALLOC(pf_pcie_adv_bdg_err_regs_t); 725 PCIE_ADV_BDG_REG(pfd_p)->pcie_sue_tgt_bdf = 726 PCIE_INVALID_BDF; 727 } 728 729 if (PCIE_IS_PCIE_BDG(bus_p) && PCIE_IS_PCIX(bus_p)) { 730 PCIX_BDG_ERR_REG(pfd_p) = 731 PCIE_ZALLOC(pf_pcix_bdg_err_regs_t); 732 733 if (PCIX_ECC_VERSION_CHECK(bus_p)) { 734 PCIX_BDG_ECC_REG(pfd_p, 0) = 735 PCIE_ZALLOC(pf_pcix_ecc_regs_t); 736 PCIX_BDG_ECC_REG(pfd_p, 1) = 737 PCIE_ZALLOC(pf_pcix_ecc_regs_t); 738 } 739 } 740 } else if (PCIE_IS_PCIX(bus_p)) { 741 if (PCIE_IS_BDG(bus_p)) { 742 PCIX_BDG_ERR_REG(pfd_p) = 743 PCIE_ZALLOC(pf_pcix_bdg_err_regs_t); 744 745 if (PCIX_ECC_VERSION_CHECK(bus_p)) { 746 PCIX_BDG_ECC_REG(pfd_p, 0) = 747 PCIE_ZALLOC(pf_pcix_ecc_regs_t); 748 PCIX_BDG_ECC_REG(pfd_p, 1) = 749 PCIE_ZALLOC(pf_pcix_ecc_regs_t); 750 } 751 } else { 752 PCIX_ERR_REG(pfd_p) = PCIE_ZALLOC(pf_pcix_err_regs_t); 753 754 if (PCIX_ECC_VERSION_CHECK(bus_p)) 755 PCIX_ECC_REG(pfd_p) = 756 PCIE_ZALLOC(pf_pcix_ecc_regs_t); 757 } 758 } 759 } 760 761 static void 762 pcie_fini_pfd(dev_info_t *dip) 763 { 764 pf_data_t *pfd_p = PCIE_DIP2PFD(dip); 765 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 766 767 if (PCIE_IS_PCIE(bus_p)) { 768 if (PCIE_IS_PCIE_BDG(bus_p) && PCIE_IS_PCIX(bus_p)) { 769 if (PCIX_ECC_VERSION_CHECK(bus_p)) { 770 kmem_free(PCIX_BDG_ECC_REG(pfd_p, 0), 771 sizeof (pf_pcix_ecc_regs_t)); 772 kmem_free(PCIX_BDG_ECC_REG(pfd_p, 1), 773 sizeof (pf_pcix_ecc_regs_t)); 774 } 775 776 kmem_free(PCIX_BDG_ERR_REG(pfd_p), 777 sizeof (pf_pcix_bdg_err_regs_t)); 778 } 779 780 if (PCIE_IS_RP(bus_p)) 781 kmem_free(PCIE_ADV_RP_REG(pfd_p), 782 sizeof (pf_pcie_adv_rp_err_regs_t)); 783 else if (PCIE_IS_PCIE_BDG(bus_p)) 784 kmem_free(PCIE_ADV_BDG_REG(pfd_p), 785 sizeof (pf_pcie_adv_bdg_err_regs_t)); 786 787 kmem_free(PCIE_ADV_REG(pfd_p), 788 sizeof (pf_pcie_adv_err_regs_t)); 789 790 if (PCIE_IS_RP(bus_p)) 791 kmem_free(PCIE_RP_REG(pfd_p), 792 sizeof (pf_pcie_rp_err_regs_t)); 793 794 kmem_free(PCIE_ERR_REG(pfd_p), sizeof (pf_pcie_err_regs_t)); 795 } else if (PCIE_IS_PCIX(bus_p)) { 796 if (PCIE_IS_BDG(bus_p)) { 797 if (PCIX_ECC_VERSION_CHECK(bus_p)) { 798 kmem_free(PCIX_BDG_ECC_REG(pfd_p, 0), 799 sizeof (pf_pcix_ecc_regs_t)); 800 kmem_free(PCIX_BDG_ECC_REG(pfd_p, 1), 801 sizeof (pf_pcix_ecc_regs_t)); 802 } 803 804 kmem_free(PCIX_BDG_ERR_REG(pfd_p), 805 sizeof (pf_pcix_bdg_err_regs_t)); 806 } else { 807 if (PCIX_ECC_VERSION_CHECK(bus_p)) 808 kmem_free(PCIX_ECC_REG(pfd_p), 809 sizeof (pf_pcix_ecc_regs_t)); 810 811 kmem_free(PCIX_ERR_REG(pfd_p), 812 sizeof (pf_pcix_err_regs_t)); 813 } 814 } 815 816 if (PCIE_IS_BDG(bus_p)) 817 kmem_free(PCI_BDG_ERR_REG(pfd_p), 818 sizeof (pf_pci_bdg_err_regs_t)); 819 820 kmem_free(PFD_AFFECTED_DEV(pfd_p), sizeof (pf_affected_dev_t)); 821 kmem_free(PCI_ERR_REG(pfd_p), sizeof (pf_pci_err_regs_t)); 822 823 if (PCIE_IS_ROOT(bus_p)) { 824 kmem_free(PCIE_ROOT_FAULT(pfd_p), sizeof (pf_root_fault_t)); 825 kmem_free(PCIE_ROOT_EH_SRC(pfd_p), sizeof (pf_root_eh_src_t)); 826 } 827 828 kmem_free(PCIE_DIP2PFD(dip), sizeof (pf_data_t)); 829 830 PCIE_DIP2PFD(dip) = NULL; 831 } 832 833 834 /* 835 * Special functions to allocate pf_data_t's for PCIe root complexes. 836 * Note: Root Complex not Root Port 837 */ 838 void 839 pcie_rc_init_pfd(dev_info_t *dip, pf_data_t *pfd_p) 840 { 841 pfd_p->pe_bus_p = PCIE_DIP2DOWNBUS(dip); 842 pfd_p->pe_severity_flags = 0; 843 pfd_p->pe_orig_severity_flags = 0; 844 pfd_p->pe_lock = B_FALSE; 845 pfd_p->pe_valid = B_FALSE; 846 847 PCIE_ROOT_FAULT(pfd_p) = PCIE_ZALLOC(pf_root_fault_t); 848 PCIE_ROOT_FAULT(pfd_p)->scan_bdf = PCIE_INVALID_BDF; 849 PCIE_ROOT_EH_SRC(pfd_p) = PCIE_ZALLOC(pf_root_eh_src_t); 850 PCI_ERR_REG(pfd_p) = PCIE_ZALLOC(pf_pci_err_regs_t); 851 PFD_AFFECTED_DEV(pfd_p) = PCIE_ZALLOC(pf_affected_dev_t); 852 PFD_AFFECTED_DEV(pfd_p)->pe_affected_bdf = PCIE_INVALID_BDF; 853 PCI_BDG_ERR_REG(pfd_p) = PCIE_ZALLOC(pf_pci_bdg_err_regs_t); 854 PCIE_ERR_REG(pfd_p) = PCIE_ZALLOC(pf_pcie_err_regs_t); 855 PCIE_RP_REG(pfd_p) = PCIE_ZALLOC(pf_pcie_rp_err_regs_t); 856 PCIE_ADV_REG(pfd_p) = PCIE_ZALLOC(pf_pcie_adv_err_regs_t); 857 PCIE_ADV_RP_REG(pfd_p) = PCIE_ZALLOC(pf_pcie_adv_rp_err_regs_t); 858 PCIE_ADV_RP_REG(pfd_p)->pcie_rp_ce_src_id = PCIE_INVALID_BDF; 859 PCIE_ADV_RP_REG(pfd_p)->pcie_rp_ue_src_id = PCIE_INVALID_BDF; 860 861 PCIE_ADV_REG(pfd_p)->pcie_ue_sev = pcie_aer_uce_severity; 862 } 863 864 void 865 pcie_rc_fini_pfd(pf_data_t *pfd_p) 866 { 867 kmem_free(PCIE_ADV_RP_REG(pfd_p), sizeof (pf_pcie_adv_rp_err_regs_t)); 868 kmem_free(PCIE_ADV_REG(pfd_p), sizeof (pf_pcie_adv_err_regs_t)); 869 kmem_free(PCIE_RP_REG(pfd_p), sizeof (pf_pcie_rp_err_regs_t)); 870 kmem_free(PCIE_ERR_REG(pfd_p), sizeof (pf_pcie_err_regs_t)); 871 kmem_free(PCI_BDG_ERR_REG(pfd_p), sizeof (pf_pci_bdg_err_regs_t)); 872 kmem_free(PFD_AFFECTED_DEV(pfd_p), sizeof (pf_affected_dev_t)); 873 kmem_free(PCI_ERR_REG(pfd_p), sizeof (pf_pci_err_regs_t)); 874 kmem_free(PCIE_ROOT_FAULT(pfd_p), sizeof (pf_root_fault_t)); 875 kmem_free(PCIE_ROOT_EH_SRC(pfd_p), sizeof (pf_root_eh_src_t)); 876 } 877 878 /* 879 * init pcie_bus_t for root complex 880 * 881 * Only a few of the fields in bus_t is valid for root complex. 882 * The fields that are bracketed are initialized in this routine: 883 * 884 * dev_info_t * <bus_dip> 885 * dev_info_t * bus_rp_dip 886 * ddi_acc_handle_t bus_cfg_hdl 887 * uint_t <bus_fm_flags> 888 * pcie_req_id_t bus_bdf 889 * pcie_req_id_t bus_rp_bdf 890 * uint32_t bus_dev_ven_id 891 * uint8_t bus_rev_id 892 * uint8_t <bus_hdr_type> 893 * uint16_t <bus_dev_type> 894 * uint8_t bus_bdg_secbus 895 * uint16_t bus_pcie_off 896 * uint16_t <bus_aer_off> 897 * uint16_t bus_pcix_off 898 * uint16_t bus_ecc_ver 899 * pci_bus_range_t bus_bus_range 900 * ppb_ranges_t * bus_addr_ranges 901 * int bus_addr_entries 902 * pci_regspec_t * bus_assigned_addr 903 * int bus_assigned_entries 904 * pf_data_t * bus_pfd 905 * pcie_domain_t * <bus_dom> 906 * int bus_mps 907 * uint64_t bus_cfgacc_base 908 * void * bus_plat_private 909 */ 910 void 911 pcie_rc_init_bus(dev_info_t *dip) 912 { 913 pcie_bus_t *bus_p; 914 915 bus_p = (pcie_bus_t *)kmem_zalloc(sizeof (pcie_bus_t), KM_SLEEP); 916 bus_p->bus_dip = dip; 917 bus_p->bus_dev_type = PCIE_PCIECAP_DEV_TYPE_RC_PSEUDO; 918 bus_p->bus_hdr_type = PCI_HEADER_ONE; 919 920 /* Fake that there are AER logs */ 921 bus_p->bus_aer_off = (uint16_t)-1; 922 923 /* Needed only for handle lookup */ 924 bus_p->bus_fm_flags |= PF_FM_READY; 925 926 ndi_set_bus_private(dip, B_FALSE, DEVI_PORT_TYPE_PCI, bus_p); 927 928 PCIE_BUS2DOM(bus_p) = PCIE_ZALLOC(pcie_domain_t); 929 } 930 931 void 932 pcie_rc_fini_bus(dev_info_t *dip) 933 { 934 pcie_bus_t *bus_p = PCIE_DIP2DOWNBUS(dip); 935 ndi_set_bus_private(dip, B_FALSE, 0, NULL); 936 kmem_free(PCIE_BUS2DOM(bus_p), sizeof (pcie_domain_t)); 937 kmem_free(bus_p, sizeof (pcie_bus_t)); 938 } 939 940 /* 941 * We need to capture the supported, maximum, and current device speed and 942 * width. The way that this has been done has changed over time. 943 * 944 * Prior to PCIe Gen 3, there were only current and supported speed fields. 945 * These were found in the link status and link capabilities registers of the 946 * PCI express capability. With the change to PCIe Gen 3, the information in the 947 * link capabilities changed to the maximum value. The supported speeds vector 948 * was moved to the link capabilities 2 register. 949 * 950 * Now, a device may not implement some of these registers. To determine whether 951 * or not it's here, we have to do the following. First, we need to check the 952 * revision of the PCI express capability. The link capabilities 2 register did 953 * not exist prior to version 2 of this register. 954 */ 955 static void 956 pcie_capture_speeds(pcie_bus_t *bus_p, pcie_req_id_t bdf, dev_info_t *rcdip) 957 { 958 uint16_t vers, status; 959 uint32_t val, cap, cap2; 960 961 if (!PCIE_IS_PCIE(bus_p)) 962 return; 963 964 vers = pci_cfgacc_get16(rcdip, bdf, bus_p->bus_pcie_off + PCIE_PCIECAP); 965 if (vers == PCI_EINVAL16) 966 return; 967 vers &= PCIE_PCIECAP_VER_MASK; 968 969 /* 970 * Verify the capability's version. 971 */ 972 switch (vers) { 973 case PCIE_PCIECAP_VER_1_0: 974 cap2 = 0; 975 break; 976 case PCIE_PCIECAP_VER_2_0: 977 cap2 = pci_cfgacc_get32(rcdip, bdf, bus_p->bus_pcie_off + 978 PCIE_LINKCAP2); 979 if (cap2 == PCI_EINVAL32) 980 cap2 = 0; 981 break; 982 default: 983 /* Don't try and handle an unknown version */ 984 return; 985 } 986 987 status = pci_cfgacc_get16(rcdip, bdf, bus_p->bus_pcie_off + 988 PCIE_LINKSTS); 989 cap = pci_cfgacc_get32(rcdip, bdf, bus_p->bus_pcie_off + PCIE_LINKCAP); 990 if (status == PCI_EINVAL16 || cap == PCI_EINVAL32) 991 return; 992 993 switch (status & PCIE_LINKSTS_SPEED_MASK) { 994 case PCIE_LINKSTS_SPEED_2_5: 995 bus_p->bus_cur_speed = PCIE_LINK_SPEED_2_5; 996 break; 997 case PCIE_LINKSTS_SPEED_5: 998 bus_p->bus_cur_speed = PCIE_LINK_SPEED_5; 999 break; 1000 case PCIE_LINKSTS_SPEED_8: 1001 bus_p->bus_cur_speed = PCIE_LINK_SPEED_8; 1002 break; 1003 default: 1004 bus_p->bus_cur_speed = PCIE_LINK_SPEED_UNKNOWN; 1005 break; 1006 } 1007 1008 switch (status & PCIE_LINKSTS_NEG_WIDTH_MASK) { 1009 case PCIE_LINKSTS_NEG_WIDTH_X1: 1010 bus_p->bus_cur_width = PCIE_LINK_WIDTH_X1; 1011 break; 1012 case PCIE_LINKSTS_NEG_WIDTH_X2: 1013 bus_p->bus_cur_width = PCIE_LINK_WIDTH_X2; 1014 break; 1015 case PCIE_LINKSTS_NEG_WIDTH_X4: 1016 bus_p->bus_cur_width = PCIE_LINK_WIDTH_X4; 1017 break; 1018 case PCIE_LINKSTS_NEG_WIDTH_X8: 1019 bus_p->bus_cur_width = PCIE_LINK_WIDTH_X8; 1020 break; 1021 case PCIE_LINKSTS_NEG_WIDTH_X12: 1022 bus_p->bus_cur_width = PCIE_LINK_WIDTH_X12; 1023 break; 1024 case PCIE_LINKSTS_NEG_WIDTH_X16: 1025 bus_p->bus_cur_width = PCIE_LINK_WIDTH_X16; 1026 break; 1027 case PCIE_LINKSTS_NEG_WIDTH_X32: 1028 bus_p->bus_cur_width = PCIE_LINK_WIDTH_X32; 1029 break; 1030 default: 1031 bus_p->bus_cur_width = PCIE_LINK_WIDTH_UNKNOWN; 1032 break; 1033 } 1034 1035 switch (cap & PCIE_LINKCAP_MAX_WIDTH_MASK) { 1036 case PCIE_LINKCAP_MAX_WIDTH_X1: 1037 bus_p->bus_max_width = PCIE_LINK_WIDTH_X1; 1038 break; 1039 case PCIE_LINKCAP_MAX_WIDTH_X2: 1040 bus_p->bus_max_width = PCIE_LINK_WIDTH_X2; 1041 break; 1042 case PCIE_LINKCAP_MAX_WIDTH_X4: 1043 bus_p->bus_max_width = PCIE_LINK_WIDTH_X4; 1044 break; 1045 case PCIE_LINKCAP_MAX_WIDTH_X8: 1046 bus_p->bus_max_width = PCIE_LINK_WIDTH_X8; 1047 break; 1048 case PCIE_LINKCAP_MAX_WIDTH_X12: 1049 bus_p->bus_max_width = PCIE_LINK_WIDTH_X12; 1050 break; 1051 case PCIE_LINKCAP_MAX_WIDTH_X16: 1052 bus_p->bus_max_width = PCIE_LINK_WIDTH_X16; 1053 break; 1054 case PCIE_LINKCAP_MAX_WIDTH_X32: 1055 bus_p->bus_max_width = PCIE_LINK_WIDTH_X32; 1056 break; 1057 default: 1058 bus_p->bus_max_width = PCIE_LINK_WIDTH_UNKNOWN; 1059 break; 1060 } 1061 1062 /* 1063 * If we have the Link Capabilities 2, then we can get the supported 1064 * speeds from it and treat the bits in Link Capabilities 1 as the 1065 * maximum. If we don't, then we need to follow the Implementation Note 1066 * in the standard under Link Capabilities 2. Effectively, this means 1067 * that if the value of 10b is set in Link Capabilities register, that 1068 * it supports both 2.5 and 5 GT/s speeds. 1069 */ 1070 if (cap2 != 0) { 1071 if (cap2 & PCIE_LINKCAP2_SPEED_2_5) 1072 bus_p->bus_sup_speed |= PCIE_LINK_SPEED_2_5; 1073 if (cap2 & PCIE_LINKCAP2_SPEED_5) 1074 bus_p->bus_sup_speed |= PCIE_LINK_SPEED_5; 1075 if (cap2 & PCIE_LINKCAP2_SPEED_8) 1076 bus_p->bus_sup_speed |= PCIE_LINK_SPEED_8; 1077 1078 switch (cap & PCIE_LINKCAP_MAX_SPEED_MASK) { 1079 case PCIE_LINKCAP_MAX_SPEED_2_5: 1080 bus_p->bus_max_speed = PCIE_LINK_SPEED_2_5; 1081 break; 1082 case PCIE_LINKCAP_MAX_SPEED_5: 1083 bus_p->bus_max_speed = PCIE_LINK_SPEED_5; 1084 break; 1085 case PCIE_LINKCAP_MAX_SPEED_8: 1086 bus_p->bus_max_speed = PCIE_LINK_SPEED_8; 1087 break; 1088 default: 1089 bus_p->bus_max_speed = PCIE_LINK_SPEED_UNKNOWN; 1090 break; 1091 } 1092 } else { 1093 if (cap & PCIE_LINKCAP_MAX_SPEED_5) { 1094 bus_p->bus_max_speed = PCIE_LINK_SPEED_5; 1095 bus_p->bus_sup_speed = PCIE_LINK_SPEED_2_5 | 1096 PCIE_LINK_SPEED_5; 1097 } 1098 1099 if (cap & PCIE_LINKCAP_MAX_SPEED_2_5) { 1100 bus_p->bus_max_speed = PCIE_LINK_SPEED_2_5; 1101 bus_p->bus_sup_speed = PCIE_LINK_SPEED_2_5; 1102 } 1103 } 1104 } 1105 1106 /* 1107 * partially init pcie_bus_t for device (dip,bdf) for accessing pci 1108 * config space 1109 * 1110 * This routine is invoked during boot, either after creating a devinfo node 1111 * (x86 case) or during px driver attach (sparc case); it is also invoked 1112 * in hotplug context after a devinfo node is created. 1113 * 1114 * The fields that are bracketed are initialized if flag PCIE_BUS_INITIAL 1115 * is set: 1116 * 1117 * dev_info_t * <bus_dip> 1118 * dev_info_t * <bus_rp_dip> 1119 * ddi_acc_handle_t bus_cfg_hdl 1120 * uint_t bus_fm_flags 1121 * pcie_req_id_t <bus_bdf> 1122 * pcie_req_id_t <bus_rp_bdf> 1123 * uint32_t <bus_dev_ven_id> 1124 * uint8_t <bus_rev_id> 1125 * uint8_t <bus_hdr_type> 1126 * uint16_t <bus_dev_type> 1127 * uint8_t <bus_bdg_secbus 1128 * uint16_t <bus_pcie_off> 1129 * uint16_t <bus_aer_off> 1130 * uint16_t <bus_pcix_off> 1131 * uint16_t <bus_ecc_ver> 1132 * pci_bus_range_t bus_bus_range 1133 * ppb_ranges_t * bus_addr_ranges 1134 * int bus_addr_entries 1135 * pci_regspec_t * bus_assigned_addr 1136 * int bus_assigned_entries 1137 * pf_data_t * bus_pfd 1138 * pcie_domain_t * bus_dom 1139 * int bus_mps 1140 * uint64_t bus_cfgacc_base 1141 * void * bus_plat_private 1142 * 1143 * The fields that are bracketed are initialized if flag PCIE_BUS_FINAL 1144 * is set: 1145 * 1146 * dev_info_t * bus_dip 1147 * dev_info_t * bus_rp_dip 1148 * ddi_acc_handle_t bus_cfg_hdl 1149 * uint_t bus_fm_flags 1150 * pcie_req_id_t bus_bdf 1151 * pcie_req_id_t bus_rp_bdf 1152 * uint32_t bus_dev_ven_id 1153 * uint8_t bus_rev_id 1154 * uint8_t bus_hdr_type 1155 * uint16_t bus_dev_type 1156 * uint8_t <bus_bdg_secbus> 1157 * uint16_t bus_pcie_off 1158 * uint16_t bus_aer_off 1159 * uint16_t bus_pcix_off 1160 * uint16_t bus_ecc_ver 1161 * pci_bus_range_t <bus_bus_range> 1162 * ppb_ranges_t * <bus_addr_ranges> 1163 * int <bus_addr_entries> 1164 * pci_regspec_t * <bus_assigned_addr> 1165 * int <bus_assigned_entries> 1166 * pf_data_t * <bus_pfd> 1167 * pcie_domain_t * bus_dom 1168 * int bus_mps 1169 * uint64_t bus_cfgacc_base 1170 * void * <bus_plat_private> 1171 */ 1172 1173 pcie_bus_t * 1174 pcie_init_bus(dev_info_t *dip, pcie_req_id_t bdf, uint8_t flags) 1175 { 1176 uint16_t status, base, baseptr, num_cap; 1177 uint32_t capid; 1178 int range_size; 1179 pcie_bus_t *bus_p; 1180 dev_info_t *rcdip; 1181 dev_info_t *pdip; 1182 const char *errstr = NULL; 1183 1184 if (!(flags & PCIE_BUS_INITIAL)) 1185 goto initial_done; 1186 1187 bus_p = kmem_zalloc(sizeof (pcie_bus_t), KM_SLEEP); 1188 1189 bus_p->bus_dip = dip; 1190 bus_p->bus_bdf = bdf; 1191 1192 rcdip = pcie_get_rc_dip(dip); 1193 ASSERT(rcdip != NULL); 1194 1195 /* Save the Vendor ID, Device ID and revision ID */ 1196 bus_p->bus_dev_ven_id = pci_cfgacc_get32(rcdip, bdf, PCI_CONF_VENID); 1197 bus_p->bus_rev_id = pci_cfgacc_get8(rcdip, bdf, PCI_CONF_REVID); 1198 /* Save the Header Type */ 1199 bus_p->bus_hdr_type = pci_cfgacc_get8(rcdip, bdf, PCI_CONF_HEADER); 1200 bus_p->bus_hdr_type &= PCI_HEADER_TYPE_M; 1201 1202 /* 1203 * Figure out the device type and all the relavant capability offsets 1204 */ 1205 /* set default value */ 1206 bus_p->bus_dev_type = PCIE_PCIECAP_DEV_TYPE_PCI_PSEUDO; 1207 1208 status = pci_cfgacc_get16(rcdip, bdf, PCI_CONF_STAT); 1209 if (status == PCI_CAP_EINVAL16 || !(status & PCI_STAT_CAP)) 1210 goto caps_done; /* capability not supported */ 1211 1212 /* Relevant conventional capabilities first */ 1213 1214 /* Conventional caps: PCI_CAP_ID_PCI_E, PCI_CAP_ID_PCIX */ 1215 num_cap = 2; 1216 1217 switch (bus_p->bus_hdr_type) { 1218 case PCI_HEADER_ZERO: 1219 baseptr = PCI_CONF_CAP_PTR; 1220 break; 1221 case PCI_HEADER_PPB: 1222 baseptr = PCI_BCNF_CAP_PTR; 1223 break; 1224 case PCI_HEADER_CARDBUS: 1225 baseptr = PCI_CBUS_CAP_PTR; 1226 break; 1227 default: 1228 cmn_err(CE_WARN, "%s: unexpected pci header type:%x", 1229 __func__, bus_p->bus_hdr_type); 1230 goto caps_done; 1231 } 1232 1233 base = baseptr; 1234 for (base = pci_cfgacc_get8(rcdip, bdf, base); base && num_cap; 1235 base = pci_cfgacc_get8(rcdip, bdf, base + PCI_CAP_NEXT_PTR)) { 1236 capid = pci_cfgacc_get8(rcdip, bdf, base); 1237 switch (capid) { 1238 case PCI_CAP_ID_PCI_E: 1239 bus_p->bus_pcie_off = base; 1240 bus_p->bus_dev_type = pci_cfgacc_get16(rcdip, bdf, 1241 base + PCIE_PCIECAP) & PCIE_PCIECAP_DEV_TYPE_MASK; 1242 1243 /* Check and save PCIe hotplug capability information */ 1244 if ((PCIE_IS_RP(bus_p) || PCIE_IS_SWD(bus_p)) && 1245 (pci_cfgacc_get16(rcdip, bdf, base + PCIE_PCIECAP) 1246 & PCIE_PCIECAP_SLOT_IMPL) && 1247 (pci_cfgacc_get32(rcdip, bdf, base + PCIE_SLOTCAP) 1248 & PCIE_SLOTCAP_HP_CAPABLE)) 1249 bus_p->bus_hp_sup_modes |= PCIE_NATIVE_HP_MODE; 1250 1251 num_cap--; 1252 break; 1253 case PCI_CAP_ID_PCIX: 1254 bus_p->bus_pcix_off = base; 1255 if (PCIE_IS_BDG(bus_p)) 1256 bus_p->bus_ecc_ver = 1257 pci_cfgacc_get16(rcdip, bdf, base + 1258 PCI_PCIX_SEC_STATUS) & PCI_PCIX_VER_MASK; 1259 else 1260 bus_p->bus_ecc_ver = 1261 pci_cfgacc_get16(rcdip, bdf, base + 1262 PCI_PCIX_COMMAND) & PCI_PCIX_VER_MASK; 1263 num_cap--; 1264 break; 1265 default: 1266 break; 1267 } 1268 } 1269 1270 /* Check and save PCI hotplug (SHPC) capability information */ 1271 if (PCIE_IS_BDG(bus_p)) { 1272 base = baseptr; 1273 for (base = pci_cfgacc_get8(rcdip, bdf, base); 1274 base; base = pci_cfgacc_get8(rcdip, bdf, 1275 base + PCI_CAP_NEXT_PTR)) { 1276 capid = pci_cfgacc_get8(rcdip, bdf, base); 1277 if (capid == PCI_CAP_ID_PCI_HOTPLUG) { 1278 bus_p->bus_pci_hp_off = base; 1279 bus_p->bus_hp_sup_modes |= PCIE_PCI_HP_MODE; 1280 break; 1281 } 1282 } 1283 } 1284 1285 /* Then, relevant extended capabilities */ 1286 1287 if (!PCIE_IS_PCIE(bus_p)) 1288 goto caps_done; 1289 1290 /* Extended caps: PCIE_EXT_CAP_ID_AER */ 1291 for (base = PCIE_EXT_CAP; base; base = (capid >> 1292 PCIE_EXT_CAP_NEXT_PTR_SHIFT) & PCIE_EXT_CAP_NEXT_PTR_MASK) { 1293 capid = pci_cfgacc_get32(rcdip, bdf, base); 1294 if (capid == PCI_CAP_EINVAL32) 1295 break; 1296 if (((capid >> PCIE_EXT_CAP_ID_SHIFT) & PCIE_EXT_CAP_ID_MASK) 1297 == PCIE_EXT_CAP_ID_AER) { 1298 bus_p->bus_aer_off = base; 1299 break; 1300 } 1301 } 1302 1303 /* 1304 * Save and record speed information about the device. 1305 */ 1306 1307 caps_done: 1308 /* save RP dip and RP bdf */ 1309 if (PCIE_IS_RP(bus_p)) { 1310 bus_p->bus_rp_dip = dip; 1311 bus_p->bus_rp_bdf = bus_p->bus_bdf; 1312 } else { 1313 for (pdip = ddi_get_parent(dip); pdip; 1314 pdip = ddi_get_parent(pdip)) { 1315 pcie_bus_t *parent_bus_p = PCIE_DIP2BUS(pdip); 1316 1317 /* 1318 * If RP dip and RP bdf in parent's bus_t have 1319 * been initialized, simply use these instead of 1320 * continuing up to the RC. 1321 */ 1322 if (parent_bus_p->bus_rp_dip != NULL) { 1323 bus_p->bus_rp_dip = parent_bus_p->bus_rp_dip; 1324 bus_p->bus_rp_bdf = parent_bus_p->bus_rp_bdf; 1325 break; 1326 } 1327 1328 /* 1329 * When debugging be aware that some NVIDIA x86 1330 * architectures have 2 nodes for each RP, One at Bus 1331 * 0x0 and one at Bus 0x80. The requester is from Bus 1332 * 0x80 1333 */ 1334 if (PCIE_IS_ROOT(parent_bus_p)) { 1335 bus_p->bus_rp_dip = pdip; 1336 bus_p->bus_rp_bdf = parent_bus_p->bus_bdf; 1337 break; 1338 } 1339 } 1340 } 1341 1342 bus_p->bus_soft_state = PCI_SOFT_STATE_CLOSED; 1343 bus_p->bus_fm_flags = 0; 1344 bus_p->bus_mps = 0; 1345 1346 ndi_set_bus_private(dip, B_TRUE, DEVI_PORT_TYPE_PCI, (void *)bus_p); 1347 1348 if (PCIE_IS_HOTPLUG_CAPABLE(dip)) 1349 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 1350 "hotplug-capable"); 1351 1352 initial_done: 1353 if (!(flags & PCIE_BUS_FINAL)) 1354 goto final_done; 1355 1356 /* already initialized? */ 1357 bus_p = PCIE_DIP2BUS(dip); 1358 1359 /* Save the Range information if device is a switch/bridge */ 1360 if (PCIE_IS_BDG(bus_p)) { 1361 /* get "bus_range" property */ 1362 range_size = sizeof (pci_bus_range_t); 1363 if (ddi_getlongprop_buf(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1364 "bus-range", (caddr_t)&bus_p->bus_bus_range, &range_size) 1365 != DDI_PROP_SUCCESS) { 1366 errstr = "Cannot find \"bus-range\" property"; 1367 cmn_err(CE_WARN, 1368 "PCIE init err info failed BDF 0x%x:%s\n", 1369 bus_p->bus_bdf, errstr); 1370 } 1371 1372 /* get secondary bus number */ 1373 rcdip = pcie_get_rc_dip(dip); 1374 ASSERT(rcdip != NULL); 1375 1376 bus_p->bus_bdg_secbus = pci_cfgacc_get8(rcdip, 1377 bus_p->bus_bdf, PCI_BCNF_SECBUS); 1378 1379 /* Get "ranges" property */ 1380 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1381 "ranges", (caddr_t)&bus_p->bus_addr_ranges, 1382 &bus_p->bus_addr_entries) != DDI_PROP_SUCCESS) 1383 bus_p->bus_addr_entries = 0; 1384 bus_p->bus_addr_entries /= sizeof (ppb_ranges_t); 1385 } 1386 1387 /* save "assigned-addresses" property array, ignore failues */ 1388 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1389 "assigned-addresses", (caddr_t)&bus_p->bus_assigned_addr, 1390 &bus_p->bus_assigned_entries) == DDI_PROP_SUCCESS) 1391 bus_p->bus_assigned_entries /= sizeof (pci_regspec_t); 1392 else 1393 bus_p->bus_assigned_entries = 0; 1394 1395 pcie_init_pfd(dip); 1396 1397 pcie_init_plat(dip); 1398 1399 pcie_capture_speeds(bus_p, bdf, rcdip); 1400 1401 final_done: 1402 1403 PCIE_DBG("Add %s(dip 0x%p, bdf 0x%x, secbus 0x%x)\n", 1404 ddi_driver_name(dip), (void *)dip, bus_p->bus_bdf, 1405 bus_p->bus_bdg_secbus); 1406 #ifdef DEBUG 1407 pcie_print_bus(bus_p); 1408 #endif 1409 1410 return (bus_p); 1411 } 1412 1413 /* 1414 * Invoked before destroying devinfo node, mostly during hotplug 1415 * operation to free pcie_bus_t data structure 1416 */ 1417 /* ARGSUSED */ 1418 void 1419 pcie_fini_bus(dev_info_t *dip, uint8_t flags) 1420 { 1421 pcie_bus_t *bus_p = PCIE_DIP2UPBUS(dip); 1422 ASSERT(bus_p); 1423 1424 if (flags & PCIE_BUS_INITIAL) { 1425 pcie_fini_plat(dip); 1426 pcie_fini_pfd(dip); 1427 1428 kmem_free(bus_p->bus_assigned_addr, 1429 (sizeof (pci_regspec_t) * bus_p->bus_assigned_entries)); 1430 kmem_free(bus_p->bus_addr_ranges, 1431 (sizeof (ppb_ranges_t) * bus_p->bus_addr_entries)); 1432 /* zero out the fields that have been destroyed */ 1433 bus_p->bus_assigned_addr = NULL; 1434 bus_p->bus_addr_ranges = NULL; 1435 bus_p->bus_assigned_entries = 0; 1436 bus_p->bus_addr_entries = 0; 1437 } 1438 1439 if (flags & PCIE_BUS_FINAL) { 1440 if (PCIE_IS_HOTPLUG_CAPABLE(dip)) { 1441 (void) ndi_prop_remove(DDI_DEV_T_NONE, dip, 1442 "hotplug-capable"); 1443 } 1444 1445 ndi_set_bus_private(dip, B_TRUE, 0, NULL); 1446 kmem_free(bus_p, sizeof (pcie_bus_t)); 1447 } 1448 } 1449 1450 int 1451 pcie_postattach_child(dev_info_t *cdip) 1452 { 1453 pcie_bus_t *bus_p = PCIE_DIP2BUS(cdip); 1454 1455 if (!bus_p) 1456 return (DDI_FAILURE); 1457 1458 return (pcie_enable_ce(cdip)); 1459 } 1460 1461 /* 1462 * PCI-Express child device de-initialization. 1463 * This function disables generic pci-express interrupts and error 1464 * handling. 1465 */ 1466 void 1467 pcie_uninitchild(dev_info_t *cdip) 1468 { 1469 pcie_disable_errors(cdip); 1470 pcie_fini_cfghdl(cdip); 1471 pcie_fini_dom(cdip); 1472 } 1473 1474 /* 1475 * find the root complex dip 1476 */ 1477 dev_info_t * 1478 pcie_get_rc_dip(dev_info_t *dip) 1479 { 1480 dev_info_t *rcdip; 1481 pcie_bus_t *rc_bus_p; 1482 1483 for (rcdip = ddi_get_parent(dip); rcdip; 1484 rcdip = ddi_get_parent(rcdip)) { 1485 rc_bus_p = PCIE_DIP2BUS(rcdip); 1486 if (rc_bus_p && PCIE_IS_RC(rc_bus_p)) 1487 break; 1488 } 1489 1490 return (rcdip); 1491 } 1492 1493 static boolean_t 1494 pcie_is_pci_device(dev_info_t *dip) 1495 { 1496 dev_info_t *pdip; 1497 char *device_type; 1498 1499 pdip = ddi_get_parent(dip); 1500 ASSERT(pdip); 1501 1502 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, pdip, DDI_PROP_DONTPASS, 1503 "device_type", &device_type) != DDI_PROP_SUCCESS) 1504 return (B_FALSE); 1505 1506 if (strcmp(device_type, "pciex") != 0 && 1507 strcmp(device_type, "pci") != 0) { 1508 ddi_prop_free(device_type); 1509 return (B_FALSE); 1510 } 1511 1512 ddi_prop_free(device_type); 1513 return (B_TRUE); 1514 } 1515 1516 typedef struct { 1517 boolean_t init; 1518 uint8_t flags; 1519 } pcie_bus_arg_t; 1520 1521 /*ARGSUSED*/ 1522 static int 1523 pcie_fab_do_init_fini(dev_info_t *dip, void *arg) 1524 { 1525 pcie_req_id_t bdf; 1526 pcie_bus_arg_t *bus_arg = (pcie_bus_arg_t *)arg; 1527 1528 if (!pcie_is_pci_device(dip)) 1529 goto out; 1530 1531 if (bus_arg->init) { 1532 if (pcie_get_bdf_from_dip(dip, &bdf) != DDI_SUCCESS) 1533 goto out; 1534 1535 (void) pcie_init_bus(dip, bdf, bus_arg->flags); 1536 } else { 1537 (void) pcie_fini_bus(dip, bus_arg->flags); 1538 } 1539 1540 return (DDI_WALK_CONTINUE); 1541 1542 out: 1543 return (DDI_WALK_PRUNECHILD); 1544 } 1545 1546 void 1547 pcie_fab_init_bus(dev_info_t *rcdip, uint8_t flags) 1548 { 1549 int circular_count; 1550 dev_info_t *dip = ddi_get_child(rcdip); 1551 pcie_bus_arg_t arg; 1552 1553 arg.init = B_TRUE; 1554 arg.flags = flags; 1555 1556 ndi_devi_enter(rcdip, &circular_count); 1557 ddi_walk_devs(dip, pcie_fab_do_init_fini, &arg); 1558 ndi_devi_exit(rcdip, circular_count); 1559 } 1560 1561 void 1562 pcie_fab_fini_bus(dev_info_t *rcdip, uint8_t flags) 1563 { 1564 int circular_count; 1565 dev_info_t *dip = ddi_get_child(rcdip); 1566 pcie_bus_arg_t arg; 1567 1568 arg.init = B_FALSE; 1569 arg.flags = flags; 1570 1571 ndi_devi_enter(rcdip, &circular_count); 1572 ddi_walk_devs(dip, pcie_fab_do_init_fini, &arg); 1573 ndi_devi_exit(rcdip, circular_count); 1574 } 1575 1576 void 1577 pcie_enable_errors(dev_info_t *dip) 1578 { 1579 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 1580 uint16_t reg16, tmp16; 1581 uint32_t reg32, tmp32; 1582 1583 ASSERT(bus_p); 1584 1585 /* 1586 * Clear any pending errors 1587 */ 1588 pcie_clear_errors(dip); 1589 1590 if (!PCIE_IS_PCIE(bus_p)) 1591 return; 1592 1593 /* 1594 * Enable Baseline Error Handling but leave CE reporting off (poweron 1595 * default). 1596 */ 1597 if ((reg16 = PCIE_CAP_GET(16, bus_p, PCIE_DEVCTL)) != 1598 PCI_CAP_EINVAL16) { 1599 tmp16 = (reg16 & (PCIE_DEVCTL_MAX_READ_REQ_MASK | 1600 PCIE_DEVCTL_MAX_PAYLOAD_MASK)) | 1601 (pcie_devctl_default & ~(PCIE_DEVCTL_MAX_READ_REQ_MASK | 1602 PCIE_DEVCTL_MAX_PAYLOAD_MASK)) | 1603 (pcie_base_err_default & (~PCIE_DEVCTL_CE_REPORTING_EN)); 1604 1605 PCIE_CAP_PUT(16, bus_p, PCIE_DEVCTL, tmp16); 1606 PCIE_DBG_CAP(dip, bus_p, "DEVCTL", 16, PCIE_DEVCTL, reg16); 1607 } 1608 1609 /* Enable Root Port Baseline Error Receiving */ 1610 if (PCIE_IS_ROOT(bus_p) && 1611 (reg16 = PCIE_CAP_GET(16, bus_p, PCIE_ROOTCTL)) != 1612 PCI_CAP_EINVAL16) { 1613 1614 tmp16 = pcie_serr_disable_flag ? 1615 (pcie_root_ctrl_default & ~PCIE_ROOT_SYS_ERR) : 1616 pcie_root_ctrl_default; 1617 PCIE_CAP_PUT(16, bus_p, PCIE_ROOTCTL, tmp16); 1618 PCIE_DBG_CAP(dip, bus_p, "ROOT DEVCTL", 16, PCIE_ROOTCTL, 1619 reg16); 1620 } 1621 1622 /* 1623 * Enable PCI-Express Advanced Error Handling if Exists 1624 */ 1625 if (!PCIE_HAS_AER(bus_p)) 1626 return; 1627 1628 /* Set Uncorrectable Severity */ 1629 if ((reg32 = PCIE_AER_GET(32, bus_p, PCIE_AER_UCE_SERV)) != 1630 PCI_CAP_EINVAL32) { 1631 tmp32 = pcie_aer_uce_severity; 1632 1633 PCIE_AER_PUT(32, bus_p, PCIE_AER_UCE_SERV, tmp32); 1634 PCIE_DBG_AER(dip, bus_p, "AER UCE SEV", 32, PCIE_AER_UCE_SERV, 1635 reg32); 1636 } 1637 1638 /* Enable Uncorrectable errors */ 1639 if ((reg32 = PCIE_AER_GET(32, bus_p, PCIE_AER_UCE_MASK)) != 1640 PCI_CAP_EINVAL32) { 1641 tmp32 = pcie_aer_uce_mask; 1642 1643 PCIE_AER_PUT(32, bus_p, PCIE_AER_UCE_MASK, tmp32); 1644 PCIE_DBG_AER(dip, bus_p, "AER UCE MASK", 32, PCIE_AER_UCE_MASK, 1645 reg32); 1646 } 1647 1648 /* Enable ECRC generation and checking */ 1649 if ((reg32 = PCIE_AER_GET(32, bus_p, PCIE_AER_CTL)) != 1650 PCI_CAP_EINVAL32) { 1651 tmp32 = reg32 | pcie_ecrc_value; 1652 PCIE_AER_PUT(32, bus_p, PCIE_AER_CTL, tmp32); 1653 PCIE_DBG_AER(dip, bus_p, "AER CTL", 32, PCIE_AER_CTL, reg32); 1654 } 1655 1656 /* Enable Secondary Uncorrectable errors if this is a bridge */ 1657 if (!PCIE_IS_PCIE_BDG(bus_p)) 1658 goto root; 1659 1660 /* Set Uncorrectable Severity */ 1661 if ((reg32 = PCIE_AER_GET(32, bus_p, PCIE_AER_SUCE_SERV)) != 1662 PCI_CAP_EINVAL32) { 1663 tmp32 = pcie_aer_suce_severity; 1664 1665 PCIE_AER_PUT(32, bus_p, PCIE_AER_SUCE_SERV, tmp32); 1666 PCIE_DBG_AER(dip, bus_p, "AER SUCE SEV", 32, PCIE_AER_SUCE_SERV, 1667 reg32); 1668 } 1669 1670 if ((reg32 = PCIE_AER_GET(32, bus_p, PCIE_AER_SUCE_MASK)) != 1671 PCI_CAP_EINVAL32) { 1672 PCIE_AER_PUT(32, bus_p, PCIE_AER_SUCE_MASK, pcie_aer_suce_mask); 1673 PCIE_DBG_AER(dip, bus_p, "AER SUCE MASK", 32, 1674 PCIE_AER_SUCE_MASK, reg32); 1675 } 1676 1677 root: 1678 /* 1679 * Enable Root Control this is a Root device 1680 */ 1681 if (!PCIE_IS_ROOT(bus_p)) 1682 return; 1683 1684 if ((reg16 = PCIE_AER_GET(16, bus_p, PCIE_AER_RE_CMD)) != 1685 PCI_CAP_EINVAL16) { 1686 PCIE_AER_PUT(16, bus_p, PCIE_AER_RE_CMD, 1687 pcie_root_error_cmd_default); 1688 PCIE_DBG_AER(dip, bus_p, "AER Root Err Cmd", 16, 1689 PCIE_AER_RE_CMD, reg16); 1690 } 1691 } 1692 1693 /* 1694 * This function is used for enabling CE reporting and setting the AER CE mask. 1695 * When called from outside the pcie module it should always be preceded by 1696 * a call to pcie_enable_errors. 1697 */ 1698 int 1699 pcie_enable_ce(dev_info_t *dip) 1700 { 1701 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 1702 uint16_t device_sts, device_ctl; 1703 uint32_t tmp_pcie_aer_ce_mask; 1704 1705 if (!PCIE_IS_PCIE(bus_p)) 1706 return (DDI_SUCCESS); 1707 1708 /* 1709 * The "pcie_ce_mask" property is used to control both the CE reporting 1710 * enable field in the device control register and the AER CE mask. We 1711 * leave CE reporting disabled if pcie_ce_mask is set to -1. 1712 */ 1713 1714 tmp_pcie_aer_ce_mask = (uint32_t)ddi_prop_get_int(DDI_DEV_T_ANY, dip, 1715 DDI_PROP_DONTPASS, "pcie_ce_mask", pcie_aer_ce_mask); 1716 1717 if (tmp_pcie_aer_ce_mask == (uint32_t)-1) { 1718 /* 1719 * Nothing to do since CE reporting has already been disabled. 1720 */ 1721 return (DDI_SUCCESS); 1722 } 1723 1724 if (PCIE_HAS_AER(bus_p)) { 1725 /* Enable AER CE */ 1726 PCIE_AER_PUT(32, bus_p, PCIE_AER_CE_MASK, tmp_pcie_aer_ce_mask); 1727 PCIE_DBG_AER(dip, bus_p, "AER CE MASK", 32, PCIE_AER_CE_MASK, 1728 0); 1729 1730 /* Clear any pending AER CE errors */ 1731 PCIE_AER_PUT(32, bus_p, PCIE_AER_CE_STS, -1); 1732 } 1733 1734 /* clear any pending CE errors */ 1735 if ((device_sts = PCIE_CAP_GET(16, bus_p, PCIE_DEVSTS)) != 1736 PCI_CAP_EINVAL16) 1737 PCIE_CAP_PUT(16, bus_p, PCIE_DEVSTS, 1738 device_sts & (~PCIE_DEVSTS_CE_DETECTED)); 1739 1740 /* Enable CE reporting */ 1741 device_ctl = PCIE_CAP_GET(16, bus_p, PCIE_DEVCTL); 1742 PCIE_CAP_PUT(16, bus_p, PCIE_DEVCTL, 1743 (device_ctl & (~PCIE_DEVCTL_ERR_MASK)) | pcie_base_err_default); 1744 PCIE_DBG_CAP(dip, bus_p, "DEVCTL", 16, PCIE_DEVCTL, device_ctl); 1745 1746 return (DDI_SUCCESS); 1747 } 1748 1749 /* ARGSUSED */ 1750 void 1751 pcie_disable_errors(dev_info_t *dip) 1752 { 1753 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 1754 uint16_t device_ctl; 1755 uint32_t aer_reg; 1756 1757 if (!PCIE_IS_PCIE(bus_p)) 1758 return; 1759 1760 /* 1761 * Disable PCI-Express Baseline Error Handling 1762 */ 1763 device_ctl = PCIE_CAP_GET(16, bus_p, PCIE_DEVCTL); 1764 device_ctl &= ~PCIE_DEVCTL_ERR_MASK; 1765 PCIE_CAP_PUT(16, bus_p, PCIE_DEVCTL, device_ctl); 1766 1767 /* 1768 * Disable PCI-Express Advanced Error Handling if Exists 1769 */ 1770 if (!PCIE_HAS_AER(bus_p)) 1771 goto root; 1772 1773 /* Disable Uncorrectable errors */ 1774 PCIE_AER_PUT(32, bus_p, PCIE_AER_UCE_MASK, PCIE_AER_UCE_BITS); 1775 1776 /* Disable Correctable errors */ 1777 PCIE_AER_PUT(32, bus_p, PCIE_AER_CE_MASK, PCIE_AER_CE_BITS); 1778 1779 /* Disable ECRC generation and checking */ 1780 if ((aer_reg = PCIE_AER_GET(32, bus_p, PCIE_AER_CTL)) != 1781 PCI_CAP_EINVAL32) { 1782 aer_reg &= ~(PCIE_AER_CTL_ECRC_GEN_ENA | 1783 PCIE_AER_CTL_ECRC_CHECK_ENA); 1784 1785 PCIE_AER_PUT(32, bus_p, PCIE_AER_CTL, aer_reg); 1786 } 1787 /* 1788 * Disable Secondary Uncorrectable errors if this is a bridge 1789 */ 1790 if (!PCIE_IS_PCIE_BDG(bus_p)) 1791 goto root; 1792 1793 PCIE_AER_PUT(32, bus_p, PCIE_AER_SUCE_MASK, PCIE_AER_SUCE_BITS); 1794 1795 root: 1796 /* 1797 * disable Root Control this is a Root device 1798 */ 1799 if (!PCIE_IS_ROOT(bus_p)) 1800 return; 1801 1802 if (!pcie_serr_disable_flag) { 1803 device_ctl = PCIE_CAP_GET(16, bus_p, PCIE_ROOTCTL); 1804 device_ctl &= ~PCIE_ROOT_SYS_ERR; 1805 PCIE_CAP_PUT(16, bus_p, PCIE_ROOTCTL, device_ctl); 1806 } 1807 1808 if (!PCIE_HAS_AER(bus_p)) 1809 return; 1810 1811 if ((device_ctl = PCIE_CAP_GET(16, bus_p, PCIE_AER_RE_CMD)) != 1812 PCI_CAP_EINVAL16) { 1813 device_ctl &= ~pcie_root_error_cmd_default; 1814 PCIE_CAP_PUT(16, bus_p, PCIE_AER_RE_CMD, device_ctl); 1815 } 1816 } 1817 1818 /* 1819 * Extract bdf from "reg" property. 1820 */ 1821 int 1822 pcie_get_bdf_from_dip(dev_info_t *dip, pcie_req_id_t *bdf) 1823 { 1824 pci_regspec_t *regspec; 1825 int reglen; 1826 1827 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1828 "reg", (int **)®spec, (uint_t *)®len) != DDI_SUCCESS) 1829 return (DDI_FAILURE); 1830 1831 if (reglen < (sizeof (pci_regspec_t) / sizeof (int))) { 1832 ddi_prop_free(regspec); 1833 return (DDI_FAILURE); 1834 } 1835 1836 /* Get phys_hi from first element. All have same bdf. */ 1837 *bdf = (regspec->pci_phys_hi & (PCI_REG_BDFR_M ^ PCI_REG_REG_M)) >> 8; 1838 1839 ddi_prop_free(regspec); 1840 return (DDI_SUCCESS); 1841 } 1842 1843 dev_info_t * 1844 pcie_get_my_childs_dip(dev_info_t *dip, dev_info_t *rdip) 1845 { 1846 dev_info_t *cdip = rdip; 1847 1848 for (; ddi_get_parent(cdip) != dip; cdip = ddi_get_parent(cdip)) 1849 ; 1850 1851 return (cdip); 1852 } 1853 1854 uint32_t 1855 pcie_get_bdf_for_dma_xfer(dev_info_t *dip, dev_info_t *rdip) 1856 { 1857 dev_info_t *cdip; 1858 1859 /* 1860 * As part of the probing, the PCI fcode interpreter may setup a DMA 1861 * request if a given card has a fcode on it using dip and rdip of the 1862 * hotplug connector i.e, dip and rdip of px/pcieb driver. In this 1863 * case, return a invalid value for the bdf since we cannot get to the 1864 * bdf value of the actual device which will be initiating this DMA. 1865 */ 1866 if (rdip == dip) 1867 return (PCIE_INVALID_BDF); 1868 1869 cdip = pcie_get_my_childs_dip(dip, rdip); 1870 1871 /* 1872 * For a given rdip, return the bdf value of dip's (px or pcieb) 1873 * immediate child or secondary bus-id if dip is a PCIe2PCI bridge. 1874 * 1875 * XXX - For now, return a invalid bdf value for all PCI and PCI-X 1876 * devices since this needs more work. 1877 */ 1878 return (PCI_GET_PCIE2PCI_SECBUS(cdip) ? 1879 PCIE_INVALID_BDF : PCI_GET_BDF(cdip)); 1880 } 1881 1882 uint32_t 1883 pcie_get_aer_uce_mask() 1884 { 1885 return (pcie_aer_uce_mask); 1886 } 1887 uint32_t 1888 pcie_get_aer_ce_mask() 1889 { 1890 return (pcie_aer_ce_mask); 1891 } 1892 uint32_t 1893 pcie_get_aer_suce_mask() 1894 { 1895 return (pcie_aer_suce_mask); 1896 } 1897 uint32_t 1898 pcie_get_serr_mask() 1899 { 1900 return (pcie_serr_disable_flag); 1901 } 1902 1903 void 1904 pcie_set_aer_uce_mask(uint32_t mask) 1905 { 1906 pcie_aer_uce_mask = mask; 1907 if (mask & PCIE_AER_UCE_UR) 1908 pcie_base_err_default &= ~PCIE_DEVCTL_UR_REPORTING_EN; 1909 else 1910 pcie_base_err_default |= PCIE_DEVCTL_UR_REPORTING_EN; 1911 1912 if (mask & PCIE_AER_UCE_ECRC) 1913 pcie_ecrc_value = 0; 1914 } 1915 1916 void 1917 pcie_set_aer_ce_mask(uint32_t mask) 1918 { 1919 pcie_aer_ce_mask = mask; 1920 } 1921 void 1922 pcie_set_aer_suce_mask(uint32_t mask) 1923 { 1924 pcie_aer_suce_mask = mask; 1925 } 1926 void 1927 pcie_set_serr_mask(uint32_t mask) 1928 { 1929 pcie_serr_disable_flag = mask; 1930 } 1931 1932 /* 1933 * Is the rdip a child of dip. Used for checking certain CTLOPS from bubbling 1934 * up erronously. Ex. ISA ctlops to a PCI-PCI Bridge. 1935 */ 1936 boolean_t 1937 pcie_is_child(dev_info_t *dip, dev_info_t *rdip) 1938 { 1939 dev_info_t *cdip = ddi_get_child(dip); 1940 for (; cdip; cdip = ddi_get_next_sibling(cdip)) 1941 if (cdip == rdip) 1942 break; 1943 return (cdip != NULL); 1944 } 1945 1946 boolean_t 1947 pcie_is_link_disabled(dev_info_t *dip) 1948 { 1949 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 1950 1951 if (PCIE_IS_PCIE(bus_p)) { 1952 if (PCIE_CAP_GET(16, bus_p, PCIE_LINKCTL) & 1953 PCIE_LINKCTL_LINK_DISABLE) 1954 return (B_TRUE); 1955 } 1956 return (B_FALSE); 1957 } 1958 1959 /* 1960 * Initialize the MPS for a root port. 1961 * 1962 * dip - dip of root port device. 1963 */ 1964 void 1965 pcie_init_root_port_mps(dev_info_t *dip) 1966 { 1967 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 1968 int rp_cap, max_supported = pcie_max_mps; 1969 1970 (void) pcie_get_fabric_mps(ddi_get_parent(dip), 1971 ddi_get_child(dip), &max_supported); 1972 1973 rp_cap = PCI_CAP_GET16(bus_p->bus_cfg_hdl, 0, 1974 bus_p->bus_pcie_off, PCIE_DEVCAP) & 1975 PCIE_DEVCAP_MAX_PAYLOAD_MASK; 1976 1977 if (rp_cap < max_supported) 1978 max_supported = rp_cap; 1979 1980 bus_p->bus_mps = max_supported; 1981 (void) pcie_initchild_mps(dip); 1982 } 1983 1984 /* 1985 * Initialize the Maximum Payload Size of a device. 1986 * 1987 * cdip - dip of device. 1988 * 1989 * returns - DDI_SUCCESS or DDI_FAILURE 1990 */ 1991 int 1992 pcie_initchild_mps(dev_info_t *cdip) 1993 { 1994 pcie_bus_t *bus_p; 1995 dev_info_t *pdip = ddi_get_parent(cdip); 1996 uint8_t dev_type; 1997 1998 bus_p = PCIE_DIP2BUS(cdip); 1999 if (bus_p == NULL) { 2000 PCIE_DBG("%s: BUS not found.\n", 2001 ddi_driver_name(cdip)); 2002 return (DDI_FAILURE); 2003 } 2004 2005 dev_type = bus_p->bus_dev_type; 2006 2007 /* 2008 * For ARI Devices, only function zero's MPS needs to be set. 2009 */ 2010 if ((dev_type == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV) && 2011 (pcie_ari_is_enabled(pdip) == PCIE_ARI_FORW_ENABLED)) { 2012 pcie_req_id_t child_bdf; 2013 2014 if (pcie_get_bdf_from_dip(cdip, &child_bdf) == DDI_FAILURE) 2015 return (DDI_FAILURE); 2016 if ((child_bdf & PCIE_REQ_ID_ARI_FUNC_MASK) != 0) 2017 return (DDI_SUCCESS); 2018 } 2019 2020 if (PCIE_IS_PCIE(bus_p)) { 2021 int suggested_mrrs, fabric_mps; 2022 uint16_t device_mps, device_mps_cap, device_mrrs, dev_ctrl; 2023 2024 dev_ctrl = PCIE_CAP_GET(16, bus_p, PCIE_DEVCTL); 2025 if ((fabric_mps = (PCIE_IS_RP(bus_p) ? bus_p : 2026 PCIE_DIP2BUS(pdip))->bus_mps) < 0) { 2027 dev_ctrl = (dev_ctrl & ~(PCIE_DEVCTL_MAX_READ_REQ_MASK | 2028 PCIE_DEVCTL_MAX_PAYLOAD_MASK)) | 2029 (pcie_devctl_default & 2030 (PCIE_DEVCTL_MAX_READ_REQ_MASK | 2031 PCIE_DEVCTL_MAX_PAYLOAD_MASK)); 2032 2033 PCIE_CAP_PUT(16, bus_p, PCIE_DEVCTL, dev_ctrl); 2034 return (DDI_SUCCESS); 2035 } 2036 2037 device_mps_cap = PCIE_CAP_GET(16, bus_p, PCIE_DEVCAP) & 2038 PCIE_DEVCAP_MAX_PAYLOAD_MASK; 2039 2040 device_mrrs = (dev_ctrl & PCIE_DEVCTL_MAX_READ_REQ_MASK) >> 2041 PCIE_DEVCTL_MAX_READ_REQ_SHIFT; 2042 2043 if (device_mps_cap < fabric_mps) 2044 device_mrrs = device_mps = device_mps_cap; 2045 else 2046 device_mps = (uint16_t)fabric_mps; 2047 2048 suggested_mrrs = (uint32_t)ddi_prop_get_int(DDI_DEV_T_ANY, 2049 cdip, DDI_PROP_DONTPASS, "suggested-mrrs", device_mrrs); 2050 2051 if ((device_mps == fabric_mps) || 2052 (suggested_mrrs < device_mrrs)) 2053 device_mrrs = (uint16_t)suggested_mrrs; 2054 2055 /* 2056 * Replace MPS and MRRS settings. 2057 */ 2058 dev_ctrl &= ~(PCIE_DEVCTL_MAX_READ_REQ_MASK | 2059 PCIE_DEVCTL_MAX_PAYLOAD_MASK); 2060 2061 dev_ctrl |= ((device_mrrs << PCIE_DEVCTL_MAX_READ_REQ_SHIFT) | 2062 device_mps << PCIE_DEVCTL_MAX_PAYLOAD_SHIFT); 2063 2064 PCIE_CAP_PUT(16, bus_p, PCIE_DEVCTL, dev_ctrl); 2065 2066 bus_p->bus_mps = device_mps; 2067 } 2068 2069 return (DDI_SUCCESS); 2070 } 2071 2072 /* 2073 * Scans a device tree/branch for a maximum payload size capabilities. 2074 * 2075 * rc_dip - dip of Root Complex. 2076 * dip - dip of device where scan will begin. 2077 * max_supported (IN) - maximum allowable MPS. 2078 * max_supported (OUT) - maximum payload size capability of fabric. 2079 */ 2080 void 2081 pcie_get_fabric_mps(dev_info_t *rc_dip, dev_info_t *dip, int *max_supported) 2082 { 2083 if (dip == NULL) 2084 return; 2085 2086 /* 2087 * Perform a fabric scan to obtain Maximum Payload Capabilities 2088 */ 2089 (void) pcie_scan_mps(rc_dip, dip, max_supported); 2090 2091 PCIE_DBG("MPS: Highest Common MPS= %x\n", max_supported); 2092 } 2093 2094 /* 2095 * Scans fabric and determines Maximum Payload Size based on 2096 * highest common denominator alogorithm 2097 */ 2098 static void 2099 pcie_scan_mps(dev_info_t *rc_dip, dev_info_t *dip, int *max_supported) 2100 { 2101 int circular_count; 2102 pcie_max_supported_t max_pay_load_supported; 2103 2104 max_pay_load_supported.dip = rc_dip; 2105 max_pay_load_supported.highest_common_mps = *max_supported; 2106 2107 ndi_devi_enter(ddi_get_parent(dip), &circular_count); 2108 ddi_walk_devs(dip, pcie_get_max_supported, 2109 (void *)&max_pay_load_supported); 2110 ndi_devi_exit(ddi_get_parent(dip), circular_count); 2111 2112 *max_supported = max_pay_load_supported.highest_common_mps; 2113 } 2114 2115 /* 2116 * Called as part of the Maximum Payload Size scan. 2117 */ 2118 static int 2119 pcie_get_max_supported(dev_info_t *dip, void *arg) 2120 { 2121 uint32_t max_supported; 2122 uint16_t cap_ptr; 2123 pcie_max_supported_t *current = (pcie_max_supported_t *)arg; 2124 pci_regspec_t *reg; 2125 int rlen; 2126 caddr_t virt; 2127 ddi_acc_handle_t config_handle; 2128 2129 if (ddi_get_child(current->dip) == NULL) { 2130 goto fail1; 2131 } 2132 2133 if (pcie_dev(dip) == DDI_FAILURE) { 2134 PCIE_DBG("MPS: pcie_get_max_supported: %s: " 2135 "Not a PCIe dev\n", ddi_driver_name(dip)); 2136 goto fail1; 2137 } 2138 2139 /* 2140 * If the suggested-mrrs property exists, then don't include this 2141 * device in the MPS capabilities scan. 2142 */ 2143 if (ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 2144 "suggested-mrrs") != 0) 2145 goto fail1; 2146 2147 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "reg", 2148 (caddr_t)®, &rlen) != DDI_PROP_SUCCESS) { 2149 PCIE_DBG("MPS: pcie_get_max_supported: %s: " 2150 "Can not read reg\n", ddi_driver_name(dip)); 2151 goto fail1; 2152 } 2153 2154 if (pcie_map_phys(ddi_get_child(current->dip), reg, &virt, 2155 &config_handle) != DDI_SUCCESS) { 2156 PCIE_DBG("MPS: pcie_get_max_supported: %s: pcie_map_phys " 2157 "failed\n", ddi_driver_name(dip)); 2158 goto fail2; 2159 } 2160 2161 if ((PCI_CAP_LOCATE(config_handle, PCI_CAP_ID_PCI_E, &cap_ptr)) == 2162 DDI_FAILURE) { 2163 goto fail3; 2164 } 2165 2166 max_supported = PCI_CAP_GET16(config_handle, 0, cap_ptr, 2167 PCIE_DEVCAP) & PCIE_DEVCAP_MAX_PAYLOAD_MASK; 2168 2169 PCIE_DBG("PCIE MPS: %s: MPS Capabilities %x\n", ddi_driver_name(dip), 2170 max_supported); 2171 2172 if (max_supported < current->highest_common_mps) 2173 current->highest_common_mps = max_supported; 2174 2175 fail3: 2176 pcie_unmap_phys(&config_handle, reg); 2177 fail2: 2178 kmem_free(reg, rlen); 2179 fail1: 2180 return (DDI_WALK_CONTINUE); 2181 } 2182 2183 /* 2184 * Determines if there are any root ports attached to a root complex. 2185 * 2186 * dip - dip of root complex 2187 * 2188 * Returns - DDI_SUCCESS if there is at least one root port otherwise 2189 * DDI_FAILURE. 2190 */ 2191 int 2192 pcie_root_port(dev_info_t *dip) 2193 { 2194 int port_type; 2195 uint16_t cap_ptr; 2196 ddi_acc_handle_t config_handle; 2197 dev_info_t *cdip = ddi_get_child(dip); 2198 2199 /* 2200 * Determine if any of the children of the passed in dip 2201 * are root ports. 2202 */ 2203 for (; cdip; cdip = ddi_get_next_sibling(cdip)) { 2204 2205 if (pci_config_setup(cdip, &config_handle) != DDI_SUCCESS) 2206 continue; 2207 2208 if ((PCI_CAP_LOCATE(config_handle, PCI_CAP_ID_PCI_E, 2209 &cap_ptr)) == DDI_FAILURE) { 2210 pci_config_teardown(&config_handle); 2211 continue; 2212 } 2213 2214 port_type = PCI_CAP_GET16(config_handle, 0, cap_ptr, 2215 PCIE_PCIECAP) & PCIE_PCIECAP_DEV_TYPE_MASK; 2216 2217 pci_config_teardown(&config_handle); 2218 2219 if (port_type == PCIE_PCIECAP_DEV_TYPE_ROOT) 2220 return (DDI_SUCCESS); 2221 } 2222 2223 /* No root ports were found */ 2224 2225 return (DDI_FAILURE); 2226 } 2227 2228 /* 2229 * Function that determines if a device a PCIe device. 2230 * 2231 * dip - dip of device. 2232 * 2233 * returns - DDI_SUCCESS if device is a PCIe device, otherwise DDI_FAILURE. 2234 */ 2235 int 2236 pcie_dev(dev_info_t *dip) 2237 { 2238 /* get parent device's device_type property */ 2239 char *device_type; 2240 int rc = DDI_FAILURE; 2241 dev_info_t *pdip = ddi_get_parent(dip); 2242 2243 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, pdip, 2244 DDI_PROP_DONTPASS, "device_type", &device_type) 2245 != DDI_PROP_SUCCESS) { 2246 return (DDI_FAILURE); 2247 } 2248 2249 if (strcmp(device_type, "pciex") == 0) 2250 rc = DDI_SUCCESS; 2251 else 2252 rc = DDI_FAILURE; 2253 2254 ddi_prop_free(device_type); 2255 return (rc); 2256 } 2257 2258 /* 2259 * Function to map in a device's memory space. 2260 */ 2261 static int 2262 pcie_map_phys(dev_info_t *dip, pci_regspec_t *phys_spec, 2263 caddr_t *addrp, ddi_acc_handle_t *handlep) 2264 { 2265 ddi_map_req_t mr; 2266 ddi_acc_hdl_t *hp; 2267 int result; 2268 ddi_device_acc_attr_t attr; 2269 2270 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 2271 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 2272 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 2273 attr.devacc_attr_access = DDI_CAUTIOUS_ACC; 2274 2275 *handlep = impl_acc_hdl_alloc(KM_SLEEP, NULL); 2276 hp = impl_acc_hdl_get(*handlep); 2277 hp->ah_vers = VERS_ACCHDL; 2278 hp->ah_dip = dip; 2279 hp->ah_rnumber = 0; 2280 hp->ah_offset = 0; 2281 hp->ah_len = 0; 2282 hp->ah_acc = attr; 2283 2284 mr.map_op = DDI_MO_MAP_LOCKED; 2285 mr.map_type = DDI_MT_REGSPEC; 2286 mr.map_obj.rp = (struct regspec *)phys_spec; 2287 mr.map_prot = PROT_READ | PROT_WRITE; 2288 mr.map_flags = DDI_MF_KERNEL_MAPPING; 2289 mr.map_handlep = hp; 2290 mr.map_vers = DDI_MAP_VERSION; 2291 2292 result = ddi_map(dip, &mr, 0, 0, addrp); 2293 2294 if (result != DDI_SUCCESS) { 2295 impl_acc_hdl_free(*handlep); 2296 *handlep = (ddi_acc_handle_t)NULL; 2297 } else { 2298 hp->ah_addr = *addrp; 2299 } 2300 2301 return (result); 2302 } 2303 2304 /* 2305 * Map out memory that was mapped in with pcie_map_phys(); 2306 */ 2307 static void 2308 pcie_unmap_phys(ddi_acc_handle_t *handlep, pci_regspec_t *ph) 2309 { 2310 ddi_map_req_t mr; 2311 ddi_acc_hdl_t *hp; 2312 2313 hp = impl_acc_hdl_get(*handlep); 2314 ASSERT(hp); 2315 2316 mr.map_op = DDI_MO_UNMAP; 2317 mr.map_type = DDI_MT_REGSPEC; 2318 mr.map_obj.rp = (struct regspec *)ph; 2319 mr.map_prot = PROT_READ | PROT_WRITE; 2320 mr.map_flags = DDI_MF_KERNEL_MAPPING; 2321 mr.map_handlep = hp; 2322 mr.map_vers = DDI_MAP_VERSION; 2323 2324 (void) ddi_map(hp->ah_dip, &mr, hp->ah_offset, 2325 hp->ah_len, &hp->ah_addr); 2326 2327 impl_acc_hdl_free(*handlep); 2328 *handlep = (ddi_acc_handle_t)NULL; 2329 } 2330 2331 void 2332 pcie_set_rber_fatal(dev_info_t *dip, boolean_t val) 2333 { 2334 pcie_bus_t *bus_p = PCIE_DIP2UPBUS(dip); 2335 bus_p->bus_pfd->pe_rber_fatal = val; 2336 } 2337 2338 /* 2339 * Return parent Root Port's pe_rber_fatal value. 2340 */ 2341 boolean_t 2342 pcie_get_rber_fatal(dev_info_t *dip) 2343 { 2344 pcie_bus_t *bus_p = PCIE_DIP2UPBUS(dip); 2345 pcie_bus_t *rp_bus_p = PCIE_DIP2UPBUS(bus_p->bus_rp_dip); 2346 return (rp_bus_p->bus_pfd->pe_rber_fatal); 2347 } 2348 2349 int 2350 pcie_ari_supported(dev_info_t *dip) 2351 { 2352 uint32_t devcap2; 2353 uint16_t pciecap; 2354 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 2355 uint8_t dev_type; 2356 2357 PCIE_DBG("pcie_ari_supported: dip=%p\n", dip); 2358 2359 if (bus_p == NULL) 2360 return (PCIE_ARI_FORW_NOT_SUPPORTED); 2361 2362 dev_type = bus_p->bus_dev_type; 2363 2364 if ((dev_type != PCIE_PCIECAP_DEV_TYPE_DOWN) && 2365 (dev_type != PCIE_PCIECAP_DEV_TYPE_ROOT)) 2366 return (PCIE_ARI_FORW_NOT_SUPPORTED); 2367 2368 if (pcie_disable_ari) { 2369 PCIE_DBG("pcie_ari_supported: dip=%p: ARI Disabled\n", dip); 2370 return (PCIE_ARI_FORW_NOT_SUPPORTED); 2371 } 2372 2373 pciecap = PCIE_CAP_GET(16, bus_p, PCIE_PCIECAP); 2374 2375 if ((pciecap & PCIE_PCIECAP_VER_MASK) < PCIE_PCIECAP_VER_2_0) { 2376 PCIE_DBG("pcie_ari_supported: dip=%p: Not 2.0\n", dip); 2377 return (PCIE_ARI_FORW_NOT_SUPPORTED); 2378 } 2379 2380 devcap2 = PCIE_CAP_GET(32, bus_p, PCIE_DEVCAP2); 2381 2382 PCIE_DBG("pcie_ari_supported: dip=%p: DevCap2=0x%x\n", 2383 dip, devcap2); 2384 2385 if (devcap2 & PCIE_DEVCAP2_ARI_FORWARD) { 2386 PCIE_DBG("pcie_ari_supported: " 2387 "dip=%p: ARI Forwarding is supported\n", dip); 2388 return (PCIE_ARI_FORW_SUPPORTED); 2389 } 2390 return (PCIE_ARI_FORW_NOT_SUPPORTED); 2391 } 2392 2393 int 2394 pcie_ari_enable(dev_info_t *dip) 2395 { 2396 uint16_t devctl2; 2397 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 2398 2399 PCIE_DBG("pcie_ari_enable: dip=%p\n", dip); 2400 2401 if (pcie_ari_supported(dip) == PCIE_ARI_FORW_NOT_SUPPORTED) 2402 return (DDI_FAILURE); 2403 2404 devctl2 = PCIE_CAP_GET(16, bus_p, PCIE_DEVCTL2); 2405 devctl2 |= PCIE_DEVCTL2_ARI_FORWARD_EN; 2406 PCIE_CAP_PUT(16, bus_p, PCIE_DEVCTL2, devctl2); 2407 2408 PCIE_DBG("pcie_ari_enable: dip=%p: writing 0x%x to DevCtl2\n", 2409 dip, devctl2); 2410 2411 return (DDI_SUCCESS); 2412 } 2413 2414 int 2415 pcie_ari_disable(dev_info_t *dip) 2416 { 2417 uint16_t devctl2; 2418 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 2419 2420 PCIE_DBG("pcie_ari_disable: dip=%p\n", dip); 2421 2422 if (pcie_ari_supported(dip) == PCIE_ARI_FORW_NOT_SUPPORTED) 2423 return (DDI_FAILURE); 2424 2425 devctl2 = PCIE_CAP_GET(16, bus_p, PCIE_DEVCTL2); 2426 devctl2 &= ~PCIE_DEVCTL2_ARI_FORWARD_EN; 2427 PCIE_CAP_PUT(16, bus_p, PCIE_DEVCTL2, devctl2); 2428 2429 PCIE_DBG("pcie_ari_disable: dip=%p: writing 0x%x to DevCtl2\n", 2430 dip, devctl2); 2431 2432 return (DDI_SUCCESS); 2433 } 2434 2435 int 2436 pcie_ari_is_enabled(dev_info_t *dip) 2437 { 2438 uint16_t devctl2; 2439 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 2440 2441 PCIE_DBG("pcie_ari_is_enabled: dip=%p\n", dip); 2442 2443 if (pcie_ari_supported(dip) == PCIE_ARI_FORW_NOT_SUPPORTED) 2444 return (PCIE_ARI_FORW_DISABLED); 2445 2446 devctl2 = PCIE_CAP_GET(32, bus_p, PCIE_DEVCTL2); 2447 2448 PCIE_DBG("pcie_ari_is_enabled: dip=%p: DevCtl2=0x%x\n", 2449 dip, devctl2); 2450 2451 if (devctl2 & PCIE_DEVCTL2_ARI_FORWARD_EN) { 2452 PCIE_DBG("pcie_ari_is_enabled: " 2453 "dip=%p: ARI Forwarding is enabled\n", dip); 2454 return (PCIE_ARI_FORW_ENABLED); 2455 } 2456 2457 return (PCIE_ARI_FORW_DISABLED); 2458 } 2459 2460 int 2461 pcie_ari_device(dev_info_t *dip) 2462 { 2463 ddi_acc_handle_t handle; 2464 uint16_t cap_ptr; 2465 2466 PCIE_DBG("pcie_ari_device: dip=%p\n", dip); 2467 2468 /* 2469 * XXX - This function may be called before the bus_p structure 2470 * has been populated. This code can be changed to remove 2471 * pci_config_setup()/pci_config_teardown() when the RFE 2472 * to populate the bus_p structures early in boot is putback. 2473 */ 2474 2475 /* First make sure it is a PCIe device */ 2476 2477 if (pci_config_setup(dip, &handle) != DDI_SUCCESS) 2478 return (PCIE_NOT_ARI_DEVICE); 2479 2480 if ((PCI_CAP_LOCATE(handle, PCI_CAP_ID_PCI_E, &cap_ptr)) 2481 != DDI_SUCCESS) { 2482 pci_config_teardown(&handle); 2483 return (PCIE_NOT_ARI_DEVICE); 2484 } 2485 2486 /* Locate the ARI Capability */ 2487 2488 if ((PCI_CAP_LOCATE(handle, PCI_CAP_XCFG_SPC(PCIE_EXT_CAP_ID_ARI), 2489 &cap_ptr)) == DDI_FAILURE) { 2490 pci_config_teardown(&handle); 2491 return (PCIE_NOT_ARI_DEVICE); 2492 } 2493 2494 /* ARI Capability was found so it must be a ARI device */ 2495 PCIE_DBG("pcie_ari_device: ARI Device dip=%p\n", dip); 2496 2497 pci_config_teardown(&handle); 2498 return (PCIE_ARI_DEVICE); 2499 } 2500 2501 int 2502 pcie_ari_get_next_function(dev_info_t *dip, int *func) 2503 { 2504 uint32_t val; 2505 uint16_t cap_ptr, next_function; 2506 ddi_acc_handle_t handle; 2507 2508 /* 2509 * XXX - This function may be called before the bus_p structure 2510 * has been populated. This code can be changed to remove 2511 * pci_config_setup()/pci_config_teardown() when the RFE 2512 * to populate the bus_p structures early in boot is putback. 2513 */ 2514 2515 if (pci_config_setup(dip, &handle) != DDI_SUCCESS) 2516 return (DDI_FAILURE); 2517 2518 if ((PCI_CAP_LOCATE(handle, 2519 PCI_CAP_XCFG_SPC(PCIE_EXT_CAP_ID_ARI), &cap_ptr)) == DDI_FAILURE) { 2520 pci_config_teardown(&handle); 2521 return (DDI_FAILURE); 2522 } 2523 2524 val = PCI_CAP_GET32(handle, 0, cap_ptr, PCIE_ARI_CAP); 2525 2526 next_function = (val >> PCIE_ARI_CAP_NEXT_FUNC_SHIFT) & 2527 PCIE_ARI_CAP_NEXT_FUNC_MASK; 2528 2529 pci_config_teardown(&handle); 2530 2531 *func = next_function; 2532 2533 return (DDI_SUCCESS); 2534 } 2535 2536 dev_info_t * 2537 pcie_func_to_dip(dev_info_t *dip, pcie_req_id_t function) 2538 { 2539 pcie_req_id_t child_bdf; 2540 dev_info_t *cdip; 2541 2542 for (cdip = ddi_get_child(dip); cdip; 2543 cdip = ddi_get_next_sibling(cdip)) { 2544 2545 if (pcie_get_bdf_from_dip(cdip, &child_bdf) == DDI_FAILURE) 2546 return (NULL); 2547 2548 if ((child_bdf & PCIE_REQ_ID_ARI_FUNC_MASK) == function) 2549 return (cdip); 2550 } 2551 return (NULL); 2552 } 2553 2554 #ifdef DEBUG 2555 2556 static void 2557 pcie_print_bus(pcie_bus_t *bus_p) 2558 { 2559 pcie_dbg("\tbus_dip = 0x%p\n", bus_p->bus_dip); 2560 pcie_dbg("\tbus_fm_flags = 0x%x\n", bus_p->bus_fm_flags); 2561 2562 pcie_dbg("\tbus_bdf = 0x%x\n", bus_p->bus_bdf); 2563 pcie_dbg("\tbus_dev_ven_id = 0x%x\n", bus_p->bus_dev_ven_id); 2564 pcie_dbg("\tbus_rev_id = 0x%x\n", bus_p->bus_rev_id); 2565 pcie_dbg("\tbus_hdr_type = 0x%x\n", bus_p->bus_hdr_type); 2566 pcie_dbg("\tbus_dev_type = 0x%x\n", bus_p->bus_dev_type); 2567 pcie_dbg("\tbus_bdg_secbus = 0x%x\n", bus_p->bus_bdg_secbus); 2568 pcie_dbg("\tbus_pcie_off = 0x%x\n", bus_p->bus_pcie_off); 2569 pcie_dbg("\tbus_aer_off = 0x%x\n", bus_p->bus_aer_off); 2570 pcie_dbg("\tbus_pcix_off = 0x%x\n", bus_p->bus_pcix_off); 2571 pcie_dbg("\tbus_ecc_ver = 0x%x\n", bus_p->bus_ecc_ver); 2572 } 2573 2574 /* 2575 * For debugging purposes set pcie_dbg_print != 0 to see printf messages 2576 * during interrupt. 2577 * 2578 * When a proper solution is in place this code will disappear. 2579 * Potential solutions are: 2580 * o circular buffers 2581 * o taskq to print at lower pil 2582 */ 2583 int pcie_dbg_print = 0; 2584 void 2585 pcie_dbg(char *fmt, ...) 2586 { 2587 va_list ap; 2588 2589 if (!pcie_debug_flags) { 2590 return; 2591 } 2592 va_start(ap, fmt); 2593 if (servicing_interrupt()) { 2594 if (pcie_dbg_print) { 2595 prom_vprintf(fmt, ap); 2596 } 2597 } else { 2598 prom_vprintf(fmt, ap); 2599 } 2600 va_end(ap); 2601 } 2602 #endif /* DEBUG */ 2603 2604 #if defined(__i386) || defined(__amd64) 2605 static void 2606 pcie_check_io_mem_range(ddi_acc_handle_t cfg_hdl, boolean_t *empty_io_range, 2607 boolean_t *empty_mem_range) 2608 { 2609 uint8_t class, subclass; 2610 uint_t val; 2611 2612 class = pci_config_get8(cfg_hdl, PCI_CONF_BASCLASS); 2613 subclass = pci_config_get8(cfg_hdl, PCI_CONF_SUBCLASS); 2614 2615 if ((class == PCI_CLASS_BRIDGE) && (subclass == PCI_BRIDGE_PCI)) { 2616 val = (((uint_t)pci_config_get8(cfg_hdl, PCI_BCNF_IO_BASE_LOW) & 2617 PCI_BCNF_IO_MASK) << 8); 2618 /* 2619 * Assuming that a zero based io_range[0] implies an 2620 * invalid I/O range. Likewise for mem_range[0]. 2621 */ 2622 if (val == 0) 2623 *empty_io_range = B_TRUE; 2624 val = (((uint_t)pci_config_get16(cfg_hdl, PCI_BCNF_MEM_BASE) & 2625 PCI_BCNF_MEM_MASK) << 16); 2626 if (val == 0) 2627 *empty_mem_range = B_TRUE; 2628 } 2629 } 2630 2631 #endif /* defined(__i386) || defined(__amd64) */ 2632