xref: /illumos-gate/usr/src/uts/common/io/nxge/nxge_virtual.c (revision e3d11eee)

/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved.
 */

#include <sys/nxge/nxge_impl.h>
#include <sys/nxge/nxge_mac.h>
#include <sys/nxge/nxge_hio.h>

/*
 * Local defines for FWARC 2006/556
 */
#define	NXGE_NIU_TDMA_PROP_LEN		2
#define	NXGE_NIU_RDMA_PROP_LEN		2
#define	NXGE_NIU_0_INTR_PROP_LEN	19
#define	NXGE_NIU_1_INTR_PROP_LEN	17

/*
 * Local functions.
 */
static void nxge_get_niu_property(dev_info_t *, niu_type_t *);
static nxge_status_t nxge_get_mac_addr_properties(p_nxge_t);
static nxge_status_t nxge_use_cfg_n2niu_properties(p_nxge_t);
static void nxge_use_cfg_neptune_properties(p_nxge_t);
static void nxge_use_cfg_dma_config(p_nxge_t);
static void nxge_use_cfg_vlan_class_config(p_nxge_t);
static void nxge_use_cfg_mac_class_config(p_nxge_t);
static void nxge_use_cfg_class_config(p_nxge_t);
static void nxge_use_cfg_link_cfg(p_nxge_t);
static void nxge_set_hw_dma_config(p_nxge_t);
static void nxge_set_hw_vlan_class_config(p_nxge_t);
static void nxge_set_hw_mac_class_config(p_nxge_t);
static void nxge_set_hw_class_config(p_nxge_t);
static nxge_status_t nxge_use_default_dma_config_n2(p_nxge_t);
static void nxge_ldgv_setup(p_nxge_ldg_t *, p_nxge_ldv_t *, uint8_t,
	uint8_t, int *);
static void nxge_init_mmac(p_nxge_t, boolean_t);
static void nxge_set_rdc_intr_property(p_nxge_t);

uint32_t nxge_use_hw_property = 1;
uint32_t nxge_groups_per_port = 2;

extern uint32_t nxge_use_partition;
extern uint32_t nxge_dma_obp_props_only;

extern uint_t nxge_rx_intr(char *, char *);
extern uint_t nxge_tx_intr(char *, char *);
extern uint_t nxge_mif_intr(char *, char *);
extern uint_t nxge_mac_intr(char *, char *);
extern uint_t nxge_syserr_intr(char *, char *);
extern void *nxge_list;

#define	NXGE_SHARED_REG_SW_SIM

#ifdef NXGE_SHARED_REG_SW_SIM
uint64_t global_dev_ctrl = 0;
#endif

#define	MAX_SIBLINGS	NXGE_MAX_PORTS

extern uint32_t nxge_rbr_size;
extern uint32_t nxge_rcr_size;
extern uint32_t nxge_tx_ring_size;
extern uint32_t nxge_rbr_spare_size;

extern npi_status_t npi_mac_altaddr_disable(npi_handle_t, uint8_t, uint8_t);

static uint8_t p2_tx_fair[2] = {12, 12};
static uint8_t p2_tx_equal[2] = {12, 12};
static uint8_t p4_tx_fair[4] = {6, 6, 6, 6};
static uint8_t p4_tx_equal[4] = {6, 6, 6, 6};
static uint8_t p2_rx_fair[2] = {8, 8};
static uint8_t p2_rx_equal[2] = {8, 8};
static uint8_t p4_rx_fair[4] = {4, 4, 4, 4};
static uint8_t p4_rx_equal[4] = {4, 4, 4, 4};

static uint8_t p2_rdcgrp_fair[2] = {4, 4};
static uint8_t p2_rdcgrp_equal[2] = {4, 4};
static uint8_t p4_rdcgrp_fair[4] = {2, 2, 1, 1};
static uint8_t p4_rdcgrp_equal[4] = {2, 2, 2, 2};
static uint8_t p2_rdcgrp_cls[2] = {1, 1};
static uint8_t p4_rdcgrp_cls[4] = {1, 1, 1, 1};

static uint8_t rx_4_1G[4] = {4, 4, 4, 4};
static uint8_t rx_2_10G[2] = {8, 8};
static uint8_t rx_2_10G_2_1G[4] = {6, 6, 2, 2};
static uint8_t rx_1_10G_3_1G[4] = {10, 2, 2, 2};
static uint8_t rx_1_1G_1_10G_2_1G[4] = {2, 10, 2, 2};

static uint8_t tx_4_1G[4] = {6, 6, 6, 6};
static uint8_t tx_2_10G[2] = {12, 12};
static uint8_t tx_2_10G_2_1G[4] = {10, 10, 2, 2};
static uint8_t tx_1_10G_3_1G[4] = {12, 4, 4, 4};
static uint8_t tx_1_1G_1_10G_2_1G[4] = {4, 12, 4, 4};

typedef enum {
	DEFAULT = 0,
	EQUAL,
	FAIR,
	CUSTOM,
	CLASSIFY,
	L2_CLASSIFY,
	L3_DISTRIBUTE,
	L3_CLASSIFY,
	L3_TCAM,
	CONFIG_TOKEN_NONE
} config_token_t;

static char *token_names[] = {
	"default",
	"equal",
	"fair",
	"custom",
	"classify",
	"l2_classify",
	"l3_distribute",
	"l3_classify",
	"l3_tcam",
	"none",
};

void nxge_virint_regs_dump(p_nxge_t nxgep);

void
nxge_virint_regs_dump(p_nxge_t nxgep)
{
	npi_handle_t handle;

	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_virint_regs_dump"));
	handle = NXGE_DEV_NPI_HANDLE(nxgep);
	(void) npi_vir_dump_pio_fzc_regs_one(handle);
	(void) npi_vir_dump_ldgnum(handle);
	(void) npi_vir_dump_ldsv(handle);
	(void) npi_vir_dump_imask0(handle);
	(void) npi_vir_dump_sid(handle);
	(void) npi_mac_dump_regs(handle, nxgep->function_num);
	(void) npi_ipp_dump_regs(handle, nxgep->function_num);
	(void) npi_fflp_dump_regs(handle);
	NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_virint_regs_dump"));
}

/*
 * For now: we hard coded the DMA configurations.
 *	    and assume for one partition only.
 *
 *       OBP. Then OBP will pass this partition's
 *	 Neptune configurations to fcode to create
 *	 properties for them.
 *
 *	Since Neptune(PCI-E) and NIU (Niagara-2) has
 *	different bus interfaces, the driver needs
 *	to know which bus it is connected to.
 *  	Ravinder suggested: create a device property.
 *	In partitioning environment, we cannot
 *	use .conf file (need to check). If conf changes,
 *	need to reboot the system.
 *	The following function assumes that we will
 *	retrieve its properties from a virtualized nexus driver.
 */

nxge_status_t
nxge_cntlops(dev_info_t *dip, nxge_ctl_enum_t ctlop, void *arg, void *result)
{
	nxge_status_t status = NXGE_OK;
	int instance;
	p_nxge_t nxgep;

#ifndef NXGE_SHARED_REG_SW_SIM
	npi_handle_t handle;
	uint16_t sr16, cr16;
#endif
	instance = ddi_get_instance(dip);
	NXGE_DEBUG_MSG((NULL, VIR_CTL, "Instance %d ", instance));

	if (nxge_list == NULL) {
		NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL,
		    "nxge_cntlops: nxge_list null"));
		return (NXGE_ERROR);
	}
	nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance);
	if (nxgep == NULL) {
		NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL,
		    "nxge_cntlops: nxgep null"));
		return (NXGE_ERROR);
	}
#ifndef NXGE_SHARED_REG_SW_SIM
	handle = nxgep->npi_reg_handle;
#endif
	switch (ctlop) {
	case NXGE_CTLOPS_NIUTYPE:
		nxge_get_niu_property(dip, (niu_type_t *)result);
		return (status);

	case NXGE_CTLOPS_GET_SHARED_REG:
#ifdef NXGE_SHARED_REG_SW_SIM
		*(uint64_t *)result = global_dev_ctrl;
		return (0);
#else
		status = npi_dev_func_sr_sr_get(handle, &sr16);
		*(uint16_t *)result = sr16;
		NXGE_DEBUG_MSG((NULL, VIR_CTL,
		    "nxge_cntlops: NXGE_CTLOPS_GET_SHARED_REG"));
		return (0);
#endif

	case NXGE_CTLOPS_SET_SHARED_REG_LOCK:
#ifdef NXGE_SHARED_REG_SW_SIM
		global_dev_ctrl = *(uint64_t *)arg;
		return (0);
#else
		status = NPI_FAILURE;
		while (status != NPI_SUCCESS)
			status = npi_dev_func_sr_lock_enter(handle);

		sr16 = *(uint16_t *)arg;
		status = npi_dev_func_sr_sr_set_only(handle, &sr16);
		status = npi_dev_func_sr_lock_free(handle);
		NXGE_DEBUG_MSG((NULL, VIR_CTL,
		    "nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG"));
		return (0);
#endif

	case NXGE_CTLOPS_UPDATE_SHARED_REG:
#ifdef NXGE_SHARED_REG_SW_SIM
		global_dev_ctrl |= *(uint64_t *)arg;
		return (0);
#else
		status = NPI_FAILURE;
		while (status != NPI_SUCCESS)
			status = npi_dev_func_sr_lock_enter(handle);
		status = npi_dev_func_sr_sr_get(handle, &sr16);
		sr16 |= *(uint16_t *)arg;
		status = npi_dev_func_sr_sr_set_only(handle, &sr16);
		status = npi_dev_func_sr_lock_free(handle);
		NXGE_DEBUG_MSG((NULL, VIR_CTL,
		    "nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG"));
		return (0);
#endif

	case NXGE_CTLOPS_CLEAR_BIT_SHARED_REG_UL:
#ifdef NXGE_SHARED_REG_SW_SIM
		global_dev_ctrl |= *(uint64_t *)arg;
		return (0);
#else
		status = npi_dev_func_sr_sr_get(handle, &sr16);
		cr16 = *(uint16_t *)arg;
		sr16 &= ~cr16;
		status = npi_dev_func_sr_sr_set_only(handle, &sr16);
		NXGE_DEBUG_MSG((NULL, VIR_CTL,
		    "nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG"));
		return (0);
#endif

	case NXGE_CTLOPS_CLEAR_BIT_SHARED_REG:
#ifdef NXGE_SHARED_REG_SW_SIM
		global_dev_ctrl |= *(uint64_t *)arg;
		return (0);
#else
		status = NPI_FAILURE;
		while (status != NPI_SUCCESS)
			status = npi_dev_func_sr_lock_enter(handle);
		status = npi_dev_func_sr_sr_get(handle, &sr16);
		cr16 = *(uint16_t *)arg;
		sr16 &= ~cr16;
		status = npi_dev_func_sr_sr_set_only(handle, &sr16);
		status = npi_dev_func_sr_lock_free(handle);
		NXGE_DEBUG_MSG((NULL, VIR_CTL,
		    "nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG"));
		return (0);
#endif

	case NXGE_CTLOPS_GET_LOCK_BLOCK:
#ifdef NXGE_SHARED_REG_SW_SIM
		global_dev_ctrl |= *(uint64_t *)arg;
		return (0);
#else
		status = NPI_FAILURE;
		while (status != NPI_SUCCESS)
			status = npi_dev_func_sr_lock_enter(handle);
		NXGE_DEBUG_MSG((NULL, VIR_CTL,
		    "nxge_cntlops: NXGE_CTLOPS_GET_LOCK_BLOCK"));
		return (0);
#endif
	case NXGE_CTLOPS_GET_LOCK_TRY:
#ifdef NXGE_SHARED_REG_SW_SIM
		global_dev_ctrl |= *(uint64_t *)arg;
		return (0);
#else
		status = npi_dev_func_sr_lock_enter(handle);
		NXGE_DEBUG_MSG((NULL, VIR_CTL,
		    "nxge_cntlops: NXGE_CTLOPS_GET_LOCK_TRY"));
		if (status == NPI_SUCCESS)
			return (NXGE_OK);
		else
			return (NXGE_ERROR);
#endif
	case NXGE_CTLOPS_FREE_LOCK:
#ifdef NXGE_SHARED_REG_SW_SIM
		global_dev_ctrl |= *(uint64_t *)arg;
		return (0);
#else
		status = npi_dev_func_sr_lock_free(handle);
		NXGE_DEBUG_MSG((NULL, VIR_CTL,
		    "nxge_cntlops: NXGE_CTLOPS_GET_LOCK_FREE"));
		if (status == NPI_SUCCESS)
			return (NXGE_OK);
		else
			return (NXGE_ERROR);
#endif

	default:
		status = NXGE_ERROR;
	}

	return (status);
}

void
nxge_common_lock_get(p_nxge_t nxgep)
{
	uint32_t status = NPI_FAILURE;
	npi_handle_t handle;

#if	defined(NXGE_SHARE_REG_SW_SIM)
	return;
#endif
	handle = nxgep->npi_reg_handle;
	while (status != NPI_SUCCESS)
		status = npi_dev_func_sr_lock_enter(handle);
}

void
nxge_common_lock_free(p_nxge_t nxgep)
{
	npi_handle_t handle;

#if	defined(NXGE_SHARE_REG_SW_SIM)
	return;
#endif
	handle = nxgep->npi_reg_handle;
	(void) npi_dev_func_sr_lock_free(handle);
}


static void
nxge_get_niu_property(dev_info_t *dip, niu_type_t *niu_type)
{
	uchar_t *prop_val;
	uint_t prop_len;

	*niu_type = NIU_TYPE_NONE;
	if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 0,
	    "niu-type", (uchar_t **)&prop_val,
	    &prop_len) == DDI_PROP_SUCCESS) {
		if (strncmp("niu", (caddr_t)prop_val, (size_t)prop_len) == 0) {
			*niu_type = N2_NIU;
		}
		ddi_prop_free(prop_val);
	}
}

static config_token_t
nxge_get_config_token(char *prop)
{
	config_token_t token = DEFAULT;

	while (token < CONFIG_TOKEN_NONE) {
		if (strncmp(prop, token_names[token], 4) == 0)
			break;
		token++;
	}
	return (token);
}

/* per port */

static nxge_status_t
nxge_update_rxdma_grp_properties(p_nxge_t nxgep, config_token_t token,
	dev_info_t *s_dip[])
{
	nxge_status_t status = NXGE_OK;
	int ddi_status;
	int num_ports = nxgep->nports;
	int port, bits, j;
	uint8_t start_grp = 0, num_grps = 0;
	p_nxge_param_t param_arr;
	uint32_t grp_bitmap[MAX_SIBLINGS];
	int custom_start_grp[MAX_SIBLINGS];
	int custom_num_grp[MAX_SIBLINGS];
	uint8_t bad_config = B_FALSE;
	char *start_prop, *num_prop, *cfg_prop;

	start_grp = 0;
	param_arr = nxgep->param_arr;
	start_prop = param_arr[param_rdc_grps_start].fcode_name;
	num_prop = param_arr[param_rx_rdc_grps].fcode_name;

	switch (token) {
	case FAIR:
		cfg_prop = "fair";
		for (port = 0; port < num_ports; port++) {
			custom_num_grp[port] =
			    (num_ports == 4) ?
			    p4_rdcgrp_fair[port] :
			    p2_rdcgrp_fair[port];
			custom_start_grp[port] = start_grp;
			start_grp += custom_num_grp[port];
		}
		break;

	case EQUAL:
		cfg_prop = "equal";
		for (port = 0; port < num_ports; port++) {
			custom_num_grp[port] =
			    (num_ports == 4) ?
			    p4_rdcgrp_equal[port] :
			    p2_rdcgrp_equal[port];
			custom_start_grp[port] = start_grp;
			start_grp += custom_num_grp[port];
		}
		break;


	case CLASSIFY:
		cfg_prop = "classify";
		for (port = 0; port < num_ports; port++) {
			custom_num_grp[port] = (num_ports == 4) ?
			    p4_rdcgrp_cls[port] : p2_rdcgrp_cls[port];
			custom_start_grp[port] = start_grp;
			start_grp += custom_num_grp[port];
		}
		break;

	case CUSTOM:
		cfg_prop = "custom";
		/* See if it is good config */
		num_grps = 0;
		for (port = 0; port < num_ports; port++) {
			custom_start_grp[port] =
			    ddi_prop_get_int(DDI_DEV_T_NONE, s_dip[port],
			    DDI_PROP_DONTPASS, start_prop, -1);
			if ((custom_start_grp[port] == -1) ||
			    (custom_start_grp[port] >=
			    NXGE_MAX_RDC_GRPS)) {
				bad_config = B_TRUE;
				break;
			}
			custom_num_grp[port] = ddi_prop_get_int(
			    DDI_DEV_T_NONE,
			    s_dip[port],
			    DDI_PROP_DONTPASS,
			    num_prop, -1);

			if ((custom_num_grp[port] == -1) ||
			    (custom_num_grp[port] >
			    NXGE_MAX_RDC_GRPS) ||
			    ((custom_num_grp[port] +
			    custom_start_grp[port]) >=
			    NXGE_MAX_RDC_GRPS)) {
				bad_config = B_TRUE;
				break;
			}
			num_grps += custom_num_grp[port];
			if (num_grps > NXGE_MAX_RDC_GRPS) {
				bad_config = B_TRUE;
				break;
			}
			grp_bitmap[port] = 0;
			for (bits = 0;
			    bits < custom_num_grp[port];
			    bits++) {
				grp_bitmap[port] |=
				    (1 << (bits + custom_start_grp[port]));
			}

		}

		if (bad_config == B_FALSE) {
			/* check for overlap */
			for (port = 0; port < num_ports - 1; port++) {
				for (j = port + 1; j < num_ports; j++) {
					if (grp_bitmap[port] &
					    grp_bitmap[j]) {
						bad_config = B_TRUE;
						break;
					}
				}
				if (bad_config == B_TRUE)
					break;
			}
		}
		if (bad_config == B_TRUE) {
			/* use default config */
			for (port = 0; port < num_ports; port++) {
				custom_num_grp[port] =
				    (num_ports == 4) ?
				    p4_rx_fair[port] : p2_rx_fair[port];
				custom_start_grp[port] = start_grp;
				start_grp += custom_num_grp[port];
			}
		}
		break;

	default:
		/* use default config */
		cfg_prop = "fair";
		for (port = 0; port < num_ports; port++) {
			custom_num_grp[port] = (num_ports == 4) ?
			    p4_rx_fair[port] : p2_rx_fair[port];
			custom_start_grp[port] = start_grp;
			start_grp += custom_num_grp[port];
		}
		break;
	}

	/* Now Update the rx properties */
	for (port = 0; port < num_ports; port++) {
		ddi_status = ddi_prop_update_string(DDI_DEV_T_NONE, s_dip[port],
		    "rxdma-grp-cfg", cfg_prop);
		if (ddi_status != DDI_PROP_SUCCESS) {
			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
			    " property %s not updating",
			    cfg_prop));
			status |= NXGE_DDI_FAILED;
		}
		ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port],
		    num_prop, custom_num_grp[port]);

		if (ddi_status != DDI_PROP_SUCCESS) {
			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
			    " property %s not updating",
			    num_prop));
			status |= NXGE_DDI_FAILED;
		}
		ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port],
		    start_prop, custom_start_grp[port]);

		if (ddi_status != DDI_PROP_SUCCESS) {
			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
			    " property %s not updating",
			    start_prop));
			status |= NXGE_DDI_FAILED;
		}
	}
	if (status & NXGE_DDI_FAILED)
		status |= NXGE_ERROR;

	return (status);
}

static nxge_status_t
nxge_update_rxdma_properties(p_nxge_t nxgep, config_token_t token,
	dev_info_t *s_dip[])
{
	nxge_status_t status = NXGE_OK;
	int ddi_status;
	int num_ports = nxgep->nports;
	int port, bits, j;
	uint8_t start_rdc = 0, num_rdc = 0;
	p_nxge_param_t param_arr;
	uint32_t rdc_bitmap[MAX_SIBLINGS];
	int custom_start_rdc[MAX_SIBLINGS];
	int custom_num_rdc[MAX_SIBLINGS];
	uint8_t bad_config = B_FALSE;
	int *prop_val;
	uint_t prop_len;
	char *start_rdc_prop, *num_rdc_prop, *cfg_prop;

	start_rdc = 0;
	param_arr = nxgep->param_arr;
	start_rdc_prop = param_arr[param_rxdma_channels_begin].fcode_name;
	num_rdc_prop = param_arr[param_rxdma_channels].fcode_name;

	switch (token) {
	case FAIR:
		cfg_prop = "fair";
		for (port = 0; port < num_ports; port++) {
			custom_num_rdc[port] = (num_ports == 4) ?
			    p4_rx_fair[port] : p2_rx_fair[port];
			custom_start_rdc[port] = start_rdc;
			start_rdc += custom_num_rdc[port];
		}
		break;

	case EQUAL:
		cfg_prop = "equal";
		for (port = 0; port < num_ports; port++) {
			custom_num_rdc[port] = (num_ports == 4) ?
			    p4_rx_equal[port] :
			    p2_rx_equal[port];
			custom_start_rdc[port] = start_rdc;
			start_rdc += custom_num_rdc[port];
		}
		break;

	case CUSTOM:
		cfg_prop = "custom";
		/* See if it is good config */
		num_rdc = 0;
		for (port = 0; port < num_ports; port++) {
			ddi_status = ddi_prop_lookup_int_array(
			    DDI_DEV_T_ANY,
			    s_dip[port], 0,
			    start_rdc_prop,
			    &prop_val,
			    &prop_len);
			if (ddi_status == DDI_SUCCESS)
				custom_start_rdc[port] = *prop_val;
			else {
				NXGE_DEBUG_MSG((nxgep, CFG_CTL,
				    " %s custom start port %d"
				    " read failed ",
				    " rxdma-cfg", port));
				bad_config = B_TRUE;
				status |= NXGE_DDI_FAILED;
			}
			if ((custom_start_rdc[port] == -1) ||
			    (custom_start_rdc[port] >=
			    NXGE_MAX_RDCS)) {
				NXGE_DEBUG_MSG((nxgep, CFG_CTL,
				    " %s custom start %d"
				    " out of range %x ",
				    " rxdma-cfg",
				    port,
				    custom_start_rdc[port]));
				bad_config = B_TRUE;
				break;
			}
			ddi_status = ddi_prop_lookup_int_array(
			    DDI_DEV_T_ANY,
			    s_dip[port],
			    0,
			    num_rdc_prop,
			    &prop_val,
			    &prop_len);

			if (ddi_status == DDI_SUCCESS)
				custom_num_rdc[port] = *prop_val;
			else {
				NXGE_DEBUG_MSG((nxgep, CFG_CTL,
				    " %s custom num port %d"
				    " read failed ",
				    "rxdma-cfg", port));
				bad_config = B_TRUE;
				status |= NXGE_DDI_FAILED;
			}

			if ((custom_num_rdc[port] == -1) ||
			    (custom_num_rdc[port] >
			    NXGE_MAX_RDCS) ||
			    ((custom_num_rdc[port] +
			    custom_start_rdc[port]) >
			    NXGE_MAX_RDCS)) {
				NXGE_DEBUG_MSG((nxgep, CFG_CTL,
				    " %s custom num %d"
				    " out of range %x ",
				    " rxdma-cfg",
				    port, custom_num_rdc[port]));
				bad_config = B_TRUE;
				break;
			}
			num_rdc += custom_num_rdc[port];
			if (num_rdc > NXGE_MAX_RDCS) {
				bad_config = B_TRUE;
				break;
			}
			rdc_bitmap[port] = 0;
			for (bits = 0;
			    bits < custom_num_rdc[port]; bits++) {
				rdc_bitmap[port] |=
				    (1 << (bits + custom_start_rdc[port]));
			}
		}

		if (bad_config == B_FALSE) {
			/* check for overlap */
			for (port = 0; port < num_ports - 1; port++) {
				for (j = port + 1; j < num_ports; j++) {
					if (rdc_bitmap[port] &
					    rdc_bitmap[j]) {
						NXGE_DEBUG_MSG((nxgep,
						    CFG_CTL,
						    " rxdma-cfg"
						    " property custom"
						    " bit overlap"
						    " %d %d ",
						    port, j));
						bad_config = B_TRUE;
						break;
					}
				}
				if (bad_config == B_TRUE)
					break;
			}
		}
		if (bad_config == B_TRUE) {
			/* use default config */
			NXGE_DEBUG_MSG((nxgep, CFG_CTL,
			    " rxdma-cfg property:"
			    " bad custom config:"
			    " use default"));
			for (port = 0; port < num_ports; port++) {
				custom_num_rdc[port] =
				    (num_ports == 4) ?
				    p4_rx_fair[port] :
				    p2_rx_fair[port];
				custom_start_rdc[port] = start_rdc;
				start_rdc += custom_num_rdc[port];
			}
		}
		break;

	default:
		/* use default config */
		cfg_prop = "fair";
		for (port = 0; port < num_ports; port++) {
			custom_num_rdc[port] = (num_ports == 4) ?
			    p4_rx_fair[port] : p2_rx_fair[port];
			custom_start_rdc[port] = start_rdc;
			start_rdc += custom_num_rdc[port];
		}
		break;
	}

	/* Now Update the rx properties */
	for (port = 0; port < num_ports; port++) {
		NXGE_DEBUG_MSG((nxgep, CFG_CTL,
		    " update property rxdma-cfg with %s ", cfg_prop));
		ddi_status = ddi_prop_update_string(DDI_DEV_T_NONE, s_dip[port],
		    "rxdma-cfg", cfg_prop);
		if (ddi_status != DDI_PROP_SUCCESS) {
			NXGE_DEBUG_MSG((nxgep, CFG_CTL,
			    " property rxdma-cfg is not updating to %s",
			    cfg_prop));
			status |= NXGE_DDI_FAILED;
		}
		NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ",
		    num_rdc_prop, custom_num_rdc[port]));

		ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port],
		    num_rdc_prop, custom_num_rdc[port]);

		if (ddi_status != DDI_PROP_SUCCESS) {
			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
			    " property %s not updating with %d",
			    num_rdc_prop, custom_num_rdc[port]));
			status |= NXGE_DDI_FAILED;
		}
		NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ",
		    start_rdc_prop, custom_start_rdc[port]));
		ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port],
		    start_rdc_prop, custom_start_rdc[port]);

		if (ddi_status != DDI_PROP_SUCCESS) {
			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
			    " property %s not updating with %d ",
			    start_rdc_prop, custom_start_rdc[port]));
			status |= NXGE_DDI_FAILED;
		}
	}
	if (status & NXGE_DDI_FAILED)
		status |= NXGE_ERROR;
	return (status);
}

static nxge_status_t
nxge_update_txdma_properties(p_nxge_t nxgep, config_token_t token,
	dev_info_t *s_dip[])
{
	nxge_status_t status = NXGE_OK;
	int ddi_status = DDI_SUCCESS;
	int num_ports = nxgep->nports;
	int port, bits, j;
	uint8_t  start_tdc, num_tdc = 0;
	p_nxge_param_t param_arr;
	uint32_t tdc_bitmap[MAX_SIBLINGS];
	int custom_start_tdc[MAX_SIBLINGS];
	int custom_num_tdc[MAX_SIBLINGS];
	uint8_t bad_config = B_FALSE;
	int *prop_val;
	uint_t prop_len;
	char *start_tdc_prop, *num_tdc_prop, *cfg_prop;

	start_tdc = 0;
	param_arr = nxgep->param_arr;
	start_tdc_prop = param_arr[param_txdma_channels_begin].fcode_name;
	num_tdc_prop = param_arr[param_txdma_channels].fcode_name;

	switch (token) {
	case FAIR:
		cfg_prop = "fair";
		for (port = 0; port < num_ports; port++) {
			custom_num_tdc[port] = (num_ports == 4) ?
			    p4_tx_fair[port] : p2_tx_fair[port];
			custom_start_tdc[port] = start_tdc;
			start_tdc += custom_num_tdc[port];
		}
		break;

	case EQUAL:
		cfg_prop = "equal";
		for (port = 0; port < num_ports; port++) {
			custom_num_tdc[port] = (num_ports == 4) ?
			    p4_tx_equal[port] : p2_tx_equal[port];
			custom_start_tdc[port] = start_tdc;
			start_tdc += custom_num_tdc[port];
		}
		break;

	case CUSTOM:
		cfg_prop = "custom";
		/* See if it is good config */
		num_tdc = 0;
		for (port = 0; port < num_ports; port++) {
			ddi_status = ddi_prop_lookup_int_array(
			    DDI_DEV_T_ANY, s_dip[port], 0, start_tdc_prop,
			    &prop_val, &prop_len);
			if (ddi_status == DDI_SUCCESS)
				custom_start_tdc[port] = *prop_val;
			else {
				NXGE_DEBUG_MSG((nxgep, CFG_CTL,
				    " %s custom start port %d"
				    " read failed ", " txdma-cfg", port));
				bad_config = B_TRUE;
				status |= NXGE_DDI_FAILED;
			}

			if ((custom_start_tdc[port] == -1) ||
			    (custom_start_tdc[port] >=
			    NXGE_MAX_RDCS)) {
				NXGE_DEBUG_MSG((nxgep, CFG_CTL,
				    " %s custom start %d"
				    " out of range %x ", " txdma-cfg",
				    port, custom_start_tdc[port]));
				bad_config = B_TRUE;
				break;
			}

			ddi_status = ddi_prop_lookup_int_array(
			    DDI_DEV_T_ANY, s_dip[port], 0, num_tdc_prop,
			    &prop_val, &prop_len);
			if (ddi_status == DDI_SUCCESS)
				custom_num_tdc[port] = *prop_val;
			else {
				NXGE_DEBUG_MSG((nxgep, CFG_CTL,
				    " %s custom num port %d"
				    " read failed ", " txdma-cfg", port));
				bad_config = B_TRUE;
				status |= NXGE_DDI_FAILED;
			}

			if ((custom_num_tdc[port] == -1) ||
			    (custom_num_tdc[port] >
			    NXGE_MAX_TDCS) ||
			    ((custom_num_tdc[port] +
			    custom_start_tdc[port]) >
			    NXGE_MAX_TDCS)) {
				NXGE_DEBUG_MSG((nxgep, CFG_CTL,
				    " %s custom num %d"
				    " out of range %x ", " rxdma-cfg",
				    port, custom_num_tdc[port]));
				bad_config = B_TRUE;
				break;
			}
			num_tdc += custom_num_tdc[port];
			if (num_tdc > NXGE_MAX_TDCS) {
				bad_config = B_TRUE;
				break;
			}
			tdc_bitmap[port] = 0;
			for (bits = 0;
			    bits < custom_num_tdc[port]; bits++) {
				tdc_bitmap[port] |=
				    (1 <<
				    (bits + custom_start_tdc[port]));
			}

		}

		if (bad_config == B_FALSE) {
			/* check for overlap */
			for (port = 0; port < num_ports - 1; port++) {
				for (j = port + 1; j < num_ports; j++) {
					if (tdc_bitmap[port] &
					    tdc_bitmap[j]) {
						NXGE_DEBUG_MSG((nxgep, CFG_CTL,
						    " rxdma-cfg"
						    " property custom"
						    " bit overlap"
						    " %d %d ",
						    port, j));
						bad_config = B_TRUE;
						break;
					}
				}
				if (bad_config == B_TRUE)
					break;
			}
		}
		if (bad_config == B_TRUE) {
			/* use default config */
			NXGE_DEBUG_MSG((nxgep, CFG_CTL,
			    " txdma-cfg property:"
			    " bad custom config:" " use default"));

			for (port = 0; port < num_ports; port++) {
				custom_num_tdc[port] = (num_ports == 4) ?
				    p4_tx_fair[port] : p2_tx_fair[port];
				custom_start_tdc[port] = start_tdc;
				start_tdc += custom_num_tdc[port];
			}
		}
		break;

	default:
		/* use default config */
		cfg_prop = "fair";
		for (port = 0; port < num_ports; port++) {
			custom_num_tdc[port] = (num_ports == 4) ?
			    p4_tx_fair[port] : p2_tx_fair[port];
			custom_start_tdc[port] = start_tdc;
			start_tdc += custom_num_tdc[port];
		}
		break;
	}

	/* Now Update the tx properties */
	for (port = 0; port < num_ports; port++) {
		NXGE_DEBUG_MSG((nxgep, CFG_CTL,
		    " update property txdma-cfg with %s ", cfg_prop));
		ddi_status = ddi_prop_update_string(DDI_DEV_T_NONE, s_dip[port],
		    "txdma-cfg", cfg_prop);
		if (ddi_status != DDI_PROP_SUCCESS) {
			NXGE_DEBUG_MSG((nxgep, CFG_CTL,
			    " property txdma-cfg is not updating to %s",
			    cfg_prop));
			status |= NXGE_DDI_FAILED;
		}
		NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ",
		    num_tdc_prop, custom_num_tdc[port]));

		ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port],
		    num_tdc_prop, custom_num_tdc[port]);

		if (ddi_status != DDI_PROP_SUCCESS) {
			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
			    " property %s not updating with %d",
			    num_tdc_prop,
			    custom_num_tdc[port]));
			status |= NXGE_DDI_FAILED;
		}

		NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ",
		    start_tdc_prop, custom_start_tdc[port]));

		ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port],
		    start_tdc_prop, custom_start_tdc[port]);
		if (ddi_status != DDI_PROP_SUCCESS) {
			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
			    " property %s not updating with %d ",
			    start_tdc_prop, custom_start_tdc[port]));
			status |= NXGE_DDI_FAILED;
		}
	}
	if (status & NXGE_DDI_FAILED)
		status |= NXGE_ERROR;
	return (status);
}

static nxge_status_t
nxge_update_cfg_properties(p_nxge_t nxgep, uint32_t flags,
	config_token_t token, dev_info_t *s_dip[])
{
	nxge_status_t status = NXGE_OK;

	switch (flags) {
	case COMMON_TXDMA_CFG:
		if (nxge_dma_obp_props_only == 0)
			status = nxge_update_txdma_properties(nxgep,
			    token, s_dip);
		break;
	case COMMON_RXDMA_CFG:
		if (nxge_dma_obp_props_only == 0)
			status = nxge_update_rxdma_properties(nxgep,
			    token, s_dip);

		break;
	case COMMON_RXDMA_GRP_CFG:
		status = nxge_update_rxdma_grp_properties(nxgep,
		    token, s_dip);
		break;
	default:
		return (NXGE_ERROR);
	}
	return (status);
}

/*
 * verify consistence.
 * (May require publishing the properties on all the ports.
 *
 * What if properties are published on function 0 device only?
 *
 *
 * rxdma-cfg, txdma-cfg, rxdma-grp-cfg (required )
 * What about class configs?
 *
 * If consistent, update the property on all the siblings.
 * set  a flag on hardware shared register
 * The rest of the siblings will check the flag
 * if the flag is set, they will use the updated property
 * without doing any validation.
 */

nxge_status_t
nxge_cfg_verify_set_classify_prop(p_nxge_t nxgep, char *prop,
	uint64_t known_cfg, uint32_t override, dev_info_t *c_dip[])
{
	nxge_status_t status = NXGE_OK;
	int ddi_status = DDI_SUCCESS;
	int i = 0, found = 0, update_prop = B_TRUE;
	int *cfg_val;
	uint_t new_value, cfg_value[MAX_SIBLINGS];
	uint_t prop_len;
	uint_t known_cfg_value;

	new_value = 0;
	known_cfg_value = (uint_t)known_cfg;

	if (override == B_TRUE) {
		new_value = known_cfg_value;
		for (i = 0; i < nxgep->nports; i++) {
			ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE,
			    c_dip[i], prop, new_value);
#ifdef NXGE_DEBUG_ERROR
			if (ddi_status != DDI_PROP_SUCCESS)
				NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
				    " property %s failed update ", prop));
#endif
		}
		if (ddi_status != DDI_PROP_SUCCESS)
			return (NXGE_ERROR | NXGE_DDI_FAILED);
	}
	for (i = 0; i < nxgep->nports; i++) {
		cfg_value[i] = known_cfg_value;
		if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, c_dip[i], 0,
		    prop, &cfg_val,
		    &prop_len) == DDI_PROP_SUCCESS) {
			cfg_value[i] = *cfg_val;
			ddi_prop_free(cfg_val);
			found++;
		}
	}

	if (found != i) {
		NXGE_DEBUG_MSG((nxgep, CFG_CTL,
		    " property %s not specified on all ports", prop));
		if (found == 0) {
			/* not specified: Use default */
			NXGE_DEBUG_MSG((nxgep, CFG_CTL,
			    " property %s not specified on any port:"
			    " Using default", prop));
			new_value = known_cfg_value;
		} else {
			/* specified on some */
			NXGE_DEBUG_MSG((nxgep, CFG_CTL,
			    " property %s not specified"
			    " on some ports: Using default", prop));
			/* ? use p0 value instead ? */
			new_value = known_cfg_value;
		}
	} else {
		/* check type and consistence */
		/* found on all devices */
		for (i = 1; i < found; i++) {
			if (cfg_value[i] != cfg_value[i - 1]) {
				NXGE_DEBUG_MSG((nxgep, CFG_CTL,
				    " property %s inconsistent:"
				    " Using default", prop));
				new_value = known_cfg_value;
				break;
			}
			/*
			 * Found on all the ports and consistent. Nothing to
			 * do.
			 */
			update_prop = B_FALSE;
		}
	}

	if (update_prop == B_TRUE) {
		for (i = 0; i < nxgep->nports; i++) {
			ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE,
			    c_dip[i], prop, new_value);
#ifdef NXGE_DEBUG_ERROR
			if (ddi_status != DDI_SUCCESS)
				NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
				    " property %s not updating with %d"
				    " Using default",
				    prop, new_value));
#endif
			if (ddi_status != DDI_PROP_SUCCESS)
				status |= NXGE_DDI_FAILED;
		}
	}
	if (status & NXGE_DDI_FAILED)
		status |= NXGE_ERROR;

	return (status);
}

static uint64_t
nxge_class_get_known_cfg(p_nxge_t nxgep, int class_prop, int rx_quick_cfg)
{
	int start_prop;
	uint64_t cfg_value;
	p_nxge_param_t param_arr;

	param_arr = nxgep->param_arr;
	cfg_value = param_arr[class_prop].value;
	start_prop = param_h1_init_value;

	/* update the properties per quick config */
	switch (rx_quick_cfg) {
	case CFG_L3_WEB:
	case CFG_L3_DISTRIBUTE:
		cfg_value = nxge_classify_get_cfg_value(nxgep,
		    rx_quick_cfg, class_prop - start_prop);
		break;
	default:
		cfg_value = param_arr[class_prop].value;
		break;
	}
	return (cfg_value);
}

static nxge_status_t
nxge_cfg_verify_set_classify(p_nxge_t nxgep, dev_info_t *c_dip[])
{
	nxge_status_t status = NXGE_OK;
	int rx_quick_cfg, class_prop, start_prop, end_prop;
	char *prop_name;
	int override = B_TRUE;
	uint64_t cfg_value;
	p_nxge_param_t param_arr;

	param_arr = nxgep->param_arr;
	rx_quick_cfg = param_arr[param_rx_quick_cfg].value;
	start_prop = param_h1_init_value;
	end_prop = param_class_opt_ipv6_sctp;

	/* update the properties per quick config */
	if (rx_quick_cfg == CFG_NOT_SPECIFIED)
		override = B_FALSE;

	/*
	 * these parameter affect the classification outcome.
	 * these parameters are used to configure the Flow key and
	 * the TCAM key for each of the IP classes.
	 * Included here are also the H1 and H2 initial values
	 * which affect the distribution as well as final hash value
	 * (hence the offset into RDC table and FCRAM bucket location)
	 *
	 */
	for (class_prop = start_prop; class_prop <= end_prop; class_prop++) {
		prop_name = param_arr[class_prop].fcode_name;
		cfg_value = nxge_class_get_known_cfg(nxgep,
		    class_prop, rx_quick_cfg);
		status = nxge_cfg_verify_set_classify_prop(nxgep, prop_name,
		    cfg_value, override, c_dip);
	}

	/*
	 * these properties do not affect the actual classification outcome.
	 * used to enable/disable or tune the fflp hardware
	 *
	 * fcram_access_ratio, tcam_access_ratio, tcam_enable, llc_snap_enable
	 *
	 */
	override = B_FALSE;
	for (class_prop = param_fcram_access_ratio;
	    class_prop <= param_llc_snap_enable; class_prop++) {
		prop_name = param_arr[class_prop].fcode_name;
		cfg_value = param_arr[class_prop].value;
		status = nxge_cfg_verify_set_classify_prop(nxgep, prop_name,
		    cfg_value, override, c_dip);
	}

	return (status);
}

nxge_status_t
nxge_cfg_verify_set(p_nxge_t nxgep, uint32_t flag)
{
	nxge_status_t status = NXGE_OK;
	int i = 0, found = 0;
	int num_siblings;
	dev_info_t *c_dip[MAX_SIBLINGS + 1];
	char *prop_val[MAX_SIBLINGS];
	config_token_t c_token[MAX_SIBLINGS];
	char *prop;

	if (nxge_dma_obp_props_only)
		return (NXGE_OK);

	num_siblings = 0;
	c_dip[num_siblings] = ddi_get_child(nxgep->p_dip);
	while (c_dip[num_siblings]) {
		c_dip[num_siblings + 1] =
		    ddi_get_next_sibling(c_dip[num_siblings]);
		num_siblings++;
	}

	switch (flag) {
	case COMMON_TXDMA_CFG:
		prop = "txdma-cfg";
		break;
	case COMMON_RXDMA_CFG:
		prop = "rxdma-cfg";
		break;
	case COMMON_RXDMA_GRP_CFG:
		prop = "rxdma-grp-cfg";
		break;
	case COMMON_CLASS_CFG:
		status = nxge_cfg_verify_set_classify(nxgep, c_dip);
		return (status);
	default:
		return (NXGE_ERROR);
	}

	i = 0;
	while (i < num_siblings) {
		if (ddi_prop_lookup_string(DDI_DEV_T_ANY, c_dip[i], 0, prop,
		    (char **)&prop_val[i]) == DDI_PROP_SUCCESS) {
			c_token[i] = nxge_get_config_token(prop_val[i]);
			ddi_prop_free(prop_val[i]);
			found++;
		} else
			c_token[i] = CONFIG_TOKEN_NONE;
		i++;
	}

	if (found != i) {
		if (found == 0) {
			/* not specified: Use default */
			NXGE_DEBUG_MSG((nxgep, CFG_CTL,
			    " property %s not specified on any port:"
			    " Using default", prop));

			status = nxge_update_cfg_properties(nxgep,
			    flag, FAIR, c_dip);
			return (status);
		} else {
			/*
			 * if  the convention is to use function 0 device then
			 * populate the other devices with this configuration.
			 *
			 * The other alternative is to use the default config.
			 */
			/* not specified: Use default */
			NXGE_DEBUG_MSG((nxgep, CFG_CTL,
			    " property %s not specified on some ports:"
			    " Using default", prop));
			status = nxge_update_cfg_properties(nxgep,
			    flag, FAIR, c_dip);
			return (status);
		}
	}

	/* check type and consistence */
	/* found on all devices */
	for (i = 1; i < found; i++) {
		if (c_token[i] != c_token[i - 1]) {
			NXGE_DEBUG_MSG((nxgep, CFG_CTL,
			    " property %s inconsistent:"
			    " Using default", prop));
			status = nxge_update_cfg_properties(nxgep,
			    flag, FAIR, c_dip);
			return (status);
		}
	}

	/*
	 * Found on all the ports check if it is custom configuration. if
	 * custom, then verify consistence
	 *
	 * finally create soft properties
	 */
	status = nxge_update_cfg_properties(nxgep, flag, c_token[0], c_dip);
	return (status);
}

nxge_status_t
nxge_cfg_verify_set_quick_config(p_nxge_t nxgep)
{
	nxge_status_t status = NXGE_OK;
	int ddi_status = DDI_SUCCESS;
	char *prop_val;
	char *rx_prop;
	char *prop;
	uint32_t cfg_value = CFG_NOT_SPECIFIED;
	p_nxge_param_t param_arr;

	param_arr = nxgep->param_arr;
	rx_prop = param_arr[param_rx_quick_cfg].fcode_name;

	prop = "rx-quick-cfg";

	/*
	 * good value are
	 *
	 * "web-server" "generic-server" "l3-classify" "flow-classify"
	 */
	if (ddi_prop_lookup_string(DDI_DEV_T_ANY, nxgep->dip, 0,
	    prop, (char **)&prop_val) != DDI_PROP_SUCCESS) {
		NXGE_DEBUG_MSG((nxgep, VPD_CTL,
		    " property %s not specified: using default ", prop));
		cfg_value = CFG_NOT_SPECIFIED;
	} else {
		cfg_value = CFG_L3_DISTRIBUTE;
		if (strncmp("web-server", (caddr_t)prop_val, 8) == 0) {
			cfg_value = CFG_L3_WEB;
			NXGE_DEBUG_MSG((nxgep, CFG_CTL,
			    " %s: web server ", prop));
		}
		if (strncmp("generic-server", (caddr_t)prop_val, 8) == 0) {
			cfg_value = CFG_L3_DISTRIBUTE;
			NXGE_DEBUG_MSG((nxgep, CFG_CTL,
			    " %s: distribute ", prop));
		}
		/* more */
		ddi_prop_free(prop_val);
	}

	ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
	    rx_prop, cfg_value);
	if (ddi_status != DDI_PROP_SUCCESS)
		status |= NXGE_DDI_FAILED;

	/* now handle specified cases: */
	if (status & NXGE_DDI_FAILED)
		status |= NXGE_ERROR;
	return (status);
}

/*
 * Device properties adv-autoneg-cap etc are defined by FWARC
 * http://sac.sfbay/FWARC/2002/345/20020610_asif.haswarey
 */
static void
nxge_use_cfg_link_cfg(p_nxge_t nxgep)
{
	int *prop_val;
	uint_t prop_len;
	dev_info_t *dip;
	int speed;
	int duplex;
	int adv_autoneg_cap;
	int adv_10gfdx_cap;
	int adv_10ghdx_cap;
	int adv_1000fdx_cap;
	int adv_1000hdx_cap;
	int adv_100fdx_cap;
	int adv_100hdx_cap;
	int adv_10fdx_cap;
	int adv_10hdx_cap;
	int status = DDI_SUCCESS;

	dip = nxgep->dip;

	/*
	 * first find out the card type and the supported link speeds and
	 * features
	 */
	/* add code for card type */
	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-autoneg-cap",
	    &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
		ddi_prop_free(prop_val);
		return;
	}

	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-10gfdx-cap",
	    &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
		ddi_prop_free(prop_val);
		return;
	}

	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-1000hdx-cap",
	    &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
		ddi_prop_free(prop_val);
		return;
	}

	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-1000fdx-cap",
	    &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
		ddi_prop_free(prop_val);
		return;
	}

	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-100fdx-cap",
	    &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
		ddi_prop_free(prop_val);
		return;
	}