1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/nxge/nxge_impl.h> 29 #include <sys/nxge/nxge_mac.h> 30 31 static void nxge_get_niu_property(dev_info_t *, niu_type_t *); 32 static nxge_status_t nxge_get_mac_addr_properties(p_nxge_t); 33 static nxge_status_t nxge_use_cfg_n2niu_properties(p_nxge_t); 34 static void nxge_use_cfg_neptune_properties(p_nxge_t); 35 static void nxge_use_cfg_dma_config(p_nxge_t); 36 static void nxge_use_cfg_vlan_class_config(p_nxge_t); 37 static void nxge_use_cfg_mac_class_config(p_nxge_t); 38 static void nxge_use_cfg_class_config(p_nxge_t); 39 static void nxge_use_cfg_link_cfg(p_nxge_t); 40 static void nxge_setup_hw_pciconfig(p_nxge_t); 41 static void nxge_setup_hw_vpd_rom_mac(p_nxge_t); 42 static void nxge_set_hw_dma_config(p_nxge_t); 43 static void nxge_set_hw_vlan_class_config(p_nxge_t); 44 static void nxge_set_hw_mac_class_config(p_nxge_t); 45 static void nxge_set_hw_class_config(p_nxge_t); 46 47 static nxge_status_t nxge_use_default_dma_config_n2(p_nxge_t); 48 49 static void nxge_ldgv_setup(p_nxge_ldg_t *ldgp, p_nxge_ldv_t *, uint8_t, 50 uint8_t, int *); 51 static void nxge_init_mmac(p_nxge_t); 52 53 uint32_t nxge_use_hw_property = 1; 54 uint32_t nxge_groups_per_port = 2; 55 56 extern uint32_t nxge_use_partition; 57 extern uint32_t nxge_dma_obp_props_only; 58 59 extern uint16_t nxge_rcr_timeout; 60 extern uint16_t nxge_rcr_threshold; 61 62 extern uint_t nxge_rx_intr(void *, void *); 63 extern uint_t nxge_tx_intr(void *, void *); 64 extern uint_t nxge_mif_intr(void *, void *); 65 extern uint_t nxge_mac_intr(void *, void *); 66 extern uint_t nxge_syserr_intr(void *, void *); 67 extern void *nxge_list; 68 69 #define NXGE_SHARED_REG_SW_SIM 70 71 #ifdef NXGE_SHARED_REG_SW_SIM 72 uint64_t global_dev_ctrl = 0; 73 #endif 74 75 #define MAX_SIBLINGS NXGE_MAX_PORTS 76 77 78 extern uint32_t nxge_rbr_size; 79 extern uint32_t nxge_rcr_size; 80 extern uint32_t nxge_tx_ring_size; 81 extern uint32_t nxge_rbr_spare_size; 82 83 extern npi_status_t npi_mac_altaddr_disable(npi_handle_t, uint8_t, uint8_t); 84 85 static uint8_t p2_tx_fair[2] = {12, 12}; 86 static uint8_t p2_tx_equal[2] = {12, 12}; 87 static uint8_t p4_tx_fair[4] = {6, 6, 6, 6}; 88 static uint8_t p4_tx_equal[4] = {6, 6, 6, 6}; 89 static uint8_t p2_rx_fair[2] = {8, 8}; 90 static uint8_t p2_rx_equal[2] = {8, 8}; 91 92 static uint8_t p4_rx_fair[4] = {4, 4, 4, 4}; 93 static uint8_t p4_rx_equal[4] = {4, 4, 4, 4}; 94 95 static uint8_t p2_rdcgrp_fair[2] = {4, 4}; 96 static uint8_t p2_rdcgrp_equal[2] = {4, 4}; 97 static uint8_t p4_rdcgrp_fair[4] = {2, 2, 1, 1}; 98 static uint8_t p4_rdcgrp_equal[4] = {2, 2, 2, 2}; 99 static uint8_t p2_rdcgrp_cls[2] = {1, 1}; 100 static uint8_t p4_rdcgrp_cls[4] = {1, 1, 1, 1}; 101 102 typedef enum { 103 DEFAULT = 0, 104 EQUAL, 105 FAIR, 106 CUSTOM, 107 CLASSIFY, 108 L2_CLASSIFY, 109 L3_DISTRIBUTE, 110 L3_CLASSIFY, 111 L3_TCAM, 112 CONFIG_TOKEN_NONE 113 } config_token_t; 114 115 static char *token_names[] = { 116 "default", 117 "equal", 118 "fair", 119 "custom", 120 "classify", 121 "l2_classify", 122 "l3_distribute", 123 "l3_classify", 124 "l3_tcam", 125 "none", 126 }; 127 128 void nxge_virint_regs_dump(p_nxge_t nxgep); 129 130 void 131 nxge_virint_regs_dump(p_nxge_t nxgep) 132 { 133 npi_handle_t handle; 134 135 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_virint_regs_dump")); 136 handle = NXGE_DEV_NPI_HANDLE(nxgep); 137 (void) npi_vir_dump_pio_fzc_regs_one(handle); 138 (void) npi_vir_dump_ldgnum(handle); 139 (void) npi_vir_dump_ldsv(handle); 140 (void) npi_vir_dump_imask0(handle); 141 (void) npi_vir_dump_sid(handle); 142 (void) npi_mac_dump_regs(handle, nxgep->function_num); 143 (void) npi_ipp_dump_regs(handle, nxgep->function_num); 144 (void) npi_fflp_dump_regs(handle); 145 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_virint_regs_dump")); 146 } 147 148 /* 149 * For now: we hard coded the DMA configurations. 150 * and assume for one partition only. 151 * 152 * OBP. Then OBP will pass this partition's 153 * Neptune configurations to fcode to create 154 * properties for them. 155 * 156 * Since Neptune(PCI-E) and NIU (Niagara-2) has 157 * different bus interfaces, the driver needs 158 * to know which bus it is connected to. 159 * Ravinder suggested: create a device property. 160 * In partitioning environment, we cannot 161 * use .conf file (need to check). If conf changes, 162 * need to reboot the system. 163 * The following function assumes that we will 164 * retrieve its properties from a virtualized nexus driver. 165 */ 166 167 /*ARGSUSED*/ 168 nxge_status_t 169 nxge_cntlops(dev_info_t *dip, nxge_ctl_enum_t ctlop, void *arg, void *result) 170 { 171 nxge_status_t status = NXGE_OK; 172 int instance; 173 p_nxge_t nxgep; 174 #ifndef NXGE_SHARED_REG_SW_SIM 175 npi_handle_t handle; 176 uint16_t sr16, cr16; 177 #endif 178 instance = ddi_get_instance(dip); 179 NXGE_DEBUG_MSG((NULL, VIR_CTL, 180 "Instance %d ", 181 instance)); 182 if (nxge_list == NULL) { 183 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 184 "nxge_cntlops: nxge_list null")); 185 return (NXGE_ERROR); 186 } 187 nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance); 188 if (nxgep == NULL) { 189 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 190 "nxge_cntlops: nxgep null")); 191 return (NXGE_ERROR); 192 } 193 #ifndef NXGE_SHARED_REG_SW_SIM 194 handle = nxgep->npi_reg_handle; 195 #endif 196 switch (ctlop) { 197 case NXGE_CTLOPS_NIUTYPE: 198 nxge_get_niu_property(dip, (niu_type_t *)result); 199 return (status); 200 case NXGE_CTLOPS_GET_SHARED_REG: 201 #ifdef NXGE_SHARED_REG_SW_SIM 202 *(uint64_t *)result = global_dev_ctrl; 203 return (0); 204 #else 205 status = npi_dev_func_sr_sr_get(handle, &sr16); 206 *(uint16_t *)result = sr16; 207 NXGE_DEBUG_MSG((NULL, VIR_CTL, 208 "nxge_cntlops: NXGE_CTLOPS_GET_SHARED_REG")); 209 return (0); 210 #endif 211 212 case NXGE_CTLOPS_SET_SHARED_REG_LOCK: 213 #ifdef NXGE_SHARED_REG_SW_SIM 214 global_dev_ctrl = *(uint64_t *)arg; 215 return (0); 216 #else 217 status = NPI_FAILURE; 218 while (status != NPI_SUCCESS) 219 status = npi_dev_func_sr_lock_enter(handle); 220 221 sr16 = *(uint16_t *)arg; 222 status = npi_dev_func_sr_sr_set_only(handle, &sr16); 223 status = npi_dev_func_sr_lock_free(handle); 224 NXGE_DEBUG_MSG((NULL, VIR_CTL, 225 "nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG")); 226 return (0); 227 #endif 228 229 case NXGE_CTLOPS_UPDATE_SHARED_REG: 230 #ifdef NXGE_SHARED_REG_SW_SIM 231 global_dev_ctrl |= *(uint64_t *)arg; 232 return (0); 233 #else 234 status = NPI_FAILURE; 235 while (status != NPI_SUCCESS) 236 status = npi_dev_func_sr_lock_enter(handle); 237 status = npi_dev_func_sr_sr_get(handle, &sr16); 238 sr16 |= *(uint16_t *)arg; 239 status = npi_dev_func_sr_sr_set_only(handle, &sr16); 240 status = npi_dev_func_sr_lock_free(handle); 241 NXGE_DEBUG_MSG((NULL, VIR_CTL, 242 "nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG")); 243 return (0); 244 245 #endif 246 247 case NXGE_CTLOPS_CLEAR_BIT_SHARED_REG_UL: 248 #ifdef NXGE_SHARED_REG_SW_SIM 249 global_dev_ctrl |= *(uint64_t *)arg; 250 return (0); 251 #else 252 status = npi_dev_func_sr_sr_get(handle, &sr16); 253 cr16 = *(uint16_t *)arg; 254 sr16 &= ~cr16; 255 status = npi_dev_func_sr_sr_set_only(handle, &sr16); 256 NXGE_DEBUG_MSG((NULL, VIR_CTL, 257 "nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG")); 258 return (0); 259 #endif 260 261 case NXGE_CTLOPS_CLEAR_BIT_SHARED_REG: 262 #ifdef NXGE_SHARED_REG_SW_SIM 263 global_dev_ctrl |= *(uint64_t *)arg; 264 return (0); 265 #else 266 status = NPI_FAILURE; 267 while (status != NPI_SUCCESS) 268 status = npi_dev_func_sr_lock_enter(handle); 269 status = npi_dev_func_sr_sr_get(handle, &sr16); 270 cr16 = *(uint16_t *)arg; 271 sr16 &= ~cr16; 272 status = npi_dev_func_sr_sr_set_only(handle, &sr16); 273 status = npi_dev_func_sr_lock_free(handle); 274 NXGE_DEBUG_MSG((NULL, VIR_CTL, 275 "nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG")); 276 return (0); 277 #endif 278 279 case NXGE_CTLOPS_GET_LOCK_BLOCK: 280 #ifdef NXGE_SHARED_REG_SW_SIM 281 global_dev_ctrl |= *(uint64_t *)arg; 282 return (0); 283 #else 284 status = NPI_FAILURE; 285 while (status != NPI_SUCCESS) 286 status = npi_dev_func_sr_lock_enter(handle); 287 NXGE_DEBUG_MSG((NULL, VIR_CTL, 288 "nxge_cntlops: NXGE_CTLOPS_GET_LOCK_BLOCK")); 289 return (0); 290 #endif 291 case NXGE_CTLOPS_GET_LOCK_TRY: 292 #ifdef NXGE_SHARED_REG_SW_SIM 293 global_dev_ctrl |= *(uint64_t *)arg; 294 return (0); 295 #else 296 status = npi_dev_func_sr_lock_enter(handle); 297 NXGE_DEBUG_MSG((NULL, VIR_CTL, 298 "nxge_cntlops: NXGE_CTLOPS_GET_LOCK_TRY")); 299 if (status == NPI_SUCCESS) 300 return (NXGE_OK); 301 else 302 return (NXGE_ERROR); 303 #endif 304 case NXGE_CTLOPS_FREE_LOCK: 305 #ifdef NXGE_SHARED_REG_SW_SIM 306 global_dev_ctrl |= *(uint64_t *)arg; 307 return (0); 308 #else 309 status = npi_dev_func_sr_lock_free(handle); 310 NXGE_DEBUG_MSG((NULL, VIR_CTL, 311 "nxge_cntlops: NXGE_CTLOPS_GET_LOCK_FREE")); 312 if (status == NPI_SUCCESS) 313 return (NXGE_OK); 314 else 315 return (NXGE_ERROR); 316 #endif 317 318 default: 319 status = NXGE_ERROR; 320 } 321 322 return (status); 323 } 324 325 void 326 nxge_common_lock_get(p_nxge_t nxgep) 327 { 328 uint32_t status = NPI_FAILURE; 329 npi_handle_t handle; 330 331 #if defined(NXGE_SHARE_REG_SW_SIM) 332 return; 333 #endif 334 handle = nxgep->npi_reg_handle; 335 while (status != NPI_SUCCESS) 336 status = npi_dev_func_sr_lock_enter(handle); 337 338 } 339 340 341 void 342 nxge_common_lock_free(p_nxge_t nxgep) 343 { 344 npi_handle_t handle; 345 #if defined(NXGE_SHARE_REG_SW_SIM) 346 return; 347 #endif 348 handle = nxgep->npi_reg_handle; 349 (void) npi_dev_func_sr_lock_free(handle); 350 } 351 352 static void 353 nxge_get_niu_property(dev_info_t *dip, niu_type_t *niu_type) 354 { 355 uchar_t *prop_val; 356 uint_t prop_len; 357 358 *niu_type = NEPTUNE; 359 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 0, 360 "niu-type", (uchar_t **)&prop_val, &prop_len) == 361 DDI_PROP_SUCCESS) { 362 if (strncmp("niu", (caddr_t)prop_val, (size_t)prop_len) == 0) { 363 *niu_type = N2_NIU; 364 } 365 ddi_prop_free(prop_val); 366 } 367 } 368 369 static config_token_t 370 nxge_get_config_token(char *prop) 371 { 372 config_token_t token = DEFAULT; 373 while (token < CONFIG_TOKEN_NONE) { 374 if (strncmp(prop, token_names[token], 4) == 0) 375 break; 376 token++; 377 } 378 return (token); 379 } 380 381 382 /* per port */ 383 384 static nxge_status_t 385 nxge_update_rxdma_grp_properties(p_nxge_t nxgep, config_token_t token, 386 dev_info_t *s_dip[]) 387 { 388 nxge_status_t status = NXGE_OK; 389 int ddi_status; 390 int num_ports = nxgep->nports; 391 int port, bits, j; 392 uint8_t start_grp = 0, num_grps = 0; 393 p_nxge_param_t param_arr; 394 uint32_t grp_bitmap[MAX_SIBLINGS]; 395 int custom_start_grp[MAX_SIBLINGS]; 396 int custom_num_grp[MAX_SIBLINGS]; 397 uint8_t bad_config = B_FALSE; 398 399 char *start_prop, *num_prop, *cfg_prop; 400 401 start_grp = 0; 402 param_arr = nxgep->param_arr; 403 404 start_prop = param_arr[param_rdc_grps_start].fcode_name; 405 num_prop = param_arr[param_rx_rdc_grps].fcode_name; 406 407 switch (token) { 408 case FAIR: 409 cfg_prop = "fair"; 410 for (port = 0; port < num_ports; port++) { 411 custom_num_grp[port] = 412 (num_ports == 4) ? 413 p4_rdcgrp_fair[port] : 414 p2_rdcgrp_fair[port]; 415 custom_start_grp[port] = start_grp; 416 start_grp += custom_num_grp[port]; 417 } 418 419 break; 420 421 case EQUAL: 422 cfg_prop = "equal"; 423 for (port = 0; port < num_ports; port++) { 424 custom_num_grp[port] = 425 (num_ports == 4) ? 426 p4_rdcgrp_equal[port] : 427 p2_rdcgrp_equal[port]; 428 custom_start_grp[port] = start_grp; 429 start_grp += custom_num_grp[port]; 430 } 431 432 break; 433 434 435 case CLASSIFY: 436 cfg_prop = "classify"; 437 for (port = 0; port < num_ports; port++) { 438 custom_num_grp[port] = (num_ports == 4) ? 439 p4_rdcgrp_cls[port] : p2_rdcgrp_cls[port]; 440 custom_start_grp[port] = start_grp; 441 start_grp += custom_num_grp[port]; 442 } 443 444 break; 445 446 case CUSTOM: 447 cfg_prop = "custom"; 448 /* See if it is good config */ 449 num_grps = 0; 450 for (port = 0; port < num_ports; port++) { 451 custom_start_grp[port] = 452 ddi_prop_get_int(DDI_DEV_T_NONE, s_dip[port], 453 DDI_PROP_DONTPASS, start_prop, -1); 454 if ((custom_start_grp[port] == -1) || 455 (custom_start_grp[port] >= 456 NXGE_MAX_RDC_GRPS)) { 457 bad_config = B_TRUE; 458 break; 459 } 460 461 custom_num_grp[port] = ddi_prop_get_int( 462 DDI_DEV_T_NONE, 463 s_dip[port], 464 DDI_PROP_DONTPASS, 465 num_prop, -1); 466 467 if ((custom_num_grp[port] == -1) || 468 (custom_num_grp[port] > 469 NXGE_MAX_RDC_GRPS) || 470 ((custom_num_grp[port] + 471 custom_start_grp[port]) >= 472 NXGE_MAX_RDC_GRPS)) { 473 bad_config = B_TRUE; 474 break; 475 } 476 477 num_grps += custom_num_grp[port]; 478 if (num_grps > NXGE_MAX_RDC_GRPS) { 479 bad_config = B_TRUE; 480 break; 481 } 482 483 grp_bitmap[port] = 0; 484 for (bits = 0; 485 bits < custom_num_grp[port]; 486 bits++) { 487 grp_bitmap[port] |= 488 (1 << (bits + custom_start_grp[port])); 489 } 490 491 } 492 493 if (bad_config == B_FALSE) { 494 /* check for overlap */ 495 for (port = 0; port < num_ports - 1; port++) { 496 for (j = port + 1; j < num_ports; j++) { 497 if (grp_bitmap[port] & 498 grp_bitmap[j]) { 499 bad_config = B_TRUE; 500 break; 501 } 502 } 503 if (bad_config == B_TRUE) 504 break; 505 } 506 } 507 508 if (bad_config == B_TRUE) { 509 /* use default config */ 510 for (port = 0; port < num_ports; port++) { 511 custom_num_grp[port] = 512 (num_ports == 4) ? 513 p4_rx_fair[port] : p2_rx_fair[port]; 514 custom_start_grp[port] = start_grp; 515 start_grp += custom_num_grp[port]; 516 } 517 } 518 break; 519 520 default: 521 /* use default config */ 522 cfg_prop = "fair"; 523 for (port = 0; port < num_ports; port++) { 524 custom_num_grp[port] = (num_ports == 4) ? 525 p4_rx_fair[port] : p2_rx_fair[port]; 526 custom_start_grp[port] = start_grp; 527 start_grp += custom_num_grp[port]; 528 } 529 break; 530 } 531 532 /* Now Update the rx properties */ 533 for (port = 0; port < num_ports; port++) { 534 ddi_status = ddi_prop_update_string(DDI_DEV_T_NONE, s_dip[port], 535 "rxdma-grp-cfg", cfg_prop); 536 if (ddi_status != DDI_PROP_SUCCESS) { 537 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 538 " property %s not updating", 539 cfg_prop)); 540 status |= NXGE_DDI_FAILED; 541 } 542 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port], 543 num_prop, custom_num_grp[port]); 544 545 if (ddi_status != DDI_PROP_SUCCESS) { 546 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 547 " property %s not updating", 548 num_prop)); 549 status |= NXGE_DDI_FAILED; 550 } 551 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port], 552 start_prop, custom_start_grp[port]); 553 554 if (ddi_status != DDI_PROP_SUCCESS) { 555 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 556 " property %s not updating", 557 start_prop)); 558 status |= NXGE_DDI_FAILED; 559 } 560 } 561 if (status & NXGE_DDI_FAILED) 562 status |= NXGE_ERROR; 563 564 return (status); 565 566 } 567 568 569 static nxge_status_t 570 nxge_update_rxdma_properties(p_nxge_t nxgep, config_token_t token, 571 dev_info_t *s_dip[]) 572 { 573 nxge_status_t status = NXGE_OK; 574 int ddi_status; 575 int num_ports = nxgep->nports; 576 int port, bits, j; 577 uint8_t start_rdc = 0, num_rdc = 0; 578 p_nxge_param_t param_arr; 579 uint32_t rdc_bitmap[MAX_SIBLINGS]; 580 int custom_start_rdc[MAX_SIBLINGS]; 581 int custom_num_rdc[MAX_SIBLINGS]; 582 uint8_t bad_config = B_FALSE; 583 int *prop_val; 584 uint_t prop_len; 585 char *start_rdc_prop, *num_rdc_prop, *cfg_prop; 586 587 start_rdc = 0; 588 param_arr = nxgep->param_arr; 589 590 start_rdc_prop = param_arr[param_rxdma_channels_begin].fcode_name; 591 num_rdc_prop = param_arr[param_rxdma_channels].fcode_name; 592 593 switch (token) { 594 case FAIR: 595 cfg_prop = "fair"; 596 for (port = 0; port < num_ports; port++) { 597 custom_num_rdc[port] = (num_ports == 4) ? 598 p4_rx_fair[port] : p2_rx_fair[port]; 599 custom_start_rdc[port] = start_rdc; 600 start_rdc += custom_num_rdc[port]; 601 } 602 603 break; 604 605 case EQUAL: 606 cfg_prop = "equal"; 607 for (port = 0; port < num_ports; port++) { 608 custom_num_rdc[port] = (num_ports == 4) ? 609 p4_rx_equal[port] : 610 p2_rx_equal[port]; 611 custom_start_rdc[port] = start_rdc; 612 start_rdc += custom_num_rdc[port]; 613 } 614 615 break; 616 617 case CUSTOM: 618 cfg_prop = "custom"; 619 /* See if it is good config */ 620 num_rdc = 0; 621 for (port = 0; port < num_ports; port++) { 622 ddi_status = ddi_prop_lookup_int_array( 623 DDI_DEV_T_ANY, 624 s_dip[port], 0, 625 start_rdc_prop, 626 &prop_val, 627 &prop_len); 628 if (ddi_status == DDI_SUCCESS) 629 custom_start_rdc[port] = *prop_val; 630 else { 631 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 632 " %s custom start port %d" 633 " read failed ", 634 " rxdma-cfg", port)); 635 bad_config = B_TRUE; 636 status |= NXGE_DDI_FAILED; 637 } 638 if ((custom_start_rdc[port] == -1) || 639 (custom_start_rdc[port] >= 640 NXGE_MAX_RDCS)) { 641 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 642 " %s custom start %d" 643 " out of range %x ", 644 " rxdma-cfg", 645 port, 646 custom_start_rdc[port])); 647 bad_config = B_TRUE; 648 break; 649 } 650 651 ddi_status = ddi_prop_lookup_int_array( 652 DDI_DEV_T_ANY, 653 s_dip[port], 654 0, 655 num_rdc_prop, 656 &prop_val, 657 &prop_len); 658 659 if (ddi_status == DDI_SUCCESS) 660 custom_num_rdc[port] = *prop_val; 661 else { 662 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 663 " %s custom num port %d" 664 " read failed ", 665 "rxdma-cfg", port)); 666 bad_config = B_TRUE; 667 status |= NXGE_DDI_FAILED; 668 } 669 670 if ((custom_num_rdc[port] == -1) || 671 (custom_num_rdc[port] > 672 NXGE_MAX_RDCS) || 673 ((custom_num_rdc[port] + 674 custom_start_rdc[port]) > 675 NXGE_MAX_RDCS)) { 676 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 677 " %s custom num %d" 678 " out of range %x ", 679 " rxdma-cfg", 680 port, 681 custom_num_rdc[port])); 682 bad_config = B_TRUE; 683 break; 684 } 685 686 num_rdc += custom_num_rdc[port]; 687 if (num_rdc > NXGE_MAX_RDCS) { 688 bad_config = B_TRUE; 689 break; 690 } 691 692 rdc_bitmap[port] = 0; 693 for (bits = 0; 694 bits < custom_num_rdc[port]; bits++) { 695 rdc_bitmap[port] |= 696 (1 << 697 (bits + custom_start_rdc[port])); 698 } 699 700 } 701 702 if (bad_config == B_FALSE) { 703 /* check for overlap */ 704 for (port = 0; port < num_ports - 1; port++) { 705 for (j = port + 1; j < num_ports; j++) { 706 if (rdc_bitmap[port] & 707 rdc_bitmap[j]) { 708 NXGE_DEBUG_MSG((nxgep, 709 CFG_CTL, 710 " rxdma-cfg" 711 " property custom" 712 " bit overlap" 713 " %d %d ", 714 port, j)); 715 bad_config = B_TRUE; 716 break; 717 } 718 } 719 if (bad_config == B_TRUE) 720 break; 721 } 722 } 723 724 if (bad_config == B_TRUE) { 725 /* use default config */ 726 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 727 " rxdma-cfg property:" 728 " bad custom config:" 729 " use default")); 730 731 for (port = 0; port < num_ports; port++) { 732 custom_num_rdc[port] = 733 (num_ports == 4) ? 734 p4_rx_fair[port] : 735 p2_rx_fair[port]; 736 custom_start_rdc[port] = start_rdc; 737 start_rdc += custom_num_rdc[port]; 738 } 739 } 740 break; 741 742 default: 743 /* use default config */ 744 cfg_prop = "fair"; 745 for (port = 0; port < num_ports; port++) { 746 custom_num_rdc[port] = (num_ports == 4) ? 747 p4_rx_fair[port] : p2_rx_fair[port]; 748 custom_start_rdc[port] = start_rdc; 749 start_rdc += custom_num_rdc[port]; 750 } 751 break; 752 } 753 754 /* Now Update the rx properties */ 755 for (port = 0; port < num_ports; port++) { 756 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 757 " update property rxdma-cfg with %s ", 758 cfg_prop)); 759 ddi_status = ddi_prop_update_string(DDI_DEV_T_NONE, s_dip[port], 760 "rxdma-cfg", cfg_prop); 761 if (ddi_status != DDI_PROP_SUCCESS) { 762 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 763 " property rxdma-cfg" 764 " is not updating to %s", 765 cfg_prop)); 766 status |= NXGE_DDI_FAILED; 767 } 768 769 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ", 770 num_rdc_prop, custom_num_rdc[port])); 771 772 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port], 773 num_rdc_prop, custom_num_rdc[port]); 774 775 if (ddi_status != DDI_PROP_SUCCESS) { 776 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 777 " property %s not updating with %d", 778 num_rdc_prop, 779 custom_num_rdc[port])); 780 status |= NXGE_DDI_FAILED; 781 } 782 783 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ", 784 start_rdc_prop, custom_start_rdc[port])); 785 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port], 786 start_rdc_prop, 787 custom_start_rdc[port]); 788 789 if (ddi_status != DDI_PROP_SUCCESS) { 790 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 791 " property %s" 792 " not updating with %d ", 793 start_rdc_prop, 794 custom_start_rdc[port])); 795 status |= NXGE_DDI_FAILED; 796 } 797 } 798 if (status & NXGE_DDI_FAILED) 799 status |= NXGE_ERROR; 800 return (status); 801 802 } 803 804 static nxge_status_t 805 nxge_update_txdma_properties(p_nxge_t nxgep, config_token_t token, 806 dev_info_t *s_dip[]) 807 { 808 nxge_status_t status = NXGE_OK; 809 int ddi_status = DDI_SUCCESS; 810 int num_ports = nxgep->nports; 811 int port, bits, j; 812 uint8_t start_tdc = 0, num_tdc = 0; 813 p_nxge_param_t param_arr; 814 uint32_t tdc_bitmap[MAX_SIBLINGS]; 815 int custom_start_tdc[MAX_SIBLINGS]; 816 int custom_num_tdc[MAX_SIBLINGS]; 817 uint8_t bad_config = B_FALSE; 818 int *prop_val; 819 uint_t prop_len; 820 char *start_tdc_prop, *num_tdc_prop, *cfg_prop; 821 822 start_tdc = 0; 823 param_arr = nxgep->param_arr; 824 825 start_tdc_prop = param_arr[param_txdma_channels_begin].fcode_name; 826 num_tdc_prop = param_arr[param_txdma_channels].fcode_name; 827 828 switch (token) { 829 case FAIR: 830 cfg_prop = "fair"; 831 for (port = 0; port < num_ports; port++) { 832 custom_num_tdc[port] = (num_ports == 4) ? 833 p4_tx_fair[port] : p2_tx_fair[port]; 834 custom_start_tdc[port] = start_tdc; 835 start_tdc += custom_num_tdc[port]; 836 } 837 838 break; 839 840 case EQUAL: 841 cfg_prop = "equal"; 842 for (port = 0; port < num_ports; port++) { 843 custom_num_tdc[port] = (num_ports == 4) ? 844 p4_tx_equal[port] : 845 p2_tx_equal[port]; 846 custom_start_tdc[port] = start_tdc; 847 start_tdc += custom_num_tdc[port]; 848 } 849 850 break; 851 852 case CUSTOM: 853 cfg_prop = "custom"; 854 /* See if it is good config */ 855 num_tdc = 0; 856 for (port = 0; port < num_ports; port++) { 857 ddi_status = ddi_prop_lookup_int_array( 858 DDI_DEV_T_ANY, 859 s_dip[port], 0, 860 start_tdc_prop, 861 &prop_val, 862 &prop_len); 863 if (ddi_status == DDI_SUCCESS) 864 custom_start_tdc[port] = *prop_val; 865 else { 866 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 867 " %s custom start port %d" 868 " read failed ", 869 " txdma-cfg", port)); 870 bad_config = B_TRUE; 871 status |= NXGE_DDI_FAILED; 872 } 873 if ((custom_start_tdc[port] == -1) || 874 (custom_start_tdc[port] >= 875 NXGE_MAX_RDCS)) { 876 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 877 " %s custom start %d" 878 " out of range %x ", 879 " txdma-cfg", 880 port, 881 custom_start_tdc[port])); 882 bad_config = B_TRUE; 883 break; 884 } 885 886 ddi_status = ddi_prop_lookup_int_array( 887 DDI_DEV_T_ANY, 888 s_dip[port], 889 0, 890 num_tdc_prop, 891 &prop_val, 892 &prop_len); 893 894 if (ddi_status == DDI_SUCCESS) 895 custom_num_tdc[port] = *prop_val; 896 else { 897 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 898 " %s custom num port %d" 899 " read failed ", 900 " txdma-cfg", port)); 901 bad_config = B_TRUE; 902 status |= NXGE_DDI_FAILED; 903 } 904 905 if ((custom_num_tdc[port] == -1) || 906 (custom_num_tdc[port] > 907 NXGE_MAX_TDCS) || 908 ((custom_num_tdc[port] + 909 custom_start_tdc[port]) > 910 NXGE_MAX_TDCS)) { 911 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 912 " %s custom num %d" 913 " out of range %x ", 914 " rxdma-cfg", 915 port, 916 custom_num_tdc[port])); 917 bad_config = B_TRUE; 918 break; 919 } 920 921 num_tdc += custom_num_tdc[port]; 922 if (num_tdc > NXGE_MAX_TDCS) { 923 bad_config = B_TRUE; 924 break; 925 } 926 927 tdc_bitmap[port] = 0; 928 for (bits = 0; 929 bits < custom_num_tdc[port]; bits++) { 930 tdc_bitmap[port] |= 931 (1 << 932 (bits + custom_start_tdc[port])); 933 } 934 935 } 936 937 if (bad_config == B_FALSE) { 938 /* check for overlap */ 939 for (port = 0; port < num_ports - 1; port++) { 940 for (j = port + 1; j < num_ports; j++) { 941 if (tdc_bitmap[port] & 942 tdc_bitmap[j]) { 943 NXGE_DEBUG_MSG((nxgep, 944 CFG_CTL, 945 " rxdma-cfg" 946 " property custom" 947 " bit overlap" 948 " %d %d ", 949 port, j)); 950 bad_config = B_TRUE; 951 break; 952 } 953 } 954 if (bad_config == B_TRUE) 955 break; 956 } 957 } 958 959 if (bad_config == B_TRUE) { 960 /* use default config */ 961 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 962 " txdma-cfg property:" 963 " bad custom config:" 964 " use default")); 965 966 for (port = 0; port < num_ports; port++) { 967 custom_num_tdc[port] = 968 (num_ports == 4) ? 969 p4_tx_fair[port] : 970 p2_tx_fair[port]; 971 custom_start_tdc[port] = start_tdc; 972 start_tdc += custom_num_tdc[port]; 973 } 974 } 975 break; 976 977 default: 978 /* use default config */ 979 cfg_prop = "fair"; 980 for (port = 0; port < num_ports; port++) { 981 custom_num_tdc[port] = (num_ports == 4) ? 982 p4_tx_fair[port] : p2_tx_fair[port]; 983 custom_start_tdc[port] = start_tdc; 984 start_tdc += custom_num_tdc[port]; 985 } 986 break; 987 } 988 989 /* Now Update the tx properties */ 990 for (port = 0; port < num_ports; port++) { 991 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 992 " update property txdma-cfg with %s ", 993 cfg_prop)); 994 ddi_status = ddi_prop_update_string(DDI_DEV_T_NONE, s_dip[port], 995 "txdma-cfg", cfg_prop); 996 if (ddi_status != DDI_PROP_SUCCESS) { 997 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 998 " property txdma-cfg" 999 " is not updating to %s", 1000 cfg_prop)); 1001 status |= NXGE_DDI_FAILED; 1002 } 1003 1004 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ", 1005 num_tdc_prop, custom_num_tdc[port])); 1006 1007 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port], 1008 num_tdc_prop, custom_num_tdc[port]); 1009 1010 if (ddi_status != DDI_PROP_SUCCESS) { 1011 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1012 " property %s not updating with %d", 1013 num_tdc_prop, 1014 custom_num_tdc[port])); 1015 status |= NXGE_DDI_FAILED; 1016 } 1017 1018 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ", 1019 start_tdc_prop, custom_start_tdc[port])); 1020 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port], 1021 start_tdc_prop, 1022 custom_start_tdc[port]); 1023 1024 if (ddi_status != DDI_PROP_SUCCESS) { 1025 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1026 " property %s" 1027 " not updating with %d ", 1028 start_tdc_prop, 1029 custom_start_tdc[port])); 1030 status |= NXGE_DDI_FAILED; 1031 } 1032 } 1033 if (status & NXGE_DDI_FAILED) 1034 status |= NXGE_ERROR; 1035 return (status); 1036 1037 } 1038 1039 1040 1041 static nxge_status_t 1042 nxge_update_cfg_properties(p_nxge_t nxgep, uint32_t flags, 1043 config_token_t token, 1044 dev_info_t *s_dip[]) 1045 { 1046 1047 nxge_status_t status = NXGE_OK; 1048 1049 switch (flags) { 1050 case COMMON_TXDMA_CFG: 1051 if (nxge_dma_obp_props_only == 0) 1052 status = nxge_update_txdma_properties(nxgep, 1053 token, s_dip); 1054 break; 1055 case COMMON_RXDMA_CFG: 1056 if (nxge_dma_obp_props_only == 0) 1057 status = nxge_update_rxdma_properties(nxgep, 1058 token, s_dip); 1059 1060 break; 1061 case COMMON_RXDMA_GRP_CFG: 1062 status = nxge_update_rxdma_grp_properties(nxgep, 1063 token, s_dip); 1064 break; 1065 default: 1066 return (NXGE_ERROR); 1067 } 1068 return (status); 1069 } 1070 1071 1072 1073 /* 1074 * verify consistence. 1075 * (May require publishing the properties on all the ports. 1076 * 1077 * What if properties are published on function 0 device only? 1078 * 1079 * 1080 * rxdma-cfg, txdma-cfg, rxdma-grp-cfg (required ) 1081 * What about class configs? 1082 * 1083 * If consistent, update the property on all the siblings. 1084 * set a flag on hardware shared register 1085 * The rest of the siblings will check the flag 1086 * if the flag is set, they will use the updated property 1087 * without doing any validation. 1088 */ 1089 1090 1091 nxge_status_t 1092 nxge_cfg_verify_set_classify_prop(p_nxge_t nxgep, char *prop, 1093 uint64_t known_cfg, 1094 uint32_t override, 1095 dev_info_t *c_dip[]) 1096 { 1097 nxge_status_t status = NXGE_OK; 1098 int ddi_status = DDI_SUCCESS; 1099 int i = 0, found = 0, update_prop = B_TRUE; 1100 int *cfg_val; 1101 uint_t new_value, cfg_value[MAX_SIBLINGS]; 1102 uint_t prop_len; 1103 uint_t known_cfg_value; 1104 1105 known_cfg_value = (uint_t)known_cfg; 1106 1107 if (override == B_TRUE) { 1108 new_value = known_cfg_value; 1109 for (i = 0; i < nxgep->nports; i++) { 1110 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, 1111 c_dip[i], prop, new_value); 1112 #ifdef NXGE_DEBUG_ERROR 1113 if (ddi_status != DDI_PROP_SUCCESS) 1114 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1115 " property %s failed update ", prop)); 1116 #endif 1117 } 1118 if (ddi_status != DDI_PROP_SUCCESS) 1119 return (NXGE_ERROR | NXGE_DDI_FAILED); 1120 } 1121 1122 for (i = 0; i < nxgep->nports; i++) { 1123 cfg_value[i] = known_cfg_value; 1124 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, c_dip[i], 0, 1125 prop, &cfg_val, 1126 &prop_len) == 1127 DDI_PROP_SUCCESS) { 1128 cfg_value[i] = *cfg_val; 1129 ddi_prop_free(cfg_val); 1130 found++; 1131 } 1132 } 1133 1134 if (found != i) { 1135 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1136 " property %s not specified on all ports", 1137 prop)); 1138 if (found == 0) { 1139 /* not specified: Use default */ 1140 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1141 " property %s not specified" 1142 " on any port:" 1143 " Using default", prop)); 1144 1145 new_value = known_cfg_value; 1146 } else { 1147 /* specified on some */ 1148 1149 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1150 " property %s not specified" 1151 " on some ports:" 1152 " Using default", prop)); 1153 /* ? use p0 value instead ? */ 1154 new_value = known_cfg_value; 1155 } 1156 } else { 1157 /* check type and consistence */ 1158 /* found on all devices */ 1159 for (i = 1; i < found; i++) { 1160 if (cfg_value[i] != cfg_value[i-1]) { 1161 1162 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1163 " property %s inconsistent:" 1164 " Using default", prop)); 1165 new_value = known_cfg_value; 1166 break; 1167 } 1168 1169 /* 1170 * Found on all the ports and consistent. Nothing to do. 1171 */ 1172 update_prop = B_FALSE; 1173 } 1174 1175 } 1176 1177 if (update_prop == B_TRUE) { 1178 for (i = 0; i < nxgep->nports; i++) { 1179 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, 1180 c_dip[i], 1181 prop, new_value); 1182 #ifdef NXGE_DEBUG_ERROR 1183 if (ddi_status != DDI_SUCCESS) 1184 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1185 " property %s not updating with %d" 1186 " Using default", 1187 prop, new_value)); 1188 #endif 1189 if (ddi_status != DDI_PROP_SUCCESS) 1190 status |= NXGE_DDI_FAILED; 1191 } 1192 } 1193 if (status & NXGE_DDI_FAILED) 1194 status |= NXGE_ERROR; 1195 1196 return (status); 1197 } 1198 1199 static uint64_t 1200 nxge_class_get_known_cfg(p_nxge_t nxgep, 1201 int class_prop, int rx_quick_cfg) 1202 { 1203 1204 int start_prop; 1205 uint64_t cfg_value; 1206 1207 p_nxge_param_t param_arr; 1208 param_arr = nxgep->param_arr; 1209 1210 cfg_value = param_arr[class_prop].value; 1211 start_prop = param_h1_init_value; 1212 1213 /* update the properties per quick config */ 1214 1215 switch (rx_quick_cfg) { 1216 case CFG_L3_WEB: 1217 case CFG_L3_DISTRIBUTE: 1218 cfg_value = nxge_classify_get_cfg_value(nxgep, 1219 rx_quick_cfg, 1220 class_prop - start_prop); 1221 break; 1222 default: 1223 cfg_value = param_arr[class_prop].value; 1224 break; 1225 } 1226 1227 return (cfg_value); 1228 1229 } 1230 1231 1232 static nxge_status_t 1233 nxge_cfg_verify_set_classify(p_nxge_t nxgep, dev_info_t *c_dip[]) 1234 { 1235 1236 nxge_status_t status = NXGE_OK; 1237 int rx_quick_cfg, class_prop, start_prop, end_prop; 1238 char *prop_name; 1239 int override = B_TRUE; 1240 uint64_t cfg_value; 1241 p_nxge_param_t param_arr; 1242 param_arr = nxgep->param_arr; 1243 rx_quick_cfg = param_arr[param_rx_quick_cfg].value; 1244 start_prop = param_h1_init_value; 1245 end_prop = param_class_opt_ipv6_sctp; 1246 /* update the properties per quick config */ 1247 1248 1249 if (rx_quick_cfg == CFG_NOT_SPECIFIED) 1250 override = B_FALSE; 1251 /* 1252 * these parameter affect the classification outcome. 1253 * these parameters are used to configure the Flow key and 1254 * the TCAM key for each of the IP classes. 1255 * Includee here are also the H1 and H2 initial values 1256 * which affect the distribution as well as final hash value 1257 * (hence the offset into RDC table and FCRAM bucket location) 1258 * 1259 */ 1260 for (class_prop = start_prop; 1261 class_prop <= end_prop; class_prop++) { 1262 prop_name = param_arr[class_prop].fcode_name; 1263 cfg_value = nxge_class_get_known_cfg(nxgep, 1264 class_prop, 1265 rx_quick_cfg); 1266 status = nxge_cfg_verify_set_classify_prop(nxgep, 1267 prop_name, cfg_value, 1268 override, c_dip); 1269 } 1270 1271 1272 /* 1273 * these properties do not affect the actual classification outcome. 1274 * used to enable/disable or tune the fflp hardware 1275 * 1276 * fcram_access_ratio, tcam_access_ratio, tcam_enable, llc_snap_enable 1277 * 1278 */ 1279 override = B_FALSE; 1280 for (class_prop = param_fcram_access_ratio; 1281 class_prop <= param_llc_snap_enable; 1282 class_prop++) { 1283 prop_name = param_arr[class_prop].fcode_name; 1284 cfg_value = param_arr[class_prop].value; 1285 status = nxge_cfg_verify_set_classify_prop(nxgep, prop_name, 1286 cfg_value, override, c_dip); 1287 } 1288 return (status); 1289 1290 } 1291 1292 1293 1294 nxge_status_t 1295 nxge_cfg_verify_set(p_nxge_t nxgep, uint32_t flag) 1296 { 1297 1298 nxge_status_t status = NXGE_OK; 1299 int i = 0, found = 0; 1300 int num_siblings; 1301 dev_info_t *c_dip[MAX_SIBLINGS + 1]; 1302 char *prop_val[MAX_SIBLINGS]; 1303 config_token_t c_token[MAX_SIBLINGS]; 1304 char *prop; 1305 1306 if (nxge_dma_obp_props_only) { 1307 return (NXGE_OK); 1308 } 1309 1310 num_siblings = 0; 1311 c_dip[num_siblings] = ddi_get_child(nxgep->p_dip); 1312 while (c_dip[num_siblings]) { 1313 c_dip[num_siblings + 1] = 1314 ddi_get_next_sibling(c_dip[num_siblings]); 1315 num_siblings++; 1316 } 1317 1318 1319 switch (flag) { 1320 case COMMON_TXDMA_CFG: 1321 prop = "txdma-cfg"; 1322 break; 1323 case COMMON_RXDMA_CFG: 1324 prop = "rxdma-cfg"; 1325 break; 1326 case COMMON_RXDMA_GRP_CFG: 1327 prop = "rxdma-grp-cfg"; 1328 break; 1329 case COMMON_CLASS_CFG: 1330 status = nxge_cfg_verify_set_classify(nxgep, c_dip); 1331 return (status); 1332 default: 1333 return (NXGE_ERROR); 1334 } 1335 1336 1337 i = 0; 1338 while (i < num_siblings) { 1339 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, c_dip[i], 0, 1340 prop, (char **)&prop_val[i]) == 1341 DDI_PROP_SUCCESS) { 1342 c_token[i] = nxge_get_config_token(prop_val[i]); 1343 ddi_prop_free(prop_val[i]); 1344 found++; 1345 } else 1346 c_token[i] = CONFIG_TOKEN_NONE; 1347 i++; 1348 } 1349 1350 1351 if (found != i) { 1352 if (found == 0) { 1353 /* not specified: Use default */ 1354 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1355 " property %s not specified" 1356 " on any port:" 1357 " Using default", 1358 prop)); 1359 1360 status = nxge_update_cfg_properties(nxgep, 1361 flag, FAIR, c_dip); 1362 return (status); 1363 } else { 1364 /* 1365 * if the convention is to use function 0 device 1366 * then populate the other devices with this 1367 * configuration. 1368 * 1369 * The other alternative is to use the default config. 1370 */ 1371 /* not specified: Use default */ 1372 1373 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1374 " property %s not specified" 1375 " on some ports:" 1376 " Using default", 1377 prop)); 1378 status = nxge_update_cfg_properties(nxgep, 1379 flag, FAIR, c_dip); 1380 return (status); 1381 } 1382 } 1383 /* check type and consistence */ 1384 /* found on all devices */ 1385 for (i = 1; i < found; i++) { 1386 if (c_token[i] != c_token[i-1]) { 1387 1388 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1389 " property %s inconsistent:" 1390 " Using default", prop)); 1391 1392 status = nxge_update_cfg_properties(nxgep, 1393 flag, FAIR, c_dip); 1394 return (status); 1395 } 1396 } 1397 /* 1398 * Found on all the ports 1399 * check if it is custom configuration. 1400 * if custom, then verify consistence 1401 * 1402 * finally create soft properties 1403 */ 1404 status = nxge_update_cfg_properties(nxgep, flag, c_token[0], c_dip); 1405 1406 return (status); 1407 } 1408 1409 1410 1411 nxge_status_t 1412 nxge_cfg_verify_set_quick_config(p_nxge_t nxgep) 1413 { 1414 nxge_status_t status = NXGE_OK; 1415 int ddi_status = DDI_SUCCESS; 1416 char *prop_val; 1417 char *rx_prop; 1418 char *prop; 1419 uint32_t cfg_value = CFG_NOT_SPECIFIED; 1420 p_nxge_param_t param_arr; 1421 param_arr = nxgep->param_arr; 1422 1423 rx_prop = param_arr[param_rx_quick_cfg].fcode_name; 1424 1425 prop = "rx-quick-cfg"; 1426 /* 1427 * good value are 1428 * 1429 * "web-server" 1430 * "generic-server" 1431 * "l3-classify" 1432 * "flow-classify" 1433 */ 1434 1435 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, nxgep->dip, 0, 1436 prop, (char **)&prop_val) != 1437 DDI_PROP_SUCCESS) { 1438 1439 NXGE_DEBUG_MSG((nxgep, VPD_CTL, 1440 " property %s not specified:" 1441 " using default ", prop)); 1442 cfg_value = CFG_NOT_SPECIFIED; 1443 } else { 1444 cfg_value = CFG_L3_DISTRIBUTE; 1445 if (strncmp("web-server", (caddr_t)prop_val, 8) == 0) { 1446 cfg_value = CFG_L3_WEB; 1447 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1448 " %s: web server ", prop)); 1449 } 1450 if (strncmp("generic-server", (caddr_t)prop_val, 8) == 0) { 1451 cfg_value = CFG_L3_DISTRIBUTE; 1452 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1453 " %s: distribute ", prop)); 1454 } 1455 /* more */ 1456 1457 ddi_prop_free(prop_val); 1458 } 1459 1460 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 1461 rx_prop, cfg_value); 1462 if (ddi_status != DDI_PROP_SUCCESS) 1463 status |= NXGE_DDI_FAILED; 1464 #ifdef lint 1465 status = status; 1466 #endif 1467 /* now handle specified cases: */ 1468 1469 if (status & NXGE_DDI_FAILED) 1470 status |= NXGE_ERROR; 1471 1472 return (status); 1473 } 1474 1475 1476 1477 static void 1478 nxge_use_cfg_link_cfg(p_nxge_t nxgep) 1479 { 1480 int *prop_val; 1481 uint_t prop_len; 1482 dev_info_t *dip; 1483 int speed; 1484 int duplex; 1485 int adv_autoneg_cap; 1486 int adv_10gfdx_cap; 1487 int adv_10ghdx_cap; 1488 int adv_1000fdx_cap; 1489 int adv_1000hdx_cap; 1490 int adv_100fdx_cap; 1491 int adv_100hdx_cap; 1492 int adv_10fdx_cap; 1493 int adv_10hdx_cap; 1494 int status = DDI_SUCCESS; 1495 1496 dip = nxgep->dip; 1497 /* 1498 * first find out the card type and the supported 1499 * link speeds and features 1500 */ 1501 /* add code for card type */ 1502 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-autoneg-cap", 1503 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1504 ddi_prop_free(prop_val); 1505 goto nxge_map_myargs_to_gmii_exit; 1506 } 1507 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-10gfdx-cap", 1508 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1509 ddi_prop_free(prop_val); 1510 goto nxge_map_myargs_to_gmii_exit; 1511 } 1512 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-1000hdx-cap", 1513 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1514 ddi_prop_free(prop_val); 1515 goto nxge_map_myargs_to_gmii_exit; 1516 } 1517 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-1000fdx-cap", 1518 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1519 ddi_prop_free(prop_val); 1520 goto nxge_map_myargs_to_gmii_exit; 1521 } 1522 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-100fdx-cap", 1523 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1524 ddi_prop_free(prop_val); 1525 goto nxge_map_myargs_to_gmii_exit; 1526 } 1527 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-100hdx-cap", 1528 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1529 ddi_prop_free(prop_val); 1530 goto nxge_map_myargs_to_gmii_exit; 1531 } 1532 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-10fdx-cap", 1533 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1534 ddi_prop_free(prop_val); 1535 goto nxge_map_myargs_to_gmii_exit; 1536 } 1537 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-10hdx-cap", 1538 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1539 ddi_prop_free(prop_val); 1540 goto nxge_map_myargs_to_gmii_exit; 1541 } 1542 1543 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 0, "speed", 1544 (uchar_t **)&prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1545 if (strncmp("10000", (caddr_t)prop_val, 1546 (size_t)prop_len) == 0) { 1547 speed = 10000; 1548 } else if (strncmp("1000", (caddr_t)prop_val, 1549 (size_t)prop_len) == 0) { 1550 speed = 1000; 1551 } else if (strncmp("100", (caddr_t)prop_val, 1552 (size_t)prop_len) == 0) { 1553 speed = 100; 1554 } else if (strncmp("10", (caddr_t)prop_val, 1555 (size_t)prop_len) == 0) { 1556 speed = 10; 1557 } else if (strncmp("auto", (caddr_t)prop_val, 1558 (size_t)prop_len) == 0) { 1559 speed = 0; 1560 } else { 1561 NXGE_ERROR_MSG((nxgep, NXGE_NOTE, 1562 "speed property is invalid" 1563 " reverting to auto")); 1564 speed = 0; 1565 } 1566 ddi_prop_free(prop_val); 1567 } else 1568 speed = 0; 1569 1570 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 0, "duplex", 1571 (uchar_t **)&prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1572 if (strncmp("full", (caddr_t)prop_val, 1573 (size_t)prop_len) == 0) { 1574 duplex = 2; 1575 } else if (strncmp("half", (caddr_t)prop_val, 1576 (size_t)prop_len) == 0) { 1577 duplex = 1; 1578 } else if (strncmp("auto", (caddr_t)prop_val, 1579 (size_t)prop_len) == 0) { 1580 duplex = 0; 1581 } else { 1582 NXGE_ERROR_MSG((nxgep, NXGE_NOTE, 1583 "duplex property is invalid" 1584 " reverting to auto")); 1585 duplex = 0; 1586 } 1587 ddi_prop_free(prop_val); 1588 } else 1589 duplex = 0; 1590 1591 adv_autoneg_cap = (speed == 0) || (duplex == 0); 1592 if (adv_autoneg_cap == 0) { 1593 adv_10gfdx_cap = ((speed == 10000) && (duplex == 2)); 1594 adv_10ghdx_cap = adv_10gfdx_cap; 1595 adv_10ghdx_cap |= ((speed == 10000) && (duplex == 1)); 1596 adv_1000fdx_cap = adv_10ghdx_cap; 1597 adv_1000fdx_cap |= ((speed == 1000) && (duplex == 2)); 1598 adv_1000hdx_cap = adv_1000fdx_cap; 1599 adv_1000hdx_cap |= ((speed == 1000) && (duplex == 1)); 1600 adv_100fdx_cap = adv_1000hdx_cap; 1601 adv_100fdx_cap |= ((speed == 100) && (duplex == 2)); 1602 adv_100hdx_cap = adv_100fdx_cap; 1603 adv_100hdx_cap |= ((speed == 100) && (duplex == 1)); 1604 adv_10fdx_cap = adv_100hdx_cap; 1605 adv_10fdx_cap |= ((speed == 10) && (duplex == 2)); 1606 adv_10hdx_cap = adv_10fdx_cap; 1607 adv_10hdx_cap |= ((speed == 10) && (duplex == 1)); 1608 } else if (speed == 0) { 1609 adv_10gfdx_cap = (duplex == 2); 1610 adv_10ghdx_cap = (duplex == 1); 1611 adv_1000fdx_cap = (duplex == 2); 1612 adv_1000hdx_cap = (duplex == 1); 1613 adv_100fdx_cap = (duplex == 2); 1614 adv_100hdx_cap = (duplex == 1); 1615 adv_10fdx_cap = (duplex == 2); 1616 adv_10hdx_cap = (duplex == 1); 1617 } 1618 if (duplex == 0) { 1619 adv_10gfdx_cap = (speed == 0); 1620 adv_10gfdx_cap |= (speed == 10000); 1621 adv_10ghdx_cap = adv_10gfdx_cap; 1622 adv_10ghdx_cap |= (speed == 10000); 1623 adv_1000fdx_cap = adv_10ghdx_cap; 1624 adv_1000fdx_cap |= (speed == 1000); 1625 adv_1000hdx_cap = adv_1000fdx_cap; 1626 adv_1000hdx_cap |= (speed == 1000); 1627 adv_100fdx_cap = adv_1000hdx_cap; 1628 adv_100fdx_cap |= (speed == 100); 1629 adv_100hdx_cap = adv_100fdx_cap; 1630 adv_100hdx_cap |= (speed == 100); 1631 adv_10fdx_cap = adv_100hdx_cap; 1632 adv_10fdx_cap |= (speed == 10); 1633 adv_10hdx_cap = adv_10fdx_cap; 1634 adv_10hdx_cap |= (speed == 10); 1635 } 1636 1637 1638 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1639 "adv-autoneg-cap", &adv_autoneg_cap, 1); 1640 if (status) 1641 goto nxge_map_myargs_to_gmii_exit; 1642 1643 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1644 "adv-10gfdx-cap", &adv_10gfdx_cap, 1); 1645 if (status) 1646 goto nxge_map_myargs_to_gmii_fail1; 1647 1648 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1649 "adv-10ghdx-cap", &adv_10ghdx_cap, 1); 1650 if (status) 1651 goto nxge_map_myargs_to_gmii_fail2; 1652 1653 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1654 "adv-1000fdx-cap", &adv_1000fdx_cap, 1); 1655 if (status) 1656 goto nxge_map_myargs_to_gmii_fail3; 1657 1658 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1659 "adv-1000hdx-cap", &adv_1000hdx_cap, 1); 1660 if (status) 1661 goto nxge_map_myargs_to_gmii_fail4; 1662 1663 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1664 "adv-100fdx-cap", &adv_100fdx_cap, 1); 1665 if (status) 1666 goto nxge_map_myargs_to_gmii_fail5; 1667 1668 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1669 "adv-100hdx-cap", &adv_100hdx_cap, 1); 1670 if (status) 1671 goto nxge_map_myargs_to_gmii_fail6; 1672 1673 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1674 "adv-10fdx-cap", &adv_10fdx_cap, 1); 1675 if (status) 1676 goto nxge_map_myargs_to_gmii_fail7; 1677 1678 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1679 "adv-10hdx-cap", &adv_10hdx_cap, 1); 1680 if (status) 1681 goto nxge_map_myargs_to_gmii_fail8; 1682 1683 goto nxge_map_myargs_to_gmii_exit; 1684 1685 nxge_map_myargs_to_gmii_fail9: 1686 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-10hdx-cap"); 1687 1688 nxge_map_myargs_to_gmii_fail8: 1689 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-10fdx-cap"); 1690 1691 nxge_map_myargs_to_gmii_fail7: 1692 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-100hdx-cap"); 1693 1694 nxge_map_myargs_to_gmii_fail6: 1695 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-100fdx-cap"); 1696 1697 nxge_map_myargs_to_gmii_fail5: 1698 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-1000hdx-cap"); 1699 1700 nxge_map_myargs_to_gmii_fail4: 1701 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-1000fdx-cap"); 1702 1703 nxge_map_myargs_to_gmii_fail3: 1704 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-10ghdx-cap"); 1705 1706 nxge_map_myargs_to_gmii_fail2: 1707 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-10gfdx-cap"); 1708 1709 nxge_map_myargs_to_gmii_fail1: 1710 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-autoneg-cap"); 1711 1712 nxge_map_myargs_to_gmii_exit: 1713 return; 1714 1715 } 1716 1717 1718 nxge_status_t 1719 nxge_get_config_properties(p_nxge_t nxgep) 1720 { 1721 nxge_status_t status = NXGE_OK; 1722 p_nxge_hw_list_t hw_p; 1723 uint_t prop_len; 1724 uchar_t *prop_val8; 1725 1726 NXGE_DEBUG_MSG((nxgep, VPD_CTL, " ==> nxge_get_config_properties")); 1727 1728 if ((hw_p = nxgep->nxge_hw_p) == NULL) { 1729 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1730 " nxge_get_config_properties:" 1731 " common hardware not set", 1732 nxgep->niu_type)); 1733 return (NXGE_ERROR); 1734 } 1735 1736 /* 1737 * Get info on how many ports Neptune card has. 1738 */ 1739 switch (nxgep->niu_type) { 1740 case N2_NIU: 1741 nxgep->nports = 2; 1742 nxgep->classifier.tcam_size = TCAM_NIU_TCAM_MAX_ENTRY; 1743 if (nxgep->function_num > 1) { 1744 return (NXGE_ERROR); 1745 } 1746 break; 1747 case NEPTUNE_2: 1748 if (nxgep->function_num > 1) { 1749 return (NXGE_ERROR); 1750 } 1751 /* Set Board Version Number */ 1752 nxgep->board_ver = 0; 1753 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, 1754 nxgep->dip, 1755 0, "board-model", &prop_val8, 1756 &prop_len) == DDI_PROP_SUCCESS) { 1757 if (prop_len > 9) { 1758 if ((prop_val8[9] == '0') && 1759 (prop_val8[10] == '4')) 1760 nxgep->board_ver = 4; 1761 } 1762 ddi_prop_free(prop_val8); 1763 } 1764 status = nxge_espc_num_ports_get(nxgep); 1765 if (status != NXGE_OK) { 1766 return (NXGE_ERROR); 1767 } 1768 nxgep->classifier.tcam_size = TCAM_NXGE_TCAM_MAX_ENTRY; 1769 break; 1770 1771 case NEPTUNE: 1772 default: 1773 status = nxge_espc_num_ports_get(nxgep); 1774 if (status != NXGE_OK) { 1775 return (NXGE_ERROR); 1776 } 1777 nxgep->classifier.tcam_size = TCAM_NXGE_TCAM_MAX_ENTRY; 1778 1779 break; 1780 } 1781 1782 status = nxge_get_mac_addr_properties(nxgep); 1783 if (status != NXGE_OK) { 1784 return (NXGE_ERROR); 1785 } 1786 /* 1787 * read the configuration type. 1788 * If none is specified, used default. 1789 * Config types: 1790 * equal: (default) 1791 * DMA channels, RDC groups, TCAM, FCRAM are shared equally 1792 * across all the ports. 1793 * 1794 * Fair: 1795 * DMA channels, RDC groups, TCAM, FCRAM are shared 1796 * proprtional 1797 * to te port speed. 1798 * 1799 * 1800 * custom: 1801 * DMA channels, RDC groups, TCAM, FCRAM partition is 1802 * specified in nxge.conf. Need to read each parameter 1803 * and set up the parameters in nxge structures. 1804 * 1805 */ 1806 switch (nxgep->niu_type) { 1807 case N2_NIU: 1808 NXGE_DEBUG_MSG((nxgep, VPD_CTL, 1809 " ==> nxge_get_config_properties: N2")); 1810 MUTEX_ENTER(&hw_p->nxge_cfg_lock); 1811 if ((hw_p->flags & COMMON_CFG_VALID) != 1812 COMMON_CFG_VALID) { 1813 status = nxge_cfg_verify_set(nxgep, 1814 COMMON_RXDMA_GRP_CFG); 1815 status = nxge_cfg_verify_set(nxgep, 1816 COMMON_CLASS_CFG); 1817 hw_p->flags |= COMMON_CFG_VALID; 1818 } 1819 MUTEX_EXIT(&hw_p->nxge_cfg_lock); 1820 1821 status = nxge_use_cfg_n2niu_properties(nxgep); 1822 break; 1823 1824 case NEPTUNE: 1825 NXGE_DEBUG_MSG((nxgep, VPD_CTL, 1826 " ==> nxge_get_config_properties: Neptune")); 1827 status = nxge_cfg_verify_set_quick_config(nxgep); 1828 MUTEX_ENTER(&hw_p->nxge_cfg_lock); 1829 if ((hw_p->flags & COMMON_CFG_VALID) != 1830 COMMON_CFG_VALID) { 1831 status = nxge_cfg_verify_set(nxgep, 1832 COMMON_TXDMA_CFG); 1833 status = nxge_cfg_verify_set(nxgep, 1834 COMMON_RXDMA_CFG); 1835 status = nxge_cfg_verify_set(nxgep, 1836 COMMON_RXDMA_GRP_CFG); 1837 status = nxge_cfg_verify_set(nxgep, 1838 COMMON_CLASS_CFG); 1839 hw_p->flags |= COMMON_CFG_VALID; 1840 } 1841 1842 MUTEX_EXIT(&hw_p->nxge_cfg_lock); 1843 1844 nxge_use_cfg_neptune_properties(nxgep); 1845 1846 status = NXGE_OK; 1847 break; 1848 1849 case NEPTUNE_2: 1850 NXGE_DEBUG_MSG((nxgep, VPD_CTL, 1851 " ==> nxge_get_config_properties: Neptune-2")); 1852 if (nxgep->function_num > 1) 1853 return (NXGE_ERROR); 1854 status = nxge_cfg_verify_set_quick_config(nxgep); 1855 MUTEX_ENTER(&hw_p->nxge_cfg_lock); 1856 1857 if ((hw_p->flags & COMMON_CFG_VALID) != 1858 COMMON_CFG_VALID) { 1859 status = nxge_cfg_verify_set(nxgep, 1860 COMMON_TXDMA_CFG); 1861 status = nxge_cfg_verify_set(nxgep, 1862 COMMON_RXDMA_CFG); 1863 status = nxge_cfg_verify_set(nxgep, 1864 COMMON_RXDMA_GRP_CFG); 1865 status = nxge_cfg_verify_set(nxgep, 1866 COMMON_CLASS_CFG); 1867 hw_p->flags |= COMMON_CFG_VALID; 1868 } 1869 1870 MUTEX_EXIT(&hw_p->nxge_cfg_lock); 1871 1872 nxge_use_cfg_neptune_properties(nxgep); 1873 1874 status = NXGE_OK; 1875 break; 1876 1877 default: 1878 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1879 " nxge_get_config_properties:" 1880 " unknown NIU type %x", 1881 nxgep->niu_type)); 1882 return (NXGE_ERROR); 1883 } 1884 1885 NXGE_DEBUG_MSG((nxgep, VPD_CTL, " <== nxge_get_config_properties")); 1886 return (status); 1887 } 1888 1889 1890 static nxge_status_t 1891 nxge_use_cfg_n2niu_properties(p_nxge_t nxgep) 1892 { 1893 nxge_status_t status = NXGE_OK; 1894 1895 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_use_cfg_n2niu_properties")); 1896 1897 status = nxge_use_default_dma_config_n2(nxgep); 1898 if (status != NXGE_OK) { 1899 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1900 " ==> nxge_use_cfg_n2niu_properties (err 0x%x)", 1901 status)); 1902 return (status | NXGE_ERROR); 1903 } 1904 1905 (void) nxge_use_cfg_vlan_class_config(nxgep); 1906 (void) nxge_use_cfg_mac_class_config(nxgep); 1907 (void) nxge_use_cfg_class_config(nxgep); 1908 1909 (void) nxge_use_cfg_link_cfg(nxgep); 1910 1911 /* Setup the VPD, expansion ROM, or MAC addresses configuration */ 1912 nxge_setup_hw_vpd_rom_mac(nxgep); 1913 1914 /* 1915 * Read in the hardware (fcode) properties. Use the ndd array 1916 * to read each property. 1917 */ 1918 (void) nxge_get_param_soft_properties(nxgep); 1919 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_use_cfg_n2niu_properties")); 1920 1921 return (status); 1922 } 1923 1924 1925 static void 1926 nxge_use_cfg_neptune_properties(p_nxge_t nxgep) 1927 { 1928 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1929 " ==> nxge_use_cfg_neptune_properties")); 1930 1931 (void) nxge_use_cfg_dma_config(nxgep); 1932 (void) nxge_use_cfg_vlan_class_config(nxgep); 1933 (void) nxge_use_cfg_mac_class_config(nxgep); 1934 (void) nxge_use_cfg_class_config(nxgep); 1935 1936 (void) nxge_use_cfg_link_cfg(nxgep); 1937 1938 /* Setup the PCI related configuration */ 1939 nxge_setup_hw_pciconfig(nxgep); 1940 1941 /* Setup the VPD, expansion ROM, or MAC addresses configuration */ 1942 nxge_setup_hw_vpd_rom_mac(nxgep); 1943 1944 /* 1945 * Read in the hardware (fcode) properties. Use the ndd array 1946 * to read each property. 1947 */ 1948 (void) nxge_get_param_soft_properties(nxgep); 1949 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1950 " <== nxge_use_cfg_neptune_properties")); 1951 1952 } 1953 1954 /* FWARC 2006/556 */ 1955 static nxge_status_t 1956 nxge_use_default_dma_config_n2(p_nxge_t nxgep) 1957 { 1958 int ndmas; 1959 int nrxgp; 1960 uint8_t func; 1961 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1962 p_nxge_hw_pt_cfg_t p_cfgp; 1963 int *prop_val; 1964 uint_t prop_len; 1965 int i; 1966 nxge_status_t status = NXGE_OK; 1967 1968 NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_use_default_dma_config_n2")); 1969 1970 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1971 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1972 1973 func = nxgep->function_num; 1974 p_cfgp->function_number = func; 1975 ndmas = NXGE_TDMA_PER_NIU_PORT; 1976 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 1977 "tx-dma-channels", 1978 (int **)&prop_val, 1979 &prop_len) == DDI_PROP_SUCCESS) { 1980 p_cfgp->start_tdc = prop_val[0]; 1981 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 1982 "==> nxge_use_default_dma_config_n2: tdc starts %d " 1983 "(#%d)", p_cfgp->start_tdc, prop_len)); 1984 1985 ndmas = prop_val[1]; 1986 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 1987 "==> nxge_use_default_dma_config_n2: #tdc %d (#%d)", 1988 ndmas, prop_len)); 1989 ddi_prop_free(prop_val); 1990 } else { 1991 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1992 "==> nxge_use_default_dma_config_n2: " 1993 "get tx-dma-channels failed")); 1994 return (NXGE_DDI_FAILED); 1995 } 1996 1997 p_cfgp->max_tdcs = nxgep->max_tdcs = ndmas; 1998 nxgep->tdc_mask = (ndmas - 1); 1999 2000 NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_use_default_dma_config_n2: " 2001 "p_cfgp 0x%llx max_tdcs %d nxgep->max_tdcs %d start %d", 2002 p_cfgp, p_cfgp->max_tdcs, nxgep->max_tdcs, p_cfgp->start_tdc)); 2003 2004 /* Receive DMA */ 2005 ndmas = NXGE_RDMA_PER_NIU_PORT; 2006 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 2007 "rx-dma-channels", 2008 (int **)&prop_val, 2009 &prop_len) == DDI_PROP_SUCCESS) { 2010 p_cfgp->start_rdc = prop_val[0]; 2011 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 2012 "==> nxge_use_default_dma_config_n2(obp): rdc start %d" 2013 " (#%d)", p_cfgp->start_rdc, prop_len)); 2014 2015 ndmas = prop_val[1]; 2016 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 2017 "==> nxge_use_default_dma_config_n2(obp):#rdc %d (#%d)", 2018 ndmas, prop_len)); 2019 2020 ddi_prop_free(prop_val); 2021 } else { 2022 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2023 "==> nxge_use_default_dma_config_n2: " 2024 "get rx-dma-channel failed")); 2025 return (NXGE_DDI_FAILED); 2026 } 2027 2028 p_cfgp->max_rdcs = nxgep->max_rdcs = ndmas; 2029 nxgep->rdc_mask = (ndmas - 1); 2030 2031 /* Hypervisor: rdc # and group # use the same # !! */ 2032 p_cfgp->max_grpids = p_cfgp->max_rdcs + p_cfgp->max_tdcs; 2033 p_cfgp->start_grpid = 0; 2034 p_cfgp->mif_ldvid = p_cfgp->mac_ldvid = p_cfgp->ser_ldvid = 0; 2035 2036 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 2037 "interrupts", 2038 (int **)&prop_val, 2039 &prop_len) == DDI_PROP_SUCCESS) { 2040 /* 2041 * For each device assigned, the content of each 2042 * interrupts property is its logical device group. 2043 * 2044 * Assignment of interrupts property is in the 2045 * the following order: 2046 * 2047 * MAC 2048 * MIF (if configured) 2049 * SYSTEM ERROR (if configured) 2050 * first receive channel 2051 * next channel...... 2052 * last receive channel 2053 * first transmit channel 2054 * next channel...... 2055 * last transmit channel 2056 * 2057 * prop_len should be at least for one mac 2058 * and total # of rx and tx channels. 2059 * Function 0 owns MIF and ERROR 2060 */ 2061 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 2062 "==> nxge_use_default_dma_config_n2(obp): " 2063 "# interrupts %d", prop_len)); 2064 2065 switch (func) { 2066 case 0: 2067 p_cfgp->ldg_chn_start = 3; 2068 p_cfgp->mac_ldvid = NXGE_MAC_LD_PORT0; 2069 p_cfgp->mif_ldvid = NXGE_MIF_LD; 2070 p_cfgp->ser_ldvid = NXGE_SYS_ERROR_LD; 2071 2072 break; 2073 case 1: 2074 p_cfgp->ldg_chn_start = 1; 2075 p_cfgp->mac_ldvid = NXGE_MAC_LD_PORT1; 2076 2077 break; 2078 default: 2079 status = NXGE_DDI_FAILED; 2080 break; 2081 } 2082 2083 if (status != NXGE_OK) { 2084 return (status); 2085 } 2086 2087 for (i = 0; i < prop_len; i++) { 2088 p_cfgp->ldg[i] = prop_val[i]; 2089 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 2090 "==> nxge_use_default_dma_config_n2(obp): " 2091 "interrupt #%d, ldg %d", 2092 i, p_cfgp->ldg[i])); 2093 } 2094 2095 p_cfgp->max_grpids = prop_len; 2096 2097 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 2098 "==> nxge_use_default_dma_config_n2(obp): %d " 2099 "(#%d) maxgrpids %d channel starts %d", 2100 p_cfgp->mac_ldvid, i, p_cfgp->max_grpids, 2101 p_cfgp->ldg_chn_start)); 2102 ddi_prop_free(prop_val); 2103 } else { 2104 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2105 "==> nxge_use_default_dma_config_n2: " 2106 "get interrupts failed")); 2107 return (NXGE_DDI_FAILED); 2108 } 2109 2110 p_cfgp->max_ldgs = p_cfgp->max_grpids; 2111 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 2112 "==> nxge_use_default_dma_config_n2: " 2113 "p_cfgp 0x%llx max_rdcs %d nxgep->max_rdcs %d max_grpids %d" 2114 "start_grpid %d macid %d mifid %d serrid %d", 2115 p_cfgp, p_cfgp->max_rdcs, nxgep->max_rdcs, p_cfgp->max_grpids, 2116 p_cfgp->start_grpid, 2117 p_cfgp->mac_ldvid, p_cfgp->mif_ldvid, p_cfgp->ser_ldvid)); 2118 2119 NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_use_default_dma_config_n2: " 2120 "p_cfgp p%p start_ldg %d nxgep->max_ldgs %d", 2121 p_cfgp, p_cfgp->start_ldg, p_cfgp->max_ldgs)); 2122 2123 2124 /* 2125 * RDC groups and the beginning RDC group assigned 2126 * to this function. 2127 */ 2128 nrxgp = 2; 2129 p_cfgp->max_rdc_grpids = nrxgp; 2130 p_cfgp->start_rdc_grpid = (nxgep->function_num * nrxgp); 2131 2132 status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 2133 "rx-rdc-grps", nrxgp); 2134 if (status) { 2135 return (NXGE_DDI_FAILED); 2136 } 2137 2138 status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 2139 "rx-rdc-grps-begin", p_cfgp->start_rdc_grpid); 2140 if (status) { 2141 (void) ddi_prop_remove(DDI_DEV_T_NONE, nxgep->dip, 2142 "rx-rdc-grps"); 2143 return (NXGE_DDI_FAILED); 2144 } 2145 2146 NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_use_default_dma_config_n2: " 2147 "p_cfgp $%p # rdc groups %d start rdc group id %d", 2148 p_cfgp, p_cfgp->max_rdc_grpids, 2149 p_cfgp->start_rdc_grpid)); 2150 2151 nxge_set_hw_dma_config(nxgep); 2152 2153 NXGE_DEBUG_MSG((nxgep, OBP_CTL, "<== nxge_use_default_dma_config_n2")); 2154 2155 return (status); 2156 } 2157 2158 static void 2159 nxge_use_cfg_dma_config(p_nxge_t nxgep) 2160 { 2161 int tx_ndmas, rx_ndmas, nrxgp; 2162 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2163 p_nxge_hw_pt_cfg_t p_cfgp; 2164 dev_info_t *dip; 2165 p_nxge_param_t param_arr; 2166 char *prop; 2167 int *prop_val; 2168 uint_t prop_len; 2169 int status; 2170 2171 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_use_cfg_dma_config")); 2172 param_arr = nxgep->param_arr; 2173 2174 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2175 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2176 dip = nxgep->dip; 2177 2178 p_cfgp->function_number = nxgep->function_num; 2179 2180 prop = param_arr[param_txdma_channels_begin].fcode_name; 2181 2182 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop, 2183 &prop_val, &prop_len) == 2184 DDI_PROP_SUCCESS) { 2185 p_cfgp->start_tdc = *prop_val; 2186 ddi_prop_free(prop_val); 2187 } else { 2188 if (nxgep->nports == 2) { 2189 tx_ndmas = (nxgep->function_num * p2_tx_equal[0]); 2190 } else { 2191 tx_ndmas = (nxgep->function_num * p4_tx_equal[0]); 2192 } 2193 status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 2194 prop, tx_ndmas); 2195 p_cfgp->start_tdc = tx_ndmas; 2196 } 2197 2198 prop = param_arr[param_txdma_channels].fcode_name; 2199 2200 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop, 2201 &prop_val, &prop_len) == 2202 DDI_PROP_SUCCESS) { 2203 tx_ndmas = *prop_val; 2204 ddi_prop_free(prop_val); 2205 } else { 2206 if (nxgep->nports == 2) { 2207 tx_ndmas = p2_tx_equal[0]; 2208 } else { 2209 tx_ndmas = p4_tx_equal[0]; 2210 } 2211 status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 2212 prop, tx_ndmas); 2213 } 2214 2215 p_cfgp->max_tdcs = nxgep->max_tdcs = tx_ndmas; 2216 nxgep->tdc_mask = (tx_ndmas - 1); 2217 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_cfg_dma_config: " 2218 "p_cfgp 0x%llx max_tdcs %d nxgep->max_tdcs %d", 2219 p_cfgp, p_cfgp->max_tdcs, nxgep->max_tdcs)); 2220 2221 2222 prop = param_arr[param_rxdma_channels_begin].fcode_name; 2223 2224 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop, 2225 &prop_val, &prop_len) == 2226 DDI_PROP_SUCCESS) { 2227 p_cfgp->start_rdc = *prop_val; 2228 ddi_prop_free(prop_val); 2229 } else { 2230 if (nxgep->nports == 2) { 2231 rx_ndmas = (nxgep->function_num * p2_rx_equal[0]); 2232 } else { 2233 rx_ndmas = (nxgep->function_num * p4_rx_equal[0]); 2234 } 2235 status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 2236 prop, rx_ndmas); 2237 p_cfgp->start_rdc = rx_ndmas; 2238 } 2239 2240 prop = param_arr[param_rxdma_channels].fcode_name; 2241 2242 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop, 2243 &prop_val, &prop_len) == 2244 DDI_PROP_SUCCESS) { 2245 rx_ndmas = *prop_val; 2246 ddi_prop_free(prop_val); 2247 } else { 2248 if (nxgep->nports == 2) { 2249 rx_ndmas = p2_rx_equal[0]; 2250 } else { 2251 rx_ndmas = p4_rx_equal[0]; 2252 } 2253 status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 2254 prop, rx_ndmas); 2255 } 2256 2257 p_cfgp->max_rdcs = nxgep->max_rdcs = rx_ndmas; 2258 2259 prop = param_arr[param_rdc_grps_start].fcode_name; 2260 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop, 2261 &prop_val, &prop_len) == 2262 DDI_PROP_SUCCESS) { 2263 p_cfgp->start_rdc_grpid = *prop_val; 2264 ddi_prop_free(prop_val); 2265 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 2266 "==> nxge_use_default_dma_config: " 2267 "use property " 2268 "start_grpid %d ", 2269 p_cfgp->start_grpid)); 2270 } else { 2271 p_cfgp->start_rdc_grpid = nxgep->function_num; 2272 status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 2273 prop, p_cfgp->start_rdc_grpid); 2274 2275 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 2276 "==> nxge_use_default_dma_config: " 2277 "use default " 2278 "start_grpid %d (same as function #)", 2279 p_cfgp->start_grpid)); 2280 } 2281 2282 prop = param_arr[param_rx_rdc_grps].fcode_name; 2283 2284 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop, 2285 &prop_val, &prop_len) == 2286 DDI_PROP_SUCCESS) { 2287 nrxgp = *prop_val; 2288 ddi_prop_free(prop_val); 2289 } else { 2290 nrxgp = 1; 2291 status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 2292 prop, nrxgp); 2293 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 2294 "==> nxge_use_default_dma_config: " 2295 "num_rdc_grpid not found: use def:# of " 2296 "rdc groups %d\n", nrxgp)); 2297 } 2298 2299 p_cfgp->max_rdc_grpids = nrxgp; 2300 2301 /* 2302 * 2/4 ports have the same hard-wired logical 2303 * groups assigned. 2304 */ 2305 p_cfgp->start_ldg = nxgep->function_num * NXGE_LDGRP_PER_4PORTS; 2306 p_cfgp->max_ldgs = NXGE_LDGRP_PER_4PORTS; 2307 2308 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_default_dma_config: " 2309 "p_cfgp 0x%llx max_rdcs %d nxgep->max_rdcs %d max_grpids %d" 2310 "start_grpid %d", 2311 p_cfgp, p_cfgp->max_rdcs, nxgep->max_rdcs, p_cfgp->max_grpids, 2312 p_cfgp->start_grpid)); 2313 2314 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_cfg_dma_config: " 2315 "p_cfgp 0x%016llx start_ldg %d nxgep->max_ldgs %d " 2316 "start_rdc_grpid %d", 2317 p_cfgp, p_cfgp->start_ldg, p_cfgp->max_ldgs, 2318 p_cfgp->start_rdc_grpid)); 2319 2320 /* add code for individual rdc properties */ 2321 prop = param_arr[param_rxdma_intr_time].fcode_name; 2322 2323 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop, 2324 &prop_val, &prop_len) == 2325 DDI_PROP_SUCCESS) { 2326 if ((prop_len > 0) && (prop_len <= p_cfgp->max_rdcs)) { 2327 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, 2328 nxgep->dip, prop, 2329 prop_val, prop_len); 2330 } 2331 ddi_prop_free(prop_val); 2332 } 2333 prop = param_arr[param_rxdma_intr_pkts].fcode_name; 2334 2335 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop, 2336 &prop_val, &prop_len) == 2337 DDI_PROP_SUCCESS) { 2338 if ((prop_len > 0) && (prop_len <= p_cfgp->max_rdcs)) { 2339 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, 2340 nxgep->dip, prop, 2341 prop_val, prop_len); 2342 } 2343 ddi_prop_free(prop_val); 2344 } 2345 2346 nxge_set_hw_dma_config(nxgep); 2347 #ifdef lint 2348 status = status; 2349 #endif 2350 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_use_cfg_dma_config")); 2351 } 2352 2353 2354 static void 2355 nxge_use_cfg_vlan_class_config(p_nxge_t nxgep) 2356 { 2357 uint_t vlan_cnt; 2358 int *vlan_cfg_val; 2359 int status; 2360 p_nxge_param_t param_arr; 2361 char *prop; 2362 2363 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_use_cfg_vlan_config")); 2364 param_arr = nxgep->param_arr; 2365 prop = param_arr[param_vlan_2rdc_grp].fcode_name; 2366 2367 status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop, 2368 &vlan_cfg_val, &vlan_cnt); 2369 if (status == DDI_PROP_SUCCESS) { 2370 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, 2371 nxgep->dip, prop, 2372 vlan_cfg_val, vlan_cnt); 2373 ddi_prop_free(vlan_cfg_val); 2374 } 2375 nxge_set_hw_vlan_class_config(nxgep); 2376 2377 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_use_cfg_vlan_config")); 2378 2379 } 2380 2381 2382 static void 2383 nxge_use_cfg_mac_class_config(p_nxge_t nxgep) 2384 { 2385 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2386 p_nxge_hw_pt_cfg_t p_cfgp; 2387 uint_t mac_cnt; 2388 int *mac_cfg_val; 2389 int status; 2390 p_nxge_param_t param_arr; 2391 char *prop; 2392 2393 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_cfg_mac_class_config")); 2394 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2395 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2396 p_cfgp->start_mac_entry = 0; 2397 2398 param_arr = nxgep->param_arr; 2399 prop = param_arr[param_mac_2rdc_grp].fcode_name; 2400 2401 switch (nxgep->function_num) { 2402 case 0: 2403 case 1: 2404 /* 10G ports */ 2405 p_cfgp->max_macs = NXGE_MAX_MACS_XMACS; 2406 break; 2407 case 2: 2408 case 3: 2409 /* 1G ports */ 2410 default: 2411 p_cfgp->max_macs = NXGE_MAX_MACS_BMACS; 2412 break; 2413 } 2414 2415 p_cfgp->mac_pref = 1; 2416 p_cfgp->def_mac_rxdma_grpid = p_cfgp->start_rdc_grpid; 2417 2418 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 2419 "== nxge_use_cfg_mac_class_config: " 2420 " mac_pref bit set def_mac_rxdma_grpid %d", 2421 p_cfgp->def_mac_rxdma_grpid)); 2422 2423 status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop, 2424 &mac_cfg_val, &mac_cnt); 2425 if (status == DDI_PROP_SUCCESS) { 2426 if (mac_cnt <= p_cfgp->max_macs) 2427 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, 2428 nxgep->dip, prop, 2429 mac_cfg_val, 2430 mac_cnt); 2431 ddi_prop_free(mac_cfg_val); 2432 } 2433 nxge_set_hw_mac_class_config(nxgep); 2434 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_use_cfg_mac_class_config")); 2435 } 2436 2437 2438 2439 static void 2440 nxge_use_cfg_class_config(p_nxge_t nxgep) 2441 { 2442 nxge_set_hw_class_config(nxgep); 2443 } 2444 2445 2446 /*ARGSUSED*/ 2447 static void 2448 nxge_setup_hw_pciconfig(p_nxge_t nxgep) 2449 { 2450 /* 2451 * Initialize PCI configuration registers if 2452 * required. 2453 */ 2454 } 2455 2456 /*ARGSUSED*/ 2457 static void 2458 nxge_setup_hw_vpd_rom_mac(p_nxge_t nxgep) 2459 { 2460 2461 } 2462 2463 static void 2464 nxge_set_rdc_intr_property(p_nxge_t nxgep) 2465 { 2466 int i; 2467 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2468 #ifdef NXGE_CFG_V2 2469 p_nxge_hw_pt_cfg_t p_cfgp; 2470 p_nxge_param_t param_arr; 2471 uint_t rdc_prop_cnt; 2472 int *rdc_cfg_val; 2473 nxge_rcr_param_t *tout; 2474 nxge_rcr_param_t *threshold; 2475 char *prop; 2476 uint32_t min_val = NXGE_RDC_RCR_TIMEOUT_MIN; 2477 uint32_t max_val = NXGE_RDC_RCR_TIMEOUT_MAX; 2478 #endif 2479 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_set_rdc_intr_property")); 2480 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2481 2482 2483 for (i = 0; i < NXGE_MAX_RDCS; i++) { 2484 p_dma_cfgp->rcr_timeout[i] = nxge_rcr_timeout; 2485 p_dma_cfgp->rcr_threshold[i] = nxge_rcr_threshold; 2486 } 2487 2488 #ifdef NXGE_CFG_V2 2489 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2490 param_arr = nxgep->param_arr; 2491 prop = param_arr[param_rxdma_intr_time].fcode_name; 2492 2493 /* 2494 * 2495 * Format 2496 * 2497 * uint32_t array, each array entry specifying the 2498 * rdc id and the rcr interrupt blanking parameter 2499 * 2500 * bit[30] = enable 2501 * bit[29] = remove 2502 * bits[23-16] = rdc 2503 * bits[15-0] = blanking parameter 2504 */ 2505 2506 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop, 2507 &rdc_cfg_val, &rdc_prop_cnt) == 2508 DDI_PROP_SUCCESS) { 2509 tout = (nxge_rcr_param_t *)rdc_cfg_val; 2510 for (i = 0; i < rdc_prop_cnt; i++) { 2511 if ((tout->rdc < p_cfgp->max_rdcs) && 2512 (tout->cfg_val < NXGE_RDC_RCR_TIMEOUT_MAX) && 2513 (tout->cfg_val >= NXGE_RDC_RCR_TIMEOUT_MIN)) { 2514 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 2515 " nxge_rcr param mapping" 2516 " rdc %d timeout %d", 2517 tout->rdc, tout->cfg_val)); 2518 p_dma_cfgp->rcr_timeout[tout->rdc] = 2519 tout->cfg_val; 2520 } 2521 tout++; 2522 } 2523 ddi_prop_free(rdc_cfg_val); 2524 } 2525 2526 prop = param_arr[param_rxdma_intr_pkts].fcode_name; 2527 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop, 2528 &rdc_cfg_val, &rdc_prop_cnt) == 2529 DDI_PROP_SUCCESS) { 2530 threshold = (nxge_rcr_param_t *)rdc_cfg_val; 2531 for (i = 0; i < rdc_prop_cnt; i++) { 2532 if ((threshold->rdc < p_cfgp->max_rdcs) && 2533 (threshold->cfg_val < max_val) && 2534 (threshold->cfg_val >= min_val)) { 2535 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 2536 " nxge_rcr param rdc %d" 2537 " threshold %x", 2538 threshold->rdc, 2539 threshold->cfg_val)); 2540 p_dma_cfgp->rcr_threshold[threshold->rdc] = 2541 threshold->cfg_val; 2542 } 2543 threshold++; 2544 } 2545 ddi_prop_free(rdc_cfg_val); 2546 } 2547 #endif 2548 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_set_rdc_intr_property")); 2549 } 2550 2551 2552 /*ARGSUSED*/ 2553 static void 2554 nxge_set_hw_dma_config(p_nxge_t nxgep) 2555 { 2556 int i, j, rdc, ndmas, ngrps, bitmap, end, st_rdc; 2557 int32_t status; 2558 uint8_t rdcs_per_grp; 2559 #ifdef NXGE_CFG_V2 2560 int32_t *int_prop_val; 2561 uint_t prop_len; 2562 #endif 2563 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2564 p_nxge_hw_pt_cfg_t p_cfgp; 2565 p_nxge_rdc_grp_t rdc_grp_p; 2566 int rdcgrp_cfg = CFG_NOT_SPECIFIED, rx_quick_cfg; 2567 char *prop, *prop_val; 2568 p_nxge_param_t param_arr; 2569 config_token_t token; 2570 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_set_hw_dma_config")); 2571 2572 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2573 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2574 2575 rdc_grp_p = p_dma_cfgp->rdc_grps; 2576 2577 /* Transmit DMA Channels */ 2578 bitmap = 0; 2579 end = p_cfgp->start_tdc + p_cfgp->max_tdcs; 2580 nxgep->ntdc = p_cfgp->max_tdcs; 2581 p_dma_cfgp->tx_dma_map = 0; 2582 for (i = p_cfgp->start_tdc; i < end; i++) { 2583 bitmap |= (1 << i); 2584 nxgep->tdc[i - p_cfgp->start_tdc] = (uint8_t)i; 2585 } 2586 2587 p_dma_cfgp->tx_dma_map = bitmap; 2588 2589 param_arr = nxgep->param_arr; 2590 2591 /* Assume RDCs are evenly distributed */ 2592 rx_quick_cfg = param_arr[param_rx_quick_cfg].value; 2593 switch (rx_quick_cfg) { 2594 case CFG_NOT_SPECIFIED: 2595 prop = "rxdma-grp-cfg"; 2596 status = ddi_prop_lookup_string(DDI_DEV_T_NONE, 2597 nxgep->dip, 0, 2598 prop, 2599 (char **)&prop_val); 2600 if (status != DDI_PROP_SUCCESS) { 2601 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 2602 " property %s not found", prop)); 2603 rdcgrp_cfg = CFG_L3_DISTRIBUTE; 2604 } else { 2605 token = nxge_get_config_token(prop_val); 2606 switch (token) { 2607 case L2_CLASSIFY: 2608 break; 2609 case CLASSIFY: 2610 case L3_CLASSIFY: 2611 case L3_DISTRIBUTE: 2612 case L3_TCAM: 2613 rdcgrp_cfg = CFG_L3_DISTRIBUTE; 2614 break; 2615 default: 2616 rdcgrp_cfg = CFG_L3_DISTRIBUTE; 2617 break; 2618 } 2619 ddi_prop_free(prop_val); 2620 } 2621 break; 2622 case CFG_L3_WEB: 2623 case CFG_L3_DISTRIBUTE: 2624 case CFG_L2_CLASSIFY: 2625 case CFG_L3_TCAM: 2626 rdcgrp_cfg = rx_quick_cfg; 2627 break; 2628 default: 2629 rdcgrp_cfg = CFG_L3_DISTRIBUTE; 2630 break; 2631 } 2632 2633 /* Receive DMA Channels */ 2634 st_rdc = p_cfgp->start_rdc; 2635 nxgep->nrdc = p_cfgp->max_rdcs; 2636 2637 for (i = 0; i < p_cfgp->max_rdcs; i++) { 2638 nxgep->rdc[i] = i + p_cfgp->start_rdc; 2639 } 2640 2641 switch (rdcgrp_cfg) { 2642 case CFG_L3_DISTRIBUTE: 2643 case CFG_L3_WEB: 2644 case CFG_L3_TCAM: 2645 ndmas = p_cfgp->max_rdcs; 2646 ngrps = 1; 2647 rdcs_per_grp = ndmas/ngrps; 2648 break; 2649 case CFG_L2_CLASSIFY: 2650 ndmas = p_cfgp->max_rdcs / 2; 2651 if (p_cfgp->max_rdcs < 2) 2652 ndmas = 1; 2653 ngrps = 1; 2654 rdcs_per_grp = ndmas/ngrps; 2655 break; 2656 default: 2657 ngrps = p_cfgp->max_rdc_grpids; 2658 ndmas = p_cfgp->max_rdcs; 2659 rdcs_per_grp = ndmas/ngrps; 2660 break; 2661 } 2662 2663 for (i = 0; i < ngrps; i++) { 2664 rdc_grp_p = &p_dma_cfgp->rdc_grps[i]; 2665 rdc_grp_p->start_rdc = st_rdc + i * rdcs_per_grp; 2666 rdc_grp_p->max_rdcs = rdcs_per_grp; 2667 2668 /* default to: 0, 1, 2, 3, ...., 0, 1, 2, 3.... */ 2669 rdc_grp_p->config_method = RDC_TABLE_ENTRY_METHOD_SEQ; 2670 rdc = rdc_grp_p->start_rdc; 2671 for (j = 0; j < NXGE_MAX_RDCS; j++) { 2672 rdc_grp_p->rdc[j] = rdc++; 2673 if (rdc == (rdc_grp_p->start_rdc + rdcs_per_grp)) { 2674 rdc = rdc_grp_p->start_rdc; 2675 } 2676 } 2677 rdc_grp_p->def_rdc = rdc_grp_p->rdc[0]; 2678 rdc_grp_p->flag = 1; /* configured */ 2679 } 2680 2681 /* default RDC */ 2682 #ifdef NXGE_CFG_V2 2683 prop = param_arr[param_default_port_rdc].fcode_name; 2684 2685 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop, 2686 &int_prop_val, &prop_len) == 2687 DDI_PROP_SUCCESS) { 2688 p_cfgp->def_rdc = (uint8_t)*int_prop_val; 2689 ddi_prop_free(int_prop_val); 2690 } else { 2691 p_cfgp->def_rdc = p_cfgp->start_rdc; 2692 2693 } 2694 status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 2695 prop, (int)p_cfgp->def_rdc); 2696 #ifdef NXGE_DEBUG_ERROR 2697 if (status != DDI_PROP_SUCCESS) 2698 NXGE_ERROR_MSG((nxgep, NXGE_NOTE, 2699 " property %s failed update ", prop)); 2700 #endif 2701 #else 2702 p_cfgp->def_rdc = p_cfgp->start_rdc; 2703 #endif 2704 2705 nxgep->def_rdc = p_cfgp->start_rdc; 2706 2707 /* full 18 byte header ? */ 2708 #ifdef NXGE_CFG_V2 2709 prop = param_arr[param_rxdma_full_header].fcode_name; 2710 2711 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop, 2712 &int_prop_val, &prop_len) == 2713 DDI_PROP_SUCCESS) { 2714 p_dma_cfgp->rcr_full_header = (uint8_t)*int_prop_val; 2715 ddi_prop_free(int_prop_val); 2716 } else { 2717 /* enabled by default */ 2718 p_dma_cfgp->rcr_full_header = NXGE_RCR_FULL_HEADER; 2719 2720 } 2721 status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 2722 prop, (int)p_dma_cfgp->rcr_full_header); 2723 #else 2724 p_dma_cfgp->rcr_full_header = NXGE_RCR_FULL_HEADER; 2725 #endif 2726 #ifdef NXGE_CFG_V2 2727 prop = param_arr[param_rxdma_drr_weight].fcode_name; 2728 2729 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop, 2730 &int_prop_val, &prop_len) == 2731 DDI_PROP_SUCCESS) { 2732 p_dma_cfgp->rx_drr_weight = (uint8_t)*int_prop_val; 2733 ddi_prop_free(int_prop_val); 2734 } else { 2735 p_dma_cfgp->rx_drr_weight = PT_DRR_WT_DEFAULT_10G; 2736 if (nxgep->function_num > 1) 2737 p_dma_cfgp->rx_drr_weight = PT_DRR_WT_DEFAULT_1G; 2738 2739 } 2740 status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 2741 prop, 2742 (int)p_dma_cfgp->rx_drr_weight); 2743 #else 2744 p_dma_cfgp->rx_drr_weight = PT_DRR_WT_DEFAULT_10G; 2745 if (nxgep->function_num > 1) 2746 p_dma_cfgp->rx_drr_weight = PT_DRR_WT_DEFAULT_1G; 2747 #endif 2748 2749 2750 #ifdef NXGE_CFG_V2 2751 prop = param_arr[param_rxdma_rbr_size].fcode_name; 2752 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop, 2753 &int_prop_val, &prop_len) == 2754 DDI_PROP_SUCCESS) { 2755 p_dma_cfgp->rbr_size = (uint32_t)*int_prop_val; 2756 if ((p_dma_cfgp->rbr_size < 2757 param_arr[param_rxdma_rbr_size].minimum) || 2758 (p_dma_cfgp->rbr_size > 2759 param_arr[param_rxdma_rbr_size].maximum)) 2760 p_dma_cfgp->rbr_size = nxge_rbr_size; 2761 ddi_prop_free(int_prop_val); 2762 } else { 2763 p_dma_cfgp->rbr_size = nxge_rbr_size; 2764 } 2765 status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 2766 prop, (int)p_dma_cfgp->rbr_size); 2767 #else 2768 p_dma_cfgp->rbr_size = nxge_rbr_size; 2769 #endif 2770 2771 #ifdef NXGE_CFG_V2 2772 prop = param_arr[param_rxdma_rcr_size].fcode_name; 2773 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop, 2774 &int_prop_val, &prop_len) == 2775 DDI_PROP_SUCCESS) { 2776 p_dma_cfgp->rcr_size = (uint32_t)*int_prop_val; 2777 if ((p_dma_cfgp->rcr_size < 2778 param_arr[param_rxdma_rcr_size].minimum) || 2779 (p_dma_cfgp->rcr_size > 2780 param_arr[param_rxdma_rcr_size].maximum)) 2781 p_dma_cfgp->rcr_size = nxge_rcr_size; 2782 ddi_prop_free(int_prop_val); 2783 } else { 2784 p_dma_cfgp->rcr_size = nxge_rcr_size; 2785 } 2786 2787 2788 status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 2789 prop, (int)p_dma_cfgp->rcr_size); 2790 #else 2791 p_dma_cfgp->rcr_size = nxge_rcr_size; 2792 #endif 2793 2794 nxge_set_rdc_intr_property(nxgep); 2795 2796 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_set_hw_dma_config")); 2797 2798 } 2799 2800 2801 2802 boolean_t 2803 nxge_check_rxdma_port_member(p_nxge_t nxgep, uint8_t rdc) 2804 { 2805 2806 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2807 p_nxge_hw_pt_cfg_t p_cfgp; 2808 int status = B_TRUE; 2809 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, "==> nxge_check_rxdma_port_member")); 2810 2811 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2812 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2813 2814 /* Receive DMA Channels */ 2815 if (rdc < p_cfgp->max_rdcs) 2816 status = B_TRUE; 2817 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " <== nxge_check_rxdma_port_member")); 2818 2819 return (status); 2820 } 2821 2822 boolean_t 2823 nxge_check_txdma_port_member(p_nxge_t nxgep, uint8_t tdc) 2824 { 2825 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2826 p_nxge_hw_pt_cfg_t p_cfgp; 2827 int status = B_FALSE; 2828 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, "==> nxge_check_rxdma_port_member")); 2829 2830 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2831 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2832 2833 /* Receive DMA Channels */ 2834 if (tdc < p_cfgp->max_tdcs) 2835 status = B_TRUE; 2836 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " <== nxge_check_rxdma_port_member")); 2837 return (status); 2838 } 2839 2840 2841 /*ARGSUSED*/ 2842 boolean_t 2843 nxge_check_rxdma_rdcgrp_member(p_nxge_t nxgep, uint8_t rdc_grp, uint8_t rdc) 2844 { 2845 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2846 int status = B_TRUE; 2847 p_nxge_rdc_grp_t rdc_grp_p; 2848 2849 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, 2850 " ==> nxge_check_rxdma_rdcgrp_member")); 2851 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " nxge_check_rxdma_rdcgrp_member" 2852 " rdc %d group %d", 2853 rdc, rdc_grp)); 2854 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2855 2856 rdc_grp_p = &p_dma_cfgp->rdc_grps[rdc_grp]; 2857 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " max %d ", 2858 rdc_grp_p->max_rdcs)); 2859 if (rdc >= rdc_grp_p->max_rdcs) { 2860 status = B_FALSE; 2861 } 2862 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, 2863 " <== nxge_check_rxdma_rdcgrp_member")); 2864 return (status); 2865 } 2866 2867 2868 boolean_t 2869 nxge_check_rdcgrp_port_member(p_nxge_t nxgep, uint8_t rdc_grp) 2870 { 2871 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2872 p_nxge_hw_pt_cfg_t p_cfgp; 2873 int status = B_TRUE; 2874 2875 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, "==> nxge_check_rdcgrp_port_member")); 2876 2877 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2878 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2879 2880 if (rdc_grp >= p_cfgp->max_rdc_grpids) 2881 status = B_FALSE; 2882 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " <== nxge_check_rdcgrp_port_member")); 2883 return (status); 2884 2885 } 2886 2887 2888 static void 2889 nxge_set_hw_vlan_class_config(p_nxge_t nxgep) 2890 { 2891 int status, i; 2892 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2893 p_nxge_hw_pt_cfg_t p_cfgp; 2894 p_nxge_param_t param_arr; 2895 uint_t vlan_cnt; 2896 int *vlan_cfg_val; 2897 nxge_param_map_t *vmap; 2898 char *prop; 2899 p_nxge_class_pt_cfg_t p_class_cfgp; 2900 uint32_t good_cfg[32]; 2901 int good_count = 0; 2902 nxge_mv_cfg_t *vlan_tbl; 2903 2904 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_set_hw_vlan_config")); 2905 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2906 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2907 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 2908 2909 param_arr = nxgep->param_arr; 2910 prop = param_arr[param_vlan_2rdc_grp].fcode_name; 2911 2912 /* 2913 * By default, VLAN to RDC group mapping is disabled 2914 * Need to read HW or .conf properties to find out 2915 * if mapping is required 2916 * 2917 * Format 2918 * 2919 * uint32_t array, each array entry specifying the 2920 * VLAN id and the mapping 2921 * 2922 * bit[30] = add 2923 * bit[29] = remove 2924 * bit[28] = preference 2925 * bits[23-16] = rdcgrp 2926 * bits[15-0] = VLAN ID ( ) 2927 */ 2928 for (i = 0; i < NXGE_MAX_VLANS; i++) { 2929 p_class_cfgp->vlan_tbl[i].flag = 0; 2930 } 2931 2932 vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 2933 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop, 2934 &vlan_cfg_val, &vlan_cnt) == 2935 DDI_PROP_SUCCESS) { 2936 for (i = 0; i < vlan_cnt; i++) { 2937 vmap = (nxge_param_map_t *)&vlan_cfg_val[i]; 2938 if ((vmap->param_id) && 2939 (vmap->param_id < NXGE_MAX_VLANS) && 2940 (vmap->map_to < p_cfgp->max_rdc_grpids) && 2941 (vmap->map_to >= (uint8_t)0)) { 2942 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, 2943 " nxge_vlan_config mapping" 2944 " id %d grp %d", 2945 vmap->param_id, vmap->map_to)); 2946 2947 good_cfg[good_count] = vlan_cfg_val[i]; 2948 if (vlan_tbl[vmap->param_id].flag == 0) 2949 good_count++; 2950 vlan_tbl[vmap->param_id].flag = 1; 2951 vlan_tbl[vmap->param_id].rdctbl = 2952 vmap->map_to + p_cfgp->start_rdc_grpid; 2953 vlan_tbl[vmap->param_id].mpr_npr = vmap->pref; 2954 2955 } 2956 } 2957 ddi_prop_free(vlan_cfg_val); 2958 if (good_count != vlan_cnt) { 2959 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, 2960 nxgep->dip, prop, 2961 (int *)good_cfg, good_count); 2962 } 2963 } 2964 #ifdef lint 2965 status = status; 2966 #endif 2967 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_set_hw_vlan_config")); 2968 } 2969 2970 static void 2971 nxge_set_hw_mac_class_config(p_nxge_t nxgep) 2972 { 2973 int status, i; 2974 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2975 p_nxge_hw_pt_cfg_t p_cfgp; 2976 p_nxge_param_t param_arr; 2977 uint_t mac_cnt; 2978 int *mac_cfg_val; 2979 nxge_param_map_t *mac_map; 2980 char *prop; 2981 p_nxge_class_pt_cfg_t p_class_cfgp; 2982 int good_count = 0; 2983 int good_cfg[NXGE_MAX_MACS]; 2984 nxge_mv_cfg_t *mac_host_info; 2985 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_set_hw_mac_config")); 2986 2987 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2988 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2989 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 2990 mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 2991 2992 param_arr = nxgep->param_arr; 2993 prop = param_arr[param_mac_2rdc_grp].fcode_name; 2994 2995 for (i = 0; i < NXGE_MAX_MACS; i++) { 2996 p_class_cfgp->mac_host_info[i].flag = 0; 2997 } 2998 2999 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop, 3000 &mac_cfg_val, &mac_cnt) == 3001 DDI_PROP_SUCCESS) { 3002 for (i = 0; i < mac_cnt; i++) { 3003 mac_map = (nxge_param_map_t *)&mac_cfg_val[i]; 3004 if ((mac_map->param_id < p_cfgp->max_macs) && 3005 (mac_map->map_to < p_cfgp->max_rdc_grpids) && 3006 (mac_map->map_to >= (uint8_t)0)) { 3007 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, 3008 " nxge_mac_config mapping" 3009 " id %d grp %d", 3010 mac_map->param_id, 3011 mac_map->map_to)); 3012 3013 mac_host_info[mac_map->param_id].mpr_npr = 3014 mac_map->pref; 3015 mac_host_info[mac_map->param_id].rdctbl = 3016 mac_map->map_to + 3017 p_cfgp->start_rdc_grpid; 3018 good_cfg[good_count] = mac_cfg_val[i]; 3019 if (mac_host_info[mac_map->param_id].flag == 0) 3020 good_count++; 3021 mac_host_info[mac_map->param_id].flag = 1; 3022 } 3023 } 3024 ddi_prop_free(mac_cfg_val); 3025 if (good_count != mac_cnt) { 3026 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, 3027 nxgep->dip, prop, 3028 good_cfg, good_count); 3029 } 3030 3031 } 3032 #ifdef lint 3033 status = status; 3034 #endif 3035 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_set_hw_mac_config")); 3036 } 3037 3038 3039 static void 3040 nxge_set_hw_class_config(p_nxge_t nxgep) 3041 { 3042 int i; 3043 p_nxge_param_t param_arr; 3044 int *int_prop_val; 3045 uint32_t cfg_value; 3046 char *prop; 3047 p_nxge_class_pt_cfg_t p_class_cfgp; 3048 int start_prop, end_prop; 3049 uint_t prop_cnt; 3050 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_set_hw_class_config")); 3051 3052 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 3053 3054 param_arr = nxgep->param_arr; 3055 3056 start_prop = param_class_opt_ip_usr4; 3057 end_prop = param_class_opt_ipv6_sctp; 3058 3059 for (i = start_prop; i <= end_prop; i++) { 3060 prop = param_arr[i].fcode_name; 3061 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 3062 0, prop, 3063 &int_prop_val, &prop_cnt) == 3064 DDI_PROP_SUCCESS) { 3065 cfg_value = (uint32_t)*int_prop_val; 3066 ddi_prop_free(int_prop_val); 3067 } else { 3068 cfg_value = (uint32_t)param_arr[i].value; 3069 } 3070 p_class_cfgp->class_cfg[i - start_prop] = cfg_value; 3071 } 3072 3073 prop = param_arr[param_h1_init_value].fcode_name; 3074 3075 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop, 3076 &int_prop_val, &prop_cnt) == 3077 DDI_PROP_SUCCESS) { 3078 cfg_value = (uint32_t)*int_prop_val; 3079 ddi_prop_free(int_prop_val); 3080 } else { 3081 cfg_value = (uint32_t)param_arr[param_h1_init_value].value; 3082 } 3083 3084 p_class_cfgp->init_h1 = (uint32_t)cfg_value; 3085 3086 prop = param_arr[param_h2_init_value].fcode_name; 3087 3088 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop, 3089 &int_prop_val, &prop_cnt) == 3090 DDI_PROP_SUCCESS) { 3091 cfg_value = (uint32_t)*int_prop_val; 3092 ddi_prop_free(int_prop_val); 3093 } else { 3094 cfg_value = (uint32_t)param_arr[param_h2_init_value].value; 3095 } 3096 3097 p_class_cfgp->init_h2 = (uint16_t)cfg_value; 3098 3099 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_set_hw_class_config")); 3100 } 3101 3102 /*ARGSUSED*/ 3103 nxge_status_t 3104 nxge_ldgv_init_n2(p_nxge_t nxgep, int *navail_p, int *nrequired_p) 3105 { 3106 int i, maxldvs, maxldgs, start, end, nldvs; 3107 int ldv, endldg; 3108 uint8_t func; 3109 uint8_t channel; 3110 uint8_t chn_start; 3111 boolean_t own_sys_err = B_FALSE, own_fzc = B_FALSE; 3112 p_nxge_dma_pt_cfg_t p_dma_cfgp; 3113 p_nxge_hw_pt_cfg_t p_cfgp; 3114 p_nxge_ldgv_t ldgvp; 3115 p_nxge_ldg_t ldgp, ptr; 3116 p_nxge_ldv_t ldvp; 3117 nxge_status_t status = NXGE_OK; 3118 3119 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2")); 3120 if (!*navail_p) { 3121 *nrequired_p = 0; 3122 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3123 "<== nxge_ldgv_init:no avail")); 3124 return (NXGE_ERROR); 3125 } 3126 3127 /* 3128 * N2/NIU: one logical device owns one logical group. 3129 * and each device/group will be assigned 3130 * one vector by Hypervisor. 3131 */ 3132 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 3133 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 3134 maxldgs = p_cfgp->max_ldgs; 3135 if (!maxldgs) { 3136 /* No devices configured. */ 3137 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_ldgv_init_n2: " 3138 "no logical groups configured.")); 3139 return (NXGE_ERROR); 3140 } else { 3141 maxldvs = maxldgs + 1; 3142 } 3143 3144 /* 3145 * If function zero instance, it needs to handle the 3146 * system and MIF error interrupts. 3147 * MIF interrupt may not be needed for N2/NIU. 3148 */ 3149 func = nxgep->function_num; 3150 if (func == 0) { 3151 own_sys_err = B_TRUE; 3152 if (!p_cfgp->ser_ldvid) { 3153 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3154 "nxge_ldgv_init_n2: func 0, ERR ID not set!")); 3155 } 3156 /* MIF interrupt */ 3157 if (!p_cfgp->mif_ldvid) { 3158 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3159 "nxge_ldgv_init_n2: func 0, MIF ID not set!")); 3160 } 3161 } 3162 3163 /* 3164 * Assume single partition, each function owns mac. 3165 */ 3166 if (!nxge_use_partition) { 3167 own_fzc = B_TRUE; 3168 } 3169 3170 ldgvp = nxgep->ldgvp; 3171 if (ldgvp == NULL) { 3172 ldgvp = KMEM_ZALLOC(sizeof (nxge_ldgv_t), KM_SLEEP); 3173 nxgep->ldgvp = ldgvp; 3174 ldgvp->maxldgs = (uint8_t)maxldgs; 3175 ldgvp->maxldvs = (uint8_t)maxldvs; 3176 ldgp = ldgvp->ldgp = KMEM_ZALLOC(sizeof (nxge_ldg_t) * maxldgs, 3177 KM_SLEEP); 3178 ldvp = ldgvp->ldvp = KMEM_ZALLOC(sizeof (nxge_ldv_t) * maxldvs, 3179 KM_SLEEP); 3180 } else { 3181 ldgp = ldgvp->ldgp; 3182 ldvp = ldgvp->ldvp; 3183 } 3184 3185 ldgvp->ndma_ldvs = p_cfgp->max_tdcs + p_cfgp->max_rdcs; 3186 ldgvp->tmres = NXGE_TIMER_RESO; 3187 3188 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3189 "==> nxge_ldgv_init_n2: maxldvs %d maxldgs %d", 3190 maxldvs, maxldgs)); 3191 /* logical start_ldg is ldv */ 3192 ptr = ldgp; 3193 for (i = 0; i < maxldgs; i++) { 3194 ptr->func = func; 3195 ptr->arm = B_TRUE; 3196 ptr->vldg_index = (uint8_t)i; 3197 ptr->ldg_timer = NXGE_TIMER_LDG; 3198 ptr->ldg = p_cfgp->ldg[i]; 3199 ptr->sys_intr_handler = nxge_intr; 3200 ptr->nldvs = 0; 3201 ptr->ldvp = NULL; 3202 ptr->nxgep = nxgep; 3203 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3204 "==> nxge_ldgv_init_n2: maxldvs %d maxldgs %d " 3205 "ldg %d ldgptr $%p", 3206 maxldvs, maxldgs, ptr->ldg, ptr)); 3207 ptr++; 3208 } 3209 3210 endldg = NXGE_INT_MAX_LDG; 3211 nldvs = 0; 3212 ldgvp->nldvs = 0; 3213 ldgp->ldvp = NULL; 3214 *nrequired_p = 0; 3215 3216 /* 3217 * logical device group table is organized in 3218 * the following order (same as what interrupt 3219 * property has). 3220 * function 0: owns MAC, MIF, error, rx, tx. 3221 * function 1: owns MAC, rx, tx. 3222 */ 3223 3224 if (own_fzc && p_cfgp->mac_ldvid) { 3225 /* Each function should own MAC interrupt */ 3226 ldv = p_cfgp->mac_ldvid; 3227 ldvp->ldv = (uint8_t)ldv; 3228 ldvp->is_mac = B_TRUE; 3229 ldvp->ldv_intr_handler = nxge_mac_intr; 3230 ldvp->ldv_ldf_masks = 0; 3231 ldvp->nxgep = nxgep; 3232 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3233 "==> nxge_ldgv_init_n2(mac): maxldvs %d ldv %d " 3234 "ldg %d ldgptr $%p ldvptr $%p", 3235 maxldvs, ldv, ldgp->ldg, ldgp, ldvp)); 3236 nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p); 3237 nldvs++; 3238 } 3239 3240 if (own_fzc && p_cfgp->mif_ldvid) { 3241 ldv = p_cfgp->mif_ldvid; 3242 ldvp->ldv = (uint8_t)ldv; 3243 ldvp->is_mif = B_TRUE; 3244 ldvp->ldv_intr_handler = nxge_mif_intr; 3245 ldvp->ldv_ldf_masks = 0; 3246 ldvp->nxgep = nxgep; 3247 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3248 "==> nxge_ldgv_init_n2(mif): maxldvs %d ldv %d " 3249 "ldg %d ldgptr $%p ldvptr $%p", 3250 maxldvs, ldv, ldgp->ldg, ldgp, ldvp)); 3251 nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p); 3252 nldvs++; 3253 } 3254 3255 ldv = NXGE_SYS_ERROR_LD; 3256 ldvp->use_timer = B_TRUE; 3257 if (own_sys_err && p_cfgp->ser_ldvid) { 3258 ldv = p_cfgp->ser_ldvid; 3259 /* 3260 * Unmask the system interrupt states. 3261 */ 3262 (void) nxge_fzc_sys_err_mask_set(nxgep, SYS_ERR_SMX_MASK | 3263 SYS_ERR_IPP_MASK | SYS_ERR_TXC_MASK | 3264 SYS_ERR_ZCP_MASK); 3265 } 3266 3267 ldvp->ldv = (uint8_t)ldv; 3268 ldvp->is_syserr = B_TRUE; 3269 ldvp->ldv_intr_handler = nxge_syserr_intr; 3270 ldvp->ldv_ldf_masks = 0; 3271 ldvp->nxgep = nxgep; 3272 ldgvp->ldvp_syserr = ldvp; 3273 3274 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3275 "==> nxge_ldgv_init_n2(syserr): maxldvs %d ldv %d " 3276 "ldg %d ldgptr $%p ldvptr p%p", 3277 maxldvs, ldv, ldgp->ldg, ldgp, ldvp)); 3278 3279 if (own_sys_err && p_cfgp->ser_ldvid) { 3280 (void) nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p); 3281 } else { 3282 ldvp++; 3283 } 3284 3285 nldvs++; 3286 3287 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2: " 3288 "(before rx) func %d nldvs %d navail %d nrequired %d", 3289 func, nldvs, *navail_p, *nrequired_p)); 3290 3291 /* 3292 * Receive DMA channels. 3293 */ 3294 channel = p_cfgp->start_rdc; 3295 start = p_cfgp->start_rdc + NXGE_RDMA_LD_START; 3296 end = start + p_cfgp->max_rdcs; 3297 chn_start = p_cfgp->ldg_chn_start; 3298 /* 3299 * Start with RDC to configure logical devices for each group. 3300 */ 3301 for (i = 0, ldv = start; ldv < end; i++, ldv++, chn_start++) { 3302 ldvp->is_rxdma = B_TRUE; 3303 ldvp->ldv = (uint8_t)ldv; 3304 ldvp->channel = channel++; 3305 ldvp->vdma_index = (uint8_t)i; 3306 ldvp->ldv_intr_handler = nxge_rx_intr; 3307 ldvp->ldv_ldf_masks = 0; 3308 ldvp->nxgep = nxgep; 3309 ldgp->ldg = p_cfgp->ldg[chn_start]; 3310 3311 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3312 "==> nxge_ldgv_init_n2(rx%d): maxldvs %d ldv %d " 3313 "ldg %d ldgptr 0x%016llx ldvptr 0x%016llx", 3314 i, maxldvs, ldv, ldgp->ldg, ldgp, ldvp)); 3315 nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p); 3316 nldvs++; 3317 } 3318 3319 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2: " 3320 "func %d nldvs %d navail %d nrequired %d", 3321 func, nldvs, *navail_p, *nrequired_p)); 3322 3323 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2: " 3324 "func %d nldvs %d navail %d nrequired %d ldgp 0x%llx " 3325 "ldvp 0x%llx", 3326 func, nldvs, *navail_p, *nrequired_p, ldgp, ldvp)); 3327 /* 3328 * Transmit DMA channels. 3329 */ 3330 channel = p_cfgp->start_tdc; 3331 start = p_cfgp->start_tdc + NXGE_TDMA_LD_START; 3332 end = start + p_cfgp->max_tdcs; 3333 for (i = 0, ldv = start; ldv < end; i++, ldv++, chn_start++) { 3334 ldvp->is_txdma = B_TRUE; 3335 ldvp->ldv = (uint8_t)ldv; 3336 ldvp->channel = channel++; 3337 ldvp->vdma_index = (uint8_t)i; 3338 ldvp->ldv_intr_handler = nxge_tx_intr; 3339 ldvp->ldv_ldf_masks = 0; 3340 ldgp->ldg = p_cfgp->ldg[chn_start]; 3341 ldvp->nxgep = nxgep; 3342 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3343 "==> nxge_ldgv_init_n2(tx%d): maxldvs %d ldv %d " 3344 "ldg %d ldgptr 0x%016llx ldvptr 0x%016llx", 3345 i, maxldvs, ldv, ldgp->ldg, ldgp, ldvp)); 3346 nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p); 3347 nldvs++; 3348 } 3349 3350 ldgvp->ldg_intrs = *nrequired_p; 3351 ldgvp->nldvs = (uint8_t)nldvs; 3352 3353 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2: " 3354 "func %d nldvs %d maxgrps %d navail %d nrequired %d", 3355 func, nldvs, maxldgs, *navail_p, *nrequired_p)); 3356 3357 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_ldgv_init_n2")); 3358 3359 return (status); 3360 } 3361 3362 /* 3363 * Interrupts related interface functions. 3364 */ 3365 nxge_status_t 3366 nxge_ldgv_init(p_nxge_t nxgep, int *navail_p, int *nrequired_p) 3367 { 3368 int i, maxldvs, maxldgs, start, end, nldvs; 3369 int ldv, ldg, endldg, ngrps; 3370 uint8_t func; 3371 uint8_t channel; 3372 boolean_t own_sys_err = B_FALSE, own_fzc = B_FALSE; 3373 p_nxge_dma_pt_cfg_t p_dma_cfgp; 3374 p_nxge_hw_pt_cfg_t p_cfgp; 3375 p_nxge_ldgv_t ldgvp; 3376 p_nxge_ldg_t ldgp, ptr; 3377 p_nxge_ldv_t ldvp; 3378 nxge_status_t status = NXGE_OK; 3379 3380 3381 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init")); 3382 if (!*navail_p) { 3383 *nrequired_p = 0; 3384 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3385 "<== nxge_ldgv_init:no avail")); 3386 return (NXGE_ERROR); 3387 } 3388 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 3389 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 3390 3391 nldvs = p_cfgp->max_tdcs + p_cfgp->max_rdcs; 3392 3393 /* 3394 * If function zero instance, it needs to handle the 3395 * system error interrupts. 3396 */ 3397 func = nxgep->function_num; 3398 if (func == 0) { 3399 nldvs++; 3400 own_sys_err = B_TRUE; 3401 } else { 3402 /* use timer */ 3403 nldvs++; 3404 } 3405 3406 /* 3407 * Assume single partition, each function owns mac. 3408 */ 3409 if (!nxge_use_partition) { 3410 /* mac */ 3411 nldvs++; 3412 /* MIF */ 3413 nldvs++; 3414 own_fzc = B_TRUE; 3415 } 3416 3417 maxldvs = nldvs; 3418 maxldgs = p_cfgp->max_ldgs; 3419 if (!maxldvs || !maxldgs) { 3420 /* No devices configured. */ 3421 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_ldgv_init: " 3422 "no logical devices or groups configured.")); 3423 return (NXGE_ERROR); 3424 } 3425 ldgvp = nxgep->ldgvp; 3426 if (ldgvp == NULL) { 3427 ldgvp = KMEM_ZALLOC(sizeof (nxge_ldgv_t), KM_SLEEP); 3428 nxgep->ldgvp = ldgvp; 3429 ldgvp->maxldgs = (uint8_t)maxldgs; 3430 ldgvp->maxldvs = (uint8_t)maxldvs; 3431 ldgp = ldgvp->ldgp = KMEM_ZALLOC(sizeof (nxge_ldg_t) * maxldgs, 3432 KM_SLEEP); 3433 ldvp = ldgvp->ldvp = KMEM_ZALLOC(sizeof (nxge_ldv_t) * maxldvs, 3434 KM_SLEEP); 3435 } 3436 3437 ldgvp->ndma_ldvs = p_cfgp->max_tdcs + p_cfgp->max_rdcs; 3438 ldgvp->tmres = NXGE_TIMER_RESO; 3439 3440 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3441 "==> nxge_ldgv_init: maxldvs %d maxldgs %d nldvs %d", 3442 maxldvs, maxldgs, nldvs)); 3443 ldg = p_cfgp->start_ldg; 3444 ptr = ldgp; 3445 for (i = 0; i < maxldgs; i++) { 3446 ptr->func = func; 3447 ptr->arm = B_TRUE; 3448 ptr->vldg_index = (uint8_t)i; 3449 ptr->ldg_timer = NXGE_TIMER_LDG; 3450 ptr->ldg = ldg++; 3451 ptr->sys_intr_handler = nxge_intr; 3452 ptr->nldvs = 0; 3453 ptr->nxgep = nxgep; 3454 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3455 "==> nxge_ldgv_init: maxldvs %d maxldgs %d ldg %d", 3456 maxldvs, maxldgs, ptr->ldg)); 3457 ptr++; 3458 } 3459 3460 ldg = p_cfgp->start_ldg; 3461 if (maxldgs > *navail_p) { 3462 ngrps = *navail_p; 3463 } else { 3464 ngrps = maxldgs; 3465 } 3466 endldg = ldg + ngrps; 3467 3468 /* 3469 * Receive DMA channels. 3470 */ 3471 channel = p_cfgp->start_rdc; 3472 start = p_cfgp->start_rdc + NXGE_RDMA_LD_START; 3473 end = start + p_cfgp->max_rdcs; 3474 nldvs = 0; 3475 ldgvp->nldvs = 0; 3476 ldgp->ldvp = NULL; 3477 *nrequired_p = 0; 3478 3479 /* 3480 * Start with RDC to configure logical devices for each group. 3481 */ 3482 for (i = 0, ldv = start; ldv < end; i++, ldv++) { 3483 ldvp->is_rxdma = B_TRUE; 3484 ldvp->ldv = (uint8_t)ldv; 3485 /* If non-seq needs to change the following code */ 3486 ldvp->channel = channel++; 3487 ldvp->vdma_index = (uint8_t)i; 3488 ldvp->ldv_intr_handler = nxge_rx_intr; 3489 ldvp->ldv_ldf_masks = 0; 3490 ldvp->use_timer = B_FALSE; 3491 ldvp->nxgep = nxgep; 3492 nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p); 3493 nldvs++; 3494 } 3495 /* 3496 * Transmit DMA channels. 3497 */ 3498 channel = p_cfgp->start_tdc; 3499 start = p_cfgp->start_tdc + NXGE_TDMA_LD_START; 3500 end = start + p_cfgp->max_tdcs; 3501 for (i = 0, ldv = start; ldv < end; i++, ldv++) { 3502 ldvp->is_txdma = B_TRUE; 3503 ldvp->ldv = (uint8_t)ldv; 3504 ldvp->channel = channel++; 3505 ldvp->vdma_index = (uint8_t)i; 3506 ldvp->ldv_intr_handler = nxge_tx_intr; 3507 ldvp->ldv_ldf_masks = 0; 3508 ldvp->use_timer = B_FALSE; 3509 ldvp->nxgep = nxgep; 3510 nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p); 3511 nldvs++; 3512 } 3513 3514 if (own_fzc) { 3515 ldv = NXGE_MIF_LD; 3516 ldvp->ldv = (uint8_t)ldv; 3517 ldvp->is_mif = B_TRUE; 3518 ldvp->ldv_intr_handler = nxge_mif_intr; 3519 ldvp->ldv_ldf_masks = 0; 3520 ldvp->use_timer = B_FALSE; 3521 ldvp->nxgep = nxgep; 3522 nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p); 3523 nldvs++; 3524 } 3525 3526 /* 3527 * MAC port (function zero control) 3528 */ 3529 if (own_fzc) { 3530 ldvp->is_mac = B_TRUE; 3531 ldvp->ldv_intr_handler = nxge_mac_intr; 3532 ldvp->ldv_ldf_masks = 0; 3533 ldv = func + NXGE_MAC_LD_START; 3534 ldvp->ldv = (uint8_t)ldv; 3535 ldvp->use_timer = B_FALSE; 3536 ldvp->nxgep = nxgep; 3537 nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p); 3538 nldvs++; 3539 } 3540 3541 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init: " 3542 "func %d nldvs %d navail %d nrequired %d", 3543 func, nldvs, *navail_p, *nrequired_p)); 3544 /* 3545 * Function 0 owns system error interrupts. 3546 */ 3547 ldvp->use_timer = B_TRUE; 3548 if (own_sys_err) { 3549 ldv = NXGE_SYS_ERROR_LD; 3550 ldvp->ldv = (uint8_t)ldv; 3551 ldvp->is_syserr = B_TRUE; 3552 ldvp->ldv_intr_handler = nxge_syserr_intr; 3553 ldvp->ldv_ldf_masks = 0; 3554 ldvp->nxgep = nxgep; 3555 ldgvp->ldvp_syserr = ldvp; 3556 /* 3557 * Unmask the system interrupt states. 3558 */ 3559 (void) nxge_fzc_sys_err_mask_set(nxgep, SYS_ERR_SMX_MASK | 3560 SYS_ERR_IPP_MASK | SYS_ERR_TXC_MASK | 3561 SYS_ERR_ZCP_MASK); 3562 3563 (void) nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p); 3564 nldvs++; 3565 } else { 3566 ldv = NXGE_SYS_ERROR_LD; 3567 ldvp->ldv = (uint8_t)ldv; 3568 ldvp->is_syserr = B_TRUE; 3569 ldvp->ldv_intr_handler = nxge_syserr_intr; 3570 ldvp->nxgep = nxgep; 3571 ldvp->ldv_ldf_masks = 0; 3572 ldgvp->ldvp_syserr = ldvp; 3573 } 3574 3575 ldgvp->ldg_intrs = *nrequired_p; 3576 3577 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init: " 3578 "func %d nldvs %d navail %d nrequired %d", 3579 func, nldvs, *navail_p, *nrequired_p)); 3580 3581 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_ldgv_init")); 3582 3583 return (status); 3584 } 3585 3586 nxge_status_t 3587 nxge_ldgv_uninit(p_nxge_t nxgep) 3588 { 3589 p_nxge_ldgv_t ldgvp; 3590 3591 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_uninit")); 3592 ldgvp = nxgep->ldgvp; 3593 if (ldgvp == NULL) { 3594 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_ldgv_uninit: " 3595 "no logical group configured.")); 3596 return (NXGE_OK); 3597 } 3598 3599 if (ldgvp->ldgp) { 3600 KMEM_FREE(ldgvp->ldgp, sizeof (nxge_ldg_t) * ldgvp->maxldgs); 3601 } 3602 if (ldgvp->ldvp) { 3603 KMEM_FREE(ldgvp->ldvp, sizeof (nxge_ldv_t) * ldgvp->maxldvs); 3604 } 3605 3606 KMEM_FREE(ldgvp, sizeof (nxge_ldgv_t)); 3607 nxgep->ldgvp = NULL; 3608 3609 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_ldgv_uninit")); 3610 3611 return (NXGE_OK); 3612 } 3613 3614 nxge_status_t 3615 nxge_intr_ldgv_init(p_nxge_t nxgep) 3616 { 3617 nxge_status_t status = NXGE_OK; 3618 3619 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr_ldgv_init")); 3620 /* 3621 * Configure the logical device group numbers, state vectors 3622 * and interrupt masks for each logical device. 3623 */ 3624 status = nxge_fzc_intr_init(nxgep); 3625 3626 /* 3627 * Configure logical device masks and timers. 3628 */ 3629 status = nxge_intr_mask_mgmt(nxgep); 3630 3631 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr_ldgv_init")); 3632 return (status); 3633 } 3634 3635 nxge_status_t 3636 nxge_intr_mask_mgmt(p_nxge_t nxgep) 3637 { 3638 p_nxge_ldgv_t ldgvp; 3639 p_nxge_ldg_t ldgp; 3640 p_nxge_ldv_t ldvp; 3641 npi_handle_t handle; 3642 int i, j; 3643 npi_status_t rs = NPI_SUCCESS; 3644 3645 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr_mask_mgmt")); 3646 3647 if ((ldgvp = nxgep->ldgvp) == NULL) { 3648 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3649 "<== nxge_intr_mask_mgmt: Null ldgvp")); 3650 return (NXGE_ERROR); 3651 } 3652 handle = NXGE_DEV_NPI_HANDLE(nxgep); 3653 ldgp = ldgvp->ldgp; 3654 ldvp = ldgvp->ldvp; 3655 if (ldgp == NULL || ldvp == NULL) { 3656 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3657 "<== nxge_intr_mask_mgmt: Null ldgp or ldvp")); 3658 return (NXGE_ERROR); 3659 } 3660 3661 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3662 "==> nxge_intr_mask_mgmt: # of intrs %d ", ldgvp->ldg_intrs)); 3663 /* Initialize masks. */ 3664 if (nxgep->niu_type != N2_NIU) { 3665 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3666 "==> nxge_intr_mask_mgmt(Neptune): # intrs %d ", 3667 ldgvp->ldg_intrs)); 3668 for (i = 0; i < ldgvp->ldg_intrs; i++, ldgp++) { 3669 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3670 "==> nxge_intr_mask_mgmt(Neptune): # ldv %d " 3671 "in group %d", ldgp->nldvs, ldgp->ldg)); 3672 for (j = 0; j < ldgp->nldvs; j++, ldvp++) { 3673 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3674 "==> nxge_intr_mask_mgmt: set ldv # %d " 3675 "for ldg %d", ldvp->ldv, ldgp->ldg)); 3676 rs = npi_intr_mask_set(handle, ldvp->ldv, 3677 ldvp->ldv_ldf_masks); 3678 if (rs != NPI_SUCCESS) { 3679 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3680 "<== nxge_intr_mask_mgmt: " 3681 "set mask failed " 3682 " rs 0x%x ldv %d mask 0x%x", 3683 rs, ldvp->ldv, 3684 ldvp->ldv_ldf_masks)); 3685 return (NXGE_ERROR | rs); 3686 } 3687 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3688 "==> nxge_intr_mask_mgmt: " 3689 "set mask OK " 3690 " rs 0x%x ldv %d mask 0x%x", 3691 rs, ldvp->ldv, 3692 ldvp->ldv_ldf_masks)); 3693 } 3694 } 3695 } 3696 3697 ldgp = ldgvp->ldgp; 3698 /* Configure timer and arm bit */ 3699 for (i = 0; i < nxgep->ldgvp->ldg_intrs; i++, ldgp++) { 3700 rs = npi_intr_ldg_mgmt_set(handle, ldgp->ldg, 3701 ldgp->arm, ldgp->ldg_timer); 3702 if (rs != NPI_SUCCESS) { 3703 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3704 "<== nxge_intr_mask_mgmt: " 3705 "set timer failed " 3706 " rs 0x%x dg %d timer 0x%x", 3707 rs, ldgp->ldg, ldgp->ldg_timer)); 3708 return (NXGE_ERROR | rs); 3709 } 3710 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3711 "==> nxge_intr_mask_mgmt: " 3712 "set timer OK " 3713 " rs 0x%x ldg %d timer 0x%x", 3714 rs, ldgp->ldg, ldgp->ldg_timer)); 3715 } 3716 3717 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_fzc_intr_mask_mgmt")); 3718 return (NXGE_OK); 3719 } 3720 3721 nxge_status_t 3722 nxge_intr_mask_mgmt_set(p_nxge_t nxgep, boolean_t on) 3723 { 3724 p_nxge_ldgv_t ldgvp; 3725 p_nxge_ldg_t ldgp; 3726 p_nxge_ldv_t ldvp; 3727 npi_handle_t handle; 3728 int i, j; 3729 npi_status_t rs = NPI_SUCCESS; 3730 3731 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3732 "==> nxge_intr_mask_mgmt_set (%d)", on)); 3733 3734 if (nxgep->niu_type == N2_NIU) { 3735 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3736 "<== nxge_intr_mask_mgmt_set (%d) not set (N2/NIU)", 3737 on)); 3738 return (NXGE_ERROR); 3739 3740 } 3741 if ((ldgvp = nxgep->ldgvp) == NULL) { 3742 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3743 "==> nxge_intr_mask_mgmt_set: Null ldgvp")); 3744 return (NXGE_ERROR); 3745 } 3746 handle = NXGE_DEV_NPI_HANDLE(nxgep); 3747 ldgp = ldgvp->ldgp; 3748 ldvp = ldgvp->ldvp; 3749 if (ldgp == NULL || ldvp == NULL) { 3750 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3751 "<== nxge_intr_mask_mgmt_set: Null ldgp or ldvp")); 3752 return (NXGE_ERROR); 3753 } 3754 3755 /* set masks. */ 3756 for (i = 0; i < ldgvp->ldg_intrs; i++, ldgp++) { 3757 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3758 "==> nxge_intr_mask_mgmt_set: flag %d ldg %d" 3759 "set mask nldvs %d", on, ldgp->ldg, ldgp->nldvs)); 3760 for (j = 0; j < ldgp->nldvs; j++, ldvp++) { 3761 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3762 "==> nxge_intr_mask_mgmt_set: " 3763 "for %d %d flag %d", i, j, on)); 3764 if (on) { 3765 ldvp->ldv_ldf_masks = 0; 3766 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3767 "==> nxge_intr_mask_mgmt_set: " 3768 "ON mask off")); 3769 } else if (!on) { 3770 ldvp->ldv_ldf_masks = (uint8_t)LD_IM1_MASK; 3771 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3772 "==> nxge_intr_mask_mgmt_set:mask on")); 3773 } 3774 rs = npi_intr_mask_set(handle, ldvp->ldv, 3775 ldvp->ldv_ldf_masks); 3776 if (rs != NPI_SUCCESS) { 3777 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3778 "==> nxge_intr_mask_mgmt_set: " 3779 "set mask failed " 3780 " rs 0x%x ldv %d mask 0x%x", 3781 rs, ldvp->ldv, ldvp->ldv_ldf_masks)); 3782 return (NXGE_ERROR | rs); 3783 } 3784 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3785 "==> nxge_intr_mask_mgmt_set: flag %d" 3786 "set mask OK " 3787 " ldv %d mask 0x%x", 3788 on, ldvp->ldv, ldvp->ldv_ldf_masks)); 3789 } 3790 } 3791 3792 ldgp = ldgvp->ldgp; 3793 /* set the arm bit */ 3794 for (i = 0; i < nxgep->ldgvp->ldg_intrs; i++, ldgp++) { 3795 if (on && !ldgp->arm) { 3796 ldgp->arm = B_TRUE; 3797 } else if (!on && ldgp->arm) { 3798 ldgp->arm = B_FALSE; 3799 } 3800 rs = npi_intr_ldg_mgmt_set(handle, ldgp->ldg, 3801 ldgp->arm, ldgp->ldg_timer); 3802 if (rs != NPI_SUCCESS) { 3803 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3804 "<== nxge_intr_mask_mgmt_set: " 3805 "set timer failed " 3806 " rs 0x%x ldg %d timer 0x%x", 3807 rs, ldgp->ldg, ldgp->ldg_timer)); 3808 return (NXGE_ERROR | rs); 3809 } 3810 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3811 "==> nxge_intr_mask_mgmt_set: OK (flag %d) " 3812 "set timer " 3813 " ldg %d timer 0x%x", 3814 on, ldgp->ldg, ldgp->ldg_timer)); 3815 } 3816 3817 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr_mask_mgmt_set")); 3818 return (NXGE_OK); 3819 } 3820 3821 static nxge_status_t 3822 nxge_get_mac_addr_properties(p_nxge_t nxgep) 3823 { 3824 uchar_t *prop_val; 3825 uint_t prop_len; 3826 uint_t i; 3827 uint8_t func_num; 3828 uint8_t num_macs; 3829 3830 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_get_mac_addr_properties ")); 3831 3832 #if defined(_BIG_ENDIAN) 3833 /* 3834 * Get the ethernet address. 3835 */ 3836 (void) localetheraddr((struct ether_addr *)NULL, &nxgep->ouraddr); 3837 3838 /* 3839 * Check if it is an adapter with its own local mac address 3840 * If it is present, override the system mac address. 3841 */ 3842 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0, 3843 "local-mac-address", &prop_val, 3844 &prop_len) == DDI_PROP_SUCCESS) { 3845 if (prop_len == ETHERADDRL) { 3846 nxgep->factaddr = *(p_ether_addr_t)prop_val; 3847 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "Local mac address = " 3848 "%02x:%02x:%02x:%02x:%02x:%02x", 3849 prop_val[0], prop_val[1], prop_val[2], 3850 prop_val[3], prop_val[4], prop_val[5])); 3851 } 3852 ddi_prop_free(prop_val); 3853 } 3854 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0, 3855 "local-mac-address?", &prop_val, 3856 &prop_len) == DDI_PROP_SUCCESS) { 3857 if (strncmp("true", (caddr_t)prop_val, 3858 (size_t)prop_len) == 0) { 3859 nxgep->ouraddr = nxgep->factaddr; 3860 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 3861 "Using local MAC address")); 3862 } 3863 ddi_prop_free(prop_val); 3864 } else { 3865 nxgep->ouraddr = nxgep->factaddr; 3866 } 3867 #else 3868 (void) nxge_espc_mac_addrs_get(nxgep); 3869 nxgep->ouraddr = nxgep->factaddr; 3870 #endif 3871 3872 func_num = nxgep->function_num; 3873 3874 /* NIU does not need max_num_mmac */ 3875 if (nxgep->niu_type == NEPTUNE || nxgep->niu_type == NEPTUNE_2) { 3876 if (nxge_espc_num_macs_get(nxgep, &num_macs) == NXGE_OK) { 3877 nxgep->nxge_mmac_info.max_num_mmac = num_macs; 3878 } else { 3879 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 3880 "nxge_get_mac_addr_properties, espc access failed")); 3881 return (NXGE_ERROR); 3882 } 3883 } 3884 3885 /* 3886 * Note: mac-addresses of n2-niu is the list of mac addresses 3887 * for a port. #mac-addresses stored in Neptune's SEEPROM is 3888 * the total number of MAC addresses allocated for a board. 3889 */ 3890 if (nxgep->niu_type == N2_NIU) { 3891 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0, 3892 "mac-addresses", &prop_val, &prop_len) == 3893 DDI_PROP_SUCCESS) { 3894 /* 3895 * XAUI may have up to 18 MACs, more than the XMAC can 3896 * use (1 unique MAC plus 16 alternate MACs) 3897 */ 3898 nxgep->nxge_mmac_info.num_mmac = prop_len / 6; 3899 if (nxgep->nxge_mmac_info.num_mmac > 3900 XMAC_MAX_ALT_ADDR_ENTRY + 1) { 3901 nxgep->nxge_mmac_info.num_mmac = 3902 XMAC_MAX_ALT_ADDR_ENTRY + 1; 3903 } 3904 ddi_prop_free(prop_val); 3905 } 3906 } else { 3907 nxgep->nxge_mmac_info.num_mmac 3908 = nxgep->nxge_mmac_info.max_num_mmac >> 3909 (nxgep->nports >> 1); 3910 } 3911 3912 for (i = 0; i < nxgep->nxge_mmac_info.num_mmac - 1; ++i) { 3913 /* Initialze all mac addr. to "AVAILABLE" state */ 3914 nxgep->nxge_mmac_info.rsv_mmac[i] = B_FALSE; 3915 /* 3916 * XMAC: Disable alter MAC address comparison only 3917 * (XMAC's unique MAC comparison is always 3918 * enabled. 3919 * BMAC: (Neptune only) Disable both unique and 3920 * alter MAC address comparison 3921 */ 3922 (void) npi_mac_altaddr_disable(nxgep->npi_handle, 3923 NXGE_GET_PORT_NUM(func_num), i); 3924 } 3925 3926 /* 3927 * Initialize alt. mac addr. in the mac pool 3928 */ 3929 (void) nxge_init_mmac(nxgep); 3930 3931 return (NXGE_OK); 3932 } 3933 3934 void 3935 nxge_get_xcvr_properties(p_nxge_t nxgep) 3936 { 3937 uchar_t *prop_val; 3938 uint_t prop_len; 3939 3940 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_get_xcvr_properties")); 3941 3942 /* 3943 * Read the type of physical layer interface being used. 3944 */ 3945 nxgep->statsp->mac_stats.xcvr_inuse = INT_MII_XCVR; 3946 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0, 3947 "phy-type", &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 3948 if (strncmp("pcs", (caddr_t)prop_val, (size_t)prop_len) == 0) { 3949 nxgep->statsp->mac_stats.xcvr_inuse = PCS_XCVR; 3950 } else { 3951 nxgep->statsp->mac_stats.xcvr_inuse = INT_MII_XCVR; 3952 } 3953 ddi_prop_free(prop_val); 3954 } else if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0, 3955 "phy-interface", &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 3956 if (strncmp("pcs", (caddr_t)prop_val, (size_t)prop_len) == 0) { 3957 nxgep->statsp->mac_stats.xcvr_inuse = PCS_XCVR; 3958 } else { 3959 nxgep->statsp->mac_stats.xcvr_inuse = INT_MII_XCVR; 3960 } 3961 ddi_prop_free(prop_val); 3962 } 3963 } 3964 3965 /* 3966 * Static functions start here. 3967 */ 3968 static void 3969 nxge_ldgv_setup(p_nxge_ldg_t *ldgp, p_nxge_ldv_t *ldvp, uint8_t ldv, 3970 uint8_t endldg, int *ngrps) 3971 { 3972 NXGE_DEBUG_MSG((NULL, INT_CTL, "==> nxge_ldgv_setup")); 3973 /* Assign the group number for each device. */ 3974 (*ldvp)->ldg_assigned = (*ldgp)->ldg; 3975 (*ldvp)->ldgp = *ldgp; 3976 (*ldvp)->ldv = ldv; 3977 3978 NXGE_DEBUG_MSG((NULL, INT_CTL, "==> nxge_ldgv_setup: " 3979 "ldv %d endldg %d ldg %d, ldvp $%p", 3980 ldv, endldg, (*ldgp)->ldg, (*ldgp)->ldvp)); 3981 3982 (*ldgp)->nldvs++; 3983 if ((*ldgp)->ldg == (endldg - 1)) { 3984 if ((*ldgp)->ldvp == NULL) { 3985 (*ldgp)->ldvp = *ldvp; 3986 *ngrps += 1; 3987 NXGE_DEBUG_MSG((NULL, INT_CTL, 3988 "==> nxge_ldgv_setup: ngrps %d", *ngrps)); 3989 } 3990 NXGE_DEBUG_MSG((NULL, INT_CTL, 3991 "==> nxge_ldgv_setup: ldvp $%p ngrps %d", 3992 *ldvp, *ngrps)); 3993 ++*ldvp; 3994 } else { 3995 (*ldgp)->ldvp = *ldvp; 3996 *ngrps += 1; 3997 NXGE_DEBUG_MSG((NULL, INT_CTL, "==> nxge_ldgv_setup(done): " 3998 "ldv %d endldg %d ldg %d, ldvp $%p", 3999 ldv, endldg, (*ldgp)->ldg, (*ldgp)->ldvp)); 4000 (*ldvp) = ++*ldvp; 4001 (*ldgp) = ++*ldgp; 4002 NXGE_DEBUG_MSG((NULL, INT_CTL, 4003 "==> nxge_ldgv_setup: new ngrps %d", *ngrps)); 4004 } 4005 4006 NXGE_DEBUG_MSG((NULL, INT_CTL, "==> nxge_ldgv_setup: " 4007 "ldv %d ldvp $%p endldg %d ngrps %d", 4008 ldv, ldvp, endldg, *ngrps)); 4009 4010 NXGE_DEBUG_MSG((NULL, INT_CTL, "<== nxge_ldgv_setup")); 4011 } 4012 4013 /* 4014 * Note: This function assume the following distribution of mac 4015 * addresses among 4 ports in neptune: 4016 * 4017 * ------------- 4018 * 0| |0 - local-mac-address for fn 0 4019 * ------------- 4020 * 1| |1 - local-mac-address for fn 1 4021 * ------------- 4022 * 2| |2 - local-mac-address for fn 2 4023 * ------------- 4024 * 3| |3 - local-mac-address for fn 3 4025 * ------------- 4026 * | |4 - Start of alt. mac addr. for fn 0 4027 * | | 4028 * | | 4029 * | |10 4030 * -------------- 4031 * | |11 - Start of alt. mac addr. for fn 1 4032 * | | 4033 * | | 4034 * | |17 4035 * -------------- 4036 * | |18 - Start of alt. mac addr. for fn 2 4037 * | | 4038 * | | 4039 * | |24 4040 * -------------- 4041 * | |25 - Start of alt. mac addr. for fn 3 4042 * | | 4043 * | | 4044 * | |31 4045 * -------------- 4046 * 4047 * For N2/NIU the mac addresses is from XAUI card. 4048 */ 4049 4050 static void 4051 nxge_init_mmac(p_nxge_t nxgep) 4052 { 4053 int i; 4054 uint8_t func_num; 4055 uint16_t *base_mmac_addr; 4056 uint32_t first_alt_mac_ls4b; 4057 uint16_t *mmac_addr; 4058 uint32_t base_mac_ls4b; /* least significant 4 bytes */ 4059 nxge_mmac_t *mac_poolp; 4060 npi_mac_addr_t mac_addr; 4061 4062 func_num = nxgep->function_num; 4063 base_mmac_addr = (uint16_t *)&nxgep->factaddr; 4064 mac_poolp = (nxge_mmac_t *)&nxgep->nxge_mmac_info; 4065 4066 base_mac_ls4b = ((uint32_t)base_mmac_addr[1]) << 16 | base_mmac_addr[2]; 4067 4068 if (nxgep->niu_type == N2_NIU) 4069 first_alt_mac_ls4b = base_mac_ls4b + 1; 4070 else /* Neptune */ 4071 first_alt_mac_ls4b = base_mac_ls4b + (nxgep->nports - func_num) 4072 + (func_num * (nxgep->nxge_mmac_info.num_mmac - 1)); 4073 4074 for (i = 0; i < nxgep->nxge_mmac_info.num_mmac - 1; ++i) { 4075 /* 4076 * Populate shadow mac pool w/ available mac. so we dont 4077 * have to read the h/w to search for a mac addr. 4078 */ 4079 mmac_addr = (uint16_t *)&mac_poolp->mmac_pool[i]; 4080 mmac_addr[0] = base_mmac_addr[0]; 4081 mac_addr.w0 = mmac_addr[0]; 4082 4083 mmac_addr[1] = (first_alt_mac_ls4b >> 16) & 0x0FFFF; 4084 mac_addr.w1 = mmac_addr[1]; 4085 4086 mmac_addr[2] = first_alt_mac_ls4b & 0x0FFFF; 4087 mac_addr.w2 = mmac_addr[2]; 4088 4089 /* 4090 * Program the h/w alt. mac address, starting 4091 * from reg1(reg0 corr. to unique mac addr) 4092 */ 4093 (void) npi_mac_altaddr_entry(nxgep->npi_handle, OP_SET, 4094 NXGE_GET_PORT_NUM(func_num), i, &mac_addr); 4095 first_alt_mac_ls4b++; 4096 } 4097 } 4098