xref: /illumos-gate/usr/src/uts/common/io/nxge/nxge_ndd.c (revision 3d16f8e771544ca454864650bbe6fa545a2d7dd2)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #pragma ident	"%Z%%M%	%I%	%E% SMI"
27 
28 #include <sys/nxge/nxge_impl.h>
29 #include <inet/common.h>
30 #include <inet/mi.h>
31 #include <inet/nd.h>
32 
33 extern uint64_t npi_debug_level;
34 
35 #define	NXGE_PARAM_MAC_RW \
36 	NXGE_PARAM_RW | NXGE_PARAM_MAC | \
37 	NXGE_PARAM_NDD_WR_OK | NXGE_PARAM_READ_PROP
38 
39 #define	NXGE_PARAM_MAC_DONT_SHOW \
40 	NXGE_PARAM_RW | NXGE_PARAM_MAC | NXGE_PARAM_DONT_SHOW
41 
42 #define	NXGE_PARAM_RXDMA_RW \
43 	NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_NDD_WR_OK | \
44 	NXGE_PARAM_READ_PROP
45 
46 #define	NXGE_PARAM_RXDMA_RWC \
47 	NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_INIT_ONLY | \
48 	NXGE_PARAM_READ_PROP
49 
50 #define	NXGE_PARAM_L2CLASS_CFG \
51 	NXGE_PARAM_RW | NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_READ_PROP | \
52 	NXGE_PARAM_NDD_WR_OK
53 
54 #define	NXGE_PARAM_CLASS_RWS \
55 	NXGE_PARAM_RWS |  NXGE_PARAM_READ_PROP
56 
57 #define	NXGE_PARAM_ARRAY_INIT_SIZE	0x20ULL
58 
59 #define	SET_RX_INTR_TIME_DISABLE 0
60 #define	SET_RX_INTR_TIME_ENABLE 1
61 #define	SET_RX_INTR_PKTS 2
62 
63 #define	BASE_ANY	0
64 #define	BASE_BINARY 	2
65 #define	BASE_HEX	16
66 #define	BASE_DECIMAL	10
67 #define	ALL_FF_64	0xFFFFFFFFFFFFFFFFULL
68 #define	ALL_FF_32	0xFFFFFFFFUL
69 
70 #define	NXGE_NDD_INFODUMP_BUFF_SIZE	2048 /* is 2k enough? */
71 #define	NXGE_NDD_INFODUMP_BUFF_8K	8192
72 #define	NXGE_NDD_INFODUMP_BUFF_16K	0x2000
73 #define	NXGE_NDD_INFODUMP_BUFF_64K	0x8000
74 
75 #define	PARAM_OUTOF_RANGE(vptr, eptr, rval, pa)	\
76 	((vptr == eptr) || (rval < pa->minimum) || (rval > pa->maximum))
77 
78 #define	ADVANCE_PRINT_BUFFER(pmp, plen, rlen) { \
79 	((mblk_t *)pmp)->b_wptr += plen; \
80 	rlen -= plen; \
81 }
82 
83 static int nxge_param_rx_intr_pkts(p_nxge_t, queue_t *,
84 	mblk_t *, char *, caddr_t);
85 static int nxge_param_rx_intr_time(p_nxge_t, queue_t *,
86 	mblk_t *, char *, caddr_t);
87 static int nxge_param_set_mac(p_nxge_t, queue_t *,
88 	mblk_t *, char *, caddr_t);
89 static int nxge_param_set_port_rdc(p_nxge_t, queue_t *,
90 	mblk_t *, char *, caddr_t);
91 static int nxge_param_set_grp_rdc(p_nxge_t, queue_t *,
92 	mblk_t *, char *, caddr_t);
93 static int nxge_param_set_ether_usr(p_nxge_t,
94 	queue_t *, mblk_t *, char *, caddr_t);
95 static int nxge_param_set_ip_usr(p_nxge_t,
96 	queue_t *, mblk_t *, char *, caddr_t);
97 static int nxge_param_set_ip_opt(p_nxge_t,
98 	queue_t *, mblk_t *, char *, caddr_t);
99 static int nxge_param_set_vlan_rdcgrp(p_nxge_t,
100 	queue_t *, mblk_t *, char *, caddr_t);
101 static int nxge_param_set_mac_rdcgrp(p_nxge_t,
102 	queue_t *, mblk_t *, char *, caddr_t);
103 static int nxge_param_fflp_hash_init(p_nxge_t,
104 	queue_t *, mblk_t *, char *, caddr_t);
105 static int nxge_param_llc_snap_enable(p_nxge_t, queue_t *,
106 	mblk_t *, char *, caddr_t);
107 static int nxge_param_hash_lookup_enable(p_nxge_t, queue_t *,
108 	mblk_t *, char *, caddr_t);
109 static int nxge_param_tcam_enable(p_nxge_t, queue_t *,
110 	mblk_t *, char *, caddr_t);
111 static int nxge_param_get_fw_ver(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
112 static int nxge_param_get_port_mode(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
113 static int nxge_param_get_rxdma_info(p_nxge_t, queue_t *q,
114 	p_mblk_t, caddr_t);
115 static int nxge_param_get_txdma_info(p_nxge_t, queue_t *q,
116 	p_mblk_t, caddr_t);
117 static int nxge_param_get_vlan_rdcgrp(p_nxge_t, queue_t *,
118 	p_mblk_t, caddr_t);
119 static int nxge_param_get_mac_rdcgrp(p_nxge_t, queue_t *,
120 	p_mblk_t, caddr_t);
121 static int nxge_param_get_rxdma_rdcgrp_info(p_nxge_t, queue_t *,
122 	p_mblk_t, caddr_t);
123 static int nxge_param_get_ip_opt(p_nxge_t, queue_t *, mblk_t *, caddr_t);
124 static int nxge_param_get_mac(p_nxge_t, queue_t *q, p_mblk_t, caddr_t);
125 static int nxge_param_get_debug_flag(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
126 static int nxge_param_set_nxge_debug_flag(p_nxge_t, queue_t *, mblk_t *,
127 	char *, caddr_t);
128 static int nxge_param_set_npi_debug_flag(p_nxge_t,
129 	queue_t *, mblk_t *, char *, caddr_t);
130 static int nxge_param_dump_rdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t);
131 static int nxge_param_dump_tdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t);
132 static int nxge_param_dump_mac_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
133 static int nxge_param_dump_ipp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
134 static int nxge_param_dump_fflp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
135 static int nxge_param_dump_vlan_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
136 static int nxge_param_dump_rdc_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
137 static int nxge_param_dump_ptrs(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
138 static boolean_t nxge_param_link_update(p_nxge_t);
139 
140 /*
141  * Global array of Neptune changable parameters.
142  * This array is initialized to correspond to the default
143  * Neptune 4 port configuration. This array would be copied
144  * into each port's parameter structure and modifed per
145  * fcode and nxge.conf configuration. Later, the parameters are
146  * exported to ndd to display and run-time configuration (at least
147  * some of them).
148  *
149  */
150 
151 static nxge_param_t	nxge_param_arr[] = {
152 	/*
153 	 * min	max	value	old	hw-name	conf-name
154 	 */
155 	{ nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW,
156 		0, 999, 1000, 0, "instance", "instance"},
157 
158 	{ nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW,
159 		0, 999, 1000, 0, "main-instance", "main_instance"},
160 
161 	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ,
162 		0, 3, 0, 0, "function-number", "function_number"},
163 
164 	/* Partition Id */
165 	{ nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW,
166 		0, 8, 0, 0, "partition-id", "partition_id"},
167 
168 	/* Read Write Permission Mode */
169 	{ nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW,
170 		0, 2, 0, 0, "read-write-mode", "read_write_mode"},
171 
172 	{ nxge_param_get_fw_ver, NULL, NXGE_PARAM_READ,
173 		0, 32, 0, 0, "version",	"fw_version"},
174 
175 	{ nxge_param_get_port_mode, NULL, NXGE_PARAM_READ,
176 		0, 32, 0, 0, "port-mode", "port_mode"},
177 
178 	/* hw cfg types */
179 	/* control the DMA config of Neptune/NIU */
180 	{ nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW,
181 		CFG_DEFAULT, CFG_CUSTOM, CFG_DEFAULT, CFG_DEFAULT,
182 		"niu-cfg-type", "niu_cfg_type"},
183 
184 	/* control the TXDMA config of the Port controlled by tx-quick-cfg */
185 	{ nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW,
186 		CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT,
187 		"tx-qcfg-type", "tx_qcfg_type"},
188 
189 	/* control the RXDMA config of the Port controlled by rx-quick-cfg */
190 	{ nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW,
191 		CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT,
192 		"rx-qcfg-type", "rx_qcfg_type"},
193 
194 	{ nxge_param_get_mac, nxge_param_set_mac,
195 		NXGE_PARAM_RW  | NXGE_PARAM_DONT_SHOW,
196 		0, 1, 0, 0, "master-cfg-enable", "master_cfg_enable"},
197 
198 	{ nxge_param_get_mac, nxge_param_set_mac,
199 		NXGE_PARAM_DONT_SHOW,
200 		0, 1, 0, 0, "master-cfg-value", "master_cfg_value"},
201 
202 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW,
203 		0, 1, 1, 1, "adv-autoneg-cap", "adv_autoneg_cap"},
204 
205 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW,
206 		0, 1, 1, 1, "adv-10gfdx-cap", "adv_10gfdx_cap"},
207 
208 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW,
209 		0, 1, 0, 0, "adv-10ghdx-cap", "adv_10ghdx_cap"},
210 
211 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW,
212 		0, 1, 1, 1, "adv-1000fdx-cap", "adv_1000fdx_cap"},
213 
214 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW,
215 		0, 1, 0, 0, "adv-1000hdx-cap",	"adv_1000hdx_cap"},
216 
217 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW,
218 		0, 1, 0, 0, "adv-100T4-cap", "adv_100T4_cap"},
219 
220 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW,
221 		0, 1, 1, 1, "adv-100fdx-cap", "adv_100fdx_cap"},
222 
223 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW,
224 		0, 1, 0, 0, "adv-100hdx-cap", "adv_100hdx_cap"},
225 
226 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW,
227 		0, 1, 1, 1, "adv-10fdx-cap", "adv_10fdx_cap"},
228 
229 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW,
230 		0, 1, 0, 0, "adv-10hdx-cap", "adv_10hdx_cap"},
231 
232 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW,
233 		0, 1, 0, 0, "adv-asmpause-cap",	"adv_asmpause_cap"},
234 
235 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW,
236 		0, 1, 0, 0, "adv-pause-cap", "adv_pause_cap"},
237 
238 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW,
239 		0, 1, 0, 0, "use-int-xcvr", "use_int_xcvr"},
240 
241 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW,
242 		0, 1, 1, 1, "enable-ipg0", "enable_ipg0"},
243 
244 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW,
245 		0, 255,	8, 8, "ipg0", "ipg0"},
246 
247 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW,
248 		0, 255,	8, 8, "ipg1", "ipg1"},
249 
250 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW,
251 		0, 255,	4, 4, "ipg2", "ipg2"},
252 
253 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW,
254 		0, 1, 0, 0, "accept-jumbo", "accept_jumbo"},
255 
256 	/* Transmit DMA channels */
257 	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ |
258 		NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
259 		0, 3, 0, 0, "tx-dma-weight", "tx_dma_weight"},
260 
261 	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ |
262 		NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
263 		0, 31, 0, 0, "tx-dma-channels-begin", "tx_dma_channels_begin"},
264 
265 	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ |
266 		NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
267 		0, 32, 0, 0, "tx-dma-channels", "tx_dma_channels"},
268 	{ nxge_param_get_txdma_info, NULL,
269 		NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
270 		0, 32, 0, 0, "tx-dma-info", "tx_dma_info"},
271 
272 	/* Receive DMA channels */
273 	{ nxge_param_get_generic, NULL,
274 		NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
275 		0, 31, 0, 0, "rx-dma-channels-begin", "rx_dma_channels_begin"},
276 
277 	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ |
278 		NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
279 		0, 32, 0, 0, "rx-dma-channels",	"rx_dma_channels"},
280 
281 	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ |
282 		NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
283 		0, 65535, PT_DRR_WT_DEFAULT_10G, 0,
284 		"rx-drr-weight", "rx_drr_weight"},
285 
286 	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ |
287 		NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
288 		0, 1, 1, 0, "rx-full-header", "rx_full_header"},
289 
290 	{ nxge_param_get_rxdma_info, NULL, NXGE_PARAM_READ |
291 		NXGE_PARAM_DONT_SHOW,
292 		0, 32, 0, 0, "rx-dma-info", "rx_dma_info"},
293 
294 	{ nxge_param_get_rxdma_info, NULL,
295 		NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW,
296 		NXGE_RBR_RBB_MIN, NXGE_RBR_RBB_MAX, NXGE_RBR_RBB_DEFAULT, 0,
297 		"rx-rbr-size", "rx_rbr_size"},
298 
299 	{ nxge_param_get_rxdma_info, NULL,
300 		NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW,
301 		NXGE_RCR_MIN, NXGE_RCR_MAX, NXGE_RCR_DEFAULT, 0,
302 		"rx-rcr-size", "rx_rcr_size"},
303 
304 	{ nxge_param_get_generic, nxge_param_set_port_rdc,
305 		NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
306 		0, 15, 0, 0, "default-port-rdc", "default_port_rdc"},
307 
308 	{ nxge_param_get_generic, nxge_param_rx_intr_time, NXGE_PARAM_RXDMA_RW,
309 		NXGE_RDC_RCR_TIMEOUT_MIN, NXGE_RDC_RCR_TIMEOUT_MAX,
310 		RXDMA_RCR_TO_DEFAULT, 0, "rxdma-intr-time", "rxdma_intr_time"},
311 
312 	{ nxge_param_get_generic, nxge_param_rx_intr_pkts, NXGE_PARAM_RXDMA_RW,
313 		NXGE_RDC_RCR_THRESHOLD_MIN, NXGE_RDC_RCR_THRESHOLD_MAX,
314 		RXDMA_RCR_PTHRES_DEFAULT, 0,
315 		"rxdma-intr-pkts", "rxdma_intr_pkts"},
316 
317 	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP |
318 		NXGE_PARAM_DONT_SHOW,
319 		0, 8, 0, 0, "rx-rdc-grps-begin", "rx_rdc_grps_begin"},
320 
321 	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP |
322 		NXGE_PARAM_DONT_SHOW,
323 		0, 8, 0, 0, "rx-rdc-grps", "rx_rdc_grps"},
324 
325 	{ nxge_param_get_generic, nxge_param_set_grp_rdc,
326 		NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
327 		0, 15, 0, 0, "default-grp0-rdc", "default_grp0_rdc"},
328 
329 	{ nxge_param_get_generic, nxge_param_set_grp_rdc,
330 		NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
331 		0, 15,	2, 0, "default-grp1-rdc", "default_grp1_rdc"},
332 
333 	{ nxge_param_get_generic, nxge_param_set_grp_rdc,
334 		NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
335 		0, 15, 4, 0, "default-grp2-rdc", "default_grp2_rdc"},
336 
337 	{ nxge_param_get_generic, nxge_param_set_grp_rdc,
338 		NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
339 		0, 15, 6, 0, "default-grp3-rdc", "default_grp3_rdc"},
340 
341 	{ nxge_param_get_generic, nxge_param_set_grp_rdc,
342 		NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
343 		0, 15, 8, 0, "default-grp4-rdc", "default_grp4_rdc"},
344 
345 	{ nxge_param_get_generic, nxge_param_set_grp_rdc,
346 		NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
347 		0, 15, 10, 0, "default-grp5-rdc", "default_grp5_rdc"},
348 
349 	{ nxge_param_get_generic, nxge_param_set_grp_rdc,
350 		NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
351 		0, 15, 12, 0, "default-grp6-rdc", "default_grp6_rdc"},
352 
353 	{ nxge_param_get_generic, nxge_param_set_grp_rdc,
354 		NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
355 		0, 15, 14, 0, "default-grp7-rdc", "default_grp7_rdc"},
356 
357 	{ nxge_param_get_rxdma_rdcgrp_info, NULL,
358 		NXGE_PARAM_READ | NXGE_PARAM_CMPLX | NXGE_PARAM_DONT_SHOW,
359 		0, 8, 0, 0, "rdc-groups-info", "rdc_groups_info"},
360 
361 	/* Logical device groups */
362 	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW,
363 		0, 63, 0, 0, "start-ldg", "start_ldg"},
364 
365 	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW,
366 		0, 64, 0, 0, "max-ldg", "max_ldg" },
367 
368 	/* MAC table information */
369 	{ nxge_param_get_mac_rdcgrp, nxge_param_set_mac_rdcgrp,
370 		NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW,
371 		0, 31, 0, 0, "mac-2rdc-grp", "mac_2rdc_grp"},
372 
373 	/* VLAN table information */
374 	{ nxge_param_get_vlan_rdcgrp, nxge_param_set_vlan_rdcgrp,
375 		NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW,
376 		0, 31, 0, 0, "vlan-2rdc-grp", "vlan_2rdc_grp"},
377 
378 	{ nxge_param_get_generic, NULL,
379 		NXGE_PARAM_READ_PROP | NXGE_PARAM_READ |
380 		NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_DONT_SHOW,
381 		0, 0x0ffff, 0x0ffff, 0, "fcram-part-cfg", "fcram_part_cfg"},
382 
383 	{ nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS |
384 		NXGE_PARAM_DONT_SHOW,
385 		0, 0x10, 0xa, 0, "fcram-access-ratio", "fcram_access_ratio"},
386 
387 	{ nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS |
388 		NXGE_PARAM_DONT_SHOW,
389 		0, 0x10, 0xa, 0, "tcam-access-ratio", "tcam_access_ratio"},
390 
391 	{ nxge_param_get_generic, nxge_param_tcam_enable,
392 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
393 		0, 0x1, 0x0, 0, "tcam-enable", "tcam_enable"},
394 
395 	{ nxge_param_get_generic, nxge_param_hash_lookup_enable,
396 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
397 		0, 0x01, 0x0, 0, "hash-lookup-enable", "hash_lookup_enable"},
398 
399 	{ nxge_param_get_generic, nxge_param_llc_snap_enable,
400 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
401 		0, 0x01, 0x01, 0, "llc-snap-enable", "llc_snap_enable"},
402 
403 	{ nxge_param_get_generic, nxge_param_fflp_hash_init,
404 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
405 		0, ALL_FF_32, ALL_FF_32, 0, "h1-init-value", "h1_init_value"},
406 
407 	{ nxge_param_get_generic,	nxge_param_fflp_hash_init,
408 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
409 		0, 0x0ffff, 0x0ffff, 0, "h2-init-value", "h2_init_value"},
410 
411 	{ nxge_param_get_generic, nxge_param_set_ether_usr,
412 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
413 		0, ALL_FF_32, 0x0, 0,
414 		"class-cfg-ether-usr1", "class_cfg_ether_usr1"},
415 
416 	{ nxge_param_get_generic, nxge_param_set_ether_usr,
417 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
418 		0, ALL_FF_32, 0x0, 0,
419 		"class-cfg-ether-usr2", "class_cfg_ether_usr2"},
420 
421 	{ nxge_param_get_generic, nxge_param_set_ip_usr,
422 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
423 		0, ALL_FF_32, 0x0, 0,
424 		"class-cfg-ip-usr4", "class_cfg_ip_usr4"},
425 
426 	{ nxge_param_get_generic, nxge_param_set_ip_usr,
427 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
428 		0, ALL_FF_32, 0x0, 0,
429 		"class-cfg-ip-usr5", "class_cfg_ip_usr5"},
430 
431 	{ nxge_param_get_generic, nxge_param_set_ip_usr,
432 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
433 		0, ALL_FF_32, 0x0, 0,
434 		"class-cfg-ip-usr6", "class_cfg_ip_usr6"},
435 
436 	{ nxge_param_get_generic, nxge_param_set_ip_usr,
437 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
438 		0, ALL_FF_32, 0x0, 0,
439 		"class-cfg-ip-usr7", "class_cfg_ip_usr7"},
440 
441 	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt,
442 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
443 		0, ALL_FF_32, 0x0, 0,
444 		"class-opt-ip-usr4", "class_opt_ip_usr4"},
445 
446 	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt,
447 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
448 		0, ALL_FF_32, 0x0, 0,
449 		"class-opt-ip-usr5", "class_opt_ip_usr5"},
450 
451 	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt,
452 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
453 		0, ALL_FF_32, 0x0, 0,
454 		"class-opt-ip-usr6", "class_opt_ip_usr6"},
455 
456 	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt,
457 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
458 		0, ALL_FF_32, 0x0, 0,
459 		"class-opt-ip-usr7", "class_opt_ip_usr7"},
460 
461 	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt,
462 		NXGE_PARAM_CLASS_RWS,
463 		0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
464 		"class-opt-ipv4-tcp", "class_opt_ipv4_tcp"},
465 
466 	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt,
467 		NXGE_PARAM_CLASS_RWS,
468 		0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
469 		"class-opt-ipv4-udp", "class_opt_ipv4_udp"},
470 
471 	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt,
472 		NXGE_PARAM_CLASS_RWS,
473 		0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
474 		"class-opt-ipv4-ah", "class_opt_ipv4_ah"},
475 
476 	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt,
477 		NXGE_PARAM_CLASS_RWS,
478 		0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
479 		"class-opt-ipv4-sctp", "class_opt_ipv4_sctp"},
480 
481 	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS,
482 		0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
483 		"class-opt-ipv6-tcp", "class_opt_ipv6_tcp"},
484 
485 	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS,
486 		0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
487 		"class-opt-ipv6-udp", "class_opt_ipv6_udp"},
488 
489 	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS,
490 		0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
491 		"class-opt-ipv6-ah", "class_opt_ipv6_ah"},
492 
493 	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS,
494 		0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
495 		"class-opt-ipv6-sctp",	"class_opt_ipv6_sctp"},
496 
497 	{ nxge_param_get_debug_flag, nxge_param_set_nxge_debug_flag,
498 		NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW,
499 		0ULL, ALL_FF_64, 0ULL, 0ULL,
500 		"nxge-debug-flag", "nxge_debug_flag"},
501 
502 	{ nxge_param_get_debug_flag, nxge_param_set_npi_debug_flag,
503 		NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW,
504 		0ULL, ALL_FF_64, 0ULL, 0ULL,
505 		"npi-debug-flag", "npi_debug_flag"},
506 
507 	{ nxge_param_dump_tdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW,
508 		0, 0x0fffffff, 0x0fffffff, 0, "dump-tdc", "dump_tdc"},
509 
510 	{ nxge_param_dump_rdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW,
511 		0, 0x0fffffff, 0x0fffffff, 0, "dump-rdc", "dump_rdc"},
512 
513 	{ nxge_param_dump_mac_regs, NULL, NXGE_PARAM_READ |
514 		NXGE_PARAM_DONT_SHOW,
515 		0, 0x0fffffff, 0x0fffffff, 0, "dump-mac-regs", "dump_mac_regs"},
516 
517 	{ nxge_param_dump_ipp_regs, NULL, NXGE_PARAM_READ |
518 		NXGE_PARAM_DONT_SHOW,
519 		0, 0x0fffffff, 0x0fffffff, 0, "dump-ipp-regs", "dump_ipp_regs"},
520 
521 	{ nxge_param_dump_fflp_regs, NULL, NXGE_PARAM_READ |
522 		NXGE_PARAM_DONT_SHOW,
523 		0, 0x0fffffff, 0x0fffffff, 0,
524 		"dump-fflp-regs", "dump_fflp_regs"},
525 
526 	{ nxge_param_dump_vlan_table, NULL, NXGE_PARAM_READ |
527 		NXGE_PARAM_DONT_SHOW,
528 		0, 0x0fffffff, 0x0fffffff, 0,
529 		"dump-vlan-table", "dump_vlan_table"},
530 
531 	{ nxge_param_dump_rdc_table, NULL, NXGE_PARAM_READ |
532 		NXGE_PARAM_DONT_SHOW,
533 		0, 0x0fffffff, 0x0fffffff, 0,
534 		"dump-rdc-table", "dump_rdc_table"},
535 
536 	{ nxge_param_dump_ptrs,	NULL, NXGE_PARAM_READ |
537 		NXGE_PARAM_DONT_SHOW,
538 		0, 0x0fffffff, 0x0fffffff, 0, "dump-ptrs", "dump_ptrs"},
539 
540 	{  NULL, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW,
541 		0, 0x0fffffff, 0x0fffffff, 0, "end", "end"},
542 };
543 
544 extern void 		*nxge_list;
545 
546 void
547 nxge_get_param_soft_properties(p_nxge_t nxgep)
548 {
549 
550 	p_nxge_param_t 		param_arr;
551 	uint_t 			prop_len;
552 	int 			i, j;
553 	uint32_t		param_count;
554 	uint32_t		*int_prop_val;
555 
556 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, " ==> nxge_get_param_soft_properties"));
557 
558 	param_arr = nxgep->param_arr;
559 	param_count = nxgep->param_count;
560 	for (i = 0; i < param_count; i++) {
561 		if ((param_arr[i].type & NXGE_PARAM_READ_PROP) == 0)
562 			continue;
563 		if ((param_arr[i].type & NXGE_PARAM_PROP_STR))
564 			continue;
565 		if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) ||
566 				(param_arr[i].type & NXGE_PARAM_PROP_ARR64)) {
567 			if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY,
568 					nxgep->dip, 0, param_arr[i].fcode_name,
569 					(int **)&int_prop_val,
570 					(uint_t *)&prop_len)
571 					== DDI_PROP_SUCCESS) {
572 				uint32_t *cfg_value;
573 				uint64_t prop_count;
574 
575 				if (prop_len > NXGE_PARAM_ARRAY_INIT_SIZE)
576 					prop_len = NXGE_PARAM_ARRAY_INIT_SIZE;
577 #if defined(__i386)
578 				cfg_value =
579 					(uint32_t *)(int32_t)param_arr[i].value;
580 #else
581 				cfg_value = (uint32_t *)param_arr[i].value;
582 #endif
583 				for (j = 0; j < prop_len; j++) {
584 					cfg_value[j] = int_prop_val[j];
585 				}
586 				prop_count = prop_len;
587 				param_arr[i].type |=
588 				    (prop_count << NXGE_PARAM_ARRAY_CNT_SHIFT);
589 				ddi_prop_free(int_prop_val);
590 			}
591 			continue;
592 		}
593 
594 		if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0,
595 				param_arr[i].fcode_name,
596 				(int **)&int_prop_val,
597 				&prop_len) == DDI_PROP_SUCCESS) {
598 			if ((*int_prop_val >= param_arr[i].minimum) &&
599 					(*int_prop_val <= param_arr[i].maximum))
600 				param_arr[i].value = *int_prop_val;
601 #ifdef NXGE_DEBUG_ERROR
602 			else {
603 				NXGE_DEBUG_MSG((nxgep, OBP_CTL,
604 					"nxge%d: 'prom' file parameter error\n",
605 					nxgep->instance));
606 				NXGE_DEBUG_MSG((nxgep, OBP_CTL,
607 					"Parameter keyword '%s'"
608 					" is outside valid range\n",
609 					param_arr[i].name));
610 			}
611 #endif
612 			ddi_prop_free(int_prop_val);
613 		}
614 
615 		if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0,
616 				param_arr[i].name,
617 				(int **)&int_prop_val,
618 				&prop_len) == DDI_PROP_SUCCESS) {
619 			if ((*int_prop_val >= param_arr[i].minimum) &&
620 				(*int_prop_val <= param_arr[i].maximum))
621 				param_arr[i].value = *int_prop_val;
622 #ifdef NXGE_DEBUG_ERROR
623 			else {
624 				NXGE_DEBUG_MSG((nxgep, OBP_CTL,
625 					"nxge%d: 'conf' file parameter error\n",
626 					nxgep->instance));
627 				NXGE_DEBUG_MSG((nxgep, OBP_CTL,
628 					"Parameter keyword '%s'"
629 					"is outside valid range\n",
630 					param_arr[i].name));
631 			}
632 #endif
633 			ddi_prop_free(int_prop_val);
634 		}
635 	}
636 }
637 
638 static int
639 nxge_private_param_register(p_nxge_t nxgep, p_nxge_param_t param_arr)
640 {
641 	int status = B_TRUE;
642 	int channel;
643 	uint8_t grp;
644 	char *prop_name;
645 	char *end;
646 	uint32_t name_chars;
647 
648 	NXGE_DEBUG_MSG((nxgep, NDD2_CTL,
649 		"nxge_private_param_register %s", param_arr->name));
650 
651 	if ((param_arr->type & NXGE_PARAM_PRIV) != NXGE_PARAM_PRIV)
652 		return (B_TRUE);
653 
654 	prop_name =  param_arr->name;
655 	if (param_arr->type & NXGE_PARAM_RXDMA) {
656 		if (strncmp("rxdma_intr", prop_name, 10) == 0)
657 			return (B_TRUE);
658 		name_chars = strlen("default_grp");
659 		if (strncmp("default_grp", prop_name, name_chars) == 0) {
660 			prop_name += name_chars;
661 			grp = mi_strtol(prop_name, &end, 10);
662 				/* now check if this rdcgrp is in config */
663 			return (nxge_check_rdcgrp_port_member(nxgep, grp));
664 		}
665 		name_chars = strlen(prop_name);
666 		if (strncmp("default_port_rdc", prop_name, name_chars) == 0) {
667 			return (B_TRUE);
668 		}
669 		return (B_FALSE);
670 	}
671 
672 	if (param_arr->type & NXGE_PARAM_TXDMA) {
673 		name_chars = strlen("txdma");
674 		if (strncmp("txdma", prop_name, name_chars) == 0) {
675 			prop_name += name_chars;
676 			channel = mi_strtol(prop_name, &end, 10);
677 				/* now check if this rdc is in config */
678 			NXGE_DEBUG_MSG((nxgep, NDD2_CTL,
679 					    " nxge_private_param_register: %d",
680 					    channel));
681 			return (nxge_check_txdma_port_member(nxgep, channel));
682 		}
683 		return (B_FALSE);
684 	}
685 
686 	status = B_FALSE;
687 	NXGE_DEBUG_MSG((nxgep, NDD2_CTL, "<== nxge_private_param_register"));
688 
689 	return (status);
690 }
691 
692 void
693 nxge_setup_param(p_nxge_t nxgep)
694 {
695 	p_nxge_param_t param_arr;
696 	int i;
697 	pfi_t set_pfi;
698 
699 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_setup_param"));
700 
701 	/*
702 	 * Make sure the param_instance is set to a valid device instance.
703 	 */
704 	if (nxge_param_arr[param_instance].value == 1000)
705 		nxge_param_arr[param_instance].value = nxgep->instance;
706 
707 	param_arr = nxgep->param_arr;
708 	param_arr[param_instance].value = nxgep->instance;
709 	param_arr[param_function_number].value = nxgep->function_num;
710 
711 	for (i = 0; i < nxgep->param_count; i++) {
712 		if ((param_arr[i].type & NXGE_PARAM_PRIV) &&
713 				(nxge_private_param_register(nxgep,
714 				&param_arr[i]) == B_FALSE)) {
715 			param_arr[i].setf = NULL;
716 			param_arr[i].getf = NULL;
717 		}
718 
719 		if (param_arr[i].type & NXGE_PARAM_CMPLX)
720 			param_arr[i].setf = NULL;
721 
722 		if (param_arr[i].type & NXGE_PARAM_DONT_SHOW) {
723 			param_arr[i].setf = NULL;
724 			param_arr[i].getf = NULL;
725 		}
726 
727 		set_pfi = (pfi_t)param_arr[i].setf;
728 
729 		if ((set_pfi) && (param_arr[i].type & NXGE_PARAM_INIT_ONLY)) {
730 			set_pfi = NULL;
731 		}
732 
733 		if (!nxge_nd_load(&nxgep->param_list, param_arr[i].name,
734 				(pfi_t)param_arr[i].getf, set_pfi,
735 				(caddr_t)&param_arr[i])) {
736 			(void) nxge_nd_free(&nxgep->param_list);
737 			break;
738 		}
739 	}
740 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_setup_param"));
741 }
742 
743 void
744 nxge_init_param(p_nxge_t nxgep)
745 {
746 	p_nxge_param_t param_arr;
747 	int i, alloc_size;
748 	uint64_t alloc_count;
749 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_init_param"));
750 	/*
751 	 * Make sure the param_instance is set to a valid device instance.
752 	 */
753 	if (nxge_param_arr[param_instance].value == 1000)
754 		nxge_param_arr[param_instance].value = nxgep->instance;
755 
756 	param_arr = nxgep->param_arr;
757 	if (param_arr == NULL) {
758 		param_arr = (p_nxge_param_t)
759 			KMEM_ZALLOC(sizeof (nxge_param_arr), KM_SLEEP);
760 	}
761 
762 	for (i = 0; i < sizeof (nxge_param_arr)/sizeof (nxge_param_t); i++) {
763 		param_arr[i] = nxge_param_arr[i];
764 		if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) ||
765 			(param_arr[i].type & NXGE_PARAM_PROP_ARR64)) {
766 			alloc_count = NXGE_PARAM_ARRAY_INIT_SIZE;
767 			alloc_size = alloc_count * sizeof (uint64_t);
768 			param_arr[i].value =
769 #if defined(__i386)
770 			    (uint64_t)(uint32_t)KMEM_ZALLOC(alloc_size,
771 				KM_SLEEP);
772 #else
773 			    (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP);
774 #endif
775 			param_arr[i].old_value =
776 #if defined(__i386)
777 				(uint64_t)(uint32_t)KMEM_ZALLOC(alloc_size,
778 				KM_SLEEP);
779 #else
780 				(uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP);
781 #endif
782 			param_arr[i].type |=
783 				(alloc_count << NXGE_PARAM_ARRAY_ALLOC_SHIFT);
784 		}
785 	}
786 
787 	nxgep->param_arr = param_arr;
788 	nxgep->param_count = sizeof (nxge_param_arr)/sizeof (nxge_param_t);
789 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_init_param: count %d",
790 		nxgep->param_count));
791 }
792 
793 void
794 nxge_destroy_param(p_nxge_t nxgep)
795 {
796 	int i;
797 	uint64_t free_size, free_count;
798 
799 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_param"));
800 
801 	if (nxgep->param_arr == NULL)
802 		return;
803 	/*
804 	 * Make sure the param_instance is set to a valid device instance.
805 	 */
806 	if (nxge_param_arr[param_instance].value == nxgep->instance) {
807 		for (i = 0; i <= nxge_param_arr[param_instance].maximum; i++) {
808 			if ((ddi_get_soft_state(nxge_list, i) != NULL) &&
809 				(i != nxgep->instance))
810 				break;
811 		}
812 		nxge_param_arr[param_instance].value = i;
813 	}
814 
815 	if (nxgep->param_list)
816 		nxge_nd_free(&nxgep->param_list);
817 	for (i = 0; i < nxgep->param_count; i++)
818 		if ((nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR32) ||
819 			(nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR64)) {
820 			free_count = ((nxgep->param_arr[i].type &
821 					    NXGE_PARAM_ARRAY_ALLOC_MASK) >>
822 					    NXGE_PARAM_ARRAY_ALLOC_SHIFT);
823 			free_count = NXGE_PARAM_ARRAY_INIT_SIZE;
824 			free_size = sizeof (uint64_t) * free_count;
825 #if defined(__i386)
826 			KMEM_FREE((void *)(uint32_t)nxgep->param_arr[i].value,
827 				free_size);
828 #else
829 			KMEM_FREE((void *)nxgep->param_arr[i].value, free_size);
830 #endif
831 #if defined(__i386)
832 			KMEM_FREE((void *)(uint32_t)
833 				nxgep->param_arr[i].old_value, free_size);
834 #else
835 			KMEM_FREE((void *)nxgep->param_arr[i].old_value,
836 				free_size);
837 #endif
838 		}
839 
840 	KMEM_FREE(nxgep->param_arr, sizeof (nxge_param_arr));
841 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_param"));
842 }
843 
844 /*
845  * Extracts the value from the 'nxge' parameter array and prints the
846  * parameter value. cp points to the required parameter.
847  */
848 
849 /* ARGSUSED */
850 int
851 nxge_param_get_generic(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
852 {
853 	p_nxge_param_t pa = (p_nxge_param_t)cp;
854 
855 	NXGE_DEBUG_MSG((nxgep, NDD_CTL,
856 		"==> nxge_param_get_generic name %s ", pa->name));
857 
858 	if (pa->value > 0xffffffff)
859 		(void) mi_mpprintf(mp, "%x%x",
860 			(int)(pa->value >> 32), (int)(pa->value & 0xffffffff));
861 	else
862 		(void) mi_mpprintf(mp, "%x", (int)pa->value);
863 
864 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_generic"));
865 	return (0);
866 }
867 
868 /* ARGSUSED */
869 static int
870 nxge_param_get_mac(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
871 {
872 	p_nxge_param_t pa = (p_nxge_param_t)cp;
873 
874 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac"));
875 
876 	(void) mi_mpprintf(mp, "%d", (uint32_t)pa->value);
877 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_mac"));
878 	return (0);
879 }
880 
881 /* ARGSUSED */
882 static int
883 nxge_param_get_fw_ver(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
884 {
885 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_fw_ver"));
886 
887 	(void) mi_mpprintf(mp, "Firmware version for nxge%d:  %s\n",
888 	    nxgep->instance, nxgep->vpd_info.ver);
889 
890 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_fw_ver"));
891 	return (0);
892 }
893 
894 /* ARGSUSED */
895 static int
896 nxge_param_get_port_mode(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
897 {
898 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_port_mode"));
899 
900 	switch (nxgep->mac.portmode) {
901 	case PORT_1G_COPPER:
902 		(void) mi_mpprintf(mp, "Port mode for nxge%d:  1G Copper %s\n",
903 		    nxgep->instance,
904 		    nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
905 		break;
906 	case PORT_1G_FIBER:
907 		(void) mi_mpprintf(mp, "Port mode for nxge%d:  1G Fiber %s\n",
908 		    nxgep->instance,
909 		    nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
910 		break;
911 	case PORT_10G_COPPER:
912 		(void) mi_mpprintf(mp, "Port mode for nxge%d:  10G Copper "
913 		    "%s\n", nxgep->instance,
914 		    nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
915 		break;
916 	case PORT_10G_FIBER:
917 		(void) mi_mpprintf(mp, "Port mode for nxge%d:  10G Fiber %s\n",
918 		    nxgep->instance,
919 		    nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
920 		break;
921 	case PORT_10G_SERDES:
922 		(void) mi_mpprintf(mp, "Port mode for nxge%d:  10G Serdes "
923 		    "%s\n", nxgep->instance,
924 		    nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
925 		break;
926 	case PORT_1G_SERDES:
927 		(void) mi_mpprintf(mp, "Port mode for nxge%d:  1G Serdes %s\n",
928 		    nxgep->instance,
929 		    nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
930 		break;
931 	case PORT_1G_RGMII_FIBER:
932 		(void) mi_mpprintf(mp, "Port mode for nxge%d:  1G RGMII "
933 		    "Fiber %s\n", nxgep->instance,
934 		    nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
935 		break;
936 	case PORT_HSP_MODE:
937 		(void) mi_mpprintf(mp, "Port mode for nxge%d:  Hot Swappable "
938 		    "PHY, Currently NOT present\n", nxgep->instance);
939 		break;
940 	default:
941 		(void) mi_mpprintf(mp, "Port mode for nxge%d:  Unknown %s\n",
942 		    nxgep->instance,
943 		    nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
944 		break;
945 	}
946 
947 	(void) mi_mpprintf(mp, "Software LSO for nxge%d: %s\n",
948 	    nxgep->instance,
949 	    nxgep->soft_lso_enable ? "enable" : "disable");
950 
951 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_port_mode"));
952 	return (0);
953 }
954 
955 /* ARGSUSED */
956 int
957 nxge_param_get_txdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
958 {
959 
960 	uint_t	print_len, buf_len;
961 	p_mblk_t np;
962 	int tdc;
963 
964 	int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE;
965 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_txdma_info"));
966 
967 	(void) mi_mpprintf(mp, "TXDMA Information for Port\t %d \n",
968 		nxgep->function_num);
969 
970 
971 	if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) {
972 		(void) mi_mpprintf(mp, "%s\n", "out of buffer");
973 		return (0);
974 	}
975 
976 	buf_len = buff_alloc_size;
977 	mp->b_cont = np;
978 
979 	print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
980 		"Total TDCs\t %d\n", nxgep->ntdc);
981 
982 	((mblk_t *)np)->b_wptr += print_len;
983 	buf_len -= print_len;
984 	print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
985 		"TDC\t HW TDC\t\n");
986 	((mblk_t *)np)->b_wptr += print_len;
987 
988 	buf_len -= print_len;
989 	for (tdc = 0; tdc < nxgep->ntdc; tdc++) {
990 		print_len = snprintf((char *)((mblk_t *)np)->b_wptr,
991 					    buf_len, "%d\t %d\n",
992 					    tdc, nxgep->tdc[tdc]);
993 		((mblk_t *)np)->b_wptr += print_len;
994 		buf_len -= print_len;
995 	}
996 
997 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_txdma_info"));
998 	return (0);
999 }
1000 
1001 /* ARGSUSED */
1002 int
1003 nxge_param_get_rxdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
1004 {
1005 	uint_t			print_len, buf_len;
1006 	p_mblk_t		np;
1007 	int			rdc;
1008 	p_nxge_dma_pt_cfg_t	p_dma_cfgp;
1009 	p_nxge_hw_pt_cfg_t	p_cfgp;
1010 	int			buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE;
1011 	p_rx_rcr_rings_t 	rx_rcr_rings;
1012 	p_rx_rcr_ring_t		*rcr_rings;
1013 	p_rx_rbr_rings_t 	rx_rbr_rings;
1014 	p_rx_rbr_ring_t		*rbr_rings;
1015 
1016 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rxdma_info"));
1017 
1018 	(void) mi_mpprintf(mp, "RXDMA Information for Port\t %d \n",
1019 		nxgep->function_num);
1020 
1021 	if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) {
1022 		/* The following may work even if we cannot get a large buf. */
1023 		(void) mi_mpprintf(mp, "%s\n", "out of buffer");
1024 		return (0);
1025 	}
1026 
1027 	buf_len = buff_alloc_size;
1028 	mp->b_cont = np;
1029 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
1030 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
1031 
1032 	rx_rcr_rings = nxgep->rx_rcr_rings;
1033 	rcr_rings = rx_rcr_rings->rcr_rings;
1034 	rx_rbr_rings = nxgep->rx_rbr_rings;
1035 	rbr_rings = rx_rbr_rings->rbr_rings;
1036 
1037 	print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
1038 		"Total RDCs\t %d\n", p_cfgp->max_rdcs);
1039 
1040 	((mblk_t *)np)->b_wptr += print_len;
1041 	buf_len -= print_len;
1042 	print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
1043 		"RDC\t HW RDC\t Timeout\t Packets RBR ptr \t"
1044 		"chunks\t RCR ptr\n");
1045 
1046 	((mblk_t *)np)->b_wptr += print_len;
1047 	buf_len -= print_len;
1048 	for (rdc = 0; rdc < p_cfgp->max_rdcs; rdc++) {
1049 		print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
1050 			" %d\t  %d\t   %x\t\t %x\t $%p\t 0x%x\t $%p\n",
1051 			rdc, nxgep->rdc[rdc],
1052 			p_dma_cfgp->rcr_timeout[rdc],
1053 			p_dma_cfgp->rcr_threshold[rdc],
1054 			rbr_rings[rdc],
1055 			rbr_rings[rdc]->num_blocks, rcr_rings[rdc]);
1056 			((mblk_t *)np)->b_wptr += print_len;
1057 			buf_len -= print_len;
1058 	}
1059 
1060 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rxdma_info"));
1061 	return (0);
1062 }
1063 
1064 /* ARGSUSED */
1065 int
1066 nxge_param_get_rxdma_rdcgrp_info(p_nxge_t nxgep, queue_t *q,
1067 	p_mblk_t mp, caddr_t cp)
1068 {
1069 	uint_t			print_len, buf_len;
1070 	p_mblk_t		np;
1071 	int			offset, rdc, i, rdc_grp;
1072 	p_nxge_rdc_grp_t	rdc_grp_p;
1073 	p_nxge_dma_pt_cfg_t	p_dma_cfgp;
1074 	p_nxge_hw_pt_cfg_t	p_cfgp;
1075 
1076 	int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE;
1077 	NXGE_DEBUG_MSG((nxgep, NDD_CTL,
1078 		"==> nxge_param_get_rxdma_rdcgrp_info"));
1079 
1080 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
1081 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
1082 
1083 	(void) mi_mpprintf(mp, "RXDMA RDC Group Information for Port\t %d \n",
1084 		nxgep->function_num);
1085 
1086 	rdc_grp = p_cfgp->start_rdc_grpid;
1087 	if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) {
1088 		/* The following may work even if we cannot get a large buf. */
1089 		(void) mi_mpprintf(mp, "%s\n", "out of buffer");
1090 		return (0);
1091 	}
1092 
1093 	buf_len = buff_alloc_size;
1094 	mp->b_cont = np;
1095 	print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
1096 		"Total RDC Groups\t %d \n"
1097 		"start RDC group\t %d\n",
1098 		p_cfgp->max_rdc_grpids,
1099 		p_cfgp->start_rdc_grpid);
1100 
1101 	((mblk_t *)np)->b_wptr += print_len;
1102 	buf_len -= print_len;
1103 
1104 	for (i = 0, rdc_grp = p_cfgp->start_rdc_grpid;
1105 	    rdc_grp < (p_cfgp->max_rdc_grpids + p_cfgp->start_rdc_grpid);
1106 	    rdc_grp++, i++) {
1107 		rdc_grp_p = &p_dma_cfgp->rdc_grps[i];
1108 		print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
1109 			"\nRDC Group Info for Group [%d] %d\n"
1110 			"RDC Count %d\tstart RDC %d\n"
1111 			"RDC Group Population Information"
1112 			" (offsets 0 - 15)\n",
1113 			i, rdc_grp, rdc_grp_p->max_rdcs,
1114 			rdc_grp_p->start_rdc);
1115 
1116 		((mblk_t *)np)->b_wptr += print_len;
1117 		buf_len -= print_len;
1118 		print_len = snprintf((char *)((mblk_t *)np)->b_wptr,
1119 			buf_len, "\n");
1120 		((mblk_t *)np)->b_wptr += print_len;
1121 		buf_len -= print_len;
1122 
1123 		for (rdc = 0; rdc < rdc_grp_p->max_rdcs; rdc++) {
1124 			print_len = snprintf((char *)((mblk_t *)np)->b_wptr,
1125 				buf_len, "[%d]=%d ", rdc,
1126 				rdc_grp_p->start_rdc + rdc);
1127 			((mblk_t *)np)->b_wptr += print_len;
1128 			buf_len -= print_len;
1129 		}
1130 		print_len = snprintf((char *)((mblk_t *)np)->b_wptr,
1131 					    buf_len, "\n");
1132 		((mblk_t *)np)->b_wptr += print_len;
1133 		buf_len -= print_len;
1134 
1135 		for (offset = 0; offset < 16; offset++) {
1136 			print_len = snprintf((char *)((mblk_t *)np)->b_wptr,
1137 				buf_len, " %2d ",
1138 				rdc_grp_p->rdc[offset]);
1139 			((mblk_t *)np)->b_wptr += print_len;
1140 			buf_len -= print_len;
1141 		}
1142 		print_len = snprintf((char *)((mblk_t *)np)->b_wptr,
1143 			buf_len, "\n");
1144 		((mblk_t *)np)->b_wptr += print_len;
1145 		buf_len -= print_len;
1146 	}
1147 	NXGE_DEBUG_MSG((nxgep, NDD_CTL,
1148 		"<== nxge_param_get_rxdma_rdcgrp_info"));
1149 	return (0);
1150 }
1151 
1152 int
1153 nxge_mk_mblk_tail_space(p_mblk_t mp, p_mblk_t *nmp, size_t size)
1154 {
1155 	p_mblk_t tmp;
1156 
1157 	tmp = mp;
1158 	while (tmp->b_cont)
1159 		tmp = tmp->b_cont;
1160 	if ((tmp->b_wptr + size) >= tmp->b_datap->db_lim) {
1161 		tmp->b_cont = allocb(1024, BPRI_HI);
1162 		tmp = tmp->b_cont;
1163 		if (!tmp)
1164 			return (ENOMEM);
1165 	}
1166 
1167 	*nmp = tmp;
1168 	return (0);
1169 }
1170 
1171 /*
1172  * Sets the ge parameter to the value in the nxge_param_register using
1173  * nxge_nd_load().
1174  */
1175 
1176 /* ARGSUSED */
1177 int
1178 nxge_param_set_generic(p_nxge_t nxgep, queue_t *q, mblk_t *mp,
1179 			    char *value, caddr_t cp)
1180 {
1181 	char *end;
1182 	uint32_t new_value;
1183 	p_nxge_param_t pa = (p_nxge_param_t)cp;
1184 
1185 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, " ==> nxge_param_set_generic"));
1186 	new_value = (uint32_t)mi_strtol(value, &end, 10);
1187 	if (end == value || new_value < pa->minimum ||
1188 		new_value > pa->maximum) {
1189 			return (EINVAL);
1190 	}
1191 	pa->value = new_value;
1192 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, " <== nxge_param_set_generic"));
1193 	return (0);
1194 }
1195 
1196 /*
1197  * Sets the ge parameter to the value in the nxge_param_register using
1198  * nxge_nd_load().
1199  */
1200 
1201 /* ARGSUSED */
1202 int
1203 nxge_param_set_instance(p_nxge_t nxgep, queue_t *q, mblk_t *mp,
1204 	char *value, caddr_t cp)
1205 {
1206 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, " ==> nxge_param_set_instance"));
1207 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_set_instance"));
1208 	return (0);
1209 }
1210 
1211 /*
1212  * Sets the ge parameter to the value in the nxge_param_register using
1213  * nxge_nd_load().
1214  */
1215 
1216 /* ARGSUSED */
1217 int
1218 nxge_param_set_mac(p_nxge_t nxgep, queue_t *q, mblk_t *mp,
1219 	char *value, caddr_t cp)
1220 {
1221 	char		*end;
1222 	uint32_t	new_value;
1223 	int		status = 0;
1224 	p_nxge_param_t	pa = (p_nxge_param_t)cp;
1225 
1226 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac"));
1227 	new_value = (uint32_t)mi_strtol(value, &end, BASE_DECIMAL);
1228 	if (PARAM_OUTOF_RANGE(value, end, new_value, pa)) {
1229 		return (EINVAL);
1230 	}
1231 
1232 	if (pa->value != new_value) {
1233 		pa->old_value = pa->value;
1234 		pa->value = new_value;
1235 	}
1236 
1237 	if (!nxge_param_link_update(nxgep)) {
1238 		NXGE_DEBUG_MSG((nxgep, NDD_CTL,
1239 				    " false ret from nxge_param_link_update"));
1240 		status = EINVAL;
1241 	}
1242 
1243 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac"));
1244 	return (status);
1245 }
1246 
1247 /* ARGSUSED */
1248 static int
1249 nxge_param_rx_intr_pkts(p_nxge_t nxgep, queue_t *q, mblk_t *mp,
1250 	char *value, caddr_t cp)
1251 {
1252 	char		*end;
1253 	uint32_t	cfg_value;
1254 	p_nxge_param_t	pa = (p_nxge_param_t)cp;
1255 
1256 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_pkts"));
1257 
1258 	cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY);
1259 
1260 	if ((cfg_value > NXGE_RDC_RCR_THRESHOLD_MAX) ||
1261 		(cfg_value < NXGE_RDC_RCR_THRESHOLD_MIN)) {
1262 		return (EINVAL);
1263 	}
1264 
1265 	if ((pa->value != cfg_value)) {
1266 		pa->old_value = pa->value;
1267 		pa->value = cfg_value;
1268 		nxgep->intr_threshold = pa->value;
1269 	}
1270 
1271 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_pkts"));
1272 	return (0);
1273 }
1274 
1275 /* ARGSUSED */
1276 static int
1277 nxge_param_rx_intr_time(p_nxge_t nxgep, queue_t *q, mblk_t *mp,
1278 	char *value, caddr_t cp)
1279 {
1280 	char		*end;
1281 	uint32_t	cfg_value;
1282 	p_nxge_param_t	pa = (p_nxge_param_t)cp;
1283 
1284 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_time"));
1285 
1286 	cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY);
1287 
1288 	if ((cfg_value > NXGE_RDC_RCR_TIMEOUT_MAX) ||
1289 		(cfg_value < NXGE_RDC_RCR_TIMEOUT_MIN)) {
1290 		return (EINVAL);
1291 	}
1292 
1293 	if ((pa->value != cfg_value)) {
1294 		pa->old_value = pa->value;
1295 		pa->value = cfg_value;
1296 		nxgep->intr_timeout = pa->value;
1297 	}
1298 
1299 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_time"));
1300 	return (0);
1301 }
1302 
1303 /* ARGSUSED */
1304 static int
1305 nxge_param_set_mac_rdcgrp(p_nxge_t nxgep, queue_t *q,
1306 	mblk_t *mp, char *value, caddr_t cp)
1307 {
1308 	char			 *end;
1309 	uint32_t		status = 0, cfg_value;
1310 	p_nxge_param_t		pa = (p_nxge_param_t)cp;
1311 	uint32_t		cfg_it = B_FALSE;
1312 	p_nxge_dma_pt_cfg_t	p_dma_cfgp;
1313 	p_nxge_hw_pt_cfg_t	p_cfgp;
1314 	uint32_t		*val_ptr, *old_val_ptr;
1315 	nxge_param_map_t	*mac_map;
1316 	p_nxge_class_pt_cfg_t	p_class_cfgp;
1317 	nxge_mv_cfg_t		*mac_host_info;
1318 
1319 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac_rdcgrp "));
1320 
1321 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
1322 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
1323 	p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
1324 	mac_host_info = (nxge_mv_cfg_t	*)&p_class_cfgp->mac_host_info[0];
1325 	cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX);
1326 
1327 	/*
1328 	 * now do decoding
1329 	 */
1330 	mac_map = (nxge_param_map_t *)&cfg_value;
1331 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, " cfg_value %x id %x map_to %x",
1332 		cfg_value, mac_map->param_id, mac_map->map_to));
1333 
1334 	if ((mac_map->param_id < p_cfgp->max_macs) &&
1335 			(mac_map->map_to < (p_cfgp->max_rdc_grpids +
1336 			p_cfgp->start_rdc_grpid)) && (mac_map->map_to >=
1337 			p_cfgp->start_rdc_grpid)) {
1338 		NXGE_DEBUG_MSG((nxgep, NDD_CTL,
1339 			" nxge_param_set_mac_rdcgrp mapping"
1340 			" id %d grp %d", mac_map->param_id, mac_map->map_to));
1341 #if defined(__i386)
1342 		val_ptr = (uint32_t *)(uint32_t)pa->value;
1343 #else
1344 		val_ptr = (uint32_t *)pa->value;
1345 #endif
1346 #if defined(__i386)
1347 		old_val_ptr = (uint32_t *)(uint32_t)pa->old_value;
1348 #else
1349 		old_val_ptr = (uint32_t *)pa->old_value;
1350 #endif
1351 		if (val_ptr[mac_map->param_id] != cfg_value) {
1352 			old_val_ptr[mac_map->param_id] =
1353 				    val_ptr[mac_map->param_id];
1354 			val_ptr[mac_map->param_id] = cfg_value;
1355 			mac_host_info[mac_map->param_id].mpr_npr =
1356 				    mac_map->pref;
1357 			mac_host_info[mac_map->param_id].flag = 1;
1358 			mac_host_info[mac_map->param_id].rdctbl =
1359 				    mac_map->map_to;
1360 			cfg_it = B_TRUE;
1361 		}
1362 	} else {
1363 		return (EINVAL);
1364 	}
1365 
1366 	if (cfg_it == B_TRUE) {
1367 		status = nxge_logical_mac_assign_rdc_table(nxgep,
1368 						    (uint8_t)mac_map->param_id);
1369 		if (status != NXGE_OK)
1370 			return (EINVAL);
1371 	}
1372 
1373 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac_rdcgrp"));
1374 	return (0);
1375 }
1376 
1377 /* ARGSUSED */
1378 static int
1379 nxge_param_set_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q,
1380 	mblk_t	*mp, char *value, caddr_t cp)
1381 {
1382 	char			*end;
1383 	uint32_t		status = 0, cfg_value;
1384 	p_nxge_param_t		pa = (p_nxge_param_t)cp;
1385 	uint32_t		cfg_it = B_FALSE;
1386 	p_nxge_dma_pt_cfg_t	p_dma_cfgp;
1387 	p_nxge_hw_pt_cfg_t	p_cfgp;
1388 	uint32_t		*val_ptr, *old_val_ptr;
1389 	nxge_param_map_t	*vmap, *old_map;
1390 	p_nxge_class_pt_cfg_t	p_class_cfgp;
1391 	uint64_t		cfgd_vlans;
1392 	int			i, inc = 0, cfg_position;
1393 	nxge_mv_cfg_t		*vlan_tbl;
1394 
1395 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp "));
1396 
1397 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
1398 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
1399 	p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
1400 	vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0];
1401 
1402 	cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX);
1403 
1404 	/* now do decoding */
1405 	cfgd_vlans = ((pa->type &  NXGE_PARAM_ARRAY_CNT_MASK) >>
1406 		NXGE_PARAM_ARRAY_CNT_SHIFT);
1407 
1408 	if (cfgd_vlans == NXGE_PARAM_ARRAY_INIT_SIZE) {
1409 		/*
1410 		 * for now, we process only upto max
1411 		 * NXGE_PARAM_ARRAY_INIT_SIZE parameters
1412 		 * In the future, we may want to expand
1413 		 * the storage array and continue
1414 		 */
1415 		return (EINVAL);
1416 	}
1417 
1418 	vmap = (nxge_param_map_t *)&cfg_value;
1419 	if ((vmap->param_id) &&
1420 		(vmap->param_id < NXGE_MAX_VLANS) &&
1421 		(vmap->map_to < p_cfgp->max_rdc_grpids)) {
1422 		NXGE_DEBUG_MSG((nxgep, NDD_CTL,
1423 			"nxge_param_set_vlan_rdcgrp mapping"
1424 			" id %d grp %d",
1425 			vmap->param_id, vmap->map_to));
1426 #if defined(__i386)
1427 		val_ptr = (uint32_t *)(uint32_t)pa->value;
1428 #else
1429 		val_ptr = (uint32_t *)pa->value;
1430 #endif
1431 #if defined(__i386)
1432 		old_val_ptr = (uint32_t *)(uint32_t)pa->old_value;
1433 #else
1434 		old_val_ptr = (uint32_t *)pa->old_value;
1435 #endif
1436 
1437 		/* search to see if this vlan id is already configured */
1438 		for (i = 0; i < cfgd_vlans; i++) {
1439 			old_map = (nxge_param_map_t *)&val_ptr[i];
1440 			if ((old_map->param_id == 0) ||
1441 				(vmap->param_id == old_map->param_id) ||
1442 				(vlan_tbl[vmap->param_id].flag)) {
1443 				cfg_position = i;
1444 				break;
1445 			}
1446 		}
1447 
1448 		if (cfgd_vlans == 0) {
1449 			cfg_position = 0;
1450 			inc++;
1451 		}
1452 
1453 		if (i == cfgd_vlans) {
1454 			cfg_position = i;
1455 			inc++;
1456 		}
1457 
1458 		NXGE_DEBUG_MSG((nxgep, NDD2_CTL,
1459 			"set_vlan_rdcgrp mapping"
1460 			" i %d cfgd_vlans %llx position %d ",
1461 			i, cfgd_vlans, cfg_position));
1462 		if (val_ptr[cfg_position] != cfg_value) {
1463 			old_val_ptr[cfg_position] = val_ptr[cfg_position];
1464 			val_ptr[cfg_position] = cfg_value;
1465 			vlan_tbl[vmap->param_id].mpr_npr = vmap->pref;
1466 			vlan_tbl[vmap->param_id].flag = 1;
1467 			vlan_tbl[vmap->param_id].rdctbl =
1468 			    vmap->map_to + p_cfgp->start_rdc_grpid;
1469 			cfg_it = B_TRUE;
1470 			if (inc) {
1471 				cfgd_vlans++;
1472 				pa->type &= ~NXGE_PARAM_ARRAY_CNT_MASK;
1473 				pa->type |= (cfgd_vlans <<
1474 						    NXGE_PARAM_ARRAY_CNT_SHIFT);
1475 
1476 			}
1477 			NXGE_DEBUG_MSG((nxgep, NDD2_CTL,
1478 				"after: param_set_vlan_rdcgrp "
1479 				" cfg_vlans %llx position %d \n",
1480 				cfgd_vlans, cfg_position));
1481 		}
1482 	} else {
1483 		return (EINVAL);
1484 	}
1485 
1486 	if (cfg_it == B_TRUE) {
1487 		status = nxge_fflp_config_vlan_table(nxgep,
1488 			(uint16_t)vmap->param_id);
1489 		if (status != NXGE_OK)
1490 			return (EINVAL);
1491 	}
1492 
1493 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_vlan_rdcgrp"));
1494 	return (0);
1495 }
1496 
1497 /* ARGSUSED */
1498 static int
1499 nxge_param_get_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q,
1500 	mblk_t *mp, caddr_t cp)
1501 {
1502 
1503 	uint_t 			print_len, buf_len;
1504 	p_mblk_t		np;
1505 	int			i;
1506 	uint32_t		*val_ptr;
1507 	nxge_param_map_t	*vmap;
1508 	p_nxge_param_t		pa = (p_nxge_param_t)cp;
1509 	p_nxge_class_pt_cfg_t 	p_class_cfgp;
1510 	p_nxge_dma_pt_cfg_t	p_dma_cfgp;
1511 	p_nxge_hw_pt_cfg_t	p_cfgp;
1512 	uint64_t		cfgd_vlans = 0;
1513 	nxge_mv_cfg_t		*vlan_tbl;
1514 	int			buff_alloc_size =
1515 					NXGE_NDD_INFODUMP_BUFF_SIZE * 32;
1516 
1517 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp "));
1518 	(void) mi_mpprintf(mp, "VLAN RDC Mapping Information for Port\t %d \n",
1519 		nxgep->function_num);
1520 
1521 	if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) {
1522 		(void) mi_mpprintf(mp, "%s\n", "out of buffer");
1523 		return (0);
1524 	}
1525 
1526 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
1527 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
1528 
1529 	buf_len = buff_alloc_size;
1530 	mp->b_cont = np;
1531 	cfgd_vlans = (pa->type &  NXGE_PARAM_ARRAY_CNT_MASK) >>
1532 		NXGE_PARAM_ARRAY_CNT_SHIFT;
1533 
1534 	i = (int)cfgd_vlans;
1535 	p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
1536 	vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0];
1537 	print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
1538 		"Configured VLANs %d\n"
1539 		"VLAN ID\t RDC GRP (Actual/Port)\t"
1540 		" Prefernce\n", i);
1541 	((mblk_t *)np)->b_wptr += print_len;
1542 	buf_len -= print_len;
1543 #if defined(__i386)
1544 	val_ptr = (uint32_t *)(uint32_t)pa->value;
1545 #else
1546 	val_ptr = (uint32_t *)pa->value;
1547 #endif
1548 
1549 	for (i = 0; i < cfgd_vlans; i++) {
1550 		vmap = (nxge_param_map_t *)&val_ptr[i];
1551 		if (p_class_cfgp->vlan_tbl[vmap->param_id].flag) {
1552 			print_len = snprintf((char *)((mblk_t *)np)->b_wptr,
1553 				buf_len,
1554 				"  %d\t\t %d/%d\t\t %d\n",
1555 				vmap->param_id,
1556 				vlan_tbl[vmap->param_id].rdctbl,
1557 				vlan_tbl[vmap->param_id].rdctbl -
1558 				p_cfgp->start_rdc_grpid,
1559 				vlan_tbl[vmap->param_id].mpr_npr);
1560 			((mblk_t *)np)->b_wptr += print_len;
1561 			buf_len -= print_len;
1562 		}
1563 	}
1564 
1565 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_vlan_rdcgrp"));
1566 	return (0);
1567 }
1568 
1569 /* ARGSUSED */
1570 static int
1571 nxge_param_get_mac_rdcgrp(p_nxge_t nxgep, queue_t *q,
1572 	mblk_t *mp, caddr_t cp)
1573 {
1574 	uint_t			print_len, buf_len;
1575 	p_mblk_t		np;
1576 	int			i;
1577 	p_nxge_class_pt_cfg_t 	p_class_cfgp;
1578 	p_nxge_dma_pt_cfg_t	p_dma_cfgp;
1579 	p_nxge_hw_pt_cfg_t	p_cfgp;
1580 	nxge_mv_cfg_t		*mac_host_info;
1581 
1582 	int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE * 32;
1583 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac_rdcgrp "));
1584 	(void) mi_mpprintf(mp,
1585 		"MAC ADDR RDC Mapping Information for Port\t %d\n",
1586 		nxgep->function_num);
1587 
1588 	if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) {
1589 		(void) mi_mpprintf(mp, "%s\n", "out of buffer");
1590 		return (0);
1591 	}
1592 
1593 	buf_len = buff_alloc_size;
1594 	mp->b_cont = np;
1595 	p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
1596 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
1597 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
1598 	mac_host_info = (nxge_mv_cfg_t	*)&p_class_cfgp->mac_host_info[0];
1599 	print_len = snprintf((char *)np->b_wptr, buf_len,
1600 		"MAC ID\t RDC GRP (Actual/Port)\t"
1601 		" Prefernce\n");
1602 	((mblk_t *)np)->b_wptr += print_len;
1603 	buf_len -= print_len;
1604 	for (i = 0; i < p_cfgp->max_macs; i++) {
1605 		if (mac_host_info[i].flag) {
1606 			print_len = snprintf((char *)((mblk_t *)np)->b_wptr,
1607 				buf_len,
1608 				"   %d\t  %d/%d\t\t %d\n",
1609 				i, mac_host_info[i].rdctbl,
1610 				mac_host_info[i].rdctbl -
1611 				p_cfgp->start_rdc_grpid,
1612 				mac_host_info[i].mpr_npr);
1613 			((mblk_t *)np)->b_wptr += print_len;
1614 			buf_len -= print_len;
1615 		}
1616 	}
1617 	print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
1618 		"Done Info Dumping \n");
1619 	((mblk_t *)np)->b_wptr += print_len;
1620 	buf_len -= print_len;
1621 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_macrdcgrp"));
1622 	return (0);
1623 }
1624 
1625 /* ARGSUSED */
1626 static int
1627 nxge_param_tcam_enable(p_nxge_t nxgep, queue_t *q,
1628 	mblk_t *mp, char *value, caddr_t cp)
1629 {
1630 	uint32_t	status = 0, cfg_value;
1631 	p_nxge_param_t	pa = (p_nxge_param_t)cp;
1632 	uint32_t	cfg_it = B_FALSE;
1633 	char		*end;
1634 
1635 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_tcam_enable"));
1636 
1637 	cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY);
1638 	if (pa->value != cfg_value) {
1639 		pa->old_value = pa->value;
1640 		pa->value = cfg_value;
1641 		cfg_it = B_TRUE;
1642 	}
1643 
1644 	if (cfg_it == B_TRUE) {
1645 		if (pa->value)
1646 			status = nxge_fflp_config_tcam_enable(nxgep);
1647 		else
1648 			status = nxge_fflp_config_tcam_disable(nxgep);
1649 		if (status != NXGE_OK)
1650 			return (EINVAL);
1651 	}
1652 
1653 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_tcam_enable"));
1654 	return (0);
1655 }
1656 
1657 /* ARGSUSED */
1658 static int
1659 nxge_param_hash_lookup_enable(p_nxge_t nxgep, queue_t *q,
1660 	mblk_t *mp, char *value, caddr_t cp)
1661 {
1662 	uint32_t	status = 0, cfg_value;
1663 	p_nxge_param_t	pa = (p_nxge_param_t)cp;
1664 	uint32_t	cfg_it = B_FALSE;
1665 	char		*end;
1666 
1667 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_hash_lookup_enable"));
1668 
1669 	cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY);
1670 	if (pa->value != cfg_value) {
1671 		pa->old_value = pa->value;
1672 		pa->value = cfg_value;
1673 		cfg_it = B_TRUE;
1674 	}
1675 
1676 	if (cfg_it == B_TRUE) {
1677 		if (pa->value)
1678 			status = nxge_fflp_config_hash_lookup_enable(nxgep);
1679 		else
1680 			status = nxge_fflp_config_hash_lookup_disable(nxgep);
1681 		if (status != NXGE_OK)
1682 			return (EINVAL);
1683 	}
1684 
1685 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_hash_lookup_enable"));
1686 	return (0);
1687 }
1688 
1689 /* ARGSUSED */
1690 static int
1691 nxge_param_llc_snap_enable(p_nxge_t nxgep, queue_t *q,
1692 	mblk_t *mp, char *value, caddr_t cp)
1693 {
1694 	char		*end;
1695 	uint32_t	status = 0, cfg_value;
1696 	p_nxge_param_t	pa = (p_nxge_param_t)cp;
1697 	uint32_t	cfg_it = B_FALSE;
1698 
1699 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_llc_snap_enable"));
1700 
1701 	cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY);
1702 	if (pa->value != cfg_value) {
1703 		pa->old_value = pa->value;
1704 		pa->value = cfg_value;
1705 		cfg_it = B_TRUE;
1706 	}
1707 
1708 	if (cfg_it == B_TRUE) {
1709 		if (pa->value)
1710 			status = nxge_fflp_config_tcam_enable(nxgep);
1711 		else
1712 			status = nxge_fflp_config_tcam_disable(nxgep);
1713 		if (status != NXGE_OK)
1714 			return (EINVAL);
1715 	}
1716 
1717 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_llc_snap_enable"));
1718 	return (0);
1719 }
1720 
1721 /* ARGSUSED */
1722 static int
1723 nxge_param_set_ether_usr(p_nxge_t nxgep, queue_t *q,
1724 	mblk_t	*mp, char *value, caddr_t cp)
1725 {
1726 	char		*end;
1727 	uint8_t		ether_class;
1728 	uint32_t	status = 0, cfg_value;
1729 	p_nxge_param_t	pa = (p_nxge_param_t)cp;
1730 	uint8_t		cfg_it = B_FALSE;
1731 
1732 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ether_usr"));
1733 
1734 	cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX);
1735 	if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) {
1736 		return (EINVAL);
1737 	}
1738 
1739 	if (pa->value != cfg_value) {
1740 		pa->old_value = pa->value;
1741 		pa->value = cfg_value;
1742 		cfg_it = B_TRUE;
1743 	}
1744 
1745 	/* do the actual hw setup  */
1746 	if (cfg_it == B_TRUE) {
1747 		ether_class = mi_strtol(pa->name, &end, 10);
1748 #ifdef lint
1749 		ether_class = ether_class;
1750 #endif
1751 		NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_ether_usr"));
1752 	}
1753 
1754 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ether_usr"));
1755 	return (status);
1756 }
1757 
1758 /* ARGSUSED */
1759 static int
1760 nxge_param_set_ip_usr(p_nxge_t nxgep, queue_t *q,
1761 	mblk_t *mp, char *value, caddr_t cp)
1762 {
1763 	char		*end;
1764 	tcam_class_t	class;
1765 	uint32_t	status, cfg_value;
1766 	p_nxge_param_t	pa = (p_nxge_param_t)cp;
1767 	uint32_t	cfg_it = B_FALSE;
1768 
1769 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_usr"));
1770 
1771 	cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX);
1772 	if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) {
1773 		return (EINVAL);
1774 	}
1775 
1776 	if (pa->value != cfg_value) {
1777 		pa->old_value = pa->value;
1778 		pa->value = cfg_value;
1779 		cfg_it = B_TRUE;
1780 	}
1781 
1782 	/* do the actual hw setup with cfg_value. */
1783 	if (cfg_it == B_TRUE) {
1784 		class = mi_strtol(pa->name, &end, 10);
1785 		status = nxge_fflp_ip_usr_class_config(nxgep, class, pa->value);
1786 	}
1787 
1788 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_usr"));
1789 	return (status);
1790 }
1791 
1792 /* ARGSUSED */
1793 static int
1794 nxge_class_name_2value(p_nxge_t nxgep, char *name)
1795 {
1796 	int		i;
1797 	int		class_instance = param_class_opt_ip_usr4;
1798 	p_nxge_param_t	param_arr;
1799 
1800 	param_arr = nxgep->param_arr;
1801 	for (i = TCAM_CLASS_IP_USER_4; i <= TCAM_CLASS_SCTP_IPV6; i++) {
1802 		if (strcmp(param_arr[class_instance].name, name) == 0)
1803 			return (i);
1804 		class_instance++;
1805 	}
1806 	return (-1);
1807 }
1808 
1809 /* ARGSUSED */
1810 static int
1811 nxge_param_set_ip_opt(p_nxge_t nxgep, queue_t *q,
1812 	mblk_t *mp, char *value, caddr_t cp)
1813 {
1814 	char		*end;
1815 	uint32_t	status, cfg_value;
1816 	p_nxge_param_t	pa = (p_nxge_param_t)cp;
1817 	tcam_class_t	class;
1818 	uint32_t	cfg_it = B_FALSE;
1819 
1820 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_opt"));
1821 
1822 	cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX);
1823 	if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) {
1824 		return (EINVAL);
1825 	}
1826 
1827 	if (pa->value != cfg_value) {
1828 		pa->old_value = pa->value;
1829 		pa->value = cfg_value;
1830 		cfg_it = B_TRUE;
1831 	}
1832 
1833 	if (cfg_it == B_TRUE) {
1834 		/* do the actual hw setup  */
1835 		class = nxge_class_name_2value(nxgep, pa->name);
1836 		if (class == -1)
1837 			return (EINVAL);
1838 
1839 		status = nxge_fflp_ip_class_config(nxgep, class, pa->value);
1840 		if (status != NXGE_OK)
1841 			return (EINVAL);
1842 	}
1843 
1844 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_opt"));
1845 	return (0);
1846 }
1847 
1848 /* ARGSUSED */
1849 static int
1850 nxge_param_get_ip_opt(p_nxge_t nxgep, queue_t *q,
1851 	mblk_t *mp, caddr_t cp)
1852 {
1853 	uint32_t status, cfg_value;
1854 	p_nxge_param_t pa = (p_nxge_param_t)cp;
1855 	tcam_class_t class;
1856 
1857 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_ip_opt"));
1858 
1859 	/* do the actual hw setup  */
1860 	class = nxge_class_name_2value(nxgep, pa->name);
1861 	if (class == -1)
1862 		return (EINVAL);
1863 
1864 	cfg_value = 0;
1865 	status = nxge_fflp_ip_class_config_get(nxgep, class, &cfg_value);
1866 	if (status != NXGE_OK)
1867 		return (EINVAL);
1868 
1869 	NXGE_DEBUG_MSG((nxgep, NDD_CTL,
1870 		"nxge_param_get_ip_opt_get %x ", cfg_value));
1871 
1872 	pa->value = cfg_value;
1873 	(void) mi_mpprintf(mp, "%x", cfg_value);
1874 
1875 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_ip_opt status "));
1876 	return (0);
1877 }
1878 
1879 /* ARGSUSED */
1880 static int
1881 nxge_param_fflp_hash_init(p_nxge_t nxgep, queue_t *q,
1882 	mblk_t *mp, char *value, caddr_t cp)
1883 {
1884 	char		*end;
1885 	uint32_t	status, cfg_value;
1886 	p_nxge_param_t	pa = (p_nxge_param_t)cp;
1887 	tcam_class_t	class;
1888 	uint32_t	cfg_it = B_FALSE;
1889 
1890 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_fflp_hash_init"));
1891 
1892 	cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX);
1893 	if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) {
1894 		return (EINVAL);
1895 	}
1896 
1897 	NXGE_DEBUG_MSG((nxgep, NDD_CTL,
1898 		"nxge_param_fflp_hash_init value %x", cfg_value));
1899 
1900 	if (pa->value != cfg_value) {
1901 		pa->old_value = pa->value;
1902 		pa->value = cfg_value;
1903 		cfg_it = B_TRUE;
1904 	}
1905 
1906 	if (cfg_it == B_TRUE) {
1907 		char *h_name;
1908 
1909 		/* do the actual hw setup */
1910 		h_name = pa->name;
1911 		h_name++;
1912 		class = mi_strtol(h_name, &end, 10);
1913 		switch (class) {
1914 			case 1:
1915 				status = nxge_fflp_set_hash1(nxgep,
1916 					(uint32_t)pa->value);
1917 				break;
1918 			case 2:
1919 				status = nxge_fflp_set_hash2(nxgep,
1920 					(uint16_t)pa->value);
1921 				break;
1922 
1923 			default:
1924 			NXGE_DEBUG_MSG((nxgep, NDD_CTL,
1925 				" nxge_param_fflp_hash_init"
1926 				" %s Wrong hash var %d",
1927 				pa->name, class));
1928 			return (EINVAL);
1929 		}
1930 		if (status != NXGE_OK)
1931 			return (EINVAL);
1932 	}
1933 
1934 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_fflp_hash_init"));
1935 	return (0);
1936 }
1937 
1938 /* ARGSUSED */
1939 static int
1940 nxge_param_set_grp_rdc(p_nxge_t nxgep, queue_t *q,
1941 	mblk_t *mp, char *value, caddr_t cp)
1942 {
1943 	char			*end;
1944 	uint32_t		status = 0, cfg_value;
1945 	p_nxge_param_t		pa = (p_nxge_param_t)cp;
1946 	uint32_t		cfg_it = B_FALSE;
1947 	int			rdc_grp;
1948 	uint8_t			real_rdc;
1949 	p_nxge_dma_pt_cfg_t	p_dma_cfgp;
1950 	p_nxge_hw_pt_cfg_t	p_cfgp;
1951 	p_nxge_rdc_grp_t	rdc_grp_p;
1952 
1953 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
1954 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
1955 
1956 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_grp_rdc"));
1957 
1958 	cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY);
1959 	if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) {
1960 		return (EINVAL);
1961 	}
1962 
1963 	if (cfg_value >= p_cfgp->max_rdcs) {
1964 		return (EINVAL);
1965 	}
1966 
1967 	if (pa->value != cfg_value) {
1968 		pa->old_value = pa->value;
1969 		pa->value = cfg_value;
1970 		cfg_it = B_TRUE;
1971 	}
1972 
1973 	if (cfg_it == B_TRUE) {
1974 		char *grp_name;
1975 		grp_name = pa->name;
1976 		grp_name += strlen("default-grp");
1977 		rdc_grp = mi_strtol(grp_name, &end, 10);
1978 		rdc_grp_p = &p_dma_cfgp->rdc_grps[rdc_grp];
1979 		real_rdc = rdc_grp_p->start_rdc + cfg_value;
1980 		if (nxge_check_rxdma_rdcgrp_member(nxgep, rdc_grp,
1981 				cfg_value) == B_FALSE) {
1982 			pa->value = pa->old_value;
1983 			NXGE_DEBUG_MSG((nxgep, NDD_CTL,
1984 				" nxge_param_set_grp_rdc"
1985 				" %d read %d actual %d outof range",
1986 				rdc_grp, cfg_value, real_rdc));
1987 			return (EINVAL);
1988 		}
1989 		status = nxge_rxdma_cfg_rdcgrp_default_rdc(nxgep, rdc_grp,
1990 							    real_rdc);
1991 		if (status != NXGE_OK)
1992 			return (EINVAL);
1993 	}
1994 
1995 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_grp_rdc"));
1996 	return (0);
1997 }
1998 
1999 /* ARGSUSED */
2000 static int
2001 nxge_param_set_port_rdc(p_nxge_t nxgep, queue_t *q,
2002 	mblk_t *mp, char *value, caddr_t cp)
2003 {
2004 	char		*end;
2005 	uint32_t	status = B_TRUE, cfg_value;
2006 	p_nxge_param_t	pa = (p_nxge_param_t)cp;
2007 	uint32_t	cfg_it = B_FALSE;
2008 
2009 	p_nxge_dma_pt_cfg_t	p_dma_cfgp;
2010 	p_nxge_hw_pt_cfg_t	p_cfgp;
2011 
2012 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_port_rdc"));
2013 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2014 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
2015 
2016 	cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY);
2017 	if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) {
2018 		return (EINVAL);
2019 	}
2020 
2021 	if (pa->value != cfg_value) {
2022 		if (cfg_value >= p_cfgp->max_rdcs)
2023 			return (EINVAL);
2024 		pa->old_value = pa->value;
2025 		pa->value = cfg_value;
2026 		cfg_it = B_TRUE;
2027 	}
2028 
2029 	if (cfg_it == B_TRUE) {
2030 		status = nxge_rxdma_cfg_port_default_rdc(nxgep,
2031 			nxgep->function_num,
2032 			nxgep->rdc[cfg_value]);
2033 		if (status != NXGE_OK)
2034 			return (EINVAL);
2035 	}
2036 
2037 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_port_rdc"));
2038 	return (0);
2039 }
2040 
2041 /* ARGSUSED */
2042 static int
2043 nxge_param_set_nxge_debug_flag(p_nxge_t nxgep, queue_t *q,
2044 	mblk_t *mp, char *value, caddr_t cp)
2045 {
2046 	char *end;
2047 	uint32_t status = 0;
2048 	uint64_t cfg_value = 0;
2049 	p_nxge_param_t pa = (p_nxge_param_t)cp;
2050 	uint32_t cfg_it = B_FALSE;
2051 
2052 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_nxge_debug_flag"));
2053 	cfg_value = mi_strtol(value, &end, BASE_HEX);
2054 
2055 	if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) {
2056 		NXGE_DEBUG_MSG((nxgep, NDD_CTL,
2057 			" nxge_param_set_nxge_debug_flag"
2058 			" outof range %llx", cfg_value));
2059 		return (EINVAL);
2060 	}
2061 	if (pa->value != cfg_value) {
2062 		pa->old_value = pa->value;
2063 		pa->value = cfg_value;
2064 		cfg_it = B_TRUE;
2065 	}
2066 
2067 	if (cfg_it == B_TRUE) {
2068 		nxgep->nxge_debug_level = pa->value;
2069 	}
2070 
2071 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_nxge_debug_flag"));
2072 	return (status);
2073 }
2074 
2075 /* ARGSUSED */
2076 static int
2077 nxge_param_get_debug_flag(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
2078 {
2079 	int		status = 0;
2080 	p_nxge_param_t	pa = (p_nxge_param_t)cp;
2081 
2082 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_debug_flag"));
2083 
2084 	if (pa->value > 0xffffffff)
2085 		(void) mi_mpprintf(mp, "%x%x",  (int)(pa->value >> 32),
2086 			(int)(pa->value & 0xffffffff));
2087 	else
2088 		(void) mi_mpprintf(mp, "%x", (int)pa->value);
2089 
2090 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_debug_flag"));
2091 	return (status);
2092 }
2093 
2094 /* ARGSUSED */
2095 static int
2096 nxge_param_set_npi_debug_flag(p_nxge_t nxgep, queue_t *q,
2097 	mblk_t *mp, char *value, caddr_t cp)
2098 {
2099 	char		*end;
2100 	uint32_t	status = 0;
2101 	uint64_t	 cfg_value = 0;
2102 	p_nxge_param_t	pa;
2103 	uint32_t	cfg_it = B_FALSE;
2104 
2105 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_npi_debug_flag"));
2106 	cfg_value = mi_strtol(value, &end, BASE_HEX);
2107 	pa = (p_nxge_param_t)cp;
2108 	if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) {
2109 		NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_npi_debug_flag"
2110 				    " outof range %llx", cfg_value));
2111 		return (EINVAL);
2112 	}
2113 	if (pa->value != cfg_value) {
2114 		pa->old_value = pa->value;
2115 		pa->value = cfg_value;
2116 		cfg_it = B_TRUE;
2117 	}
2118 
2119 	if (cfg_it == B_TRUE) {
2120 		npi_debug_level = pa->value;
2121 	}
2122 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_debug_flag"));
2123 	return (status);
2124 }
2125 
2126 /* ARGSUSED */
2127 static int
2128 nxge_param_dump_rdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
2129 {
2130 	uint_t rdc;
2131 
2132 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_rdc"));
2133 
2134 	(void) npi_rxdma_dump_fzc_regs(NXGE_DEV_NPI_HANDLE(nxgep));
2135 	for (rdc = 0; rdc < nxgep->nrdc; rdc++)
2136 		(void) nxge_dump_rxdma_channel(nxgep, nxgep->rdc[rdc]);
2137 
2138 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_rdc"));
2139 	return (0);
2140 }
2141 
2142 /* ARGSUSED */
2143 static int
2144 nxge_param_dump_tdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
2145 {
2146 	uint_t	tdc;
2147 
2148 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_tdc"));
2149 
2150 	for (tdc = 0; tdc < nxgep->ntdc; tdc++)
2151 		(void) nxge_txdma_regs_dump(nxgep, nxgep->tdc[tdc]);
2152 
2153 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_tdc"));
2154 	return (0);
2155 }
2156 
2157 /* ARGSUSED */
2158 static int
2159 nxge_param_dump_fflp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
2160 {
2161 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_fflp_regs"));
2162 
2163 	(void) npi_fflp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep));
2164 
2165 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_fflp_regs"));
2166 	return (0);
2167 }
2168 
2169 /* ARGSUSED */
2170 static int
2171 nxge_param_dump_mac_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
2172 {
2173 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_mac_regs"));
2174 
2175 	(void) npi_mac_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep),
2176 		nxgep->function_num);
2177 
2178 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_mac_regs"));
2179 	return (0);
2180 }
2181 
2182 /* ARGSUSED */
2183 static int
2184 nxge_param_dump_ipp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
2185 {
2186 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_ipp_regs"));
2187 
2188 	(void) npi_ipp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep),
2189 		nxgep->function_num);
2190 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ipp_regs"));
2191 	return (0);
2192 }
2193 
2194 /* ARGSUSED */
2195 static int
2196 nxge_param_dump_vlan_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
2197 {
2198 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_vlan_table"));
2199 
2200 	(void) npi_fflp_vlan_tbl_dump(NXGE_DEV_NPI_HANDLE(nxgep));
2201 
2202 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_vlan_table"));
2203 	return (0);
2204 }
2205 
2206 /* ARGSUSED */
2207 static int
2208 nxge_param_dump_rdc_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
2209 {
2210 	uint8_t	table;
2211 
2212 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_rdc_table"));
2213 	for (table = 0; table < NXGE_MAX_RDC_GROUPS; table++) {
2214 		(void) npi_rxdma_dump_rdc_table(NXGE_DEV_NPI_HANDLE(nxgep),
2215 					    table);
2216 	}
2217 
2218 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_rdc_table"));
2219 	return (0);
2220 }
2221 
2222 typedef struct block_info {
2223 	char		*name;
2224 	uint32_t	offset;
2225 } block_info_t;
2226 
2227 block_info_t reg_block[] = {
2228 	{"PIO",		PIO},
2229 	{"FZC_PIO",	FZC_PIO},
2230 	{"FZC_XMAC",	FZC_MAC},
2231 	{"FZC_IPP",	FZC_IPP},
2232 	{"FFLP",	FFLP},
2233 	{"FZC_FFLP",	FZC_FFLP},
2234 	{"PIO_VADDR",	PIO_VADDR},
2235 	{"ZCP",	ZCP},
2236 	{"FZC_ZCP",	FZC_ZCP},
2237 	{"DMC",	DMC},
2238 	{"FZC_DMC",	FZC_DMC},
2239 	{"TXC",	TXC},
2240 	{"FZC_TXC",	FZC_TXC},
2241 	{"PIO_LDSV",	PIO_LDSV},
2242 	{"PIO_LDGIM",	PIO_LDGIM},
2243 	{"PIO_IMASK0",	PIO_IMASK0},
2244 	{"PIO_IMASK1",	PIO_IMASK1},
2245 	{"FZC_PROM",	FZC_PROM},
2246 	{"END",	ALL_FF_32},
2247 };
2248 
2249 /* ARGSUSED */
2250 static int
2251 nxge_param_dump_ptrs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
2252 {
2253 	uint_t			print_len, buf_len;
2254 	p_mblk_t		np;
2255 	int			rdc, tdc, block;
2256 	uint64_t		base;
2257 	p_nxge_dma_pt_cfg_t	p_dma_cfgp;
2258 	p_nxge_hw_pt_cfg_t	p_cfgp;
2259 	int			buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_8K;
2260 	p_tx_ring_t 		*tx_rings;
2261 	p_rx_rcr_rings_t 	rx_rcr_rings;
2262 	p_rx_rcr_ring_t		*rcr_rings;
2263 	p_rx_rbr_rings_t 	rx_rbr_rings;
2264 	p_rx_rbr_ring_t		*rbr_rings;
2265 
2266 	NXGE_DEBUG_MSG((nxgep, IOC_CTL,
2267 		"==> nxge_param_dump_ptrs"));
2268 
2269 	(void) mi_mpprintf(mp, "ptr information for Port\t %d \n",
2270 		nxgep->function_num);
2271 
2272 	if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) {
2273 		/* The following may work even if we cannot get a large buf. */
2274 		(void) mi_mpprintf(mp, "%s\n", "out of buffer");
2275 		return (0);
2276 	}
2277 
2278 	buf_len = buff_alloc_size;
2279 	mp->b_cont = np;
2280 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2281 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
2282 
2283 	rx_rcr_rings = nxgep->rx_rcr_rings;
2284 	rcr_rings = rx_rcr_rings->rcr_rings;
2285 	rx_rbr_rings = nxgep->rx_rbr_rings;
2286 	rbr_rings = rx_rbr_rings->rbr_rings;
2287 	print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
2288 		"nxgep (nxge_t) $%p\n"
2289 		"dev_regs (dev_regs_t) $%p\n",
2290 		nxgep, nxgep->dev_regs);
2291 
2292 	ADVANCE_PRINT_BUFFER(np, print_len, buf_len);
2293 
2294 	/* do register pointers */
2295 	print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
2296 		"reg base (npi_reg_ptr_t) $%p\t "
2297 		"pci reg (npi_reg_ptr_t) $%p\n",
2298 		nxgep->dev_regs->nxge_regp,
2299 		nxgep->dev_regs->nxge_pciregp);
2300 
2301 	ADVANCE_PRINT_BUFFER(np, print_len, buf_len);
2302 
2303 	print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
2304 		"\nBlock \t Offset \n");
2305 
2306 	ADVANCE_PRINT_BUFFER(np, print_len, buf_len);
2307 	block = 0;
2308 #if defined(__i386)
2309 	base = (uint64_t)(uint32_t)nxgep->dev_regs->nxge_regp;
2310 #else
2311 	base = (uint64_t)nxgep->dev_regs->nxge_regp;
2312 #endif
2313 	while (reg_block[block].offset != ALL_FF_32) {
2314 		print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
2315 			"%9s\t 0x%llx\n",
2316 			reg_block[block].name,
2317 			(unsigned long long)(reg_block[block].offset + base));
2318 		ADVANCE_PRINT_BUFFER(np, print_len, buf_len);
2319 		block++;
2320 	}
2321 
2322 	print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
2323 		"\nRDC\t rcrp (rx_rcr_ring_t)\t "
2324 		"rbrp (rx_rbr_ring_t)\n");
2325 
2326 	ADVANCE_PRINT_BUFFER(np, print_len, buf_len);
2327 
2328 	for (rdc = 0; rdc < p_cfgp->max_rdcs; rdc++) {
2329 		print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
2330 			" %d\t  $%p\t\t   $%p\n",
2331 			rdc, rcr_rings[rdc],
2332 			rbr_rings[rdc]);
2333 		ADVANCE_PRINT_BUFFER(np, print_len, buf_len);
2334 	}
2335 
2336 	print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
2337 			    "\nTDC\t tdcp (tx_ring_t)\n");
2338 
2339 	ADVANCE_PRINT_BUFFER(np, print_len, buf_len);
2340 	tx_rings = nxgep->tx_rings->rings;
2341 	for (tdc = 0; tdc < p_cfgp->max_tdcs; tdc++) {
2342 		print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
2343 			" %d\t  $%p\n", tdc, tx_rings[tdc]);
2344 		ADVANCE_PRINT_BUFFER(np, print_len, buf_len);
2345 	}
2346 
2347 	print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, "\n\n");
2348 
2349 	ADVANCE_PRINT_BUFFER(np, print_len, buf_len);
2350 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ptrs"));
2351 	return (0);
2352 }
2353 
2354 /*
2355  * Load 'name' into the named dispatch table pointed to by 'ndp'.
2356  * 'ndp' should be the address of a char pointer cell.  If the table
2357  * does not exist (*ndp == 0), a new table is allocated and 'ndp'
2358  * is stuffed.  If there is not enough space in the table for a new
2359  * entry, more space is allocated.
2360  */
2361 /* ARGSUSED */
2362 boolean_t
2363 nxge_nd_load(caddr_t *pparam, char *name,
2364 	pfi_t get_pfi, pfi_t set_pfi, caddr_t data)
2365 {
2366 	ND	*nd;
2367 	NDE	*nde;
2368 
2369 	NXGE_DEBUG_MSG((NULL, NDD2_CTL, " ==> nxge_nd_load"));
2370 	if (!pparam)
2371 		return (B_FALSE);
2372 
2373 	if ((nd = (ND *)*pparam) == NULL) {
2374 		if ((nd = (ND *)KMEM_ZALLOC(sizeof (ND), KM_NOSLEEP)) == NULL)
2375 			return (B_FALSE);
2376 		*pparam = (caddr_t)nd;
2377 	}
2378 
2379 	if (nd->nd_tbl) {
2380 		for (nde = nd->nd_tbl; nde->nde_name; nde++) {
2381 			if (strcmp(name, nde->nde_name) == 0)
2382 				goto fill_it;
2383 		}
2384 	}
2385 
2386 	if (nd->nd_free_count <= 1) {
2387 		if ((nde = (NDE *)KMEM_ZALLOC(nd->nd_size +
2388 					NDE_ALLOC_SIZE, KM_NOSLEEP)) == NULL)
2389 			return (B_FALSE);
2390 		nd->nd_free_count += NDE_ALLOC_COUNT;
2391 		if (nd->nd_tbl) {
2392 			bcopy((char *)nd->nd_tbl, (char *)nde, nd->nd_size);
2393 			KMEM_FREE((char *)nd->nd_tbl, nd->nd_size);
2394 		} else {
2395 			nd->nd_free_count--;
2396 			nde->nde_name = "?";
2397 			nde->nde_get_pfi = nxge_nd_get_names;
2398 			nde->nde_set_pfi = nxge_set_default;
2399 		}
2400 		nde->nde_data = (caddr_t)nd;
2401 		nd->nd_tbl = nde;
2402 		nd->nd_size += NDE_ALLOC_SIZE;
2403 	}
2404 	for (nde = nd->nd_tbl; nde->nde_name; nde++)
2405 		noop;
2406 	nd->nd_free_count--;
2407 fill_it:
2408 	nde->nde_name = name;
2409 	nde->nde_get_pfi = get_pfi;
2410 	nde->nde_set_pfi = set_pfi;
2411 	nde->nde_data = data;
2412 	NXGE_DEBUG_MSG((NULL, NDD2_CTL, " <== nxge_nd_load"));
2413 
2414 	return (B_TRUE);
2415 }
2416 
2417 /*
2418  * Free the table pointed to by 'pparam'
2419  */
2420 void
2421 nxge_nd_free(caddr_t *pparam)
2422 {
2423 	ND *nd;
2424 
2425 	if ((nd = (ND *)*pparam) != NULL) {
2426 		if (nd->nd_tbl)
2427 			KMEM_FREE((char *)nd->nd_tbl, nd->nd_size);
2428 		KMEM_FREE((char *)nd, sizeof (ND));
2429 		*pparam = nil(caddr_t);
2430 	}
2431 }
2432 
2433 int
2434 nxge_nd_getset(p_nxge_t nxgep, queue_t *q, caddr_t param, p_mblk_t mp)
2435 {
2436 	int		err;
2437 	IOCP		iocp;
2438 	p_mblk_t	mp1, mp2;
2439 	ND		*nd;
2440 	NDE		*nde;
2441 	char		*valp;
2442 	size_t		avail;
2443 
2444 	if (!param) {
2445 		return (B_FALSE);
2446 	}
2447 
2448 	nd = (ND *)param;
2449 	iocp = (IOCP)mp->b_rptr;
2450 	if ((iocp->ioc_count == 0) || !(mp1 = mp->b_cont)) {
2451 		mp->b_datap->db_type = M_IOCACK;
2452 		iocp->ioc_count = 0;
2453 		iocp->ioc_error = EINVAL;
2454 		return (B_FALSE);
2455 	}
2456 
2457 	/*
2458 	 * NOTE - logic throughout nd_xxx assumes single data block for ioctl.
2459 	 *	However, existing code sends in some big buffers.
2460 	 */
2461 	avail = iocp->ioc_count;
2462 	if (mp1->b_cont) {
2463 		freemsg(mp1->b_cont);
2464 		mp1->b_cont = NULL;
2465 	}
2466 
2467 	mp1->b_datap->db_lim[-1] = '\0';	/* Force null termination */
2468 	for (valp = (char *)mp1->b_rptr; *valp != '\0'; valp++) {
2469 		if (*valp == '-')
2470 			*valp = '_';
2471 	}
2472 
2473 	valp = (char *)mp1->b_rptr;
2474 
2475 	for (nde = nd->nd_tbl; /* */; nde++) {
2476 		if (!nde->nde_name)
2477 			return (B_FALSE);
2478 		if (strcmp(nde->nde_name, valp) == 0)
2479 			break;
2480 	}
2481 	err = EINVAL;
2482 	while (*valp++)
2483 		noop;
2484 	if (!*valp || valp >= (char *)mp1->b_wptr)
2485 		valp = nilp(char);
2486 	switch (iocp->ioc_cmd) {
2487 	case ND_GET:
2488 		/*
2489 		 * (temporary) hack: "*valp" is size of user buffer for
2490 		 * copyout. If result of action routine is too big, free
2491 		 * excess and return ioc_rval as buffer size needed.
2492 		 * Return as many mblocks as will fit, free the rest.  For
2493 		 * backward compatibility, assume size of original ioctl
2494 		 * buffer if "*valp" bad or not given.
2495 		 */
2496 		if (valp)
2497 			avail = mi_strtol(valp, (char **)0, 10);
2498 		/*
2499 		 * We overwrite the name/value with the reply data
2500 		 */
2501 		mp2 = mp1;
2502 		while (mp2) {
2503 			mp2->b_wptr = mp2->b_rptr;
2504 			mp2 = mp2->b_cont;
2505 		}
2506 
2507 		if (nde->nde_get_pfi) {
2508 			err = (*nde->nde_get_pfi)(nxgep, q, mp1, nde->nde_data);
2509 		}
2510 
2511 		if (!err) {
2512 			size_t	size_out = 0;
2513 			ssize_t	excess;
2514 
2515 			iocp->ioc_rval = 0;
2516 
2517 			/* Tack on the null */
2518 			err = nxge_mk_mblk_tail_space(mp1, &mp2, 1);
2519 			if (!err) {
2520 				*mp2->b_wptr++ = '\0';
2521 				size_out = msgdsize(mp1);
2522 				excess = size_out - avail;
2523 				if (excess > 0) {
2524 					iocp->ioc_rval = (int)size_out;
2525 					size_out -= excess;
2526 					(void) adjmsg(mp1, -(excess + 1));
2527 					err = nxge_mk_mblk_tail_space(
2528 							mp1, &mp2, 1);
2529 					if (!err)
2530 						*mp2->b_wptr++ = '\0';
2531 					else
2532 						size_out = 0;
2533 				}
2534 			} else
2535 				size_out = 0;
2536 			iocp->ioc_count = size_out;
2537 		}
2538 		break;
2539 
2540 	case ND_SET:
2541 		if (valp) {
2542 			if (nde->nde_set_pfi) {
2543 				err = (*nde->nde_set_pfi)(nxgep, q, mp1, valp,
2544 							    nde->nde_data);
2545 				iocp->ioc_count = 0;
2546 				freemsg(mp1);
2547 				mp->b_cont = NULL;
2548 			}
2549 		}
2550 		break;
2551 
2552 	default:
2553 		break;
2554 	}
2555 	iocp->ioc_error = err;
2556 	mp->b_datap->db_type = M_IOCACK;
2557 	return (B_TRUE);
2558 }
2559 
2560 /* ARGSUSED */
2561 int
2562 nxge_nd_get_names(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t param)
2563 {
2564 	ND		*nd;
2565 	NDE		*nde;
2566 	char		*rwtag;
2567 	boolean_t	get_ok, set_ok;
2568 	size_t		param_len;
2569 	int		status = 0;
2570 
2571 	nd = (ND *)param;
2572 	if (!nd)
2573 		return (ENOENT);
2574 
2575 	for (nde = nd->nd_tbl; nde->nde_name; nde++) {
2576 		get_ok = (nde->nde_get_pfi != nxge_get_default) &&
2577 				(nde->nde_get_pfi != NULL);
2578 		set_ok = (nde->nde_set_pfi != nxge_set_default) &&
2579 				(nde->nde_set_pfi != NULL);
2580 		if (get_ok) {
2581 			if (set_ok)
2582 				rwtag = "read and write";
2583 			else
2584 				rwtag = "read only";
2585 		} else if (set_ok)
2586 			rwtag = "write only";
2587 		else {
2588 			continue;
2589 		}
2590 		param_len = strlen(rwtag);
2591 		param_len += strlen(nde->nde_name);
2592 		param_len += 4;
2593 
2594 		(void) mi_mpprintf(mp, "%s (%s)", nde->nde_name, rwtag);
2595 	}
2596 	return (status);
2597 }
2598 
2599 /* ARGSUSED */
2600 int
2601 nxge_get_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t data)
2602 {
2603 	return (EACCES);
2604 }
2605 
2606 /* ARGSUSED */
2607 int
2608 nxge_set_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, char *value,
2609 	caddr_t data)
2610 {
2611 	return (EACCES);
2612 }
2613 
2614 void
2615 nxge_param_ioctl(p_nxge_t nxgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp)
2616 {
2617 	int		cmd;
2618 	int		status = B_FALSE;
2619 
2620 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_ioctl"));
2621 	cmd = iocp->ioc_cmd;
2622 
2623 	switch (cmd) {
2624 	default:
2625 		NXGE_DEBUG_MSG((nxgep, IOC_CTL,
2626 			"nxge_param_ioctl: bad cmd 0x%0x", cmd));
2627 		break;
2628 
2629 	case ND_GET:
2630 	case ND_SET:
2631 		NXGE_DEBUG_MSG((nxgep, IOC_CTL,
2632 			"nxge_param_ioctl: cmd 0x%0x", cmd));
2633 		if (!nxge_nd_getset(nxgep, wq, nxgep->param_list, mp)) {
2634 			NXGE_DEBUG_MSG((nxgep, IOC_CTL,
2635 				"false ret from nxge_nd_getset"));
2636 			break;
2637 		}
2638 		status = B_TRUE;
2639 		break;
2640 	}
2641 
2642 	if (status) {
2643 		qreply(wq, mp);
2644 	} else {
2645 		miocnak(wq, mp, 0, EINVAL);
2646 	}
2647 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_ioctl"));
2648 }
2649 
2650 /* ARGSUSED */
2651 static boolean_t
2652 nxge_param_link_update(p_nxge_t nxgep)
2653 {
2654 	p_nxge_param_t 		param_arr;
2655 	nxge_param_index_t 	i;
2656 	boolean_t 		update_xcvr;
2657 	boolean_t 		update_dev;
2658 	int 			instance;
2659 	boolean_t 		status = B_TRUE;
2660 
2661 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_link_update"));
2662 
2663 	param_arr = nxgep->param_arr;
2664 	instance = nxgep->instance;
2665 	update_xcvr = B_FALSE;
2666 	for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) {
2667 		update_xcvr |= param_arr[i].value;
2668 	}
2669 
2670 	if (update_xcvr) {
2671 		update_xcvr = B_FALSE;
2672 		for (i = param_autoneg; i < param_enable_ipg0; i++) {
2673 			update_xcvr |=
2674 				(param_arr[i].value != param_arr[i].old_value);
2675 			param_arr[i].old_value = param_arr[i].value;
2676 		}
2677 		if (update_xcvr) {
2678 			RW_ENTER_WRITER(&nxgep->filter_lock);
2679 			(void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP);
2680 			(void) nxge_link_init(nxgep);
2681 			(void) nxge_mac_init(nxgep);
2682 			(void) nxge_link_monitor(nxgep, LINK_MONITOR_START);
2683 			RW_EXIT(&nxgep->filter_lock);
2684 		}
2685 	} else {
2686 		cmn_err(CE_WARN, " Last setting will leave nxge%d with "
2687 				" no link capabilities.", instance);
2688 		cmn_err(CE_WARN, " Restoring previous setting.");
2689 		for (i = param_anar_1000fdx; i < param_anar_asmpause; i++)
2690 			param_arr[i].value = param_arr[i].old_value;
2691 	}
2692 
2693 	update_dev = B_FALSE;
2694 
2695 	if (update_dev) {
2696 		RW_ENTER_WRITER(&nxgep->filter_lock);
2697 		(void) nxge_rx_mac_disable(nxgep);
2698 		(void) nxge_tx_mac_disable(nxgep);
2699 		(void) nxge_tx_mac_enable(nxgep);
2700 		(void) nxge_rx_mac_enable(nxgep);
2701 		RW_EXIT(&nxgep->filter_lock);
2702 	}
2703 
2704 nxge_param_hw_update_exit:
2705 	NXGE_DEBUG_MSG((nxgep, DDI_CTL,
2706 			"<== nxge_param_link_update status = 0x%08x", status));
2707 	return (status);
2708 }
2709