144961713Sgirish /* 244961713Sgirish * CDDL HEADER START 344961713Sgirish * 444961713Sgirish * The contents of this file are subject to the terms of the 544961713Sgirish * Common Development and Distribution License (the "License"). 644961713Sgirish * You may not use this file except in compliance with the License. 744961713Sgirish * 844961713Sgirish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 944961713Sgirish * or http://www.opensolaris.org/os/licensing. 1044961713Sgirish * See the License for the specific language governing permissions 1144961713Sgirish * and limitations under the License. 1244961713Sgirish * 1344961713Sgirish * When distributing Covered Code, include this CDDL HEADER in each 1444961713Sgirish * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1544961713Sgirish * If applicable, add the following below this CDDL HEADER, with the 1644961713Sgirish * fields enclosed by brackets "[]" replaced with your own identifying 1744961713Sgirish * information: Portions Copyright [yyyy] [name of copyright owner] 1844961713Sgirish * 1944961713Sgirish * CDDL HEADER END 2044961713Sgirish */ 2144961713Sgirish /* 227b26d9ffSSantwona Behera * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 2344961713Sgirish * Use is subject to license terms. 2444961713Sgirish */ 2544961713Sgirish 2644961713Sgirish #include <sys/nxge/nxge_impl.h> 27678453a8Sspeer #include <sys/nxge/nxge_hio.h> 28678453a8Sspeer 2944961713Sgirish #include <inet/common.h> 3044961713Sgirish #include <inet/mi.h> 3144961713Sgirish #include <inet/nd.h> 3244961713Sgirish 3344961713Sgirish extern uint64_t npi_debug_level; 3444961713Sgirish 35a3c5bd6dSspeer #define NXGE_PARAM_MAC_RW \ 36a3c5bd6dSspeer NXGE_PARAM_RW | NXGE_PARAM_MAC | \ 3744961713Sgirish NXGE_PARAM_NDD_WR_OK | NXGE_PARAM_READ_PROP 3844961713Sgirish 39a3c5bd6dSspeer #define NXGE_PARAM_MAC_DONT_SHOW \ 40a3c5bd6dSspeer NXGE_PARAM_RW | NXGE_PARAM_MAC | NXGE_PARAM_DONT_SHOW 4144961713Sgirish 42a3c5bd6dSspeer #define NXGE_PARAM_RXDMA_RW \ 43a3c5bd6dSspeer NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_NDD_WR_OK | \ 44a3c5bd6dSspeer NXGE_PARAM_READ_PROP 4544961713Sgirish 46a3c5bd6dSspeer #define NXGE_PARAM_RXDMA_RWC \ 47a3c5bd6dSspeer NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_INIT_ONLY | \ 48a3c5bd6dSspeer NXGE_PARAM_READ_PROP 4944961713Sgirish 50a3c5bd6dSspeer #define NXGE_PARAM_L2CLASS_CFG \ 51a3c5bd6dSspeer NXGE_PARAM_RW | NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_READ_PROP | \ 52a3c5bd6dSspeer NXGE_PARAM_NDD_WR_OK 5344961713Sgirish 54a3c5bd6dSspeer #define NXGE_PARAM_CLASS_RWS \ 55a3c5bd6dSspeer NXGE_PARAM_RWS | NXGE_PARAM_READ_PROP 5644961713Sgirish 5744961713Sgirish #define NXGE_PARAM_ARRAY_INIT_SIZE 0x20ULL 5844961713Sgirish 5944961713Sgirish #define SET_RX_INTR_TIME_DISABLE 0 6044961713Sgirish #define SET_RX_INTR_TIME_ENABLE 1 6144961713Sgirish #define SET_RX_INTR_PKTS 2 6244961713Sgirish 6344961713Sgirish #define BASE_ANY 0 64a3c5bd6dSspeer #define BASE_BINARY 2 6544961713Sgirish #define BASE_HEX 16 6644961713Sgirish #define BASE_DECIMAL 10 6744961713Sgirish #define ALL_FF_64 0xFFFFFFFFFFFFFFFFULL 6844961713Sgirish #define ALL_FF_32 0xFFFFFFFFUL 6944961713Sgirish 7044961713Sgirish #define NXGE_NDD_INFODUMP_BUFF_SIZE 2048 /* is 2k enough? */ 7144961713Sgirish #define NXGE_NDD_INFODUMP_BUFF_8K 8192 7244961713Sgirish #define NXGE_NDD_INFODUMP_BUFF_16K 0x2000 7344961713Sgirish #define NXGE_NDD_INFODUMP_BUFF_64K 0x8000 7444961713Sgirish 7544961713Sgirish #define PARAM_OUTOF_RANGE(vptr, eptr, rval, pa) \ 7644961713Sgirish ((vptr == eptr) || (rval < pa->minimum) || (rval > pa->maximum)) 7744961713Sgirish 7844961713Sgirish #define ADVANCE_PRINT_BUFFER(pmp, plen, rlen) { \ 7944961713Sgirish ((mblk_t *)pmp)->b_wptr += plen; \ 8044961713Sgirish rlen -= plen; \ 81a3c5bd6dSspeer } 8244961713Sgirish 834045d941Ssowmini int nxge_param_set_mac(p_nxge_t, queue_t *, 84a3c5bd6dSspeer mblk_t *, char *, caddr_t); 8544961713Sgirish static int nxge_param_set_port_rdc(p_nxge_t, queue_t *, 86a3c5bd6dSspeer mblk_t *, char *, caddr_t); 8744961713Sgirish static int nxge_param_set_grp_rdc(p_nxge_t, queue_t *, 88a3c5bd6dSspeer mblk_t *, char *, caddr_t); 8944961713Sgirish static int nxge_param_set_ether_usr(p_nxge_t, 90a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 9144961713Sgirish static int nxge_param_set_ip_usr(p_nxge_t, 92a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 9344961713Sgirish static int nxge_param_set_vlan_rdcgrp(p_nxge_t, 94a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 9544961713Sgirish static int nxge_param_set_mac_rdcgrp(p_nxge_t, 96a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 9744961713Sgirish static int nxge_param_fflp_hash_init(p_nxge_t, 98a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 9944961713Sgirish static int nxge_param_llc_snap_enable(p_nxge_t, queue_t *, 100a3c5bd6dSspeer mblk_t *, char *, caddr_t); 10144961713Sgirish static int nxge_param_hash_lookup_enable(p_nxge_t, queue_t *, 102a3c5bd6dSspeer mblk_t *, char *, caddr_t); 10344961713Sgirish static int nxge_param_tcam_enable(p_nxge_t, queue_t *, 104a3c5bd6dSspeer mblk_t *, char *, caddr_t); 10556d930aeSspeer static int nxge_param_get_fw_ver(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 1062e59129aSraghus static int nxge_param_get_port_mode(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 10744961713Sgirish static int nxge_param_get_rxdma_info(p_nxge_t, queue_t *q, 108a3c5bd6dSspeer p_mblk_t, caddr_t); 10944961713Sgirish static int nxge_param_get_txdma_info(p_nxge_t, queue_t *q, 110a3c5bd6dSspeer p_mblk_t, caddr_t); 11144961713Sgirish static int nxge_param_get_vlan_rdcgrp(p_nxge_t, queue_t *, 112a3c5bd6dSspeer p_mblk_t, caddr_t); 11344961713Sgirish static int nxge_param_get_mac_rdcgrp(p_nxge_t, queue_t *, 114a3c5bd6dSspeer p_mblk_t, caddr_t); 11544961713Sgirish static int nxge_param_get_rxdma_rdcgrp_info(p_nxge_t, queue_t *, 116a3c5bd6dSspeer p_mblk_t, caddr_t); 117c1f9c6e5SSantwona Behera static int nxge_param_get_rx_intr_time(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 118c1f9c6e5SSantwona Behera static int nxge_param_get_rx_intr_pkts(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 11944961713Sgirish static int nxge_param_get_ip_opt(p_nxge_t, queue_t *, mblk_t *, caddr_t); 120a3c5bd6dSspeer static int nxge_param_get_mac(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 12144961713Sgirish static int nxge_param_get_debug_flag(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 12244961713Sgirish static int nxge_param_set_nxge_debug_flag(p_nxge_t, queue_t *, mblk_t *, 123a3c5bd6dSspeer char *, caddr_t); 12444961713Sgirish static int nxge_param_set_npi_debug_flag(p_nxge_t, 125a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 12644961713Sgirish static int nxge_param_dump_rdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 12744961713Sgirish static int nxge_param_dump_tdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 12844961713Sgirish static int nxge_param_dump_mac_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 12944961713Sgirish static int nxge_param_dump_ipp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 13044961713Sgirish static int nxge_param_dump_fflp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 13144961713Sgirish static int nxge_param_dump_vlan_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 13244961713Sgirish static int nxge_param_dump_rdc_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 13344961713Sgirish static int nxge_param_dump_ptrs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 1341bd6825cSml static void nxge_param_sync(p_nxge_t); 13544961713Sgirish 13644961713Sgirish /* 13744961713Sgirish * Global array of Neptune changable parameters. 13844961713Sgirish * This array is initialized to correspond to the default 13944961713Sgirish * Neptune 4 port configuration. This array would be copied 14044961713Sgirish * into each port's parameter structure and modifed per 14144961713Sgirish * fcode and nxge.conf configuration. Later, the parameters are 14244961713Sgirish * exported to ndd to display and run-time configuration (at least 14344961713Sgirish * some of them). 14444961713Sgirish * 14500161856Syc * Parameters with DONT_SHOW are not shown by ndd. 14600161856Syc * 14744961713Sgirish */ 14844961713Sgirish 149a3c5bd6dSspeer static nxge_param_t nxge_param_arr[] = { 150a3c5bd6dSspeer /* 151a3c5bd6dSspeer * min max value old hw-name conf-name 152a3c5bd6dSspeer */ 153846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 154a3c5bd6dSspeer 0, 999, 1000, 0, "instance", "instance"}, 155a3c5bd6dSspeer 156846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 157a3c5bd6dSspeer 0, 999, 1000, 0, "main-instance", "main_instance"}, 158a3c5bd6dSspeer 159a3c5bd6dSspeer { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 160a3c5bd6dSspeer 0, 3, 0, 0, "function-number", "function_number"}, 161a3c5bd6dSspeer 162a3c5bd6dSspeer /* Partition Id */ 163846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 164a3c5bd6dSspeer 0, 8, 0, 0, "partition-id", "partition_id"}, 165a3c5bd6dSspeer 166a3c5bd6dSspeer /* Read Write Permission Mode */ 167846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 168a3c5bd6dSspeer 0, 2, 0, 0, "read-write-mode", "read_write_mode"}, 169a3c5bd6dSspeer 17056d930aeSspeer { nxge_param_get_fw_ver, NULL, NXGE_PARAM_READ, 17156d930aeSspeer 0, 32, 0, 0, "version", "fw_version"}, 17256d930aeSspeer 1732e59129aSraghus { nxge_param_get_port_mode, NULL, NXGE_PARAM_READ, 1742e59129aSraghus 0, 32, 0, 0, "port-mode", "port_mode"}, 1752e59129aSraghus 176a3c5bd6dSspeer /* hw cfg types */ 177a3c5bd6dSspeer /* control the DMA config of Neptune/NIU */ 178846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 179a3c5bd6dSspeer CFG_DEFAULT, CFG_CUSTOM, CFG_DEFAULT, CFG_DEFAULT, 180a3c5bd6dSspeer "niu-cfg-type", "niu_cfg_type"}, 181a3c5bd6dSspeer 182a3c5bd6dSspeer /* control the TXDMA config of the Port controlled by tx-quick-cfg */ 183846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 184a3c5bd6dSspeer CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT, 185a3c5bd6dSspeer "tx-qcfg-type", "tx_qcfg_type"}, 186a3c5bd6dSspeer 187a3c5bd6dSspeer /* control the RXDMA config of the Port controlled by rx-quick-cfg */ 188846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 189a3c5bd6dSspeer CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT, 190a3c5bd6dSspeer "rx-qcfg-type", "rx_qcfg_type"}, 191a3c5bd6dSspeer 192a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, 193a3c5bd6dSspeer NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 194a3c5bd6dSspeer 0, 1, 0, 0, "master-cfg-enable", "master_cfg_enable"}, 195a3c5bd6dSspeer 196a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, 197846a903dSml NXGE_PARAM_DONT_SHOW, 198a3c5bd6dSspeer 0, 1, 0, 0, "master-cfg-value", "master_cfg_value"}, 199a3c5bd6dSspeer 200a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 201a3c5bd6dSspeer 0, 1, 1, 1, "adv-autoneg-cap", "adv_autoneg_cap"}, 202a3c5bd6dSspeer 203a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 204a3c5bd6dSspeer 0, 1, 1, 1, "adv-10gfdx-cap", "adv_10gfdx_cap"}, 205a3c5bd6dSspeer 206a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 207a3c5bd6dSspeer 0, 1, 0, 0, "adv-10ghdx-cap", "adv_10ghdx_cap"}, 208a3c5bd6dSspeer 209a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 210a3c5bd6dSspeer 0, 1, 1, 1, "adv-1000fdx-cap", "adv_1000fdx_cap"}, 211a3c5bd6dSspeer 212a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 213a3c5bd6dSspeer 0, 1, 0, 0, "adv-1000hdx-cap", "adv_1000hdx_cap"}, 214a3c5bd6dSspeer 215a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 216a3c5bd6dSspeer 0, 1, 0, 0, "adv-100T4-cap", "adv_100T4_cap"}, 217a3c5bd6dSspeer 218a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 219a3c5bd6dSspeer 0, 1, 1, 1, "adv-100fdx-cap", "adv_100fdx_cap"}, 220a3c5bd6dSspeer 221a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 222a3c5bd6dSspeer 0, 1, 0, 0, "adv-100hdx-cap", "adv_100hdx_cap"}, 223a3c5bd6dSspeer 224a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 225a3c5bd6dSspeer 0, 1, 1, 1, "adv-10fdx-cap", "adv_10fdx_cap"}, 226a3c5bd6dSspeer 227a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 228a3c5bd6dSspeer 0, 1, 0, 0, "adv-10hdx-cap", "adv_10hdx_cap"}, 229a3c5bd6dSspeer 230846a903dSml { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 231a3c5bd6dSspeer 0, 1, 0, 0, "adv-asmpause-cap", "adv_asmpause_cap"}, 232a3c5bd6dSspeer 233a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 234a3c5bd6dSspeer 0, 1, 0, 0, "adv-pause-cap", "adv_pause_cap"}, 235a3c5bd6dSspeer 236846a903dSml { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 237a3c5bd6dSspeer 0, 1, 0, 0, "use-int-xcvr", "use_int_xcvr"}, 238a3c5bd6dSspeer 239846a903dSml { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 240a3c5bd6dSspeer 0, 1, 1, 1, "enable-ipg0", "enable_ipg0"}, 241a3c5bd6dSspeer 242846a903dSml { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 243a3c5bd6dSspeer 0, 255, 8, 8, "ipg0", "ipg0"}, 244a3c5bd6dSspeer 245846a903dSml { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 246a3c5bd6dSspeer 0, 255, 8, 8, "ipg1", "ipg1"}, 247a3c5bd6dSspeer 248846a903dSml { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 249a3c5bd6dSspeer 0, 255, 4, 4, "ipg2", "ipg2"}, 250a3c5bd6dSspeer 251a3c5bd6dSspeer /* Transmit DMA channels */ 252846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 253846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 254a3c5bd6dSspeer 0, 3, 0, 0, "tx-dma-weight", "tx_dma_weight"}, 255a3c5bd6dSspeer 256846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 257846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 258a3c5bd6dSspeer 0, 31, 0, 0, "tx-dma-channels-begin", "tx_dma_channels_begin"}, 259a3c5bd6dSspeer 260846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 261846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 262a3c5bd6dSspeer 0, 32, 0, 0, "tx-dma-channels", "tx_dma_channels"}, 263a3c5bd6dSspeer { nxge_param_get_txdma_info, NULL, 264846a903dSml NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 265a3c5bd6dSspeer 0, 32, 0, 0, "tx-dma-info", "tx_dma_info"}, 266a3c5bd6dSspeer 267a3c5bd6dSspeer /* Receive DMA channels */ 268a3c5bd6dSspeer { nxge_param_get_generic, NULL, 269846a903dSml NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 270a3c5bd6dSspeer 0, 31, 0, 0, "rx-dma-channels-begin", "rx_dma_channels_begin"}, 271a3c5bd6dSspeer 272846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 273846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 274a3c5bd6dSspeer 0, 32, 0, 0, "rx-dma-channels", "rx_dma_channels"}, 275a3c5bd6dSspeer 276846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 277846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 278a3c5bd6dSspeer 0, 65535, PT_DRR_WT_DEFAULT_10G, 0, 279a3c5bd6dSspeer "rx-drr-weight", "rx_drr_weight"}, 280a3c5bd6dSspeer 281846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 282846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 283a3c5bd6dSspeer 0, 1, 1, 0, "rx-full-header", "rx_full_header"}, 284a3c5bd6dSspeer 285846a903dSml { nxge_param_get_rxdma_info, NULL, NXGE_PARAM_READ | 286846a903dSml NXGE_PARAM_DONT_SHOW, 287a3c5bd6dSspeer 0, 32, 0, 0, "rx-dma-info", "rx_dma_info"}, 288a3c5bd6dSspeer 289a3c5bd6dSspeer { nxge_param_get_rxdma_info, NULL, 290a3c5bd6dSspeer NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 291a3c5bd6dSspeer NXGE_RBR_RBB_MIN, NXGE_RBR_RBB_MAX, NXGE_RBR_RBB_DEFAULT, 0, 292a3c5bd6dSspeer "rx-rbr-size", "rx_rbr_size"}, 293a3c5bd6dSspeer 294a3c5bd6dSspeer { nxge_param_get_rxdma_info, NULL, 295a3c5bd6dSspeer NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 296a3c5bd6dSspeer NXGE_RCR_MIN, NXGE_RCR_MAX, NXGE_RCR_DEFAULT, 0, 297a3c5bd6dSspeer "rx-rcr-size", "rx_rcr_size"}, 298a3c5bd6dSspeer 299846a903dSml { nxge_param_get_generic, nxge_param_set_port_rdc, 300846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 301a3c5bd6dSspeer 0, 15, 0, 0, "default-port-rdc", "default_port_rdc"}, 302a3c5bd6dSspeer 303c1f9c6e5SSantwona Behera { nxge_param_get_rx_intr_time, nxge_param_rx_intr_time, 304c1f9c6e5SSantwona Behera NXGE_PARAM_RXDMA_RW, 305a3c5bd6dSspeer NXGE_RDC_RCR_TIMEOUT_MIN, NXGE_RDC_RCR_TIMEOUT_MAX, 3067b26d9ffSSantwona Behera NXGE_RDC_RCR_TIMEOUT, 0, "rxdma-intr-time", "rxdma_intr_time"}, 307a3c5bd6dSspeer 308c1f9c6e5SSantwona Behera { nxge_param_get_rx_intr_pkts, nxge_param_rx_intr_pkts, 309c1f9c6e5SSantwona Behera NXGE_PARAM_RXDMA_RW, 310a3c5bd6dSspeer NXGE_RDC_RCR_THRESHOLD_MIN, NXGE_RDC_RCR_THRESHOLD_MAX, 3117b26d9ffSSantwona Behera NXGE_RDC_RCR_THRESHOLD, 0, 312a3c5bd6dSspeer "rxdma-intr-pkts", "rxdma_intr_pkts"}, 313a3c5bd6dSspeer 314846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP | 315846a903dSml NXGE_PARAM_DONT_SHOW, 316a3c5bd6dSspeer 0, 8, 0, 0, "rx-rdc-grps-begin", "rx_rdc_grps_begin"}, 317a3c5bd6dSspeer 318846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP | 319846a903dSml NXGE_PARAM_DONT_SHOW, 320a3c5bd6dSspeer 0, 8, 0, 0, "rx-rdc-grps", "rx_rdc_grps"}, 321a3c5bd6dSspeer 322846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 323846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 324a3c5bd6dSspeer 0, 15, 0, 0, "default-grp0-rdc", "default_grp0_rdc"}, 325a3c5bd6dSspeer 326846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 327846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 328a3c5bd6dSspeer 0, 15, 2, 0, "default-grp1-rdc", "default_grp1_rdc"}, 329a3c5bd6dSspeer 330846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 331846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 332a3c5bd6dSspeer 0, 15, 4, 0, "default-grp2-rdc", "default_grp2_rdc"}, 333a3c5bd6dSspeer 334846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 335846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 336a3c5bd6dSspeer 0, 15, 6, 0, "default-grp3-rdc", "default_grp3_rdc"}, 337a3c5bd6dSspeer 338846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 339846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 340a3c5bd6dSspeer 0, 15, 8, 0, "default-grp4-rdc", "default_grp4_rdc"}, 341a3c5bd6dSspeer 342846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 343846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 344a3c5bd6dSspeer 0, 15, 10, 0, "default-grp5-rdc", "default_grp5_rdc"}, 345a3c5bd6dSspeer 346846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 347846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 348a3c5bd6dSspeer 0, 15, 12, 0, "default-grp6-rdc", "default_grp6_rdc"}, 349a3c5bd6dSspeer 350846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 351846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 352a3c5bd6dSspeer 0, 15, 14, 0, "default-grp7-rdc", "default_grp7_rdc"}, 353a3c5bd6dSspeer 354a3c5bd6dSspeer { nxge_param_get_rxdma_rdcgrp_info, NULL, 355846a903dSml NXGE_PARAM_READ | NXGE_PARAM_CMPLX | NXGE_PARAM_DONT_SHOW, 356a3c5bd6dSspeer 0, 8, 0, 0, "rdc-groups-info", "rdc_groups_info"}, 357a3c5bd6dSspeer 358a3c5bd6dSspeer /* Logical device groups */ 359846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 360a3c5bd6dSspeer 0, 63, 0, 0, "start-ldg", "start_ldg"}, 361a3c5bd6dSspeer 362846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 363a3c5bd6dSspeer 0, 64, 0, 0, "max-ldg", "max_ldg" }, 364a3c5bd6dSspeer 365a3c5bd6dSspeer /* MAC table information */ 366a3c5bd6dSspeer { nxge_param_get_mac_rdcgrp, nxge_param_set_mac_rdcgrp, 367846a903dSml NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW, 368a3c5bd6dSspeer 0, 31, 0, 0, "mac-2rdc-grp", "mac_2rdc_grp"}, 369a3c5bd6dSspeer 370a3c5bd6dSspeer /* VLAN table information */ 371a3c5bd6dSspeer { nxge_param_get_vlan_rdcgrp, nxge_param_set_vlan_rdcgrp, 372846a903dSml NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW, 373a3c5bd6dSspeer 0, 31, 0, 0, "vlan-2rdc-grp", "vlan_2rdc_grp"}, 374a3c5bd6dSspeer 375a3c5bd6dSspeer { nxge_param_get_generic, NULL, 376846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_READ | 377846a903dSml NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_DONT_SHOW, 378a3c5bd6dSspeer 0, 0x0ffff, 0x0ffff, 0, "fcram-part-cfg", "fcram_part_cfg"}, 379a3c5bd6dSspeer 380846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS | 381846a903dSml NXGE_PARAM_DONT_SHOW, 382a3c5bd6dSspeer 0, 0x10, 0xa, 0, "fcram-access-ratio", "fcram_access_ratio"}, 383a3c5bd6dSspeer 384846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS | 385846a903dSml NXGE_PARAM_DONT_SHOW, 386a3c5bd6dSspeer 0, 0x10, 0xa, 0, "tcam-access-ratio", "tcam_access_ratio"}, 387a3c5bd6dSspeer 388a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_tcam_enable, 389846a903dSml NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 390a3c5bd6dSspeer 0, 0x1, 0x0, 0, "tcam-enable", "tcam_enable"}, 391a3c5bd6dSspeer 392a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_hash_lookup_enable, 393846a903dSml NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 394a3c5bd6dSspeer 0, 0x01, 0x0, 0, "hash-lookup-enable", "hash_lookup_enable"}, 395a3c5bd6dSspeer 396a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_llc_snap_enable, 397846a903dSml NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 398a3c5bd6dSspeer 0, 0x01, 0x01, 0, "llc-snap-enable", "llc_snap_enable"}, 399a3c5bd6dSspeer 400a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_fflp_hash_init, 401846a903dSml NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 402a3c5bd6dSspeer 0, ALL_FF_32, ALL_FF_32, 0, "h1-init-value", "h1_init_value"}, 403a3c5bd6dSspeer 404a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_fflp_hash_init, 405846a903dSml NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 406a3c5bd6dSspeer 0, 0x0ffff, 0x0ffff, 0, "h2-init-value", "h2_init_value"}, 407a3c5bd6dSspeer 408a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ether_usr, 409a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 410a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 411a3c5bd6dSspeer "class-cfg-ether-usr1", "class_cfg_ether_usr1"}, 412a3c5bd6dSspeer 413a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ether_usr, 414a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 415a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 416a3c5bd6dSspeer "class-cfg-ether-usr2", "class_cfg_ether_usr2"}, 417a3c5bd6dSspeer 418a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ip_usr, 419a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 420a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 421a3c5bd6dSspeer "class-cfg-ip-usr4", "class_cfg_ip_usr4"}, 422a3c5bd6dSspeer 423a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ip_usr, 424a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 425a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 426a3c5bd6dSspeer "class-cfg-ip-usr5", "class_cfg_ip_usr5"}, 427a3c5bd6dSspeer 428a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ip_usr, 429a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 430a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 431a3c5bd6dSspeer "class-cfg-ip-usr6", "class_cfg_ip_usr6"}, 432a3c5bd6dSspeer 433a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ip_usr, 434a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 435a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 436a3c5bd6dSspeer "class-cfg-ip-usr7", "class_cfg_ip_usr7"}, 437a3c5bd6dSspeer 438a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 439a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 440a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 441a3c5bd6dSspeer "class-opt-ip-usr4", "class_opt_ip_usr4"}, 442a3c5bd6dSspeer 443a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 444a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 445a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 446a3c5bd6dSspeer "class-opt-ip-usr5", "class_opt_ip_usr5"}, 447a3c5bd6dSspeer 448a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 449a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 450a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 451a3c5bd6dSspeer "class-opt-ip-usr6", "class_opt_ip_usr6"}, 452a3c5bd6dSspeer 453a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 454a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 455a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 456a3c5bd6dSspeer "class-opt-ip-usr7", "class_opt_ip_usr7"}, 457a3c5bd6dSspeer 458a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 459a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS, 460a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 461a3c5bd6dSspeer "class-opt-ipv4-tcp", "class_opt_ipv4_tcp"}, 462a3c5bd6dSspeer 463a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 464a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS, 465a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 466a3c5bd6dSspeer "class-opt-ipv4-udp", "class_opt_ipv4_udp"}, 467a3c5bd6dSspeer 468a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 469a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS, 470a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 471a3c5bd6dSspeer "class-opt-ipv4-ah", "class_opt_ipv4_ah"}, 472a3c5bd6dSspeer 473a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 474a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS, 475a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 476a3c5bd6dSspeer "class-opt-ipv4-sctp", "class_opt_ipv4_sctp"}, 477a3c5bd6dSspeer 478a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 479a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 480a3c5bd6dSspeer "class-opt-ipv6-tcp", "class_opt_ipv6_tcp"}, 481a3c5bd6dSspeer 482a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 483a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 484a3c5bd6dSspeer "class-opt-ipv6-udp", "class_opt_ipv6_udp"}, 485a3c5bd6dSspeer 486a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 487a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 488a3c5bd6dSspeer "class-opt-ipv6-ah", "class_opt_ipv6_ah"}, 489a3c5bd6dSspeer 490a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 491a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 492a3c5bd6dSspeer "class-opt-ipv6-sctp", "class_opt_ipv6_sctp"}, 493a3c5bd6dSspeer 494a3c5bd6dSspeer { nxge_param_get_debug_flag, nxge_param_set_nxge_debug_flag, 495846a903dSml NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 496a3c5bd6dSspeer 0ULL, ALL_FF_64, 0ULL, 0ULL, 497a3c5bd6dSspeer "nxge-debug-flag", "nxge_debug_flag"}, 498a3c5bd6dSspeer 499a3c5bd6dSspeer { nxge_param_get_debug_flag, nxge_param_set_npi_debug_flag, 500846a903dSml NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 501a3c5bd6dSspeer 0ULL, ALL_FF_64, 0ULL, 0ULL, 502a3c5bd6dSspeer "npi-debug-flag", "npi_debug_flag"}, 503a3c5bd6dSspeer 504846a903dSml { nxge_param_dump_tdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 505a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "dump-tdc", "dump_tdc"}, 506a3c5bd6dSspeer 507846a903dSml { nxge_param_dump_rdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 508a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "dump-rdc", "dump_rdc"}, 509a3c5bd6dSspeer 510846a903dSml { nxge_param_dump_mac_regs, NULL, NXGE_PARAM_READ | 511846a903dSml NXGE_PARAM_DONT_SHOW, 512a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "dump-mac-regs", "dump_mac_regs"}, 513a3c5bd6dSspeer 514846a903dSml { nxge_param_dump_ipp_regs, NULL, NXGE_PARAM_READ | 515846a903dSml NXGE_PARAM_DONT_SHOW, 516a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "dump-ipp-regs", "dump_ipp_regs"}, 517a3c5bd6dSspeer 518846a903dSml { nxge_param_dump_fflp_regs, NULL, NXGE_PARAM_READ | 519846a903dSml NXGE_PARAM_DONT_SHOW, 520a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, 521a3c5bd6dSspeer "dump-fflp-regs", "dump_fflp_regs"}, 522a3c5bd6dSspeer 523846a903dSml { nxge_param_dump_vlan_table, NULL, NXGE_PARAM_READ | 524846a903dSml NXGE_PARAM_DONT_SHOW, 525a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, 526a3c5bd6dSspeer "dump-vlan-table", "dump_vlan_table"}, 527a3c5bd6dSspeer 528846a903dSml { nxge_param_dump_rdc_table, NULL, NXGE_PARAM_READ | 529846a903dSml NXGE_PARAM_DONT_SHOW, 530a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, 531a3c5bd6dSspeer "dump-rdc-table", "dump_rdc_table"}, 532a3c5bd6dSspeer 533846a903dSml { nxge_param_dump_ptrs, NULL, NXGE_PARAM_READ | 534846a903dSml NXGE_PARAM_DONT_SHOW, 535a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "dump-ptrs", "dump_ptrs"}, 536a3c5bd6dSspeer 537a3c5bd6dSspeer { NULL, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 538a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "end", "end"}, 53944961713Sgirish }; 54044961713Sgirish 54144961713Sgirish extern void *nxge_list; 54244961713Sgirish 54344961713Sgirish void 54444961713Sgirish nxge_get_param_soft_properties(p_nxge_t nxgep) 54544961713Sgirish { 54644961713Sgirish 54744961713Sgirish p_nxge_param_t param_arr; 54844961713Sgirish uint_t prop_len; 54944961713Sgirish int i, j; 550a3c5bd6dSspeer uint32_t param_count; 551a3c5bd6dSspeer uint32_t *int_prop_val; 55244961713Sgirish 55344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, " ==> nxge_get_param_soft_properties")); 55444961713Sgirish 55544961713Sgirish param_arr = nxgep->param_arr; 55644961713Sgirish param_count = nxgep->param_count; 55744961713Sgirish for (i = 0; i < param_count; i++) { 55844961713Sgirish if ((param_arr[i].type & NXGE_PARAM_READ_PROP) == 0) 55944961713Sgirish continue; 56044961713Sgirish if ((param_arr[i].type & NXGE_PARAM_PROP_STR)) 56144961713Sgirish continue; 56244961713Sgirish if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 5634045d941Ssowmini (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 56444961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, 5654045d941Ssowmini nxgep->dip, 0, param_arr[i].fcode_name, 5664045d941Ssowmini (int **)&int_prop_val, 5674045d941Ssowmini (uint_t *)&prop_len) 5684045d941Ssowmini == DDI_PROP_SUCCESS) { 56944961713Sgirish uint32_t *cfg_value; 57044961713Sgirish uint64_t prop_count; 571a3c5bd6dSspeer 57244961713Sgirish if (prop_len > NXGE_PARAM_ARRAY_INIT_SIZE) 57344961713Sgirish prop_len = NXGE_PARAM_ARRAY_INIT_SIZE; 574adfcba55Sjoycey #if defined(__i386) 575adfcba55Sjoycey cfg_value = 5764045d941Ssowmini (uint32_t *)(int32_t)param_arr[i].value; 577adfcba55Sjoycey #else 57844961713Sgirish cfg_value = (uint32_t *)param_arr[i].value; 579adfcba55Sjoycey #endif 58044961713Sgirish for (j = 0; j < prop_len; j++) { 58144961713Sgirish cfg_value[j] = int_prop_val[j]; 58244961713Sgirish } 58344961713Sgirish prop_count = prop_len; 58444961713Sgirish param_arr[i].type |= 58544961713Sgirish (prop_count << NXGE_PARAM_ARRAY_CNT_SHIFT); 58644961713Sgirish ddi_prop_free(int_prop_val); 58744961713Sgirish } 58844961713Sgirish continue; 58944961713Sgirish } 59044961713Sgirish 59144961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 5924045d941Ssowmini param_arr[i].fcode_name, 5934045d941Ssowmini (int **)&int_prop_val, 5944045d941Ssowmini &prop_len) == DDI_PROP_SUCCESS) { 59544961713Sgirish if ((*int_prop_val >= param_arr[i].minimum) && 5964045d941Ssowmini (*int_prop_val <= param_arr[i].maximum)) 59744961713Sgirish param_arr[i].value = *int_prop_val; 59844961713Sgirish #ifdef NXGE_DEBUG_ERROR 59944961713Sgirish else { 60044961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL, 6014045d941Ssowmini "nxge%d: 'prom' file parameter error\n", 6024045d941Ssowmini nxgep->instance)); 60344961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL, 6044045d941Ssowmini "Parameter keyword '%s'" 6054045d941Ssowmini " is outside valid range\n", 6064045d941Ssowmini param_arr[i].name)); 60744961713Sgirish } 60844961713Sgirish #endif 60944961713Sgirish ddi_prop_free(int_prop_val); 61044961713Sgirish } 61144961713Sgirish 61244961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 6134045d941Ssowmini param_arr[i].name, 6144045d941Ssowmini (int **)&int_prop_val, 6154045d941Ssowmini &prop_len) == DDI_PROP_SUCCESS) { 61644961713Sgirish if ((*int_prop_val >= param_arr[i].minimum) && 6174045d941Ssowmini (*int_prop_val <= param_arr[i].maximum)) 61844961713Sgirish param_arr[i].value = *int_prop_val; 61944961713Sgirish #ifdef NXGE_DEBUG_ERROR 62044961713Sgirish else { 62144961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL, 6224045d941Ssowmini "nxge%d: 'conf' file parameter error\n", 6234045d941Ssowmini nxgep->instance)); 62444961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL, 6254045d941Ssowmini "Parameter keyword '%s'" 6264045d941Ssowmini "is outside valid range\n", 6274045d941Ssowmini param_arr[i].name)); 62844961713Sgirish } 62944961713Sgirish #endif 63044961713Sgirish ddi_prop_free(int_prop_val); 63144961713Sgirish } 63244961713Sgirish } 63344961713Sgirish } 63444961713Sgirish 63544961713Sgirish static int 63644961713Sgirish nxge_private_param_register(p_nxge_t nxgep, p_nxge_param_t param_arr) 63744961713Sgirish { 63844961713Sgirish int status = B_TRUE; 63944961713Sgirish int channel; 64044961713Sgirish uint8_t grp; 64144961713Sgirish char *prop_name; 64244961713Sgirish char *end; 64344961713Sgirish uint32_t name_chars; 64444961713Sgirish 64544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 6464045d941Ssowmini "nxge_private_param_register %s", param_arr->name)); 64744961713Sgirish 64844961713Sgirish if ((param_arr->type & NXGE_PARAM_PRIV) != NXGE_PARAM_PRIV) 64944961713Sgirish return (B_TRUE); 650a3c5bd6dSspeer 65144961713Sgirish prop_name = param_arr->name; 65244961713Sgirish if (param_arr->type & NXGE_PARAM_RXDMA) { 65344961713Sgirish if (strncmp("rxdma_intr", prop_name, 10) == 0) 65444961713Sgirish return (B_TRUE); 65544961713Sgirish name_chars = strlen("default_grp"); 65644961713Sgirish if (strncmp("default_grp", prop_name, name_chars) == 0) { 65744961713Sgirish prop_name += name_chars; 65844961713Sgirish grp = mi_strtol(prop_name, &end, 10); 65944961713Sgirish /* now check if this rdcgrp is in config */ 66044961713Sgirish return (nxge_check_rdcgrp_port_member(nxgep, grp)); 66144961713Sgirish } 66244961713Sgirish name_chars = strlen(prop_name); 66344961713Sgirish if (strncmp("default_port_rdc", prop_name, name_chars) == 0) { 66444961713Sgirish return (B_TRUE); 66544961713Sgirish } 66644961713Sgirish return (B_FALSE); 66744961713Sgirish } 66844961713Sgirish 66944961713Sgirish if (param_arr->type & NXGE_PARAM_TXDMA) { 67044961713Sgirish name_chars = strlen("txdma"); 67144961713Sgirish if (strncmp("txdma", prop_name, name_chars) == 0) { 67244961713Sgirish prop_name += name_chars; 67344961713Sgirish channel = mi_strtol(prop_name, &end, 10); 67444961713Sgirish /* now check if this rdc is in config */ 67544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 6764045d941Ssowmini " nxge_private_param_register: %d", 6774045d941Ssowmini channel)); 67844961713Sgirish return (nxge_check_txdma_port_member(nxgep, channel)); 67944961713Sgirish } 68044961713Sgirish return (B_FALSE); 68144961713Sgirish } 68244961713Sgirish 68344961713Sgirish status = B_FALSE; 68444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD2_CTL, "<== nxge_private_param_register")); 68544961713Sgirish 68644961713Sgirish return (status); 68744961713Sgirish } 68844961713Sgirish 68944961713Sgirish void 69044961713Sgirish nxge_setup_param(p_nxge_t nxgep) 69144961713Sgirish { 69244961713Sgirish p_nxge_param_t param_arr; 69344961713Sgirish int i; 69444961713Sgirish pfi_t set_pfi; 69544961713Sgirish 69644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_setup_param")); 697a3c5bd6dSspeer 69844961713Sgirish /* 69944961713Sgirish * Make sure the param_instance is set to a valid device instance. 70044961713Sgirish */ 70144961713Sgirish if (nxge_param_arr[param_instance].value == 1000) 70244961713Sgirish nxge_param_arr[param_instance].value = nxgep->instance; 70344961713Sgirish 70444961713Sgirish param_arr = nxgep->param_arr; 70544961713Sgirish param_arr[param_instance].value = nxgep->instance; 70644961713Sgirish param_arr[param_function_number].value = nxgep->function_num; 70744961713Sgirish 70844961713Sgirish for (i = 0; i < nxgep->param_count; i++) { 70944961713Sgirish if ((param_arr[i].type & NXGE_PARAM_PRIV) && 7104045d941Ssowmini (nxge_private_param_register(nxgep, 7114045d941Ssowmini ¶m_arr[i]) == B_FALSE)) { 71244961713Sgirish param_arr[i].setf = NULL; 71344961713Sgirish param_arr[i].getf = NULL; 71444961713Sgirish } 71544961713Sgirish 71644961713Sgirish if (param_arr[i].type & NXGE_PARAM_CMPLX) 71744961713Sgirish param_arr[i].setf = NULL; 71844961713Sgirish 71944961713Sgirish if (param_arr[i].type & NXGE_PARAM_DONT_SHOW) { 72044961713Sgirish param_arr[i].setf = NULL; 72144961713Sgirish param_arr[i].getf = NULL; 72244961713Sgirish } 72344961713Sgirish 72444961713Sgirish set_pfi = (pfi_t)param_arr[i].setf; 72544961713Sgirish 726a3c5bd6dSspeer if ((set_pfi) && (param_arr[i].type & NXGE_PARAM_INIT_ONLY)) { 72744961713Sgirish set_pfi = NULL; 72844961713Sgirish } 72944961713Sgirish 73044961713Sgirish } 73144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_setup_param")); 73244961713Sgirish } 73344961713Sgirish 73444961713Sgirish void 73544961713Sgirish nxge_init_param(p_nxge_t nxgep) 73644961713Sgirish { 73744961713Sgirish p_nxge_param_t param_arr; 73844961713Sgirish int i, alloc_size; 73944961713Sgirish uint64_t alloc_count; 74044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_init_param")); 74144961713Sgirish /* 74244961713Sgirish * Make sure the param_instance is set to a valid device instance. 74344961713Sgirish */ 74444961713Sgirish if (nxge_param_arr[param_instance].value == 1000) 74544961713Sgirish nxge_param_arr[param_instance].value = nxgep->instance; 74644961713Sgirish 74744961713Sgirish param_arr = nxgep->param_arr; 74844961713Sgirish if (param_arr == NULL) { 749a3c5bd6dSspeer param_arr = (p_nxge_param_t) 7504045d941Ssowmini KMEM_ZALLOC(sizeof (nxge_param_arr), KM_SLEEP); 75144961713Sgirish } 752a3c5bd6dSspeer 75344961713Sgirish for (i = 0; i < sizeof (nxge_param_arr)/sizeof (nxge_param_t); i++) { 75444961713Sgirish param_arr[i] = nxge_param_arr[i]; 75544961713Sgirish if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 7564045d941Ssowmini (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 75744961713Sgirish alloc_count = NXGE_PARAM_ARRAY_INIT_SIZE; 75844961713Sgirish alloc_size = alloc_count * sizeof (uint64_t); 75944961713Sgirish param_arr[i].value = 760adfcba55Sjoycey #if defined(__i386) 7614045d941Ssowmini (uint64_t)(uint32_t)KMEM_ZALLOC(alloc_size, 7624045d941Ssowmini KM_SLEEP); 763adfcba55Sjoycey #else 7641bd6825cSml (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP); 765adfcba55Sjoycey #endif 76644961713Sgirish param_arr[i].old_value = 767adfcba55Sjoycey #if defined(__i386) 7684045d941Ssowmini (uint64_t)(uint32_t)KMEM_ZALLOC(alloc_size, 7694045d941Ssowmini KM_SLEEP); 770adfcba55Sjoycey #else 7714045d941Ssowmini (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP); 772adfcba55Sjoycey #endif 77344961713Sgirish param_arr[i].type |= 7744045d941Ssowmini (alloc_count << NXGE_PARAM_ARRAY_ALLOC_SHIFT); 77544961713Sgirish } 77644961713Sgirish } 77744961713Sgirish 77844961713Sgirish nxgep->param_arr = param_arr; 77944961713Sgirish nxgep->param_count = sizeof (nxge_param_arr)/sizeof (nxge_param_t); 7801bd6825cSml 7811bd6825cSml nxge_param_sync(nxgep); 7821bd6825cSml 78344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_init_param: count %d", 7844045d941Ssowmini nxgep->param_count)); 78544961713Sgirish } 78644961713Sgirish 78744961713Sgirish void 78844961713Sgirish nxge_destroy_param(p_nxge_t nxgep) 78944961713Sgirish { 79044961713Sgirish int i; 79144961713Sgirish uint64_t free_size, free_count; 79244961713Sgirish 79344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_param")); 794a3c5bd6dSspeer 79559ac0c16Sdavemq if (nxgep->param_arr == NULL) 79659ac0c16Sdavemq return; 79744961713Sgirish /* 79844961713Sgirish * Make sure the param_instance is set to a valid device instance. 79944961713Sgirish */ 80044961713Sgirish if (nxge_param_arr[param_instance].value == nxgep->instance) { 80144961713Sgirish for (i = 0; i <= nxge_param_arr[param_instance].maximum; i++) { 80244961713Sgirish if ((ddi_get_soft_state(nxge_list, i) != NULL) && 8034045d941Ssowmini (i != nxgep->instance)) 80444961713Sgirish break; 80544961713Sgirish } 80644961713Sgirish nxge_param_arr[param_instance].value = i; 80744961713Sgirish } 80844961713Sgirish 80944961713Sgirish for (i = 0; i < nxgep->param_count; i++) 81044961713Sgirish if ((nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 8114045d941Ssowmini (nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 81244961713Sgirish free_count = ((nxgep->param_arr[i].type & 8134045d941Ssowmini NXGE_PARAM_ARRAY_ALLOC_MASK) >> 8144045d941Ssowmini NXGE_PARAM_ARRAY_ALLOC_SHIFT); 81544961713Sgirish free_count = NXGE_PARAM_ARRAY_INIT_SIZE; 81644961713Sgirish free_size = sizeof (uint64_t) * free_count; 817adfcba55Sjoycey #if defined(__i386) 818adfcba55Sjoycey KMEM_FREE((void *)(uint32_t)nxgep->param_arr[i].value, 8194045d941Ssowmini free_size); 820adfcba55Sjoycey #else 82144961713Sgirish KMEM_FREE((void *)nxgep->param_arr[i].value, free_size); 822adfcba55Sjoycey #endif 823adfcba55Sjoycey #if defined(__i386) 824adfcba55Sjoycey KMEM_FREE((void *)(uint32_t) 8254045d941Ssowmini nxgep->param_arr[i].old_value, free_size); 826adfcba55Sjoycey #else 82744961713Sgirish KMEM_FREE((void *)nxgep->param_arr[i].old_value, 8284045d941Ssowmini free_size); 829adfcba55Sjoycey #endif 83044961713Sgirish } 83144961713Sgirish 83244961713Sgirish KMEM_FREE(nxgep->param_arr, sizeof (nxge_param_arr)); 83344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_param")); 83444961713Sgirish } 83544961713Sgirish 83644961713Sgirish /* 83744961713Sgirish * Extracts the value from the 'nxge' parameter array and prints the 83844961713Sgirish * parameter value. cp points to the required parameter. 83944961713Sgirish */ 840a3c5bd6dSspeer 84144961713Sgirish /* ARGSUSED */ 84244961713Sgirish int 84344961713Sgirish nxge_param_get_generic(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 84444961713Sgirish { 84544961713Sgirish p_nxge_param_t pa = (p_nxge_param_t)cp; 84644961713Sgirish 847a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, NDD_CTL, 8484045d941Ssowmini "==> nxge_param_get_generic name %s ", pa->name)); 84944961713Sgirish 85044961713Sgirish if (pa->value > 0xffffffff) 851a3c5bd6dSspeer (void) mi_mpprintf(mp, "%x%x", 8524045d941Ssowmini (int)(pa->value >> 32), (int)(pa->value & 0xffffffff)); 85344961713Sgirish else 85444961713Sgirish (void) mi_mpprintf(mp, "%x", (int)pa->value); 85544961713Sgirish 85644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_generic")); 85744961713Sgirish return (0); 85844961713Sgirish } 85944961713Sgirish 86044961713Sgirish /* ARGSUSED */ 86144961713Sgirish static int 86244961713Sgirish nxge_param_get_mac(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 86344961713Sgirish { 86444961713Sgirish p_nxge_param_t pa = (p_nxge_param_t)cp; 86544961713Sgirish 86644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac")); 86744961713Sgirish 86844961713Sgirish (void) mi_mpprintf(mp, "%d", (uint32_t)pa->value); 86944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_mac")); 87044961713Sgirish return (0); 87144961713Sgirish } 87244961713Sgirish 87356d930aeSspeer /* ARGSUSED */ 87456d930aeSspeer static int 87556d930aeSspeer nxge_param_get_fw_ver(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 87656d930aeSspeer { 87756d930aeSspeer NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_fw_ver")); 87856d930aeSspeer 87956d930aeSspeer (void) mi_mpprintf(mp, "Firmware version for nxge%d: %s\n", 88056d930aeSspeer nxgep->instance, nxgep->vpd_info.ver); 88156d930aeSspeer 88256d930aeSspeer NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_fw_ver")); 88356d930aeSspeer return (0); 88456d930aeSspeer } 88556d930aeSspeer 8862e59129aSraghus /* ARGSUSED */ 8872e59129aSraghus static int 8882e59129aSraghus nxge_param_get_port_mode(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 8892e59129aSraghus { 8902e59129aSraghus NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_port_mode")); 8912e59129aSraghus 8922e59129aSraghus switch (nxgep->mac.portmode) { 8932e59129aSraghus case PORT_1G_COPPER: 8942d17280bSsbehera (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Copper %s\n", 8952d17280bSsbehera nxgep->instance, 8962d17280bSsbehera nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 8972e59129aSraghus break; 8982e59129aSraghus case PORT_1G_FIBER: 8992d17280bSsbehera (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Fiber %s\n", 9002d17280bSsbehera nxgep->instance, 9012d17280bSsbehera nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 9022e59129aSraghus break; 9032e59129aSraghus case PORT_10G_COPPER: 9042d17280bSsbehera (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Copper " 9052d17280bSsbehera "%s\n", nxgep->instance, 9062d17280bSsbehera nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 9072e59129aSraghus break; 9082e59129aSraghus case PORT_10G_FIBER: 9092d17280bSsbehera (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Fiber %s\n", 9102d17280bSsbehera nxgep->instance, 9112d17280bSsbehera nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 9122e59129aSraghus break; 9132e59129aSraghus case PORT_10G_SERDES: 9142d17280bSsbehera (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Serdes " 9152d17280bSsbehera "%s\n", nxgep->instance, 9162d17280bSsbehera nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 9172e59129aSraghus break; 9182e59129aSraghus case PORT_1G_SERDES: 9192d17280bSsbehera (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Serdes %s\n", 9202d17280bSsbehera nxgep->instance, 9212d17280bSsbehera nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 9222e59129aSraghus break; 9232e59129aSraghus case PORT_1G_RGMII_FIBER: 9242e59129aSraghus (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G RGMII " 9252d17280bSsbehera "Fiber %s\n", nxgep->instance, 9262d17280bSsbehera nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 9272d17280bSsbehera break; 9282d17280bSsbehera case PORT_HSP_MODE: 9292d17280bSsbehera (void) mi_mpprintf(mp, "Port mode for nxge%d: Hot Swappable " 9302d17280bSsbehera "PHY, Currently NOT present\n", nxgep->instance); 9312e59129aSraghus break; 93200161856Syc case PORT_10G_TN1010: 93300161856Syc (void) mi_mpprintf(mp, "Port mode for nxge%d:" 93400161856Syc " 10G Copper with TN1010 %s\n", nxgep->instance, 93500161856Syc nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 93600161856Syc break; 93700161856Syc case PORT_1G_TN1010: 938c6e5ef56Syc (void) mi_mpprintf(mp, "Port mode for nxge%d:" 93900161856Syc " 1G Copper with TN1010 %s\n", nxgep->instance, 94000161856Syc nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 94100161856Syc break; 9422e59129aSraghus default: 9432d17280bSsbehera (void) mi_mpprintf(mp, "Port mode for nxge%d: Unknown %s\n", 9442d17280bSsbehera nxgep->instance, 9452d17280bSsbehera nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 9462e59129aSraghus break; 9472e59129aSraghus } 9482e59129aSraghus 9493d16f8e7Sml (void) mi_mpprintf(mp, "Software LSO for nxge%d: %s\n", 9503d16f8e7Sml nxgep->instance, 9513d16f8e7Sml nxgep->soft_lso_enable ? "enable" : "disable"); 9523d16f8e7Sml 9532e59129aSraghus NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_port_mode")); 9542e59129aSraghus return (0); 9552e59129aSraghus } 9562e59129aSraghus 957c1f9c6e5SSantwona Behera /* ARGSUSED */ 958c1f9c6e5SSantwona Behera static int 959c1f9c6e5SSantwona Behera nxge_param_get_rx_intr_time(p_nxge_t nxgep, queue_t *q, mblk_t *mp, caddr_t cp) 960c1f9c6e5SSantwona Behera { 961c1f9c6e5SSantwona Behera p_nxge_param_t pa = (p_nxge_param_t)cp; 962c1f9c6e5SSantwona Behera 963c1f9c6e5SSantwona Behera NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rx_intr_time")); 964c1f9c6e5SSantwona Behera 965c1f9c6e5SSantwona Behera pa->value = (uint32_t)nxgep->intr_timeout; 966c1f9c6e5SSantwona Behera (void) mi_mpprintf(mp, "%d", (uint32_t)nxgep->intr_timeout); 967c1f9c6e5SSantwona Behera 968c1f9c6e5SSantwona Behera NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rx_intr_time")); 969c1f9c6e5SSantwona Behera return (0); 970c1f9c6e5SSantwona Behera } 971c1f9c6e5SSantwona Behera 972c1f9c6e5SSantwona Behera /* ARGSUSED */ 973c1f9c6e5SSantwona Behera static int 974c1f9c6e5SSantwona Behera nxge_param_get_rx_intr_pkts(p_nxge_t nxgep, queue_t *q, mblk_t *mp, caddr_t cp) 975c1f9c6e5SSantwona Behera { 976c1f9c6e5SSantwona Behera p_nxge_param_t pa = (p_nxge_param_t)cp; 977c1f9c6e5SSantwona Behera 978c1f9c6e5SSantwona Behera NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rx_intr_pkts")); 979c1f9c6e5SSantwona Behera 980c1f9c6e5SSantwona Behera pa->value = (uint32_t)nxgep->intr_threshold; 981c1f9c6e5SSantwona Behera (void) mi_mpprintf(mp, "%d", (uint32_t)nxgep->intr_threshold); 982c1f9c6e5SSantwona Behera 983c1f9c6e5SSantwona Behera NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rx_intr_pkts")); 984c1f9c6e5SSantwona Behera return (0); 985c1f9c6e5SSantwona Behera } 986c1f9c6e5SSantwona Behera 98744961713Sgirish /* ARGSUSED */ 98844961713Sgirish int 98944961713Sgirish nxge_param_get_txdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 99044961713Sgirish { 99144961713Sgirish 992678453a8Sspeer uint_t print_len, buf_len; 99344961713Sgirish p_mblk_t np; 99444961713Sgirish 99544961713Sgirish int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 996678453a8Sspeer int tdc; 997678453a8Sspeer 998678453a8Sspeer nxge_grp_set_t *set; 999678453a8Sspeer 100044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_txdma_info")); 100144961713Sgirish 1002a3c5bd6dSspeer (void) mi_mpprintf(mp, "TXDMA Information for Port\t %d \n", 10034045d941Ssowmini nxgep->function_num); 100444961713Sgirish 100544961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 100644961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 100744961713Sgirish return (0); 100844961713Sgirish } 100944961713Sgirish 101044961713Sgirish buf_len = buff_alloc_size; 101144961713Sgirish mp->b_cont = np; 1012678453a8Sspeer print_len = 0; 101344961713Sgirish 101444961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 10154045d941Ssowmini "TDC\t HW TDC\t\n"); 101644961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 101744961713Sgirish buf_len -= print_len; 1018678453a8Sspeer 1019678453a8Sspeer set = &nxgep->tx_set; 1020da14cebeSEric Cheng for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) { 1021678453a8Sspeer if ((1 << tdc) & set->owned.map) { 1022678453a8Sspeer print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1023678453a8Sspeer buf_len, "%d\n", tdc); 1024678453a8Sspeer ((mblk_t *)np)->b_wptr += print_len; 1025678453a8Sspeer buf_len -= print_len; 1026678453a8Sspeer } 102744961713Sgirish } 1028a3c5bd6dSspeer 102944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_txdma_info")); 103044961713Sgirish return (0); 103144961713Sgirish } 103244961713Sgirish 103344961713Sgirish /* ARGSUSED */ 103444961713Sgirish int 103544961713Sgirish nxge_param_get_rxdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 103644961713Sgirish { 1037a3c5bd6dSspeer uint_t print_len, buf_len; 1038a3c5bd6dSspeer p_mblk_t np; 1039a3c5bd6dSspeer int rdc; 104044961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 104144961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 1042a3c5bd6dSspeer int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 104344961713Sgirish p_rx_rcr_rings_t rx_rcr_rings; 104444961713Sgirish p_rx_rcr_ring_t *rcr_rings; 104544961713Sgirish p_rx_rbr_rings_t rx_rbr_rings; 104644961713Sgirish p_rx_rbr_ring_t *rbr_rings; 1047678453a8Sspeer nxge_grp_set_t *set; 104844961713Sgirish 104944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rxdma_info")); 105044961713Sgirish 1051a3c5bd6dSspeer (void) mi_mpprintf(mp, "RXDMA Information for Port\t %d \n", 10524045d941Ssowmini nxgep->function_num); 105344961713Sgirish 105444961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 105544961713Sgirish /* The following may work even if we cannot get a large buf. */ 105644961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 105744961713Sgirish return (0); 105844961713Sgirish } 105944961713Sgirish 106044961713Sgirish buf_len = buff_alloc_size; 106144961713Sgirish mp->b_cont = np; 106244961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 106344961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 106444961713Sgirish 106544961713Sgirish rx_rcr_rings = nxgep->rx_rcr_rings; 106644961713Sgirish rcr_rings = rx_rcr_rings->rcr_rings; 106744961713Sgirish rx_rbr_rings = nxgep->rx_rbr_rings; 106844961713Sgirish rbr_rings = rx_rbr_rings->rbr_rings; 106944961713Sgirish 107044961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 10714045d941Ssowmini "Total RDCs\t %d\n", p_cfgp->max_rdcs); 107244961713Sgirish 107344961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 107444961713Sgirish buf_len -= print_len; 107544961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 10764045d941Ssowmini "RDC\t HW RDC\t Timeout\t Packets RBR ptr \t" 10774045d941Ssowmini "chunks\t RCR ptr\n"); 1078a3c5bd6dSspeer 107944961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 108044961713Sgirish buf_len -= print_len; 1081678453a8Sspeer 1082678453a8Sspeer set = &nxgep->rx_set; 1083678453a8Sspeer for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 1084678453a8Sspeer if ((1 << rdc) & set->owned.map) { 1085678453a8Sspeer print_len = snprintf((char *) 1086678453a8Sspeer ((mblk_t *)np)->b_wptr, buf_len, 1087678453a8Sspeer " %d\t %x\t\t %x\t $%p\t 0x%x\t $%p\n", 1088678453a8Sspeer rdc, 1089678453a8Sspeer p_dma_cfgp->rcr_timeout[rdc], 1090678453a8Sspeer p_dma_cfgp->rcr_threshold[rdc], 10918793b36bSNick Todd (void *)rbr_rings[rdc], 10928793b36bSNick Todd rbr_rings[rdc]->num_blocks, (void *)rcr_rings[rdc]); 1093a3c5bd6dSspeer ((mblk_t *)np)->b_wptr += print_len; 1094a3c5bd6dSspeer buf_len -= print_len; 1095678453a8Sspeer } 109644961713Sgirish } 1097a3c5bd6dSspeer 109844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rxdma_info")); 109944961713Sgirish return (0); 110044961713Sgirish } 110144961713Sgirish 110244961713Sgirish /* ARGSUSED */ 110344961713Sgirish int 110444961713Sgirish nxge_param_get_rxdma_rdcgrp_info(p_nxge_t nxgep, queue_t *q, 1105*fe054a6cSToomas Soome p_mblk_t mp, caddr_t cp) 110644961713Sgirish { 1107a3c5bd6dSspeer uint_t print_len, buf_len; 1108a3c5bd6dSspeer p_mblk_t np; 1109a3c5bd6dSspeer int offset, rdc, i, rdc_grp; 111044961713Sgirish p_nxge_rdc_grp_t rdc_grp_p; 111144961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 111244961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 111344961713Sgirish 111444961713Sgirish int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 111544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 11164045d941Ssowmini "==> nxge_param_get_rxdma_rdcgrp_info")); 111744961713Sgirish 111844961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 111944961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 112044961713Sgirish 1121a3c5bd6dSspeer (void) mi_mpprintf(mp, "RXDMA RDC Group Information for Port\t %d \n", 11224045d941Ssowmini nxgep->function_num); 112344961713Sgirish 1124678453a8Sspeer rdc_grp = p_cfgp->def_mac_rxdma_grpid; 112544961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 112644961713Sgirish /* The following may work even if we cannot get a large buf. */ 112744961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 112844961713Sgirish return (0); 112944961713Sgirish } 113044961713Sgirish 113144961713Sgirish buf_len = buff_alloc_size; 113244961713Sgirish mp->b_cont = np; 113344961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 11344045d941Ssowmini "Total RDC Groups\t %d \n" 11354045d941Ssowmini "default RDC group\t %d\n", 11364045d941Ssowmini p_cfgp->max_rdc_grpids, 11374045d941Ssowmini p_cfgp->def_mac_rxdma_grpid); 113844961713Sgirish 113944961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 114044961713Sgirish buf_len -= print_len; 114144961713Sgirish 11427b26d9ffSSantwona Behera for (i = 0; i < NXGE_MAX_RDC_GROUPS; i++) { 1143678453a8Sspeer if (p_cfgp->grpids[i]) { 1144678453a8Sspeer rdc_grp_p = &p_dma_cfgp->rdc_grps[i]; 114544961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1146678453a8Sspeer buf_len, 1147678453a8Sspeer "\nRDC Group Info for Group [%d] %d\n" 1148678453a8Sspeer "RDC Count %d\tstart RDC %d\n" 1149678453a8Sspeer "RDC Group Population Information" 1150678453a8Sspeer " (offsets 0 - 15)\n", 1151678453a8Sspeer i, rdc_grp, rdc_grp_p->max_rdcs, 1152678453a8Sspeer rdc_grp_p->start_rdc); 1153678453a8Sspeer 1154678453a8Sspeer ((mblk_t *)np)->b_wptr += print_len; 1155678453a8Sspeer buf_len -= print_len; 1156678453a8Sspeer print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1157678453a8Sspeer buf_len, "\n"); 1158678453a8Sspeer ((mblk_t *)np)->b_wptr += print_len; 1159678453a8Sspeer buf_len -= print_len; 1160678453a8Sspeer 1161678453a8Sspeer for (rdc = 0; rdc < rdc_grp_p->max_rdcs; rdc++) { 1162678453a8Sspeer print_len = snprintf( 11634045d941Ssowmini (char *)((mblk_t *)np)->b_wptr, 11644045d941Ssowmini buf_len, "[%d]=%d ", rdc, 11654045d941Ssowmini rdc_grp_p->start_rdc + rdc); 1166678453a8Sspeer ((mblk_t *)np)->b_wptr += print_len; 1167678453a8Sspeer buf_len -= print_len; 1168678453a8Sspeer } 1169678453a8Sspeer print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1170678453a8Sspeer buf_len, "\n"); 117144961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 117244961713Sgirish buf_len -= print_len; 117344961713Sgirish 1174678453a8Sspeer for (offset = 0; offset < 16; offset++) { 1175678453a8Sspeer print_len = snprintf( 11764045d941Ssowmini (char *)((mblk_t *)np)->b_wptr, 11774045d941Ssowmini buf_len, " %c", 11784045d941Ssowmini rdc_grp_p->map & (1 << offset) ? 11794045d941Ssowmini '1' : '0'); 1180678453a8Sspeer ((mblk_t *)np)->b_wptr += print_len; 1181678453a8Sspeer buf_len -= print_len; 1182678453a8Sspeer } 118344961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1184678453a8Sspeer buf_len, "\n"); 118544961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 118644961713Sgirish buf_len -= print_len; 118744961713Sgirish } 118844961713Sgirish } 118944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 11904045d941Ssowmini "<== nxge_param_get_rxdma_rdcgrp_info")); 119144961713Sgirish return (0); 119244961713Sgirish } 119344961713Sgirish 119444961713Sgirish int 119544961713Sgirish nxge_mk_mblk_tail_space(p_mblk_t mp, p_mblk_t *nmp, size_t size) 119644961713Sgirish { 119744961713Sgirish p_mblk_t tmp; 119844961713Sgirish 119944961713Sgirish tmp = mp; 120044961713Sgirish while (tmp->b_cont) 120144961713Sgirish tmp = tmp->b_cont; 120244961713Sgirish if ((tmp->b_wptr + size) >= tmp->b_datap->db_lim) { 120344961713Sgirish tmp->b_cont = allocb(1024, BPRI_HI); 120444961713Sgirish tmp = tmp->b_cont; 120544961713Sgirish if (!tmp) 120644961713Sgirish return (ENOMEM); 120744961713Sgirish } 1208a3c5bd6dSspeer 120944961713Sgirish *nmp = tmp; 121044961713Sgirish return (0); 121144961713Sgirish } 121244961713Sgirish 1213a3c5bd6dSspeer 121444961713Sgirish /* ARGSUSED */ 121544961713Sgirish int 121644961713Sgirish nxge_param_set_generic(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1217*fe054a6cSToomas Soome char *value, caddr_t cp) 121844961713Sgirish { 121944961713Sgirish char *end; 122044961713Sgirish uint32_t new_value; 122144961713Sgirish p_nxge_param_t pa = (p_nxge_param_t)cp; 122244961713Sgirish 122344961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, " ==> nxge_param_set_generic")); 122444961713Sgirish new_value = (uint32_t)mi_strtol(value, &end, 10); 122544961713Sgirish if (end == value || new_value < pa->minimum || 12264045d941Ssowmini new_value > pa->maximum) { 122744961713Sgirish return (EINVAL); 122844961713Sgirish } 122944961713Sgirish pa->value = new_value; 123044961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, " <== nxge_param_set_generic")); 123144961713Sgirish return (0); 123244961713Sgirish } 123344961713Sgirish 123444961713Sgirish 1235a3c5bd6dSspeer /* ARGSUSED */ 123644961713Sgirish int 1237a3c5bd6dSspeer nxge_param_set_instance(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1238*fe054a6cSToomas Soome char *value, caddr_t cp) 123944961713Sgirish { 124044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " ==> nxge_param_set_instance")); 124144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_set_instance")); 124244961713Sgirish return (0); 124344961713Sgirish } 124444961713Sgirish 124544961713Sgirish 1246a3c5bd6dSspeer /* ARGSUSED */ 124744961713Sgirish int 1248a3c5bd6dSspeer nxge_param_set_mac(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1249*fe054a6cSToomas Soome char *value, caddr_t cp) 125044961713Sgirish { 1251a3c5bd6dSspeer char *end; 1252a3c5bd6dSspeer uint32_t new_value; 1253a3c5bd6dSspeer int status = 0; 1254a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 125544961713Sgirish 125644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac")); 125744961713Sgirish new_value = (uint32_t)mi_strtol(value, &end, BASE_DECIMAL); 125844961713Sgirish if (PARAM_OUTOF_RANGE(value, end, new_value, pa)) { 125944961713Sgirish return (EINVAL); 126044961713Sgirish } 126144961713Sgirish 126244961713Sgirish if (pa->value != new_value) { 126344961713Sgirish pa->old_value = pa->value; 126444961713Sgirish pa->value = new_value; 126544961713Sgirish } 126644961713Sgirish 126744961713Sgirish if (!nxge_param_link_update(nxgep)) { 126844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 12694045d941Ssowmini " false ret from nxge_param_link_update")); 127044961713Sgirish status = EINVAL; 127144961713Sgirish } 127244961713Sgirish 127344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac")); 127444961713Sgirish return (status); 127544961713Sgirish } 127644961713Sgirish 127744961713Sgirish /* ARGSUSED */ 12781bd6825cSml int 1279a3c5bd6dSspeer nxge_param_rx_intr_pkts(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1280*fe054a6cSToomas Soome char *value, caddr_t cp) 128144961713Sgirish { 1282a3c5bd6dSspeer char *end; 1283a3c5bd6dSspeer uint32_t cfg_value; 1284a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 128514ea4bb7Ssd 128644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_pkts")); 128744961713Sgirish 128814ea4bb7Ssd cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 128944961713Sgirish 129014ea4bb7Ssd if ((cfg_value > NXGE_RDC_RCR_THRESHOLD_MAX) || 12914045d941Ssowmini (cfg_value < NXGE_RDC_RCR_THRESHOLD_MIN)) { 129244961713Sgirish return (EINVAL); 129344961713Sgirish } 129414ea4bb7Ssd 129514ea4bb7Ssd if ((pa->value != cfg_value)) { 129614ea4bb7Ssd pa->old_value = pa->value; 129714ea4bb7Ssd pa->value = cfg_value; 129814ea4bb7Ssd nxgep->intr_threshold = pa->value; 129944961713Sgirish } 130014ea4bb7Ssd 130144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_pkts")); 130244961713Sgirish return (0); 130344961713Sgirish } 130444961713Sgirish 130544961713Sgirish /* ARGSUSED */ 13061bd6825cSml int 1307a3c5bd6dSspeer nxge_param_rx_intr_time(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1308*fe054a6cSToomas Soome char *value, caddr_t cp) 130944961713Sgirish { 1310a3c5bd6dSspeer char *end; 1311a3c5bd6dSspeer uint32_t cfg_value; 1312a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 131344961713Sgirish 131444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_time")); 131544961713Sgirish 131614ea4bb7Ssd cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 131744961713Sgirish 131814ea4bb7Ssd if ((cfg_value > NXGE_RDC_RCR_TIMEOUT_MAX) || 13194045d941Ssowmini (cfg_value < NXGE_RDC_RCR_TIMEOUT_MIN)) { 132044961713Sgirish return (EINVAL); 132144961713Sgirish } 132244961713Sgirish 132314ea4bb7Ssd if ((pa->value != cfg_value)) { 132414ea4bb7Ssd pa->old_value = pa->value; 132514ea4bb7Ssd pa->value = cfg_value; 132614ea4bb7Ssd nxgep->intr_timeout = pa->value; 132744961713Sgirish } 132844961713Sgirish 132944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_time")); 133044961713Sgirish return (0); 133144961713Sgirish } 133244961713Sgirish 133344961713Sgirish /* ARGSUSED */ 133444961713Sgirish static int 133544961713Sgirish nxge_param_set_mac_rdcgrp(p_nxge_t nxgep, queue_t *q, 1336*fe054a6cSToomas Soome mblk_t *mp, char *value, caddr_t cp) 133744961713Sgirish { 1338a3c5bd6dSspeer char *end; 1339a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1340a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1341a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 134244961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 134344961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 1344a3c5bd6dSspeer uint32_t *val_ptr, *old_val_ptr; 1345a3c5bd6dSspeer nxge_param_map_t *mac_map; 1346a3c5bd6dSspeer p_nxge_class_pt_cfg_t p_class_cfgp; 1347a3c5bd6dSspeer nxge_mv_cfg_t *mac_host_info; 134844961713Sgirish 134944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac_rdcgrp ")); 135044961713Sgirish 135144961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 135244961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 135344961713Sgirish p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 135444961713Sgirish mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 135544961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1356a3c5bd6dSspeer 1357a3c5bd6dSspeer /* 1358a3c5bd6dSspeer * now do decoding 1359a3c5bd6dSspeer */ 136044961713Sgirish mac_map = (nxge_param_map_t *)&cfg_value; 1361a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, NDD_CTL, " cfg_value %x id %x map_to %x", 13624045d941Ssowmini cfg_value, mac_map->param_id, mac_map->map_to)); 136344961713Sgirish 136444961713Sgirish if ((mac_map->param_id < p_cfgp->max_macs) && 1365678453a8Sspeer p_cfgp->grpids[mac_map->map_to]) { 136644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1367678453a8Sspeer " nxge_param_set_mac_rdcgrp mapping" 1368678453a8Sspeer " id %d grp %d", mac_map->param_id, mac_map->map_to)); 1369adfcba55Sjoycey #if defined(__i386) 1370adfcba55Sjoycey val_ptr = (uint32_t *)(uint32_t)pa->value; 1371adfcba55Sjoycey #else 137244961713Sgirish val_ptr = (uint32_t *)pa->value; 1373adfcba55Sjoycey #endif 1374adfcba55Sjoycey #if defined(__i386) 1375adfcba55Sjoycey old_val_ptr = (uint32_t *)(uint32_t)pa->old_value; 1376adfcba55Sjoycey #else 137744961713Sgirish old_val_ptr = (uint32_t *)pa->old_value; 1378adfcba55Sjoycey #endif 137944961713Sgirish if (val_ptr[mac_map->param_id] != cfg_value) { 138044961713Sgirish old_val_ptr[mac_map->param_id] = 1381678453a8Sspeer val_ptr[mac_map->param_id]; 138244961713Sgirish val_ptr[mac_map->param_id] = cfg_value; 138344961713Sgirish mac_host_info[mac_map->param_id].mpr_npr = 1384678453a8Sspeer mac_map->pref; 138544961713Sgirish mac_host_info[mac_map->param_id].flag = 1; 138644961713Sgirish mac_host_info[mac_map->param_id].rdctbl = 1387678453a8Sspeer mac_map->map_to; 138844961713Sgirish cfg_it = B_TRUE; 138944961713Sgirish } 139044961713Sgirish } else { 139144961713Sgirish return (EINVAL); 139244961713Sgirish } 139344961713Sgirish 139444961713Sgirish if (cfg_it == B_TRUE) { 139544961713Sgirish status = nxge_logical_mac_assign_rdc_table(nxgep, 1396678453a8Sspeer (uint8_t)mac_map->param_id); 139744961713Sgirish if (status != NXGE_OK) 139844961713Sgirish return (EINVAL); 139944961713Sgirish } 140044961713Sgirish 140144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac_rdcgrp")); 140244961713Sgirish return (0); 140344961713Sgirish } 140444961713Sgirish 140544961713Sgirish /* ARGSUSED */ 140644961713Sgirish static int 140744961713Sgirish nxge_param_set_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q, 1408*fe054a6cSToomas Soome mblk_t *mp, char *value, caddr_t cp) 140944961713Sgirish { 1410a3c5bd6dSspeer char *end; 1411a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1412a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1413a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 141444961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 141544961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 1416a3c5bd6dSspeer uint32_t *val_ptr, *old_val_ptr; 1417a3c5bd6dSspeer nxge_param_map_t *vmap, *old_map; 1418a3c5bd6dSspeer p_nxge_class_pt_cfg_t p_class_cfgp; 1419a3c5bd6dSspeer uint64_t cfgd_vlans; 1420a3c5bd6dSspeer int i, inc = 0, cfg_position; 1421a3c5bd6dSspeer nxge_mv_cfg_t *vlan_tbl; 142244961713Sgirish 142344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp ")); 142444961713Sgirish 142544961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 142644961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 142744961713Sgirish p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 142844961713Sgirish vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 142944961713Sgirish 143044961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1431a3c5bd6dSspeer 1432a3c5bd6dSspeer /* now do decoding */ 143344961713Sgirish cfgd_vlans = ((pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >> 14344045d941Ssowmini NXGE_PARAM_ARRAY_CNT_SHIFT); 143544961713Sgirish 143644961713Sgirish if (cfgd_vlans == NXGE_PARAM_ARRAY_INIT_SIZE) { 143744961713Sgirish /* 143844961713Sgirish * for now, we process only upto max 143944961713Sgirish * NXGE_PARAM_ARRAY_INIT_SIZE parameters 144044961713Sgirish * In the future, we may want to expand 144144961713Sgirish * the storage array and continue 144244961713Sgirish */ 144344961713Sgirish return (EINVAL); 144444961713Sgirish } 1445a3c5bd6dSspeer 144644961713Sgirish vmap = (nxge_param_map_t *)&cfg_value; 144744961713Sgirish if ((vmap->param_id) && 14484045d941Ssowmini (vmap->param_id < NXGE_MAX_VLANS) && 14494045d941Ssowmini (vmap->map_to < p_cfgp->max_rdc_grpids)) { 145044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 14514045d941Ssowmini "nxge_param_set_vlan_rdcgrp mapping" 14524045d941Ssowmini " id %d grp %d", 14534045d941Ssowmini vmap->param_id, vmap->map_to)); 1454adfcba55Sjoycey #if defined(__i386) 1455adfcba55Sjoycey val_ptr = (uint32_t *)(uint32_t)pa->value; 1456adfcba55Sjoycey #else 145744961713Sgirish val_ptr = (uint32_t *)pa->value; 1458adfcba55Sjoycey #endif 1459adfcba55Sjoycey #if defined(__i386) 1460adfcba55Sjoycey old_val_ptr = (uint32_t *)(uint32_t)pa->old_value; 1461adfcba55Sjoycey #else 146244961713Sgirish old_val_ptr = (uint32_t *)pa->old_value; 1463adfcba55Sjoycey #endif 146444961713Sgirish 146544961713Sgirish /* search to see if this vlan id is already configured */ 146644961713Sgirish for (i = 0; i < cfgd_vlans; i++) { 146744961713Sgirish old_map = (nxge_param_map_t *)&val_ptr[i]; 146844961713Sgirish if ((old_map->param_id == 0) || 14694045d941Ssowmini (vmap->param_id == old_map->param_id) || 14704045d941Ssowmini (vlan_tbl[vmap->param_id].flag)) { 147144961713Sgirish cfg_position = i; 147244961713Sgirish break; 147344961713Sgirish } 147444961713Sgirish } 147544961713Sgirish 147644961713Sgirish if (cfgd_vlans == 0) { 147744961713Sgirish cfg_position = 0; 147844961713Sgirish inc++; 147944961713Sgirish } 148044961713Sgirish 148144961713Sgirish if (i == cfgd_vlans) { 148244961713Sgirish cfg_position = i; 148344961713Sgirish inc++; 148444961713Sgirish } 148544961713Sgirish 148644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 14874045d941Ssowmini "set_vlan_rdcgrp mapping" 14884045d941Ssowmini " i %d cfgd_vlans %llx position %d ", 14894045d941Ssowmini i, cfgd_vlans, cfg_position)); 149044961713Sgirish if (val_ptr[cfg_position] != cfg_value) { 149144961713Sgirish old_val_ptr[cfg_position] = val_ptr[cfg_position]; 149244961713Sgirish val_ptr[cfg_position] = cfg_value; 149344961713Sgirish vlan_tbl[vmap->param_id].mpr_npr = vmap->pref; 149444961713Sgirish vlan_tbl[vmap->param_id].flag = 1; 149544961713Sgirish vlan_tbl[vmap->param_id].rdctbl = 1496678453a8Sspeer vmap->map_to + p_cfgp->def_mac_rxdma_grpid; 149744961713Sgirish cfg_it = B_TRUE; 149844961713Sgirish if (inc) { 149944961713Sgirish cfgd_vlans++; 150044961713Sgirish pa->type &= ~NXGE_PARAM_ARRAY_CNT_MASK; 150144961713Sgirish pa->type |= (cfgd_vlans << 15024045d941Ssowmini NXGE_PARAM_ARRAY_CNT_SHIFT); 150344961713Sgirish 150444961713Sgirish } 150544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 15064045d941Ssowmini "after: param_set_vlan_rdcgrp " 15074045d941Ssowmini " cfg_vlans %llx position %d \n", 15084045d941Ssowmini cfgd_vlans, cfg_position)); 150944961713Sgirish } 151044961713Sgirish } else { 151144961713Sgirish return (EINVAL); 151244961713Sgirish } 151344961713Sgirish 151444961713Sgirish if (cfg_it == B_TRUE) { 151544961713Sgirish status = nxge_fflp_config_vlan_table(nxgep, 15164045d941Ssowmini (uint16_t)vmap->param_id); 151744961713Sgirish if (status != NXGE_OK) 151844961713Sgirish return (EINVAL); 151944961713Sgirish } 152044961713Sgirish 152144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_vlan_rdcgrp")); 152244961713Sgirish return (0); 152344961713Sgirish } 152444961713Sgirish 152544961713Sgirish /* ARGSUSED */ 152644961713Sgirish static int 152744961713Sgirish nxge_param_get_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q, 1528*fe054a6cSToomas Soome mblk_t *mp, caddr_t cp) 152944961713Sgirish { 153044961713Sgirish 1531a3c5bd6dSspeer uint_t print_len, buf_len; 1532a3c5bd6dSspeer p_mblk_t np; 1533a3c5bd6dSspeer int i; 1534a3c5bd6dSspeer uint32_t *val_ptr; 1535a3c5bd6dSspeer nxge_param_map_t *vmap; 1536a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 153744961713Sgirish p_nxge_class_pt_cfg_t p_class_cfgp; 153844961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 153944961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 1540a3c5bd6dSspeer uint64_t cfgd_vlans = 0; 1541a3c5bd6dSspeer nxge_mv_cfg_t *vlan_tbl; 1542a3c5bd6dSspeer int buff_alloc_size = 15434045d941Ssowmini NXGE_NDD_INFODUMP_BUFF_SIZE * 32; 154444961713Sgirish 154544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp ")); 1546a3c5bd6dSspeer (void) mi_mpprintf(mp, "VLAN RDC Mapping Information for Port\t %d \n", 15474045d941Ssowmini nxgep->function_num); 154844961713Sgirish 154944961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 155044961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 155144961713Sgirish return (0); 155244961713Sgirish } 1553a3c5bd6dSspeer 155444961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 155544961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 155644961713Sgirish 155744961713Sgirish buf_len = buff_alloc_size; 155844961713Sgirish mp->b_cont = np; 155944961713Sgirish cfgd_vlans = (pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >> 15604045d941Ssowmini NXGE_PARAM_ARRAY_CNT_SHIFT; 156144961713Sgirish 156244961713Sgirish i = (int)cfgd_vlans; 156344961713Sgirish p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 156444961713Sgirish vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 156544961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 15664045d941Ssowmini "Configured VLANs %d\n" 15674045d941Ssowmini "VLAN ID\t RDC GRP (Actual/Port)\t" 15684045d941Ssowmini " Prefernce\n", i); 156944961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 157044961713Sgirish buf_len -= print_len; 1571adfcba55Sjoycey #if defined(__i386) 1572adfcba55Sjoycey val_ptr = (uint32_t *)(uint32_t)pa->value; 1573adfcba55Sjoycey #else 157444961713Sgirish val_ptr = (uint32_t *)pa->value; 1575adfcba55Sjoycey #endif 157644961713Sgirish 157744961713Sgirish for (i = 0; i < cfgd_vlans; i++) { 157844961713Sgirish vmap = (nxge_param_map_t *)&val_ptr[i]; 157944961713Sgirish if (p_class_cfgp->vlan_tbl[vmap->param_id].flag) { 158044961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 15814045d941Ssowmini buf_len, 15824045d941Ssowmini " %d\t\t %d/%d\t\t %d\n", 15834045d941Ssowmini vmap->param_id, 15844045d941Ssowmini vlan_tbl[vmap->param_id].rdctbl, 15854045d941Ssowmini vlan_tbl[vmap->param_id].rdctbl - 15864045d941Ssowmini p_cfgp->def_mac_rxdma_grpid, 15874045d941Ssowmini vlan_tbl[vmap->param_id].mpr_npr); 158844961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 158944961713Sgirish buf_len -= print_len; 159044961713Sgirish } 159144961713Sgirish } 159244961713Sgirish 159344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_vlan_rdcgrp")); 159444961713Sgirish return (0); 159544961713Sgirish } 159644961713Sgirish 159744961713Sgirish /* ARGSUSED */ 159844961713Sgirish static int 159944961713Sgirish nxge_param_get_mac_rdcgrp(p_nxge_t nxgep, queue_t *q, 1600*fe054a6cSToomas Soome mblk_t *mp, caddr_t cp) 160144961713Sgirish { 1602a3c5bd6dSspeer uint_t print_len, buf_len; 1603a3c5bd6dSspeer p_mblk_t np; 1604a3c5bd6dSspeer int i; 160544961713Sgirish p_nxge_class_pt_cfg_t p_class_cfgp; 160644961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 160744961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 1608a3c5bd6dSspeer nxge_mv_cfg_t *mac_host_info; 160944961713Sgirish 161044961713Sgirish int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE * 32; 161144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac_rdcgrp ")); 161244961713Sgirish (void) mi_mpprintf(mp, 16134045d941Ssowmini "MAC ADDR RDC Mapping Information for Port\t %d\n", 16144045d941Ssowmini nxgep->function_num); 161544961713Sgirish 161644961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 161744961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 161844961713Sgirish return (0); 161944961713Sgirish } 162044961713Sgirish 162144961713Sgirish buf_len = buff_alloc_size; 162244961713Sgirish mp->b_cont = np; 162344961713Sgirish p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 162444961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 162544961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 162644961713Sgirish mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 162744961713Sgirish print_len = snprintf((char *)np->b_wptr, buf_len, 16284045d941Ssowmini "MAC ID\t RDC GRP (Actual/Port)\t" 16294045d941Ssowmini " Prefernce\n"); 163044961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 163144961713Sgirish buf_len -= print_len; 163244961713Sgirish for (i = 0; i < p_cfgp->max_macs; i++) { 163344961713Sgirish if (mac_host_info[i].flag) { 163444961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 16354045d941Ssowmini buf_len, 16364045d941Ssowmini " %d\t %d/%d\t\t %d\n", 16374045d941Ssowmini i, mac_host_info[i].rdctbl, 16384045d941Ssowmini mac_host_info[i].rdctbl - 16394045d941Ssowmini p_cfgp->def_mac_rxdma_grpid, 16404045d941Ssowmini mac_host_info[i].mpr_npr); 164144961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 164244961713Sgirish buf_len -= print_len; 164344961713Sgirish } 164444961713Sgirish } 164544961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 16464045d941Ssowmini "Done Info Dumping \n"); 164744961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 164844961713Sgirish buf_len -= print_len; 164944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_macrdcgrp")); 165044961713Sgirish return (0); 165144961713Sgirish } 165244961713Sgirish 165344961713Sgirish /* ARGSUSED */ 165444961713Sgirish static int 165544961713Sgirish nxge_param_tcam_enable(p_nxge_t nxgep, queue_t *q, 1656*fe054a6cSToomas Soome mblk_t *mp, char *value, caddr_t cp) 165744961713Sgirish { 1658a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1659a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1660a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 1661a3c5bd6dSspeer char *end; 166244961713Sgirish 166344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_tcam_enable")); 166444961713Sgirish 166544961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 166644961713Sgirish if (pa->value != cfg_value) { 166744961713Sgirish pa->old_value = pa->value; 166844961713Sgirish pa->value = cfg_value; 166944961713Sgirish cfg_it = B_TRUE; 167044961713Sgirish } 167144961713Sgirish 167244961713Sgirish if (cfg_it == B_TRUE) { 167344961713Sgirish if (pa->value) 167444961713Sgirish status = nxge_fflp_config_tcam_enable(nxgep); 167544961713Sgirish else 167644961713Sgirish status = nxge_fflp_config_tcam_disable(nxgep); 167744961713Sgirish if (status != NXGE_OK) 167844961713Sgirish return (EINVAL); 167944961713Sgirish } 168044961713Sgirish 168144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_tcam_enable")); 168244961713Sgirish return (0); 168344961713Sgirish } 168444961713Sgirish 168544961713Sgirish /* ARGSUSED */ 168644961713Sgirish static int 168744961713Sgirish nxge_param_hash_lookup_enable(p_nxge_t nxgep, queue_t *q, 1688*fe054a6cSToomas Soome mblk_t *mp, char *value, caddr_t cp) 168944961713Sgirish { 1690a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1691a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1692a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 1693a3c5bd6dSspeer char *end; 169444961713Sgirish 169544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_hash_lookup_enable")); 169644961713Sgirish 169744961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 169844961713Sgirish if (pa->value != cfg_value) { 169944961713Sgirish pa->old_value = pa->value; 170044961713Sgirish pa->value = cfg_value; 170144961713Sgirish cfg_it = B_TRUE; 170244961713Sgirish } 170344961713Sgirish 170444961713Sgirish if (cfg_it == B_TRUE) { 170544961713Sgirish if (pa->value) 170644961713Sgirish status = nxge_fflp_config_hash_lookup_enable(nxgep); 170744961713Sgirish else 170844961713Sgirish status = nxge_fflp_config_hash_lookup_disable(nxgep); 170944961713Sgirish if (status != NXGE_OK) 171044961713Sgirish return (EINVAL); 171144961713Sgirish } 171244961713Sgirish 171344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_hash_lookup_enable")); 171444961713Sgirish return (0); 171544961713Sgirish } 171644961713Sgirish 171744961713Sgirish /* ARGSUSED */ 171844961713Sgirish static int 171944961713Sgirish nxge_param_llc_snap_enable(p_nxge_t nxgep, queue_t *q, 1720*fe054a6cSToomas Soome mblk_t *mp, char *value, caddr_t cp) 172144961713Sgirish { 1722a3c5bd6dSspeer char *end; 1723a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1724a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1725a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 172644961713Sgirish 172744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_llc_snap_enable")); 172844961713Sgirish 172944961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 173044961713Sgirish if (pa->value != cfg_value) { 173144961713Sgirish pa->old_value = pa->value; 173244961713Sgirish pa->value = cfg_value; 173344961713Sgirish cfg_it = B_TRUE; 173444961713Sgirish } 173544961713Sgirish 173644961713Sgirish if (cfg_it == B_TRUE) { 173744961713Sgirish if (pa->value) 173844961713Sgirish status = nxge_fflp_config_tcam_enable(nxgep); 173944961713Sgirish else 174044961713Sgirish status = nxge_fflp_config_tcam_disable(nxgep); 174144961713Sgirish if (status != NXGE_OK) 174244961713Sgirish return (EINVAL); 174344961713Sgirish } 174444961713Sgirish 174544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_llc_snap_enable")); 174644961713Sgirish return (0); 174744961713Sgirish } 174844961713Sgirish 174944961713Sgirish /* ARGSUSED */ 175044961713Sgirish static int 175144961713Sgirish nxge_param_set_ether_usr(p_nxge_t nxgep, queue_t *q, 1752*fe054a6cSToomas Soome mblk_t *mp, char *value, caddr_t cp) 175344961713Sgirish { 1754a3c5bd6dSspeer char *end; 1755a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1756a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1757a3c5bd6dSspeer uint8_t cfg_it = B_FALSE; 175844961713Sgirish 175944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ether_usr")); 176044961713Sgirish 176144961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 176244961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 176344961713Sgirish return (EINVAL); 176444961713Sgirish } 1765a3c5bd6dSspeer 176644961713Sgirish if (pa->value != cfg_value) { 176744961713Sgirish pa->old_value = pa->value; 176844961713Sgirish pa->value = cfg_value; 176944961713Sgirish cfg_it = B_TRUE; 177044961713Sgirish } 177144961713Sgirish 177244961713Sgirish /* do the actual hw setup */ 177344961713Sgirish if (cfg_it == B_TRUE) { 1774*fe054a6cSToomas Soome (void) mi_strtol(pa->name, &end, BASE_DECIMAL); 177544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_ether_usr")); 177644961713Sgirish } 1777a3c5bd6dSspeer 177844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ether_usr")); 177944961713Sgirish return (status); 178044961713Sgirish } 178144961713Sgirish 178244961713Sgirish /* ARGSUSED */ 178344961713Sgirish static int 178444961713Sgirish nxge_param_set_ip_usr(p_nxge_t nxgep, queue_t *q, 1785*fe054a6cSToomas Soome mblk_t *mp, char *value, caddr_t cp) 178644961713Sgirish { 1787a3c5bd6dSspeer char *end; 1788a3c5bd6dSspeer tcam_class_t class; 1789a3c5bd6dSspeer uint32_t status, cfg_value; 1790a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1791a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 179244961713Sgirish 179344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_usr")); 179444961713Sgirish 179544961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 179644961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 179744961713Sgirish return (EINVAL); 179844961713Sgirish } 179944961713Sgirish 180044961713Sgirish if (pa->value != cfg_value) { 180144961713Sgirish pa->old_value = pa->value; 180244961713Sgirish pa->value = cfg_value; 180344961713Sgirish cfg_it = B_TRUE; 180444961713Sgirish } 180544961713Sgirish 180644961713Sgirish /* do the actual hw setup with cfg_value. */ 180744961713Sgirish if (cfg_it == B_TRUE) { 180844961713Sgirish class = mi_strtol(pa->name, &end, 10); 180944961713Sgirish status = nxge_fflp_ip_usr_class_config(nxgep, class, pa->value); 181044961713Sgirish } 181144961713Sgirish 181244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_usr")); 181344961713Sgirish return (status); 181444961713Sgirish } 181544961713Sgirish 1816a3c5bd6dSspeer /* ARGSUSED */ 181744961713Sgirish static int 181844961713Sgirish nxge_class_name_2value(p_nxge_t nxgep, char *name) 181944961713Sgirish { 1820a3c5bd6dSspeer int i; 1821a3c5bd6dSspeer int class_instance = param_class_opt_ip_usr4; 1822a3c5bd6dSspeer p_nxge_param_t param_arr; 1823a3c5bd6dSspeer 182444961713Sgirish param_arr = nxgep->param_arr; 182544961713Sgirish for (i = TCAM_CLASS_IP_USER_4; i <= TCAM_CLASS_SCTP_IPV6; i++) { 182644961713Sgirish if (strcmp(param_arr[class_instance].name, name) == 0) 182744961713Sgirish return (i); 182844961713Sgirish class_instance++; 182944961713Sgirish } 183044961713Sgirish return (-1); 183144961713Sgirish } 183244961713Sgirish 183344961713Sgirish /* ARGSUSED */ 18341bd6825cSml int 183544961713Sgirish nxge_param_set_ip_opt(p_nxge_t nxgep, queue_t *q, 1836*fe054a6cSToomas Soome mblk_t *mp, char *value, caddr_t cp) 183744961713Sgirish { 1838a3c5bd6dSspeer char *end; 1839a3c5bd6dSspeer uint32_t status, cfg_value; 1840a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1841a3c5bd6dSspeer tcam_class_t class; 1842a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 184344961713Sgirish 184444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_opt")); 184544961713Sgirish 184644961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 184744961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 184844961713Sgirish return (EINVAL); 184944961713Sgirish } 185044961713Sgirish 185144961713Sgirish if (pa->value != cfg_value) { 185244961713Sgirish pa->old_value = pa->value; 185344961713Sgirish pa->value = cfg_value; 185444961713Sgirish cfg_it = B_TRUE; 185544961713Sgirish } 185644961713Sgirish 185744961713Sgirish if (cfg_it == B_TRUE) { 1858a3c5bd6dSspeer /* do the actual hw setup */ 185944961713Sgirish class = nxge_class_name_2value(nxgep, pa->name); 186044961713Sgirish if (class == -1) 186144961713Sgirish return (EINVAL); 186244961713Sgirish 1863c1f9c6e5SSantwona Behera /* Filter out the allowed bits */ 1864c1f9c6e5SSantwona Behera pa->value &= (NXGE_CLASS_FLOW_USE_PORTNUM | 1865c1f9c6e5SSantwona Behera NXGE_CLASS_FLOW_USE_L2DA | NXGE_CLASS_FLOW_USE_VLAN | 1866c1f9c6e5SSantwona Behera NXGE_CLASS_FLOW_USE_PROTO | NXGE_CLASS_FLOW_USE_IPSRC | 1867c1f9c6e5SSantwona Behera NXGE_CLASS_FLOW_USE_IPDST | NXGE_CLASS_FLOW_USE_SRC_PORT | 1868c1f9c6e5SSantwona Behera NXGE_CLASS_FLOW_USE_DST_PORT); 1869c1f9c6e5SSantwona Behera 187044961713Sgirish status = nxge_fflp_ip_class_config(nxgep, class, pa->value); 187144961713Sgirish if (status != NXGE_OK) 187244961713Sgirish return (EINVAL); 187344961713Sgirish } 187444961713Sgirish 187544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_opt")); 187644961713Sgirish return (0); 187744961713Sgirish } 187844961713Sgirish 187944961713Sgirish /* ARGSUSED */ 188044961713Sgirish static int 188144961713Sgirish nxge_param_get_ip_opt(p_nxge_t nxgep, queue_t *q, 1882*fe054a6cSToomas Soome mblk_t *mp, caddr_t cp) 188344961713Sgirish { 188444961713Sgirish uint32_t status, cfg_value; 188544961713Sgirish p_nxge_param_t pa = (p_nxge_param_t)cp; 188644961713Sgirish tcam_class_t class; 188744961713Sgirish 188844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_ip_opt")); 188944961713Sgirish 1890a3c5bd6dSspeer /* do the actual hw setup */ 189144961713Sgirish class = nxge_class_name_2value(nxgep, pa->name); 189244961713Sgirish if (class == -1) 189344961713Sgirish return (EINVAL); 1894a3c5bd6dSspeer 189544961713Sgirish cfg_value = 0; 189644961713Sgirish status = nxge_fflp_ip_class_config_get(nxgep, class, &cfg_value); 189744961713Sgirish if (status != NXGE_OK) 189844961713Sgirish return (EINVAL); 1899a3c5bd6dSspeer 1900c1f9c6e5SSantwona Behera /* Filter out the allowed bits */ 1901c1f9c6e5SSantwona Behera cfg_value &= (NXGE_CLASS_FLOW_USE_PORTNUM | NXGE_CLASS_FLOW_USE_L2DA | 1902c1f9c6e5SSantwona Behera NXGE_CLASS_FLOW_USE_VLAN | NXGE_CLASS_FLOW_USE_PROTO | 1903c1f9c6e5SSantwona Behera NXGE_CLASS_FLOW_USE_IPSRC | NXGE_CLASS_FLOW_USE_IPDST | 1904c1f9c6e5SSantwona Behera NXGE_CLASS_FLOW_USE_SRC_PORT | NXGE_CLASS_FLOW_USE_DST_PORT); 1905c1f9c6e5SSantwona Behera 190644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 19074045d941Ssowmini "nxge_param_get_ip_opt_get %x ", cfg_value)); 190844961713Sgirish 1909a3c5bd6dSspeer pa->value = cfg_value; 191044961713Sgirish (void) mi_mpprintf(mp, "%x", cfg_value); 1911a3c5bd6dSspeer 191244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_ip_opt status ")); 191344961713Sgirish return (0); 191444961713Sgirish } 191544961713Sgirish 191644961713Sgirish /* ARGSUSED */ 191744961713Sgirish static int 191844961713Sgirish nxge_param_fflp_hash_init(p_nxge_t nxgep, queue_t *q, 1919*fe054a6cSToomas Soome mblk_t *mp, char *value, caddr_t cp) 192044961713Sgirish { 1921a3c5bd6dSspeer char *end; 1922a3c5bd6dSspeer uint32_t status, cfg_value; 1923a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1924a3c5bd6dSspeer tcam_class_t class; 1925a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 192644961713Sgirish 192744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_fflp_hash_init")); 192844961713Sgirish 192944961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 193044961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 193144961713Sgirish return (EINVAL); 193244961713Sgirish } 193344961713Sgirish 193444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 19354045d941Ssowmini "nxge_param_fflp_hash_init value %x", cfg_value)); 1936a3c5bd6dSspeer 193744961713Sgirish if (pa->value != cfg_value) { 193844961713Sgirish pa->old_value = pa->value; 193944961713Sgirish pa->value = cfg_value; 194044961713Sgirish cfg_it = B_TRUE; 194144961713Sgirish } 194244961713Sgirish 194344961713Sgirish if (cfg_it == B_TRUE) { 194444961713Sgirish char *h_name; 1945a3c5bd6dSspeer 194644961713Sgirish /* do the actual hw setup */ 194744961713Sgirish h_name = pa->name; 194844961713Sgirish h_name++; 194944961713Sgirish class = mi_strtol(h_name, &end, 10); 195044961713Sgirish switch (class) { 195144961713Sgirish case 1: 195244961713Sgirish status = nxge_fflp_set_hash1(nxgep, 19534045d941Ssowmini (uint32_t)pa->value); 195444961713Sgirish break; 195544961713Sgirish case 2: 195644961713Sgirish status = nxge_fflp_set_hash2(nxgep, 19574045d941Ssowmini (uint16_t)pa->value); 195844961713Sgirish break; 195944961713Sgirish 196044961713Sgirish default: 196144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 19624045d941Ssowmini " nxge_param_fflp_hash_init" 19634045d941Ssowmini " %s Wrong hash var %d", 19644045d941Ssowmini pa->name, class)); 196544961713Sgirish return (EINVAL); 196644961713Sgirish } 196744961713Sgirish if (status != NXGE_OK) 196844961713Sgirish return (EINVAL); 196944961713Sgirish } 197044961713Sgirish 197144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_fflp_hash_init")); 197244961713Sgirish return (0); 197344961713Sgirish } 197444961713Sgirish 197544961713Sgirish /* ARGSUSED */ 197644961713Sgirish static int 197744961713Sgirish nxge_param_set_grp_rdc(p_nxge_t nxgep, queue_t *q, 1978*fe054a6cSToomas Soome mblk_t *mp, char *value, caddr_t cp) 197944961713Sgirish { 1980a3c5bd6dSspeer char *end; 1981a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1982a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1983a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 1984a3c5bd6dSspeer int rdc_grp; 1985a3c5bd6dSspeer uint8_t real_rdc; 198644961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 198744961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 198844961713Sgirish p_nxge_rdc_grp_t rdc_grp_p; 198944961713Sgirish 199044961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 199144961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 199244961713Sgirish 199344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_grp_rdc")); 199444961713Sgirish 199544961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 199644961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 199744961713Sgirish return (EINVAL); 199844961713Sgirish } 1999a3c5bd6dSspeer 200044961713Sgirish if (cfg_value >= p_cfgp->max_rdcs) { 200144961713Sgirish return (EINVAL); 200244961713Sgirish } 2003a3c5bd6dSspeer 200444961713Sgirish if (pa->value != cfg_value) { 200544961713Sgirish pa->old_value = pa->value; 200644961713Sgirish pa->value = cfg_value; 200744961713Sgirish cfg_it = B_TRUE; 200844961713Sgirish } 200944961713Sgirish 201044961713Sgirish if (cfg_it == B_TRUE) { 201144961713Sgirish char *grp_name; 201244961713Sgirish grp_name = pa->name; 201344961713Sgirish grp_name += strlen("default-grp"); 201444961713Sgirish rdc_grp = mi_strtol(grp_name, &end, 10); 201544961713Sgirish rdc_grp_p = &p_dma_cfgp->rdc_grps[rdc_grp]; 201644961713Sgirish real_rdc = rdc_grp_p->start_rdc + cfg_value; 201744961713Sgirish if (nxge_check_rxdma_rdcgrp_member(nxgep, rdc_grp, 20184045d941Ssowmini cfg_value) == B_FALSE) { 201944961713Sgirish pa->value = pa->old_value; 202044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 20214045d941Ssowmini " nxge_param_set_grp_rdc" 20224045d941Ssowmini " %d read %d actual %d outof range", 20234045d941Ssowmini rdc_grp, cfg_value, real_rdc)); 202444961713Sgirish return (EINVAL); 202544961713Sgirish } 202644961713Sgirish status = nxge_rxdma_cfg_rdcgrp_default_rdc(nxgep, rdc_grp, 20274045d941Ssowmini real_rdc); 202844961713Sgirish if (status != NXGE_OK) 202944961713Sgirish return (EINVAL); 203044961713Sgirish } 203144961713Sgirish 203244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_grp_rdc")); 203344961713Sgirish return (0); 203444961713Sgirish } 203544961713Sgirish 203644961713Sgirish /* ARGSUSED */ 203744961713Sgirish static int 203844961713Sgirish nxge_param_set_port_rdc(p_nxge_t nxgep, queue_t *q, 2039*fe054a6cSToomas Soome mblk_t *mp, char *value, caddr_t cp) 204044961713Sgirish { 2041a3c5bd6dSspeer char *end; 2042a3c5bd6dSspeer uint32_t status = B_TRUE, cfg_value; 2043a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 2044a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 204544961713Sgirish 204644961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 204744961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 204844961713Sgirish 204944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_port_rdc")); 205044961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 205144961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 205244961713Sgirish 205344961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 205444961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 205544961713Sgirish return (EINVAL); 205644961713Sgirish } 2057a3c5bd6dSspeer 205844961713Sgirish if (pa->value != cfg_value) { 205944961713Sgirish if (cfg_value >= p_cfgp->max_rdcs) 206044961713Sgirish return (EINVAL); 206144961713Sgirish pa->old_value = pa->value; 206244961713Sgirish pa->value = cfg_value; 206344961713Sgirish cfg_it = B_TRUE; 206444961713Sgirish } 206544961713Sgirish 206644961713Sgirish if (cfg_it == B_TRUE) { 2067678453a8Sspeer int rdc; 2068678453a8Sspeer if ((rdc = nxge_dci_map(nxgep, VP_BOUND_RX, cfg_value)) < 0) 2069678453a8Sspeer return (EINVAL); 207044961713Sgirish status = nxge_rxdma_cfg_port_default_rdc(nxgep, 2071678453a8Sspeer nxgep->function_num, rdc); 207244961713Sgirish if (status != NXGE_OK) 207344961713Sgirish return (EINVAL); 207444961713Sgirish } 207544961713Sgirish 207644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_port_rdc")); 207744961713Sgirish return (0); 207844961713Sgirish } 207944961713Sgirish 208044961713Sgirish /* ARGSUSED */ 208144961713Sgirish static int 208244961713Sgirish nxge_param_set_nxge_debug_flag(p_nxge_t nxgep, queue_t *q, 2083*fe054a6cSToomas Soome mblk_t *mp, char *value, caddr_t cp) 208444961713Sgirish { 208544961713Sgirish char *end; 208644961713Sgirish uint32_t status = 0; 208744961713Sgirish uint64_t cfg_value = 0; 208844961713Sgirish p_nxge_param_t pa = (p_nxge_param_t)cp; 208944961713Sgirish uint32_t cfg_it = B_FALSE; 209044961713Sgirish 209144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_nxge_debug_flag")); 209244961713Sgirish cfg_value = mi_strtol(value, &end, BASE_HEX); 209344961713Sgirish 209444961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 209544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 20964045d941Ssowmini " nxge_param_set_nxge_debug_flag" 20974045d941Ssowmini " outof range %llx", cfg_value)); 209844961713Sgirish return (EINVAL); 209944961713Sgirish } 210044961713Sgirish if (pa->value != cfg_value) { 210144961713Sgirish pa->old_value = pa->value; 210244961713Sgirish pa->value = cfg_value; 210344961713Sgirish cfg_it = B_TRUE; 210444961713Sgirish } 210544961713Sgirish 210644961713Sgirish if (cfg_it == B_TRUE) { 210744961713Sgirish nxgep->nxge_debug_level = pa->value; 210844961713Sgirish } 2109a3c5bd6dSspeer 211044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_nxge_debug_flag")); 211144961713Sgirish return (status); 211244961713Sgirish } 211344961713Sgirish 211444961713Sgirish /* ARGSUSED */ 211544961713Sgirish static int 211644961713Sgirish nxge_param_get_debug_flag(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 211744961713Sgirish { 2118a3c5bd6dSspeer int status = 0; 2119a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 212044961713Sgirish 212144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_debug_flag")); 212244961713Sgirish 212344961713Sgirish if (pa->value > 0xffffffff) 212444961713Sgirish (void) mi_mpprintf(mp, "%x%x", (int)(pa->value >> 32), 21254045d941Ssowmini (int)(pa->value & 0xffffffff)); 212644961713Sgirish else 212744961713Sgirish (void) mi_mpprintf(mp, "%x", (int)pa->value); 212844961713Sgirish 212944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_debug_flag")); 213044961713Sgirish return (status); 213144961713Sgirish } 213244961713Sgirish 213344961713Sgirish /* ARGSUSED */ 213444961713Sgirish static int 213544961713Sgirish nxge_param_set_npi_debug_flag(p_nxge_t nxgep, queue_t *q, 2136*fe054a6cSToomas Soome mblk_t *mp, char *value, caddr_t cp) 213744961713Sgirish { 2138a3c5bd6dSspeer char *end; 2139a3c5bd6dSspeer uint32_t status = 0; 2140a3c5bd6dSspeer uint64_t cfg_value = 0; 2141a3c5bd6dSspeer p_nxge_param_t pa; 2142a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 214344961713Sgirish 214444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_npi_debug_flag")); 214544961713Sgirish cfg_value = mi_strtol(value, &end, BASE_HEX); 214644961713Sgirish pa = (p_nxge_param_t)cp; 214744961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 214844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_npi_debug_flag" 21494045d941Ssowmini " outof range %llx", cfg_value)); 215044961713Sgirish return (EINVAL); 215144961713Sgirish } 215244961713Sgirish if (pa->value != cfg_value) { 215344961713Sgirish pa->old_value = pa->value; 215444961713Sgirish pa->value = cfg_value; 215544961713Sgirish cfg_it = B_TRUE; 215644961713Sgirish } 215744961713Sgirish 215844961713Sgirish if (cfg_it == B_TRUE) { 215944961713Sgirish npi_debug_level = pa->value; 216044961713Sgirish } 216144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_debug_flag")); 216244961713Sgirish return (status); 216344961713Sgirish } 216444961713Sgirish 216544961713Sgirish /* ARGSUSED */ 216644961713Sgirish static int 216744961713Sgirish nxge_param_dump_rdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 216844961713Sgirish { 2169678453a8Sspeer nxge_grp_set_t *set = &nxgep->rx_set; 2170678453a8Sspeer int rdc; 217144961713Sgirish 217244961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_rdc")); 217344961713Sgirish 2174678453a8Sspeer if (!isLDOMguest(nxgep)) 21754045d941Ssowmini (void) npi_rxdma_dump_fzc_regs(NXGE_DEV_NPI_HANDLE(nxgep)); 2176678453a8Sspeer 2177678453a8Sspeer for (rdc = 0; rdc < NXGE_MAX_TDCS; rdc++) { 2178678453a8Sspeer if ((1 << rdc) & set->owned.map) { 2179678453a8Sspeer (void) nxge_dump_rxdma_channel(nxgep, rdc); 2180678453a8Sspeer } 2181678453a8Sspeer } 218244961713Sgirish 218344961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_rdc")); 218444961713Sgirish return (0); 218544961713Sgirish } 218644961713Sgirish 218744961713Sgirish /* ARGSUSED */ 218844961713Sgirish static int 218944961713Sgirish nxge_param_dump_tdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 219044961713Sgirish { 2191678453a8Sspeer nxge_grp_set_t *set = &nxgep->tx_set; 2192678453a8Sspeer int tdc; 219344961713Sgirish 219444961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_tdc")); 219544961713Sgirish 2196678453a8Sspeer for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) { 2197678453a8Sspeer if ((1 << tdc) & set->owned.map) { 2198678453a8Sspeer (void) nxge_txdma_regs_dump(nxgep, tdc); 2199678453a8Sspeer } 2200678453a8Sspeer } 220144961713Sgirish 220244961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_tdc")); 220344961713Sgirish return (0); 220444961713Sgirish } 220544961713Sgirish 220644961713Sgirish /* ARGSUSED */ 220744961713Sgirish static int 220844961713Sgirish nxge_param_dump_fflp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 220944961713Sgirish { 221044961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_fflp_regs")); 221144961713Sgirish 221244961713Sgirish (void) npi_fflp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep)); 221344961713Sgirish 221444961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_fflp_regs")); 221544961713Sgirish return (0); 221644961713Sgirish } 221744961713Sgirish 221844961713Sgirish /* ARGSUSED */ 221944961713Sgirish static int 222044961713Sgirish nxge_param_dump_mac_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 222144961713Sgirish { 222244961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_mac_regs")); 222344961713Sgirish 222444961713Sgirish (void) npi_mac_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep), 22254045d941Ssowmini nxgep->function_num); 222644961713Sgirish 222744961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_mac_regs")); 222844961713Sgirish return (0); 222944961713Sgirish } 223044961713Sgirish 223144961713Sgirish /* ARGSUSED */ 223244961713Sgirish static int 223344961713Sgirish nxge_param_dump_ipp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 223444961713Sgirish { 223544961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_ipp_regs")); 223644961713Sgirish 2237a3c5bd6dSspeer (void) npi_ipp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep), 22384045d941Ssowmini nxgep->function_num); 223944961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ipp_regs")); 224044961713Sgirish return (0); 224144961713Sgirish } 224244961713Sgirish 224344961713Sgirish /* ARGSUSED */ 224444961713Sgirish static int 224544961713Sgirish nxge_param_dump_vlan_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 224644961713Sgirish { 224744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_vlan_table")); 224844961713Sgirish 224944961713Sgirish (void) npi_fflp_vlan_tbl_dump(NXGE_DEV_NPI_HANDLE(nxgep)); 225044961713Sgirish 225144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_vlan_table")); 225244961713Sgirish return (0); 225344961713Sgirish } 225444961713Sgirish 225544961713Sgirish /* ARGSUSED */ 225644961713Sgirish static int 225744961713Sgirish nxge_param_dump_rdc_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 225844961713Sgirish { 2259a3c5bd6dSspeer uint8_t table; 226044961713Sgirish 226144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_rdc_table")); 226244961713Sgirish for (table = 0; table < NXGE_MAX_RDC_GROUPS; table++) { 226344961713Sgirish (void) npi_rxdma_dump_rdc_table(NXGE_DEV_NPI_HANDLE(nxgep), 22644045d941Ssowmini table); 226544961713Sgirish } 2266a3c5bd6dSspeer 226744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_rdc_table")); 226844961713Sgirish return (0); 226944961713Sgirish } 227044961713Sgirish 227144961713Sgirish typedef struct block_info { 227244961713Sgirish char *name; 227344961713Sgirish uint32_t offset; 227444961713Sgirish } block_info_t; 227544961713Sgirish 227644961713Sgirish block_info_t reg_block[] = { 227744961713Sgirish {"PIO", PIO}, 227844961713Sgirish {"FZC_PIO", FZC_PIO}, 227944961713Sgirish {"FZC_XMAC", FZC_MAC}, 228044961713Sgirish {"FZC_IPP", FZC_IPP}, 228144961713Sgirish {"FFLP", FFLP}, 228244961713Sgirish {"FZC_FFLP", FZC_FFLP}, 228344961713Sgirish {"PIO_VADDR", PIO_VADDR}, 228444961713Sgirish {"ZCP", ZCP}, 228544961713Sgirish {"FZC_ZCP", FZC_ZCP}, 228644961713Sgirish {"DMC", DMC}, 228744961713Sgirish {"FZC_DMC", FZC_DMC}, 228844961713Sgirish {"TXC", TXC}, 228944961713Sgirish {"FZC_TXC", FZC_TXC}, 229044961713Sgirish {"PIO_LDSV", PIO_LDSV}, 229144961713Sgirish {"PIO_LDGIM", PIO_LDGIM}, 229244961713Sgirish {"PIO_IMASK0", PIO_IMASK0}, 229344961713Sgirish {"PIO_IMASK1", PIO_IMASK1}, 229444961713Sgirish {"FZC_PROM", FZC_PROM}, 229544961713Sgirish {"END", ALL_FF_32}, 229644961713Sgirish }; 229744961713Sgirish 229844961713Sgirish /* ARGSUSED */ 229944961713Sgirish static int 230044961713Sgirish nxge_param_dump_ptrs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 230144961713Sgirish { 2302a3c5bd6dSspeer uint_t print_len, buf_len; 2303a3c5bd6dSspeer p_mblk_t np; 2304a3c5bd6dSspeer int rdc, tdc, block; 2305a3c5bd6dSspeer uint64_t base; 230644961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 230744961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 2308a3c5bd6dSspeer int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_8K; 230944961713Sgirish p_tx_ring_t *tx_rings; 231044961713Sgirish p_rx_rcr_rings_t rx_rcr_rings; 231144961713Sgirish p_rx_rcr_ring_t *rcr_rings; 231244961713Sgirish p_rx_rbr_rings_t rx_rbr_rings; 231344961713Sgirish p_rx_rbr_ring_t *rbr_rings; 231444961713Sgirish 2315a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, IOC_CTL, 23164045d941Ssowmini "==> nxge_param_dump_ptrs")); 231744961713Sgirish 2318a3c5bd6dSspeer (void) mi_mpprintf(mp, "ptr information for Port\t %d \n", 23194045d941Ssowmini nxgep->function_num); 232044961713Sgirish 232144961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 232244961713Sgirish /* The following may work even if we cannot get a large buf. */ 232344961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 232444961713Sgirish return (0); 232544961713Sgirish } 232644961713Sgirish 232744961713Sgirish buf_len = buff_alloc_size; 232844961713Sgirish mp->b_cont = np; 232944961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 233044961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 233144961713Sgirish 233244961713Sgirish rx_rcr_rings = nxgep->rx_rcr_rings; 233344961713Sgirish rcr_rings = rx_rcr_rings->rcr_rings; 233444961713Sgirish rx_rbr_rings = nxgep->rx_rbr_rings; 233544961713Sgirish rbr_rings = rx_rbr_rings->rbr_rings; 233644961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 23374045d941Ssowmini "nxgep (nxge_t) $%p\n" 23384045d941Ssowmini "dev_regs (dev_regs_t) $%p\n", 23398793b36bSNick Todd (void *)nxgep, (void *)nxgep->dev_regs); 234044961713Sgirish 234144961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2342a3c5bd6dSspeer 2343a3c5bd6dSspeer /* do register pointers */ 234444961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 23454045d941Ssowmini "reg base (npi_reg_ptr_t) $%p\t " 23464045d941Ssowmini "pci reg (npi_reg_ptr_t) $%p\n", 23478793b36bSNick Todd (void *)nxgep->dev_regs->nxge_regp, 23488793b36bSNick Todd (void *)nxgep->dev_regs->nxge_pciregp); 234944961713Sgirish 235044961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 235144961713Sgirish 235244961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 23534045d941Ssowmini "\nBlock \t Offset \n"); 235444961713Sgirish 235544961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 235644961713Sgirish block = 0; 2357adfcba55Sjoycey #if defined(__i386) 2358adfcba55Sjoycey base = (uint64_t)(uint32_t)nxgep->dev_regs->nxge_regp; 2359adfcba55Sjoycey #else 236044961713Sgirish base = (uint64_t)nxgep->dev_regs->nxge_regp; 2361adfcba55Sjoycey #endif 236244961713Sgirish while (reg_block[block].offset != ALL_FF_32) { 236344961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 23644045d941Ssowmini "%9s\t 0x%llx\n", 23654045d941Ssowmini reg_block[block].name, 23664045d941Ssowmini (unsigned long long)(reg_block[block].offset + base)); 236744961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 236844961713Sgirish block++; 236944961713Sgirish } 237044961713Sgirish 237144961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 23724045d941Ssowmini "\nRDC\t rcrp (rx_rcr_ring_t)\t " 23734045d941Ssowmini "rbrp (rx_rbr_ring_t)\n"); 237444961713Sgirish 237544961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 237644961713Sgirish 237744961713Sgirish for (rdc = 0; rdc < p_cfgp->max_rdcs; rdc++) { 237844961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 23794045d941Ssowmini " %d\t $%p\t\t $%p\n", 23808793b36bSNick Todd rdc, (void *)rcr_rings[rdc], 23818793b36bSNick Todd (void *)rbr_rings[rdc]); 238244961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 238344961713Sgirish } 238444961713Sgirish 238544961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 23864045d941Ssowmini "\nTDC\t tdcp (tx_ring_t)\n"); 238744961713Sgirish 238844961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 238944961713Sgirish tx_rings = nxgep->tx_rings->rings; 2390678453a8Sspeer for (tdc = 0; tdc < p_cfgp->tdc.count; tdc++) { 239144961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 23928793b36bSNick Todd " %d\t $%p\n", tdc, (void *)tx_rings[tdc]); 239344961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 239444961713Sgirish } 239544961713Sgirish 2396a3c5bd6dSspeer print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, "\n\n"); 239744961713Sgirish 239844961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 239944961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ptrs")); 240044961713Sgirish return (0); 240144961713Sgirish } 240244961713Sgirish 240344961713Sgirish 240444961713Sgirish /* ARGSUSED */ 240544961713Sgirish int 240644961713Sgirish nxge_nd_get_names(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t param) 240744961713Sgirish { 2408a3c5bd6dSspeer ND *nd; 2409a3c5bd6dSspeer NDE *nde; 2410a3c5bd6dSspeer char *rwtag; 2411a3c5bd6dSspeer boolean_t get_ok, set_ok; 2412a3c5bd6dSspeer size_t param_len; 2413a3c5bd6dSspeer int status = 0; 241444961713Sgirish 241544961713Sgirish nd = (ND *)param; 241644961713Sgirish if (!nd) 241744961713Sgirish return (ENOENT); 241844961713Sgirish 241944961713Sgirish for (nde = nd->nd_tbl; nde->nde_name; nde++) { 242044961713Sgirish get_ok = (nde->nde_get_pfi != nxge_get_default) && 24214045d941Ssowmini (nde->nde_get_pfi != NULL); 242244961713Sgirish set_ok = (nde->nde_set_pfi != nxge_set_default) && 24234045d941Ssowmini (nde->nde_set_pfi != NULL); 242444961713Sgirish if (get_ok) { 242544961713Sgirish if (set_ok) 242644961713Sgirish rwtag = "read and write"; 242744961713Sgirish else 242844961713Sgirish rwtag = "read only"; 242944961713Sgirish } else if (set_ok) 243044961713Sgirish rwtag = "write only"; 243144961713Sgirish else { 243244961713Sgirish continue; 243344961713Sgirish } 243444961713Sgirish param_len = strlen(rwtag); 243544961713Sgirish param_len += strlen(nde->nde_name); 243644961713Sgirish param_len += 4; 243744961713Sgirish 243844961713Sgirish (void) mi_mpprintf(mp, "%s (%s)", nde->nde_name, rwtag); 243944961713Sgirish } 244044961713Sgirish return (status); 244144961713Sgirish } 244244961713Sgirish 244344961713Sgirish /* ARGSUSED */ 244444961713Sgirish int 244544961713Sgirish nxge_get_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t data) 244644961713Sgirish { 244744961713Sgirish return (EACCES); 244844961713Sgirish } 244944961713Sgirish 245044961713Sgirish /* ARGSUSED */ 245144961713Sgirish int 245244961713Sgirish nxge_set_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, char *value, 2453*fe054a6cSToomas Soome caddr_t data) 245444961713Sgirish { 245544961713Sgirish return (EACCES); 245644961713Sgirish } 245744961713Sgirish 24581bd6825cSml boolean_t 245944961713Sgirish nxge_param_link_update(p_nxge_t nxgep) 246044961713Sgirish { 246144961713Sgirish p_nxge_param_t param_arr; 246244961713Sgirish nxge_param_index_t i; 246344961713Sgirish boolean_t update_xcvr; 246444961713Sgirish boolean_t update_dev; 246544961713Sgirish int instance; 246644961713Sgirish boolean_t status = B_TRUE; 246744961713Sgirish 24681bd6825cSml NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_link_update")); 246944961713Sgirish 247044961713Sgirish param_arr = nxgep->param_arr; 247144961713Sgirish instance = nxgep->instance; 247244961713Sgirish update_xcvr = B_FALSE; 247344961713Sgirish for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) { 247444961713Sgirish update_xcvr |= param_arr[i].value; 247544961713Sgirish } 247644961713Sgirish 247744961713Sgirish if (update_xcvr) { 247844961713Sgirish update_xcvr = B_FALSE; 247944961713Sgirish for (i = param_autoneg; i < param_enable_ipg0; i++) { 248044961713Sgirish update_xcvr |= 24814045d941Ssowmini (param_arr[i].value != param_arr[i].old_value); 248244961713Sgirish param_arr[i].old_value = param_arr[i].value; 248344961713Sgirish } 248444961713Sgirish if (update_xcvr) { 24851bd6825cSml NXGE_DEBUG_MSG((nxgep, NDD_CTL, 24861bd6825cSml "==> nxge_param_link_update: update xcvr")); 248744961713Sgirish RW_ENTER_WRITER(&nxgep->filter_lock); 248844961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 248944961713Sgirish (void) nxge_link_init(nxgep); 249044961713Sgirish (void) nxge_mac_init(nxgep); 249144961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 249244961713Sgirish RW_EXIT(&nxgep->filter_lock); 249344961713Sgirish } 249444961713Sgirish } else { 249544961713Sgirish cmn_err(CE_WARN, " Last setting will leave nxge%d with " 24964045d941Ssowmini " no link capabilities.", instance); 249744961713Sgirish cmn_err(CE_WARN, " Restoring previous setting."); 249844961713Sgirish for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) 249944961713Sgirish param_arr[i].value = param_arr[i].old_value; 250044961713Sgirish } 2501a3c5bd6dSspeer 250244961713Sgirish update_dev = B_FALSE; 250344961713Sgirish 250444961713Sgirish if (update_dev) { 250544961713Sgirish RW_ENTER_WRITER(&nxgep->filter_lock); 25061bd6825cSml NXGE_DEBUG_MSG((nxgep, NDD_CTL, 25071bd6825cSml "==> nxge_param_link_update: update dev")); 250844961713Sgirish (void) nxge_rx_mac_disable(nxgep); 250944961713Sgirish (void) nxge_tx_mac_disable(nxgep); 251044961713Sgirish (void) nxge_tx_mac_enable(nxgep); 251144961713Sgirish (void) nxge_rx_mac_enable(nxgep); 251244961713Sgirish RW_EXIT(&nxgep->filter_lock); 251344961713Sgirish } 251444961713Sgirish 251544961713Sgirish nxge_param_hw_update_exit: 251644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 25174045d941Ssowmini "<== nxge_param_link_update status = 0x%08x", status)); 251844961713Sgirish return (status); 251944961713Sgirish } 25201bd6825cSml 25211bd6825cSml /* 25221bd6825cSml * synchronize the adv* and en* parameters. 25231bd6825cSml * 25241bd6825cSml * See comments in <sys/dld.h> for details of the *_en_* 25251bd6825cSml * parameters. The usage of ndd for setting adv parameters will 25261bd6825cSml * synchronize all the en parameters with the nxge parameters, 25271bd6825cSml * implicitly disabling any settings made via dladm. 25281bd6825cSml */ 25291bd6825cSml static void 25301bd6825cSml nxge_param_sync(p_nxge_t nxgep) 25311bd6825cSml { 25321bd6825cSml p_nxge_param_t param_arr; 25331bd6825cSml param_arr = nxgep->param_arr; 25341bd6825cSml 25351bd6825cSml nxgep->param_en_pause = param_arr[param_anar_pause].value; 25361bd6825cSml nxgep->param_en_1000fdx = param_arr[param_anar_1000fdx].value; 25371bd6825cSml nxgep->param_en_100fdx = param_arr[param_anar_100fdx].value; 25381bd6825cSml nxgep->param_en_10fdx = param_arr[param_anar_10fdx].value; 25391bd6825cSml } 25401bd6825cSml 25411bd6825cSml /* ARGSUSED */ 25421bd6825cSml int 25431bd6825cSml nxge_dld_get_ip_opt(p_nxge_t nxgep, caddr_t cp) 25441bd6825cSml { 25451bd6825cSml uint32_t status, cfg_value; 25461bd6825cSml p_nxge_param_t pa = (p_nxge_param_t)cp; 25471bd6825cSml tcam_class_t class; 25481bd6825cSml 25491bd6825cSml NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_dld_get_ip_opt")); 25501bd6825cSml 25511bd6825cSml /* do the actual hw setup */ 25521bd6825cSml class = nxge_class_name_2value(nxgep, pa->name); 25531bd6825cSml if (class == -1) 25541bd6825cSml return (EINVAL); 25551bd6825cSml 25561bd6825cSml cfg_value = 0; 25571bd6825cSml status = nxge_fflp_ip_class_config_get(nxgep, class, &cfg_value); 25581bd6825cSml if (status != NXGE_OK) 25591bd6825cSml return (EINVAL); 25601bd6825cSml 2561c1f9c6e5SSantwona Behera /* Filter out the allowed bits */ 2562c1f9c6e5SSantwona Behera cfg_value &= (NXGE_CLASS_FLOW_USE_PORTNUM | NXGE_CLASS_FLOW_USE_L2DA | 2563c1f9c6e5SSantwona Behera NXGE_CLASS_FLOW_USE_VLAN | NXGE_CLASS_FLOW_USE_PROTO | 2564c1f9c6e5SSantwona Behera NXGE_CLASS_FLOW_USE_IPSRC | NXGE_CLASS_FLOW_USE_IPDST | 2565c1f9c6e5SSantwona Behera NXGE_CLASS_FLOW_USE_SRC_PORT | NXGE_CLASS_FLOW_USE_DST_PORT); 2566c1f9c6e5SSantwona Behera 25671bd6825cSml NXGE_DEBUG_MSG((nxgep, NDD_CTL, 25681bd6825cSml "nxge_param_get_ip_opt_get %x ", cfg_value)); 25691bd6825cSml 25701bd6825cSml pa->value = cfg_value; 25711bd6825cSml 25721bd6825cSml NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_ip_opt status ")); 25731bd6825cSml return (0); 25741bd6825cSml } 2575