xref: /illumos-gate/usr/src/uts/common/io/nxge/nxge_ndd.c (revision c6e5ef56e2660bc334c7ecb747ea378a9a05101a)
144961713Sgirish /*
244961713Sgirish  * CDDL HEADER START
344961713Sgirish  *
444961713Sgirish  * The contents of this file are subject to the terms of the
544961713Sgirish  * Common Development and Distribution License (the "License").
644961713Sgirish  * You may not use this file except in compliance with the License.
744961713Sgirish  *
844961713Sgirish  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
944961713Sgirish  * or http://www.opensolaris.org/os/licensing.
1044961713Sgirish  * See the License for the specific language governing permissions
1144961713Sgirish  * and limitations under the License.
1244961713Sgirish  *
1344961713Sgirish  * When distributing Covered Code, include this CDDL HEADER in each
1444961713Sgirish  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1544961713Sgirish  * If applicable, add the following below this CDDL HEADER, with the
1644961713Sgirish  * fields enclosed by brackets "[]" replaced with your own identifying
1744961713Sgirish  * information: Portions Copyright [yyyy] [name of copyright owner]
1844961713Sgirish  *
1944961713Sgirish  * CDDL HEADER END
2044961713Sgirish  */
2144961713Sgirish /*
223d16f8e7Sml  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
2344961713Sgirish  * Use is subject to license terms.
2444961713Sgirish  */
2544961713Sgirish 
2644961713Sgirish #pragma ident	"%Z%%M%	%I%	%E% SMI"
2744961713Sgirish 
2844961713Sgirish #include <sys/nxge/nxge_impl.h>
29678453a8Sspeer #include <sys/nxge/nxge_hio.h>
30678453a8Sspeer 
3144961713Sgirish #include <inet/common.h>
3244961713Sgirish #include <inet/mi.h>
3344961713Sgirish #include <inet/nd.h>
3444961713Sgirish 
3544961713Sgirish extern uint64_t npi_debug_level;
3644961713Sgirish 
37a3c5bd6dSspeer #define	NXGE_PARAM_MAC_RW \
38a3c5bd6dSspeer 	NXGE_PARAM_RW | NXGE_PARAM_MAC | \
3944961713Sgirish 	NXGE_PARAM_NDD_WR_OK | NXGE_PARAM_READ_PROP
4044961713Sgirish 
41a3c5bd6dSspeer #define	NXGE_PARAM_MAC_DONT_SHOW \
42a3c5bd6dSspeer 	NXGE_PARAM_RW | NXGE_PARAM_MAC | NXGE_PARAM_DONT_SHOW
4344961713Sgirish 
44a3c5bd6dSspeer #define	NXGE_PARAM_RXDMA_RW \
45a3c5bd6dSspeer 	NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_NDD_WR_OK | \
46a3c5bd6dSspeer 	NXGE_PARAM_READ_PROP
4744961713Sgirish 
48a3c5bd6dSspeer #define	NXGE_PARAM_RXDMA_RWC \
49a3c5bd6dSspeer 	NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_INIT_ONLY | \
50a3c5bd6dSspeer 	NXGE_PARAM_READ_PROP
5144961713Sgirish 
52a3c5bd6dSspeer #define	NXGE_PARAM_L2CLASS_CFG \
53a3c5bd6dSspeer 	NXGE_PARAM_RW | NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_READ_PROP | \
54a3c5bd6dSspeer 	NXGE_PARAM_NDD_WR_OK
5544961713Sgirish 
56a3c5bd6dSspeer #define	NXGE_PARAM_CLASS_RWS \
57a3c5bd6dSspeer 	NXGE_PARAM_RWS |  NXGE_PARAM_READ_PROP
5844961713Sgirish 
5944961713Sgirish #define	NXGE_PARAM_ARRAY_INIT_SIZE	0x20ULL
6044961713Sgirish 
6144961713Sgirish #define	SET_RX_INTR_TIME_DISABLE 0
6244961713Sgirish #define	SET_RX_INTR_TIME_ENABLE 1
6344961713Sgirish #define	SET_RX_INTR_PKTS 2
6444961713Sgirish 
6544961713Sgirish #define	BASE_ANY	0
66a3c5bd6dSspeer #define	BASE_BINARY 	2
6744961713Sgirish #define	BASE_HEX	16
6844961713Sgirish #define	BASE_DECIMAL	10
6944961713Sgirish #define	ALL_FF_64	0xFFFFFFFFFFFFFFFFULL
7044961713Sgirish #define	ALL_FF_32	0xFFFFFFFFUL
7144961713Sgirish 
7244961713Sgirish #define	NXGE_NDD_INFODUMP_BUFF_SIZE	2048 /* is 2k enough? */
7344961713Sgirish #define	NXGE_NDD_INFODUMP_BUFF_8K	8192
7444961713Sgirish #define	NXGE_NDD_INFODUMP_BUFF_16K	0x2000
7544961713Sgirish #define	NXGE_NDD_INFODUMP_BUFF_64K	0x8000
7644961713Sgirish 
7744961713Sgirish #define	PARAM_OUTOF_RANGE(vptr, eptr, rval, pa)	\
7844961713Sgirish 	((vptr == eptr) || (rval < pa->minimum) || (rval > pa->maximum))
7944961713Sgirish 
8044961713Sgirish #define	ADVANCE_PRINT_BUFFER(pmp, plen, rlen) { \
8144961713Sgirish 	((mblk_t *)pmp)->b_wptr += plen; \
8244961713Sgirish 	rlen -= plen; \
83a3c5bd6dSspeer }
8444961713Sgirish 
854045d941Ssowmini int nxge_param_set_mac(p_nxge_t, queue_t *,
86a3c5bd6dSspeer 	mblk_t *, char *, caddr_t);
8744961713Sgirish static int nxge_param_set_port_rdc(p_nxge_t, queue_t *,
88a3c5bd6dSspeer 	mblk_t *, char *, caddr_t);
8944961713Sgirish static int nxge_param_set_grp_rdc(p_nxge_t, queue_t *,
90a3c5bd6dSspeer 	mblk_t *, char *, caddr_t);
9144961713Sgirish static int nxge_param_set_ether_usr(p_nxge_t,
92a3c5bd6dSspeer 	queue_t *, mblk_t *, char *, caddr_t);
9344961713Sgirish static int nxge_param_set_ip_usr(p_nxge_t,
94a3c5bd6dSspeer 	queue_t *, mblk_t *, char *, caddr_t);
9544961713Sgirish static int nxge_param_set_vlan_rdcgrp(p_nxge_t,
96a3c5bd6dSspeer 	queue_t *, mblk_t *, char *, caddr_t);
9744961713Sgirish static int nxge_param_set_mac_rdcgrp(p_nxge_t,
98a3c5bd6dSspeer 	queue_t *, mblk_t *, char *, caddr_t);
9944961713Sgirish static int nxge_param_fflp_hash_init(p_nxge_t,
100a3c5bd6dSspeer 	queue_t *, mblk_t *, char *, caddr_t);
10144961713Sgirish static int nxge_param_llc_snap_enable(p_nxge_t, queue_t *,
102a3c5bd6dSspeer 	mblk_t *, char *, caddr_t);
10344961713Sgirish static int nxge_param_hash_lookup_enable(p_nxge_t, queue_t *,
104a3c5bd6dSspeer 	mblk_t *, char *, caddr_t);
10544961713Sgirish static int nxge_param_tcam_enable(p_nxge_t, queue_t *,
106a3c5bd6dSspeer 	mblk_t *, char *, caddr_t);
10756d930aeSspeer static int nxge_param_get_fw_ver(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
1082e59129aSraghus static int nxge_param_get_port_mode(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
10944961713Sgirish static int nxge_param_get_rxdma_info(p_nxge_t, queue_t *q,
110a3c5bd6dSspeer 	p_mblk_t, caddr_t);
11144961713Sgirish static int nxge_param_get_txdma_info(p_nxge_t, queue_t *q,
112a3c5bd6dSspeer 	p_mblk_t, caddr_t);
11344961713Sgirish static int nxge_param_get_vlan_rdcgrp(p_nxge_t, queue_t *,
114a3c5bd6dSspeer 	p_mblk_t, caddr_t);
11544961713Sgirish static int nxge_param_get_mac_rdcgrp(p_nxge_t, queue_t *,
116a3c5bd6dSspeer 	p_mblk_t, caddr_t);
11744961713Sgirish static int nxge_param_get_rxdma_rdcgrp_info(p_nxge_t, queue_t *,
118a3c5bd6dSspeer 	p_mblk_t, caddr_t);
11944961713Sgirish static int nxge_param_get_ip_opt(p_nxge_t, queue_t *, mblk_t *, caddr_t);
120a3c5bd6dSspeer static int nxge_param_get_mac(p_nxge_t, queue_t *q, p_mblk_t, caddr_t);
12144961713Sgirish static int nxge_param_get_debug_flag(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
12244961713Sgirish static int nxge_param_set_nxge_debug_flag(p_nxge_t, queue_t *, mblk_t *,
123a3c5bd6dSspeer 	char *, caddr_t);
12444961713Sgirish static int nxge_param_set_npi_debug_flag(p_nxge_t,
125a3c5bd6dSspeer 	queue_t *, mblk_t *, char *, caddr_t);
12644961713Sgirish static int nxge_param_dump_rdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t);
12744961713Sgirish static int nxge_param_dump_tdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t);
12844961713Sgirish static int nxge_param_dump_mac_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
12944961713Sgirish static int nxge_param_dump_ipp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
13044961713Sgirish static int nxge_param_dump_fflp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
13144961713Sgirish static int nxge_param_dump_vlan_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
13244961713Sgirish static int nxge_param_dump_rdc_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
13344961713Sgirish static int nxge_param_dump_ptrs(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
1341bd6825cSml static void nxge_param_sync(p_nxge_t);
13544961713Sgirish 
13644961713Sgirish /*
13744961713Sgirish  * Global array of Neptune changable parameters.
13844961713Sgirish  * This array is initialized to correspond to the default
13944961713Sgirish  * Neptune 4 port configuration. This array would be copied
14044961713Sgirish  * into each port's parameter structure and modifed per
14144961713Sgirish  * fcode and nxge.conf configuration. Later, the parameters are
14244961713Sgirish  * exported to ndd to display and run-time configuration (at least
14344961713Sgirish  * some of them).
14444961713Sgirish  *
14500161856Syc  * Parameters with DONT_SHOW are not shown by ndd.
14600161856Syc  *
14744961713Sgirish  */
14844961713Sgirish 
149a3c5bd6dSspeer static nxge_param_t	nxge_param_arr[] = {
150a3c5bd6dSspeer 	/*
151a3c5bd6dSspeer 	 * min	max	value	old	hw-name	conf-name
152a3c5bd6dSspeer 	 */
153846a903dSml 	{ nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW,
154a3c5bd6dSspeer 		0, 999, 1000, 0, "instance", "instance"},
155a3c5bd6dSspeer 
156846a903dSml 	{ nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW,
157a3c5bd6dSspeer 		0, 999, 1000, 0, "main-instance", "main_instance"},
158a3c5bd6dSspeer 
159a3c5bd6dSspeer 	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ,
160a3c5bd6dSspeer 		0, 3, 0, 0, "function-number", "function_number"},
161a3c5bd6dSspeer 
162a3c5bd6dSspeer 	/* Partition Id */
163846a903dSml 	{ nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW,
164a3c5bd6dSspeer 		0, 8, 0, 0, "partition-id", "partition_id"},
165a3c5bd6dSspeer 
166a3c5bd6dSspeer 	/* Read Write Permission Mode */
167846a903dSml 	{ nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW,
168a3c5bd6dSspeer 		0, 2, 0, 0, "read-write-mode", "read_write_mode"},
169a3c5bd6dSspeer 
17056d930aeSspeer 	{ nxge_param_get_fw_ver, NULL, NXGE_PARAM_READ,
17156d930aeSspeer 		0, 32, 0, 0, "version",	"fw_version"},
17256d930aeSspeer 
1732e59129aSraghus 	{ nxge_param_get_port_mode, NULL, NXGE_PARAM_READ,
1742e59129aSraghus 		0, 32, 0, 0, "port-mode", "port_mode"},
1752e59129aSraghus 
176a3c5bd6dSspeer 	/* hw cfg types */
177a3c5bd6dSspeer 	/* control the DMA config of Neptune/NIU */
178846a903dSml 	{ nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW,
179a3c5bd6dSspeer 		CFG_DEFAULT, CFG_CUSTOM, CFG_DEFAULT, CFG_DEFAULT,
180a3c5bd6dSspeer 		"niu-cfg-type", "niu_cfg_type"},
181a3c5bd6dSspeer 
182a3c5bd6dSspeer 	/* control the TXDMA config of the Port controlled by tx-quick-cfg */
183846a903dSml 	{ nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW,
184a3c5bd6dSspeer 		CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT,
185a3c5bd6dSspeer 		"tx-qcfg-type", "tx_qcfg_type"},
186a3c5bd6dSspeer 
187a3c5bd6dSspeer 	/* control the RXDMA config of the Port controlled by rx-quick-cfg */
188846a903dSml 	{ nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW,
189a3c5bd6dSspeer 		CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT,
190a3c5bd6dSspeer 		"rx-qcfg-type", "rx_qcfg_type"},
191a3c5bd6dSspeer 
192a3c5bd6dSspeer 	{ nxge_param_get_mac, nxge_param_set_mac,
193a3c5bd6dSspeer 		NXGE_PARAM_RW  | NXGE_PARAM_DONT_SHOW,
194a3c5bd6dSspeer 		0, 1, 0, 0, "master-cfg-enable", "master_cfg_enable"},
195a3c5bd6dSspeer 
196a3c5bd6dSspeer 	{ nxge_param_get_mac, nxge_param_set_mac,
197846a903dSml 		NXGE_PARAM_DONT_SHOW,
198a3c5bd6dSspeer 		0, 1, 0, 0, "master-cfg-value", "master_cfg_value"},
199a3c5bd6dSspeer 
200a3c5bd6dSspeer 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW,
201a3c5bd6dSspeer 		0, 1, 1, 1, "adv-autoneg-cap", "adv_autoneg_cap"},
202a3c5bd6dSspeer 
203a3c5bd6dSspeer 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW,
204a3c5bd6dSspeer 		0, 1, 1, 1, "adv-10gfdx-cap", "adv_10gfdx_cap"},
205a3c5bd6dSspeer 
206a3c5bd6dSspeer 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW,
207a3c5bd6dSspeer 		0, 1, 0, 0, "adv-10ghdx-cap", "adv_10ghdx_cap"},
208a3c5bd6dSspeer 
209a3c5bd6dSspeer 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW,
210a3c5bd6dSspeer 		0, 1, 1, 1, "adv-1000fdx-cap", "adv_1000fdx_cap"},
211a3c5bd6dSspeer 
212a3c5bd6dSspeer 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW,
213a3c5bd6dSspeer 		0, 1, 0, 0, "adv-1000hdx-cap",	"adv_1000hdx_cap"},
214a3c5bd6dSspeer 
215a3c5bd6dSspeer 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW,
216a3c5bd6dSspeer 		0, 1, 0, 0, "adv-100T4-cap", "adv_100T4_cap"},
217a3c5bd6dSspeer 
218a3c5bd6dSspeer 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW,
219a3c5bd6dSspeer 		0, 1, 1, 1, "adv-100fdx-cap", "adv_100fdx_cap"},
220a3c5bd6dSspeer 
221a3c5bd6dSspeer 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW,
222a3c5bd6dSspeer 		0, 1, 0, 0, "adv-100hdx-cap", "adv_100hdx_cap"},
223a3c5bd6dSspeer 
224a3c5bd6dSspeer 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW,
225a3c5bd6dSspeer 		0, 1, 1, 1, "adv-10fdx-cap", "adv_10fdx_cap"},
226a3c5bd6dSspeer 
227a3c5bd6dSspeer 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW,
228a3c5bd6dSspeer 		0, 1, 0, 0, "adv-10hdx-cap", "adv_10hdx_cap"},
229a3c5bd6dSspeer 
230846a903dSml 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW,
231a3c5bd6dSspeer 		0, 1, 0, 0, "adv-asmpause-cap",	"adv_asmpause_cap"},
232a3c5bd6dSspeer 
233a3c5bd6dSspeer 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW,
234a3c5bd6dSspeer 		0, 1, 0, 0, "adv-pause-cap", "adv_pause_cap"},
235a3c5bd6dSspeer 
236846a903dSml 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW,
237a3c5bd6dSspeer 		0, 1, 0, 0, "use-int-xcvr", "use_int_xcvr"},
238a3c5bd6dSspeer 
239846a903dSml 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW,
240a3c5bd6dSspeer 		0, 1, 1, 1, "enable-ipg0", "enable_ipg0"},
241a3c5bd6dSspeer 
242846a903dSml 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW,
243a3c5bd6dSspeer 		0, 255,	8, 8, "ipg0", "ipg0"},
244a3c5bd6dSspeer 
245846a903dSml 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW,
246a3c5bd6dSspeer 		0, 255,	8, 8, "ipg1", "ipg1"},
247a3c5bd6dSspeer 
248846a903dSml 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW,
249a3c5bd6dSspeer 		0, 255,	4, 4, "ipg2", "ipg2"},
250a3c5bd6dSspeer 
251a3c5bd6dSspeer 	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW,
252a3c5bd6dSspeer 		0, 1, 0, 0, "accept-jumbo", "accept_jumbo"},
253a3c5bd6dSspeer 
254a3c5bd6dSspeer 	/* Transmit DMA channels */
255846a903dSml 	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ |
256846a903dSml 		NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
257a3c5bd6dSspeer 		0, 3, 0, 0, "tx-dma-weight", "tx_dma_weight"},
258a3c5bd6dSspeer 
259846a903dSml 	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ |
260846a903dSml 		NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
261a3c5bd6dSspeer 		0, 31, 0, 0, "tx-dma-channels-begin", "tx_dma_channels_begin"},
262a3c5bd6dSspeer 
263846a903dSml 	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ |
264846a903dSml 		NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
265a3c5bd6dSspeer 		0, 32, 0, 0, "tx-dma-channels", "tx_dma_channels"},
266a3c5bd6dSspeer 	{ nxge_param_get_txdma_info, NULL,
267846a903dSml 		NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
268a3c5bd6dSspeer 		0, 32, 0, 0, "tx-dma-info", "tx_dma_info"},
269a3c5bd6dSspeer 
270a3c5bd6dSspeer 	/* Receive DMA channels */
271a3c5bd6dSspeer 	{ nxge_param_get_generic, NULL,
272846a903dSml 		NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
273a3c5bd6dSspeer 		0, 31, 0, 0, "rx-dma-channels-begin", "rx_dma_channels_begin"},
274a3c5bd6dSspeer 
275846a903dSml 	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ |
276846a903dSml 		NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
277a3c5bd6dSspeer 		0, 32, 0, 0, "rx-dma-channels",	"rx_dma_channels"},
278a3c5bd6dSspeer 
279846a903dSml 	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ |
280846a903dSml 		NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
281a3c5bd6dSspeer 		0, 65535, PT_DRR_WT_DEFAULT_10G, 0,
282a3c5bd6dSspeer 		"rx-drr-weight", "rx_drr_weight"},
283a3c5bd6dSspeer 
284846a903dSml 	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ |
285846a903dSml 		NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
286a3c5bd6dSspeer 		0, 1, 1, 0, "rx-full-header", "rx_full_header"},
287a3c5bd6dSspeer 
288846a903dSml 	{ nxge_param_get_rxdma_info, NULL, NXGE_PARAM_READ |
289846a903dSml 		NXGE_PARAM_DONT_SHOW,
290a3c5bd6dSspeer 		0, 32, 0, 0, "rx-dma-info", "rx_dma_info"},
291a3c5bd6dSspeer 
292a3c5bd6dSspeer 	{ nxge_param_get_rxdma_info, NULL,
293a3c5bd6dSspeer 		NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW,
294a3c5bd6dSspeer 		NXGE_RBR_RBB_MIN, NXGE_RBR_RBB_MAX, NXGE_RBR_RBB_DEFAULT, 0,
295a3c5bd6dSspeer 		"rx-rbr-size", "rx_rbr_size"},
296a3c5bd6dSspeer 
297a3c5bd6dSspeer 	{ nxge_param_get_rxdma_info, NULL,
298a3c5bd6dSspeer 		NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW,
299a3c5bd6dSspeer 		NXGE_RCR_MIN, NXGE_RCR_MAX, NXGE_RCR_DEFAULT, 0,
300a3c5bd6dSspeer 		"rx-rcr-size", "rx_rcr_size"},
301a3c5bd6dSspeer 
302846a903dSml 	{ nxge_param_get_generic, nxge_param_set_port_rdc,
303846a903dSml 		NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
304a3c5bd6dSspeer 		0, 15, 0, 0, "default-port-rdc", "default_port_rdc"},
305a3c5bd6dSspeer 
306a3c5bd6dSspeer 	{ nxge_param_get_generic, nxge_param_rx_intr_time, NXGE_PARAM_RXDMA_RW,
307a3c5bd6dSspeer 		NXGE_RDC_RCR_TIMEOUT_MIN, NXGE_RDC_RCR_TIMEOUT_MAX,
308a3c5bd6dSspeer 		RXDMA_RCR_TO_DEFAULT, 0, "rxdma-intr-time", "rxdma_intr_time"},
309a3c5bd6dSspeer 
310a3c5bd6dSspeer 	{ nxge_param_get_generic, nxge_param_rx_intr_pkts, NXGE_PARAM_RXDMA_RW,
311a3c5bd6dSspeer 		NXGE_RDC_RCR_THRESHOLD_MIN, NXGE_RDC_RCR_THRESHOLD_MAX,
312a3c5bd6dSspeer 		RXDMA_RCR_PTHRES_DEFAULT, 0,
313a3c5bd6dSspeer 		"rxdma-intr-pkts", "rxdma_intr_pkts"},
314a3c5bd6dSspeer 
315846a903dSml 	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP |
316846a903dSml 		NXGE_PARAM_DONT_SHOW,
317a3c5bd6dSspeer 		0, 8, 0, 0, "rx-rdc-grps-begin", "rx_rdc_grps_begin"},
318a3c5bd6dSspeer 
319846a903dSml 	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP |
320846a903dSml 		NXGE_PARAM_DONT_SHOW,
321a3c5bd6dSspeer 		0, 8, 0, 0, "rx-rdc-grps", "rx_rdc_grps"},
322a3c5bd6dSspeer 
323846a903dSml 	{ nxge_param_get_generic, nxge_param_set_grp_rdc,
324846a903dSml 		NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
325a3c5bd6dSspeer 		0, 15, 0, 0, "default-grp0-rdc", "default_grp0_rdc"},
326a3c5bd6dSspeer 
327846a903dSml 	{ nxge_param_get_generic, nxge_param_set_grp_rdc,
328846a903dSml 		NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
329a3c5bd6dSspeer 		0, 15,	2, 0, "default-grp1-rdc", "default_grp1_rdc"},
330a3c5bd6dSspeer 
331846a903dSml 	{ nxge_param_get_generic, nxge_param_set_grp_rdc,
332846a903dSml 		NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
333a3c5bd6dSspeer 		0, 15, 4, 0, "default-grp2-rdc", "default_grp2_rdc"},
334a3c5bd6dSspeer 
335846a903dSml 	{ nxge_param_get_generic, nxge_param_set_grp_rdc,
336846a903dSml 		NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
337a3c5bd6dSspeer 		0, 15, 6, 0, "default-grp3-rdc", "default_grp3_rdc"},
338a3c5bd6dSspeer 
339846a903dSml 	{ nxge_param_get_generic, nxge_param_set_grp_rdc,
340846a903dSml 		NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
341a3c5bd6dSspeer 		0, 15, 8, 0, "default-grp4-rdc", "default_grp4_rdc"},
342a3c5bd6dSspeer 
343846a903dSml 	{ nxge_param_get_generic, nxge_param_set_grp_rdc,
344846a903dSml 		NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
345a3c5bd6dSspeer 		0, 15, 10, 0, "default-grp5-rdc", "default_grp5_rdc"},
346a3c5bd6dSspeer 
347846a903dSml 	{ nxge_param_get_generic, nxge_param_set_grp_rdc,
348846a903dSml 		NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
349a3c5bd6dSspeer 		0, 15, 12, 0, "default-grp6-rdc", "default_grp6_rdc"},
350a3c5bd6dSspeer 
351846a903dSml 	{ nxge_param_get_generic, nxge_param_set_grp_rdc,
352846a903dSml 		NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
353a3c5bd6dSspeer 		0, 15, 14, 0, "default-grp7-rdc", "default_grp7_rdc"},
354a3c5bd6dSspeer 
355a3c5bd6dSspeer 	{ nxge_param_get_rxdma_rdcgrp_info, NULL,
356846a903dSml 		NXGE_PARAM_READ | NXGE_PARAM_CMPLX | NXGE_PARAM_DONT_SHOW,
357a3c5bd6dSspeer 		0, 8, 0, 0, "rdc-groups-info", "rdc_groups_info"},
358a3c5bd6dSspeer 
359a3c5bd6dSspeer 	/* Logical device groups */
360846a903dSml 	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW,
361a3c5bd6dSspeer 		0, 63, 0, 0, "start-ldg", "start_ldg"},
362a3c5bd6dSspeer 
363846a903dSml 	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW,
364a3c5bd6dSspeer 		0, 64, 0, 0, "max-ldg", "max_ldg" },
365a3c5bd6dSspeer 
366a3c5bd6dSspeer 	/* MAC table information */
367a3c5bd6dSspeer 	{ nxge_param_get_mac_rdcgrp, nxge_param_set_mac_rdcgrp,
368846a903dSml 		NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW,
369a3c5bd6dSspeer 		0, 31, 0, 0, "mac-2rdc-grp", "mac_2rdc_grp"},
370a3c5bd6dSspeer 
371a3c5bd6dSspeer 	/* VLAN table information */
372a3c5bd6dSspeer 	{ nxge_param_get_vlan_rdcgrp, nxge_param_set_vlan_rdcgrp,
373846a903dSml 		NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW,
374a3c5bd6dSspeer 		0, 31, 0, 0, "vlan-2rdc-grp", "vlan_2rdc_grp"},
375a3c5bd6dSspeer 
376a3c5bd6dSspeer 	{ nxge_param_get_generic, NULL,
377846a903dSml 		NXGE_PARAM_READ_PROP | NXGE_PARAM_READ |
378846a903dSml 		NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_DONT_SHOW,
379a3c5bd6dSspeer 		0, 0x0ffff, 0x0ffff, 0, "fcram-part-cfg", "fcram_part_cfg"},
380a3c5bd6dSspeer 
381846a903dSml 	{ nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS |
382846a903dSml 		NXGE_PARAM_DONT_SHOW,
383a3c5bd6dSspeer 		0, 0x10, 0xa, 0, "fcram-access-ratio", "fcram_access_ratio"},
384a3c5bd6dSspeer 
385846a903dSml 	{ nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS |
386846a903dSml 		NXGE_PARAM_DONT_SHOW,
387a3c5bd6dSspeer 		0, 0x10, 0xa, 0, "tcam-access-ratio", "tcam_access_ratio"},
388a3c5bd6dSspeer 
389a3c5bd6dSspeer 	{ nxge_param_get_generic, nxge_param_tcam_enable,
390846a903dSml 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
391a3c5bd6dSspeer 		0, 0x1, 0x0, 0, "tcam-enable", "tcam_enable"},
392a3c5bd6dSspeer 
393a3c5bd6dSspeer 	{ nxge_param_get_generic, nxge_param_hash_lookup_enable,
394846a903dSml 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
395a3c5bd6dSspeer 		0, 0x01, 0x0, 0, "hash-lookup-enable", "hash_lookup_enable"},
396a3c5bd6dSspeer 
397a3c5bd6dSspeer 	{ nxge_param_get_generic, nxge_param_llc_snap_enable,
398846a903dSml 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
399a3c5bd6dSspeer 		0, 0x01, 0x01, 0, "llc-snap-enable", "llc_snap_enable"},
400a3c5bd6dSspeer 
401a3c5bd6dSspeer 	{ nxge_param_get_generic, nxge_param_fflp_hash_init,
402846a903dSml 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
403a3c5bd6dSspeer 		0, ALL_FF_32, ALL_FF_32, 0, "h1-init-value", "h1_init_value"},
404a3c5bd6dSspeer 
405a3c5bd6dSspeer 	{ nxge_param_get_generic,	nxge_param_fflp_hash_init,
406846a903dSml 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
407a3c5bd6dSspeer 		0, 0x0ffff, 0x0ffff, 0, "h2-init-value", "h2_init_value"},
408a3c5bd6dSspeer 
409a3c5bd6dSspeer 	{ nxge_param_get_generic, nxge_param_set_ether_usr,
410a3c5bd6dSspeer 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
411a3c5bd6dSspeer 		0, ALL_FF_32, 0x0, 0,
412a3c5bd6dSspeer 		"class-cfg-ether-usr1", "class_cfg_ether_usr1"},
413a3c5bd6dSspeer 
414a3c5bd6dSspeer 	{ nxge_param_get_generic, nxge_param_set_ether_usr,
415a3c5bd6dSspeer 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
416a3c5bd6dSspeer 		0, ALL_FF_32, 0x0, 0,
417a3c5bd6dSspeer 		"class-cfg-ether-usr2", "class_cfg_ether_usr2"},
418a3c5bd6dSspeer 
419a3c5bd6dSspeer 	{ nxge_param_get_generic, nxge_param_set_ip_usr,
420a3c5bd6dSspeer 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
421a3c5bd6dSspeer 		0, ALL_FF_32, 0x0, 0,
422a3c5bd6dSspeer 		"class-cfg-ip-usr4", "class_cfg_ip_usr4"},
423a3c5bd6dSspeer 
424a3c5bd6dSspeer 	{ nxge_param_get_generic, nxge_param_set_ip_usr,
425a3c5bd6dSspeer 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
426a3c5bd6dSspeer 		0, ALL_FF_32, 0x0, 0,
427a3c5bd6dSspeer 		"class-cfg-ip-usr5", "class_cfg_ip_usr5"},
428a3c5bd6dSspeer 
429a3c5bd6dSspeer 	{ nxge_param_get_generic, nxge_param_set_ip_usr,
430a3c5bd6dSspeer 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
431a3c5bd6dSspeer 		0, ALL_FF_32, 0x0, 0,
432a3c5bd6dSspeer 		"class-cfg-ip-usr6", "class_cfg_ip_usr6"},
433a3c5bd6dSspeer 
434a3c5bd6dSspeer 	{ nxge_param_get_generic, nxge_param_set_ip_usr,
435a3c5bd6dSspeer 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
436a3c5bd6dSspeer 		0, ALL_FF_32, 0x0, 0,
437a3c5bd6dSspeer 		"class-cfg-ip-usr7", "class_cfg_ip_usr7"},
438a3c5bd6dSspeer 
439a3c5bd6dSspeer 	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt,
440a3c5bd6dSspeer 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
441a3c5bd6dSspeer 		0, ALL_FF_32, 0x0, 0,
442a3c5bd6dSspeer 		"class-opt-ip-usr4", "class_opt_ip_usr4"},
443a3c5bd6dSspeer 
444a3c5bd6dSspeer 	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt,
445a3c5bd6dSspeer 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
446a3c5bd6dSspeer 		0, ALL_FF_32, 0x0, 0,
447a3c5bd6dSspeer 		"class-opt-ip-usr5", "class_opt_ip_usr5"},
448a3c5bd6dSspeer 
449a3c5bd6dSspeer 	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt,
450a3c5bd6dSspeer 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
451a3c5bd6dSspeer 		0, ALL_FF_32, 0x0, 0,
452a3c5bd6dSspeer 		"class-opt-ip-usr6", "class_opt_ip_usr6"},
453a3c5bd6dSspeer 
454a3c5bd6dSspeer 	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt,
455a3c5bd6dSspeer 		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
456a3c5bd6dSspeer 		0, ALL_FF_32, 0x0, 0,
457a3c5bd6dSspeer 		"class-opt-ip-usr7", "class_opt_ip_usr7"},
458a3c5bd6dSspeer 
459a3c5bd6dSspeer 	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt,
460a3c5bd6dSspeer 		NXGE_PARAM_CLASS_RWS,
461a3c5bd6dSspeer 		0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
462a3c5bd6dSspeer 		"class-opt-ipv4-tcp", "class_opt_ipv4_tcp"},
463a3c5bd6dSspeer 
464a3c5bd6dSspeer 	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt,
465a3c5bd6dSspeer 		NXGE_PARAM_CLASS_RWS,
466a3c5bd6dSspeer 		0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
467a3c5bd6dSspeer 		"class-opt-ipv4-udp", "class_opt_ipv4_udp"},
468a3c5bd6dSspeer 
469a3c5bd6dSspeer 	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt,
470a3c5bd6dSspeer 		NXGE_PARAM_CLASS_RWS,
471a3c5bd6dSspeer 		0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
472a3c5bd6dSspeer 		"class-opt-ipv4-ah", "class_opt_ipv4_ah"},
473a3c5bd6dSspeer 
474a3c5bd6dSspeer 	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt,
475a3c5bd6dSspeer 		NXGE_PARAM_CLASS_RWS,
476a3c5bd6dSspeer 		0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
477a3c5bd6dSspeer 		"class-opt-ipv4-sctp", "class_opt_ipv4_sctp"},
478a3c5bd6dSspeer 
479a3c5bd6dSspeer 	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS,
480a3c5bd6dSspeer 		0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
481a3c5bd6dSspeer 		"class-opt-ipv6-tcp", "class_opt_ipv6_tcp"},
482a3c5bd6dSspeer 
483a3c5bd6dSspeer 	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS,
484a3c5bd6dSspeer 		0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
485a3c5bd6dSspeer 		"class-opt-ipv6-udp", "class_opt_ipv6_udp"},
486a3c5bd6dSspeer 
487a3c5bd6dSspeer 	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS,
488a3c5bd6dSspeer 		0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
489a3c5bd6dSspeer 		"class-opt-ipv6-ah", "class_opt_ipv6_ah"},
490a3c5bd6dSspeer 
491a3c5bd6dSspeer 	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS,
492a3c5bd6dSspeer 		0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
493a3c5bd6dSspeer 		"class-opt-ipv6-sctp",	"class_opt_ipv6_sctp"},
494a3c5bd6dSspeer 
495a3c5bd6dSspeer 	{ nxge_param_get_debug_flag, nxge_param_set_nxge_debug_flag,
496846a903dSml 		NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW,
497a3c5bd6dSspeer 		0ULL, ALL_FF_64, 0ULL, 0ULL,
498a3c5bd6dSspeer 		"nxge-debug-flag", "nxge_debug_flag"},
499a3c5bd6dSspeer 
500a3c5bd6dSspeer 	{ nxge_param_get_debug_flag, nxge_param_set_npi_debug_flag,
501846a903dSml 		NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW,
502a3c5bd6dSspeer 		0ULL, ALL_FF_64, 0ULL, 0ULL,
503a3c5bd6dSspeer 		"npi-debug-flag", "npi_debug_flag"},
504a3c5bd6dSspeer 
505846a903dSml 	{ nxge_param_dump_tdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW,
506a3c5bd6dSspeer 		0, 0x0fffffff, 0x0fffffff, 0, "dump-tdc", "dump_tdc"},
507a3c5bd6dSspeer 
508846a903dSml 	{ nxge_param_dump_rdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW,
509a3c5bd6dSspeer 		0, 0x0fffffff, 0x0fffffff, 0, "dump-rdc", "dump_rdc"},
510a3c5bd6dSspeer 
511846a903dSml 	{ nxge_param_dump_mac_regs, NULL, NXGE_PARAM_READ |
512846a903dSml 		NXGE_PARAM_DONT_SHOW,
513a3c5bd6dSspeer 		0, 0x0fffffff, 0x0fffffff, 0, "dump-mac-regs", "dump_mac_regs"},
514a3c5bd6dSspeer 
515846a903dSml 	{ nxge_param_dump_ipp_regs, NULL, NXGE_PARAM_READ |
516846a903dSml 		NXGE_PARAM_DONT_SHOW,
517a3c5bd6dSspeer 		0, 0x0fffffff, 0x0fffffff, 0, "dump-ipp-regs", "dump_ipp_regs"},
518a3c5bd6dSspeer 
519846a903dSml 	{ nxge_param_dump_fflp_regs, NULL, NXGE_PARAM_READ |
520846a903dSml 		NXGE_PARAM_DONT_SHOW,
521a3c5bd6dSspeer 		0, 0x0fffffff, 0x0fffffff, 0,
522a3c5bd6dSspeer 		"dump-fflp-regs", "dump_fflp_regs"},
523a3c5bd6dSspeer 
524846a903dSml 	{ nxge_param_dump_vlan_table, NULL, NXGE_PARAM_READ |
525846a903dSml 		NXGE_PARAM_DONT_SHOW,
526a3c5bd6dSspeer 		0, 0x0fffffff, 0x0fffffff, 0,
527a3c5bd6dSspeer 		"dump-vlan-table", "dump_vlan_table"},
528a3c5bd6dSspeer 
529846a903dSml 	{ nxge_param_dump_rdc_table, NULL, NXGE_PARAM_READ |
530846a903dSml 		NXGE_PARAM_DONT_SHOW,
531a3c5bd6dSspeer 		0, 0x0fffffff, 0x0fffffff, 0,
532a3c5bd6dSspeer 		"dump-rdc-table", "dump_rdc_table"},
533a3c5bd6dSspeer 
534846a903dSml 	{ nxge_param_dump_ptrs,	NULL, NXGE_PARAM_READ |
535846a903dSml 		NXGE_PARAM_DONT_SHOW,
536a3c5bd6dSspeer 		0, 0x0fffffff, 0x0fffffff, 0, "dump-ptrs", "dump_ptrs"},
537a3c5bd6dSspeer 
538a3c5bd6dSspeer 	{  NULL, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW,
539a3c5bd6dSspeer 		0, 0x0fffffff, 0x0fffffff, 0, "end", "end"},
54044961713Sgirish };
54144961713Sgirish 
54244961713Sgirish extern void 		*nxge_list;
54344961713Sgirish 
54444961713Sgirish void
54544961713Sgirish nxge_get_param_soft_properties(p_nxge_t nxgep)
54644961713Sgirish {
54744961713Sgirish 
54844961713Sgirish 	p_nxge_param_t 		param_arr;
54944961713Sgirish 	uint_t 			prop_len;
55044961713Sgirish 	int 			i, j;
551a3c5bd6dSspeer 	uint32_t		param_count;
552a3c5bd6dSspeer 	uint32_t		*int_prop_val;
55344961713Sgirish 
55444961713Sgirish 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, " ==> nxge_get_param_soft_properties"));
55544961713Sgirish 
55644961713Sgirish 	param_arr = nxgep->param_arr;
55744961713Sgirish 	param_count = nxgep->param_count;
55844961713Sgirish 	for (i = 0; i < param_count; i++) {
55944961713Sgirish 		if ((param_arr[i].type & NXGE_PARAM_READ_PROP) == 0)
56044961713Sgirish 			continue;
56144961713Sgirish 		if ((param_arr[i].type & NXGE_PARAM_PROP_STR))
56244961713Sgirish 			continue;
56344961713Sgirish 		if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) ||
5644045d941Ssowmini 		    (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) {
56544961713Sgirish 			if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY,
5664045d941Ssowmini 			    nxgep->dip, 0, param_arr[i].fcode_name,
5674045d941Ssowmini 			    (int **)&int_prop_val,
5684045d941Ssowmini 			    (uint_t *)&prop_len)
5694045d941Ssowmini 			    == DDI_PROP_SUCCESS) {
57044961713Sgirish 				uint32_t *cfg_value;
57144961713Sgirish 				uint64_t prop_count;
572a3c5bd6dSspeer 
57344961713Sgirish 				if (prop_len > NXGE_PARAM_ARRAY_INIT_SIZE)
57444961713Sgirish 					prop_len = NXGE_PARAM_ARRAY_INIT_SIZE;
575adfcba55Sjoycey #if defined(__i386)
576adfcba55Sjoycey 				cfg_value =
5774045d941Ssowmini 				    (uint32_t *)(int32_t)param_arr[i].value;
578adfcba55Sjoycey #else
57944961713Sgirish 				cfg_value = (uint32_t *)param_arr[i].value;
580adfcba55Sjoycey #endif
58144961713Sgirish 				for (j = 0; j < prop_len; j++) {
58244961713Sgirish 					cfg_value[j] = int_prop_val[j];
58344961713Sgirish 				}
58444961713Sgirish 				prop_count = prop_len;
58544961713Sgirish 				param_arr[i].type |=
58644961713Sgirish 				    (prop_count << NXGE_PARAM_ARRAY_CNT_SHIFT);
58744961713Sgirish 				ddi_prop_free(int_prop_val);
58844961713Sgirish 			}
58944961713Sgirish 			continue;
59044961713Sgirish 		}
59144961713Sgirish 
59244961713Sgirish 		if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0,
5934045d941Ssowmini 		    param_arr[i].fcode_name,
5944045d941Ssowmini 		    (int **)&int_prop_val,
5954045d941Ssowmini 		    &prop_len) == DDI_PROP_SUCCESS) {
59644961713Sgirish 			if ((*int_prop_val >= param_arr[i].minimum) &&
5974045d941Ssowmini 			    (*int_prop_val <= param_arr[i].maximum))
59844961713Sgirish 				param_arr[i].value = *int_prop_val;
59944961713Sgirish #ifdef NXGE_DEBUG_ERROR
60044961713Sgirish 			else {
60144961713Sgirish 				NXGE_DEBUG_MSG((nxgep, OBP_CTL,
6024045d941Ssowmini 				    "nxge%d: 'prom' file parameter error\n",
6034045d941Ssowmini 				    nxgep->instance));
60444961713Sgirish 				NXGE_DEBUG_MSG((nxgep, OBP_CTL,
6054045d941Ssowmini 				    "Parameter keyword '%s'"
6064045d941Ssowmini 				    " is outside valid range\n",
6074045d941Ssowmini 				    param_arr[i].name));
60844961713Sgirish 			}
60944961713Sgirish #endif
61044961713Sgirish 			ddi_prop_free(int_prop_val);
61144961713Sgirish 		}
61244961713Sgirish 
61344961713Sgirish 		if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0,
6144045d941Ssowmini 		    param_arr[i].name,
6154045d941Ssowmini 		    (int **)&int_prop_val,
6164045d941Ssowmini 		    &prop_len) == DDI_PROP_SUCCESS) {
61744961713Sgirish 			if ((*int_prop_val >= param_arr[i].minimum) &&
6184045d941Ssowmini 			    (*int_prop_val <= param_arr[i].maximum))
61944961713Sgirish 				param_arr[i].value = *int_prop_val;
62044961713Sgirish #ifdef NXGE_DEBUG_ERROR
62144961713Sgirish 			else {
62244961713Sgirish 				NXGE_DEBUG_MSG((nxgep, OBP_CTL,
6234045d941Ssowmini 				    "nxge%d: 'conf' file parameter error\n",
6244045d941Ssowmini 				    nxgep->instance));
62544961713Sgirish 				NXGE_DEBUG_MSG((nxgep, OBP_CTL,
6264045d941Ssowmini 				    "Parameter keyword '%s'"
6274045d941Ssowmini 				    "is outside valid range\n",
6284045d941Ssowmini 				    param_arr[i].name));
62944961713Sgirish 			}
63044961713Sgirish #endif
63144961713Sgirish 			ddi_prop_free(int_prop_val);
63244961713Sgirish 		}
63344961713Sgirish 	}
63444961713Sgirish }
63544961713Sgirish 
63644961713Sgirish static int
63744961713Sgirish nxge_private_param_register(p_nxge_t nxgep, p_nxge_param_t param_arr)
63844961713Sgirish {
63944961713Sgirish 	int status = B_TRUE;
64044961713Sgirish 	int channel;
64144961713Sgirish 	uint8_t grp;
64244961713Sgirish 	char *prop_name;
64344961713Sgirish 	char *end;
64444961713Sgirish 	uint32_t name_chars;
64544961713Sgirish 
64644961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD2_CTL,
6474045d941Ssowmini 	    "nxge_private_param_register %s", param_arr->name));
64844961713Sgirish 
64944961713Sgirish 	if ((param_arr->type & NXGE_PARAM_PRIV) != NXGE_PARAM_PRIV)
65044961713Sgirish 		return (B_TRUE);
651a3c5bd6dSspeer 
65244961713Sgirish 	prop_name =  param_arr->name;
65344961713Sgirish 	if (param_arr->type & NXGE_PARAM_RXDMA) {
65444961713Sgirish 		if (strncmp("rxdma_intr", prop_name, 10) == 0)
65544961713Sgirish 			return (B_TRUE);
65644961713Sgirish 		name_chars = strlen("default_grp");
65744961713Sgirish 		if (strncmp("default_grp", prop_name, name_chars) == 0) {
65844961713Sgirish 			prop_name += name_chars;
65944961713Sgirish 			grp = mi_strtol(prop_name, &end, 10);
66044961713Sgirish 				/* now check if this rdcgrp is in config */
66144961713Sgirish 			return (nxge_check_rdcgrp_port_member(nxgep, grp));
66244961713Sgirish 		}
66344961713Sgirish 		name_chars = strlen(prop_name);
66444961713Sgirish 		if (strncmp("default_port_rdc", prop_name, name_chars) == 0) {
66544961713Sgirish 			return (B_TRUE);
66644961713Sgirish 		}
66744961713Sgirish 		return (B_FALSE);
66844961713Sgirish 	}
66944961713Sgirish 
67044961713Sgirish 	if (param_arr->type & NXGE_PARAM_TXDMA) {
67144961713Sgirish 		name_chars = strlen("txdma");
67244961713Sgirish 		if (strncmp("txdma", prop_name, name_chars) == 0) {
67344961713Sgirish 			prop_name += name_chars;
67444961713Sgirish 			channel = mi_strtol(prop_name, &end, 10);
67544961713Sgirish 				/* now check if this rdc is in config */
67644961713Sgirish 			NXGE_DEBUG_MSG((nxgep, NDD2_CTL,
6774045d941Ssowmini 			    " nxge_private_param_register: %d",
6784045d941Ssowmini 			    channel));
67944961713Sgirish 			return (nxge_check_txdma_port_member(nxgep, channel));
68044961713Sgirish 		}
68144961713Sgirish 		return (B_FALSE);
68244961713Sgirish 	}
68344961713Sgirish 
68444961713Sgirish 	status = B_FALSE;
68544961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD2_CTL, "<== nxge_private_param_register"));
68644961713Sgirish 
68744961713Sgirish 	return (status);
68844961713Sgirish }
68944961713Sgirish 
69044961713Sgirish void
69144961713Sgirish nxge_setup_param(p_nxge_t nxgep)
69244961713Sgirish {
69344961713Sgirish 	p_nxge_param_t param_arr;
69444961713Sgirish 	int i;
69544961713Sgirish 	pfi_t set_pfi;
69644961713Sgirish 
69744961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_setup_param"));
698a3c5bd6dSspeer 
69944961713Sgirish 	/*
70044961713Sgirish 	 * Make sure the param_instance is set to a valid device instance.
70144961713Sgirish 	 */
70244961713Sgirish 	if (nxge_param_arr[param_instance].value == 1000)
70344961713Sgirish 		nxge_param_arr[param_instance].value = nxgep->instance;
70444961713Sgirish 
70544961713Sgirish 	param_arr = nxgep->param_arr;
70644961713Sgirish 	param_arr[param_instance].value = nxgep->instance;
70744961713Sgirish 	param_arr[param_function_number].value = nxgep->function_num;
70844961713Sgirish 
70944961713Sgirish 	for (i = 0; i < nxgep->param_count; i++) {
71044961713Sgirish 		if ((param_arr[i].type & NXGE_PARAM_PRIV) &&
7114045d941Ssowmini 		    (nxge_private_param_register(nxgep,
7124045d941Ssowmini 		    &param_arr[i]) == B_FALSE)) {
71344961713Sgirish 			param_arr[i].setf = NULL;
71444961713Sgirish 			param_arr[i].getf = NULL;
71544961713Sgirish 		}
71644961713Sgirish 
71744961713Sgirish 		if (param_arr[i].type & NXGE_PARAM_CMPLX)
71844961713Sgirish 			param_arr[i].setf = NULL;
71944961713Sgirish 
72044961713Sgirish 		if (param_arr[i].type & NXGE_PARAM_DONT_SHOW) {
72144961713Sgirish 			param_arr[i].setf = NULL;
72244961713Sgirish 			param_arr[i].getf = NULL;
72344961713Sgirish 		}
72444961713Sgirish 
72544961713Sgirish 		set_pfi = (pfi_t)param_arr[i].setf;
72644961713Sgirish 
727a3c5bd6dSspeer 		if ((set_pfi) && (param_arr[i].type & NXGE_PARAM_INIT_ONLY)) {
72844961713Sgirish 			set_pfi = NULL;
72944961713Sgirish 		}
73044961713Sgirish 
73144961713Sgirish 	}
73244961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_setup_param"));
73344961713Sgirish }
73444961713Sgirish 
73544961713Sgirish void
73644961713Sgirish nxge_init_param(p_nxge_t nxgep)
73744961713Sgirish {
73844961713Sgirish 	p_nxge_param_t param_arr;
73944961713Sgirish 	int i, alloc_size;
74044961713Sgirish 	uint64_t alloc_count;
74144961713Sgirish 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_init_param"));
74244961713Sgirish 	/*
74344961713Sgirish 	 * Make sure the param_instance is set to a valid device instance.
74444961713Sgirish 	 */
74544961713Sgirish 	if (nxge_param_arr[param_instance].value == 1000)
74644961713Sgirish 		nxge_param_arr[param_instance].value = nxgep->instance;
74744961713Sgirish 
74844961713Sgirish 	param_arr = nxgep->param_arr;
74944961713Sgirish 	if (param_arr == NULL) {
750a3c5bd6dSspeer 		param_arr = (p_nxge_param_t)
7514045d941Ssowmini 		    KMEM_ZALLOC(sizeof (nxge_param_arr), KM_SLEEP);
75244961713Sgirish 	}
753a3c5bd6dSspeer 
75444961713Sgirish 	for (i = 0; i < sizeof (nxge_param_arr)/sizeof (nxge_param_t); i++) {
75544961713Sgirish 		param_arr[i] = nxge_param_arr[i];
75644961713Sgirish 		if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) ||
7574045d941Ssowmini 		    (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) {
75844961713Sgirish 			alloc_count = NXGE_PARAM_ARRAY_INIT_SIZE;
75944961713Sgirish 			alloc_size = alloc_count * sizeof (uint64_t);
76044961713Sgirish 			param_arr[i].value =
761adfcba55Sjoycey #if defined(__i386)
7624045d941Ssowmini 			    (uint64_t)(uint32_t)KMEM_ZALLOC(alloc_size,
7634045d941Ssowmini 			    KM_SLEEP);
764adfcba55Sjoycey #else
7651bd6825cSml 			(uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP);
766adfcba55Sjoycey #endif
76744961713Sgirish 			param_arr[i].old_value =
768adfcba55Sjoycey #if defined(__i386)
7694045d941Ssowmini 			    (uint64_t)(uint32_t)KMEM_ZALLOC(alloc_size,
7704045d941Ssowmini 			    KM_SLEEP);
771adfcba55Sjoycey #else
7724045d941Ssowmini 			(uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP);
773adfcba55Sjoycey #endif
77444961713Sgirish 			param_arr[i].type |=
7754045d941Ssowmini 			    (alloc_count << NXGE_PARAM_ARRAY_ALLOC_SHIFT);
77644961713Sgirish 		}
77744961713Sgirish 	}
77844961713Sgirish 
77944961713Sgirish 	nxgep->param_arr = param_arr;
78044961713Sgirish 	nxgep->param_count = sizeof (nxge_param_arr)/sizeof (nxge_param_t);
7811bd6825cSml 
7821bd6825cSml 	nxge_param_sync(nxgep);
7831bd6825cSml 
78444961713Sgirish 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_init_param: count %d",
7854045d941Ssowmini 	    nxgep->param_count));
78644961713Sgirish }
78744961713Sgirish 
78844961713Sgirish void
78944961713Sgirish nxge_destroy_param(p_nxge_t nxgep)
79044961713Sgirish {
79144961713Sgirish 	int i;
79244961713Sgirish 	uint64_t free_size, free_count;
79344961713Sgirish 
79444961713Sgirish 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_param"));
795a3c5bd6dSspeer 
79659ac0c16Sdavemq 	if (nxgep->param_arr == NULL)
79759ac0c16Sdavemq 		return;
79844961713Sgirish 	/*
79944961713Sgirish 	 * Make sure the param_instance is set to a valid device instance.
80044961713Sgirish 	 */
80144961713Sgirish 	if (nxge_param_arr[param_instance].value == nxgep->instance) {
80244961713Sgirish 		for (i = 0; i <= nxge_param_arr[param_instance].maximum; i++) {
80344961713Sgirish 			if ((ddi_get_soft_state(nxge_list, i) != NULL) &&
8044045d941Ssowmini 			    (i != nxgep->instance))
80544961713Sgirish 				break;
80644961713Sgirish 		}
80744961713Sgirish 		nxge_param_arr[param_instance].value = i;
80844961713Sgirish 	}
80944961713Sgirish 
81044961713Sgirish 	for (i = 0; i < nxgep->param_count; i++)
81144961713Sgirish 		if ((nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR32) ||
8124045d941Ssowmini 		    (nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR64)) {
81344961713Sgirish 			free_count = ((nxgep->param_arr[i].type &
8144045d941Ssowmini 			    NXGE_PARAM_ARRAY_ALLOC_MASK) >>
8154045d941Ssowmini 			    NXGE_PARAM_ARRAY_ALLOC_SHIFT);
81644961713Sgirish 			free_count = NXGE_PARAM_ARRAY_INIT_SIZE;
81744961713Sgirish 			free_size = sizeof (uint64_t) * free_count;
818adfcba55Sjoycey #if defined(__i386)
819adfcba55Sjoycey 			KMEM_FREE((void *)(uint32_t)nxgep->param_arr[i].value,
8204045d941Ssowmini 			    free_size);
821adfcba55Sjoycey #else
82244961713Sgirish 			KMEM_FREE((void *)nxgep->param_arr[i].value, free_size);
823adfcba55Sjoycey #endif
824adfcba55Sjoycey #if defined(__i386)
825adfcba55Sjoycey 			KMEM_FREE((void *)(uint32_t)
8264045d941Ssowmini 			    nxgep->param_arr[i].old_value, free_size);
827adfcba55Sjoycey #else
82844961713Sgirish 			KMEM_FREE((void *)nxgep->param_arr[i].old_value,
8294045d941Ssowmini 			    free_size);
830adfcba55Sjoycey #endif
83144961713Sgirish 		}
83244961713Sgirish 
83344961713Sgirish 	KMEM_FREE(nxgep->param_arr, sizeof (nxge_param_arr));
83444961713Sgirish 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_param"));
83544961713Sgirish }
83644961713Sgirish 
83744961713Sgirish /*
83844961713Sgirish  * Extracts the value from the 'nxge' parameter array and prints the
83944961713Sgirish  * parameter value. cp points to the required parameter.
84044961713Sgirish  */
841a3c5bd6dSspeer 
84244961713Sgirish /* ARGSUSED */
84344961713Sgirish int
84444961713Sgirish nxge_param_get_generic(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
84544961713Sgirish {
84644961713Sgirish 	p_nxge_param_t pa = (p_nxge_param_t)cp;
84744961713Sgirish 
848a3c5bd6dSspeer 	NXGE_DEBUG_MSG((nxgep, NDD_CTL,
8494045d941Ssowmini 	    "==> nxge_param_get_generic name %s ", pa->name));
85044961713Sgirish 
85144961713Sgirish 	if (pa->value > 0xffffffff)
852a3c5bd6dSspeer 		(void) mi_mpprintf(mp, "%x%x",
8534045d941Ssowmini 		    (int)(pa->value >> 32), (int)(pa->value & 0xffffffff));
85444961713Sgirish 	else
85544961713Sgirish 		(void) mi_mpprintf(mp, "%x", (int)pa->value);
85644961713Sgirish 
85744961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_generic"));
85844961713Sgirish 	return (0);
85944961713Sgirish }
86044961713Sgirish 
86144961713Sgirish /* ARGSUSED */
86244961713Sgirish static int
86344961713Sgirish nxge_param_get_mac(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
86444961713Sgirish {
86544961713Sgirish 	p_nxge_param_t pa = (p_nxge_param_t)cp;
86644961713Sgirish 
86744961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac"));
86844961713Sgirish 
86944961713Sgirish 	(void) mi_mpprintf(mp, "%d", (uint32_t)pa->value);
87044961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_mac"));
87144961713Sgirish 	return (0);
87244961713Sgirish }
87344961713Sgirish 
87456d930aeSspeer /* ARGSUSED */
87556d930aeSspeer static int
87656d930aeSspeer nxge_param_get_fw_ver(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
87756d930aeSspeer {
87856d930aeSspeer 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_fw_ver"));
87956d930aeSspeer 
88056d930aeSspeer 	(void) mi_mpprintf(mp, "Firmware version for nxge%d:  %s\n",
88156d930aeSspeer 	    nxgep->instance, nxgep->vpd_info.ver);
88256d930aeSspeer 
88356d930aeSspeer 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_fw_ver"));
88456d930aeSspeer 	return (0);
88556d930aeSspeer }
88656d930aeSspeer 
8872e59129aSraghus /* ARGSUSED */
8882e59129aSraghus static int
8892e59129aSraghus nxge_param_get_port_mode(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
8902e59129aSraghus {
8912e59129aSraghus 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_port_mode"));
8922e59129aSraghus 
8932e59129aSraghus 	switch (nxgep->mac.portmode) {
8942e59129aSraghus 	case PORT_1G_COPPER:
8952d17280bSsbehera 		(void) mi_mpprintf(mp, "Port mode for nxge%d:  1G Copper %s\n",
8962d17280bSsbehera 		    nxgep->instance,
8972d17280bSsbehera 		    nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
8982e59129aSraghus 		break;
8992e59129aSraghus 	case PORT_1G_FIBER:
9002d17280bSsbehera 		(void) mi_mpprintf(mp, "Port mode for nxge%d:  1G Fiber %s\n",
9012d17280bSsbehera 		    nxgep->instance,
9022d17280bSsbehera 		    nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
9032e59129aSraghus 		break;
9042e59129aSraghus 	case PORT_10G_COPPER:
9052d17280bSsbehera 		(void) mi_mpprintf(mp, "Port mode for nxge%d:  10G Copper "
9062d17280bSsbehera 		    "%s\n", nxgep->instance,
9072d17280bSsbehera 		    nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
9082e59129aSraghus 		break;
9092e59129aSraghus 	case PORT_10G_FIBER:
9102d17280bSsbehera 		(void) mi_mpprintf(mp, "Port mode for nxge%d:  10G Fiber %s\n",
9112d17280bSsbehera 		    nxgep->instance,
9122d17280bSsbehera 		    nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
9132e59129aSraghus 		break;
9142e59129aSraghus 	case PORT_10G_SERDES:
9152d17280bSsbehera 		(void) mi_mpprintf(mp, "Port mode for nxge%d:  10G Serdes "
9162d17280bSsbehera 		    "%s\n", nxgep->instance,
9172d17280bSsbehera 		    nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
9182e59129aSraghus 		break;
9192e59129aSraghus 	case PORT_1G_SERDES:
9202d17280bSsbehera 		(void) mi_mpprintf(mp, "Port mode for nxge%d:  1G Serdes %s\n",
9212d17280bSsbehera 		    nxgep->instance,
9222d17280bSsbehera 		    nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
9232e59129aSraghus 		break;
9242e59129aSraghus 	case PORT_1G_RGMII_FIBER:
9252e59129aSraghus 		(void) mi_mpprintf(mp, "Port mode for nxge%d:  1G RGMII "
9262d17280bSsbehera 		    "Fiber %s\n", nxgep->instance,
9272d17280bSsbehera 		    nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
9282d17280bSsbehera 		break;
9292d17280bSsbehera 	case PORT_HSP_MODE:
9302d17280bSsbehera 		(void) mi_mpprintf(mp, "Port mode for nxge%d:  Hot Swappable "
9312d17280bSsbehera 		    "PHY, Currently NOT present\n", nxgep->instance);
9322e59129aSraghus 		break;
93300161856Syc 	case PORT_10G_TN1010:
93400161856Syc 		(void) mi_mpprintf(mp, "Port mode for nxge%d:"
93500161856Syc 		    " 10G Copper with TN1010 %s\n", nxgep->instance,
93600161856Syc 		    nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
93700161856Syc 		break;
93800161856Syc 	case PORT_1G_TN1010:
939*c6e5ef56Syc 		(void) mi_mpprintf(mp, "Port mode for nxge%d:"
94000161856Syc 		    " 1G Copper with TN1010 %s\n", nxgep->instance,
94100161856Syc 		    nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
94200161856Syc 		break;
9432e59129aSraghus 	default:
9442d17280bSsbehera 		(void) mi_mpprintf(mp, "Port mode for nxge%d:  Unknown %s\n",
9452d17280bSsbehera 		    nxgep->instance,
9462d17280bSsbehera 		    nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
9472e59129aSraghus 		break;
9482e59129aSraghus 	}
9492e59129aSraghus 
9503d16f8e7Sml 	(void) mi_mpprintf(mp, "Software LSO for nxge%d: %s\n",
9513d16f8e7Sml 	    nxgep->instance,
9523d16f8e7Sml 	    nxgep->soft_lso_enable ? "enable" : "disable");
9533d16f8e7Sml 
9542e59129aSraghus 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_port_mode"));
9552e59129aSraghus 	return (0);
9562e59129aSraghus }
9572e59129aSraghus 
95844961713Sgirish /* ARGSUSED */
95944961713Sgirish int
96044961713Sgirish nxge_param_get_txdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
96144961713Sgirish {
96244961713Sgirish 
963678453a8Sspeer 	uint_t print_len, buf_len;
96444961713Sgirish 	p_mblk_t np;
96544961713Sgirish 
96644961713Sgirish 	int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE;
967678453a8Sspeer 	int tdc;
968678453a8Sspeer 
969678453a8Sspeer 	nxge_grp_set_t *set;
970678453a8Sspeer 
97144961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_txdma_info"));
97244961713Sgirish 
973a3c5bd6dSspeer 	(void) mi_mpprintf(mp, "TXDMA Information for Port\t %d \n",
9744045d941Ssowmini 	    nxgep->function_num);
97544961713Sgirish 
97644961713Sgirish 	if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) {
97744961713Sgirish 		(void) mi_mpprintf(mp, "%s\n", "out of buffer");
97844961713Sgirish 		return (0);
97944961713Sgirish 	}
98044961713Sgirish 
98144961713Sgirish 	buf_len = buff_alloc_size;
98244961713Sgirish 	mp->b_cont = np;
983678453a8Sspeer 	print_len = 0;
98444961713Sgirish 
98544961713Sgirish 	((mblk_t *)np)->b_wptr += print_len;
98644961713Sgirish 	buf_len -= print_len;
98744961713Sgirish 	print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
9884045d941Ssowmini 	    "TDC\t HW TDC\t\n");
98944961713Sgirish 	((mblk_t *)np)->b_wptr += print_len;
99044961713Sgirish 	buf_len -= print_len;
991678453a8Sspeer 
992678453a8Sspeer 	set = &nxgep->tx_set;
993678453a8Sspeer 	for (tdc = 0; tdc < NXGE_MAX_RDCS; tdc++) {
994678453a8Sspeer 		if ((1 << tdc) & set->owned.map) {
995678453a8Sspeer 			print_len = snprintf((char *)((mblk_t *)np)->b_wptr,
996678453a8Sspeer 			    buf_len, "%d\n", tdc);
997678453a8Sspeer 			((mblk_t *)np)->b_wptr += print_len;
998678453a8Sspeer 			buf_len -= print_len;
999678453a8Sspeer 		}
100044961713Sgirish 	}
1001a3c5bd6dSspeer 
100244961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_txdma_info"));
100344961713Sgirish 	return (0);
100444961713Sgirish }
100544961713Sgirish 
100644961713Sgirish /* ARGSUSED */
100744961713Sgirish int
100844961713Sgirish nxge_param_get_rxdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
100944961713Sgirish {
1010a3c5bd6dSspeer 	uint_t			print_len, buf_len;
1011a3c5bd6dSspeer 	p_mblk_t		np;
1012a3c5bd6dSspeer 	int			rdc;
101344961713Sgirish 	p_nxge_dma_pt_cfg_t	p_dma_cfgp;
101444961713Sgirish 	p_nxge_hw_pt_cfg_t	p_cfgp;
1015a3c5bd6dSspeer 	int			buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE;
101644961713Sgirish 	p_rx_rcr_rings_t 	rx_rcr_rings;
101744961713Sgirish 	p_rx_rcr_ring_t		*rcr_rings;
101844961713Sgirish 	p_rx_rbr_rings_t 	rx_rbr_rings;
101944961713Sgirish 	p_rx_rbr_ring_t		*rbr_rings;
1020678453a8Sspeer 	nxge_grp_set_t		*set;
102144961713Sgirish 
102244961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rxdma_info"));
102344961713Sgirish 
1024a3c5bd6dSspeer 	(void) mi_mpprintf(mp, "RXDMA Information for Port\t %d \n",
10254045d941Ssowmini 	    nxgep->function_num);
102644961713Sgirish 
102744961713Sgirish 	if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) {
102844961713Sgirish 		/* The following may work even if we cannot get a large buf. */
102944961713Sgirish 		(void) mi_mpprintf(mp, "%s\n", "out of buffer");
103044961713Sgirish 		return (0);
103144961713Sgirish 	}
103244961713Sgirish 
103344961713Sgirish 	buf_len = buff_alloc_size;
103444961713Sgirish 	mp->b_cont = np;
103544961713Sgirish 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
103644961713Sgirish 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
103744961713Sgirish 
103844961713Sgirish 	rx_rcr_rings = nxgep->rx_rcr_rings;
103944961713Sgirish 	rcr_rings = rx_rcr_rings->rcr_rings;
104044961713Sgirish 	rx_rbr_rings = nxgep->rx_rbr_rings;
104144961713Sgirish 	rbr_rings = rx_rbr_rings->rbr_rings;
104244961713Sgirish 
104344961713Sgirish 	print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
10444045d941Ssowmini 	    "Total RDCs\t %d\n", p_cfgp->max_rdcs);
104544961713Sgirish 
104644961713Sgirish 	((mblk_t *)np)->b_wptr += print_len;
104744961713Sgirish 	buf_len -= print_len;
104844961713Sgirish 	print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
10494045d941Ssowmini 	    "RDC\t HW RDC\t Timeout\t Packets RBR ptr \t"
10504045d941Ssowmini 	    "chunks\t RCR ptr\n");
1051a3c5bd6dSspeer 
105244961713Sgirish 	((mblk_t *)np)->b_wptr += print_len;
105344961713Sgirish 	buf_len -= print_len;
1054678453a8Sspeer 
1055678453a8Sspeer 	set = &nxgep->rx_set;
1056678453a8Sspeer 	for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) {
1057678453a8Sspeer 		if ((1 << rdc) & set->owned.map) {
1058678453a8Sspeer 			print_len = snprintf((char *)
1059678453a8Sspeer 			    ((mblk_t *)np)->b_wptr, buf_len,
1060678453a8Sspeer 			    " %d\t   %x\t\t %x\t $%p\t 0x%x\t $%p\n",
1061678453a8Sspeer 			    rdc,
1062678453a8Sspeer 			    p_dma_cfgp->rcr_timeout[rdc],
1063678453a8Sspeer 			    p_dma_cfgp->rcr_threshold[rdc],
1064678453a8Sspeer 			    rbr_rings[rdc],
1065678453a8Sspeer 			    rbr_rings[rdc]->num_blocks, rcr_rings[rdc]);
1066a3c5bd6dSspeer 			((mblk_t *)np)->b_wptr += print_len;
1067a3c5bd6dSspeer 			buf_len -= print_len;
1068678453a8Sspeer 		}
106944961713Sgirish 	}
1070a3c5bd6dSspeer 
107144961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rxdma_info"));
107244961713Sgirish 	return (0);
107344961713Sgirish }
107444961713Sgirish 
107544961713Sgirish /* ARGSUSED */
107644961713Sgirish int
107744961713Sgirish nxge_param_get_rxdma_rdcgrp_info(p_nxge_t nxgep, queue_t *q,
1078a3c5bd6dSspeer 	p_mblk_t mp, caddr_t cp)
107944961713Sgirish {
1080a3c5bd6dSspeer 	uint_t			print_len, buf_len;
1081a3c5bd6dSspeer 	p_mblk_t		np;
1082a3c5bd6dSspeer 	int			offset, rdc, i, rdc_grp;
108344961713Sgirish 	p_nxge_rdc_grp_t	rdc_grp_p;
108444961713Sgirish 	p_nxge_dma_pt_cfg_t	p_dma_cfgp;
108544961713Sgirish 	p_nxge_hw_pt_cfg_t	p_cfgp;
108644961713Sgirish 
108744961713Sgirish 	int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE;
108844961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL,
10894045d941Ssowmini 	    "==> nxge_param_get_rxdma_rdcgrp_info"));
109044961713Sgirish 
109144961713Sgirish 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
109244961713Sgirish 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
109344961713Sgirish 
1094a3c5bd6dSspeer 	(void) mi_mpprintf(mp, "RXDMA RDC Group Information for Port\t %d \n",
10954045d941Ssowmini 	    nxgep->function_num);
109644961713Sgirish 
1097678453a8Sspeer 	rdc_grp = p_cfgp->def_mac_rxdma_grpid;
109844961713Sgirish 	if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) {
109944961713Sgirish 		/* The following may work even if we cannot get a large buf. */
110044961713Sgirish 		(void) mi_mpprintf(mp, "%s\n", "out of buffer");
110144961713Sgirish 		return (0);
110244961713Sgirish 	}
110344961713Sgirish 
110444961713Sgirish 	buf_len = buff_alloc_size;
110544961713Sgirish 	mp->b_cont = np;
110644961713Sgirish 	print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
11074045d941Ssowmini 	    "Total RDC Groups\t %d \n"
11084045d941Ssowmini 	    "default RDC group\t %d\n",
11094045d941Ssowmini 	    p_cfgp->max_rdc_grpids,
11104045d941Ssowmini 	    p_cfgp->def_mac_rxdma_grpid);
111144961713Sgirish 
111244961713Sgirish 	((mblk_t *)np)->b_wptr += print_len;
111344961713Sgirish 	buf_len -= print_len;
111444961713Sgirish 
1115678453a8Sspeer 	for (i = 0; i < NXGE_MAX_RDCS; i++) {
1116678453a8Sspeer 		if (p_cfgp->grpids[i]) {
1117678453a8Sspeer 			rdc_grp_p = &p_dma_cfgp->rdc_grps[i];
111844961713Sgirish 			print_len = snprintf((char *)((mblk_t *)np)->b_wptr,
1119678453a8Sspeer 			    buf_len,
1120678453a8Sspeer 			    "\nRDC Group Info for Group [%d] %d\n"
1121678453a8Sspeer 			    "RDC Count %d\tstart RDC %d\n"
1122678453a8Sspeer 			    "RDC Group Population Information"
1123678453a8Sspeer 			    " (offsets 0 - 15)\n",
1124678453a8Sspeer 			    i, rdc_grp, rdc_grp_p->max_rdcs,
1125678453a8Sspeer 			    rdc_grp_p->start_rdc);
1126678453a8Sspeer 
1127678453a8Sspeer 			((mblk_t *)np)->b_wptr += print_len;
1128678453a8Sspeer 			buf_len -= print_len;
1129678453a8Sspeer 			print_len = snprintf((char *)((mblk_t *)np)->b_wptr,
1130678453a8Sspeer 			    buf_len, "\n");
1131678453a8Sspeer 			((mblk_t *)np)->b_wptr += print_len;
1132678453a8Sspeer 			buf_len -= print_len;
1133678453a8Sspeer 
1134678453a8Sspeer 			for (rdc = 0; rdc < rdc_grp_p->max_rdcs; rdc++) {
1135678453a8Sspeer 				print_len = snprintf(
11364045d941Ssowmini 				    (char *)((mblk_t *)np)->b_wptr,
11374045d941Ssowmini 				    buf_len, "[%d]=%d ", rdc,
11384045d941Ssowmini 				    rdc_grp_p->start_rdc + rdc);
1139678453a8Sspeer 				((mblk_t *)np)->b_wptr += print_len;
1140678453a8Sspeer 				buf_len -= print_len;
1141678453a8Sspeer 			}
1142678453a8Sspeer 			print_len = snprintf((char *)((mblk_t *)np)->b_wptr,
1143678453a8Sspeer 			    buf_len, "\n");
114444961713Sgirish 			((mblk_t *)np)->b_wptr += print_len;
114544961713Sgirish 			buf_len -= print_len;
114644961713Sgirish 
1147678453a8Sspeer 			for (offset = 0; offset < 16; offset++) {
1148678453a8Sspeer 				print_len = snprintf(
11494045d941Ssowmini 				    (char *)((mblk_t *)np)->b_wptr,
11504045d941Ssowmini 				    buf_len, " %c",
11514045d941Ssowmini 				    rdc_grp_p->map & (1 << offset) ?
11524045d941Ssowmini 				    '1' : '0');
1153678453a8Sspeer 				((mblk_t *)np)->b_wptr += print_len;
1154678453a8Sspeer 				buf_len -= print_len;
1155678453a8Sspeer 			}
115644961713Sgirish 			print_len = snprintf((char *)((mblk_t *)np)->b_wptr,
1157678453a8Sspeer 			    buf_len, "\n");
115844961713Sgirish 			((mblk_t *)np)->b_wptr += print_len;
115944961713Sgirish 			buf_len -= print_len;
116044961713Sgirish 		}
116144961713Sgirish 	}
116244961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL,
11634045d941Ssowmini 	    "<== nxge_param_get_rxdma_rdcgrp_info"));
116444961713Sgirish 	return (0);
116544961713Sgirish }
116644961713Sgirish 
116744961713Sgirish int
116844961713Sgirish nxge_mk_mblk_tail_space(p_mblk_t mp, p_mblk_t *nmp, size_t size)
116944961713Sgirish {
117044961713Sgirish 	p_mblk_t tmp;
117144961713Sgirish 
117244961713Sgirish 	tmp = mp;
117344961713Sgirish 	while (tmp->b_cont)
117444961713Sgirish 		tmp = tmp->b_cont;
117544961713Sgirish 	if ((tmp->b_wptr + size) >= tmp->b_datap->db_lim) {
117644961713Sgirish 		tmp->b_cont = allocb(1024, BPRI_HI);
117744961713Sgirish 		tmp = tmp->b_cont;
117844961713Sgirish 		if (!tmp)
117944961713Sgirish 			return (ENOMEM);
118044961713Sgirish 	}
1181a3c5bd6dSspeer 
118244961713Sgirish 	*nmp = tmp;
118344961713Sgirish 	return (0);
118444961713Sgirish }
118544961713Sgirish 
1186a3c5bd6dSspeer 
118744961713Sgirish /* ARGSUSED */
118844961713Sgirish int
118944961713Sgirish nxge_param_set_generic(p_nxge_t nxgep, queue_t *q, mblk_t *mp,
119044961713Sgirish 			    char *value, caddr_t cp)
119144961713Sgirish {
119244961713Sgirish 	char *end;
119344961713Sgirish 	uint32_t new_value;
119444961713Sgirish 	p_nxge_param_t pa = (p_nxge_param_t)cp;
119544961713Sgirish 
119644961713Sgirish 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, " ==> nxge_param_set_generic"));
119744961713Sgirish 	new_value = (uint32_t)mi_strtol(value, &end, 10);
119844961713Sgirish 	if (end == value || new_value < pa->minimum ||
11994045d941Ssowmini 	    new_value > pa->maximum) {
120044961713Sgirish 			return (EINVAL);
120144961713Sgirish 	}
120244961713Sgirish 	pa->value = new_value;
120344961713Sgirish 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, " <== nxge_param_set_generic"));
120444961713Sgirish 	return (0);
120544961713Sgirish }
120644961713Sgirish 
120744961713Sgirish 
1208a3c5bd6dSspeer /* ARGSUSED */
120944961713Sgirish int
1210a3c5bd6dSspeer nxge_param_set_instance(p_nxge_t nxgep, queue_t *q, mblk_t *mp,
1211a3c5bd6dSspeer 	char *value, caddr_t cp)
121244961713Sgirish {
121344961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, " ==> nxge_param_set_instance"));
121444961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_set_instance"));
121544961713Sgirish 	return (0);
121644961713Sgirish }
121744961713Sgirish 
121844961713Sgirish 
1219a3c5bd6dSspeer /* ARGSUSED */
122044961713Sgirish int
1221a3c5bd6dSspeer nxge_param_set_mac(p_nxge_t nxgep, queue_t *q, mblk_t *mp,
1222a3c5bd6dSspeer 	char *value, caddr_t cp)
122344961713Sgirish {
1224a3c5bd6dSspeer 	char		*end;
1225a3c5bd6dSspeer 	uint32_t	new_value;
1226a3c5bd6dSspeer 	int		status = 0;
1227a3c5bd6dSspeer 	p_nxge_param_t	pa = (p_nxge_param_t)cp;
122844961713Sgirish 
122944961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac"));
123044961713Sgirish 	new_value = (uint32_t)mi_strtol(value, &end, BASE_DECIMAL);
123144961713Sgirish 	if (PARAM_OUTOF_RANGE(value, end, new_value, pa)) {
123244961713Sgirish 		return (EINVAL);
123344961713Sgirish 	}
123444961713Sgirish 
123544961713Sgirish 	if (pa->value != new_value) {
123644961713Sgirish 		pa->old_value = pa->value;
123744961713Sgirish 		pa->value = new_value;
123844961713Sgirish 	}
123944961713Sgirish 
124044961713Sgirish 	if (!nxge_param_link_update(nxgep)) {
124144961713Sgirish 		NXGE_DEBUG_MSG((nxgep, NDD_CTL,
12424045d941Ssowmini 		    " false ret from nxge_param_link_update"));
124344961713Sgirish 		status = EINVAL;
124444961713Sgirish 	}
124544961713Sgirish 
124644961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac"));
124744961713Sgirish 	return (status);
124844961713Sgirish }
124944961713Sgirish 
125044961713Sgirish /* ARGSUSED */
12511bd6825cSml int
1252a3c5bd6dSspeer nxge_param_rx_intr_pkts(p_nxge_t nxgep, queue_t *q, mblk_t *mp,
1253a3c5bd6dSspeer 	char *value, caddr_t cp)
125444961713Sgirish {
1255a3c5bd6dSspeer 	char		*end;
1256a3c5bd6dSspeer 	uint32_t	cfg_value;
1257a3c5bd6dSspeer 	p_nxge_param_t	pa = (p_nxge_param_t)cp;
125814ea4bb7Ssd 
125944961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_pkts"));
126044961713Sgirish 
126114ea4bb7Ssd 	cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY);
126244961713Sgirish 
126314ea4bb7Ssd 	if ((cfg_value > NXGE_RDC_RCR_THRESHOLD_MAX) ||
12644045d941Ssowmini 	    (cfg_value < NXGE_RDC_RCR_THRESHOLD_MIN)) {
126544961713Sgirish 		return (EINVAL);
126644961713Sgirish 	}
126714ea4bb7Ssd 
126814ea4bb7Ssd 	if ((pa->value != cfg_value)) {
126914ea4bb7Ssd 		pa->old_value = pa->value;
127014ea4bb7Ssd 		pa->value = cfg_value;
127114ea4bb7Ssd 		nxgep->intr_threshold = pa->value;
127244961713Sgirish 	}
127314ea4bb7Ssd 
127444961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_pkts"));
127544961713Sgirish 	return (0);
127644961713Sgirish }
127744961713Sgirish 
127844961713Sgirish /* ARGSUSED */
12791bd6825cSml int
1280a3c5bd6dSspeer nxge_param_rx_intr_time(p_nxge_t nxgep, queue_t *q, mblk_t *mp,
1281a3c5bd6dSspeer 	char *value, caddr_t cp)
128244961713Sgirish {
1283a3c5bd6dSspeer 	char		*end;
1284a3c5bd6dSspeer 	uint32_t	cfg_value;
1285a3c5bd6dSspeer 	p_nxge_param_t	pa = (p_nxge_param_t)cp;
128644961713Sgirish 
128744961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_time"));
128844961713Sgirish 
128914ea4bb7Ssd 	cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY);
129044961713Sgirish 
129114ea4bb7Ssd 	if ((cfg_value > NXGE_RDC_RCR_TIMEOUT_MAX) ||
12924045d941Ssowmini 	    (cfg_value < NXGE_RDC_RCR_TIMEOUT_MIN)) {
129344961713Sgirish 		return (EINVAL);
129444961713Sgirish 	}
129544961713Sgirish 
129614ea4bb7Ssd 	if ((pa->value != cfg_value)) {
129714ea4bb7Ssd 		pa->old_value = pa->value;
129814ea4bb7Ssd 		pa->value = cfg_value;
129914ea4bb7Ssd 		nxgep->intr_timeout = pa->value;
130044961713Sgirish 	}
130144961713Sgirish 
130244961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_time"));
130344961713Sgirish 	return (0);
130444961713Sgirish }
130544961713Sgirish 
130644961713Sgirish /* ARGSUSED */
130744961713Sgirish static int
130844961713Sgirish nxge_param_set_mac_rdcgrp(p_nxge_t nxgep, queue_t *q,
1309a3c5bd6dSspeer 	mblk_t *mp, char *value, caddr_t cp)
131044961713Sgirish {
1311a3c5bd6dSspeer 	char			 *end;
1312a3c5bd6dSspeer 	uint32_t		status = 0, cfg_value;
1313a3c5bd6dSspeer 	p_nxge_param_t		pa = (p_nxge_param_t)cp;
1314a3c5bd6dSspeer 	uint32_t		cfg_it = B_FALSE;
131544961713Sgirish 	p_nxge_dma_pt_cfg_t	p_dma_cfgp;
131644961713Sgirish 	p_nxge_hw_pt_cfg_t	p_cfgp;
1317a3c5bd6dSspeer 	uint32_t		*val_ptr, *old_val_ptr;
1318a3c5bd6dSspeer 	nxge_param_map_t	*mac_map;
1319a3c5bd6dSspeer 	p_nxge_class_pt_cfg_t	p_class_cfgp;
1320a3c5bd6dSspeer 	nxge_mv_cfg_t		*mac_host_info;
132144961713Sgirish 
132244961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac_rdcgrp "));
132344961713Sgirish 
132444961713Sgirish 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
132544961713Sgirish 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
132644961713Sgirish 	p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
132744961713Sgirish 	mac_host_info = (nxge_mv_cfg_t	*)&p_class_cfgp->mac_host_info[0];
132844961713Sgirish 	cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX);
1329a3c5bd6dSspeer 
1330a3c5bd6dSspeer 	/*
1331a3c5bd6dSspeer 	 * now do decoding
1332a3c5bd6dSspeer 	 */
133344961713Sgirish 	mac_map = (nxge_param_map_t *)&cfg_value;
1334a3c5bd6dSspeer 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, " cfg_value %x id %x map_to %x",
13354045d941Ssowmini 	    cfg_value, mac_map->param_id, mac_map->map_to));
133644961713Sgirish 
133744961713Sgirish 	if ((mac_map->param_id < p_cfgp->max_macs) &&
1338678453a8Sspeer 	    p_cfgp->grpids[mac_map->map_to]) {
133944961713Sgirish 		NXGE_DEBUG_MSG((nxgep, NDD_CTL,
1340678453a8Sspeer 		    " nxge_param_set_mac_rdcgrp mapping"
1341678453a8Sspeer 		    " id %d grp %d", mac_map->param_id, mac_map->map_to));
1342adfcba55Sjoycey #if defined(__i386)
1343adfcba55Sjoycey 		val_ptr = (uint32_t *)(uint32_t)pa->value;
1344adfcba55Sjoycey #else
134544961713Sgirish 		val_ptr = (uint32_t *)pa->value;
1346adfcba55Sjoycey #endif
1347adfcba55Sjoycey #if defined(__i386)
1348adfcba55Sjoycey 		old_val_ptr = (uint32_t *)(uint32_t)pa->old_value;
1349adfcba55Sjoycey #else
135044961713Sgirish 		old_val_ptr = (uint32_t *)pa->old_value;
1351adfcba55Sjoycey #endif
135244961713Sgirish 		if (val_ptr[mac_map->param_id] != cfg_value) {
135344961713Sgirish 			old_val_ptr[mac_map->param_id] =
1354678453a8Sspeer 			    val_ptr[mac_map->param_id];
135544961713Sgirish 			val_ptr[mac_map->param_id] = cfg_value;
135644961713Sgirish 			mac_host_info[mac_map->param_id].mpr_npr =
1357678453a8Sspeer 			    mac_map->pref;
135844961713Sgirish 			mac_host_info[mac_map->param_id].flag = 1;
135944961713Sgirish 			mac_host_info[mac_map->param_id].rdctbl =
1360678453a8Sspeer 			    mac_map->map_to;
136144961713Sgirish 			cfg_it = B_TRUE;
136244961713Sgirish 		}
136344961713Sgirish 	} else {
136444961713Sgirish 		return (EINVAL);
136544961713Sgirish 	}
136644961713Sgirish 
136744961713Sgirish 	if (cfg_it == B_TRUE) {
136844961713Sgirish 		status = nxge_logical_mac_assign_rdc_table(nxgep,
1369678453a8Sspeer 		    (uint8_t)mac_map->param_id);
137044961713Sgirish 		if (status != NXGE_OK)
137144961713Sgirish 			return (EINVAL);
137244961713Sgirish 	}
137344961713Sgirish 
137444961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac_rdcgrp"));
137544961713Sgirish 	return (0);
137644961713Sgirish }
137744961713Sgirish 
137844961713Sgirish /* ARGSUSED */
137944961713Sgirish static int
138044961713Sgirish nxge_param_set_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q,
1381a3c5bd6dSspeer 	mblk_t	*mp, char *value, caddr_t cp)
138244961713Sgirish {
1383a3c5bd6dSspeer 	char			*end;
1384a3c5bd6dSspeer 	uint32_t		status = 0, cfg_value;
1385a3c5bd6dSspeer 	p_nxge_param_t		pa = (p_nxge_param_t)cp;
1386a3c5bd6dSspeer 	uint32_t		cfg_it = B_FALSE;
138744961713Sgirish 	p_nxge_dma_pt_cfg_t	p_dma_cfgp;
138844961713Sgirish 	p_nxge_hw_pt_cfg_t	p_cfgp;
1389a3c5bd6dSspeer 	uint32_t		*val_ptr, *old_val_ptr;
1390a3c5bd6dSspeer 	nxge_param_map_t	*vmap, *old_map;
1391a3c5bd6dSspeer 	p_nxge_class_pt_cfg_t	p_class_cfgp;
1392a3c5bd6dSspeer 	uint64_t		cfgd_vlans;
1393a3c5bd6dSspeer 	int			i, inc = 0, cfg_position;
1394a3c5bd6dSspeer 	nxge_mv_cfg_t		*vlan_tbl;
139544961713Sgirish 
139644961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp "));
139744961713Sgirish 
139844961713Sgirish 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
139944961713Sgirish 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
140044961713Sgirish 	p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
140144961713Sgirish 	vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0];
140244961713Sgirish 
140344961713Sgirish 	cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX);
1404a3c5bd6dSspeer 
1405a3c5bd6dSspeer 	/* now do decoding */
140644961713Sgirish 	cfgd_vlans = ((pa->type &  NXGE_PARAM_ARRAY_CNT_MASK) >>
14074045d941Ssowmini 	    NXGE_PARAM_ARRAY_CNT_SHIFT);
140844961713Sgirish 
140944961713Sgirish 	if (cfgd_vlans == NXGE_PARAM_ARRAY_INIT_SIZE) {
141044961713Sgirish 		/*
141144961713Sgirish 		 * for now, we process only upto max
141244961713Sgirish 		 * NXGE_PARAM_ARRAY_INIT_SIZE parameters
141344961713Sgirish 		 * In the future, we may want to expand
141444961713Sgirish 		 * the storage array and continue
141544961713Sgirish 		 */
141644961713Sgirish 		return (EINVAL);
141744961713Sgirish 	}
1418a3c5bd6dSspeer 
141944961713Sgirish 	vmap = (nxge_param_map_t *)&cfg_value;
142044961713Sgirish 	if ((vmap->param_id) &&
14214045d941Ssowmini 	    (vmap->param_id < NXGE_MAX_VLANS) &&
14224045d941Ssowmini 	    (vmap->map_to < p_cfgp->max_rdc_grpids)) {
142344961713Sgirish 		NXGE_DEBUG_MSG((nxgep, NDD_CTL,
14244045d941Ssowmini 		    "nxge_param_set_vlan_rdcgrp mapping"
14254045d941Ssowmini 		    " id %d grp %d",
14264045d941Ssowmini 		    vmap->param_id, vmap->map_to));
1427adfcba55Sjoycey #if defined(__i386)
1428adfcba55Sjoycey 		val_ptr = (uint32_t *)(uint32_t)pa->value;
1429adfcba55Sjoycey #else
143044961713Sgirish 		val_ptr = (uint32_t *)pa->value;
1431adfcba55Sjoycey #endif
1432adfcba55Sjoycey #if defined(__i386)
1433adfcba55Sjoycey 		old_val_ptr = (uint32_t *)(uint32_t)pa->old_value;
1434adfcba55Sjoycey #else
143544961713Sgirish 		old_val_ptr = (uint32_t *)pa->old_value;
1436adfcba55Sjoycey #endif
143744961713Sgirish 
143844961713Sgirish 		/* search to see if this vlan id is already configured */
143944961713Sgirish 		for (i = 0; i < cfgd_vlans; i++) {
144044961713Sgirish 			old_map = (nxge_param_map_t *)&val_ptr[i];
144144961713Sgirish 			if ((old_map->param_id == 0) ||
14424045d941Ssowmini 			    (vmap->param_id == old_map->param_id) ||
14434045d941Ssowmini 			    (vlan_tbl[vmap->param_id].flag)) {
144444961713Sgirish 				cfg_position = i;
144544961713Sgirish 				break;
144644961713Sgirish 			}
144744961713Sgirish 		}
144844961713Sgirish 
144944961713Sgirish 		if (cfgd_vlans == 0) {
145044961713Sgirish 			cfg_position = 0;
145144961713Sgirish 			inc++;
145244961713Sgirish 		}
145344961713Sgirish 
145444961713Sgirish 		if (i == cfgd_vlans) {
145544961713Sgirish 			cfg_position = i;
145644961713Sgirish 			inc++;
145744961713Sgirish 		}
145844961713Sgirish 
145944961713Sgirish 		NXGE_DEBUG_MSG((nxgep, NDD2_CTL,
14604045d941Ssowmini 		    "set_vlan_rdcgrp mapping"
14614045d941Ssowmini 		    " i %d cfgd_vlans %llx position %d ",
14624045d941Ssowmini 		    i, cfgd_vlans, cfg_position));
146344961713Sgirish 		if (val_ptr[cfg_position] != cfg_value) {
146444961713Sgirish 			old_val_ptr[cfg_position] = val_ptr[cfg_position];
146544961713Sgirish 			val_ptr[cfg_position] = cfg_value;
146644961713Sgirish 			vlan_tbl[vmap->param_id].mpr_npr = vmap->pref;
146744961713Sgirish 			vlan_tbl[vmap->param_id].flag = 1;
146844961713Sgirish 			vlan_tbl[vmap->param_id].rdctbl =
1469678453a8Sspeer 			    vmap->map_to + p_cfgp->def_mac_rxdma_grpid;
147044961713Sgirish 			cfg_it = B_TRUE;
147144961713Sgirish 			if (inc) {
147244961713Sgirish 				cfgd_vlans++;
147344961713Sgirish 				pa->type &= ~NXGE_PARAM_ARRAY_CNT_MASK;
147444961713Sgirish 				pa->type |= (cfgd_vlans <<
14754045d941Ssowmini 				    NXGE_PARAM_ARRAY_CNT_SHIFT);
147644961713Sgirish 
147744961713Sgirish 			}
147844961713Sgirish 			NXGE_DEBUG_MSG((nxgep, NDD2_CTL,
14794045d941Ssowmini 			    "after: param_set_vlan_rdcgrp "
14804045d941Ssowmini 			    " cfg_vlans %llx position %d \n",
14814045d941Ssowmini 			    cfgd_vlans, cfg_position));
148244961713Sgirish 		}
148344961713Sgirish 	} else {
148444961713Sgirish 		return (EINVAL);
148544961713Sgirish 	}
148644961713Sgirish 
148744961713Sgirish 	if (cfg_it == B_TRUE) {
148844961713Sgirish 		status = nxge_fflp_config_vlan_table(nxgep,
14894045d941Ssowmini 		    (uint16_t)vmap->param_id);
149044961713Sgirish 		if (status != NXGE_OK)
149144961713Sgirish 			return (EINVAL);
149244961713Sgirish 	}
149344961713Sgirish 
149444961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_vlan_rdcgrp"));
149544961713Sgirish 	return (0);
149644961713Sgirish }
149744961713Sgirish 
149844961713Sgirish /* ARGSUSED */
149944961713Sgirish static int
150044961713Sgirish nxge_param_get_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q,
1501a3c5bd6dSspeer 	mblk_t *mp, caddr_t cp)
150244961713Sgirish {
150344961713Sgirish 
1504a3c5bd6dSspeer 	uint_t 			print_len, buf_len;
1505a3c5bd6dSspeer 	p_mblk_t		np;
1506a3c5bd6dSspeer 	int			i;
1507a3c5bd6dSspeer 	uint32_t		*val_ptr;
1508a3c5bd6dSspeer 	nxge_param_map_t	*vmap;
1509a3c5bd6dSspeer 	p_nxge_param_t		pa = (p_nxge_param_t)cp;
151044961713Sgirish 	p_nxge_class_pt_cfg_t 	p_class_cfgp;
151144961713Sgirish 	p_nxge_dma_pt_cfg_t	p_dma_cfgp;
151244961713Sgirish 	p_nxge_hw_pt_cfg_t	p_cfgp;
1513a3c5bd6dSspeer 	uint64_t		cfgd_vlans = 0;
1514a3c5bd6dSspeer 	nxge_mv_cfg_t		*vlan_tbl;
1515a3c5bd6dSspeer 	int			buff_alloc_size =
15164045d941Ssowmini 	    NXGE_NDD_INFODUMP_BUFF_SIZE * 32;
151744961713Sgirish 
151844961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp "));
1519a3c5bd6dSspeer 	(void) mi_mpprintf(mp, "VLAN RDC Mapping Information for Port\t %d \n",
15204045d941Ssowmini 	    nxgep->function_num);
152144961713Sgirish 
152244961713Sgirish 	if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) {
152344961713Sgirish 		(void) mi_mpprintf(mp, "%s\n", "out of buffer");
152444961713Sgirish 		return (0);
152544961713Sgirish 	}
1526a3c5bd6dSspeer 
152744961713Sgirish 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
152844961713Sgirish 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
152944961713Sgirish 
153044961713Sgirish 	buf_len = buff_alloc_size;
153144961713Sgirish 	mp->b_cont = np;
153244961713Sgirish 	cfgd_vlans = (pa->type &  NXGE_PARAM_ARRAY_CNT_MASK) >>
15334045d941Ssowmini 	    NXGE_PARAM_ARRAY_CNT_SHIFT;
153444961713Sgirish 
153544961713Sgirish 	i = (int)cfgd_vlans;
153644961713Sgirish 	p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
153744961713Sgirish 	vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0];
153844961713Sgirish 	print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
15394045d941Ssowmini 	    "Configured VLANs %d\n"
15404045d941Ssowmini 	    "VLAN ID\t RDC GRP (Actual/Port)\t"
15414045d941Ssowmini 	    " Prefernce\n", i);
154244961713Sgirish 	((mblk_t *)np)->b_wptr += print_len;
154344961713Sgirish 	buf_len -= print_len;
1544adfcba55Sjoycey #if defined(__i386)
1545adfcba55Sjoycey 	val_ptr = (uint32_t *)(uint32_t)pa->value;
1546adfcba55Sjoycey #else
154744961713Sgirish 	val_ptr = (uint32_t *)pa->value;
1548adfcba55Sjoycey #endif
154944961713Sgirish 
155044961713Sgirish 	for (i = 0; i < cfgd_vlans; i++) {
155144961713Sgirish 		vmap = (nxge_param_map_t *)&val_ptr[i];
155244961713Sgirish 		if (p_class_cfgp->vlan_tbl[vmap->param_id].flag) {
155344961713Sgirish 			print_len = snprintf((char *)((mblk_t *)np)->b_wptr,
15544045d941Ssowmini 			    buf_len,
15554045d941Ssowmini 			    "  %d\t\t %d/%d\t\t %d\n",
15564045d941Ssowmini 			    vmap->param_id,
15574045d941Ssowmini 			    vlan_tbl[vmap->param_id].rdctbl,
15584045d941Ssowmini 			    vlan_tbl[vmap->param_id].rdctbl -
15594045d941Ssowmini 			    p_cfgp->def_mac_rxdma_grpid,
15604045d941Ssowmini 			    vlan_tbl[vmap->param_id].mpr_npr);
156144961713Sgirish 			((mblk_t *)np)->b_wptr += print_len;
156244961713Sgirish 			buf_len -= print_len;
156344961713Sgirish 		}
156444961713Sgirish 	}
156544961713Sgirish 
156644961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_vlan_rdcgrp"));
156744961713Sgirish 	return (0);
156844961713Sgirish }
156944961713Sgirish 
157044961713Sgirish /* ARGSUSED */
157144961713Sgirish static int
157244961713Sgirish nxge_param_get_mac_rdcgrp(p_nxge_t nxgep, queue_t *q,
1573a3c5bd6dSspeer 	mblk_t *mp, caddr_t cp)
157444961713Sgirish {
1575a3c5bd6dSspeer 	uint_t			print_len, buf_len;
1576a3c5bd6dSspeer 	p_mblk_t		np;
1577a3c5bd6dSspeer 	int			i;
157844961713Sgirish 	p_nxge_class_pt_cfg_t 	p_class_cfgp;
157944961713Sgirish 	p_nxge_dma_pt_cfg_t	p_dma_cfgp;
158044961713Sgirish 	p_nxge_hw_pt_cfg_t	p_cfgp;
1581a3c5bd6dSspeer 	nxge_mv_cfg_t		*mac_host_info;
158244961713Sgirish 
158344961713Sgirish 	int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE * 32;
158444961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac_rdcgrp "));
158544961713Sgirish 	(void) mi_mpprintf(mp,
15864045d941Ssowmini 	    "MAC ADDR RDC Mapping Information for Port\t %d\n",
15874045d941Ssowmini 	    nxgep->function_num);
158844961713Sgirish 
158944961713Sgirish 	if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) {
159044961713Sgirish 		(void) mi_mpprintf(mp, "%s\n", "out of buffer");
159144961713Sgirish 		return (0);
159244961713Sgirish 	}
159344961713Sgirish 
159444961713Sgirish 	buf_len = buff_alloc_size;
159544961713Sgirish 	mp->b_cont = np;
159644961713Sgirish 	p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
159744961713Sgirish 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
159844961713Sgirish 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
159944961713Sgirish 	mac_host_info = (nxge_mv_cfg_t	*)&p_class_cfgp->mac_host_info[0];
160044961713Sgirish 	print_len = snprintf((char *)np->b_wptr, buf_len,
16014045d941Ssowmini 	    "MAC ID\t RDC GRP (Actual/Port)\t"
16024045d941Ssowmini 	    " Prefernce\n");
160344961713Sgirish 	((mblk_t *)np)->b_wptr += print_len;
160444961713Sgirish 	buf_len -= print_len;
160544961713Sgirish 	for (i = 0; i < p_cfgp->max_macs; i++) {
160644961713Sgirish 		if (mac_host_info[i].flag) {
160744961713Sgirish 			print_len = snprintf((char *)((mblk_t *)np)->b_wptr,
16084045d941Ssowmini 			    buf_len,
16094045d941Ssowmini 			    "   %d\t  %d/%d\t\t %d\n",
16104045d941Ssowmini 			    i, mac_host_info[i].rdctbl,
16114045d941Ssowmini 			    mac_host_info[i].rdctbl -
16124045d941Ssowmini 			    p_cfgp->def_mac_rxdma_grpid,
16134045d941Ssowmini 			    mac_host_info[i].mpr_npr);
161444961713Sgirish 			((mblk_t *)np)->b_wptr += print_len;
161544961713Sgirish 			buf_len -= print_len;
161644961713Sgirish 		}
161744961713Sgirish 	}
161844961713Sgirish 	print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
16194045d941Ssowmini 	    "Done Info Dumping \n");
162044961713Sgirish 	((mblk_t *)np)->b_wptr += print_len;
162144961713Sgirish 	buf_len -= print_len;
162244961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_macrdcgrp"));
162344961713Sgirish 	return (0);
162444961713Sgirish }
162544961713Sgirish 
162644961713Sgirish /* ARGSUSED */
162744961713Sgirish static int
162844961713Sgirish nxge_param_tcam_enable(p_nxge_t nxgep, queue_t *q,
1629a3c5bd6dSspeer 	mblk_t *mp, char *value, caddr_t cp)
163044961713Sgirish {
1631a3c5bd6dSspeer 	uint32_t	status = 0, cfg_value;
1632a3c5bd6dSspeer 	p_nxge_param_t	pa = (p_nxge_param_t)cp;
1633a3c5bd6dSspeer 	uint32_t	cfg_it = B_FALSE;
1634a3c5bd6dSspeer 	char		*end;
163544961713Sgirish 
163644961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_tcam_enable"));
163744961713Sgirish 
163844961713Sgirish 	cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY);
163944961713Sgirish 	if (pa->value != cfg_value) {
164044961713Sgirish 		pa->old_value = pa->value;
164144961713Sgirish 		pa->value = cfg_value;
164244961713Sgirish 		cfg_it = B_TRUE;
164344961713Sgirish 	}
164444961713Sgirish 
164544961713Sgirish 	if (cfg_it == B_TRUE) {
164644961713Sgirish 		if (pa->value)
164744961713Sgirish 			status = nxge_fflp_config_tcam_enable(nxgep);
164844961713Sgirish 		else
164944961713Sgirish 			status = nxge_fflp_config_tcam_disable(nxgep);
165044961713Sgirish 		if (status != NXGE_OK)
165144961713Sgirish 			return (EINVAL);
165244961713Sgirish 	}
165344961713Sgirish 
165444961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_tcam_enable"));
165544961713Sgirish 	return (0);
165644961713Sgirish }
165744961713Sgirish 
165844961713Sgirish /* ARGSUSED */
165944961713Sgirish static int
166044961713Sgirish nxge_param_hash_lookup_enable(p_nxge_t nxgep, queue_t *q,
1661a3c5bd6dSspeer 	mblk_t *mp, char *value, caddr_t cp)
166244961713Sgirish {
1663a3c5bd6dSspeer 	uint32_t	status = 0, cfg_value;
1664a3c5bd6dSspeer 	p_nxge_param_t	pa = (p_nxge_param_t)cp;
1665a3c5bd6dSspeer 	uint32_t	cfg_it = B_FALSE;
1666a3c5bd6dSspeer 	char		*end;
166744961713Sgirish 
166844961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_hash_lookup_enable"));
166944961713Sgirish 
167044961713Sgirish 	cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY);
167144961713Sgirish 	if (pa->value != cfg_value) {
167244961713Sgirish 		pa->old_value = pa->value;
167344961713Sgirish 		pa->value = cfg_value;
167444961713Sgirish 		cfg_it = B_TRUE;
167544961713Sgirish 	}
167644961713Sgirish 
167744961713Sgirish 	if (cfg_it == B_TRUE) {
167844961713Sgirish 		if (pa->value)
167944961713Sgirish 			status = nxge_fflp_config_hash_lookup_enable(nxgep);
168044961713Sgirish 		else
168144961713Sgirish 			status = nxge_fflp_config_hash_lookup_disable(nxgep);
168244961713Sgirish 		if (status != NXGE_OK)
168344961713Sgirish 			return (EINVAL);
168444961713Sgirish 	}
168544961713Sgirish 
168644961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_hash_lookup_enable"));
168744961713Sgirish 	return (0);
168844961713Sgirish }
168944961713Sgirish 
169044961713Sgirish /* ARGSUSED */
169144961713Sgirish static int
169244961713Sgirish nxge_param_llc_snap_enable(p_nxge_t nxgep, queue_t *q,
1693a3c5bd6dSspeer 	mblk_t *mp, char *value, caddr_t cp)
169444961713Sgirish {
1695a3c5bd6dSspeer 	char		*end;
1696a3c5bd6dSspeer 	uint32_t	status = 0, cfg_value;
1697a3c5bd6dSspeer 	p_nxge_param_t	pa = (p_nxge_param_t)cp;
1698a3c5bd6dSspeer 	uint32_t	cfg_it = B_FALSE;
169944961713Sgirish 
170044961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_llc_snap_enable"));
170144961713Sgirish 
170244961713Sgirish 	cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY);
170344961713Sgirish 	if (pa->value != cfg_value) {
170444961713Sgirish 		pa->old_value = pa->value;
170544961713Sgirish 		pa->value = cfg_value;
170644961713Sgirish 		cfg_it = B_TRUE;
170744961713Sgirish 	}
170844961713Sgirish 
170944961713Sgirish 	if (cfg_it == B_TRUE) {
171044961713Sgirish 		if (pa->value)
171144961713Sgirish 			status = nxge_fflp_config_tcam_enable(nxgep);
171244961713Sgirish 		else
171344961713Sgirish 			status = nxge_fflp_config_tcam_disable(nxgep);
171444961713Sgirish 		if (status != NXGE_OK)
171544961713Sgirish 			return (EINVAL);
171644961713Sgirish 	}
171744961713Sgirish 
171844961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_llc_snap_enable"));
171944961713Sgirish 	return (0);
172044961713Sgirish }
172144961713Sgirish 
172244961713Sgirish /* ARGSUSED */
172344961713Sgirish static int
172444961713Sgirish nxge_param_set_ether_usr(p_nxge_t nxgep, queue_t *q,
1725a3c5bd6dSspeer 	mblk_t	*mp, char *value, caddr_t cp)
172644961713Sgirish {
1727a3c5bd6dSspeer 	char		*end;
1728a3c5bd6dSspeer 	uint8_t		ether_class;
1729a3c5bd6dSspeer 	uint32_t	status = 0, cfg_value;
1730a3c5bd6dSspeer 	p_nxge_param_t	pa = (p_nxge_param_t)cp;
1731a3c5bd6dSspeer 	uint8_t		cfg_it = B_FALSE;
173244961713Sgirish 
173344961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ether_usr"));
173444961713Sgirish 
173544961713Sgirish 	cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX);
173644961713Sgirish 	if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) {
173744961713Sgirish 		return (EINVAL);
173844961713Sgirish 	}
1739a3c5bd6dSspeer 
174044961713Sgirish 	if (pa->value != cfg_value) {
174144961713Sgirish 		pa->old_value = pa->value;
174244961713Sgirish 		pa->value = cfg_value;
174344961713Sgirish 		cfg_it = B_TRUE;
174444961713Sgirish 	}
174544961713Sgirish 
174644961713Sgirish 	/* do the actual hw setup  */
174744961713Sgirish 	if (cfg_it == B_TRUE) {
174844961713Sgirish 		ether_class = mi_strtol(pa->name, &end, 10);
174944961713Sgirish #ifdef lint
175044961713Sgirish 		ether_class = ether_class;
175144961713Sgirish #endif
175244961713Sgirish 		NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_ether_usr"));
175344961713Sgirish 	}
1754a3c5bd6dSspeer 
175544961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ether_usr"));
175644961713Sgirish 	return (status);
175744961713Sgirish }
175844961713Sgirish 
175944961713Sgirish /* ARGSUSED */
176044961713Sgirish static int
176144961713Sgirish nxge_param_set_ip_usr(p_nxge_t nxgep, queue_t *q,
1762a3c5bd6dSspeer 	mblk_t *mp, char *value, caddr_t cp)
176344961713Sgirish {
1764a3c5bd6dSspeer 	char		*end;
1765a3c5bd6dSspeer 	tcam_class_t	class;
1766a3c5bd6dSspeer 	uint32_t	status, cfg_value;
1767a3c5bd6dSspeer 	p_nxge_param_t	pa = (p_nxge_param_t)cp;
1768a3c5bd6dSspeer 	uint32_t	cfg_it = B_FALSE;
176944961713Sgirish 
177044961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_usr"));
177144961713Sgirish 
177244961713Sgirish 	cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX);
177344961713Sgirish 	if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) {
177444961713Sgirish 		return (EINVAL);
177544961713Sgirish 	}
177644961713Sgirish 
177744961713Sgirish 	if (pa->value != cfg_value) {
177844961713Sgirish 		pa->old_value = pa->value;
177944961713Sgirish 		pa->value = cfg_value;
178044961713Sgirish 		cfg_it = B_TRUE;
178144961713Sgirish 	}
178244961713Sgirish 
178344961713Sgirish 	/* do the actual hw setup with cfg_value. */
178444961713Sgirish 	if (cfg_it == B_TRUE) {
178544961713Sgirish 		class = mi_strtol(pa->name, &end, 10);
178644961713Sgirish 		status = nxge_fflp_ip_usr_class_config(nxgep, class, pa->value);
178744961713Sgirish 	}
178844961713Sgirish 
178944961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_usr"));
179044961713Sgirish 	return (status);
179144961713Sgirish }
179244961713Sgirish 
1793a3c5bd6dSspeer /* ARGSUSED */
179444961713Sgirish static int
179544961713Sgirish nxge_class_name_2value(p_nxge_t nxgep, char *name)
179644961713Sgirish {
1797a3c5bd6dSspeer 	int		i;
1798a3c5bd6dSspeer 	int		class_instance = param_class_opt_ip_usr4;
1799a3c5bd6dSspeer 	p_nxge_param_t	param_arr;
1800a3c5bd6dSspeer 
180144961713Sgirish 	param_arr = nxgep->param_arr;
180244961713Sgirish 	for (i = TCAM_CLASS_IP_USER_4; i <= TCAM_CLASS_SCTP_IPV6; i++) {
180344961713Sgirish 		if (strcmp(param_arr[class_instance].name, name) == 0)
180444961713Sgirish 			return (i);
180544961713Sgirish 		class_instance++;
180644961713Sgirish 	}
180744961713Sgirish 	return (-1);
180844961713Sgirish }
180944961713Sgirish 
181044961713Sgirish /* ARGSUSED */
18111bd6825cSml int
181244961713Sgirish nxge_param_set_ip_opt(p_nxge_t nxgep, queue_t *q,
1813a3c5bd6dSspeer 	mblk_t *mp, char *value, caddr_t cp)
181444961713Sgirish {
1815a3c5bd6dSspeer 	char		*end;
1816a3c5bd6dSspeer 	uint32_t	status, cfg_value;
1817a3c5bd6dSspeer 	p_nxge_param_t	pa = (p_nxge_param_t)cp;
1818a3c5bd6dSspeer 	tcam_class_t	class;
1819a3c5bd6dSspeer 	uint32_t	cfg_it = B_FALSE;
182044961713Sgirish 
182144961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_opt"));
182244961713Sgirish 
182344961713Sgirish 	cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX);
182444961713Sgirish 	if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) {
182544961713Sgirish 		return (EINVAL);
182644961713Sgirish 	}
182744961713Sgirish 
182844961713Sgirish 	if (pa->value != cfg_value) {
182944961713Sgirish 		pa->old_value = pa->value;
183044961713Sgirish 		pa->value = cfg_value;
183144961713Sgirish 		cfg_it = B_TRUE;
183244961713Sgirish 	}
183344961713Sgirish 
183444961713Sgirish 	if (cfg_it == B_TRUE) {
1835a3c5bd6dSspeer 		/* do the actual hw setup  */
183644961713Sgirish 		class = nxge_class_name_2value(nxgep, pa->name);
183744961713Sgirish 		if (class == -1)
183844961713Sgirish 			return (EINVAL);
183944961713Sgirish 
184044961713Sgirish 		status = nxge_fflp_ip_class_config(nxgep, class, pa->value);
184144961713Sgirish 		if (status != NXGE_OK)
184244961713Sgirish 			return (EINVAL);
184344961713Sgirish 	}
184444961713Sgirish 
184544961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_opt"));
184644961713Sgirish 	return (0);
184744961713Sgirish }
184844961713Sgirish 
184944961713Sgirish /* ARGSUSED */
185044961713Sgirish static int
185144961713Sgirish nxge_param_get_ip_opt(p_nxge_t nxgep, queue_t *q,
1852a3c5bd6dSspeer 	mblk_t *mp, caddr_t cp)
185344961713Sgirish {
185444961713Sgirish 	uint32_t status, cfg_value;
185544961713Sgirish 	p_nxge_param_t pa = (p_nxge_param_t)cp;
185644961713Sgirish 	tcam_class_t class;
185744961713Sgirish 
185844961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_ip_opt"));
185944961713Sgirish 
1860a3c5bd6dSspeer 	/* do the actual hw setup  */
186144961713Sgirish 	class = nxge_class_name_2value(nxgep, pa->name);
186244961713Sgirish 	if (class == -1)
186344961713Sgirish 		return (EINVAL);
1864a3c5bd6dSspeer 
186544961713Sgirish 	cfg_value = 0;
186644961713Sgirish 	status = nxge_fflp_ip_class_config_get(nxgep, class, &cfg_value);
186744961713Sgirish 	if (status != NXGE_OK)
186844961713Sgirish 		return (EINVAL);
1869a3c5bd6dSspeer 
187044961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL,
18714045d941Ssowmini 	    "nxge_param_get_ip_opt_get %x ", cfg_value));
187244961713Sgirish 
1873a3c5bd6dSspeer 	pa->value = cfg_value;
187444961713Sgirish 	(void) mi_mpprintf(mp, "%x", cfg_value);
1875a3c5bd6dSspeer 
187644961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_ip_opt status "));
187744961713Sgirish 	return (0);
187844961713Sgirish }
187944961713Sgirish 
188044961713Sgirish /* ARGSUSED */
188144961713Sgirish static int
188244961713Sgirish nxge_param_fflp_hash_init(p_nxge_t nxgep, queue_t *q,
1883a3c5bd6dSspeer 	mblk_t *mp, char *value, caddr_t cp)
188444961713Sgirish {
1885a3c5bd6dSspeer 	char		*end;
1886a3c5bd6dSspeer 	uint32_t	status, cfg_value;
1887a3c5bd6dSspeer 	p_nxge_param_t	pa = (p_nxge_param_t)cp;
1888a3c5bd6dSspeer 	tcam_class_t	class;
1889a3c5bd6dSspeer 	uint32_t	cfg_it = B_FALSE;
189044961713Sgirish 
189144961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_fflp_hash_init"));
189244961713Sgirish 
189344961713Sgirish 	cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX);
189444961713Sgirish 	if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) {
189544961713Sgirish 		return (EINVAL);
189644961713Sgirish 	}
189744961713Sgirish 
189844961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL,
18994045d941Ssowmini 	    "nxge_param_fflp_hash_init value %x", cfg_value));
1900a3c5bd6dSspeer 
190144961713Sgirish 	if (pa->value != cfg_value) {
190244961713Sgirish 		pa->old_value = pa->value;
190344961713Sgirish 		pa->value = cfg_value;
190444961713Sgirish 		cfg_it = B_TRUE;
190544961713Sgirish 	}
190644961713Sgirish 
190744961713Sgirish 	if (cfg_it == B_TRUE) {
190844961713Sgirish 		char *h_name;
1909a3c5bd6dSspeer 
191044961713Sgirish 		/* do the actual hw setup */
191144961713Sgirish 		h_name = pa->name;
191244961713Sgirish 		h_name++;
191344961713Sgirish 		class = mi_strtol(h_name, &end, 10);
191444961713Sgirish 		switch (class) {
191544961713Sgirish 			case 1:
191644961713Sgirish 				status = nxge_fflp_set_hash1(nxgep,
19174045d941Ssowmini 				    (uint32_t)pa->value);
191844961713Sgirish 				break;
191944961713Sgirish 			case 2:
192044961713Sgirish 				status = nxge_fflp_set_hash2(nxgep,
19214045d941Ssowmini 				    (uint16_t)pa->value);
192244961713Sgirish 				break;
192344961713Sgirish 
192444961713Sgirish 			default:
192544961713Sgirish 			NXGE_DEBUG_MSG((nxgep, NDD_CTL,
19264045d941Ssowmini 			    " nxge_param_fflp_hash_init"
19274045d941Ssowmini 			    " %s Wrong hash var %d",
19284045d941Ssowmini 			    pa->name, class));
192944961713Sgirish 			return (EINVAL);
193044961713Sgirish 		}
193144961713Sgirish 		if (status != NXGE_OK)
193244961713Sgirish 			return (EINVAL);
193344961713Sgirish 	}
193444961713Sgirish 
193544961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_fflp_hash_init"));
193644961713Sgirish 	return (0);
193744961713Sgirish }
193844961713Sgirish 
193944961713Sgirish /* ARGSUSED */
194044961713Sgirish static int
194144961713Sgirish nxge_param_set_grp_rdc(p_nxge_t nxgep, queue_t *q,
1942a3c5bd6dSspeer 	mblk_t *mp, char *value, caddr_t cp)
194344961713Sgirish {
1944a3c5bd6dSspeer 	char			*end;
1945a3c5bd6dSspeer 	uint32_t		status = 0, cfg_value;
1946a3c5bd6dSspeer 	p_nxge_param_t		pa = (p_nxge_param_t)cp;
1947a3c5bd6dSspeer 	uint32_t		cfg_it = B_FALSE;
1948a3c5bd6dSspeer 	int			rdc_grp;
1949a3c5bd6dSspeer 	uint8_t			real_rdc;
195044961713Sgirish 	p_nxge_dma_pt_cfg_t	p_dma_cfgp;
195144961713Sgirish 	p_nxge_hw_pt_cfg_t	p_cfgp;
195244961713Sgirish 	p_nxge_rdc_grp_t	rdc_grp_p;
195344961713Sgirish 
195444961713Sgirish 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
195544961713Sgirish 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
195644961713Sgirish 
195744961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_grp_rdc"));
195844961713Sgirish 
195944961713Sgirish 	cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY);
196044961713Sgirish 	if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) {
196144961713Sgirish 		return (EINVAL);
196244961713Sgirish 	}
1963a3c5bd6dSspeer 
196444961713Sgirish 	if (cfg_value >= p_cfgp->max_rdcs) {
196544961713Sgirish 		return (EINVAL);
196644961713Sgirish 	}
1967a3c5bd6dSspeer 
196844961713Sgirish 	if (pa->value != cfg_value) {
196944961713Sgirish 		pa->old_value = pa->value;
197044961713Sgirish 		pa->value = cfg_value;
197144961713Sgirish 		cfg_it = B_TRUE;
197244961713Sgirish 	}
197344961713Sgirish 
197444961713Sgirish 	if (cfg_it == B_TRUE) {
197544961713Sgirish 		char *grp_name;
197644961713Sgirish 		grp_name = pa->name;
197744961713Sgirish 		grp_name += strlen("default-grp");
197844961713Sgirish 		rdc_grp = mi_strtol(grp_name, &end, 10);
197944961713Sgirish 		rdc_grp_p = &p_dma_cfgp->rdc_grps[rdc_grp];
198044961713Sgirish 		real_rdc = rdc_grp_p->start_rdc + cfg_value;
198144961713Sgirish 		if (nxge_check_rxdma_rdcgrp_member(nxgep, rdc_grp,
19824045d941Ssowmini 		    cfg_value) == B_FALSE) {
198344961713Sgirish 			pa->value = pa->old_value;
198444961713Sgirish 			NXGE_DEBUG_MSG((nxgep, NDD_CTL,
19854045d941Ssowmini 			    " nxge_param_set_grp_rdc"
19864045d941Ssowmini 			    " %d read %d actual %d outof range",
19874045d941Ssowmini 			    rdc_grp, cfg_value, real_rdc));
198844961713Sgirish 			return (EINVAL);
198944961713Sgirish 		}
199044961713Sgirish 		status = nxge_rxdma_cfg_rdcgrp_default_rdc(nxgep, rdc_grp,
19914045d941Ssowmini 		    real_rdc);
199244961713Sgirish 		if (status != NXGE_OK)
199344961713Sgirish 			return (EINVAL);
199444961713Sgirish 	}
199544961713Sgirish 
199644961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_grp_rdc"));
199744961713Sgirish 	return (0);
199844961713Sgirish }
199944961713Sgirish 
200044961713Sgirish /* ARGSUSED */
200144961713Sgirish static int
200244961713Sgirish nxge_param_set_port_rdc(p_nxge_t nxgep, queue_t *q,
2003a3c5bd6dSspeer 	mblk_t *mp, char *value, caddr_t cp)
200444961713Sgirish {
2005a3c5bd6dSspeer 	char		*end;
2006a3c5bd6dSspeer 	uint32_t	status = B_TRUE, cfg_value;
2007a3c5bd6dSspeer 	p_nxge_param_t	pa = (p_nxge_param_t)cp;
2008a3c5bd6dSspeer 	uint32_t	cfg_it = B_FALSE;
200944961713Sgirish 
201044961713Sgirish 	p_nxge_dma_pt_cfg_t	p_dma_cfgp;
201144961713Sgirish 	p_nxge_hw_pt_cfg_t	p_cfgp;
201244961713Sgirish 
201344961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_port_rdc"));
201444961713Sgirish 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
201544961713Sgirish 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
201644961713Sgirish 
201744961713Sgirish 	cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY);
201844961713Sgirish 	if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) {
201944961713Sgirish 		return (EINVAL);
202044961713Sgirish 	}
2021a3c5bd6dSspeer 
202244961713Sgirish 	if (pa->value != cfg_value) {
202344961713Sgirish 		if (cfg_value >= p_cfgp->max_rdcs)
202444961713Sgirish 			return (EINVAL);
202544961713Sgirish 		pa->old_value = pa->value;
202644961713Sgirish 		pa->value = cfg_value;
202744961713Sgirish 		cfg_it = B_TRUE;
202844961713Sgirish 	}
202944961713Sgirish 
203044961713Sgirish 	if (cfg_it == B_TRUE) {
2031678453a8Sspeer 		int rdc;
2032678453a8Sspeer 		if ((rdc = nxge_dci_map(nxgep, VP_BOUND_RX, cfg_value)) < 0)
2033678453a8Sspeer 			return (EINVAL);
203444961713Sgirish 		status = nxge_rxdma_cfg_port_default_rdc(nxgep,
2035678453a8Sspeer 		    nxgep->function_num, rdc);
203644961713Sgirish 		if (status != NXGE_OK)
203744961713Sgirish 			return (EINVAL);
203844961713Sgirish 	}
203944961713Sgirish 
204044961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_port_rdc"));
204144961713Sgirish 	return (0);
204244961713Sgirish }
204344961713Sgirish 
204444961713Sgirish /* ARGSUSED */
204544961713Sgirish static int
204644961713Sgirish nxge_param_set_nxge_debug_flag(p_nxge_t nxgep, queue_t *q,
2047a3c5bd6dSspeer 	mblk_t *mp, char *value, caddr_t cp)
204844961713Sgirish {
204944961713Sgirish 	char *end;
205044961713Sgirish 	uint32_t status = 0;
205144961713Sgirish 	uint64_t cfg_value = 0;
205244961713Sgirish 	p_nxge_param_t pa = (p_nxge_param_t)cp;
205344961713Sgirish 	uint32_t cfg_it = B_FALSE;
205444961713Sgirish 
205544961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_nxge_debug_flag"));
205644961713Sgirish 	cfg_value = mi_strtol(value, &end, BASE_HEX);
205744961713Sgirish 
205844961713Sgirish 	if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) {
205944961713Sgirish 		NXGE_DEBUG_MSG((nxgep, NDD_CTL,
20604045d941Ssowmini 		    " nxge_param_set_nxge_debug_flag"
20614045d941Ssowmini 		    " outof range %llx", cfg_value));
206244961713Sgirish 		return (EINVAL);
206344961713Sgirish 	}
206444961713Sgirish 	if (pa->value != cfg_value) {
206544961713Sgirish 		pa->old_value = pa->value;
206644961713Sgirish 		pa->value = cfg_value;
206744961713Sgirish 		cfg_it = B_TRUE;
206844961713Sgirish 	}
206944961713Sgirish 
207044961713Sgirish 	if (cfg_it == B_TRUE) {
207144961713Sgirish 		nxgep->nxge_debug_level = pa->value;
207244961713Sgirish 	}
2073a3c5bd6dSspeer 
207444961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_nxge_debug_flag"));
207544961713Sgirish 	return (status);
207644961713Sgirish }
207744961713Sgirish 
207844961713Sgirish /* ARGSUSED */
207944961713Sgirish static int
208044961713Sgirish nxge_param_get_debug_flag(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
208144961713Sgirish {
2082a3c5bd6dSspeer 	int		status = 0;
2083a3c5bd6dSspeer 	p_nxge_param_t	pa = (p_nxge_param_t)cp;
208444961713Sgirish 
208544961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_debug_flag"));
208644961713Sgirish 
208744961713Sgirish 	if (pa->value > 0xffffffff)
208844961713Sgirish 		(void) mi_mpprintf(mp, "%x%x",  (int)(pa->value >> 32),
20894045d941Ssowmini 		    (int)(pa->value & 0xffffffff));
209044961713Sgirish 	else
209144961713Sgirish 		(void) mi_mpprintf(mp, "%x", (int)pa->value);
209244961713Sgirish 
209344961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_debug_flag"));
209444961713Sgirish 	return (status);
209544961713Sgirish }
209644961713Sgirish 
209744961713Sgirish /* ARGSUSED */
209844961713Sgirish static int
209944961713Sgirish nxge_param_set_npi_debug_flag(p_nxge_t nxgep, queue_t *q,
2100a3c5bd6dSspeer 	mblk_t *mp, char *value, caddr_t cp)
210144961713Sgirish {
2102a3c5bd6dSspeer 	char		*end;
2103a3c5bd6dSspeer 	uint32_t	status = 0;
2104a3c5bd6dSspeer 	uint64_t	 cfg_value = 0;
2105a3c5bd6dSspeer 	p_nxge_param_t	pa;
2106a3c5bd6dSspeer 	uint32_t	cfg_it = B_FALSE;
210744961713Sgirish 
210844961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_npi_debug_flag"));
210944961713Sgirish 	cfg_value = mi_strtol(value, &end, BASE_HEX);
211044961713Sgirish 	pa = (p_nxge_param_t)cp;
211144961713Sgirish 	if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) {
211244961713Sgirish 		NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_npi_debug_flag"
21134045d941Ssowmini 		    " outof range %llx", cfg_value));
211444961713Sgirish 		return (EINVAL);
211544961713Sgirish 	}
211644961713Sgirish 	if (pa->value != cfg_value) {
211744961713Sgirish 		pa->old_value = pa->value;
211844961713Sgirish 		pa->value = cfg_value;
211944961713Sgirish 		cfg_it = B_TRUE;
212044961713Sgirish 	}
212144961713Sgirish 
212244961713Sgirish 	if (cfg_it == B_TRUE) {
212344961713Sgirish 		npi_debug_level = pa->value;
212444961713Sgirish 	}
212544961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_debug_flag"));
212644961713Sgirish 	return (status);
212744961713Sgirish }
212844961713Sgirish 
212944961713Sgirish /* ARGSUSED */
213044961713Sgirish static int
213144961713Sgirish nxge_param_dump_rdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
213244961713Sgirish {
2133678453a8Sspeer 	nxge_grp_set_t *set = &nxgep->rx_set;
2134678453a8Sspeer 	int rdc;
213544961713Sgirish 
213644961713Sgirish 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_rdc"));
213744961713Sgirish 
2138678453a8Sspeer 	if (!isLDOMguest(nxgep))
21394045d941Ssowmini 		(void) npi_rxdma_dump_fzc_regs(NXGE_DEV_NPI_HANDLE(nxgep));
2140678453a8Sspeer 
2141678453a8Sspeer 	for (rdc = 0; rdc < NXGE_MAX_TDCS; rdc++) {
2142678453a8Sspeer 		if ((1 << rdc) & set->owned.map) {
2143678453a8Sspeer 			(void) nxge_dump_rxdma_channel(nxgep, rdc);
2144678453a8Sspeer 		}
2145678453a8Sspeer 	}
214644961713Sgirish 
214744961713Sgirish 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_rdc"));
214844961713Sgirish 	return (0);
214944961713Sgirish }
215044961713Sgirish 
215144961713Sgirish /* ARGSUSED */
215244961713Sgirish static int
215344961713Sgirish nxge_param_dump_tdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
215444961713Sgirish {
2155678453a8Sspeer 	nxge_grp_set_t *set = &nxgep->tx_set;
2156678453a8Sspeer 	int tdc;
215744961713Sgirish 
215844961713Sgirish 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_tdc"));
215944961713Sgirish 
2160678453a8Sspeer 	for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) {
2161678453a8Sspeer 		if ((1 << tdc) & set->owned.map) {
2162678453a8Sspeer 			(void) nxge_txdma_regs_dump(nxgep, tdc);
2163678453a8Sspeer 		}
2164678453a8Sspeer 	}
216544961713Sgirish 
216644961713Sgirish 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_tdc"));
216744961713Sgirish 	return (0);
216844961713Sgirish }
216944961713Sgirish 
217044961713Sgirish /* ARGSUSED */
217144961713Sgirish static int
217244961713Sgirish nxge_param_dump_fflp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
217344961713Sgirish {
217444961713Sgirish 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_fflp_regs"));
217544961713Sgirish 
217644961713Sgirish 	(void) npi_fflp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep));
217744961713Sgirish 
217844961713Sgirish 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_fflp_regs"));
217944961713Sgirish 	return (0);
218044961713Sgirish }
218144961713Sgirish 
218244961713Sgirish /* ARGSUSED */
218344961713Sgirish static int
218444961713Sgirish nxge_param_dump_mac_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
218544961713Sgirish {
218644961713Sgirish 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_mac_regs"));
218744961713Sgirish 
218844961713Sgirish 	(void) npi_mac_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep),
21894045d941Ssowmini 	    nxgep->function_num);
219044961713Sgirish 
219144961713Sgirish 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_mac_regs"));
219244961713Sgirish 	return (0);
219344961713Sgirish }
219444961713Sgirish 
219544961713Sgirish /* ARGSUSED */
219644961713Sgirish static int
219744961713Sgirish nxge_param_dump_ipp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
219844961713Sgirish {
219944961713Sgirish 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_ipp_regs"));
220044961713Sgirish 
2201a3c5bd6dSspeer 	(void) npi_ipp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep),
22024045d941Ssowmini 	    nxgep->function_num);
220344961713Sgirish 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ipp_regs"));
220444961713Sgirish 	return (0);
220544961713Sgirish }
220644961713Sgirish 
220744961713Sgirish /* ARGSUSED */
220844961713Sgirish static int
220944961713Sgirish nxge_param_dump_vlan_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
221044961713Sgirish {
221144961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_vlan_table"));
221244961713Sgirish 
221344961713Sgirish 	(void) npi_fflp_vlan_tbl_dump(NXGE_DEV_NPI_HANDLE(nxgep));
221444961713Sgirish 
221544961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_vlan_table"));
221644961713Sgirish 	return (0);
221744961713Sgirish }
221844961713Sgirish 
221944961713Sgirish /* ARGSUSED */
222044961713Sgirish static int
222144961713Sgirish nxge_param_dump_rdc_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
222244961713Sgirish {
2223a3c5bd6dSspeer 	uint8_t	table;
222444961713Sgirish 
222544961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_rdc_table"));
222644961713Sgirish 	for (table = 0; table < NXGE_MAX_RDC_GROUPS; table++) {
222744961713Sgirish 		(void) npi_rxdma_dump_rdc_table(NXGE_DEV_NPI_HANDLE(nxgep),
22284045d941Ssowmini 		    table);
222944961713Sgirish 	}
2230a3c5bd6dSspeer 
223144961713Sgirish 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_rdc_table"));
223244961713Sgirish 	return (0);
223344961713Sgirish }
223444961713Sgirish 
223544961713Sgirish typedef struct block_info {
223644961713Sgirish 	char		*name;
223744961713Sgirish 	uint32_t	offset;
223844961713Sgirish } block_info_t;
223944961713Sgirish 
224044961713Sgirish block_info_t reg_block[] = {
224144961713Sgirish 	{"PIO",		PIO},
224244961713Sgirish 	{"FZC_PIO",	FZC_PIO},
224344961713Sgirish 	{"FZC_XMAC",	FZC_MAC},
224444961713Sgirish 	{"FZC_IPP",	FZC_IPP},
224544961713Sgirish 	{"FFLP",	FFLP},
224644961713Sgirish 	{"FZC_FFLP",	FZC_FFLP},
224744961713Sgirish 	{"PIO_VADDR",	PIO_VADDR},
224844961713Sgirish 	{"ZCP",	ZCP},
224944961713Sgirish 	{"FZC_ZCP",	FZC_ZCP},
225044961713Sgirish 	{"DMC",	DMC},
225144961713Sgirish 	{"FZC_DMC",	FZC_DMC},
225244961713Sgirish 	{"TXC",	TXC},
225344961713Sgirish 	{"FZC_TXC",	FZC_TXC},
225444961713Sgirish 	{"PIO_LDSV",	PIO_LDSV},
225544961713Sgirish 	{"PIO_LDGIM",	PIO_LDGIM},
225644961713Sgirish 	{"PIO_IMASK0",	PIO_IMASK0},
225744961713Sgirish 	{"PIO_IMASK1",	PIO_IMASK1},
225844961713Sgirish 	{"FZC_PROM",	FZC_PROM},
225944961713Sgirish 	{"END",	ALL_FF_32},
226044961713Sgirish };
226144961713Sgirish 
226244961713Sgirish /* ARGSUSED */
226344961713Sgirish static int
226444961713Sgirish nxge_param_dump_ptrs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
226544961713Sgirish {
2266a3c5bd6dSspeer 	uint_t			print_len, buf_len;
2267a3c5bd6dSspeer 	p_mblk_t		np;
2268a3c5bd6dSspeer 	int			rdc, tdc, block;
2269a3c5bd6dSspeer 	uint64_t		base;
227044961713Sgirish 	p_nxge_dma_pt_cfg_t	p_dma_cfgp;
227144961713Sgirish 	p_nxge_hw_pt_cfg_t	p_cfgp;
2272a3c5bd6dSspeer 	int			buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_8K;
227344961713Sgirish 	p_tx_ring_t 		*tx_rings;
227444961713Sgirish 	p_rx_rcr_rings_t 	rx_rcr_rings;
227544961713Sgirish 	p_rx_rcr_ring_t		*rcr_rings;
227644961713Sgirish 	p_rx_rbr_rings_t 	rx_rbr_rings;
227744961713Sgirish 	p_rx_rbr_ring_t		*rbr_rings;
227844961713Sgirish 
2279a3c5bd6dSspeer 	NXGE_DEBUG_MSG((nxgep, IOC_CTL,
22804045d941Ssowmini 	    "==> nxge_param_dump_ptrs"));
228144961713Sgirish 
2282a3c5bd6dSspeer 	(void) mi_mpprintf(mp, "ptr information for Port\t %d \n",
22834045d941Ssowmini 	    nxgep->function_num);
228444961713Sgirish 
228544961713Sgirish 	if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) {
228644961713Sgirish 		/* The following may work even if we cannot get a large buf. */
228744961713Sgirish 		(void) mi_mpprintf(mp, "%s\n", "out of buffer");
228844961713Sgirish 		return (0);
228944961713Sgirish 	}
229044961713Sgirish 
229144961713Sgirish 	buf_len = buff_alloc_size;
229244961713Sgirish 	mp->b_cont = np;
229344961713Sgirish 	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
229444961713Sgirish 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
229544961713Sgirish 
229644961713Sgirish 	rx_rcr_rings = nxgep->rx_rcr_rings;
229744961713Sgirish 	rcr_rings = rx_rcr_rings->rcr_rings;
229844961713Sgirish 	rx_rbr_rings = nxgep->rx_rbr_rings;
229944961713Sgirish 	rbr_rings = rx_rbr_rings->rbr_rings;
230044961713Sgirish 	print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
23014045d941Ssowmini 	    "nxgep (nxge_t) $%p\n"
23024045d941Ssowmini 	    "dev_regs (dev_regs_t) $%p\n",
23034045d941Ssowmini 	    nxgep, nxgep->dev_regs);
230444961713Sgirish 
230544961713Sgirish 	ADVANCE_PRINT_BUFFER(np, print_len, buf_len);
2306a3c5bd6dSspeer 
2307a3c5bd6dSspeer 	/* do register pointers */
230844961713Sgirish 	print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
23094045d941Ssowmini 	    "reg base (npi_reg_ptr_t) $%p\t "
23104045d941Ssowmini 	    "pci reg (npi_reg_ptr_t) $%p\n",
23114045d941Ssowmini 	    nxgep->dev_regs->nxge_regp,
23124045d941Ssowmini 	    nxgep->dev_regs->nxge_pciregp);
231344961713Sgirish 
231444961713Sgirish 	ADVANCE_PRINT_BUFFER(np, print_len, buf_len);
231544961713Sgirish 
231644961713Sgirish 	print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
23174045d941Ssowmini 	    "\nBlock \t Offset \n");
231844961713Sgirish 
231944961713Sgirish 	ADVANCE_PRINT_BUFFER(np, print_len, buf_len);
232044961713Sgirish 	block = 0;
2321adfcba55Sjoycey #if defined(__i386)
2322adfcba55Sjoycey 	base = (uint64_t)(uint32_t)nxgep->dev_regs->nxge_regp;
2323adfcba55Sjoycey #else
232444961713Sgirish 	base = (uint64_t)nxgep->dev_regs->nxge_regp;
2325adfcba55Sjoycey #endif
232644961713Sgirish 	while (reg_block[block].offset != ALL_FF_32) {
232744961713Sgirish 		print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
23284045d941Ssowmini 		    "%9s\t 0x%llx\n",
23294045d941Ssowmini 		    reg_block[block].name,
23304045d941Ssowmini 		    (unsigned long long)(reg_block[block].offset + base));
233144961713Sgirish 		ADVANCE_PRINT_BUFFER(np, print_len, buf_len);
233244961713Sgirish 		block++;
233344961713Sgirish 	}
233444961713Sgirish 
233544961713Sgirish 	print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
23364045d941Ssowmini 	    "\nRDC\t rcrp (rx_rcr_ring_t)\t "
23374045d941Ssowmini 	    "rbrp (rx_rbr_ring_t)\n");
233844961713Sgirish 
233944961713Sgirish 	ADVANCE_PRINT_BUFFER(np, print_len, buf_len);
234044961713Sgirish 
234144961713Sgirish 	for (rdc = 0; rdc < p_cfgp->max_rdcs; rdc++) {
234244961713Sgirish 		print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
23434045d941Ssowmini 		    " %d\t  $%p\t\t   $%p\n",
23444045d941Ssowmini 		    rdc, rcr_rings[rdc],
23454045d941Ssowmini 		    rbr_rings[rdc]);
234644961713Sgirish 		ADVANCE_PRINT_BUFFER(np, print_len, buf_len);
234744961713Sgirish 	}
234844961713Sgirish 
234944961713Sgirish 	print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
23504045d941Ssowmini 	    "\nTDC\t tdcp (tx_ring_t)\n");
235144961713Sgirish 
235244961713Sgirish 	ADVANCE_PRINT_BUFFER(np, print_len, buf_len);
235344961713Sgirish 	tx_rings = nxgep->tx_rings->rings;
2354678453a8Sspeer 	for (tdc = 0; tdc < p_cfgp->tdc.count; tdc++) {
235544961713Sgirish 		print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
23564045d941Ssowmini 		    " %d\t  $%p\n", tdc, tx_rings[tdc]);
235744961713Sgirish 		ADVANCE_PRINT_BUFFER(np, print_len, buf_len);
235844961713Sgirish 	}
235944961713Sgirish 
2360a3c5bd6dSspeer 	print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, "\n\n");
236144961713Sgirish 
236244961713Sgirish 	ADVANCE_PRINT_BUFFER(np, print_len, buf_len);
236344961713Sgirish 	NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ptrs"));
236444961713Sgirish 	return (0);
236544961713Sgirish }
236644961713Sgirish 
236744961713Sgirish 
236844961713Sgirish /* ARGSUSED */
236944961713Sgirish int
237044961713Sgirish nxge_nd_get_names(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t param)
237144961713Sgirish {
2372a3c5bd6dSspeer 	ND		*nd;
2373a3c5bd6dSspeer 	NDE		*nde;
2374a3c5bd6dSspeer 	char		*rwtag;
2375a3c5bd6dSspeer 	boolean_t	get_ok, set_ok;
2376a3c5bd6dSspeer 	size_t		param_len;
2377a3c5bd6dSspeer 	int		status = 0;
237844961713Sgirish 
237944961713Sgirish 	nd = (ND *)param;
238044961713Sgirish 	if (!nd)
238144961713Sgirish 		return (ENOENT);
238244961713Sgirish 
238344961713Sgirish 	for (nde = nd->nd_tbl; nde->nde_name; nde++) {
238444961713Sgirish 		get_ok = (nde->nde_get_pfi != nxge_get_default) &&
23854045d941Ssowmini 		    (nde->nde_get_pfi != NULL);
238644961713Sgirish 		set_ok = (nde->nde_set_pfi != nxge_set_default) &&
23874045d941Ssowmini 		    (nde->nde_set_pfi != NULL);
238844961713Sgirish 		if (get_ok) {
238944961713Sgirish 			if (set_ok)
239044961713Sgirish 				rwtag = "read and write";
239144961713Sgirish 			else
239244961713Sgirish 				rwtag = "read only";
239344961713Sgirish 		} else if (set_ok)
239444961713Sgirish 			rwtag = "write only";
239544961713Sgirish 		else {
239644961713Sgirish 			continue;
239744961713Sgirish 		}
239844961713Sgirish 		param_len = strlen(rwtag);
239944961713Sgirish 		param_len += strlen(nde->nde_name);
240044961713Sgirish 		param_len += 4;
240144961713Sgirish 
240244961713Sgirish 		(void) mi_mpprintf(mp, "%s (%s)", nde->nde_name, rwtag);
240344961713Sgirish 	}
240444961713Sgirish 	return (status);
240544961713Sgirish }
240644961713Sgirish 
240744961713Sgirish /* ARGSUSED */
240844961713Sgirish int
240944961713Sgirish nxge_get_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t data)
241044961713Sgirish {
241144961713Sgirish 	return (EACCES);
241244961713Sgirish }
241344961713Sgirish 
241444961713Sgirish /* ARGSUSED */
241544961713Sgirish int
241644961713Sgirish nxge_set_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, char *value,
2417a3c5bd6dSspeer 	caddr_t data)
241844961713Sgirish {
241944961713Sgirish 	return (EACCES);
242044961713Sgirish }
242144961713Sgirish 
24221bd6825cSml boolean_t
242344961713Sgirish nxge_param_link_update(p_nxge_t nxgep)
242444961713Sgirish {
242544961713Sgirish 	p_nxge_param_t 		param_arr;
242644961713Sgirish 	nxge_param_index_t 	i;
242744961713Sgirish 	boolean_t 		update_xcvr;
242844961713Sgirish 	boolean_t 		update_dev;
242944961713Sgirish 	int 			instance;
243044961713Sgirish 	boolean_t 		status = B_TRUE;
243144961713Sgirish 
24321bd6825cSml 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_link_update"));
243344961713Sgirish 
243444961713Sgirish 	param_arr = nxgep->param_arr;
243544961713Sgirish 	instance = nxgep->instance;
243644961713Sgirish 	update_xcvr = B_FALSE;
243744961713Sgirish 	for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) {
243844961713Sgirish 		update_xcvr |= param_arr[i].value;
243944961713Sgirish 	}
244044961713Sgirish 
244144961713Sgirish 	if (update_xcvr) {
244244961713Sgirish 		update_xcvr = B_FALSE;
244344961713Sgirish 		for (i = param_autoneg; i < param_enable_ipg0; i++) {
244444961713Sgirish 			update_xcvr |=
24454045d941Ssowmini 			    (param_arr[i].value != param_arr[i].old_value);
244644961713Sgirish 			param_arr[i].old_value = param_arr[i].value;
244744961713Sgirish 		}
244844961713Sgirish 		if (update_xcvr) {
24491bd6825cSml 			NXGE_DEBUG_MSG((nxgep, NDD_CTL,
24501bd6825cSml 			    "==> nxge_param_link_update: update xcvr"));
245144961713Sgirish 			RW_ENTER_WRITER(&nxgep->filter_lock);
245244961713Sgirish 			(void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP);
245344961713Sgirish 			(void) nxge_link_init(nxgep);
245444961713Sgirish 			(void) nxge_mac_init(nxgep);
245544961713Sgirish 			(void) nxge_link_monitor(nxgep, LINK_MONITOR_START);
245644961713Sgirish 			RW_EXIT(&nxgep->filter_lock);
245744961713Sgirish 		}
245844961713Sgirish 	} else {
245944961713Sgirish 		cmn_err(CE_WARN, " Last setting will leave nxge%d with "
24604045d941Ssowmini 		    " no link capabilities.", instance);
246144961713Sgirish 		cmn_err(CE_WARN, " Restoring previous setting.");
246244961713Sgirish 		for (i = param_anar_1000fdx; i < param_anar_asmpause; i++)
246344961713Sgirish 			param_arr[i].value = param_arr[i].old_value;
246444961713Sgirish 	}
2465a3c5bd6dSspeer 
246644961713Sgirish 	update_dev = B_FALSE;
246744961713Sgirish 
246844961713Sgirish 	if (update_dev) {
246944961713Sgirish 		RW_ENTER_WRITER(&nxgep->filter_lock);
24701bd6825cSml 		NXGE_DEBUG_MSG((nxgep, NDD_CTL,
24711bd6825cSml 		    "==> nxge_param_link_update: update dev"));
247244961713Sgirish 		(void) nxge_rx_mac_disable(nxgep);
247344961713Sgirish 		(void) nxge_tx_mac_disable(nxgep);
247444961713Sgirish 		(void) nxge_tx_mac_enable(nxgep);
247544961713Sgirish 		(void) nxge_rx_mac_enable(nxgep);
247644961713Sgirish 		RW_EXIT(&nxgep->filter_lock);
247744961713Sgirish 	}
247844961713Sgirish 
247944961713Sgirish nxge_param_hw_update_exit:
248044961713Sgirish 	NXGE_DEBUG_MSG((nxgep, DDI_CTL,
24814045d941Ssowmini 	    "<== nxge_param_link_update status = 0x%08x", status));
248244961713Sgirish 	return (status);
248344961713Sgirish }
24841bd6825cSml 
24851bd6825cSml /*
24861bd6825cSml  * synchronize the  adv* and en* parameters.
24871bd6825cSml  *
24881bd6825cSml  * See comments in <sys/dld.h> for details of the *_en_*
24891bd6825cSml  * parameters.  The usage of ndd for setting adv parameters will
24901bd6825cSml  * synchronize all the en parameters with the nxge parameters,
24911bd6825cSml  * implicitly disabling any settings made via dladm.
24921bd6825cSml  */
24931bd6825cSml static void
24941bd6825cSml nxge_param_sync(p_nxge_t nxgep)
24951bd6825cSml {
24961bd6825cSml 	p_nxge_param_t	param_arr;
24971bd6825cSml 	param_arr = nxgep->param_arr;
24981bd6825cSml 
24991bd6825cSml 	nxgep->param_en_pause	= param_arr[param_anar_pause].value;
25001bd6825cSml 	nxgep->param_en_1000fdx	= param_arr[param_anar_1000fdx].value;
25011bd6825cSml 	nxgep->param_en_100fdx	= param_arr[param_anar_100fdx].value;
25021bd6825cSml 	nxgep->param_en_10fdx	= param_arr[param_anar_10fdx].value;
25031bd6825cSml }
25041bd6825cSml 
25051bd6825cSml /* ARGSUSED */
25061bd6825cSml int
25071bd6825cSml nxge_dld_get_ip_opt(p_nxge_t nxgep, caddr_t cp)
25081bd6825cSml {
25091bd6825cSml 	uint32_t status, cfg_value;
25101bd6825cSml 	p_nxge_param_t pa = (p_nxge_param_t)cp;
25111bd6825cSml 	tcam_class_t class;
25121bd6825cSml 
25131bd6825cSml 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_dld_get_ip_opt"));
25141bd6825cSml 
25151bd6825cSml 	/* do the actual hw setup  */
25161bd6825cSml 	class = nxge_class_name_2value(nxgep, pa->name);
25171bd6825cSml 	if (class == -1)
25181bd6825cSml 		return (EINVAL);
25191bd6825cSml 
25201bd6825cSml 	cfg_value = 0;
25211bd6825cSml 	status = nxge_fflp_ip_class_config_get(nxgep, class, &cfg_value);
25221bd6825cSml 	if (status != NXGE_OK)
25231bd6825cSml 		return (EINVAL);
25241bd6825cSml 
25251bd6825cSml 	NXGE_DEBUG_MSG((nxgep, NDD_CTL,
25261bd6825cSml 	    "nxge_param_get_ip_opt_get %x ", cfg_value));
25271bd6825cSml 
25281bd6825cSml 	pa->value = cfg_value;
25291bd6825cSml 
25301bd6825cSml 	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_ip_opt status "));
25311bd6825cSml 	return (0);
25321bd6825cSml }
2533