144961713Sgirish /* 244961713Sgirish * CDDL HEADER START 344961713Sgirish * 444961713Sgirish * The contents of this file are subject to the terms of the 544961713Sgirish * Common Development and Distribution License (the "License"). 644961713Sgirish * You may not use this file except in compliance with the License. 744961713Sgirish * 844961713Sgirish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 944961713Sgirish * or http://www.opensolaris.org/os/licensing. 1044961713Sgirish * See the License for the specific language governing permissions 1144961713Sgirish * and limitations under the License. 1244961713Sgirish * 1344961713Sgirish * When distributing Covered Code, include this CDDL HEADER in each 1444961713Sgirish * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1544961713Sgirish * If applicable, add the following below this CDDL HEADER, with the 1644961713Sgirish * fields enclosed by brackets "[]" replaced with your own identifying 1744961713Sgirish * information: Portions Copyright [yyyy] [name of copyright owner] 1844961713Sgirish * 1944961713Sgirish * CDDL HEADER END 2044961713Sgirish */ 2144961713Sgirish /* 22a3c5bd6dSspeer * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 2344961713Sgirish * Use is subject to license terms. 2444961713Sgirish */ 2544961713Sgirish 2644961713Sgirish #pragma ident "%Z%%M% %I% %E% SMI" 2744961713Sgirish 2844961713Sgirish #include <sys/nxge/nxge_impl.h> 2944961713Sgirish #include <inet/common.h> 3044961713Sgirish #include <inet/mi.h> 3144961713Sgirish #include <inet/nd.h> 3244961713Sgirish 3344961713Sgirish extern uint64_t npi_debug_level; 3444961713Sgirish 35a3c5bd6dSspeer #define NXGE_PARAM_MAC_RW \ 36a3c5bd6dSspeer NXGE_PARAM_RW | NXGE_PARAM_MAC | \ 3744961713Sgirish NXGE_PARAM_NDD_WR_OK | NXGE_PARAM_READ_PROP 3844961713Sgirish 39a3c5bd6dSspeer #define NXGE_PARAM_MAC_DONT_SHOW \ 40a3c5bd6dSspeer NXGE_PARAM_RW | NXGE_PARAM_MAC | NXGE_PARAM_DONT_SHOW 4144961713Sgirish 42a3c5bd6dSspeer #define NXGE_PARAM_RXDMA_RW \ 43a3c5bd6dSspeer NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_NDD_WR_OK | \ 44a3c5bd6dSspeer NXGE_PARAM_READ_PROP 4544961713Sgirish 46a3c5bd6dSspeer #define NXGE_PARAM_RXDMA_RWC \ 47a3c5bd6dSspeer NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_INIT_ONLY | \ 48a3c5bd6dSspeer NXGE_PARAM_READ_PROP 4944961713Sgirish 50a3c5bd6dSspeer #define NXGE_PARAM_L2CLASS_CFG \ 51a3c5bd6dSspeer NXGE_PARAM_RW | NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_READ_PROP | \ 52a3c5bd6dSspeer NXGE_PARAM_NDD_WR_OK 5344961713Sgirish 54a3c5bd6dSspeer #define NXGE_PARAM_CLASS_RWS \ 55a3c5bd6dSspeer NXGE_PARAM_RWS | NXGE_PARAM_READ_PROP 5644961713Sgirish 5744961713Sgirish #define NXGE_PARAM_ARRAY_INIT_SIZE 0x20ULL 5844961713Sgirish 5944961713Sgirish #define SET_RX_INTR_TIME_DISABLE 0 6044961713Sgirish #define SET_RX_INTR_TIME_ENABLE 1 6144961713Sgirish #define SET_RX_INTR_PKTS 2 6244961713Sgirish 6344961713Sgirish #define BASE_ANY 0 64a3c5bd6dSspeer #define BASE_BINARY 2 6544961713Sgirish #define BASE_HEX 16 6644961713Sgirish #define BASE_DECIMAL 10 6744961713Sgirish #define ALL_FF_64 0xFFFFFFFFFFFFFFFFULL 6844961713Sgirish #define ALL_FF_32 0xFFFFFFFFUL 6944961713Sgirish 7044961713Sgirish #define NXGE_NDD_INFODUMP_BUFF_SIZE 2048 /* is 2k enough? */ 7144961713Sgirish #define NXGE_NDD_INFODUMP_BUFF_8K 8192 7244961713Sgirish #define NXGE_NDD_INFODUMP_BUFF_16K 0x2000 7344961713Sgirish #define NXGE_NDD_INFODUMP_BUFF_64K 0x8000 7444961713Sgirish 7544961713Sgirish #define PARAM_OUTOF_RANGE(vptr, eptr, rval, pa) \ 7644961713Sgirish ((vptr == eptr) || (rval < pa->minimum) || (rval > pa->maximum)) 7744961713Sgirish 7844961713Sgirish #define ADVANCE_PRINT_BUFFER(pmp, plen, rlen) { \ 7944961713Sgirish ((mblk_t *)pmp)->b_wptr += plen; \ 8044961713Sgirish rlen -= plen; \ 81a3c5bd6dSspeer } 8244961713Sgirish 8344961713Sgirish static int nxge_param_rx_intr_pkts(p_nxge_t, queue_t *, 84a3c5bd6dSspeer mblk_t *, char *, caddr_t); 8544961713Sgirish static int nxge_param_rx_intr_time(p_nxge_t, queue_t *, 86a3c5bd6dSspeer mblk_t *, char *, caddr_t); 8744961713Sgirish static int nxge_param_set_mac(p_nxge_t, queue_t *, 88a3c5bd6dSspeer mblk_t *, char *, caddr_t); 8944961713Sgirish static int nxge_param_set_port_rdc(p_nxge_t, queue_t *, 90a3c5bd6dSspeer mblk_t *, char *, caddr_t); 9144961713Sgirish static int nxge_param_set_grp_rdc(p_nxge_t, queue_t *, 92a3c5bd6dSspeer mblk_t *, char *, caddr_t); 9344961713Sgirish static int nxge_param_set_ether_usr(p_nxge_t, 94a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 9544961713Sgirish static int nxge_param_set_ip_usr(p_nxge_t, 96a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 9744961713Sgirish static int nxge_param_set_ip_opt(p_nxge_t, 98a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 9944961713Sgirish static int nxge_param_set_vlan_rdcgrp(p_nxge_t, 100a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 10144961713Sgirish static int nxge_param_set_mac_rdcgrp(p_nxge_t, 102a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 10344961713Sgirish static int nxge_param_fflp_hash_init(p_nxge_t, 104a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 10544961713Sgirish static int nxge_param_llc_snap_enable(p_nxge_t, queue_t *, 106a3c5bd6dSspeer mblk_t *, char *, caddr_t); 10744961713Sgirish static int nxge_param_hash_lookup_enable(p_nxge_t, queue_t *, 108a3c5bd6dSspeer mblk_t *, char *, caddr_t); 10944961713Sgirish static int nxge_param_tcam_enable(p_nxge_t, queue_t *, 110a3c5bd6dSspeer mblk_t *, char *, caddr_t); 11156d930aeSspeer static int nxge_param_get_fw_ver(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 1122e59129aSraghus static int nxge_param_get_port_mode(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 11344961713Sgirish static int nxge_param_get_rxdma_info(p_nxge_t, queue_t *q, 114a3c5bd6dSspeer p_mblk_t, caddr_t); 11544961713Sgirish static int nxge_param_get_txdma_info(p_nxge_t, queue_t *q, 116a3c5bd6dSspeer p_mblk_t, caddr_t); 11744961713Sgirish static int nxge_param_get_vlan_rdcgrp(p_nxge_t, queue_t *, 118a3c5bd6dSspeer p_mblk_t, caddr_t); 11944961713Sgirish static int nxge_param_get_mac_rdcgrp(p_nxge_t, queue_t *, 120a3c5bd6dSspeer p_mblk_t, caddr_t); 12144961713Sgirish static int nxge_param_get_rxdma_rdcgrp_info(p_nxge_t, queue_t *, 122a3c5bd6dSspeer p_mblk_t, caddr_t); 12344961713Sgirish static int nxge_param_get_ip_opt(p_nxge_t, queue_t *, mblk_t *, caddr_t); 124a3c5bd6dSspeer static int nxge_param_get_mac(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 12544961713Sgirish static int nxge_param_get_debug_flag(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 12644961713Sgirish static int nxge_param_set_nxge_debug_flag(p_nxge_t, queue_t *, mblk_t *, 127a3c5bd6dSspeer char *, caddr_t); 12844961713Sgirish static int nxge_param_set_npi_debug_flag(p_nxge_t, 129a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 13044961713Sgirish static int nxge_param_dump_rdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 13144961713Sgirish static int nxge_param_dump_tdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 13244961713Sgirish static int nxge_param_dump_mac_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 13344961713Sgirish static int nxge_param_dump_ipp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 13444961713Sgirish static int nxge_param_dump_fflp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 13544961713Sgirish static int nxge_param_dump_vlan_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 13644961713Sgirish static int nxge_param_dump_rdc_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 13744961713Sgirish static int nxge_param_dump_ptrs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 13844961713Sgirish static boolean_t nxge_param_link_update(p_nxge_t); 13944961713Sgirish 14044961713Sgirish /* 14144961713Sgirish * Global array of Neptune changable parameters. 14244961713Sgirish * This array is initialized to correspond to the default 14344961713Sgirish * Neptune 4 port configuration. This array would be copied 14444961713Sgirish * into each port's parameter structure and modifed per 14544961713Sgirish * fcode and nxge.conf configuration. Later, the parameters are 14644961713Sgirish * exported to ndd to display and run-time configuration (at least 14744961713Sgirish * some of them). 14844961713Sgirish * 14944961713Sgirish */ 15044961713Sgirish 151a3c5bd6dSspeer static nxge_param_t nxge_param_arr[] = { 152a3c5bd6dSspeer /* 153a3c5bd6dSspeer * min max value old hw-name conf-name 154a3c5bd6dSspeer */ 155846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 156a3c5bd6dSspeer 0, 999, 1000, 0, "instance", "instance"}, 157a3c5bd6dSspeer 158846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 159a3c5bd6dSspeer 0, 999, 1000, 0, "main-instance", "main_instance"}, 160a3c5bd6dSspeer 161a3c5bd6dSspeer { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 162a3c5bd6dSspeer 0, 3, 0, 0, "function-number", "function_number"}, 163a3c5bd6dSspeer 164a3c5bd6dSspeer /* Partition Id */ 165846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 166a3c5bd6dSspeer 0, 8, 0, 0, "partition-id", "partition_id"}, 167a3c5bd6dSspeer 168a3c5bd6dSspeer /* Read Write Permission Mode */ 169846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 170a3c5bd6dSspeer 0, 2, 0, 0, "read-write-mode", "read_write_mode"}, 171a3c5bd6dSspeer 17256d930aeSspeer { nxge_param_get_fw_ver, NULL, NXGE_PARAM_READ, 17356d930aeSspeer 0, 32, 0, 0, "version", "fw_version"}, 17456d930aeSspeer 1752e59129aSraghus { nxge_param_get_port_mode, NULL, NXGE_PARAM_READ, 1762e59129aSraghus 0, 32, 0, 0, "port-mode", "port_mode"}, 1772e59129aSraghus 178a3c5bd6dSspeer /* hw cfg types */ 179a3c5bd6dSspeer /* control the DMA config of Neptune/NIU */ 180846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 181a3c5bd6dSspeer CFG_DEFAULT, CFG_CUSTOM, CFG_DEFAULT, CFG_DEFAULT, 182a3c5bd6dSspeer "niu-cfg-type", "niu_cfg_type"}, 183a3c5bd6dSspeer 184a3c5bd6dSspeer /* control the TXDMA config of the Port controlled by tx-quick-cfg */ 185846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 186a3c5bd6dSspeer CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT, 187a3c5bd6dSspeer "tx-qcfg-type", "tx_qcfg_type"}, 188a3c5bd6dSspeer 189a3c5bd6dSspeer /* control the RXDMA config of the Port controlled by rx-quick-cfg */ 190846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 191a3c5bd6dSspeer CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT, 192a3c5bd6dSspeer "rx-qcfg-type", "rx_qcfg_type"}, 193a3c5bd6dSspeer 194a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, 195a3c5bd6dSspeer NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 196a3c5bd6dSspeer 0, 1, 0, 0, "master-cfg-enable", "master_cfg_enable"}, 197a3c5bd6dSspeer 198a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, 199846a903dSml NXGE_PARAM_DONT_SHOW, 200a3c5bd6dSspeer 0, 1, 0, 0, "master-cfg-value", "master_cfg_value"}, 201a3c5bd6dSspeer 202a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 203a3c5bd6dSspeer 0, 1, 1, 1, "adv-autoneg-cap", "adv_autoneg_cap"}, 204a3c5bd6dSspeer 205a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 206a3c5bd6dSspeer 0, 1, 1, 1, "adv-10gfdx-cap", "adv_10gfdx_cap"}, 207a3c5bd6dSspeer 208a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 209a3c5bd6dSspeer 0, 1, 0, 0, "adv-10ghdx-cap", "adv_10ghdx_cap"}, 210a3c5bd6dSspeer 211a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 212a3c5bd6dSspeer 0, 1, 1, 1, "adv-1000fdx-cap", "adv_1000fdx_cap"}, 213a3c5bd6dSspeer 214a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 215a3c5bd6dSspeer 0, 1, 0, 0, "adv-1000hdx-cap", "adv_1000hdx_cap"}, 216a3c5bd6dSspeer 217a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 218a3c5bd6dSspeer 0, 1, 0, 0, "adv-100T4-cap", "adv_100T4_cap"}, 219a3c5bd6dSspeer 220a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 221a3c5bd6dSspeer 0, 1, 1, 1, "adv-100fdx-cap", "adv_100fdx_cap"}, 222a3c5bd6dSspeer 223a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 224a3c5bd6dSspeer 0, 1, 0, 0, "adv-100hdx-cap", "adv_100hdx_cap"}, 225a3c5bd6dSspeer 226a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 227a3c5bd6dSspeer 0, 1, 1, 1, "adv-10fdx-cap", "adv_10fdx_cap"}, 228a3c5bd6dSspeer 229a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 230a3c5bd6dSspeer 0, 1, 0, 0, "adv-10hdx-cap", "adv_10hdx_cap"}, 231a3c5bd6dSspeer 232846a903dSml { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 233a3c5bd6dSspeer 0, 1, 0, 0, "adv-asmpause-cap", "adv_asmpause_cap"}, 234a3c5bd6dSspeer 235a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 236a3c5bd6dSspeer 0, 1, 0, 0, "adv-pause-cap", "adv_pause_cap"}, 237a3c5bd6dSspeer 238846a903dSml { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 239a3c5bd6dSspeer 0, 1, 0, 0, "use-int-xcvr", "use_int_xcvr"}, 240a3c5bd6dSspeer 241846a903dSml { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 242a3c5bd6dSspeer 0, 1, 1, 1, "enable-ipg0", "enable_ipg0"}, 243a3c5bd6dSspeer 244846a903dSml { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 245a3c5bd6dSspeer 0, 255, 8, 8, "ipg0", "ipg0"}, 246a3c5bd6dSspeer 247846a903dSml { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 248a3c5bd6dSspeer 0, 255, 8, 8, "ipg1", "ipg1"}, 249a3c5bd6dSspeer 250846a903dSml { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 251a3c5bd6dSspeer 0, 255, 4, 4, "ipg2", "ipg2"}, 252a3c5bd6dSspeer 253a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 254a3c5bd6dSspeer 0, 1, 0, 0, "accept-jumbo", "accept_jumbo"}, 255a3c5bd6dSspeer 256a3c5bd6dSspeer /* Transmit DMA channels */ 257846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 258846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 259a3c5bd6dSspeer 0, 3, 0, 0, "tx-dma-weight", "tx_dma_weight"}, 260a3c5bd6dSspeer 261846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 262846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 263a3c5bd6dSspeer 0, 31, 0, 0, "tx-dma-channels-begin", "tx_dma_channels_begin"}, 264a3c5bd6dSspeer 265846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 266846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 267a3c5bd6dSspeer 0, 32, 0, 0, "tx-dma-channels", "tx_dma_channels"}, 268a3c5bd6dSspeer { nxge_param_get_txdma_info, NULL, 269846a903dSml NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 270a3c5bd6dSspeer 0, 32, 0, 0, "tx-dma-info", "tx_dma_info"}, 271a3c5bd6dSspeer 272a3c5bd6dSspeer /* Receive DMA channels */ 273a3c5bd6dSspeer { nxge_param_get_generic, NULL, 274846a903dSml NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 275a3c5bd6dSspeer 0, 31, 0, 0, "rx-dma-channels-begin", "rx_dma_channels_begin"}, 276a3c5bd6dSspeer 277846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 278846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 279a3c5bd6dSspeer 0, 32, 0, 0, "rx-dma-channels", "rx_dma_channels"}, 280a3c5bd6dSspeer 281846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 282846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 283a3c5bd6dSspeer 0, 65535, PT_DRR_WT_DEFAULT_10G, 0, 284a3c5bd6dSspeer "rx-drr-weight", "rx_drr_weight"}, 285a3c5bd6dSspeer 286846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 287846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 288a3c5bd6dSspeer 0, 1, 1, 0, "rx-full-header", "rx_full_header"}, 289a3c5bd6dSspeer 290846a903dSml { nxge_param_get_rxdma_info, NULL, NXGE_PARAM_READ | 291846a903dSml NXGE_PARAM_DONT_SHOW, 292a3c5bd6dSspeer 0, 32, 0, 0, "rx-dma-info", "rx_dma_info"}, 293a3c5bd6dSspeer 294a3c5bd6dSspeer { nxge_param_get_rxdma_info, NULL, 295a3c5bd6dSspeer NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 296a3c5bd6dSspeer NXGE_RBR_RBB_MIN, NXGE_RBR_RBB_MAX, NXGE_RBR_RBB_DEFAULT, 0, 297a3c5bd6dSspeer "rx-rbr-size", "rx_rbr_size"}, 298a3c5bd6dSspeer 299a3c5bd6dSspeer { nxge_param_get_rxdma_info, NULL, 300a3c5bd6dSspeer NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 301a3c5bd6dSspeer NXGE_RCR_MIN, NXGE_RCR_MAX, NXGE_RCR_DEFAULT, 0, 302a3c5bd6dSspeer "rx-rcr-size", "rx_rcr_size"}, 303a3c5bd6dSspeer 304846a903dSml { nxge_param_get_generic, nxge_param_set_port_rdc, 305846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 306a3c5bd6dSspeer 0, 15, 0, 0, "default-port-rdc", "default_port_rdc"}, 307a3c5bd6dSspeer 308a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_rx_intr_time, NXGE_PARAM_RXDMA_RW, 309a3c5bd6dSspeer NXGE_RDC_RCR_TIMEOUT_MIN, NXGE_RDC_RCR_TIMEOUT_MAX, 310a3c5bd6dSspeer RXDMA_RCR_TO_DEFAULT, 0, "rxdma-intr-time", "rxdma_intr_time"}, 311a3c5bd6dSspeer 312a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_rx_intr_pkts, NXGE_PARAM_RXDMA_RW, 313a3c5bd6dSspeer NXGE_RDC_RCR_THRESHOLD_MIN, NXGE_RDC_RCR_THRESHOLD_MAX, 314a3c5bd6dSspeer RXDMA_RCR_PTHRES_DEFAULT, 0, 315a3c5bd6dSspeer "rxdma-intr-pkts", "rxdma_intr_pkts"}, 316a3c5bd6dSspeer 317846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP | 318846a903dSml NXGE_PARAM_DONT_SHOW, 319a3c5bd6dSspeer 0, 8, 0, 0, "rx-rdc-grps-begin", "rx_rdc_grps_begin"}, 320a3c5bd6dSspeer 321846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP | 322846a903dSml NXGE_PARAM_DONT_SHOW, 323a3c5bd6dSspeer 0, 8, 0, 0, "rx-rdc-grps", "rx_rdc_grps"}, 324a3c5bd6dSspeer 325846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 326846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 327a3c5bd6dSspeer 0, 15, 0, 0, "default-grp0-rdc", "default_grp0_rdc"}, 328a3c5bd6dSspeer 329846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 330846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 331a3c5bd6dSspeer 0, 15, 2, 0, "default-grp1-rdc", "default_grp1_rdc"}, 332a3c5bd6dSspeer 333846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 334846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 335a3c5bd6dSspeer 0, 15, 4, 0, "default-grp2-rdc", "default_grp2_rdc"}, 336a3c5bd6dSspeer 337846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 338846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 339a3c5bd6dSspeer 0, 15, 6, 0, "default-grp3-rdc", "default_grp3_rdc"}, 340a3c5bd6dSspeer 341846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 342846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 343a3c5bd6dSspeer 0, 15, 8, 0, "default-grp4-rdc", "default_grp4_rdc"}, 344a3c5bd6dSspeer 345846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 346846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 347a3c5bd6dSspeer 0, 15, 10, 0, "default-grp5-rdc", "default_grp5_rdc"}, 348a3c5bd6dSspeer 349846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 350846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 351a3c5bd6dSspeer 0, 15, 12, 0, "default-grp6-rdc", "default_grp6_rdc"}, 352a3c5bd6dSspeer 353846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 354846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 355a3c5bd6dSspeer 0, 15, 14, 0, "default-grp7-rdc", "default_grp7_rdc"}, 356a3c5bd6dSspeer 357a3c5bd6dSspeer { nxge_param_get_rxdma_rdcgrp_info, NULL, 358846a903dSml NXGE_PARAM_READ | NXGE_PARAM_CMPLX | NXGE_PARAM_DONT_SHOW, 359a3c5bd6dSspeer 0, 8, 0, 0, "rdc-groups-info", "rdc_groups_info"}, 360a3c5bd6dSspeer 361a3c5bd6dSspeer /* Logical device groups */ 362846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 363a3c5bd6dSspeer 0, 63, 0, 0, "start-ldg", "start_ldg"}, 364a3c5bd6dSspeer 365846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 366a3c5bd6dSspeer 0, 64, 0, 0, "max-ldg", "max_ldg" }, 367a3c5bd6dSspeer 368a3c5bd6dSspeer /* MAC table information */ 369a3c5bd6dSspeer { nxge_param_get_mac_rdcgrp, nxge_param_set_mac_rdcgrp, 370846a903dSml NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW, 371a3c5bd6dSspeer 0, 31, 0, 0, "mac-2rdc-grp", "mac_2rdc_grp"}, 372a3c5bd6dSspeer 373a3c5bd6dSspeer /* VLAN table information */ 374a3c5bd6dSspeer { nxge_param_get_vlan_rdcgrp, nxge_param_set_vlan_rdcgrp, 375846a903dSml NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW, 376a3c5bd6dSspeer 0, 31, 0, 0, "vlan-2rdc-grp", "vlan_2rdc_grp"}, 377a3c5bd6dSspeer 378a3c5bd6dSspeer { nxge_param_get_generic, NULL, 379846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_READ | 380846a903dSml NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_DONT_SHOW, 381a3c5bd6dSspeer 0, 0x0ffff, 0x0ffff, 0, "fcram-part-cfg", "fcram_part_cfg"}, 382a3c5bd6dSspeer 383846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS | 384846a903dSml NXGE_PARAM_DONT_SHOW, 385a3c5bd6dSspeer 0, 0x10, 0xa, 0, "fcram-access-ratio", "fcram_access_ratio"}, 386a3c5bd6dSspeer 387846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS | 388846a903dSml NXGE_PARAM_DONT_SHOW, 389a3c5bd6dSspeer 0, 0x10, 0xa, 0, "tcam-access-ratio", "tcam_access_ratio"}, 390a3c5bd6dSspeer 391a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_tcam_enable, 392846a903dSml NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 393a3c5bd6dSspeer 0, 0x1, 0x0, 0, "tcam-enable", "tcam_enable"}, 394a3c5bd6dSspeer 395a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_hash_lookup_enable, 396846a903dSml NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 397a3c5bd6dSspeer 0, 0x01, 0x0, 0, "hash-lookup-enable", "hash_lookup_enable"}, 398a3c5bd6dSspeer 399a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_llc_snap_enable, 400846a903dSml NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 401a3c5bd6dSspeer 0, 0x01, 0x01, 0, "llc-snap-enable", "llc_snap_enable"}, 402a3c5bd6dSspeer 403a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_fflp_hash_init, 404846a903dSml NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 405a3c5bd6dSspeer 0, ALL_FF_32, ALL_FF_32, 0, "h1-init-value", "h1_init_value"}, 406a3c5bd6dSspeer 407a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_fflp_hash_init, 408846a903dSml NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 409a3c5bd6dSspeer 0, 0x0ffff, 0x0ffff, 0, "h2-init-value", "h2_init_value"}, 410a3c5bd6dSspeer 411a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ether_usr, 412a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 413a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 414a3c5bd6dSspeer "class-cfg-ether-usr1", "class_cfg_ether_usr1"}, 415a3c5bd6dSspeer 416a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ether_usr, 417a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 418a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 419a3c5bd6dSspeer "class-cfg-ether-usr2", "class_cfg_ether_usr2"}, 420a3c5bd6dSspeer 421a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ip_usr, 422a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 423a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 424a3c5bd6dSspeer "class-cfg-ip-usr4", "class_cfg_ip_usr4"}, 425a3c5bd6dSspeer 426a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ip_usr, 427a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 428a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 429a3c5bd6dSspeer "class-cfg-ip-usr5", "class_cfg_ip_usr5"}, 430a3c5bd6dSspeer 431a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ip_usr, 432a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 433a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 434a3c5bd6dSspeer "class-cfg-ip-usr6", "class_cfg_ip_usr6"}, 435a3c5bd6dSspeer 436a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ip_usr, 437a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 438a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 439a3c5bd6dSspeer "class-cfg-ip-usr7", "class_cfg_ip_usr7"}, 440a3c5bd6dSspeer 441a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 442a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 443a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 444a3c5bd6dSspeer "class-opt-ip-usr4", "class_opt_ip_usr4"}, 445a3c5bd6dSspeer 446a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 447a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 448a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 449a3c5bd6dSspeer "class-opt-ip-usr5", "class_opt_ip_usr5"}, 450a3c5bd6dSspeer 451a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 452a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 453a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 454a3c5bd6dSspeer "class-opt-ip-usr6", "class_opt_ip_usr6"}, 455a3c5bd6dSspeer 456a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 457a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 458a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 459a3c5bd6dSspeer "class-opt-ip-usr7", "class_opt_ip_usr7"}, 460a3c5bd6dSspeer 461a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 462a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS, 463a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 464a3c5bd6dSspeer "class-opt-ipv4-tcp", "class_opt_ipv4_tcp"}, 465a3c5bd6dSspeer 466a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 467a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS, 468a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 469a3c5bd6dSspeer "class-opt-ipv4-udp", "class_opt_ipv4_udp"}, 470a3c5bd6dSspeer 471a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 472a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS, 473a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 474a3c5bd6dSspeer "class-opt-ipv4-ah", "class_opt_ipv4_ah"}, 475a3c5bd6dSspeer 476a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 477a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS, 478a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 479a3c5bd6dSspeer "class-opt-ipv4-sctp", "class_opt_ipv4_sctp"}, 480a3c5bd6dSspeer 481a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 482a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 483a3c5bd6dSspeer "class-opt-ipv6-tcp", "class_opt_ipv6_tcp"}, 484a3c5bd6dSspeer 485a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 486a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 487a3c5bd6dSspeer "class-opt-ipv6-udp", "class_opt_ipv6_udp"}, 488a3c5bd6dSspeer 489a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 490a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 491a3c5bd6dSspeer "class-opt-ipv6-ah", "class_opt_ipv6_ah"}, 492a3c5bd6dSspeer 493a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 494a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 495a3c5bd6dSspeer "class-opt-ipv6-sctp", "class_opt_ipv6_sctp"}, 496a3c5bd6dSspeer 497a3c5bd6dSspeer { nxge_param_get_debug_flag, nxge_param_set_nxge_debug_flag, 498846a903dSml NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 499a3c5bd6dSspeer 0ULL, ALL_FF_64, 0ULL, 0ULL, 500a3c5bd6dSspeer "nxge-debug-flag", "nxge_debug_flag"}, 501a3c5bd6dSspeer 502a3c5bd6dSspeer { nxge_param_get_debug_flag, nxge_param_set_npi_debug_flag, 503846a903dSml NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 504a3c5bd6dSspeer 0ULL, ALL_FF_64, 0ULL, 0ULL, 505a3c5bd6dSspeer "npi-debug-flag", "npi_debug_flag"}, 506a3c5bd6dSspeer 507846a903dSml { nxge_param_dump_tdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 508a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "dump-tdc", "dump_tdc"}, 509a3c5bd6dSspeer 510846a903dSml { nxge_param_dump_rdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 511a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "dump-rdc", "dump_rdc"}, 512a3c5bd6dSspeer 513846a903dSml { nxge_param_dump_mac_regs, NULL, NXGE_PARAM_READ | 514846a903dSml NXGE_PARAM_DONT_SHOW, 515a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "dump-mac-regs", "dump_mac_regs"}, 516a3c5bd6dSspeer 517846a903dSml { nxge_param_dump_ipp_regs, NULL, NXGE_PARAM_READ | 518846a903dSml NXGE_PARAM_DONT_SHOW, 519a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "dump-ipp-regs", "dump_ipp_regs"}, 520a3c5bd6dSspeer 521846a903dSml { nxge_param_dump_fflp_regs, NULL, NXGE_PARAM_READ | 522846a903dSml NXGE_PARAM_DONT_SHOW, 523a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, 524a3c5bd6dSspeer "dump-fflp-regs", "dump_fflp_regs"}, 525a3c5bd6dSspeer 526846a903dSml { nxge_param_dump_vlan_table, NULL, NXGE_PARAM_READ | 527846a903dSml NXGE_PARAM_DONT_SHOW, 528a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, 529a3c5bd6dSspeer "dump-vlan-table", "dump_vlan_table"}, 530a3c5bd6dSspeer 531846a903dSml { nxge_param_dump_rdc_table, NULL, NXGE_PARAM_READ | 532846a903dSml NXGE_PARAM_DONT_SHOW, 533a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, 534a3c5bd6dSspeer "dump-rdc-table", "dump_rdc_table"}, 535a3c5bd6dSspeer 536846a903dSml { nxge_param_dump_ptrs, NULL, NXGE_PARAM_READ | 537846a903dSml NXGE_PARAM_DONT_SHOW, 538a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "dump-ptrs", "dump_ptrs"}, 539a3c5bd6dSspeer 540a3c5bd6dSspeer { NULL, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 541a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "end", "end"}, 54244961713Sgirish }; 54344961713Sgirish 54444961713Sgirish extern void *nxge_list; 54544961713Sgirish 54644961713Sgirish void 54744961713Sgirish nxge_get_param_soft_properties(p_nxge_t nxgep) 54844961713Sgirish { 54944961713Sgirish 55044961713Sgirish p_nxge_param_t param_arr; 55144961713Sgirish uint_t prop_len; 55244961713Sgirish int i, j; 553a3c5bd6dSspeer uint32_t param_count; 554a3c5bd6dSspeer uint32_t *int_prop_val; 55544961713Sgirish 55644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, " ==> nxge_get_param_soft_properties")); 55744961713Sgirish 55844961713Sgirish param_arr = nxgep->param_arr; 55944961713Sgirish param_count = nxgep->param_count; 56044961713Sgirish for (i = 0; i < param_count; i++) { 56144961713Sgirish if ((param_arr[i].type & NXGE_PARAM_READ_PROP) == 0) 56244961713Sgirish continue; 56344961713Sgirish if ((param_arr[i].type & NXGE_PARAM_PROP_STR)) 56444961713Sgirish continue; 56544961713Sgirish if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 566a3c5bd6dSspeer (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 56744961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, 568a3c5bd6dSspeer nxgep->dip, 0, param_arr[i].fcode_name, 569a3c5bd6dSspeer (int **)&int_prop_val, 570a3c5bd6dSspeer (uint_t *)&prop_len) 571a3c5bd6dSspeer == DDI_PROP_SUCCESS) { 57244961713Sgirish uint32_t *cfg_value; 57344961713Sgirish uint64_t prop_count; 574a3c5bd6dSspeer 57544961713Sgirish if (prop_len > NXGE_PARAM_ARRAY_INIT_SIZE) 57644961713Sgirish prop_len = NXGE_PARAM_ARRAY_INIT_SIZE; 577*adfcba55Sjoycey #if defined(__i386) 578*adfcba55Sjoycey cfg_value = 579*adfcba55Sjoycey (uint32_t *)(int32_t)param_arr[i].value; 580*adfcba55Sjoycey #else 58144961713Sgirish cfg_value = (uint32_t *)param_arr[i].value; 582*adfcba55Sjoycey #endif 58344961713Sgirish for (j = 0; j < prop_len; j++) { 58444961713Sgirish cfg_value[j] = int_prop_val[j]; 58544961713Sgirish } 58644961713Sgirish prop_count = prop_len; 58744961713Sgirish param_arr[i].type |= 58844961713Sgirish (prop_count << NXGE_PARAM_ARRAY_CNT_SHIFT); 58944961713Sgirish ddi_prop_free(int_prop_val); 59044961713Sgirish } 59144961713Sgirish continue; 59244961713Sgirish } 59344961713Sgirish 59444961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 595a3c5bd6dSspeer param_arr[i].fcode_name, 596a3c5bd6dSspeer (int **)&int_prop_val, 597a3c5bd6dSspeer &prop_len) == DDI_PROP_SUCCESS) { 59844961713Sgirish if ((*int_prop_val >= param_arr[i].minimum) && 599a3c5bd6dSspeer (*int_prop_val <= param_arr[i].maximum)) 60044961713Sgirish param_arr[i].value = *int_prop_val; 60144961713Sgirish #ifdef NXGE_DEBUG_ERROR 60244961713Sgirish else { 60344961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL, 604a3c5bd6dSspeer "nxge%d: 'prom' file parameter error\n", 605a3c5bd6dSspeer nxgep->instance)); 60644961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL, 607a3c5bd6dSspeer "Parameter keyword '%s'" 608a3c5bd6dSspeer " is outside valid range\n", 609a3c5bd6dSspeer param_arr[i].name)); 61044961713Sgirish } 61144961713Sgirish #endif 61244961713Sgirish ddi_prop_free(int_prop_val); 61344961713Sgirish } 61444961713Sgirish 61544961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 616a3c5bd6dSspeer param_arr[i].name, 617a3c5bd6dSspeer (int **)&int_prop_val, 618a3c5bd6dSspeer &prop_len) == DDI_PROP_SUCCESS) { 61944961713Sgirish if ((*int_prop_val >= param_arr[i].minimum) && 62044961713Sgirish (*int_prop_val <= param_arr[i].maximum)) 62144961713Sgirish param_arr[i].value = *int_prop_val; 62244961713Sgirish #ifdef NXGE_DEBUG_ERROR 62344961713Sgirish else { 62444961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL, 625a3c5bd6dSspeer "nxge%d: 'conf' file parameter error\n", 626a3c5bd6dSspeer nxgep->instance)); 62744961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL, 628a3c5bd6dSspeer "Parameter keyword '%s'" 629a3c5bd6dSspeer "is outside valid range\n", 630a3c5bd6dSspeer param_arr[i].name)); 63144961713Sgirish } 63244961713Sgirish #endif 63344961713Sgirish ddi_prop_free(int_prop_val); 63444961713Sgirish } 63544961713Sgirish } 63644961713Sgirish } 63744961713Sgirish 63844961713Sgirish static int 63944961713Sgirish nxge_private_param_register(p_nxge_t nxgep, p_nxge_param_t param_arr) 64044961713Sgirish { 64144961713Sgirish int status = B_TRUE; 64244961713Sgirish int channel; 64344961713Sgirish uint8_t grp; 64444961713Sgirish char *prop_name; 64544961713Sgirish char *end; 64644961713Sgirish uint32_t name_chars; 64744961713Sgirish 64844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 649a3c5bd6dSspeer "nxge_private_param_register %s", param_arr->name)); 65044961713Sgirish 65144961713Sgirish if ((param_arr->type & NXGE_PARAM_PRIV) != NXGE_PARAM_PRIV) 65244961713Sgirish return (B_TRUE); 653a3c5bd6dSspeer 65444961713Sgirish prop_name = param_arr->name; 65544961713Sgirish if (param_arr->type & NXGE_PARAM_RXDMA) { 65644961713Sgirish if (strncmp("rxdma_intr", prop_name, 10) == 0) 65744961713Sgirish return (B_TRUE); 65844961713Sgirish name_chars = strlen("default_grp"); 65944961713Sgirish if (strncmp("default_grp", prop_name, name_chars) == 0) { 66044961713Sgirish prop_name += name_chars; 66144961713Sgirish grp = mi_strtol(prop_name, &end, 10); 66244961713Sgirish /* now check if this rdcgrp is in config */ 66344961713Sgirish return (nxge_check_rdcgrp_port_member(nxgep, grp)); 66444961713Sgirish } 66544961713Sgirish name_chars = strlen(prop_name); 66644961713Sgirish if (strncmp("default_port_rdc", prop_name, name_chars) == 0) { 66744961713Sgirish return (B_TRUE); 66844961713Sgirish } 66944961713Sgirish return (B_FALSE); 67044961713Sgirish } 67144961713Sgirish 67244961713Sgirish if (param_arr->type & NXGE_PARAM_TXDMA) { 67344961713Sgirish name_chars = strlen("txdma"); 67444961713Sgirish if (strncmp("txdma", prop_name, name_chars) == 0) { 67544961713Sgirish prop_name += name_chars; 67644961713Sgirish channel = mi_strtol(prop_name, &end, 10); 67744961713Sgirish /* now check if this rdc is in config */ 67844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 67944961713Sgirish " nxge_private_param_register: %d", 68044961713Sgirish channel)); 68144961713Sgirish return (nxge_check_txdma_port_member(nxgep, channel)); 68244961713Sgirish } 68344961713Sgirish return (B_FALSE); 68444961713Sgirish } 68544961713Sgirish 68644961713Sgirish status = B_FALSE; 68744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD2_CTL, "<== nxge_private_param_register")); 68844961713Sgirish 68944961713Sgirish return (status); 69044961713Sgirish } 69144961713Sgirish 69244961713Sgirish void 69344961713Sgirish nxge_setup_param(p_nxge_t nxgep) 69444961713Sgirish { 69544961713Sgirish p_nxge_param_t param_arr; 69644961713Sgirish int i; 69744961713Sgirish pfi_t set_pfi; 69844961713Sgirish 69944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_setup_param")); 700a3c5bd6dSspeer 70144961713Sgirish /* 70244961713Sgirish * Make sure the param_instance is set to a valid device instance. 70344961713Sgirish */ 70444961713Sgirish if (nxge_param_arr[param_instance].value == 1000) 70544961713Sgirish nxge_param_arr[param_instance].value = nxgep->instance; 70644961713Sgirish 70744961713Sgirish param_arr = nxgep->param_arr; 70844961713Sgirish param_arr[param_instance].value = nxgep->instance; 70944961713Sgirish param_arr[param_function_number].value = nxgep->function_num; 71044961713Sgirish 71144961713Sgirish for (i = 0; i < nxgep->param_count; i++) { 71244961713Sgirish if ((param_arr[i].type & NXGE_PARAM_PRIV) && 713a3c5bd6dSspeer (nxge_private_param_register(nxgep, 714a3c5bd6dSspeer ¶m_arr[i]) == B_FALSE)) { 71544961713Sgirish param_arr[i].setf = NULL; 71644961713Sgirish param_arr[i].getf = NULL; 71744961713Sgirish } 71844961713Sgirish 71944961713Sgirish if (param_arr[i].type & NXGE_PARAM_CMPLX) 72044961713Sgirish param_arr[i].setf = NULL; 72144961713Sgirish 72244961713Sgirish if (param_arr[i].type & NXGE_PARAM_DONT_SHOW) { 72344961713Sgirish param_arr[i].setf = NULL; 72444961713Sgirish param_arr[i].getf = NULL; 72544961713Sgirish } 72644961713Sgirish 72744961713Sgirish set_pfi = (pfi_t)param_arr[i].setf; 72844961713Sgirish 729a3c5bd6dSspeer if ((set_pfi) && (param_arr[i].type & NXGE_PARAM_INIT_ONLY)) { 73044961713Sgirish set_pfi = NULL; 73144961713Sgirish } 73244961713Sgirish 733a3c5bd6dSspeer if (!nxge_nd_load(&nxgep->param_list, param_arr[i].name, 734a3c5bd6dSspeer (pfi_t)param_arr[i].getf, set_pfi, 73544961713Sgirish (caddr_t)¶m_arr[i])) { 73644961713Sgirish (void) nxge_nd_free(&nxgep->param_list); 73744961713Sgirish break; 73844961713Sgirish } 73944961713Sgirish } 74044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_setup_param")); 74144961713Sgirish } 74244961713Sgirish 74344961713Sgirish void 74444961713Sgirish nxge_init_param(p_nxge_t nxgep) 74544961713Sgirish { 74644961713Sgirish p_nxge_param_t param_arr; 74744961713Sgirish int i, alloc_size; 74844961713Sgirish uint64_t alloc_count; 74944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_init_param")); 75044961713Sgirish /* 75144961713Sgirish * Make sure the param_instance is set to a valid device instance. 75244961713Sgirish */ 75344961713Sgirish if (nxge_param_arr[param_instance].value == 1000) 75444961713Sgirish nxge_param_arr[param_instance].value = nxgep->instance; 75544961713Sgirish 75644961713Sgirish param_arr = nxgep->param_arr; 75744961713Sgirish if (param_arr == NULL) { 758a3c5bd6dSspeer param_arr = (p_nxge_param_t) 759a3c5bd6dSspeer KMEM_ZALLOC(sizeof (nxge_param_arr), KM_SLEEP); 76044961713Sgirish } 761a3c5bd6dSspeer 76244961713Sgirish for (i = 0; i < sizeof (nxge_param_arr)/sizeof (nxge_param_t); i++) { 76344961713Sgirish param_arr[i] = nxge_param_arr[i]; 76444961713Sgirish if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 76544961713Sgirish (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 76644961713Sgirish alloc_count = NXGE_PARAM_ARRAY_INIT_SIZE; 76744961713Sgirish alloc_size = alloc_count * sizeof (uint64_t); 76844961713Sgirish param_arr[i].value = 769*adfcba55Sjoycey #if defined(__i386) 770*adfcba55Sjoycey (uint64_t)(uint32_t)KMEM_ZALLOC(alloc_size, 771*adfcba55Sjoycey KM_SLEEP); 772*adfcba55Sjoycey #else 77344961713Sgirish (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP); 774*adfcba55Sjoycey #endif 77544961713Sgirish param_arr[i].old_value = 776*adfcba55Sjoycey #if defined(__i386) 777*adfcba55Sjoycey (uint64_t)(uint32_t)KMEM_ZALLOC(alloc_size, 778*adfcba55Sjoycey KM_SLEEP); 779*adfcba55Sjoycey #else 780*adfcba55Sjoycey (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP); 781*adfcba55Sjoycey #endif 78244961713Sgirish param_arr[i].type |= 78344961713Sgirish (alloc_count << NXGE_PARAM_ARRAY_ALLOC_SHIFT); 78444961713Sgirish } 78544961713Sgirish } 78644961713Sgirish 78744961713Sgirish nxgep->param_arr = param_arr; 78844961713Sgirish nxgep->param_count = sizeof (nxge_param_arr)/sizeof (nxge_param_t); 78944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_init_param: count %d", 790a3c5bd6dSspeer nxgep->param_count)); 79144961713Sgirish } 79244961713Sgirish 79344961713Sgirish void 79444961713Sgirish nxge_destroy_param(p_nxge_t nxgep) 79544961713Sgirish { 79644961713Sgirish int i; 79744961713Sgirish uint64_t free_size, free_count; 79844961713Sgirish 79944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_param")); 800a3c5bd6dSspeer 80159ac0c16Sdavemq if (nxgep->param_arr == NULL) 80259ac0c16Sdavemq return; 80344961713Sgirish /* 80444961713Sgirish * Make sure the param_instance is set to a valid device instance. 80544961713Sgirish */ 80644961713Sgirish if (nxge_param_arr[param_instance].value == nxgep->instance) { 80744961713Sgirish for (i = 0; i <= nxge_param_arr[param_instance].maximum; i++) { 80844961713Sgirish if ((ddi_get_soft_state(nxge_list, i) != NULL) && 80944961713Sgirish (i != nxgep->instance)) 81044961713Sgirish break; 81144961713Sgirish } 81244961713Sgirish nxge_param_arr[param_instance].value = i; 81344961713Sgirish } 81444961713Sgirish 81544961713Sgirish if (nxgep->param_list) 81644961713Sgirish nxge_nd_free(&nxgep->param_list); 81744961713Sgirish for (i = 0; i < nxgep->param_count; i++) 81844961713Sgirish if ((nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 81944961713Sgirish (nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 82044961713Sgirish free_count = ((nxgep->param_arr[i].type & 82144961713Sgirish NXGE_PARAM_ARRAY_ALLOC_MASK) >> 82244961713Sgirish NXGE_PARAM_ARRAY_ALLOC_SHIFT); 82344961713Sgirish free_count = NXGE_PARAM_ARRAY_INIT_SIZE; 82444961713Sgirish free_size = sizeof (uint64_t) * free_count; 825*adfcba55Sjoycey #if defined(__i386) 826*adfcba55Sjoycey KMEM_FREE((void *)(uint32_t)nxgep->param_arr[i].value, 827*adfcba55Sjoycey free_size); 828*adfcba55Sjoycey #else 82944961713Sgirish KMEM_FREE((void *)nxgep->param_arr[i].value, free_size); 830*adfcba55Sjoycey #endif 831*adfcba55Sjoycey #if defined(__i386) 832*adfcba55Sjoycey KMEM_FREE((void *)(uint32_t) 833*adfcba55Sjoycey nxgep->param_arr[i].old_value, free_size); 834*adfcba55Sjoycey #else 83544961713Sgirish KMEM_FREE((void *)nxgep->param_arr[i].old_value, 836a3c5bd6dSspeer free_size); 837*adfcba55Sjoycey #endif 83844961713Sgirish } 83944961713Sgirish 84044961713Sgirish KMEM_FREE(nxgep->param_arr, sizeof (nxge_param_arr)); 84144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_param")); 84244961713Sgirish } 84344961713Sgirish 84444961713Sgirish /* 84544961713Sgirish * Extracts the value from the 'nxge' parameter array and prints the 84644961713Sgirish * parameter value. cp points to the required parameter. 84744961713Sgirish */ 848a3c5bd6dSspeer 84944961713Sgirish /* ARGSUSED */ 85044961713Sgirish int 85144961713Sgirish nxge_param_get_generic(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 85244961713Sgirish { 85344961713Sgirish p_nxge_param_t pa = (p_nxge_param_t)cp; 85444961713Sgirish 855a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, NDD_CTL, 856a3c5bd6dSspeer "==> nxge_param_get_generic name %s ", pa->name)); 85744961713Sgirish 85844961713Sgirish if (pa->value > 0xffffffff) 859a3c5bd6dSspeer (void) mi_mpprintf(mp, "%x%x", 860a3c5bd6dSspeer (int)(pa->value >> 32), (int)(pa->value & 0xffffffff)); 86144961713Sgirish else 86244961713Sgirish (void) mi_mpprintf(mp, "%x", (int)pa->value); 86344961713Sgirish 86444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_generic")); 86544961713Sgirish return (0); 86644961713Sgirish } 86744961713Sgirish 86844961713Sgirish /* ARGSUSED */ 86944961713Sgirish static int 87044961713Sgirish nxge_param_get_mac(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 87144961713Sgirish { 87244961713Sgirish p_nxge_param_t pa = (p_nxge_param_t)cp; 87344961713Sgirish 87444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac")); 87544961713Sgirish 87644961713Sgirish (void) mi_mpprintf(mp, "%d", (uint32_t)pa->value); 87744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_mac")); 87844961713Sgirish return (0); 87944961713Sgirish } 88044961713Sgirish 88156d930aeSspeer /* ARGSUSED */ 88256d930aeSspeer static int 88356d930aeSspeer nxge_param_get_fw_ver(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 88456d930aeSspeer { 88556d930aeSspeer NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_fw_ver")); 88656d930aeSspeer 88756d930aeSspeer (void) mi_mpprintf(mp, "Firmware version for nxge%d: %s\n", 88856d930aeSspeer nxgep->instance, nxgep->vpd_info.ver); 88956d930aeSspeer 89056d930aeSspeer NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_fw_ver")); 89156d930aeSspeer return (0); 89256d930aeSspeer } 89356d930aeSspeer 8942e59129aSraghus /* ARGSUSED */ 8952e59129aSraghus static int 8962e59129aSraghus nxge_param_get_port_mode(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 8972e59129aSraghus { 8982e59129aSraghus NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_port_mode")); 8992e59129aSraghus 9002e59129aSraghus switch (nxgep->mac.portmode) { 9012e59129aSraghus case PORT_1G_COPPER: 9022e59129aSraghus (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Copper\n", 9032e59129aSraghus nxgep->instance); 9042e59129aSraghus break; 9052e59129aSraghus case PORT_1G_FIBER: 9062e59129aSraghus (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Fiber\n", 9072e59129aSraghus nxgep->instance); 9082e59129aSraghus break; 9092e59129aSraghus case PORT_10G_COPPER: 9102e59129aSraghus (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Copper\n", 9112e59129aSraghus nxgep->instance); 9122e59129aSraghus break; 9132e59129aSraghus case PORT_10G_FIBER: 9142e59129aSraghus (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Fiber\n", 9152e59129aSraghus nxgep->instance); 9162e59129aSraghus break; 9172e59129aSraghus case PORT_10G_SERDES: 9182e59129aSraghus (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Serdes\n", 9192e59129aSraghus nxgep->instance); 9202e59129aSraghus break; 9212e59129aSraghus case PORT_1G_SERDES: 9222e59129aSraghus (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Serdes\n", 9232e59129aSraghus nxgep->instance); 9242e59129aSraghus break; 9252e59129aSraghus case PORT_1G_RGMII_FIBER: 9262e59129aSraghus (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G RGMII " 9272e59129aSraghus "Fiber\n", nxgep->instance); 9282e59129aSraghus break; 9292e59129aSraghus default: 9302e59129aSraghus (void) mi_mpprintf(mp, "Port mode for nxge%d: Unknown\n", 9312e59129aSraghus nxgep->instance); 9322e59129aSraghus break; 9332e59129aSraghus } 9342e59129aSraghus 9352e59129aSraghus NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_port_mode")); 9362e59129aSraghus return (0); 9372e59129aSraghus } 9382e59129aSraghus 93944961713Sgirish /* ARGSUSED */ 94044961713Sgirish int 94144961713Sgirish nxge_param_get_txdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 94244961713Sgirish { 94344961713Sgirish 94444961713Sgirish uint_t print_len, buf_len; 94544961713Sgirish p_mblk_t np; 94644961713Sgirish int tdc; 94744961713Sgirish 94844961713Sgirish int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 94944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_txdma_info")); 95044961713Sgirish 951a3c5bd6dSspeer (void) mi_mpprintf(mp, "TXDMA Information for Port\t %d \n", 952a3c5bd6dSspeer nxgep->function_num); 95344961713Sgirish 95444961713Sgirish 95544961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 95644961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 95744961713Sgirish return (0); 95844961713Sgirish } 95944961713Sgirish 96044961713Sgirish buf_len = buff_alloc_size; 96144961713Sgirish mp->b_cont = np; 96244961713Sgirish 96344961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 964a3c5bd6dSspeer "Total TDCs\t %d\n", nxgep->ntdc); 96544961713Sgirish 96644961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 96744961713Sgirish buf_len -= print_len; 96844961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 969a3c5bd6dSspeer "TDC\t HW TDC\t\n"); 97044961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 971a3c5bd6dSspeer 97244961713Sgirish buf_len -= print_len; 97344961713Sgirish for (tdc = 0; tdc < nxgep->ntdc; tdc++) { 97444961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 97544961713Sgirish buf_len, "%d\t %d\n", 97644961713Sgirish tdc, nxgep->tdc[tdc]); 97744961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 97844961713Sgirish buf_len -= print_len; 97944961713Sgirish } 980a3c5bd6dSspeer 98144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_txdma_info")); 98244961713Sgirish return (0); 98344961713Sgirish } 98444961713Sgirish 98544961713Sgirish /* ARGSUSED */ 98644961713Sgirish int 98744961713Sgirish nxge_param_get_rxdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 98844961713Sgirish { 989a3c5bd6dSspeer uint_t print_len, buf_len; 990a3c5bd6dSspeer p_mblk_t np; 991a3c5bd6dSspeer int rdc; 99244961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 99344961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 994a3c5bd6dSspeer int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 99544961713Sgirish p_rx_rcr_rings_t rx_rcr_rings; 99644961713Sgirish p_rx_rcr_ring_t *rcr_rings; 99744961713Sgirish p_rx_rbr_rings_t rx_rbr_rings; 99844961713Sgirish p_rx_rbr_ring_t *rbr_rings; 99944961713Sgirish 100044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rxdma_info")); 100144961713Sgirish 1002a3c5bd6dSspeer (void) mi_mpprintf(mp, "RXDMA Information for Port\t %d \n", 1003a3c5bd6dSspeer nxgep->function_num); 100444961713Sgirish 100544961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 100644961713Sgirish /* The following may work even if we cannot get a large buf. */ 100744961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 100844961713Sgirish return (0); 100944961713Sgirish } 101044961713Sgirish 101144961713Sgirish buf_len = buff_alloc_size; 101244961713Sgirish mp->b_cont = np; 101344961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 101444961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 101544961713Sgirish 101644961713Sgirish rx_rcr_rings = nxgep->rx_rcr_rings; 101744961713Sgirish rcr_rings = rx_rcr_rings->rcr_rings; 101844961713Sgirish rx_rbr_rings = nxgep->rx_rbr_rings; 101944961713Sgirish rbr_rings = rx_rbr_rings->rbr_rings; 102044961713Sgirish 102144961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1022a3c5bd6dSspeer "Total RDCs\t %d\n", p_cfgp->max_rdcs); 102344961713Sgirish 102444961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 102544961713Sgirish buf_len -= print_len; 102644961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1027a3c5bd6dSspeer "RDC\t HW RDC\t Timeout\t Packets RBR ptr \t" 1028a3c5bd6dSspeer "chunks\t RCR ptr\n"); 1029a3c5bd6dSspeer 103044961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 103144961713Sgirish buf_len -= print_len; 103244961713Sgirish for (rdc = 0; rdc < p_cfgp->max_rdcs; rdc++) { 103344961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1034a3c5bd6dSspeer " %d\t %d\t %x\t\t %x\t $%p\t 0x%x\t $%p\n", 1035a3c5bd6dSspeer rdc, nxgep->rdc[rdc], 1036a3c5bd6dSspeer p_dma_cfgp->rcr_timeout[rdc], 1037a3c5bd6dSspeer p_dma_cfgp->rcr_threshold[rdc], 1038a3c5bd6dSspeer rbr_rings[rdc], 1039a3c5bd6dSspeer rbr_rings[rdc]->num_blocks, rcr_rings[rdc]); 1040a3c5bd6dSspeer ((mblk_t *)np)->b_wptr += print_len; 1041a3c5bd6dSspeer buf_len -= print_len; 104244961713Sgirish } 1043a3c5bd6dSspeer 104444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rxdma_info")); 104544961713Sgirish return (0); 104644961713Sgirish } 104744961713Sgirish 104844961713Sgirish /* ARGSUSED */ 104944961713Sgirish int 105044961713Sgirish nxge_param_get_rxdma_rdcgrp_info(p_nxge_t nxgep, queue_t *q, 1051a3c5bd6dSspeer p_mblk_t mp, caddr_t cp) 105244961713Sgirish { 1053a3c5bd6dSspeer uint_t print_len, buf_len; 1054a3c5bd6dSspeer p_mblk_t np; 1055a3c5bd6dSspeer int offset, rdc, i, rdc_grp; 105644961713Sgirish p_nxge_rdc_grp_t rdc_grp_p; 105744961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 105844961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 105944961713Sgirish 106044961713Sgirish int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 106144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1062a3c5bd6dSspeer "==> nxge_param_get_rxdma_rdcgrp_info")); 106344961713Sgirish 106444961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 106544961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 106644961713Sgirish 1067a3c5bd6dSspeer (void) mi_mpprintf(mp, "RXDMA RDC Group Information for Port\t %d \n", 1068a3c5bd6dSspeer nxgep->function_num); 106944961713Sgirish 107044961713Sgirish rdc_grp = p_cfgp->start_rdc_grpid; 107144961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 107244961713Sgirish /* The following may work even if we cannot get a large buf. */ 107344961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 107444961713Sgirish return (0); 107544961713Sgirish } 107644961713Sgirish 107744961713Sgirish buf_len = buff_alloc_size; 107844961713Sgirish mp->b_cont = np; 107944961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1080a3c5bd6dSspeer "Total RDC Groups\t %d \n" 1081a3c5bd6dSspeer "start RDC group\t %d\n", 1082a3c5bd6dSspeer p_cfgp->max_rdc_grpids, 1083a3c5bd6dSspeer p_cfgp->start_rdc_grpid); 108444961713Sgirish 108544961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 108644961713Sgirish buf_len -= print_len; 108744961713Sgirish 108844961713Sgirish for (i = 0, rdc_grp = p_cfgp->start_rdc_grpid; 108944961713Sgirish rdc_grp < (p_cfgp->max_rdc_grpids + p_cfgp->start_rdc_grpid); 109044961713Sgirish rdc_grp++, i++) { 109144961713Sgirish rdc_grp_p = &p_dma_cfgp->rdc_grps[i]; 109244961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1093a3c5bd6dSspeer "\nRDC Group Info for Group [%d] %d\n" 1094a3c5bd6dSspeer "RDC Count %d\tstart RDC %d\n" 1095a3c5bd6dSspeer "RDC Group Population Information" 1096a3c5bd6dSspeer " (offsets 0 - 15)\n", 1097a3c5bd6dSspeer i, rdc_grp, rdc_grp_p->max_rdcs, 1098a3c5bd6dSspeer rdc_grp_p->start_rdc); 109944961713Sgirish 110044961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 110144961713Sgirish buf_len -= print_len; 110244961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1103a3c5bd6dSspeer buf_len, "\n"); 110444961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 110544961713Sgirish buf_len -= print_len; 110644961713Sgirish 110744961713Sgirish for (rdc = 0; rdc < rdc_grp_p->max_rdcs; rdc++) { 110844961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1109a3c5bd6dSspeer buf_len, "[%d]=%d ", rdc, 1110a3c5bd6dSspeer rdc_grp_p->start_rdc + rdc); 111144961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 111244961713Sgirish buf_len -= print_len; 111344961713Sgirish } 111444961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 111544961713Sgirish buf_len, "\n"); 111644961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 111744961713Sgirish buf_len -= print_len; 111844961713Sgirish 111944961713Sgirish for (offset = 0; offset < 16; offset++) { 112044961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1121a3c5bd6dSspeer buf_len, " %2d ", 1122a3c5bd6dSspeer rdc_grp_p->rdc[offset]); 112344961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 112444961713Sgirish buf_len -= print_len; 112544961713Sgirish } 112644961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1127a3c5bd6dSspeer buf_len, "\n"); 112844961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 112944961713Sgirish buf_len -= print_len; 113044961713Sgirish } 113144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1132a3c5bd6dSspeer "<== nxge_param_get_rxdma_rdcgrp_info")); 113344961713Sgirish return (0); 113444961713Sgirish } 113544961713Sgirish 113644961713Sgirish int 113744961713Sgirish nxge_mk_mblk_tail_space(p_mblk_t mp, p_mblk_t *nmp, size_t size) 113844961713Sgirish { 113944961713Sgirish p_mblk_t tmp; 114044961713Sgirish 114144961713Sgirish tmp = mp; 114244961713Sgirish while (tmp->b_cont) 114344961713Sgirish tmp = tmp->b_cont; 114444961713Sgirish if ((tmp->b_wptr + size) >= tmp->b_datap->db_lim) { 114544961713Sgirish tmp->b_cont = allocb(1024, BPRI_HI); 114644961713Sgirish tmp = tmp->b_cont; 114744961713Sgirish if (!tmp) 114844961713Sgirish return (ENOMEM); 114944961713Sgirish } 1150a3c5bd6dSspeer 115144961713Sgirish *nmp = tmp; 115244961713Sgirish return (0); 115344961713Sgirish } 115444961713Sgirish 115544961713Sgirish /* 115644961713Sgirish * Sets the ge parameter to the value in the nxge_param_register using 115744961713Sgirish * nxge_nd_load(). 115844961713Sgirish */ 1159a3c5bd6dSspeer 116044961713Sgirish /* ARGSUSED */ 116144961713Sgirish int 116244961713Sgirish nxge_param_set_generic(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 116344961713Sgirish char *value, caddr_t cp) 116444961713Sgirish { 116544961713Sgirish char *end; 116644961713Sgirish uint32_t new_value; 116744961713Sgirish p_nxge_param_t pa = (p_nxge_param_t)cp; 116844961713Sgirish 116944961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, " ==> nxge_param_set_generic")); 117044961713Sgirish new_value = (uint32_t)mi_strtol(value, &end, 10); 117144961713Sgirish if (end == value || new_value < pa->minimum || 117244961713Sgirish new_value > pa->maximum) { 117344961713Sgirish return (EINVAL); 117444961713Sgirish } 117544961713Sgirish pa->value = new_value; 117644961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, " <== nxge_param_set_generic")); 117744961713Sgirish return (0); 117844961713Sgirish } 117944961713Sgirish 118044961713Sgirish /* 118144961713Sgirish * Sets the ge parameter to the value in the nxge_param_register using 118244961713Sgirish * nxge_nd_load(). 118344961713Sgirish */ 118444961713Sgirish 1185a3c5bd6dSspeer /* ARGSUSED */ 118644961713Sgirish int 1187a3c5bd6dSspeer nxge_param_set_instance(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1188a3c5bd6dSspeer char *value, caddr_t cp) 118944961713Sgirish { 119044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " ==> nxge_param_set_instance")); 119144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_set_instance")); 119244961713Sgirish return (0); 119344961713Sgirish } 119444961713Sgirish 119544961713Sgirish /* 119644961713Sgirish * Sets the ge parameter to the value in the nxge_param_register using 119744961713Sgirish * nxge_nd_load(). 119844961713Sgirish */ 119944961713Sgirish 1200a3c5bd6dSspeer /* ARGSUSED */ 120144961713Sgirish int 1202a3c5bd6dSspeer nxge_param_set_mac(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1203a3c5bd6dSspeer char *value, caddr_t cp) 120444961713Sgirish { 1205a3c5bd6dSspeer char *end; 1206a3c5bd6dSspeer uint32_t new_value; 1207a3c5bd6dSspeer int status = 0; 1208a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 120944961713Sgirish 121044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac")); 121144961713Sgirish new_value = (uint32_t)mi_strtol(value, &end, BASE_DECIMAL); 121244961713Sgirish if (PARAM_OUTOF_RANGE(value, end, new_value, pa)) { 121344961713Sgirish return (EINVAL); 121444961713Sgirish } 121544961713Sgirish 121644961713Sgirish if (pa->value != new_value) { 121744961713Sgirish pa->old_value = pa->value; 121844961713Sgirish pa->value = new_value; 121944961713Sgirish } 122044961713Sgirish 122144961713Sgirish if (!nxge_param_link_update(nxgep)) { 122244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 122344961713Sgirish " false ret from nxge_param_link_update")); 122444961713Sgirish status = EINVAL; 122544961713Sgirish } 122644961713Sgirish 122744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac")); 122844961713Sgirish return (status); 122944961713Sgirish } 123044961713Sgirish 123144961713Sgirish /* ARGSUSED */ 123244961713Sgirish static int 1233a3c5bd6dSspeer nxge_param_rx_intr_pkts(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1234a3c5bd6dSspeer char *value, caddr_t cp) 123544961713Sgirish { 1236a3c5bd6dSspeer char *end; 1237a3c5bd6dSspeer uint32_t cfg_value; 1238a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 123914ea4bb7Ssd 124044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_pkts")); 124144961713Sgirish 124214ea4bb7Ssd cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 124344961713Sgirish 124414ea4bb7Ssd if ((cfg_value > NXGE_RDC_RCR_THRESHOLD_MAX) || 124514ea4bb7Ssd (cfg_value < NXGE_RDC_RCR_THRESHOLD_MIN)) { 124644961713Sgirish return (EINVAL); 124744961713Sgirish } 124814ea4bb7Ssd 124914ea4bb7Ssd if ((pa->value != cfg_value)) { 125014ea4bb7Ssd pa->old_value = pa->value; 125114ea4bb7Ssd pa->value = cfg_value; 125214ea4bb7Ssd nxgep->intr_threshold = pa->value; 125344961713Sgirish } 125414ea4bb7Ssd 125544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_pkts")); 125644961713Sgirish return (0); 125744961713Sgirish } 125844961713Sgirish 125944961713Sgirish /* ARGSUSED */ 126044961713Sgirish static int 1261a3c5bd6dSspeer nxge_param_rx_intr_time(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1262a3c5bd6dSspeer char *value, caddr_t cp) 126344961713Sgirish { 1264a3c5bd6dSspeer char *end; 1265a3c5bd6dSspeer uint32_t cfg_value; 1266a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 126744961713Sgirish 126844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_time")); 126944961713Sgirish 127014ea4bb7Ssd cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 127144961713Sgirish 127214ea4bb7Ssd if ((cfg_value > NXGE_RDC_RCR_TIMEOUT_MAX) || 127314ea4bb7Ssd (cfg_value < NXGE_RDC_RCR_TIMEOUT_MIN)) { 127444961713Sgirish return (EINVAL); 127544961713Sgirish } 127644961713Sgirish 127714ea4bb7Ssd if ((pa->value != cfg_value)) { 127814ea4bb7Ssd pa->old_value = pa->value; 127914ea4bb7Ssd pa->value = cfg_value; 128014ea4bb7Ssd nxgep->intr_timeout = pa->value; 128144961713Sgirish } 128244961713Sgirish 128344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_time")); 128444961713Sgirish return (0); 128544961713Sgirish } 128644961713Sgirish 128744961713Sgirish /* ARGSUSED */ 128844961713Sgirish static int 128944961713Sgirish nxge_param_set_mac_rdcgrp(p_nxge_t nxgep, queue_t *q, 1290a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 129144961713Sgirish { 1292a3c5bd6dSspeer char *end; 1293a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1294a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1295a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 129644961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 129744961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 1298a3c5bd6dSspeer uint32_t *val_ptr, *old_val_ptr; 1299a3c5bd6dSspeer nxge_param_map_t *mac_map; 1300a3c5bd6dSspeer p_nxge_class_pt_cfg_t p_class_cfgp; 1301a3c5bd6dSspeer nxge_mv_cfg_t *mac_host_info; 130244961713Sgirish 130344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac_rdcgrp ")); 130444961713Sgirish 130544961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 130644961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 130744961713Sgirish p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 130844961713Sgirish mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 130944961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1310a3c5bd6dSspeer 1311a3c5bd6dSspeer /* 1312a3c5bd6dSspeer * now do decoding 1313a3c5bd6dSspeer */ 131444961713Sgirish mac_map = (nxge_param_map_t *)&cfg_value; 1315a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, NDD_CTL, " cfg_value %x id %x map_to %x", 1316a3c5bd6dSspeer cfg_value, mac_map->param_id, mac_map->map_to)); 131744961713Sgirish 131844961713Sgirish if ((mac_map->param_id < p_cfgp->max_macs) && 1319a3c5bd6dSspeer (mac_map->map_to < (p_cfgp->max_rdc_grpids + 1320a3c5bd6dSspeer p_cfgp->start_rdc_grpid)) && (mac_map->map_to >= 1321a3c5bd6dSspeer p_cfgp->start_rdc_grpid)) { 132244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1323a3c5bd6dSspeer " nxge_param_set_mac_rdcgrp mapping" 1324a3c5bd6dSspeer " id %d grp %d", mac_map->param_id, mac_map->map_to)); 1325*adfcba55Sjoycey #if defined(__i386) 1326*adfcba55Sjoycey val_ptr = (uint32_t *)(uint32_t)pa->value; 1327*adfcba55Sjoycey #else 132844961713Sgirish val_ptr = (uint32_t *)pa->value; 1329*adfcba55Sjoycey #endif 1330*adfcba55Sjoycey #if defined(__i386) 1331*adfcba55Sjoycey old_val_ptr = (uint32_t *)(uint32_t)pa->old_value; 1332*adfcba55Sjoycey #else 133344961713Sgirish old_val_ptr = (uint32_t *)pa->old_value; 1334*adfcba55Sjoycey #endif 133544961713Sgirish if (val_ptr[mac_map->param_id] != cfg_value) { 133644961713Sgirish old_val_ptr[mac_map->param_id] = 133744961713Sgirish val_ptr[mac_map->param_id]; 133844961713Sgirish val_ptr[mac_map->param_id] = cfg_value; 133944961713Sgirish mac_host_info[mac_map->param_id].mpr_npr = 134044961713Sgirish mac_map->pref; 134144961713Sgirish mac_host_info[mac_map->param_id].flag = 1; 134244961713Sgirish mac_host_info[mac_map->param_id].rdctbl = 134344961713Sgirish mac_map->map_to; 134444961713Sgirish cfg_it = B_TRUE; 134544961713Sgirish } 134644961713Sgirish } else { 134744961713Sgirish return (EINVAL); 134844961713Sgirish } 134944961713Sgirish 135044961713Sgirish if (cfg_it == B_TRUE) { 135144961713Sgirish status = nxge_logical_mac_assign_rdc_table(nxgep, 135244961713Sgirish (uint8_t)mac_map->param_id); 135344961713Sgirish if (status != NXGE_OK) 135444961713Sgirish return (EINVAL); 135544961713Sgirish } 135644961713Sgirish 135744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac_rdcgrp")); 135844961713Sgirish return (0); 135944961713Sgirish } 136044961713Sgirish 136144961713Sgirish /* ARGSUSED */ 136244961713Sgirish static int 136344961713Sgirish nxge_param_set_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q, 1364a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 136544961713Sgirish { 1366a3c5bd6dSspeer char *end; 1367a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1368a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1369a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 137044961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 137144961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 1372a3c5bd6dSspeer uint32_t *val_ptr, *old_val_ptr; 1373a3c5bd6dSspeer nxge_param_map_t *vmap, *old_map; 1374a3c5bd6dSspeer p_nxge_class_pt_cfg_t p_class_cfgp; 1375a3c5bd6dSspeer uint64_t cfgd_vlans; 1376a3c5bd6dSspeer int i, inc = 0, cfg_position; 1377a3c5bd6dSspeer nxge_mv_cfg_t *vlan_tbl; 137844961713Sgirish 137944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp ")); 138044961713Sgirish 138144961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 138244961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 138344961713Sgirish p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 138444961713Sgirish vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 138544961713Sgirish 138644961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1387a3c5bd6dSspeer 1388a3c5bd6dSspeer /* now do decoding */ 138944961713Sgirish cfgd_vlans = ((pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >> 1390a3c5bd6dSspeer NXGE_PARAM_ARRAY_CNT_SHIFT); 139144961713Sgirish 139244961713Sgirish if (cfgd_vlans == NXGE_PARAM_ARRAY_INIT_SIZE) { 139344961713Sgirish /* 139444961713Sgirish * for now, we process only upto max 139544961713Sgirish * NXGE_PARAM_ARRAY_INIT_SIZE parameters 139644961713Sgirish * In the future, we may want to expand 139744961713Sgirish * the storage array and continue 139844961713Sgirish */ 139944961713Sgirish return (EINVAL); 140044961713Sgirish } 1401a3c5bd6dSspeer 140244961713Sgirish vmap = (nxge_param_map_t *)&cfg_value; 140344961713Sgirish if ((vmap->param_id) && 140444961713Sgirish (vmap->param_id < NXGE_MAX_VLANS) && 140544961713Sgirish (vmap->map_to < p_cfgp->max_rdc_grpids)) { 140644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1407a3c5bd6dSspeer "nxge_param_set_vlan_rdcgrp mapping" 1408a3c5bd6dSspeer " id %d grp %d", 1409a3c5bd6dSspeer vmap->param_id, vmap->map_to)); 1410*adfcba55Sjoycey #if defined(__i386) 1411*adfcba55Sjoycey val_ptr = (uint32_t *)(uint32_t)pa->value; 1412*adfcba55Sjoycey #else 141344961713Sgirish val_ptr = (uint32_t *)pa->value; 1414*adfcba55Sjoycey #endif 1415*adfcba55Sjoycey #if defined(__i386) 1416*adfcba55Sjoycey old_val_ptr = (uint32_t *)(uint32_t)pa->old_value; 1417*adfcba55Sjoycey #else 141844961713Sgirish old_val_ptr = (uint32_t *)pa->old_value; 1419*adfcba55Sjoycey #endif 142044961713Sgirish 142144961713Sgirish /* search to see if this vlan id is already configured */ 142244961713Sgirish for (i = 0; i < cfgd_vlans; i++) { 142344961713Sgirish old_map = (nxge_param_map_t *)&val_ptr[i]; 142444961713Sgirish if ((old_map->param_id == 0) || 142544961713Sgirish (vmap->param_id == old_map->param_id) || 142644961713Sgirish (vlan_tbl[vmap->param_id].flag)) { 142744961713Sgirish cfg_position = i; 142844961713Sgirish break; 142944961713Sgirish } 143044961713Sgirish } 143144961713Sgirish 143244961713Sgirish if (cfgd_vlans == 0) { 143344961713Sgirish cfg_position = 0; 143444961713Sgirish inc++; 143544961713Sgirish } 143644961713Sgirish 143744961713Sgirish if (i == cfgd_vlans) { 143844961713Sgirish cfg_position = i; 143944961713Sgirish inc++; 144044961713Sgirish } 144144961713Sgirish 144244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 1443a3c5bd6dSspeer "set_vlan_rdcgrp mapping" 1444a3c5bd6dSspeer " i %d cfgd_vlans %llx position %d ", 1445a3c5bd6dSspeer i, cfgd_vlans, cfg_position)); 144644961713Sgirish if (val_ptr[cfg_position] != cfg_value) { 144744961713Sgirish old_val_ptr[cfg_position] = val_ptr[cfg_position]; 144844961713Sgirish val_ptr[cfg_position] = cfg_value; 144944961713Sgirish vlan_tbl[vmap->param_id].mpr_npr = vmap->pref; 145044961713Sgirish vlan_tbl[vmap->param_id].flag = 1; 145144961713Sgirish vlan_tbl[vmap->param_id].rdctbl = 145244961713Sgirish vmap->map_to + p_cfgp->start_rdc_grpid; 145344961713Sgirish cfg_it = B_TRUE; 145444961713Sgirish if (inc) { 145544961713Sgirish cfgd_vlans++; 145644961713Sgirish pa->type &= ~NXGE_PARAM_ARRAY_CNT_MASK; 145744961713Sgirish pa->type |= (cfgd_vlans << 145844961713Sgirish NXGE_PARAM_ARRAY_CNT_SHIFT); 145944961713Sgirish 146044961713Sgirish } 146144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 1462a3c5bd6dSspeer "after: param_set_vlan_rdcgrp " 1463a3c5bd6dSspeer " cfg_vlans %llx position %d \n", 1464a3c5bd6dSspeer cfgd_vlans, cfg_position)); 146544961713Sgirish } 146644961713Sgirish } else { 146744961713Sgirish return (EINVAL); 146844961713Sgirish } 146944961713Sgirish 147044961713Sgirish if (cfg_it == B_TRUE) { 147144961713Sgirish status = nxge_fflp_config_vlan_table(nxgep, 1472a3c5bd6dSspeer (uint16_t)vmap->param_id); 147344961713Sgirish if (status != NXGE_OK) 147444961713Sgirish return (EINVAL); 147544961713Sgirish } 147644961713Sgirish 147744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_vlan_rdcgrp")); 147844961713Sgirish return (0); 147944961713Sgirish } 148044961713Sgirish 148144961713Sgirish /* ARGSUSED */ 148244961713Sgirish static int 148344961713Sgirish nxge_param_get_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q, 1484a3c5bd6dSspeer mblk_t *mp, caddr_t cp) 148544961713Sgirish { 148644961713Sgirish 1487a3c5bd6dSspeer uint_t print_len, buf_len; 1488a3c5bd6dSspeer p_mblk_t np; 1489a3c5bd6dSspeer int i; 1490a3c5bd6dSspeer uint32_t *val_ptr; 1491a3c5bd6dSspeer nxge_param_map_t *vmap; 1492a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 149344961713Sgirish p_nxge_class_pt_cfg_t p_class_cfgp; 149444961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 149544961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 1496a3c5bd6dSspeer uint64_t cfgd_vlans = 0; 1497a3c5bd6dSspeer nxge_mv_cfg_t *vlan_tbl; 1498a3c5bd6dSspeer int buff_alloc_size = 1499a3c5bd6dSspeer NXGE_NDD_INFODUMP_BUFF_SIZE * 32; 150044961713Sgirish 150144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp ")); 1502a3c5bd6dSspeer (void) mi_mpprintf(mp, "VLAN RDC Mapping Information for Port\t %d \n", 1503a3c5bd6dSspeer nxgep->function_num); 150444961713Sgirish 150544961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 150644961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 150744961713Sgirish return (0); 150844961713Sgirish } 1509a3c5bd6dSspeer 151044961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 151144961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 151244961713Sgirish 151344961713Sgirish buf_len = buff_alloc_size; 151444961713Sgirish mp->b_cont = np; 151544961713Sgirish cfgd_vlans = (pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >> 151644961713Sgirish NXGE_PARAM_ARRAY_CNT_SHIFT; 151744961713Sgirish 151844961713Sgirish i = (int)cfgd_vlans; 151944961713Sgirish p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 152044961713Sgirish vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 152144961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1522a3c5bd6dSspeer "Configured VLANs %d\n" 1523a3c5bd6dSspeer "VLAN ID\t RDC GRP (Actual/Port)\t" 1524a3c5bd6dSspeer " Prefernce\n", i); 152544961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 152644961713Sgirish buf_len -= print_len; 1527*adfcba55Sjoycey #if defined(__i386) 1528*adfcba55Sjoycey val_ptr = (uint32_t *)(uint32_t)pa->value; 1529*adfcba55Sjoycey #else 153044961713Sgirish val_ptr = (uint32_t *)pa->value; 1531*adfcba55Sjoycey #endif 153244961713Sgirish 153344961713Sgirish for (i = 0; i < cfgd_vlans; i++) { 153444961713Sgirish vmap = (nxge_param_map_t *)&val_ptr[i]; 153544961713Sgirish if (p_class_cfgp->vlan_tbl[vmap->param_id].flag) { 153644961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1537a3c5bd6dSspeer buf_len, 1538a3c5bd6dSspeer " %d\t\t %d/%d\t\t %d\n", 1539a3c5bd6dSspeer vmap->param_id, 1540a3c5bd6dSspeer vlan_tbl[vmap->param_id].rdctbl, 1541a3c5bd6dSspeer vlan_tbl[vmap->param_id].rdctbl - 1542a3c5bd6dSspeer p_cfgp->start_rdc_grpid, 1543a3c5bd6dSspeer vlan_tbl[vmap->param_id].mpr_npr); 154444961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 154544961713Sgirish buf_len -= print_len; 154644961713Sgirish } 154744961713Sgirish } 154844961713Sgirish 154944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_vlan_rdcgrp")); 155044961713Sgirish return (0); 155144961713Sgirish } 155244961713Sgirish 155344961713Sgirish /* ARGSUSED */ 155444961713Sgirish static int 155544961713Sgirish nxge_param_get_mac_rdcgrp(p_nxge_t nxgep, queue_t *q, 1556a3c5bd6dSspeer mblk_t *mp, caddr_t cp) 155744961713Sgirish { 1558a3c5bd6dSspeer uint_t print_len, buf_len; 1559a3c5bd6dSspeer p_mblk_t np; 1560a3c5bd6dSspeer int i; 156144961713Sgirish p_nxge_class_pt_cfg_t p_class_cfgp; 156244961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 156344961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 1564a3c5bd6dSspeer nxge_mv_cfg_t *mac_host_info; 156544961713Sgirish 156644961713Sgirish int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE * 32; 156744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac_rdcgrp ")); 156844961713Sgirish (void) mi_mpprintf(mp, 1569a3c5bd6dSspeer "MAC ADDR RDC Mapping Information for Port\t %d\n", 1570a3c5bd6dSspeer nxgep->function_num); 157144961713Sgirish 157244961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 157344961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 157444961713Sgirish return (0); 157544961713Sgirish } 157644961713Sgirish 157744961713Sgirish buf_len = buff_alloc_size; 157844961713Sgirish mp->b_cont = np; 157944961713Sgirish p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 158044961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 158144961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 158244961713Sgirish mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 158344961713Sgirish print_len = snprintf((char *)np->b_wptr, buf_len, 1584a3c5bd6dSspeer "MAC ID\t RDC GRP (Actual/Port)\t" 1585a3c5bd6dSspeer " Prefernce\n"); 158644961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 158744961713Sgirish buf_len -= print_len; 158844961713Sgirish for (i = 0; i < p_cfgp->max_macs; i++) { 158944961713Sgirish if (mac_host_info[i].flag) { 159044961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1591a3c5bd6dSspeer buf_len, 1592a3c5bd6dSspeer " %d\t %d/%d\t\t %d\n", 1593a3c5bd6dSspeer i, mac_host_info[i].rdctbl, 1594a3c5bd6dSspeer mac_host_info[i].rdctbl - 1595a3c5bd6dSspeer p_cfgp->start_rdc_grpid, 1596a3c5bd6dSspeer mac_host_info[i].mpr_npr); 159744961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 159844961713Sgirish buf_len -= print_len; 159944961713Sgirish } 160044961713Sgirish } 160144961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1602a3c5bd6dSspeer "Done Info Dumping \n"); 160344961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 160444961713Sgirish buf_len -= print_len; 160544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_macrdcgrp")); 160644961713Sgirish return (0); 160744961713Sgirish } 160844961713Sgirish 160944961713Sgirish /* ARGSUSED */ 161044961713Sgirish static int 161144961713Sgirish nxge_param_tcam_enable(p_nxge_t nxgep, queue_t *q, 1612a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 161344961713Sgirish { 1614a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1615a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1616a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 1617a3c5bd6dSspeer char *end; 161844961713Sgirish 161944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_tcam_enable")); 162044961713Sgirish 162144961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 162244961713Sgirish if (pa->value != cfg_value) { 162344961713Sgirish pa->old_value = pa->value; 162444961713Sgirish pa->value = cfg_value; 162544961713Sgirish cfg_it = B_TRUE; 162644961713Sgirish } 162744961713Sgirish 162844961713Sgirish if (cfg_it == B_TRUE) { 162944961713Sgirish if (pa->value) 163044961713Sgirish status = nxge_fflp_config_tcam_enable(nxgep); 163144961713Sgirish else 163244961713Sgirish status = nxge_fflp_config_tcam_disable(nxgep); 163344961713Sgirish if (status != NXGE_OK) 163444961713Sgirish return (EINVAL); 163544961713Sgirish } 163644961713Sgirish 163744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_tcam_enable")); 163844961713Sgirish return (0); 163944961713Sgirish } 164044961713Sgirish 164144961713Sgirish /* ARGSUSED */ 164244961713Sgirish static int 164344961713Sgirish nxge_param_hash_lookup_enable(p_nxge_t nxgep, queue_t *q, 1644a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 164544961713Sgirish { 1646a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1647a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1648a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 1649a3c5bd6dSspeer char *end; 165044961713Sgirish 165144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_hash_lookup_enable")); 165244961713Sgirish 165344961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 165444961713Sgirish if (pa->value != cfg_value) { 165544961713Sgirish pa->old_value = pa->value; 165644961713Sgirish pa->value = cfg_value; 165744961713Sgirish cfg_it = B_TRUE; 165844961713Sgirish } 165944961713Sgirish 166044961713Sgirish if (cfg_it == B_TRUE) { 166144961713Sgirish if (pa->value) 166244961713Sgirish status = nxge_fflp_config_hash_lookup_enable(nxgep); 166344961713Sgirish else 166444961713Sgirish status = nxge_fflp_config_hash_lookup_disable(nxgep); 166544961713Sgirish if (status != NXGE_OK) 166644961713Sgirish return (EINVAL); 166744961713Sgirish } 166844961713Sgirish 166944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_hash_lookup_enable")); 167044961713Sgirish return (0); 167144961713Sgirish } 167244961713Sgirish 167344961713Sgirish /* ARGSUSED */ 167444961713Sgirish static int 167544961713Sgirish nxge_param_llc_snap_enable(p_nxge_t nxgep, queue_t *q, 1676a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 167744961713Sgirish { 1678a3c5bd6dSspeer char *end; 1679a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1680a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1681a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 168244961713Sgirish 168344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_llc_snap_enable")); 168444961713Sgirish 168544961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 168644961713Sgirish if (pa->value != cfg_value) { 168744961713Sgirish pa->old_value = pa->value; 168844961713Sgirish pa->value = cfg_value; 168944961713Sgirish cfg_it = B_TRUE; 169044961713Sgirish } 169144961713Sgirish 169244961713Sgirish if (cfg_it == B_TRUE) { 169344961713Sgirish if (pa->value) 169444961713Sgirish status = nxge_fflp_config_tcam_enable(nxgep); 169544961713Sgirish else 169644961713Sgirish status = nxge_fflp_config_tcam_disable(nxgep); 169744961713Sgirish if (status != NXGE_OK) 169844961713Sgirish return (EINVAL); 169944961713Sgirish } 170044961713Sgirish 170144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_llc_snap_enable")); 170244961713Sgirish return (0); 170344961713Sgirish } 170444961713Sgirish 170544961713Sgirish /* ARGSUSED */ 170644961713Sgirish static int 170744961713Sgirish nxge_param_set_ether_usr(p_nxge_t nxgep, queue_t *q, 1708a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 170944961713Sgirish { 1710a3c5bd6dSspeer char *end; 1711a3c5bd6dSspeer uint8_t ether_class; 1712a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1713a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1714a3c5bd6dSspeer uint8_t cfg_it = B_FALSE; 171544961713Sgirish 171644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ether_usr")); 171744961713Sgirish 171844961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 171944961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 172044961713Sgirish return (EINVAL); 172144961713Sgirish } 1722a3c5bd6dSspeer 172344961713Sgirish if (pa->value != cfg_value) { 172444961713Sgirish pa->old_value = pa->value; 172544961713Sgirish pa->value = cfg_value; 172644961713Sgirish cfg_it = B_TRUE; 172744961713Sgirish } 172844961713Sgirish 172944961713Sgirish /* do the actual hw setup */ 173044961713Sgirish if (cfg_it == B_TRUE) { 173144961713Sgirish ether_class = mi_strtol(pa->name, &end, 10); 173244961713Sgirish #ifdef lint 173344961713Sgirish ether_class = ether_class; 173444961713Sgirish #endif 173544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_ether_usr")); 173644961713Sgirish } 1737a3c5bd6dSspeer 173844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ether_usr")); 173944961713Sgirish return (status); 174044961713Sgirish } 174144961713Sgirish 174244961713Sgirish /* ARGSUSED */ 174344961713Sgirish static int 174444961713Sgirish nxge_param_set_ip_usr(p_nxge_t nxgep, queue_t *q, 1745a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 174644961713Sgirish { 1747a3c5bd6dSspeer char *end; 1748a3c5bd6dSspeer tcam_class_t class; 1749a3c5bd6dSspeer uint32_t status, cfg_value; 1750a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1751a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 175244961713Sgirish 175344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_usr")); 175444961713Sgirish 175544961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 175644961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 175744961713Sgirish return (EINVAL); 175844961713Sgirish } 175944961713Sgirish 176044961713Sgirish if (pa->value != cfg_value) { 176144961713Sgirish pa->old_value = pa->value; 176244961713Sgirish pa->value = cfg_value; 176344961713Sgirish cfg_it = B_TRUE; 176444961713Sgirish } 176544961713Sgirish 176644961713Sgirish /* do the actual hw setup with cfg_value. */ 176744961713Sgirish if (cfg_it == B_TRUE) { 176844961713Sgirish class = mi_strtol(pa->name, &end, 10); 176944961713Sgirish status = nxge_fflp_ip_usr_class_config(nxgep, class, pa->value); 177044961713Sgirish } 177144961713Sgirish 177244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_usr")); 177344961713Sgirish return (status); 177444961713Sgirish } 177544961713Sgirish 1776a3c5bd6dSspeer /* ARGSUSED */ 177744961713Sgirish static int 177844961713Sgirish nxge_class_name_2value(p_nxge_t nxgep, char *name) 177944961713Sgirish { 1780a3c5bd6dSspeer int i; 1781a3c5bd6dSspeer int class_instance = param_class_opt_ip_usr4; 1782a3c5bd6dSspeer p_nxge_param_t param_arr; 1783a3c5bd6dSspeer 178444961713Sgirish param_arr = nxgep->param_arr; 178544961713Sgirish for (i = TCAM_CLASS_IP_USER_4; i <= TCAM_CLASS_SCTP_IPV6; i++) { 178644961713Sgirish if (strcmp(param_arr[class_instance].name, name) == 0) 178744961713Sgirish return (i); 178844961713Sgirish class_instance++; 178944961713Sgirish } 179044961713Sgirish return (-1); 179144961713Sgirish } 179244961713Sgirish 179344961713Sgirish /* ARGSUSED */ 179444961713Sgirish static int 179544961713Sgirish nxge_param_set_ip_opt(p_nxge_t nxgep, queue_t *q, 1796a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 179744961713Sgirish { 1798a3c5bd6dSspeer char *end; 1799a3c5bd6dSspeer uint32_t status, cfg_value; 1800a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1801a3c5bd6dSspeer tcam_class_t class; 1802a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 180344961713Sgirish 180444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_opt")); 180544961713Sgirish 180644961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 180744961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 180844961713Sgirish return (EINVAL); 180944961713Sgirish } 181044961713Sgirish 181144961713Sgirish if (pa->value != cfg_value) { 181244961713Sgirish pa->old_value = pa->value; 181344961713Sgirish pa->value = cfg_value; 181444961713Sgirish cfg_it = B_TRUE; 181544961713Sgirish } 181644961713Sgirish 181744961713Sgirish if (cfg_it == B_TRUE) { 1818a3c5bd6dSspeer /* do the actual hw setup */ 181944961713Sgirish class = nxge_class_name_2value(nxgep, pa->name); 182044961713Sgirish if (class == -1) 182144961713Sgirish return (EINVAL); 182244961713Sgirish 182344961713Sgirish status = nxge_fflp_ip_class_config(nxgep, class, pa->value); 182444961713Sgirish if (status != NXGE_OK) 182544961713Sgirish return (EINVAL); 182644961713Sgirish } 182744961713Sgirish 182844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_opt")); 182944961713Sgirish return (0); 183044961713Sgirish } 183144961713Sgirish 183244961713Sgirish /* ARGSUSED */ 183344961713Sgirish static int 183444961713Sgirish nxge_param_get_ip_opt(p_nxge_t nxgep, queue_t *q, 1835a3c5bd6dSspeer mblk_t *mp, caddr_t cp) 183644961713Sgirish { 183744961713Sgirish uint32_t status, cfg_value; 183844961713Sgirish p_nxge_param_t pa = (p_nxge_param_t)cp; 183944961713Sgirish tcam_class_t class; 184044961713Sgirish 184144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_ip_opt")); 184244961713Sgirish 1843a3c5bd6dSspeer /* do the actual hw setup */ 184444961713Sgirish class = nxge_class_name_2value(nxgep, pa->name); 184544961713Sgirish if (class == -1) 184644961713Sgirish return (EINVAL); 1847a3c5bd6dSspeer 184844961713Sgirish cfg_value = 0; 184944961713Sgirish status = nxge_fflp_ip_class_config_get(nxgep, class, &cfg_value); 185044961713Sgirish if (status != NXGE_OK) 185144961713Sgirish return (EINVAL); 1852a3c5bd6dSspeer 185344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1854a3c5bd6dSspeer "nxge_param_get_ip_opt_get %x ", cfg_value)); 185544961713Sgirish 1856a3c5bd6dSspeer pa->value = cfg_value; 185744961713Sgirish (void) mi_mpprintf(mp, "%x", cfg_value); 1858a3c5bd6dSspeer 185944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_ip_opt status ")); 186044961713Sgirish return (0); 186144961713Sgirish } 186244961713Sgirish 186344961713Sgirish /* ARGSUSED */ 186444961713Sgirish static int 186544961713Sgirish nxge_param_fflp_hash_init(p_nxge_t nxgep, queue_t *q, 1866a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 186744961713Sgirish { 1868a3c5bd6dSspeer char *end; 1869a3c5bd6dSspeer uint32_t status, cfg_value; 1870a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1871a3c5bd6dSspeer tcam_class_t class; 1872a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 187344961713Sgirish 187444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_fflp_hash_init")); 187544961713Sgirish 187644961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 187744961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 187844961713Sgirish return (EINVAL); 187944961713Sgirish } 188044961713Sgirish 188144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1882a3c5bd6dSspeer "nxge_param_fflp_hash_init value %x", cfg_value)); 1883a3c5bd6dSspeer 188444961713Sgirish if (pa->value != cfg_value) { 188544961713Sgirish pa->old_value = pa->value; 188644961713Sgirish pa->value = cfg_value; 188744961713Sgirish cfg_it = B_TRUE; 188844961713Sgirish } 188944961713Sgirish 189044961713Sgirish if (cfg_it == B_TRUE) { 189144961713Sgirish char *h_name; 1892a3c5bd6dSspeer 189344961713Sgirish /* do the actual hw setup */ 189444961713Sgirish h_name = pa->name; 189544961713Sgirish h_name++; 189644961713Sgirish class = mi_strtol(h_name, &end, 10); 189744961713Sgirish switch (class) { 189844961713Sgirish case 1: 189944961713Sgirish status = nxge_fflp_set_hash1(nxgep, 1900a3c5bd6dSspeer (uint32_t)pa->value); 190144961713Sgirish break; 190244961713Sgirish case 2: 190344961713Sgirish status = nxge_fflp_set_hash2(nxgep, 1904a3c5bd6dSspeer (uint16_t)pa->value); 190544961713Sgirish break; 190644961713Sgirish 190744961713Sgirish default: 190844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1909a3c5bd6dSspeer " nxge_param_fflp_hash_init" 1910a3c5bd6dSspeer " %s Wrong hash var %d", 1911a3c5bd6dSspeer pa->name, class)); 191244961713Sgirish return (EINVAL); 191344961713Sgirish } 191444961713Sgirish if (status != NXGE_OK) 191544961713Sgirish return (EINVAL); 191644961713Sgirish } 191744961713Sgirish 191844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_fflp_hash_init")); 191944961713Sgirish return (0); 192044961713Sgirish } 192144961713Sgirish 192244961713Sgirish /* ARGSUSED */ 192344961713Sgirish static int 192444961713Sgirish nxge_param_set_grp_rdc(p_nxge_t nxgep, queue_t *q, 1925a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 192644961713Sgirish { 1927a3c5bd6dSspeer char *end; 1928a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1929a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1930a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 1931a3c5bd6dSspeer int rdc_grp; 1932a3c5bd6dSspeer uint8_t real_rdc; 193344961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 193444961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 193544961713Sgirish p_nxge_rdc_grp_t rdc_grp_p; 193644961713Sgirish 193744961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 193844961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 193944961713Sgirish 194044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_grp_rdc")); 194144961713Sgirish 194244961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 194344961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 194444961713Sgirish return (EINVAL); 194544961713Sgirish } 1946a3c5bd6dSspeer 194744961713Sgirish if (cfg_value >= p_cfgp->max_rdcs) { 194844961713Sgirish return (EINVAL); 194944961713Sgirish } 1950a3c5bd6dSspeer 195144961713Sgirish if (pa->value != cfg_value) { 195244961713Sgirish pa->old_value = pa->value; 195344961713Sgirish pa->value = cfg_value; 195444961713Sgirish cfg_it = B_TRUE; 195544961713Sgirish } 195644961713Sgirish 195744961713Sgirish if (cfg_it == B_TRUE) { 195844961713Sgirish char *grp_name; 195944961713Sgirish grp_name = pa->name; 196044961713Sgirish grp_name += strlen("default-grp"); 196144961713Sgirish rdc_grp = mi_strtol(grp_name, &end, 10); 196244961713Sgirish rdc_grp_p = &p_dma_cfgp->rdc_grps[rdc_grp]; 196344961713Sgirish real_rdc = rdc_grp_p->start_rdc + cfg_value; 196444961713Sgirish if (nxge_check_rxdma_rdcgrp_member(nxgep, rdc_grp, 1965a3c5bd6dSspeer cfg_value) == B_FALSE) { 196644961713Sgirish pa->value = pa->old_value; 196744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1968a3c5bd6dSspeer " nxge_param_set_grp_rdc" 1969a3c5bd6dSspeer " %d read %d actual %d outof range", 1970a3c5bd6dSspeer rdc_grp, cfg_value, real_rdc)); 197144961713Sgirish return (EINVAL); 197244961713Sgirish } 197344961713Sgirish status = nxge_rxdma_cfg_rdcgrp_default_rdc(nxgep, rdc_grp, 197444961713Sgirish real_rdc); 197544961713Sgirish if (status != NXGE_OK) 197644961713Sgirish return (EINVAL); 197744961713Sgirish } 197844961713Sgirish 197944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_grp_rdc")); 198044961713Sgirish return (0); 198144961713Sgirish } 198244961713Sgirish 198344961713Sgirish /* ARGSUSED */ 198444961713Sgirish static int 198544961713Sgirish nxge_param_set_port_rdc(p_nxge_t nxgep, queue_t *q, 1986a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 198744961713Sgirish { 1988a3c5bd6dSspeer char *end; 1989a3c5bd6dSspeer uint32_t status = B_TRUE, cfg_value; 1990a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1991a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 199244961713Sgirish 199344961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 199444961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 199544961713Sgirish 199644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_port_rdc")); 199744961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 199844961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 199944961713Sgirish 200044961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 200144961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 200244961713Sgirish return (EINVAL); 200344961713Sgirish } 2004a3c5bd6dSspeer 200544961713Sgirish if (pa->value != cfg_value) { 200644961713Sgirish if (cfg_value >= p_cfgp->max_rdcs) 200744961713Sgirish return (EINVAL); 200844961713Sgirish pa->old_value = pa->value; 200944961713Sgirish pa->value = cfg_value; 201044961713Sgirish cfg_it = B_TRUE; 201144961713Sgirish } 201244961713Sgirish 201344961713Sgirish if (cfg_it == B_TRUE) { 201444961713Sgirish status = nxge_rxdma_cfg_port_default_rdc(nxgep, 2015a3c5bd6dSspeer nxgep->function_num, 2016a3c5bd6dSspeer nxgep->rdc[cfg_value]); 201744961713Sgirish if (status != NXGE_OK) 201844961713Sgirish return (EINVAL); 201944961713Sgirish } 202044961713Sgirish 202144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_port_rdc")); 202244961713Sgirish return (0); 202344961713Sgirish } 202444961713Sgirish 202544961713Sgirish /* ARGSUSED */ 202644961713Sgirish static int 202744961713Sgirish nxge_param_set_nxge_debug_flag(p_nxge_t nxgep, queue_t *q, 2028a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 202944961713Sgirish { 203044961713Sgirish char *end; 203144961713Sgirish uint32_t status = 0; 203244961713Sgirish uint64_t cfg_value = 0; 203344961713Sgirish p_nxge_param_t pa = (p_nxge_param_t)cp; 203444961713Sgirish uint32_t cfg_it = B_FALSE; 203544961713Sgirish 203644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_nxge_debug_flag")); 203744961713Sgirish cfg_value = mi_strtol(value, &end, BASE_HEX); 203844961713Sgirish 203944961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 204044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 2041a3c5bd6dSspeer " nxge_param_set_nxge_debug_flag" 2042a3c5bd6dSspeer " outof range %llx", cfg_value)); 204344961713Sgirish return (EINVAL); 204444961713Sgirish } 204544961713Sgirish if (pa->value != cfg_value) { 204644961713Sgirish pa->old_value = pa->value; 204744961713Sgirish pa->value = cfg_value; 204844961713Sgirish cfg_it = B_TRUE; 204944961713Sgirish } 205044961713Sgirish 205144961713Sgirish if (cfg_it == B_TRUE) { 205244961713Sgirish nxgep->nxge_debug_level = pa->value; 205344961713Sgirish } 2054a3c5bd6dSspeer 205544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_nxge_debug_flag")); 205644961713Sgirish return (status); 205744961713Sgirish } 205844961713Sgirish 205944961713Sgirish /* ARGSUSED */ 206044961713Sgirish static int 206144961713Sgirish nxge_param_get_debug_flag(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 206244961713Sgirish { 2063a3c5bd6dSspeer int status = 0; 2064a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 206544961713Sgirish 206644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_debug_flag")); 206744961713Sgirish 206844961713Sgirish if (pa->value > 0xffffffff) 206944961713Sgirish (void) mi_mpprintf(mp, "%x%x", (int)(pa->value >> 32), 2070a3c5bd6dSspeer (int)(pa->value & 0xffffffff)); 207144961713Sgirish else 207244961713Sgirish (void) mi_mpprintf(mp, "%x", (int)pa->value); 207344961713Sgirish 207444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_debug_flag")); 207544961713Sgirish return (status); 207644961713Sgirish } 207744961713Sgirish 207844961713Sgirish /* ARGSUSED */ 207944961713Sgirish static int 208044961713Sgirish nxge_param_set_npi_debug_flag(p_nxge_t nxgep, queue_t *q, 2081a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 208244961713Sgirish { 2083a3c5bd6dSspeer char *end; 2084a3c5bd6dSspeer uint32_t status = 0; 2085a3c5bd6dSspeer uint64_t cfg_value = 0; 2086a3c5bd6dSspeer p_nxge_param_t pa; 2087a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 208844961713Sgirish 208944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_npi_debug_flag")); 209044961713Sgirish cfg_value = mi_strtol(value, &end, BASE_HEX); 209144961713Sgirish pa = (p_nxge_param_t)cp; 209244961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 209344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_npi_debug_flag" 209444961713Sgirish " outof range %llx", cfg_value)); 209544961713Sgirish return (EINVAL); 209644961713Sgirish } 209744961713Sgirish if (pa->value != cfg_value) { 209844961713Sgirish pa->old_value = pa->value; 209944961713Sgirish pa->value = cfg_value; 210044961713Sgirish cfg_it = B_TRUE; 210144961713Sgirish } 210244961713Sgirish 210344961713Sgirish if (cfg_it == B_TRUE) { 210444961713Sgirish npi_debug_level = pa->value; 210544961713Sgirish } 210644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_debug_flag")); 210744961713Sgirish return (status); 210844961713Sgirish } 210944961713Sgirish 211044961713Sgirish /* ARGSUSED */ 211144961713Sgirish static int 211244961713Sgirish nxge_param_dump_rdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 211344961713Sgirish { 2114a3c5bd6dSspeer uint_t rdc; 211544961713Sgirish 211644961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_rdc")); 211744961713Sgirish 211844961713Sgirish (void) npi_rxdma_dump_fzc_regs(NXGE_DEV_NPI_HANDLE(nxgep)); 211944961713Sgirish for (rdc = 0; rdc < nxgep->nrdc; rdc++) 212044961713Sgirish (void) nxge_dump_rxdma_channel(nxgep, nxgep->rdc[rdc]); 212144961713Sgirish 212244961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_rdc")); 212344961713Sgirish return (0); 212444961713Sgirish } 212544961713Sgirish 212644961713Sgirish /* ARGSUSED */ 212744961713Sgirish static int 212844961713Sgirish nxge_param_dump_tdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 212944961713Sgirish { 213044961713Sgirish uint_t tdc; 213144961713Sgirish 213244961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_tdc")); 213344961713Sgirish 213444961713Sgirish for (tdc = 0; tdc < nxgep->ntdc; tdc++) 213544961713Sgirish (void) nxge_txdma_regs_dump(nxgep, nxgep->tdc[tdc]); 213644961713Sgirish 213744961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_tdc")); 213844961713Sgirish return (0); 213944961713Sgirish } 214044961713Sgirish 214144961713Sgirish /* ARGSUSED */ 214244961713Sgirish static int 214344961713Sgirish nxge_param_dump_fflp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 214444961713Sgirish { 214544961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_fflp_regs")); 214644961713Sgirish 214744961713Sgirish (void) npi_fflp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep)); 214844961713Sgirish 214944961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_fflp_regs")); 215044961713Sgirish return (0); 215144961713Sgirish } 215244961713Sgirish 215344961713Sgirish /* ARGSUSED */ 215444961713Sgirish static int 215544961713Sgirish nxge_param_dump_mac_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 215644961713Sgirish { 215744961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_mac_regs")); 215844961713Sgirish 215944961713Sgirish (void) npi_mac_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep), 2160a3c5bd6dSspeer nxgep->function_num); 216144961713Sgirish 216244961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_mac_regs")); 216344961713Sgirish return (0); 216444961713Sgirish } 216544961713Sgirish 216644961713Sgirish /* ARGSUSED */ 216744961713Sgirish static int 216844961713Sgirish nxge_param_dump_ipp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 216944961713Sgirish { 217044961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_ipp_regs")); 217144961713Sgirish 2172a3c5bd6dSspeer (void) npi_ipp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep), 2173a3c5bd6dSspeer nxgep->function_num); 217444961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ipp_regs")); 217544961713Sgirish return (0); 217644961713Sgirish } 217744961713Sgirish 217844961713Sgirish /* ARGSUSED */ 217944961713Sgirish static int 218044961713Sgirish nxge_param_dump_vlan_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 218144961713Sgirish { 218244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_vlan_table")); 218344961713Sgirish 218444961713Sgirish (void) npi_fflp_vlan_tbl_dump(NXGE_DEV_NPI_HANDLE(nxgep)); 218544961713Sgirish 218644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_vlan_table")); 218744961713Sgirish return (0); 218844961713Sgirish } 218944961713Sgirish 219044961713Sgirish /* ARGSUSED */ 219144961713Sgirish static int 219244961713Sgirish nxge_param_dump_rdc_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 219344961713Sgirish { 2194a3c5bd6dSspeer uint8_t table; 219544961713Sgirish 219644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_rdc_table")); 219744961713Sgirish for (table = 0; table < NXGE_MAX_RDC_GROUPS; table++) { 219844961713Sgirish (void) npi_rxdma_dump_rdc_table(NXGE_DEV_NPI_HANDLE(nxgep), 219944961713Sgirish table); 220044961713Sgirish } 2201a3c5bd6dSspeer 220244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_rdc_table")); 220344961713Sgirish return (0); 220444961713Sgirish } 220544961713Sgirish 220644961713Sgirish typedef struct block_info { 220744961713Sgirish char *name; 220844961713Sgirish uint32_t offset; 220944961713Sgirish } block_info_t; 221044961713Sgirish 221144961713Sgirish block_info_t reg_block[] = { 221244961713Sgirish {"PIO", PIO}, 221344961713Sgirish {"FZC_PIO", FZC_PIO}, 221444961713Sgirish {"FZC_XMAC", FZC_MAC}, 221544961713Sgirish {"FZC_IPP", FZC_IPP}, 221644961713Sgirish {"FFLP", FFLP}, 221744961713Sgirish {"FZC_FFLP", FZC_FFLP}, 221844961713Sgirish {"PIO_VADDR", PIO_VADDR}, 221944961713Sgirish {"ZCP", ZCP}, 222044961713Sgirish {"FZC_ZCP", FZC_ZCP}, 222144961713Sgirish {"DMC", DMC}, 222244961713Sgirish {"FZC_DMC", FZC_DMC}, 222344961713Sgirish {"TXC", TXC}, 222444961713Sgirish {"FZC_TXC", FZC_TXC}, 222544961713Sgirish {"PIO_LDSV", PIO_LDSV}, 222644961713Sgirish {"PIO_LDGIM", PIO_LDGIM}, 222744961713Sgirish {"PIO_IMASK0", PIO_IMASK0}, 222844961713Sgirish {"PIO_IMASK1", PIO_IMASK1}, 222944961713Sgirish {"FZC_PROM", FZC_PROM}, 223044961713Sgirish {"END", ALL_FF_32}, 223144961713Sgirish }; 223244961713Sgirish 223344961713Sgirish /* ARGSUSED */ 223444961713Sgirish static int 223544961713Sgirish nxge_param_dump_ptrs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 223644961713Sgirish { 2237a3c5bd6dSspeer uint_t print_len, buf_len; 2238a3c5bd6dSspeer p_mblk_t np; 2239a3c5bd6dSspeer int rdc, tdc, block; 2240a3c5bd6dSspeer uint64_t base; 224144961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 224244961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 2243a3c5bd6dSspeer int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_8K; 224444961713Sgirish p_tx_ring_t *tx_rings; 224544961713Sgirish p_rx_rcr_rings_t rx_rcr_rings; 224644961713Sgirish p_rx_rcr_ring_t *rcr_rings; 224744961713Sgirish p_rx_rbr_rings_t rx_rbr_rings; 224844961713Sgirish p_rx_rbr_ring_t *rbr_rings; 224944961713Sgirish 2250a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, IOC_CTL, 2251a3c5bd6dSspeer "==> nxge_param_dump_ptrs")); 225244961713Sgirish 2253a3c5bd6dSspeer (void) mi_mpprintf(mp, "ptr information for Port\t %d \n", 2254a3c5bd6dSspeer nxgep->function_num); 225544961713Sgirish 225644961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 225744961713Sgirish /* The following may work even if we cannot get a large buf. */ 225844961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 225944961713Sgirish return (0); 226044961713Sgirish } 226144961713Sgirish 226244961713Sgirish buf_len = buff_alloc_size; 226344961713Sgirish mp->b_cont = np; 226444961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 226544961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 226644961713Sgirish 226744961713Sgirish rx_rcr_rings = nxgep->rx_rcr_rings; 226844961713Sgirish rcr_rings = rx_rcr_rings->rcr_rings; 226944961713Sgirish rx_rbr_rings = nxgep->rx_rbr_rings; 227044961713Sgirish rbr_rings = rx_rbr_rings->rbr_rings; 227144961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2272a3c5bd6dSspeer "nxgep (nxge_t) $%p\n" 2273a3c5bd6dSspeer "dev_regs (dev_regs_t) $%p\n", 2274a3c5bd6dSspeer nxgep, nxgep->dev_regs); 227544961713Sgirish 227644961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2277a3c5bd6dSspeer 2278a3c5bd6dSspeer /* do register pointers */ 227944961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2280a3c5bd6dSspeer "reg base (npi_reg_ptr_t) $%p\t " 2281a3c5bd6dSspeer "pci reg (npi_reg_ptr_t) $%p\n", 2282a3c5bd6dSspeer nxgep->dev_regs->nxge_regp, 2283a3c5bd6dSspeer nxgep->dev_regs->nxge_pciregp); 228444961713Sgirish 228544961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 228644961713Sgirish 228744961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2288a3c5bd6dSspeer "\nBlock \t Offset \n"); 228944961713Sgirish 229044961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 229144961713Sgirish block = 0; 2292*adfcba55Sjoycey #if defined(__i386) 2293*adfcba55Sjoycey base = (uint64_t)(uint32_t)nxgep->dev_regs->nxge_regp; 2294*adfcba55Sjoycey #else 229544961713Sgirish base = (uint64_t)nxgep->dev_regs->nxge_regp; 2296*adfcba55Sjoycey #endif 229744961713Sgirish while (reg_block[block].offset != ALL_FF_32) { 229844961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2299a3c5bd6dSspeer "%9s\t 0x%llx\n", 2300a3c5bd6dSspeer reg_block[block].name, 2301a3c5bd6dSspeer (unsigned long long)(reg_block[block].offset + base)); 230244961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 230344961713Sgirish block++; 230444961713Sgirish } 230544961713Sgirish 230644961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2307a3c5bd6dSspeer "\nRDC\t rcrp (rx_rcr_ring_t)\t " 2308a3c5bd6dSspeer "rbrp (rx_rbr_ring_t)\n"); 230944961713Sgirish 231044961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 231144961713Sgirish 231244961713Sgirish for (rdc = 0; rdc < p_cfgp->max_rdcs; rdc++) { 231344961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2314a3c5bd6dSspeer " %d\t $%p\t\t $%p\n", 2315a3c5bd6dSspeer rdc, rcr_rings[rdc], 2316a3c5bd6dSspeer rbr_rings[rdc]); 231744961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 231844961713Sgirish } 231944961713Sgirish 232044961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 232144961713Sgirish "\nTDC\t tdcp (tx_ring_t)\n"); 232244961713Sgirish 232344961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 232444961713Sgirish tx_rings = nxgep->tx_rings->rings; 232544961713Sgirish for (tdc = 0; tdc < p_cfgp->max_tdcs; tdc++) { 232644961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2327a3c5bd6dSspeer " %d\t $%p\n", tdc, tx_rings[tdc]); 232844961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 232944961713Sgirish } 233044961713Sgirish 2331a3c5bd6dSspeer print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, "\n\n"); 233244961713Sgirish 233344961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 233444961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ptrs")); 233544961713Sgirish return (0); 233644961713Sgirish } 233744961713Sgirish 233844961713Sgirish /* 233944961713Sgirish * Load 'name' into the named dispatch table pointed to by 'ndp'. 234044961713Sgirish * 'ndp' should be the address of a char pointer cell. If the table 234144961713Sgirish * does not exist (*ndp == 0), a new table is allocated and 'ndp' 234244961713Sgirish * is stuffed. If there is not enough space in the table for a new 234344961713Sgirish * entry, more space is allocated. 234444961713Sgirish */ 2345a3c5bd6dSspeer /* ARGSUSED */ 234644961713Sgirish boolean_t 234744961713Sgirish nxge_nd_load(caddr_t *pparam, char *name, 2348a3c5bd6dSspeer pfi_t get_pfi, pfi_t set_pfi, caddr_t data) 234944961713Sgirish { 235044961713Sgirish ND *nd; 235144961713Sgirish NDE *nde; 235244961713Sgirish 235344961713Sgirish NXGE_DEBUG_MSG((NULL, NDD2_CTL, " ==> nxge_nd_load")); 235444961713Sgirish if (!pparam) 235544961713Sgirish return (B_FALSE); 2356a3c5bd6dSspeer 235744961713Sgirish if ((nd = (ND *)*pparam) == NULL) { 2358a3c5bd6dSspeer if ((nd = (ND *)KMEM_ZALLOC(sizeof (ND), KM_NOSLEEP)) == NULL) 235944961713Sgirish return (B_FALSE); 236044961713Sgirish *pparam = (caddr_t)nd; 236144961713Sgirish } 2362a3c5bd6dSspeer 236344961713Sgirish if (nd->nd_tbl) { 236444961713Sgirish for (nde = nd->nd_tbl; nde->nde_name; nde++) { 236544961713Sgirish if (strcmp(name, nde->nde_name) == 0) 236644961713Sgirish goto fill_it; 236744961713Sgirish } 236844961713Sgirish } 2369a3c5bd6dSspeer 237044961713Sgirish if (nd->nd_free_count <= 1) { 237144961713Sgirish if ((nde = (NDE *)KMEM_ZALLOC(nd->nd_size + 237244961713Sgirish NDE_ALLOC_SIZE, KM_NOSLEEP)) == NULL) 237344961713Sgirish return (B_FALSE); 237444961713Sgirish nd->nd_free_count += NDE_ALLOC_COUNT; 237544961713Sgirish if (nd->nd_tbl) { 237644961713Sgirish bcopy((char *)nd->nd_tbl, (char *)nde, nd->nd_size); 237744961713Sgirish KMEM_FREE((char *)nd->nd_tbl, nd->nd_size); 237844961713Sgirish } else { 237944961713Sgirish nd->nd_free_count--; 238044961713Sgirish nde->nde_name = "?"; 238144961713Sgirish nde->nde_get_pfi = nxge_nd_get_names; 238244961713Sgirish nde->nde_set_pfi = nxge_set_default; 238344961713Sgirish } 238444961713Sgirish nde->nde_data = (caddr_t)nd; 238544961713Sgirish nd->nd_tbl = nde; 238644961713Sgirish nd->nd_size += NDE_ALLOC_SIZE; 238744961713Sgirish } 238844961713Sgirish for (nde = nd->nd_tbl; nde->nde_name; nde++) 238944961713Sgirish noop; 239044961713Sgirish nd->nd_free_count--; 239144961713Sgirish fill_it: 239244961713Sgirish nde->nde_name = name; 239344961713Sgirish nde->nde_get_pfi = get_pfi; 239444961713Sgirish nde->nde_set_pfi = set_pfi; 239544961713Sgirish nde->nde_data = data; 239644961713Sgirish NXGE_DEBUG_MSG((NULL, NDD2_CTL, " <== nxge_nd_load")); 239744961713Sgirish 239844961713Sgirish return (B_TRUE); 239944961713Sgirish } 240044961713Sgirish 240144961713Sgirish /* 240244961713Sgirish * Free the table pointed to by 'pparam' 240344961713Sgirish */ 240444961713Sgirish void 240544961713Sgirish nxge_nd_free(caddr_t *pparam) 240644961713Sgirish { 2407a3c5bd6dSspeer ND *nd; 240844961713Sgirish 240944961713Sgirish if ((nd = (ND *)*pparam) != NULL) { 241044961713Sgirish if (nd->nd_tbl) 241144961713Sgirish KMEM_FREE((char *)nd->nd_tbl, nd->nd_size); 241244961713Sgirish KMEM_FREE((char *)nd, sizeof (ND)); 241344961713Sgirish *pparam = nil(caddr_t); 241444961713Sgirish } 241544961713Sgirish } 241644961713Sgirish 241744961713Sgirish int 241844961713Sgirish nxge_nd_getset(p_nxge_t nxgep, queue_t *q, caddr_t param, p_mblk_t mp) 241944961713Sgirish { 2420a3c5bd6dSspeer int err; 2421a3c5bd6dSspeer IOCP iocp; 2422a3c5bd6dSspeer p_mblk_t mp1, mp2; 2423a3c5bd6dSspeer ND *nd; 2424a3c5bd6dSspeer NDE *nde; 2425a3c5bd6dSspeer char *valp; 2426a3c5bd6dSspeer size_t avail; 242744961713Sgirish 242844961713Sgirish if (!param) { 242944961713Sgirish return (B_FALSE); 243044961713Sgirish } 2431a3c5bd6dSspeer 243244961713Sgirish nd = (ND *)param; 243344961713Sgirish iocp = (IOCP)mp->b_rptr; 243444961713Sgirish if ((iocp->ioc_count == 0) || !(mp1 = mp->b_cont)) { 243544961713Sgirish mp->b_datap->db_type = M_IOCACK; 243644961713Sgirish iocp->ioc_count = 0; 243744961713Sgirish iocp->ioc_error = EINVAL; 243844961713Sgirish return (B_FALSE); 243944961713Sgirish } 2440a3c5bd6dSspeer 244144961713Sgirish /* 244244961713Sgirish * NOTE - logic throughout nd_xxx assumes single data block for ioctl. 244344961713Sgirish * However, existing code sends in some big buffers. 244444961713Sgirish */ 244544961713Sgirish avail = iocp->ioc_count; 244644961713Sgirish if (mp1->b_cont) { 244744961713Sgirish freemsg(mp1->b_cont); 244844961713Sgirish mp1->b_cont = NULL; 244944961713Sgirish } 245044961713Sgirish 245144961713Sgirish mp1->b_datap->db_lim[-1] = '\0'; /* Force null termination */ 245244961713Sgirish for (valp = (char *)mp1->b_rptr; *valp != '\0'; valp++) { 245344961713Sgirish if (*valp == '-') 245444961713Sgirish *valp = '_'; 245544961713Sgirish } 245644961713Sgirish 245744961713Sgirish valp = (char *)mp1->b_rptr; 245844961713Sgirish 245944961713Sgirish for (nde = nd->nd_tbl; /* */; nde++) { 246044961713Sgirish if (!nde->nde_name) 246144961713Sgirish return (B_FALSE); 246244961713Sgirish if (strcmp(nde->nde_name, valp) == 0) 246344961713Sgirish break; 246444961713Sgirish } 246544961713Sgirish err = EINVAL; 246644961713Sgirish while (*valp++) 246744961713Sgirish noop; 246844961713Sgirish if (!*valp || valp >= (char *)mp1->b_wptr) 246944961713Sgirish valp = nilp(char); 247044961713Sgirish switch (iocp->ioc_cmd) { 247144961713Sgirish case ND_GET: 247244961713Sgirish /* 247344961713Sgirish * (temporary) hack: "*valp" is size of user buffer for 247444961713Sgirish * copyout. If result of action routine is too big, free 247544961713Sgirish * excess and return ioc_rval as buffer size needed. 247644961713Sgirish * Return as many mblocks as will fit, free the rest. For 247744961713Sgirish * backward compatibility, assume size of original ioctl 247844961713Sgirish * buffer if "*valp" bad or not given. 247944961713Sgirish */ 248044961713Sgirish if (valp) 248144961713Sgirish avail = mi_strtol(valp, (char **)0, 10); 248244961713Sgirish /* 248344961713Sgirish * We overwrite the name/value with the reply data 248444961713Sgirish */ 248544961713Sgirish mp2 = mp1; 248644961713Sgirish while (mp2) { 248744961713Sgirish mp2->b_wptr = mp2->b_rptr; 248844961713Sgirish mp2 = mp2->b_cont; 248944961713Sgirish } 249044961713Sgirish 2491846a903dSml if (nde->nde_get_pfi) { 2492846a903dSml err = (*nde->nde_get_pfi)(nxgep, q, mp1, nde->nde_data); 2493846a903dSml } 249444961713Sgirish 249544961713Sgirish if (!err) { 249644961713Sgirish size_t size_out = 0; 2497958cea9eSml ssize_t excess; 249844961713Sgirish 249944961713Sgirish iocp->ioc_rval = 0; 250044961713Sgirish 250144961713Sgirish /* Tack on the null */ 250244961713Sgirish err = nxge_mk_mblk_tail_space(mp1, &mp2, 1); 250344961713Sgirish if (!err) { 250444961713Sgirish *mp2->b_wptr++ = '\0'; 250544961713Sgirish size_out = msgdsize(mp1); 250644961713Sgirish excess = size_out - avail; 250744961713Sgirish if (excess > 0) { 250844961713Sgirish iocp->ioc_rval = (int)size_out; 250944961713Sgirish size_out -= excess; 251044961713Sgirish (void) adjmsg(mp1, -(excess + 1)); 251144961713Sgirish err = nxge_mk_mblk_tail_space( 251244961713Sgirish mp1, &mp2, 1); 251344961713Sgirish if (!err) 251444961713Sgirish *mp2->b_wptr++ = '\0'; 251544961713Sgirish else 251644961713Sgirish size_out = 0; 251744961713Sgirish } 251844961713Sgirish } else 251944961713Sgirish size_out = 0; 252044961713Sgirish iocp->ioc_count = size_out; 252144961713Sgirish } 252244961713Sgirish break; 252344961713Sgirish 252444961713Sgirish case ND_SET: 252544961713Sgirish if (valp) { 252644961713Sgirish if (nde->nde_set_pfi) { 252744961713Sgirish err = (*nde->nde_set_pfi)(nxgep, q, mp1, valp, 252844961713Sgirish nde->nde_data); 252944961713Sgirish iocp->ioc_count = 0; 253044961713Sgirish freemsg(mp1); 253144961713Sgirish mp->b_cont = NULL; 253244961713Sgirish } 253344961713Sgirish } 253444961713Sgirish break; 253544961713Sgirish 253644961713Sgirish default: 253744961713Sgirish break; 253844961713Sgirish } 253944961713Sgirish iocp->ioc_error = err; 254044961713Sgirish mp->b_datap->db_type = M_IOCACK; 254144961713Sgirish return (B_TRUE); 254244961713Sgirish } 254344961713Sgirish 254444961713Sgirish /* ARGSUSED */ 254544961713Sgirish int 254644961713Sgirish nxge_nd_get_names(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t param) 254744961713Sgirish { 2548a3c5bd6dSspeer ND *nd; 2549a3c5bd6dSspeer NDE *nde; 2550a3c5bd6dSspeer char *rwtag; 2551a3c5bd6dSspeer boolean_t get_ok, set_ok; 2552a3c5bd6dSspeer size_t param_len; 2553a3c5bd6dSspeer int status = 0; 255444961713Sgirish 255544961713Sgirish nd = (ND *)param; 255644961713Sgirish if (!nd) 255744961713Sgirish return (ENOENT); 255844961713Sgirish 255944961713Sgirish for (nde = nd->nd_tbl; nde->nde_name; nde++) { 256044961713Sgirish get_ok = (nde->nde_get_pfi != nxge_get_default) && 256144961713Sgirish (nde->nde_get_pfi != NULL); 256244961713Sgirish set_ok = (nde->nde_set_pfi != nxge_set_default) && 256344961713Sgirish (nde->nde_set_pfi != NULL); 256444961713Sgirish if (get_ok) { 256544961713Sgirish if (set_ok) 256644961713Sgirish rwtag = "read and write"; 256744961713Sgirish else 256844961713Sgirish rwtag = "read only"; 256944961713Sgirish } else if (set_ok) 257044961713Sgirish rwtag = "write only"; 257144961713Sgirish else { 257244961713Sgirish continue; 257344961713Sgirish } 257444961713Sgirish param_len = strlen(rwtag); 257544961713Sgirish param_len += strlen(nde->nde_name); 257644961713Sgirish param_len += 4; 257744961713Sgirish 257844961713Sgirish (void) mi_mpprintf(mp, "%s (%s)", nde->nde_name, rwtag); 257944961713Sgirish } 258044961713Sgirish return (status); 258144961713Sgirish } 258244961713Sgirish 258344961713Sgirish /* ARGSUSED */ 258444961713Sgirish int 258544961713Sgirish nxge_get_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t data) 258644961713Sgirish { 258744961713Sgirish return (EACCES); 258844961713Sgirish } 258944961713Sgirish 259044961713Sgirish /* ARGSUSED */ 259144961713Sgirish int 259244961713Sgirish nxge_set_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, char *value, 2593a3c5bd6dSspeer caddr_t data) 259444961713Sgirish { 259544961713Sgirish return (EACCES); 259644961713Sgirish } 259744961713Sgirish 259844961713Sgirish void 259944961713Sgirish nxge_param_ioctl(p_nxge_t nxgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 260044961713Sgirish { 260144961713Sgirish int cmd; 260244961713Sgirish int status = B_FALSE; 260344961713Sgirish 260444961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_ioctl")); 260544961713Sgirish cmd = iocp->ioc_cmd; 2606a3c5bd6dSspeer 260744961713Sgirish switch (cmd) { 260844961713Sgirish default: 260944961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, 261044961713Sgirish "nxge_param_ioctl: bad cmd 0x%0x", cmd)); 261144961713Sgirish break; 261244961713Sgirish 261344961713Sgirish case ND_GET: 261444961713Sgirish case ND_SET: 261544961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, 261644961713Sgirish "nxge_param_ioctl: cmd 0x%0x", cmd)); 261744961713Sgirish if (!nxge_nd_getset(nxgep, wq, nxgep->param_list, mp)) { 261844961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, 261944961713Sgirish "false ret from nxge_nd_getset")); 262044961713Sgirish break; 262144961713Sgirish } 262244961713Sgirish status = B_TRUE; 262344961713Sgirish break; 262444961713Sgirish } 262544961713Sgirish 262644961713Sgirish if (status) { 262744961713Sgirish qreply(wq, mp); 262844961713Sgirish } else { 262944961713Sgirish miocnak(wq, mp, 0, EINVAL); 263044961713Sgirish } 263144961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_ioctl")); 263244961713Sgirish } 263344961713Sgirish 263444961713Sgirish /* ARGSUSED */ 263544961713Sgirish static boolean_t 263644961713Sgirish nxge_param_link_update(p_nxge_t nxgep) 263744961713Sgirish { 263844961713Sgirish p_nxge_param_t param_arr; 263944961713Sgirish nxge_param_index_t i; 264044961713Sgirish boolean_t update_xcvr; 264144961713Sgirish boolean_t update_dev; 264244961713Sgirish int instance; 264344961713Sgirish boolean_t status = B_TRUE; 264444961713Sgirish 264544961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_link_update")); 264644961713Sgirish 264744961713Sgirish param_arr = nxgep->param_arr; 264844961713Sgirish instance = nxgep->instance; 264944961713Sgirish update_xcvr = B_FALSE; 265044961713Sgirish for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) { 265144961713Sgirish update_xcvr |= param_arr[i].value; 265244961713Sgirish } 265344961713Sgirish 265444961713Sgirish if (update_xcvr) { 265544961713Sgirish update_xcvr = B_FALSE; 265644961713Sgirish for (i = param_autoneg; i < param_enable_ipg0; i++) { 265744961713Sgirish update_xcvr |= 265844961713Sgirish (param_arr[i].value != param_arr[i].old_value); 265944961713Sgirish param_arr[i].old_value = param_arr[i].value; 266044961713Sgirish } 266144961713Sgirish if (update_xcvr) { 266244961713Sgirish RW_ENTER_WRITER(&nxgep->filter_lock); 266344961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 266444961713Sgirish (void) nxge_link_init(nxgep); 266544961713Sgirish (void) nxge_mac_init(nxgep); 266644961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 266744961713Sgirish RW_EXIT(&nxgep->filter_lock); 266844961713Sgirish } 266944961713Sgirish } else { 267044961713Sgirish cmn_err(CE_WARN, " Last setting will leave nxge%d with " 267144961713Sgirish " no link capabilities.", instance); 267244961713Sgirish cmn_err(CE_WARN, " Restoring previous setting."); 267344961713Sgirish for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) 267444961713Sgirish param_arr[i].value = param_arr[i].old_value; 267544961713Sgirish } 2676a3c5bd6dSspeer 267744961713Sgirish update_dev = B_FALSE; 267844961713Sgirish 267944961713Sgirish if (update_dev) { 268044961713Sgirish RW_ENTER_WRITER(&nxgep->filter_lock); 268144961713Sgirish (void) nxge_rx_mac_disable(nxgep); 268244961713Sgirish (void) nxge_tx_mac_disable(nxgep); 268344961713Sgirish (void) nxge_tx_mac_enable(nxgep); 268444961713Sgirish (void) nxge_rx_mac_enable(nxgep); 268544961713Sgirish RW_EXIT(&nxgep->filter_lock); 268644961713Sgirish } 268744961713Sgirish 268844961713Sgirish nxge_param_hw_update_exit: 268944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 269044961713Sgirish "<== nxge_param_link_update status = 0x%08x", status)); 269144961713Sgirish return (status); 269244961713Sgirish } 2693