144961713Sgirish /* 244961713Sgirish * CDDL HEADER START 344961713Sgirish * 444961713Sgirish * The contents of this file are subject to the terms of the 544961713Sgirish * Common Development and Distribution License (the "License"). 644961713Sgirish * You may not use this file except in compliance with the License. 744961713Sgirish * 844961713Sgirish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 944961713Sgirish * or http://www.opensolaris.org/os/licensing. 1044961713Sgirish * See the License for the specific language governing permissions 1144961713Sgirish * and limitations under the License. 1244961713Sgirish * 1344961713Sgirish * When distributing Covered Code, include this CDDL HEADER in each 1444961713Sgirish * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1544961713Sgirish * If applicable, add the following below this CDDL HEADER, with the 1644961713Sgirish * fields enclosed by brackets "[]" replaced with your own identifying 1744961713Sgirish * information: Portions Copyright [yyyy] [name of copyright owner] 1844961713Sgirish * 1944961713Sgirish * CDDL HEADER END 2044961713Sgirish */ 2144961713Sgirish /* 22a3c5bd6dSspeer * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 2344961713Sgirish * Use is subject to license terms. 2444961713Sgirish */ 2544961713Sgirish 2644961713Sgirish #pragma ident "%Z%%M% %I% %E% SMI" 2744961713Sgirish 2844961713Sgirish #include <sys/nxge/nxge_impl.h> 2944961713Sgirish #include <inet/common.h> 3044961713Sgirish #include <inet/mi.h> 3144961713Sgirish #include <inet/nd.h> 3244961713Sgirish 3344961713Sgirish extern uint64_t npi_debug_level; 3444961713Sgirish 35a3c5bd6dSspeer #define NXGE_PARAM_MAC_RW \ 36a3c5bd6dSspeer NXGE_PARAM_RW | NXGE_PARAM_MAC | \ 3744961713Sgirish NXGE_PARAM_NDD_WR_OK | NXGE_PARAM_READ_PROP 3844961713Sgirish 39a3c5bd6dSspeer #define NXGE_PARAM_MAC_DONT_SHOW \ 40a3c5bd6dSspeer NXGE_PARAM_RW | NXGE_PARAM_MAC | NXGE_PARAM_DONT_SHOW 4144961713Sgirish 42a3c5bd6dSspeer #define NXGE_PARAM_RXDMA_RW \ 43a3c5bd6dSspeer NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_NDD_WR_OK | \ 44a3c5bd6dSspeer NXGE_PARAM_READ_PROP 4544961713Sgirish 46a3c5bd6dSspeer #define NXGE_PARAM_RXDMA_RWC \ 47a3c5bd6dSspeer NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_INIT_ONLY | \ 48a3c5bd6dSspeer NXGE_PARAM_READ_PROP 4944961713Sgirish 50a3c5bd6dSspeer #define NXGE_PARAM_L2CLASS_CFG \ 51a3c5bd6dSspeer NXGE_PARAM_RW | NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_READ_PROP | \ 52a3c5bd6dSspeer NXGE_PARAM_NDD_WR_OK 5344961713Sgirish 54a3c5bd6dSspeer #define NXGE_PARAM_CLASS_RWS \ 55a3c5bd6dSspeer NXGE_PARAM_RWS | NXGE_PARAM_READ_PROP 5644961713Sgirish 5744961713Sgirish #define NXGE_PARAM_ARRAY_INIT_SIZE 0x20ULL 5844961713Sgirish 5944961713Sgirish #define SET_RX_INTR_TIME_DISABLE 0 6044961713Sgirish #define SET_RX_INTR_TIME_ENABLE 1 6144961713Sgirish #define SET_RX_INTR_PKTS 2 6244961713Sgirish 6344961713Sgirish #define BASE_ANY 0 64a3c5bd6dSspeer #define BASE_BINARY 2 6544961713Sgirish #define BASE_HEX 16 6644961713Sgirish #define BASE_DECIMAL 10 6744961713Sgirish #define ALL_FF_64 0xFFFFFFFFFFFFFFFFULL 6844961713Sgirish #define ALL_FF_32 0xFFFFFFFFUL 6944961713Sgirish 7044961713Sgirish #define NXGE_NDD_INFODUMP_BUFF_SIZE 2048 /* is 2k enough? */ 7144961713Sgirish #define NXGE_NDD_INFODUMP_BUFF_8K 8192 7244961713Sgirish #define NXGE_NDD_INFODUMP_BUFF_16K 0x2000 7344961713Sgirish #define NXGE_NDD_INFODUMP_BUFF_64K 0x8000 7444961713Sgirish 7544961713Sgirish #define PARAM_OUTOF_RANGE(vptr, eptr, rval, pa) \ 7644961713Sgirish ((vptr == eptr) || (rval < pa->minimum) || (rval > pa->maximum)) 7744961713Sgirish 7844961713Sgirish #define ADVANCE_PRINT_BUFFER(pmp, plen, rlen) { \ 7944961713Sgirish ((mblk_t *)pmp)->b_wptr += plen; \ 8044961713Sgirish rlen -= plen; \ 81a3c5bd6dSspeer } 8244961713Sgirish 8344961713Sgirish static int nxge_param_rx_intr_pkts(p_nxge_t, queue_t *, 84a3c5bd6dSspeer mblk_t *, char *, caddr_t); 8544961713Sgirish static int nxge_param_rx_intr_time(p_nxge_t, queue_t *, 86a3c5bd6dSspeer mblk_t *, char *, caddr_t); 8744961713Sgirish static int nxge_param_set_mac(p_nxge_t, queue_t *, 88a3c5bd6dSspeer mblk_t *, char *, caddr_t); 8944961713Sgirish static int nxge_param_set_port_rdc(p_nxge_t, queue_t *, 90a3c5bd6dSspeer mblk_t *, char *, caddr_t); 9144961713Sgirish static int nxge_param_set_grp_rdc(p_nxge_t, queue_t *, 92a3c5bd6dSspeer mblk_t *, char *, caddr_t); 9344961713Sgirish static int nxge_param_set_ether_usr(p_nxge_t, 94a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 9544961713Sgirish static int nxge_param_set_ip_usr(p_nxge_t, 96a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 9744961713Sgirish static int nxge_param_set_ip_opt(p_nxge_t, 98a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 9944961713Sgirish static int nxge_param_set_vlan_rdcgrp(p_nxge_t, 100a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 10144961713Sgirish static int nxge_param_set_mac_rdcgrp(p_nxge_t, 102a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 10344961713Sgirish static int nxge_param_fflp_hash_init(p_nxge_t, 104a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 10544961713Sgirish static int nxge_param_llc_snap_enable(p_nxge_t, queue_t *, 106a3c5bd6dSspeer mblk_t *, char *, caddr_t); 10744961713Sgirish static int nxge_param_hash_lookup_enable(p_nxge_t, queue_t *, 108a3c5bd6dSspeer mblk_t *, char *, caddr_t); 10944961713Sgirish static int nxge_param_tcam_enable(p_nxge_t, queue_t *, 110a3c5bd6dSspeer mblk_t *, char *, caddr_t); 11156d930aeSspeer static int nxge_param_get_fw_ver(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 11244961713Sgirish static int nxge_param_get_rxdma_info(p_nxge_t, queue_t *q, 113a3c5bd6dSspeer p_mblk_t, caddr_t); 11444961713Sgirish static int nxge_param_get_txdma_info(p_nxge_t, queue_t *q, 115a3c5bd6dSspeer p_mblk_t, caddr_t); 11644961713Sgirish static int nxge_param_get_vlan_rdcgrp(p_nxge_t, queue_t *, 117a3c5bd6dSspeer p_mblk_t, caddr_t); 11844961713Sgirish static int nxge_param_get_mac_rdcgrp(p_nxge_t, queue_t *, 119a3c5bd6dSspeer p_mblk_t, caddr_t); 12044961713Sgirish static int nxge_param_get_rxdma_rdcgrp_info(p_nxge_t, queue_t *, 121a3c5bd6dSspeer p_mblk_t, caddr_t); 12244961713Sgirish static int nxge_param_get_ip_opt(p_nxge_t, queue_t *, mblk_t *, caddr_t); 123a3c5bd6dSspeer static int nxge_param_get_mac(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 12444961713Sgirish static int nxge_param_get_debug_flag(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 12544961713Sgirish static int nxge_param_set_nxge_debug_flag(p_nxge_t, queue_t *, mblk_t *, 126a3c5bd6dSspeer char *, caddr_t); 12744961713Sgirish static int nxge_param_set_npi_debug_flag(p_nxge_t, 128a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 12944961713Sgirish static int nxge_param_dump_rdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 13044961713Sgirish static int nxge_param_dump_tdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 13144961713Sgirish static int nxge_param_dump_mac_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 13244961713Sgirish static int nxge_param_dump_ipp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 13344961713Sgirish static int nxge_param_dump_fflp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 13444961713Sgirish static int nxge_param_dump_vlan_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 13544961713Sgirish static int nxge_param_dump_rdc_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 13644961713Sgirish static int nxge_param_dump_ptrs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 13744961713Sgirish static boolean_t nxge_param_link_update(p_nxge_t); 13844961713Sgirish 13944961713Sgirish /* 14044961713Sgirish * Global array of Neptune changable parameters. 14144961713Sgirish * This array is initialized to correspond to the default 14244961713Sgirish * Neptune 4 port configuration. This array would be copied 14344961713Sgirish * into each port's parameter structure and modifed per 14444961713Sgirish * fcode and nxge.conf configuration. Later, the parameters are 14544961713Sgirish * exported to ndd to display and run-time configuration (at least 14644961713Sgirish * some of them). 14744961713Sgirish * 14844961713Sgirish */ 14944961713Sgirish 150a3c5bd6dSspeer static nxge_param_t nxge_param_arr[] = { 151a3c5bd6dSspeer /* 152a3c5bd6dSspeer * min max value old hw-name conf-name 153a3c5bd6dSspeer */ 154846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 155a3c5bd6dSspeer 0, 999, 1000, 0, "instance", "instance"}, 156a3c5bd6dSspeer 157846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 158a3c5bd6dSspeer 0, 999, 1000, 0, "main-instance", "main_instance"}, 159a3c5bd6dSspeer 160a3c5bd6dSspeer { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 161a3c5bd6dSspeer 0, 3, 0, 0, "function-number", "function_number"}, 162a3c5bd6dSspeer 163a3c5bd6dSspeer /* Partition Id */ 164846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 165a3c5bd6dSspeer 0, 8, 0, 0, "partition-id", "partition_id"}, 166a3c5bd6dSspeer 167a3c5bd6dSspeer /* Read Write Permission Mode */ 168846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 169a3c5bd6dSspeer 0, 2, 0, 0, "read-write-mode", "read_write_mode"}, 170a3c5bd6dSspeer 17156d930aeSspeer { nxge_param_get_fw_ver, NULL, NXGE_PARAM_READ, 17256d930aeSspeer 0, 32, 0, 0, "version", "fw_version"}, 17356d930aeSspeer 174a3c5bd6dSspeer /* hw cfg types */ 175a3c5bd6dSspeer /* control the DMA config of Neptune/NIU */ 176846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 177a3c5bd6dSspeer CFG_DEFAULT, CFG_CUSTOM, CFG_DEFAULT, CFG_DEFAULT, 178a3c5bd6dSspeer "niu-cfg-type", "niu_cfg_type"}, 179a3c5bd6dSspeer 180a3c5bd6dSspeer /* control the TXDMA config of the Port controlled by tx-quick-cfg */ 181846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 182a3c5bd6dSspeer CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT, 183a3c5bd6dSspeer "tx-qcfg-type", "tx_qcfg_type"}, 184a3c5bd6dSspeer 185a3c5bd6dSspeer /* control the RXDMA config of the Port controlled by rx-quick-cfg */ 186846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 187a3c5bd6dSspeer CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT, 188a3c5bd6dSspeer "rx-qcfg-type", "rx_qcfg_type"}, 189a3c5bd6dSspeer 190a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, 191a3c5bd6dSspeer NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 192a3c5bd6dSspeer 0, 1, 0, 0, "master-cfg-enable", "master_cfg_enable"}, 193a3c5bd6dSspeer 194a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, 195846a903dSml NXGE_PARAM_DONT_SHOW, 196a3c5bd6dSspeer 0, 1, 0, 0, "master-cfg-value", "master_cfg_value"}, 197a3c5bd6dSspeer 198a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 199a3c5bd6dSspeer 0, 1, 1, 1, "adv-autoneg-cap", "adv_autoneg_cap"}, 200a3c5bd6dSspeer 201a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 202a3c5bd6dSspeer 0, 1, 1, 1, "adv-10gfdx-cap", "adv_10gfdx_cap"}, 203a3c5bd6dSspeer 204a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 205a3c5bd6dSspeer 0, 1, 0, 0, "adv-10ghdx-cap", "adv_10ghdx_cap"}, 206a3c5bd6dSspeer 207a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 208a3c5bd6dSspeer 0, 1, 1, 1, "adv-1000fdx-cap", "adv_1000fdx_cap"}, 209a3c5bd6dSspeer 210a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 211a3c5bd6dSspeer 0, 1, 0, 0, "adv-1000hdx-cap", "adv_1000hdx_cap"}, 212a3c5bd6dSspeer 213a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 214a3c5bd6dSspeer 0, 1, 0, 0, "adv-100T4-cap", "adv_100T4_cap"}, 215a3c5bd6dSspeer 216a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 217a3c5bd6dSspeer 0, 1, 1, 1, "adv-100fdx-cap", "adv_100fdx_cap"}, 218a3c5bd6dSspeer 219a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 220a3c5bd6dSspeer 0, 1, 0, 0, "adv-100hdx-cap", "adv_100hdx_cap"}, 221a3c5bd6dSspeer 222a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 223a3c5bd6dSspeer 0, 1, 1, 1, "adv-10fdx-cap", "adv_10fdx_cap"}, 224a3c5bd6dSspeer 225a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 226a3c5bd6dSspeer 0, 1, 0, 0, "adv-10hdx-cap", "adv_10hdx_cap"}, 227a3c5bd6dSspeer 228846a903dSml { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 229a3c5bd6dSspeer 0, 1, 0, 0, "adv-asmpause-cap", "adv_asmpause_cap"}, 230a3c5bd6dSspeer 231a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 232a3c5bd6dSspeer 0, 1, 0, 0, "adv-pause-cap", "adv_pause_cap"}, 233a3c5bd6dSspeer 234846a903dSml { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 235a3c5bd6dSspeer 0, 1, 0, 0, "use-int-xcvr", "use_int_xcvr"}, 236a3c5bd6dSspeer 237846a903dSml { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 238a3c5bd6dSspeer 0, 1, 1, 1, "enable-ipg0", "enable_ipg0"}, 239a3c5bd6dSspeer 240846a903dSml { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 241a3c5bd6dSspeer 0, 255, 8, 8, "ipg0", "ipg0"}, 242a3c5bd6dSspeer 243846a903dSml { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 244a3c5bd6dSspeer 0, 255, 8, 8, "ipg1", "ipg1"}, 245a3c5bd6dSspeer 246846a903dSml { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 247a3c5bd6dSspeer 0, 255, 4, 4, "ipg2", "ipg2"}, 248a3c5bd6dSspeer 249a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 250a3c5bd6dSspeer 0, 1, 0, 0, "accept-jumbo", "accept_jumbo"}, 251a3c5bd6dSspeer 252a3c5bd6dSspeer /* Transmit DMA channels */ 253846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 254846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 255a3c5bd6dSspeer 0, 3, 0, 0, "tx-dma-weight", "tx_dma_weight"}, 256a3c5bd6dSspeer 257846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 258846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 259a3c5bd6dSspeer 0, 31, 0, 0, "tx-dma-channels-begin", "tx_dma_channels_begin"}, 260a3c5bd6dSspeer 261846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 262846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 263a3c5bd6dSspeer 0, 32, 0, 0, "tx-dma-channels", "tx_dma_channels"}, 264a3c5bd6dSspeer { nxge_param_get_txdma_info, NULL, 265846a903dSml NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 266a3c5bd6dSspeer 0, 32, 0, 0, "tx-dma-info", "tx_dma_info"}, 267a3c5bd6dSspeer 268a3c5bd6dSspeer /* Receive DMA channels */ 269a3c5bd6dSspeer { nxge_param_get_generic, NULL, 270846a903dSml NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 271a3c5bd6dSspeer 0, 31, 0, 0, "rx-dma-channels-begin", "rx_dma_channels_begin"}, 272a3c5bd6dSspeer 273846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 274846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 275a3c5bd6dSspeer 0, 32, 0, 0, "rx-dma-channels", "rx_dma_channels"}, 276a3c5bd6dSspeer 277846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 278846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 279a3c5bd6dSspeer 0, 65535, PT_DRR_WT_DEFAULT_10G, 0, 280a3c5bd6dSspeer "rx-drr-weight", "rx_drr_weight"}, 281a3c5bd6dSspeer 282846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 283846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 284a3c5bd6dSspeer 0, 1, 1, 0, "rx-full-header", "rx_full_header"}, 285a3c5bd6dSspeer 286846a903dSml { nxge_param_get_rxdma_info, NULL, NXGE_PARAM_READ | 287846a903dSml NXGE_PARAM_DONT_SHOW, 288a3c5bd6dSspeer 0, 32, 0, 0, "rx-dma-info", "rx_dma_info"}, 289a3c5bd6dSspeer 290a3c5bd6dSspeer { nxge_param_get_rxdma_info, NULL, 291a3c5bd6dSspeer NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 292a3c5bd6dSspeer NXGE_RBR_RBB_MIN, NXGE_RBR_RBB_MAX, NXGE_RBR_RBB_DEFAULT, 0, 293a3c5bd6dSspeer "rx-rbr-size", "rx_rbr_size"}, 294a3c5bd6dSspeer 295a3c5bd6dSspeer { nxge_param_get_rxdma_info, NULL, 296a3c5bd6dSspeer NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 297a3c5bd6dSspeer NXGE_RCR_MIN, NXGE_RCR_MAX, NXGE_RCR_DEFAULT, 0, 298a3c5bd6dSspeer "rx-rcr-size", "rx_rcr_size"}, 299a3c5bd6dSspeer 300846a903dSml { nxge_param_get_generic, nxge_param_set_port_rdc, 301846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 302a3c5bd6dSspeer 0, 15, 0, 0, "default-port-rdc", "default_port_rdc"}, 303a3c5bd6dSspeer 304a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_rx_intr_time, NXGE_PARAM_RXDMA_RW, 305a3c5bd6dSspeer NXGE_RDC_RCR_TIMEOUT_MIN, NXGE_RDC_RCR_TIMEOUT_MAX, 306a3c5bd6dSspeer RXDMA_RCR_TO_DEFAULT, 0, "rxdma-intr-time", "rxdma_intr_time"}, 307a3c5bd6dSspeer 308a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_rx_intr_pkts, NXGE_PARAM_RXDMA_RW, 309a3c5bd6dSspeer NXGE_RDC_RCR_THRESHOLD_MIN, NXGE_RDC_RCR_THRESHOLD_MAX, 310a3c5bd6dSspeer RXDMA_RCR_PTHRES_DEFAULT, 0, 311a3c5bd6dSspeer "rxdma-intr-pkts", "rxdma_intr_pkts"}, 312a3c5bd6dSspeer 313846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP | 314846a903dSml NXGE_PARAM_DONT_SHOW, 315a3c5bd6dSspeer 0, 8, 0, 0, "rx-rdc-grps-begin", "rx_rdc_grps_begin"}, 316a3c5bd6dSspeer 317846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP | 318846a903dSml NXGE_PARAM_DONT_SHOW, 319a3c5bd6dSspeer 0, 8, 0, 0, "rx-rdc-grps", "rx_rdc_grps"}, 320a3c5bd6dSspeer 321846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 322846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 323a3c5bd6dSspeer 0, 15, 0, 0, "default-grp0-rdc", "default_grp0_rdc"}, 324a3c5bd6dSspeer 325846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 326846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 327a3c5bd6dSspeer 0, 15, 2, 0, "default-grp1-rdc", "default_grp1_rdc"}, 328a3c5bd6dSspeer 329846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 330846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 331a3c5bd6dSspeer 0, 15, 4, 0, "default-grp2-rdc", "default_grp2_rdc"}, 332a3c5bd6dSspeer 333846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 334846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 335a3c5bd6dSspeer 0, 15, 6, 0, "default-grp3-rdc", "default_grp3_rdc"}, 336a3c5bd6dSspeer 337846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 338846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 339a3c5bd6dSspeer 0, 15, 8, 0, "default-grp4-rdc", "default_grp4_rdc"}, 340a3c5bd6dSspeer 341846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 342846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 343a3c5bd6dSspeer 0, 15, 10, 0, "default-grp5-rdc", "default_grp5_rdc"}, 344a3c5bd6dSspeer 345846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 346846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 347a3c5bd6dSspeer 0, 15, 12, 0, "default-grp6-rdc", "default_grp6_rdc"}, 348a3c5bd6dSspeer 349846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 350846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 351a3c5bd6dSspeer 0, 15, 14, 0, "default-grp7-rdc", "default_grp7_rdc"}, 352a3c5bd6dSspeer 353a3c5bd6dSspeer { nxge_param_get_rxdma_rdcgrp_info, NULL, 354846a903dSml NXGE_PARAM_READ | NXGE_PARAM_CMPLX | NXGE_PARAM_DONT_SHOW, 355a3c5bd6dSspeer 0, 8, 0, 0, "rdc-groups-info", "rdc_groups_info"}, 356a3c5bd6dSspeer 357a3c5bd6dSspeer /* Logical device groups */ 358846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 359a3c5bd6dSspeer 0, 63, 0, 0, "start-ldg", "start_ldg"}, 360a3c5bd6dSspeer 361846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 362a3c5bd6dSspeer 0, 64, 0, 0, "max-ldg", "max_ldg" }, 363a3c5bd6dSspeer 364a3c5bd6dSspeer /* MAC table information */ 365a3c5bd6dSspeer { nxge_param_get_mac_rdcgrp, nxge_param_set_mac_rdcgrp, 366846a903dSml NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW, 367a3c5bd6dSspeer 0, 31, 0, 0, "mac-2rdc-grp", "mac_2rdc_grp"}, 368a3c5bd6dSspeer 369a3c5bd6dSspeer /* VLAN table information */ 370a3c5bd6dSspeer { nxge_param_get_vlan_rdcgrp, nxge_param_set_vlan_rdcgrp, 371846a903dSml NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW, 372a3c5bd6dSspeer 0, 31, 0, 0, "vlan-2rdc-grp", "vlan_2rdc_grp"}, 373a3c5bd6dSspeer 374a3c5bd6dSspeer { nxge_param_get_generic, NULL, 375846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_READ | 376846a903dSml NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_DONT_SHOW, 377a3c5bd6dSspeer 0, 0x0ffff, 0x0ffff, 0, "fcram-part-cfg", "fcram_part_cfg"}, 378a3c5bd6dSspeer 379846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS | 380846a903dSml NXGE_PARAM_DONT_SHOW, 381a3c5bd6dSspeer 0, 0x10, 0xa, 0, "fcram-access-ratio", "fcram_access_ratio"}, 382a3c5bd6dSspeer 383846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS | 384846a903dSml NXGE_PARAM_DONT_SHOW, 385a3c5bd6dSspeer 0, 0x10, 0xa, 0, "tcam-access-ratio", "tcam_access_ratio"}, 386a3c5bd6dSspeer 387a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_tcam_enable, 388846a903dSml NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 389a3c5bd6dSspeer 0, 0x1, 0x0, 0, "tcam-enable", "tcam_enable"}, 390a3c5bd6dSspeer 391a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_hash_lookup_enable, 392846a903dSml NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 393a3c5bd6dSspeer 0, 0x01, 0x0, 0, "hash-lookup-enable", "hash_lookup_enable"}, 394a3c5bd6dSspeer 395a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_llc_snap_enable, 396846a903dSml NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 397a3c5bd6dSspeer 0, 0x01, 0x01, 0, "llc-snap-enable", "llc_snap_enable"}, 398a3c5bd6dSspeer 399a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_fflp_hash_init, 400846a903dSml NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 401a3c5bd6dSspeer 0, ALL_FF_32, ALL_FF_32, 0, "h1-init-value", "h1_init_value"}, 402a3c5bd6dSspeer 403a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_fflp_hash_init, 404846a903dSml NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 405a3c5bd6dSspeer 0, 0x0ffff, 0x0ffff, 0, "h2-init-value", "h2_init_value"}, 406a3c5bd6dSspeer 407a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ether_usr, 408a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 409a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 410a3c5bd6dSspeer "class-cfg-ether-usr1", "class_cfg_ether_usr1"}, 411a3c5bd6dSspeer 412a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ether_usr, 413a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 414a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 415a3c5bd6dSspeer "class-cfg-ether-usr2", "class_cfg_ether_usr2"}, 416a3c5bd6dSspeer 417a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ip_usr, 418a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 419a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 420a3c5bd6dSspeer "class-cfg-ip-usr4", "class_cfg_ip_usr4"}, 421a3c5bd6dSspeer 422a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ip_usr, 423a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 424a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 425a3c5bd6dSspeer "class-cfg-ip-usr5", "class_cfg_ip_usr5"}, 426a3c5bd6dSspeer 427a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ip_usr, 428a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 429a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 430a3c5bd6dSspeer "class-cfg-ip-usr6", "class_cfg_ip_usr6"}, 431a3c5bd6dSspeer 432a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ip_usr, 433a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 434a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 435a3c5bd6dSspeer "class-cfg-ip-usr7", "class_cfg_ip_usr7"}, 436a3c5bd6dSspeer 437a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 438a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 439a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 440a3c5bd6dSspeer "class-opt-ip-usr4", "class_opt_ip_usr4"}, 441a3c5bd6dSspeer 442a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 443a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 444a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 445a3c5bd6dSspeer "class-opt-ip-usr5", "class_opt_ip_usr5"}, 446a3c5bd6dSspeer 447a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 448a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 449a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 450a3c5bd6dSspeer "class-opt-ip-usr6", "class_opt_ip_usr6"}, 451a3c5bd6dSspeer 452a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 453a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 454a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 455a3c5bd6dSspeer "class-opt-ip-usr7", "class_opt_ip_usr7"}, 456a3c5bd6dSspeer 457a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 458a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS, 459a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 460a3c5bd6dSspeer "class-opt-ipv4-tcp", "class_opt_ipv4_tcp"}, 461a3c5bd6dSspeer 462a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 463a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS, 464a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 465a3c5bd6dSspeer "class-opt-ipv4-udp", "class_opt_ipv4_udp"}, 466a3c5bd6dSspeer 467a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 468a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS, 469a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 470a3c5bd6dSspeer "class-opt-ipv4-ah", "class_opt_ipv4_ah"}, 471a3c5bd6dSspeer 472a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 473a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS, 474a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 475a3c5bd6dSspeer "class-opt-ipv4-sctp", "class_opt_ipv4_sctp"}, 476a3c5bd6dSspeer 477a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 478a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 479a3c5bd6dSspeer "class-opt-ipv6-tcp", "class_opt_ipv6_tcp"}, 480a3c5bd6dSspeer 481a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 482a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 483a3c5bd6dSspeer "class-opt-ipv6-udp", "class_opt_ipv6_udp"}, 484a3c5bd6dSspeer 485a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 486a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 487a3c5bd6dSspeer "class-opt-ipv6-ah", "class_opt_ipv6_ah"}, 488a3c5bd6dSspeer 489a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 490a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 491a3c5bd6dSspeer "class-opt-ipv6-sctp", "class_opt_ipv6_sctp"}, 492a3c5bd6dSspeer 493a3c5bd6dSspeer { nxge_param_get_debug_flag, nxge_param_set_nxge_debug_flag, 494846a903dSml NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 495a3c5bd6dSspeer 0ULL, ALL_FF_64, 0ULL, 0ULL, 496a3c5bd6dSspeer "nxge-debug-flag", "nxge_debug_flag"}, 497a3c5bd6dSspeer 498a3c5bd6dSspeer { nxge_param_get_debug_flag, nxge_param_set_npi_debug_flag, 499846a903dSml NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 500a3c5bd6dSspeer 0ULL, ALL_FF_64, 0ULL, 0ULL, 501a3c5bd6dSspeer "npi-debug-flag", "npi_debug_flag"}, 502a3c5bd6dSspeer 503846a903dSml { nxge_param_dump_tdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 504a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "dump-tdc", "dump_tdc"}, 505a3c5bd6dSspeer 506846a903dSml { nxge_param_dump_rdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 507a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "dump-rdc", "dump_rdc"}, 508a3c5bd6dSspeer 509846a903dSml { nxge_param_dump_mac_regs, NULL, NXGE_PARAM_READ | 510846a903dSml NXGE_PARAM_DONT_SHOW, 511a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "dump-mac-regs", "dump_mac_regs"}, 512a3c5bd6dSspeer 513846a903dSml { nxge_param_dump_ipp_regs, NULL, NXGE_PARAM_READ | 514846a903dSml NXGE_PARAM_DONT_SHOW, 515a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "dump-ipp-regs", "dump_ipp_regs"}, 516a3c5bd6dSspeer 517846a903dSml { nxge_param_dump_fflp_regs, NULL, NXGE_PARAM_READ | 518846a903dSml NXGE_PARAM_DONT_SHOW, 519a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, 520a3c5bd6dSspeer "dump-fflp-regs", "dump_fflp_regs"}, 521a3c5bd6dSspeer 522846a903dSml { nxge_param_dump_vlan_table, NULL, NXGE_PARAM_READ | 523846a903dSml NXGE_PARAM_DONT_SHOW, 524a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, 525a3c5bd6dSspeer "dump-vlan-table", "dump_vlan_table"}, 526a3c5bd6dSspeer 527846a903dSml { nxge_param_dump_rdc_table, NULL, NXGE_PARAM_READ | 528846a903dSml NXGE_PARAM_DONT_SHOW, 529a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, 530a3c5bd6dSspeer "dump-rdc-table", "dump_rdc_table"}, 531a3c5bd6dSspeer 532846a903dSml { nxge_param_dump_ptrs, NULL, NXGE_PARAM_READ | 533846a903dSml NXGE_PARAM_DONT_SHOW, 534a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "dump-ptrs", "dump_ptrs"}, 535a3c5bd6dSspeer 536a3c5bd6dSspeer { NULL, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 537a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "end", "end"}, 53844961713Sgirish }; 53944961713Sgirish 54044961713Sgirish extern void *nxge_list; 54144961713Sgirish 54244961713Sgirish void 54344961713Sgirish nxge_get_param_soft_properties(p_nxge_t nxgep) 54444961713Sgirish { 54544961713Sgirish 54644961713Sgirish p_nxge_param_t param_arr; 54744961713Sgirish uint_t prop_len; 54844961713Sgirish int i, j; 549a3c5bd6dSspeer uint32_t param_count; 550a3c5bd6dSspeer uint32_t *int_prop_val; 55144961713Sgirish 55244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, " ==> nxge_get_param_soft_properties")); 55344961713Sgirish 55444961713Sgirish param_arr = nxgep->param_arr; 55544961713Sgirish param_count = nxgep->param_count; 55644961713Sgirish for (i = 0; i < param_count; i++) { 55744961713Sgirish if ((param_arr[i].type & NXGE_PARAM_READ_PROP) == 0) 55844961713Sgirish continue; 55944961713Sgirish if ((param_arr[i].type & NXGE_PARAM_PROP_STR)) 56044961713Sgirish continue; 56144961713Sgirish if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 562a3c5bd6dSspeer (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 56344961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, 564a3c5bd6dSspeer nxgep->dip, 0, param_arr[i].fcode_name, 565a3c5bd6dSspeer (int **)&int_prop_val, 566a3c5bd6dSspeer (uint_t *)&prop_len) 567a3c5bd6dSspeer == DDI_PROP_SUCCESS) { 56844961713Sgirish uint32_t *cfg_value; 56944961713Sgirish uint64_t prop_count; 570a3c5bd6dSspeer 57144961713Sgirish if (prop_len > NXGE_PARAM_ARRAY_INIT_SIZE) 57244961713Sgirish prop_len = NXGE_PARAM_ARRAY_INIT_SIZE; 57344961713Sgirish cfg_value = (uint32_t *)param_arr[i].value; 57444961713Sgirish for (j = 0; j < prop_len; j++) { 57544961713Sgirish cfg_value[j] = int_prop_val[j]; 57644961713Sgirish } 57744961713Sgirish prop_count = prop_len; 57844961713Sgirish param_arr[i].type |= 57944961713Sgirish (prop_count << NXGE_PARAM_ARRAY_CNT_SHIFT); 58044961713Sgirish ddi_prop_free(int_prop_val); 58144961713Sgirish } 58244961713Sgirish continue; 58344961713Sgirish } 58444961713Sgirish 58544961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 586a3c5bd6dSspeer param_arr[i].fcode_name, 587a3c5bd6dSspeer (int **)&int_prop_val, 588a3c5bd6dSspeer &prop_len) == DDI_PROP_SUCCESS) { 58944961713Sgirish if ((*int_prop_val >= param_arr[i].minimum) && 590a3c5bd6dSspeer (*int_prop_val <= param_arr[i].maximum)) 59144961713Sgirish param_arr[i].value = *int_prop_val; 59244961713Sgirish #ifdef NXGE_DEBUG_ERROR 59344961713Sgirish else { 59444961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL, 595a3c5bd6dSspeer "nxge%d: 'prom' file parameter error\n", 596a3c5bd6dSspeer nxgep->instance)); 59744961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL, 598a3c5bd6dSspeer "Parameter keyword '%s'" 599a3c5bd6dSspeer " is outside valid range\n", 600a3c5bd6dSspeer param_arr[i].name)); 60144961713Sgirish } 60244961713Sgirish #endif 60344961713Sgirish ddi_prop_free(int_prop_val); 60444961713Sgirish } 60544961713Sgirish 60644961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 607a3c5bd6dSspeer param_arr[i].name, 608a3c5bd6dSspeer (int **)&int_prop_val, 609a3c5bd6dSspeer &prop_len) == DDI_PROP_SUCCESS) { 61044961713Sgirish if ((*int_prop_val >= param_arr[i].minimum) && 61144961713Sgirish (*int_prop_val <= param_arr[i].maximum)) 61244961713Sgirish param_arr[i].value = *int_prop_val; 61344961713Sgirish #ifdef NXGE_DEBUG_ERROR 61444961713Sgirish else { 61544961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL, 616a3c5bd6dSspeer "nxge%d: 'conf' file parameter error\n", 617a3c5bd6dSspeer nxgep->instance)); 61844961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL, 619a3c5bd6dSspeer "Parameter keyword '%s'" 620a3c5bd6dSspeer "is outside valid range\n", 621a3c5bd6dSspeer param_arr[i].name)); 62244961713Sgirish } 62344961713Sgirish #endif 62444961713Sgirish ddi_prop_free(int_prop_val); 62544961713Sgirish } 62644961713Sgirish } 62744961713Sgirish } 62844961713Sgirish 62944961713Sgirish static int 63044961713Sgirish nxge_private_param_register(p_nxge_t nxgep, p_nxge_param_t param_arr) 63144961713Sgirish { 63244961713Sgirish int status = B_TRUE; 63344961713Sgirish int channel; 63444961713Sgirish uint8_t grp; 63544961713Sgirish char *prop_name; 63644961713Sgirish char *end; 63744961713Sgirish uint32_t name_chars; 63844961713Sgirish 63944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 640a3c5bd6dSspeer "nxge_private_param_register %s", param_arr->name)); 64144961713Sgirish 64244961713Sgirish if ((param_arr->type & NXGE_PARAM_PRIV) != NXGE_PARAM_PRIV) 64344961713Sgirish return (B_TRUE); 644a3c5bd6dSspeer 64544961713Sgirish prop_name = param_arr->name; 64644961713Sgirish if (param_arr->type & NXGE_PARAM_RXDMA) { 64744961713Sgirish if (strncmp("rxdma_intr", prop_name, 10) == 0) 64844961713Sgirish return (B_TRUE); 64944961713Sgirish name_chars = strlen("default_grp"); 65044961713Sgirish if (strncmp("default_grp", prop_name, name_chars) == 0) { 65144961713Sgirish prop_name += name_chars; 65244961713Sgirish grp = mi_strtol(prop_name, &end, 10); 65344961713Sgirish /* now check if this rdcgrp is in config */ 65444961713Sgirish return (nxge_check_rdcgrp_port_member(nxgep, grp)); 65544961713Sgirish } 65644961713Sgirish name_chars = strlen(prop_name); 65744961713Sgirish if (strncmp("default_port_rdc", prop_name, name_chars) == 0) { 65844961713Sgirish return (B_TRUE); 65944961713Sgirish } 66044961713Sgirish return (B_FALSE); 66144961713Sgirish } 66244961713Sgirish 66344961713Sgirish if (param_arr->type & NXGE_PARAM_TXDMA) { 66444961713Sgirish name_chars = strlen("txdma"); 66544961713Sgirish if (strncmp("txdma", prop_name, name_chars) == 0) { 66644961713Sgirish prop_name += name_chars; 66744961713Sgirish channel = mi_strtol(prop_name, &end, 10); 66844961713Sgirish /* now check if this rdc is in config */ 66944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 67044961713Sgirish " nxge_private_param_register: %d", 67144961713Sgirish channel)); 67244961713Sgirish return (nxge_check_txdma_port_member(nxgep, channel)); 67344961713Sgirish } 67444961713Sgirish return (B_FALSE); 67544961713Sgirish } 67644961713Sgirish 67744961713Sgirish status = B_FALSE; 67844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD2_CTL, "<== nxge_private_param_register")); 67944961713Sgirish 68044961713Sgirish return (status); 68144961713Sgirish } 68244961713Sgirish 68344961713Sgirish void 68444961713Sgirish nxge_setup_param(p_nxge_t nxgep) 68544961713Sgirish { 68644961713Sgirish p_nxge_param_t param_arr; 68744961713Sgirish int i; 68844961713Sgirish pfi_t set_pfi; 68944961713Sgirish 69044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_setup_param")); 691a3c5bd6dSspeer 69244961713Sgirish /* 69344961713Sgirish * Make sure the param_instance is set to a valid device instance. 69444961713Sgirish */ 69544961713Sgirish if (nxge_param_arr[param_instance].value == 1000) 69644961713Sgirish nxge_param_arr[param_instance].value = nxgep->instance; 69744961713Sgirish 69844961713Sgirish param_arr = nxgep->param_arr; 69944961713Sgirish param_arr[param_instance].value = nxgep->instance; 70044961713Sgirish param_arr[param_function_number].value = nxgep->function_num; 70144961713Sgirish 70244961713Sgirish for (i = 0; i < nxgep->param_count; i++) { 70344961713Sgirish if ((param_arr[i].type & NXGE_PARAM_PRIV) && 704a3c5bd6dSspeer (nxge_private_param_register(nxgep, 705a3c5bd6dSspeer ¶m_arr[i]) == B_FALSE)) { 70644961713Sgirish param_arr[i].setf = NULL; 70744961713Sgirish param_arr[i].getf = NULL; 70844961713Sgirish } 70944961713Sgirish 71044961713Sgirish if (param_arr[i].type & NXGE_PARAM_CMPLX) 71144961713Sgirish param_arr[i].setf = NULL; 71244961713Sgirish 71344961713Sgirish if (param_arr[i].type & NXGE_PARAM_DONT_SHOW) { 71444961713Sgirish param_arr[i].setf = NULL; 71544961713Sgirish param_arr[i].getf = NULL; 71644961713Sgirish } 71744961713Sgirish 71844961713Sgirish set_pfi = (pfi_t)param_arr[i].setf; 71944961713Sgirish 720a3c5bd6dSspeer if ((set_pfi) && (param_arr[i].type & NXGE_PARAM_INIT_ONLY)) { 72144961713Sgirish set_pfi = NULL; 72244961713Sgirish } 72344961713Sgirish 724a3c5bd6dSspeer if (!nxge_nd_load(&nxgep->param_list, param_arr[i].name, 725a3c5bd6dSspeer (pfi_t)param_arr[i].getf, set_pfi, 72644961713Sgirish (caddr_t)¶m_arr[i])) { 72744961713Sgirish (void) nxge_nd_free(&nxgep->param_list); 72844961713Sgirish break; 72944961713Sgirish } 73044961713Sgirish } 73144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_setup_param")); 73244961713Sgirish } 73344961713Sgirish 73444961713Sgirish void 73544961713Sgirish nxge_init_param(p_nxge_t nxgep) 73644961713Sgirish { 73744961713Sgirish p_nxge_param_t param_arr; 73844961713Sgirish int i, alloc_size; 73944961713Sgirish uint64_t alloc_count; 74044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_init_param")); 74144961713Sgirish /* 74244961713Sgirish * Make sure the param_instance is set to a valid device instance. 74344961713Sgirish */ 74444961713Sgirish if (nxge_param_arr[param_instance].value == 1000) 74544961713Sgirish nxge_param_arr[param_instance].value = nxgep->instance; 74644961713Sgirish 74744961713Sgirish param_arr = nxgep->param_arr; 74844961713Sgirish if (param_arr == NULL) { 749a3c5bd6dSspeer param_arr = (p_nxge_param_t) 750a3c5bd6dSspeer KMEM_ZALLOC(sizeof (nxge_param_arr), KM_SLEEP); 75144961713Sgirish } 752a3c5bd6dSspeer 75344961713Sgirish for (i = 0; i < sizeof (nxge_param_arr)/sizeof (nxge_param_t); i++) { 75444961713Sgirish param_arr[i] = nxge_param_arr[i]; 75544961713Sgirish if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 75644961713Sgirish (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 75744961713Sgirish alloc_count = NXGE_PARAM_ARRAY_INIT_SIZE; 75844961713Sgirish alloc_size = alloc_count * sizeof (uint64_t); 75944961713Sgirish param_arr[i].value = 76044961713Sgirish (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP); 76144961713Sgirish param_arr[i].old_value = 76244961713Sgirish (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP); 76344961713Sgirish param_arr[i].type |= 76444961713Sgirish (alloc_count << NXGE_PARAM_ARRAY_ALLOC_SHIFT); 76544961713Sgirish } 76644961713Sgirish } 76744961713Sgirish 76844961713Sgirish nxgep->param_arr = param_arr; 76944961713Sgirish nxgep->param_count = sizeof (nxge_param_arr)/sizeof (nxge_param_t); 77044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_init_param: count %d", 771a3c5bd6dSspeer nxgep->param_count)); 77244961713Sgirish } 77344961713Sgirish 77444961713Sgirish void 77544961713Sgirish nxge_destroy_param(p_nxge_t nxgep) 77644961713Sgirish { 77744961713Sgirish int i; 77844961713Sgirish uint64_t free_size, free_count; 77944961713Sgirish 78044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_param")); 781a3c5bd6dSspeer 782*59ac0c16Sdavemq if (nxgep->param_arr == NULL) 783*59ac0c16Sdavemq return; 78444961713Sgirish /* 78544961713Sgirish * Make sure the param_instance is set to a valid device instance. 78644961713Sgirish */ 78744961713Sgirish if (nxge_param_arr[param_instance].value == nxgep->instance) { 78844961713Sgirish for (i = 0; i <= nxge_param_arr[param_instance].maximum; i++) { 78944961713Sgirish if ((ddi_get_soft_state(nxge_list, i) != NULL) && 79044961713Sgirish (i != nxgep->instance)) 79144961713Sgirish break; 79244961713Sgirish } 79344961713Sgirish nxge_param_arr[param_instance].value = i; 79444961713Sgirish } 79544961713Sgirish 79644961713Sgirish if (nxgep->param_list) 79744961713Sgirish nxge_nd_free(&nxgep->param_list); 79844961713Sgirish for (i = 0; i < nxgep->param_count; i++) 79944961713Sgirish if ((nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 80044961713Sgirish (nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 80144961713Sgirish free_count = ((nxgep->param_arr[i].type & 80244961713Sgirish NXGE_PARAM_ARRAY_ALLOC_MASK) >> 80344961713Sgirish NXGE_PARAM_ARRAY_ALLOC_SHIFT); 80444961713Sgirish free_count = NXGE_PARAM_ARRAY_INIT_SIZE; 80544961713Sgirish free_size = sizeof (uint64_t) * free_count; 80644961713Sgirish KMEM_FREE((void *)nxgep->param_arr[i].value, free_size); 80744961713Sgirish KMEM_FREE((void *)nxgep->param_arr[i].old_value, 808a3c5bd6dSspeer free_size); 80944961713Sgirish } 81044961713Sgirish 81144961713Sgirish KMEM_FREE(nxgep->param_arr, sizeof (nxge_param_arr)); 81244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_param")); 81344961713Sgirish } 81444961713Sgirish 81544961713Sgirish /* 81644961713Sgirish * Extracts the value from the 'nxge' parameter array and prints the 81744961713Sgirish * parameter value. cp points to the required parameter. 81844961713Sgirish */ 819a3c5bd6dSspeer 82044961713Sgirish /* ARGSUSED */ 82144961713Sgirish int 82244961713Sgirish nxge_param_get_generic(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 82344961713Sgirish { 82444961713Sgirish p_nxge_param_t pa = (p_nxge_param_t)cp; 82544961713Sgirish 826a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, NDD_CTL, 827a3c5bd6dSspeer "==> nxge_param_get_generic name %s ", pa->name)); 82844961713Sgirish 82944961713Sgirish if (pa->value > 0xffffffff) 830a3c5bd6dSspeer (void) mi_mpprintf(mp, "%x%x", 831a3c5bd6dSspeer (int)(pa->value >> 32), (int)(pa->value & 0xffffffff)); 83244961713Sgirish else 83344961713Sgirish (void) mi_mpprintf(mp, "%x", (int)pa->value); 83444961713Sgirish 83544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_generic")); 83644961713Sgirish return (0); 83744961713Sgirish } 83844961713Sgirish 83944961713Sgirish /* ARGSUSED */ 84044961713Sgirish static int 84144961713Sgirish nxge_param_get_mac(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 84244961713Sgirish { 84344961713Sgirish p_nxge_param_t pa = (p_nxge_param_t)cp; 84444961713Sgirish 84544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac")); 84644961713Sgirish 84744961713Sgirish (void) mi_mpprintf(mp, "%d", (uint32_t)pa->value); 84844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_mac")); 84944961713Sgirish return (0); 85044961713Sgirish } 85144961713Sgirish 85256d930aeSspeer /* ARGSUSED */ 85356d930aeSspeer static int 85456d930aeSspeer nxge_param_get_fw_ver(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 85556d930aeSspeer { 85656d930aeSspeer NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_fw_ver")); 85756d930aeSspeer 85856d930aeSspeer (void) mi_mpprintf(mp, "Firmware version for nxge%d: %s\n", 85956d930aeSspeer nxgep->instance, nxgep->vpd_info.ver); 86056d930aeSspeer 86156d930aeSspeer NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_fw_ver")); 86256d930aeSspeer return (0); 86356d930aeSspeer } 86456d930aeSspeer 86544961713Sgirish /* ARGSUSED */ 86644961713Sgirish int 86744961713Sgirish nxge_param_get_txdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 86844961713Sgirish { 86944961713Sgirish 87044961713Sgirish uint_t print_len, buf_len; 87144961713Sgirish p_mblk_t np; 87244961713Sgirish int tdc; 87344961713Sgirish 87444961713Sgirish int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 87544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_txdma_info")); 87644961713Sgirish 877a3c5bd6dSspeer (void) mi_mpprintf(mp, "TXDMA Information for Port\t %d \n", 878a3c5bd6dSspeer nxgep->function_num); 87944961713Sgirish 88044961713Sgirish 88144961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 88244961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 88344961713Sgirish return (0); 88444961713Sgirish } 88544961713Sgirish 88644961713Sgirish buf_len = buff_alloc_size; 88744961713Sgirish mp->b_cont = np; 88844961713Sgirish 88944961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 890a3c5bd6dSspeer "Total TDCs\t %d\n", nxgep->ntdc); 89144961713Sgirish 89244961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 89344961713Sgirish buf_len -= print_len; 89444961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 895a3c5bd6dSspeer "TDC\t HW TDC\t\n"); 89644961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 897a3c5bd6dSspeer 89844961713Sgirish buf_len -= print_len; 89944961713Sgirish for (tdc = 0; tdc < nxgep->ntdc; tdc++) { 90044961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 90144961713Sgirish buf_len, "%d\t %d\n", 90244961713Sgirish tdc, nxgep->tdc[tdc]); 90344961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 90444961713Sgirish buf_len -= print_len; 90544961713Sgirish } 906a3c5bd6dSspeer 90744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_txdma_info")); 90844961713Sgirish return (0); 90944961713Sgirish } 91044961713Sgirish 91144961713Sgirish /* ARGSUSED */ 91244961713Sgirish int 91344961713Sgirish nxge_param_get_rxdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 91444961713Sgirish { 915a3c5bd6dSspeer uint_t print_len, buf_len; 916a3c5bd6dSspeer p_mblk_t np; 917a3c5bd6dSspeer int rdc; 91844961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 91944961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 920a3c5bd6dSspeer int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 92144961713Sgirish p_rx_rcr_rings_t rx_rcr_rings; 92244961713Sgirish p_rx_rcr_ring_t *rcr_rings; 92344961713Sgirish p_rx_rbr_rings_t rx_rbr_rings; 92444961713Sgirish p_rx_rbr_ring_t *rbr_rings; 92544961713Sgirish 92644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rxdma_info")); 92744961713Sgirish 928a3c5bd6dSspeer (void) mi_mpprintf(mp, "RXDMA Information for Port\t %d \n", 929a3c5bd6dSspeer nxgep->function_num); 93044961713Sgirish 93144961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 93244961713Sgirish /* The following may work even if we cannot get a large buf. */ 93344961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 93444961713Sgirish return (0); 93544961713Sgirish } 93644961713Sgirish 93744961713Sgirish buf_len = buff_alloc_size; 93844961713Sgirish mp->b_cont = np; 93944961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 94044961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 94144961713Sgirish 94244961713Sgirish rx_rcr_rings = nxgep->rx_rcr_rings; 94344961713Sgirish rcr_rings = rx_rcr_rings->rcr_rings; 94444961713Sgirish rx_rbr_rings = nxgep->rx_rbr_rings; 94544961713Sgirish rbr_rings = rx_rbr_rings->rbr_rings; 94644961713Sgirish 94744961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 948a3c5bd6dSspeer "Total RDCs\t %d\n", p_cfgp->max_rdcs); 94944961713Sgirish 95044961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 95144961713Sgirish buf_len -= print_len; 95244961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 953a3c5bd6dSspeer "RDC\t HW RDC\t Timeout\t Packets RBR ptr \t" 954a3c5bd6dSspeer "chunks\t RCR ptr\n"); 955a3c5bd6dSspeer 95644961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 95744961713Sgirish buf_len -= print_len; 95844961713Sgirish for (rdc = 0; rdc < p_cfgp->max_rdcs; rdc++) { 95944961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 960a3c5bd6dSspeer " %d\t %d\t %x\t\t %x\t $%p\t 0x%x\t $%p\n", 961a3c5bd6dSspeer rdc, nxgep->rdc[rdc], 962a3c5bd6dSspeer p_dma_cfgp->rcr_timeout[rdc], 963a3c5bd6dSspeer p_dma_cfgp->rcr_threshold[rdc], 964a3c5bd6dSspeer rbr_rings[rdc], 965a3c5bd6dSspeer rbr_rings[rdc]->num_blocks, rcr_rings[rdc]); 966a3c5bd6dSspeer ((mblk_t *)np)->b_wptr += print_len; 967a3c5bd6dSspeer buf_len -= print_len; 96844961713Sgirish } 969a3c5bd6dSspeer 97044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rxdma_info")); 97144961713Sgirish return (0); 97244961713Sgirish } 97344961713Sgirish 97444961713Sgirish /* ARGSUSED */ 97544961713Sgirish int 97644961713Sgirish nxge_param_get_rxdma_rdcgrp_info(p_nxge_t nxgep, queue_t *q, 977a3c5bd6dSspeer p_mblk_t mp, caddr_t cp) 97844961713Sgirish { 979a3c5bd6dSspeer uint_t print_len, buf_len; 980a3c5bd6dSspeer p_mblk_t np; 981a3c5bd6dSspeer int offset, rdc, i, rdc_grp; 98244961713Sgirish p_nxge_rdc_grp_t rdc_grp_p; 98344961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 98444961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 98544961713Sgirish 98644961713Sgirish int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 98744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 988a3c5bd6dSspeer "==> nxge_param_get_rxdma_rdcgrp_info")); 98944961713Sgirish 99044961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 99144961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 99244961713Sgirish 993a3c5bd6dSspeer (void) mi_mpprintf(mp, "RXDMA RDC Group Information for Port\t %d \n", 994a3c5bd6dSspeer nxgep->function_num); 99544961713Sgirish 99644961713Sgirish rdc_grp = p_cfgp->start_rdc_grpid; 99744961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 99844961713Sgirish /* The following may work even if we cannot get a large buf. */ 99944961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 100044961713Sgirish return (0); 100144961713Sgirish } 100244961713Sgirish 100344961713Sgirish buf_len = buff_alloc_size; 100444961713Sgirish mp->b_cont = np; 100544961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1006a3c5bd6dSspeer "Total RDC Groups\t %d \n" 1007a3c5bd6dSspeer "start RDC group\t %d\n", 1008a3c5bd6dSspeer p_cfgp->max_rdc_grpids, 1009a3c5bd6dSspeer p_cfgp->start_rdc_grpid); 101044961713Sgirish 101144961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 101244961713Sgirish buf_len -= print_len; 101344961713Sgirish 101444961713Sgirish for (i = 0, rdc_grp = p_cfgp->start_rdc_grpid; 101544961713Sgirish rdc_grp < (p_cfgp->max_rdc_grpids + p_cfgp->start_rdc_grpid); 101644961713Sgirish rdc_grp++, i++) { 101744961713Sgirish rdc_grp_p = &p_dma_cfgp->rdc_grps[i]; 101844961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1019a3c5bd6dSspeer "\nRDC Group Info for Group [%d] %d\n" 1020a3c5bd6dSspeer "RDC Count %d\tstart RDC %d\n" 1021a3c5bd6dSspeer "RDC Group Population Information" 1022a3c5bd6dSspeer " (offsets 0 - 15)\n", 1023a3c5bd6dSspeer i, rdc_grp, rdc_grp_p->max_rdcs, 1024a3c5bd6dSspeer rdc_grp_p->start_rdc); 102544961713Sgirish 102644961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 102744961713Sgirish buf_len -= print_len; 102844961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1029a3c5bd6dSspeer buf_len, "\n"); 103044961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 103144961713Sgirish buf_len -= print_len; 103244961713Sgirish 103344961713Sgirish for (rdc = 0; rdc < rdc_grp_p->max_rdcs; rdc++) { 103444961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1035a3c5bd6dSspeer buf_len, "[%d]=%d ", rdc, 1036a3c5bd6dSspeer rdc_grp_p->start_rdc + rdc); 103744961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 103844961713Sgirish buf_len -= print_len; 103944961713Sgirish } 104044961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 104144961713Sgirish buf_len, "\n"); 104244961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 104344961713Sgirish buf_len -= print_len; 104444961713Sgirish 104544961713Sgirish for (offset = 0; offset < 16; offset++) { 104644961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1047a3c5bd6dSspeer buf_len, " %2d ", 1048a3c5bd6dSspeer rdc_grp_p->rdc[offset]); 104944961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 105044961713Sgirish buf_len -= print_len; 105144961713Sgirish } 105244961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1053a3c5bd6dSspeer buf_len, "\n"); 105444961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 105544961713Sgirish buf_len -= print_len; 105644961713Sgirish } 105744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1058a3c5bd6dSspeer "<== nxge_param_get_rxdma_rdcgrp_info")); 105944961713Sgirish return (0); 106044961713Sgirish } 106144961713Sgirish 106244961713Sgirish int 106344961713Sgirish nxge_mk_mblk_tail_space(p_mblk_t mp, p_mblk_t *nmp, size_t size) 106444961713Sgirish { 106544961713Sgirish p_mblk_t tmp; 106644961713Sgirish 106744961713Sgirish tmp = mp; 106844961713Sgirish while (tmp->b_cont) 106944961713Sgirish tmp = tmp->b_cont; 107044961713Sgirish if ((tmp->b_wptr + size) >= tmp->b_datap->db_lim) { 107144961713Sgirish tmp->b_cont = allocb(1024, BPRI_HI); 107244961713Sgirish tmp = tmp->b_cont; 107344961713Sgirish if (!tmp) 107444961713Sgirish return (ENOMEM); 107544961713Sgirish } 1076a3c5bd6dSspeer 107744961713Sgirish *nmp = tmp; 107844961713Sgirish return (0); 107944961713Sgirish } 108044961713Sgirish 108144961713Sgirish /* 108244961713Sgirish * Sets the ge parameter to the value in the nxge_param_register using 108344961713Sgirish * nxge_nd_load(). 108444961713Sgirish */ 1085a3c5bd6dSspeer 108644961713Sgirish /* ARGSUSED */ 108744961713Sgirish int 108844961713Sgirish nxge_param_set_generic(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 108944961713Sgirish char *value, caddr_t cp) 109044961713Sgirish { 109144961713Sgirish char *end; 109244961713Sgirish uint32_t new_value; 109344961713Sgirish p_nxge_param_t pa = (p_nxge_param_t)cp; 109444961713Sgirish 109544961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, " ==> nxge_param_set_generic")); 109644961713Sgirish new_value = (uint32_t)mi_strtol(value, &end, 10); 109744961713Sgirish if (end == value || new_value < pa->minimum || 109844961713Sgirish new_value > pa->maximum) { 109944961713Sgirish return (EINVAL); 110044961713Sgirish } 110144961713Sgirish pa->value = new_value; 110244961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, " <== nxge_param_set_generic")); 110344961713Sgirish return (0); 110444961713Sgirish } 110544961713Sgirish 110644961713Sgirish /* 110744961713Sgirish * Sets the ge parameter to the value in the nxge_param_register using 110844961713Sgirish * nxge_nd_load(). 110944961713Sgirish */ 111044961713Sgirish 1111a3c5bd6dSspeer /* ARGSUSED */ 111244961713Sgirish int 1113a3c5bd6dSspeer nxge_param_set_instance(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1114a3c5bd6dSspeer char *value, caddr_t cp) 111544961713Sgirish { 111644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " ==> nxge_param_set_instance")); 111744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_set_instance")); 111844961713Sgirish return (0); 111944961713Sgirish } 112044961713Sgirish 112144961713Sgirish /* 112244961713Sgirish * Sets the ge parameter to the value in the nxge_param_register using 112344961713Sgirish * nxge_nd_load(). 112444961713Sgirish */ 112544961713Sgirish 1126a3c5bd6dSspeer /* ARGSUSED */ 112744961713Sgirish int 1128a3c5bd6dSspeer nxge_param_set_mac(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1129a3c5bd6dSspeer char *value, caddr_t cp) 113044961713Sgirish { 1131a3c5bd6dSspeer char *end; 1132a3c5bd6dSspeer uint32_t new_value; 1133a3c5bd6dSspeer int status = 0; 1134a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 113544961713Sgirish 113644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac")); 113744961713Sgirish new_value = (uint32_t)mi_strtol(value, &end, BASE_DECIMAL); 113844961713Sgirish if (PARAM_OUTOF_RANGE(value, end, new_value, pa)) { 113944961713Sgirish return (EINVAL); 114044961713Sgirish } 114144961713Sgirish 114244961713Sgirish if (pa->value != new_value) { 114344961713Sgirish pa->old_value = pa->value; 114444961713Sgirish pa->value = new_value; 114544961713Sgirish } 114644961713Sgirish 114744961713Sgirish if (!nxge_param_link_update(nxgep)) { 114844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 114944961713Sgirish " false ret from nxge_param_link_update")); 115044961713Sgirish status = EINVAL; 115144961713Sgirish } 115244961713Sgirish 115344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac")); 115444961713Sgirish return (status); 115544961713Sgirish } 115644961713Sgirish 115744961713Sgirish /* ARGSUSED */ 115844961713Sgirish static int 1159a3c5bd6dSspeer nxge_param_rx_intr_pkts(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1160a3c5bd6dSspeer char *value, caddr_t cp) 116144961713Sgirish { 1162a3c5bd6dSspeer char *end; 1163a3c5bd6dSspeer uint32_t cfg_value; 1164a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 116514ea4bb7Ssd 116644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_pkts")); 116744961713Sgirish 116814ea4bb7Ssd cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 116944961713Sgirish 117014ea4bb7Ssd if ((cfg_value > NXGE_RDC_RCR_THRESHOLD_MAX) || 117114ea4bb7Ssd (cfg_value < NXGE_RDC_RCR_THRESHOLD_MIN)) { 117244961713Sgirish return (EINVAL); 117344961713Sgirish } 117414ea4bb7Ssd 117514ea4bb7Ssd if ((pa->value != cfg_value)) { 117614ea4bb7Ssd pa->old_value = pa->value; 117714ea4bb7Ssd pa->value = cfg_value; 117814ea4bb7Ssd nxgep->intr_threshold = pa->value; 117944961713Sgirish } 118014ea4bb7Ssd 118144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_pkts")); 118244961713Sgirish return (0); 118344961713Sgirish } 118444961713Sgirish 118544961713Sgirish /* ARGSUSED */ 118644961713Sgirish static int 1187a3c5bd6dSspeer nxge_param_rx_intr_time(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1188a3c5bd6dSspeer char *value, caddr_t cp) 118944961713Sgirish { 1190a3c5bd6dSspeer char *end; 1191a3c5bd6dSspeer uint32_t cfg_value; 1192a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 119344961713Sgirish 119444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_time")); 119544961713Sgirish 119614ea4bb7Ssd cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 119744961713Sgirish 119814ea4bb7Ssd if ((cfg_value > NXGE_RDC_RCR_TIMEOUT_MAX) || 119914ea4bb7Ssd (cfg_value < NXGE_RDC_RCR_TIMEOUT_MIN)) { 120044961713Sgirish return (EINVAL); 120144961713Sgirish } 120244961713Sgirish 120314ea4bb7Ssd if ((pa->value != cfg_value)) { 120414ea4bb7Ssd pa->old_value = pa->value; 120514ea4bb7Ssd pa->value = cfg_value; 120614ea4bb7Ssd nxgep->intr_timeout = pa->value; 120744961713Sgirish } 120844961713Sgirish 120944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_time")); 121044961713Sgirish return (0); 121144961713Sgirish } 121244961713Sgirish 121344961713Sgirish /* ARGSUSED */ 121444961713Sgirish static int 121544961713Sgirish nxge_param_set_mac_rdcgrp(p_nxge_t nxgep, queue_t *q, 1216a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 121744961713Sgirish { 1218a3c5bd6dSspeer char *end; 1219a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1220a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1221a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 122244961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 122344961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 1224a3c5bd6dSspeer uint32_t *val_ptr, *old_val_ptr; 1225a3c5bd6dSspeer nxge_param_map_t *mac_map; 1226a3c5bd6dSspeer p_nxge_class_pt_cfg_t p_class_cfgp; 1227a3c5bd6dSspeer nxge_mv_cfg_t *mac_host_info; 122844961713Sgirish 122944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac_rdcgrp ")); 123044961713Sgirish 123144961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 123244961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 123344961713Sgirish p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 123444961713Sgirish mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 123544961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1236a3c5bd6dSspeer 1237a3c5bd6dSspeer /* 1238a3c5bd6dSspeer * now do decoding 1239a3c5bd6dSspeer */ 124044961713Sgirish mac_map = (nxge_param_map_t *)&cfg_value; 1241a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, NDD_CTL, " cfg_value %x id %x map_to %x", 1242a3c5bd6dSspeer cfg_value, mac_map->param_id, mac_map->map_to)); 124344961713Sgirish 124444961713Sgirish if ((mac_map->param_id < p_cfgp->max_macs) && 1245a3c5bd6dSspeer (mac_map->map_to < (p_cfgp->max_rdc_grpids + 1246a3c5bd6dSspeer p_cfgp->start_rdc_grpid)) && (mac_map->map_to >= 1247a3c5bd6dSspeer p_cfgp->start_rdc_grpid)) { 124844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1249a3c5bd6dSspeer " nxge_param_set_mac_rdcgrp mapping" 1250a3c5bd6dSspeer " id %d grp %d", mac_map->param_id, mac_map->map_to)); 125144961713Sgirish val_ptr = (uint32_t *)pa->value; 125244961713Sgirish old_val_ptr = (uint32_t *)pa->old_value; 125344961713Sgirish if (val_ptr[mac_map->param_id] != cfg_value) { 125444961713Sgirish old_val_ptr[mac_map->param_id] = 125544961713Sgirish val_ptr[mac_map->param_id]; 125644961713Sgirish val_ptr[mac_map->param_id] = cfg_value; 125744961713Sgirish mac_host_info[mac_map->param_id].mpr_npr = 125844961713Sgirish mac_map->pref; 125944961713Sgirish mac_host_info[mac_map->param_id].flag = 1; 126044961713Sgirish mac_host_info[mac_map->param_id].rdctbl = 126144961713Sgirish mac_map->map_to; 126244961713Sgirish cfg_it = B_TRUE; 126344961713Sgirish } 126444961713Sgirish } else { 126544961713Sgirish return (EINVAL); 126644961713Sgirish } 126744961713Sgirish 126844961713Sgirish if (cfg_it == B_TRUE) { 126944961713Sgirish status = nxge_logical_mac_assign_rdc_table(nxgep, 127044961713Sgirish (uint8_t)mac_map->param_id); 127144961713Sgirish if (status != NXGE_OK) 127244961713Sgirish return (EINVAL); 127344961713Sgirish } 127444961713Sgirish 127544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac_rdcgrp")); 127644961713Sgirish return (0); 127744961713Sgirish } 127844961713Sgirish 127944961713Sgirish /* ARGSUSED */ 128044961713Sgirish static int 128144961713Sgirish nxge_param_set_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q, 1282a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 128344961713Sgirish { 1284a3c5bd6dSspeer char *end; 1285a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1286a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1287a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 128844961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 128944961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 1290a3c5bd6dSspeer uint32_t *val_ptr, *old_val_ptr; 1291a3c5bd6dSspeer nxge_param_map_t *vmap, *old_map; 1292a3c5bd6dSspeer p_nxge_class_pt_cfg_t p_class_cfgp; 1293a3c5bd6dSspeer uint64_t cfgd_vlans; 1294a3c5bd6dSspeer int i, inc = 0, cfg_position; 1295a3c5bd6dSspeer nxge_mv_cfg_t *vlan_tbl; 129644961713Sgirish 129744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp ")); 129844961713Sgirish 129944961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 130044961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 130144961713Sgirish p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 130244961713Sgirish vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 130344961713Sgirish 130444961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1305a3c5bd6dSspeer 1306a3c5bd6dSspeer /* now do decoding */ 130744961713Sgirish cfgd_vlans = ((pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >> 1308a3c5bd6dSspeer NXGE_PARAM_ARRAY_CNT_SHIFT); 130944961713Sgirish 131044961713Sgirish if (cfgd_vlans == NXGE_PARAM_ARRAY_INIT_SIZE) { 131144961713Sgirish /* 131244961713Sgirish * for now, we process only upto max 131344961713Sgirish * NXGE_PARAM_ARRAY_INIT_SIZE parameters 131444961713Sgirish * In the future, we may want to expand 131544961713Sgirish * the storage array and continue 131644961713Sgirish */ 131744961713Sgirish return (EINVAL); 131844961713Sgirish } 1319a3c5bd6dSspeer 132044961713Sgirish vmap = (nxge_param_map_t *)&cfg_value; 132144961713Sgirish if ((vmap->param_id) && 132244961713Sgirish (vmap->param_id < NXGE_MAX_VLANS) && 132344961713Sgirish (vmap->map_to < p_cfgp->max_rdc_grpids)) { 132444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1325a3c5bd6dSspeer "nxge_param_set_vlan_rdcgrp mapping" 1326a3c5bd6dSspeer " id %d grp %d", 1327a3c5bd6dSspeer vmap->param_id, vmap->map_to)); 132844961713Sgirish val_ptr = (uint32_t *)pa->value; 132944961713Sgirish old_val_ptr = (uint32_t *)pa->old_value; 133044961713Sgirish 133144961713Sgirish /* search to see if this vlan id is already configured */ 133244961713Sgirish for (i = 0; i < cfgd_vlans; i++) { 133344961713Sgirish old_map = (nxge_param_map_t *)&val_ptr[i]; 133444961713Sgirish if ((old_map->param_id == 0) || 133544961713Sgirish (vmap->param_id == old_map->param_id) || 133644961713Sgirish (vlan_tbl[vmap->param_id].flag)) { 133744961713Sgirish cfg_position = i; 133844961713Sgirish break; 133944961713Sgirish } 134044961713Sgirish } 134144961713Sgirish 134244961713Sgirish if (cfgd_vlans == 0) { 134344961713Sgirish cfg_position = 0; 134444961713Sgirish inc++; 134544961713Sgirish } 134644961713Sgirish 134744961713Sgirish if (i == cfgd_vlans) { 134844961713Sgirish cfg_position = i; 134944961713Sgirish inc++; 135044961713Sgirish } 135144961713Sgirish 135244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 1353a3c5bd6dSspeer "set_vlan_rdcgrp mapping" 1354a3c5bd6dSspeer " i %d cfgd_vlans %llx position %d ", 1355a3c5bd6dSspeer i, cfgd_vlans, cfg_position)); 135644961713Sgirish if (val_ptr[cfg_position] != cfg_value) { 135744961713Sgirish old_val_ptr[cfg_position] = val_ptr[cfg_position]; 135844961713Sgirish val_ptr[cfg_position] = cfg_value; 135944961713Sgirish vlan_tbl[vmap->param_id].mpr_npr = vmap->pref; 136044961713Sgirish vlan_tbl[vmap->param_id].flag = 1; 136144961713Sgirish vlan_tbl[vmap->param_id].rdctbl = 136244961713Sgirish vmap->map_to + p_cfgp->start_rdc_grpid; 136344961713Sgirish cfg_it = B_TRUE; 136444961713Sgirish if (inc) { 136544961713Sgirish cfgd_vlans++; 136644961713Sgirish pa->type &= ~NXGE_PARAM_ARRAY_CNT_MASK; 136744961713Sgirish pa->type |= (cfgd_vlans << 136844961713Sgirish NXGE_PARAM_ARRAY_CNT_SHIFT); 136944961713Sgirish 137044961713Sgirish } 137144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 1372a3c5bd6dSspeer "after: param_set_vlan_rdcgrp " 1373a3c5bd6dSspeer " cfg_vlans %llx position %d \n", 1374a3c5bd6dSspeer cfgd_vlans, cfg_position)); 137544961713Sgirish } 137644961713Sgirish } else { 137744961713Sgirish return (EINVAL); 137844961713Sgirish } 137944961713Sgirish 138044961713Sgirish if (cfg_it == B_TRUE) { 138144961713Sgirish status = nxge_fflp_config_vlan_table(nxgep, 1382a3c5bd6dSspeer (uint16_t)vmap->param_id); 138344961713Sgirish if (status != NXGE_OK) 138444961713Sgirish return (EINVAL); 138544961713Sgirish } 138644961713Sgirish 138744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_vlan_rdcgrp")); 138844961713Sgirish return (0); 138944961713Sgirish } 139044961713Sgirish 139144961713Sgirish /* ARGSUSED */ 139244961713Sgirish static int 139344961713Sgirish nxge_param_get_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q, 1394a3c5bd6dSspeer mblk_t *mp, caddr_t cp) 139544961713Sgirish { 139644961713Sgirish 1397a3c5bd6dSspeer uint_t print_len, buf_len; 1398a3c5bd6dSspeer p_mblk_t np; 1399a3c5bd6dSspeer int i; 1400a3c5bd6dSspeer uint32_t *val_ptr; 1401a3c5bd6dSspeer nxge_param_map_t *vmap; 1402a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 140344961713Sgirish p_nxge_class_pt_cfg_t p_class_cfgp; 140444961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 140544961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 1406a3c5bd6dSspeer uint64_t cfgd_vlans = 0; 1407a3c5bd6dSspeer nxge_mv_cfg_t *vlan_tbl; 1408a3c5bd6dSspeer int buff_alloc_size = 1409a3c5bd6dSspeer NXGE_NDD_INFODUMP_BUFF_SIZE * 32; 141044961713Sgirish 141144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp ")); 1412a3c5bd6dSspeer (void) mi_mpprintf(mp, "VLAN RDC Mapping Information for Port\t %d \n", 1413a3c5bd6dSspeer nxgep->function_num); 141444961713Sgirish 141544961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 141644961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 141744961713Sgirish return (0); 141844961713Sgirish } 1419a3c5bd6dSspeer 142044961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 142144961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 142244961713Sgirish 142344961713Sgirish buf_len = buff_alloc_size; 142444961713Sgirish mp->b_cont = np; 142544961713Sgirish cfgd_vlans = (pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >> 142644961713Sgirish NXGE_PARAM_ARRAY_CNT_SHIFT; 142744961713Sgirish 142844961713Sgirish i = (int)cfgd_vlans; 142944961713Sgirish p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 143044961713Sgirish vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 143144961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1432a3c5bd6dSspeer "Configured VLANs %d\n" 1433a3c5bd6dSspeer "VLAN ID\t RDC GRP (Actual/Port)\t" 1434a3c5bd6dSspeer " Prefernce\n", i); 143544961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 143644961713Sgirish buf_len -= print_len; 143744961713Sgirish 143844961713Sgirish val_ptr = (uint32_t *)pa->value; 143944961713Sgirish 144044961713Sgirish for (i = 0; i < cfgd_vlans; i++) { 144144961713Sgirish vmap = (nxge_param_map_t *)&val_ptr[i]; 144244961713Sgirish if (p_class_cfgp->vlan_tbl[vmap->param_id].flag) { 144344961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1444a3c5bd6dSspeer buf_len, 1445a3c5bd6dSspeer " %d\t\t %d/%d\t\t %d\n", 1446a3c5bd6dSspeer vmap->param_id, 1447a3c5bd6dSspeer vlan_tbl[vmap->param_id].rdctbl, 1448a3c5bd6dSspeer vlan_tbl[vmap->param_id].rdctbl - 1449a3c5bd6dSspeer p_cfgp->start_rdc_grpid, 1450a3c5bd6dSspeer vlan_tbl[vmap->param_id].mpr_npr); 145144961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 145244961713Sgirish buf_len -= print_len; 145344961713Sgirish } 145444961713Sgirish } 145544961713Sgirish 145644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_vlan_rdcgrp")); 145744961713Sgirish return (0); 145844961713Sgirish } 145944961713Sgirish 146044961713Sgirish /* ARGSUSED */ 146144961713Sgirish static int 146244961713Sgirish nxge_param_get_mac_rdcgrp(p_nxge_t nxgep, queue_t *q, 1463a3c5bd6dSspeer mblk_t *mp, caddr_t cp) 146444961713Sgirish { 1465a3c5bd6dSspeer uint_t print_len, buf_len; 1466a3c5bd6dSspeer p_mblk_t np; 1467a3c5bd6dSspeer int i; 146844961713Sgirish p_nxge_class_pt_cfg_t p_class_cfgp; 146944961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 147044961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 1471a3c5bd6dSspeer nxge_mv_cfg_t *mac_host_info; 147244961713Sgirish 147344961713Sgirish int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE * 32; 147444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac_rdcgrp ")); 147544961713Sgirish (void) mi_mpprintf(mp, 1476a3c5bd6dSspeer "MAC ADDR RDC Mapping Information for Port\t %d\n", 1477a3c5bd6dSspeer nxgep->function_num); 147844961713Sgirish 147944961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 148044961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 148144961713Sgirish return (0); 148244961713Sgirish } 148344961713Sgirish 148444961713Sgirish buf_len = buff_alloc_size; 148544961713Sgirish mp->b_cont = np; 148644961713Sgirish p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 148744961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 148844961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 148944961713Sgirish mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 149044961713Sgirish print_len = snprintf((char *)np->b_wptr, buf_len, 1491a3c5bd6dSspeer "MAC ID\t RDC GRP (Actual/Port)\t" 1492a3c5bd6dSspeer " Prefernce\n"); 149344961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 149444961713Sgirish buf_len -= print_len; 149544961713Sgirish for (i = 0; i < p_cfgp->max_macs; i++) { 149644961713Sgirish if (mac_host_info[i].flag) { 149744961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1498a3c5bd6dSspeer buf_len, 1499a3c5bd6dSspeer " %d\t %d/%d\t\t %d\n", 1500a3c5bd6dSspeer i, mac_host_info[i].rdctbl, 1501a3c5bd6dSspeer mac_host_info[i].rdctbl - 1502a3c5bd6dSspeer p_cfgp->start_rdc_grpid, 1503a3c5bd6dSspeer mac_host_info[i].mpr_npr); 150444961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 150544961713Sgirish buf_len -= print_len; 150644961713Sgirish } 150744961713Sgirish } 150844961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1509a3c5bd6dSspeer "Done Info Dumping \n"); 151044961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 151144961713Sgirish buf_len -= print_len; 151244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_macrdcgrp")); 151344961713Sgirish return (0); 151444961713Sgirish } 151544961713Sgirish 151644961713Sgirish /* ARGSUSED */ 151744961713Sgirish static int 151844961713Sgirish nxge_param_tcam_enable(p_nxge_t nxgep, queue_t *q, 1519a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 152044961713Sgirish { 1521a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1522a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1523a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 1524a3c5bd6dSspeer char *end; 152544961713Sgirish 152644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_tcam_enable")); 152744961713Sgirish 152844961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 152944961713Sgirish if (pa->value != cfg_value) { 153044961713Sgirish pa->old_value = pa->value; 153144961713Sgirish pa->value = cfg_value; 153244961713Sgirish cfg_it = B_TRUE; 153344961713Sgirish } 153444961713Sgirish 153544961713Sgirish if (cfg_it == B_TRUE) { 153644961713Sgirish if (pa->value) 153744961713Sgirish status = nxge_fflp_config_tcam_enable(nxgep); 153844961713Sgirish else 153944961713Sgirish status = nxge_fflp_config_tcam_disable(nxgep); 154044961713Sgirish if (status != NXGE_OK) 154144961713Sgirish return (EINVAL); 154244961713Sgirish } 154344961713Sgirish 154444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_tcam_enable")); 154544961713Sgirish return (0); 154644961713Sgirish } 154744961713Sgirish 154844961713Sgirish /* ARGSUSED */ 154944961713Sgirish static int 155044961713Sgirish nxge_param_hash_lookup_enable(p_nxge_t nxgep, queue_t *q, 1551a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 155244961713Sgirish { 1553a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1554a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1555a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 1556a3c5bd6dSspeer char *end; 155744961713Sgirish 155844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_hash_lookup_enable")); 155944961713Sgirish 156044961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 156144961713Sgirish if (pa->value != cfg_value) { 156244961713Sgirish pa->old_value = pa->value; 156344961713Sgirish pa->value = cfg_value; 156444961713Sgirish cfg_it = B_TRUE; 156544961713Sgirish } 156644961713Sgirish 156744961713Sgirish if (cfg_it == B_TRUE) { 156844961713Sgirish if (pa->value) 156944961713Sgirish status = nxge_fflp_config_hash_lookup_enable(nxgep); 157044961713Sgirish else 157144961713Sgirish status = nxge_fflp_config_hash_lookup_disable(nxgep); 157244961713Sgirish if (status != NXGE_OK) 157344961713Sgirish return (EINVAL); 157444961713Sgirish } 157544961713Sgirish 157644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_hash_lookup_enable")); 157744961713Sgirish return (0); 157844961713Sgirish } 157944961713Sgirish 158044961713Sgirish /* ARGSUSED */ 158144961713Sgirish static int 158244961713Sgirish nxge_param_llc_snap_enable(p_nxge_t nxgep, queue_t *q, 1583a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 158444961713Sgirish { 1585a3c5bd6dSspeer char *end; 1586a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1587a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1588a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 158944961713Sgirish 159044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_llc_snap_enable")); 159144961713Sgirish 159244961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 159344961713Sgirish if (pa->value != cfg_value) { 159444961713Sgirish pa->old_value = pa->value; 159544961713Sgirish pa->value = cfg_value; 159644961713Sgirish cfg_it = B_TRUE; 159744961713Sgirish } 159844961713Sgirish 159944961713Sgirish if (cfg_it == B_TRUE) { 160044961713Sgirish if (pa->value) 160144961713Sgirish status = nxge_fflp_config_tcam_enable(nxgep); 160244961713Sgirish else 160344961713Sgirish status = nxge_fflp_config_tcam_disable(nxgep); 160444961713Sgirish if (status != NXGE_OK) 160544961713Sgirish return (EINVAL); 160644961713Sgirish } 160744961713Sgirish 160844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_llc_snap_enable")); 160944961713Sgirish return (0); 161044961713Sgirish } 161144961713Sgirish 161244961713Sgirish /* ARGSUSED */ 161344961713Sgirish static int 161444961713Sgirish nxge_param_set_ether_usr(p_nxge_t nxgep, queue_t *q, 1615a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 161644961713Sgirish { 1617a3c5bd6dSspeer char *end; 1618a3c5bd6dSspeer uint8_t ether_class; 1619a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1620a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1621a3c5bd6dSspeer uint8_t cfg_it = B_FALSE; 162244961713Sgirish 162344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ether_usr")); 162444961713Sgirish 162544961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 162644961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 162744961713Sgirish return (EINVAL); 162844961713Sgirish } 1629a3c5bd6dSspeer 163044961713Sgirish if (pa->value != cfg_value) { 163144961713Sgirish pa->old_value = pa->value; 163244961713Sgirish pa->value = cfg_value; 163344961713Sgirish cfg_it = B_TRUE; 163444961713Sgirish } 163544961713Sgirish 163644961713Sgirish /* do the actual hw setup */ 163744961713Sgirish if (cfg_it == B_TRUE) { 163844961713Sgirish ether_class = mi_strtol(pa->name, &end, 10); 163944961713Sgirish #ifdef lint 164044961713Sgirish ether_class = ether_class; 164144961713Sgirish #endif 164244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_ether_usr")); 164344961713Sgirish } 1644a3c5bd6dSspeer 164544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ether_usr")); 164644961713Sgirish return (status); 164744961713Sgirish } 164844961713Sgirish 164944961713Sgirish /* ARGSUSED */ 165044961713Sgirish static int 165144961713Sgirish nxge_param_set_ip_usr(p_nxge_t nxgep, queue_t *q, 1652a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 165344961713Sgirish { 1654a3c5bd6dSspeer char *end; 1655a3c5bd6dSspeer tcam_class_t class; 1656a3c5bd6dSspeer uint32_t status, cfg_value; 1657a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1658a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 165944961713Sgirish 166044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_usr")); 166144961713Sgirish 166244961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 166344961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 166444961713Sgirish return (EINVAL); 166544961713Sgirish } 166644961713Sgirish 166744961713Sgirish if (pa->value != cfg_value) { 166844961713Sgirish pa->old_value = pa->value; 166944961713Sgirish pa->value = cfg_value; 167044961713Sgirish cfg_it = B_TRUE; 167144961713Sgirish } 167244961713Sgirish 167344961713Sgirish /* do the actual hw setup with cfg_value. */ 167444961713Sgirish if (cfg_it == B_TRUE) { 167544961713Sgirish class = mi_strtol(pa->name, &end, 10); 167644961713Sgirish status = nxge_fflp_ip_usr_class_config(nxgep, class, pa->value); 167744961713Sgirish } 167844961713Sgirish 167944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_usr")); 168044961713Sgirish return (status); 168144961713Sgirish } 168244961713Sgirish 1683a3c5bd6dSspeer /* ARGSUSED */ 168444961713Sgirish static int 168544961713Sgirish nxge_class_name_2value(p_nxge_t nxgep, char *name) 168644961713Sgirish { 1687a3c5bd6dSspeer int i; 1688a3c5bd6dSspeer int class_instance = param_class_opt_ip_usr4; 1689a3c5bd6dSspeer p_nxge_param_t param_arr; 1690a3c5bd6dSspeer 169144961713Sgirish param_arr = nxgep->param_arr; 169244961713Sgirish for (i = TCAM_CLASS_IP_USER_4; i <= TCAM_CLASS_SCTP_IPV6; i++) { 169344961713Sgirish if (strcmp(param_arr[class_instance].name, name) == 0) 169444961713Sgirish return (i); 169544961713Sgirish class_instance++; 169644961713Sgirish } 169744961713Sgirish return (-1); 169844961713Sgirish } 169944961713Sgirish 170044961713Sgirish /* ARGSUSED */ 170144961713Sgirish static int 170244961713Sgirish nxge_param_set_ip_opt(p_nxge_t nxgep, queue_t *q, 1703a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 170444961713Sgirish { 1705a3c5bd6dSspeer char *end; 1706a3c5bd6dSspeer uint32_t status, cfg_value; 1707a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1708a3c5bd6dSspeer tcam_class_t class; 1709a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 171044961713Sgirish 171144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_opt")); 171244961713Sgirish 171344961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 171444961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 171544961713Sgirish return (EINVAL); 171644961713Sgirish } 171744961713Sgirish 171844961713Sgirish if (pa->value != cfg_value) { 171944961713Sgirish pa->old_value = pa->value; 172044961713Sgirish pa->value = cfg_value; 172144961713Sgirish cfg_it = B_TRUE; 172244961713Sgirish } 172344961713Sgirish 172444961713Sgirish if (cfg_it == B_TRUE) { 1725a3c5bd6dSspeer /* do the actual hw setup */ 172644961713Sgirish class = nxge_class_name_2value(nxgep, pa->name); 172744961713Sgirish if (class == -1) 172844961713Sgirish return (EINVAL); 172944961713Sgirish 173044961713Sgirish status = nxge_fflp_ip_class_config(nxgep, class, pa->value); 173144961713Sgirish if (status != NXGE_OK) 173244961713Sgirish return (EINVAL); 173344961713Sgirish } 173444961713Sgirish 173544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_opt")); 173644961713Sgirish return (0); 173744961713Sgirish } 173844961713Sgirish 173944961713Sgirish /* ARGSUSED */ 174044961713Sgirish static int 174144961713Sgirish nxge_param_get_ip_opt(p_nxge_t nxgep, queue_t *q, 1742a3c5bd6dSspeer mblk_t *mp, caddr_t cp) 174344961713Sgirish { 174444961713Sgirish uint32_t status, cfg_value; 174544961713Sgirish p_nxge_param_t pa = (p_nxge_param_t)cp; 174644961713Sgirish tcam_class_t class; 174744961713Sgirish 174844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_ip_opt")); 174944961713Sgirish 1750a3c5bd6dSspeer /* do the actual hw setup */ 175144961713Sgirish class = nxge_class_name_2value(nxgep, pa->name); 175244961713Sgirish if (class == -1) 175344961713Sgirish return (EINVAL); 1754a3c5bd6dSspeer 175544961713Sgirish cfg_value = 0; 175644961713Sgirish status = nxge_fflp_ip_class_config_get(nxgep, class, &cfg_value); 175744961713Sgirish if (status != NXGE_OK) 175844961713Sgirish return (EINVAL); 1759a3c5bd6dSspeer 176044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1761a3c5bd6dSspeer "nxge_param_get_ip_opt_get %x ", cfg_value)); 176244961713Sgirish 1763a3c5bd6dSspeer pa->value = cfg_value; 176444961713Sgirish (void) mi_mpprintf(mp, "%x", cfg_value); 1765a3c5bd6dSspeer 176644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_ip_opt status ")); 176744961713Sgirish return (0); 176844961713Sgirish } 176944961713Sgirish 177044961713Sgirish /* ARGSUSED */ 177144961713Sgirish static int 177244961713Sgirish nxge_param_fflp_hash_init(p_nxge_t nxgep, queue_t *q, 1773a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 177444961713Sgirish { 1775a3c5bd6dSspeer char *end; 1776a3c5bd6dSspeer uint32_t status, cfg_value; 1777a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1778a3c5bd6dSspeer tcam_class_t class; 1779a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 178044961713Sgirish 178144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_fflp_hash_init")); 178244961713Sgirish 178344961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 178444961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 178544961713Sgirish return (EINVAL); 178644961713Sgirish } 178744961713Sgirish 178844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1789a3c5bd6dSspeer "nxge_param_fflp_hash_init value %x", cfg_value)); 1790a3c5bd6dSspeer 179144961713Sgirish if (pa->value != cfg_value) { 179244961713Sgirish pa->old_value = pa->value; 179344961713Sgirish pa->value = cfg_value; 179444961713Sgirish cfg_it = B_TRUE; 179544961713Sgirish } 179644961713Sgirish 179744961713Sgirish if (cfg_it == B_TRUE) { 179844961713Sgirish char *h_name; 1799a3c5bd6dSspeer 180044961713Sgirish /* do the actual hw setup */ 180144961713Sgirish h_name = pa->name; 180244961713Sgirish h_name++; 180344961713Sgirish class = mi_strtol(h_name, &end, 10); 180444961713Sgirish switch (class) { 180544961713Sgirish case 1: 180644961713Sgirish status = nxge_fflp_set_hash1(nxgep, 1807a3c5bd6dSspeer (uint32_t)pa->value); 180844961713Sgirish break; 180944961713Sgirish case 2: 181044961713Sgirish status = nxge_fflp_set_hash2(nxgep, 1811a3c5bd6dSspeer (uint16_t)pa->value); 181244961713Sgirish break; 181344961713Sgirish 181444961713Sgirish default: 181544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1816a3c5bd6dSspeer " nxge_param_fflp_hash_init" 1817a3c5bd6dSspeer " %s Wrong hash var %d", 1818a3c5bd6dSspeer pa->name, class)); 181944961713Sgirish return (EINVAL); 182044961713Sgirish } 182144961713Sgirish if (status != NXGE_OK) 182244961713Sgirish return (EINVAL); 182344961713Sgirish } 182444961713Sgirish 182544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_fflp_hash_init")); 182644961713Sgirish return (0); 182744961713Sgirish } 182844961713Sgirish 182944961713Sgirish /* ARGSUSED */ 183044961713Sgirish static int 183144961713Sgirish nxge_param_set_grp_rdc(p_nxge_t nxgep, queue_t *q, 1832a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 183344961713Sgirish { 1834a3c5bd6dSspeer char *end; 1835a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1836a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1837a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 1838a3c5bd6dSspeer int rdc_grp; 1839a3c5bd6dSspeer uint8_t real_rdc; 184044961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 184144961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 184244961713Sgirish p_nxge_rdc_grp_t rdc_grp_p; 184344961713Sgirish 184444961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 184544961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 184644961713Sgirish 184744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_grp_rdc")); 184844961713Sgirish 184944961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 185044961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 185144961713Sgirish return (EINVAL); 185244961713Sgirish } 1853a3c5bd6dSspeer 185444961713Sgirish if (cfg_value >= p_cfgp->max_rdcs) { 185544961713Sgirish return (EINVAL); 185644961713Sgirish } 1857a3c5bd6dSspeer 185844961713Sgirish if (pa->value != cfg_value) { 185944961713Sgirish pa->old_value = pa->value; 186044961713Sgirish pa->value = cfg_value; 186144961713Sgirish cfg_it = B_TRUE; 186244961713Sgirish } 186344961713Sgirish 186444961713Sgirish if (cfg_it == B_TRUE) { 186544961713Sgirish char *grp_name; 186644961713Sgirish grp_name = pa->name; 186744961713Sgirish grp_name += strlen("default-grp"); 186844961713Sgirish rdc_grp = mi_strtol(grp_name, &end, 10); 186944961713Sgirish rdc_grp_p = &p_dma_cfgp->rdc_grps[rdc_grp]; 187044961713Sgirish real_rdc = rdc_grp_p->start_rdc + cfg_value; 187144961713Sgirish if (nxge_check_rxdma_rdcgrp_member(nxgep, rdc_grp, 1872a3c5bd6dSspeer cfg_value) == B_FALSE) { 187344961713Sgirish pa->value = pa->old_value; 187444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1875a3c5bd6dSspeer " nxge_param_set_grp_rdc" 1876a3c5bd6dSspeer " %d read %d actual %d outof range", 1877a3c5bd6dSspeer rdc_grp, cfg_value, real_rdc)); 187844961713Sgirish return (EINVAL); 187944961713Sgirish } 188044961713Sgirish status = nxge_rxdma_cfg_rdcgrp_default_rdc(nxgep, rdc_grp, 188144961713Sgirish real_rdc); 188244961713Sgirish if (status != NXGE_OK) 188344961713Sgirish return (EINVAL); 188444961713Sgirish } 188544961713Sgirish 188644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_grp_rdc")); 188744961713Sgirish return (0); 188844961713Sgirish } 188944961713Sgirish 189044961713Sgirish /* ARGSUSED */ 189144961713Sgirish static int 189244961713Sgirish nxge_param_set_port_rdc(p_nxge_t nxgep, queue_t *q, 1893a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 189444961713Sgirish { 1895a3c5bd6dSspeer char *end; 1896a3c5bd6dSspeer uint32_t status = B_TRUE, cfg_value; 1897a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1898a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 189944961713Sgirish 190044961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 190144961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 190244961713Sgirish 190344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_port_rdc")); 190444961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 190544961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 190644961713Sgirish 190744961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 190844961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 190944961713Sgirish return (EINVAL); 191044961713Sgirish } 1911a3c5bd6dSspeer 191244961713Sgirish if (pa->value != cfg_value) { 191344961713Sgirish if (cfg_value >= p_cfgp->max_rdcs) 191444961713Sgirish return (EINVAL); 191544961713Sgirish pa->old_value = pa->value; 191644961713Sgirish pa->value = cfg_value; 191744961713Sgirish cfg_it = B_TRUE; 191844961713Sgirish } 191944961713Sgirish 192044961713Sgirish if (cfg_it == B_TRUE) { 192144961713Sgirish status = nxge_rxdma_cfg_port_default_rdc(nxgep, 1922a3c5bd6dSspeer nxgep->function_num, 1923a3c5bd6dSspeer nxgep->rdc[cfg_value]); 192444961713Sgirish if (status != NXGE_OK) 192544961713Sgirish return (EINVAL); 192644961713Sgirish } 192744961713Sgirish 192844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_port_rdc")); 192944961713Sgirish return (0); 193044961713Sgirish } 193144961713Sgirish 193244961713Sgirish /* ARGSUSED */ 193344961713Sgirish static int 193444961713Sgirish nxge_param_set_nxge_debug_flag(p_nxge_t nxgep, queue_t *q, 1935a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 193644961713Sgirish { 193744961713Sgirish char *end; 193844961713Sgirish uint32_t status = 0; 193944961713Sgirish uint64_t cfg_value = 0; 194044961713Sgirish p_nxge_param_t pa = (p_nxge_param_t)cp; 194144961713Sgirish uint32_t cfg_it = B_FALSE; 194244961713Sgirish 194344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_nxge_debug_flag")); 194444961713Sgirish cfg_value = mi_strtol(value, &end, BASE_HEX); 194544961713Sgirish 194644961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 194744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1948a3c5bd6dSspeer " nxge_param_set_nxge_debug_flag" 1949a3c5bd6dSspeer " outof range %llx", cfg_value)); 195044961713Sgirish return (EINVAL); 195144961713Sgirish } 195244961713Sgirish if (pa->value != cfg_value) { 195344961713Sgirish pa->old_value = pa->value; 195444961713Sgirish pa->value = cfg_value; 195544961713Sgirish cfg_it = B_TRUE; 195644961713Sgirish } 195744961713Sgirish 195844961713Sgirish if (cfg_it == B_TRUE) { 195944961713Sgirish nxgep->nxge_debug_level = pa->value; 196044961713Sgirish } 1961a3c5bd6dSspeer 196244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_nxge_debug_flag")); 196344961713Sgirish return (status); 196444961713Sgirish } 196544961713Sgirish 196644961713Sgirish /* ARGSUSED */ 196744961713Sgirish static int 196844961713Sgirish nxge_param_get_debug_flag(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 196944961713Sgirish { 1970a3c5bd6dSspeer int status = 0; 1971a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 197244961713Sgirish 197344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_debug_flag")); 197444961713Sgirish 197544961713Sgirish if (pa->value > 0xffffffff) 197644961713Sgirish (void) mi_mpprintf(mp, "%x%x", (int)(pa->value >> 32), 1977a3c5bd6dSspeer (int)(pa->value & 0xffffffff)); 197844961713Sgirish else 197944961713Sgirish (void) mi_mpprintf(mp, "%x", (int)pa->value); 198044961713Sgirish 198144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_debug_flag")); 198244961713Sgirish return (status); 198344961713Sgirish } 198444961713Sgirish 198544961713Sgirish /* ARGSUSED */ 198644961713Sgirish static int 198744961713Sgirish nxge_param_set_npi_debug_flag(p_nxge_t nxgep, queue_t *q, 1988a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 198944961713Sgirish { 1990a3c5bd6dSspeer char *end; 1991a3c5bd6dSspeer uint32_t status = 0; 1992a3c5bd6dSspeer uint64_t cfg_value = 0; 1993a3c5bd6dSspeer p_nxge_param_t pa; 1994a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 199544961713Sgirish 199644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_npi_debug_flag")); 199744961713Sgirish cfg_value = mi_strtol(value, &end, BASE_HEX); 199844961713Sgirish pa = (p_nxge_param_t)cp; 199944961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 200044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_npi_debug_flag" 200144961713Sgirish " outof range %llx", cfg_value)); 200244961713Sgirish return (EINVAL); 200344961713Sgirish } 200444961713Sgirish if (pa->value != cfg_value) { 200544961713Sgirish pa->old_value = pa->value; 200644961713Sgirish pa->value = cfg_value; 200744961713Sgirish cfg_it = B_TRUE; 200844961713Sgirish } 200944961713Sgirish 201044961713Sgirish if (cfg_it == B_TRUE) { 201144961713Sgirish npi_debug_level = pa->value; 201244961713Sgirish } 201344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_debug_flag")); 201444961713Sgirish return (status); 201544961713Sgirish } 201644961713Sgirish 201744961713Sgirish /* ARGSUSED */ 201844961713Sgirish static int 201944961713Sgirish nxge_param_dump_rdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 202044961713Sgirish { 2021a3c5bd6dSspeer uint_t rdc; 202244961713Sgirish 202344961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_rdc")); 202444961713Sgirish 202544961713Sgirish (void) npi_rxdma_dump_fzc_regs(NXGE_DEV_NPI_HANDLE(nxgep)); 202644961713Sgirish for (rdc = 0; rdc < nxgep->nrdc; rdc++) 202744961713Sgirish (void) nxge_dump_rxdma_channel(nxgep, nxgep->rdc[rdc]); 202844961713Sgirish 202944961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_rdc")); 203044961713Sgirish return (0); 203144961713Sgirish } 203244961713Sgirish 203344961713Sgirish /* ARGSUSED */ 203444961713Sgirish static int 203544961713Sgirish nxge_param_dump_tdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 203644961713Sgirish { 203744961713Sgirish uint_t tdc; 203844961713Sgirish 203944961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_tdc")); 204044961713Sgirish 204144961713Sgirish for (tdc = 0; tdc < nxgep->ntdc; tdc++) 204244961713Sgirish (void) nxge_txdma_regs_dump(nxgep, nxgep->tdc[tdc]); 204344961713Sgirish 204444961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_tdc")); 204544961713Sgirish return (0); 204644961713Sgirish } 204744961713Sgirish 204844961713Sgirish /* ARGSUSED */ 204944961713Sgirish static int 205044961713Sgirish nxge_param_dump_fflp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 205144961713Sgirish { 205244961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_fflp_regs")); 205344961713Sgirish 205444961713Sgirish (void) npi_fflp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep)); 205544961713Sgirish 205644961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_fflp_regs")); 205744961713Sgirish return (0); 205844961713Sgirish } 205944961713Sgirish 206044961713Sgirish /* ARGSUSED */ 206144961713Sgirish static int 206244961713Sgirish nxge_param_dump_mac_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 206344961713Sgirish { 206444961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_mac_regs")); 206544961713Sgirish 206644961713Sgirish (void) npi_mac_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep), 2067a3c5bd6dSspeer nxgep->function_num); 206844961713Sgirish 206944961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_mac_regs")); 207044961713Sgirish return (0); 207144961713Sgirish } 207244961713Sgirish 207344961713Sgirish /* ARGSUSED */ 207444961713Sgirish static int 207544961713Sgirish nxge_param_dump_ipp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 207644961713Sgirish { 207744961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_ipp_regs")); 207844961713Sgirish 2079a3c5bd6dSspeer (void) npi_ipp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep), 2080a3c5bd6dSspeer nxgep->function_num); 208144961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ipp_regs")); 208244961713Sgirish return (0); 208344961713Sgirish } 208444961713Sgirish 208544961713Sgirish /* ARGSUSED */ 208644961713Sgirish static int 208744961713Sgirish nxge_param_dump_vlan_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 208844961713Sgirish { 208944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_vlan_table")); 209044961713Sgirish 209144961713Sgirish (void) npi_fflp_vlan_tbl_dump(NXGE_DEV_NPI_HANDLE(nxgep)); 209244961713Sgirish 209344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_vlan_table")); 209444961713Sgirish return (0); 209544961713Sgirish } 209644961713Sgirish 209744961713Sgirish /* ARGSUSED */ 209844961713Sgirish static int 209944961713Sgirish nxge_param_dump_rdc_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 210044961713Sgirish { 2101a3c5bd6dSspeer uint8_t table; 210244961713Sgirish 210344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_rdc_table")); 210444961713Sgirish for (table = 0; table < NXGE_MAX_RDC_GROUPS; table++) { 210544961713Sgirish (void) npi_rxdma_dump_rdc_table(NXGE_DEV_NPI_HANDLE(nxgep), 210644961713Sgirish table); 210744961713Sgirish } 2108a3c5bd6dSspeer 210944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_rdc_table")); 211044961713Sgirish return (0); 211144961713Sgirish } 211244961713Sgirish 211344961713Sgirish typedef struct block_info { 211444961713Sgirish char *name; 211544961713Sgirish uint32_t offset; 211644961713Sgirish } block_info_t; 211744961713Sgirish 211844961713Sgirish block_info_t reg_block[] = { 211944961713Sgirish {"PIO", PIO}, 212044961713Sgirish {"FZC_PIO", FZC_PIO}, 212144961713Sgirish {"FZC_XMAC", FZC_MAC}, 212244961713Sgirish {"FZC_IPP", FZC_IPP}, 212344961713Sgirish {"FFLP", FFLP}, 212444961713Sgirish {"FZC_FFLP", FZC_FFLP}, 212544961713Sgirish {"PIO_VADDR", PIO_VADDR}, 212644961713Sgirish {"ZCP", ZCP}, 212744961713Sgirish {"FZC_ZCP", FZC_ZCP}, 212844961713Sgirish {"DMC", DMC}, 212944961713Sgirish {"FZC_DMC", FZC_DMC}, 213044961713Sgirish {"TXC", TXC}, 213144961713Sgirish {"FZC_TXC", FZC_TXC}, 213244961713Sgirish {"PIO_LDSV", PIO_LDSV}, 213344961713Sgirish {"PIO_LDGIM", PIO_LDGIM}, 213444961713Sgirish {"PIO_IMASK0", PIO_IMASK0}, 213544961713Sgirish {"PIO_IMASK1", PIO_IMASK1}, 213644961713Sgirish {"FZC_PROM", FZC_PROM}, 213744961713Sgirish {"END", ALL_FF_32}, 213844961713Sgirish }; 213944961713Sgirish 214044961713Sgirish /* ARGSUSED */ 214144961713Sgirish static int 214244961713Sgirish nxge_param_dump_ptrs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 214344961713Sgirish { 2144a3c5bd6dSspeer uint_t print_len, buf_len; 2145a3c5bd6dSspeer p_mblk_t np; 2146a3c5bd6dSspeer int rdc, tdc, block; 2147a3c5bd6dSspeer uint64_t base; 214844961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 214944961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 2150a3c5bd6dSspeer int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_8K; 215144961713Sgirish p_tx_ring_t *tx_rings; 215244961713Sgirish p_rx_rcr_rings_t rx_rcr_rings; 215344961713Sgirish p_rx_rcr_ring_t *rcr_rings; 215444961713Sgirish p_rx_rbr_rings_t rx_rbr_rings; 215544961713Sgirish p_rx_rbr_ring_t *rbr_rings; 215644961713Sgirish 2157a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, IOC_CTL, 2158a3c5bd6dSspeer "==> nxge_param_dump_ptrs")); 215944961713Sgirish 2160a3c5bd6dSspeer (void) mi_mpprintf(mp, "ptr information for Port\t %d \n", 2161a3c5bd6dSspeer nxgep->function_num); 216244961713Sgirish 216344961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 216444961713Sgirish /* The following may work even if we cannot get a large buf. */ 216544961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 216644961713Sgirish return (0); 216744961713Sgirish } 216844961713Sgirish 216944961713Sgirish buf_len = buff_alloc_size; 217044961713Sgirish mp->b_cont = np; 217144961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 217244961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 217344961713Sgirish 217444961713Sgirish rx_rcr_rings = nxgep->rx_rcr_rings; 217544961713Sgirish rcr_rings = rx_rcr_rings->rcr_rings; 217644961713Sgirish rx_rbr_rings = nxgep->rx_rbr_rings; 217744961713Sgirish rbr_rings = rx_rbr_rings->rbr_rings; 217844961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2179a3c5bd6dSspeer "nxgep (nxge_t) $%p\n" 2180a3c5bd6dSspeer "dev_regs (dev_regs_t) $%p\n", 2181a3c5bd6dSspeer nxgep, nxgep->dev_regs); 218244961713Sgirish 218344961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2184a3c5bd6dSspeer 2185a3c5bd6dSspeer /* do register pointers */ 218644961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2187a3c5bd6dSspeer "reg base (npi_reg_ptr_t) $%p\t " 2188a3c5bd6dSspeer "pci reg (npi_reg_ptr_t) $%p\n", 2189a3c5bd6dSspeer nxgep->dev_regs->nxge_regp, 2190a3c5bd6dSspeer nxgep->dev_regs->nxge_pciregp); 219144961713Sgirish 219244961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 219344961713Sgirish 219444961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2195a3c5bd6dSspeer "\nBlock \t Offset \n"); 219644961713Sgirish 219744961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 219844961713Sgirish block = 0; 219944961713Sgirish base = (uint64_t)nxgep->dev_regs->nxge_regp; 220044961713Sgirish while (reg_block[block].offset != ALL_FF_32) { 220144961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2202a3c5bd6dSspeer "%9s\t 0x%llx\n", 2203a3c5bd6dSspeer reg_block[block].name, 2204a3c5bd6dSspeer (unsigned long long)(reg_block[block].offset + base)); 220544961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 220644961713Sgirish block++; 220744961713Sgirish } 220844961713Sgirish 220944961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2210a3c5bd6dSspeer "\nRDC\t rcrp (rx_rcr_ring_t)\t " 2211a3c5bd6dSspeer "rbrp (rx_rbr_ring_t)\n"); 221244961713Sgirish 221344961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 221444961713Sgirish 221544961713Sgirish for (rdc = 0; rdc < p_cfgp->max_rdcs; rdc++) { 221644961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2217a3c5bd6dSspeer " %d\t $%p\t\t $%p\n", 2218a3c5bd6dSspeer rdc, rcr_rings[rdc], 2219a3c5bd6dSspeer rbr_rings[rdc]); 222044961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 222144961713Sgirish } 222244961713Sgirish 222344961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 222444961713Sgirish "\nTDC\t tdcp (tx_ring_t)\n"); 222544961713Sgirish 222644961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 222744961713Sgirish tx_rings = nxgep->tx_rings->rings; 222844961713Sgirish for (tdc = 0; tdc < p_cfgp->max_tdcs; tdc++) { 222944961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2230a3c5bd6dSspeer " %d\t $%p\n", tdc, tx_rings[tdc]); 223144961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 223244961713Sgirish } 223344961713Sgirish 2234a3c5bd6dSspeer print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, "\n\n"); 223544961713Sgirish 223644961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 223744961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ptrs")); 223844961713Sgirish return (0); 223944961713Sgirish } 224044961713Sgirish 224144961713Sgirish /* 224244961713Sgirish * Load 'name' into the named dispatch table pointed to by 'ndp'. 224344961713Sgirish * 'ndp' should be the address of a char pointer cell. If the table 224444961713Sgirish * does not exist (*ndp == 0), a new table is allocated and 'ndp' 224544961713Sgirish * is stuffed. If there is not enough space in the table for a new 224644961713Sgirish * entry, more space is allocated. 224744961713Sgirish */ 2248a3c5bd6dSspeer /* ARGSUSED */ 224944961713Sgirish boolean_t 225044961713Sgirish nxge_nd_load(caddr_t *pparam, char *name, 2251a3c5bd6dSspeer pfi_t get_pfi, pfi_t set_pfi, caddr_t data) 225244961713Sgirish { 225344961713Sgirish ND *nd; 225444961713Sgirish NDE *nde; 225544961713Sgirish 225644961713Sgirish NXGE_DEBUG_MSG((NULL, NDD2_CTL, " ==> nxge_nd_load")); 225744961713Sgirish if (!pparam) 225844961713Sgirish return (B_FALSE); 2259a3c5bd6dSspeer 226044961713Sgirish if ((nd = (ND *)*pparam) == NULL) { 2261a3c5bd6dSspeer if ((nd = (ND *)KMEM_ZALLOC(sizeof (ND), KM_NOSLEEP)) == NULL) 226244961713Sgirish return (B_FALSE); 226344961713Sgirish *pparam = (caddr_t)nd; 226444961713Sgirish } 2265a3c5bd6dSspeer 226644961713Sgirish if (nd->nd_tbl) { 226744961713Sgirish for (nde = nd->nd_tbl; nde->nde_name; nde++) { 226844961713Sgirish if (strcmp(name, nde->nde_name) == 0) 226944961713Sgirish goto fill_it; 227044961713Sgirish } 227144961713Sgirish } 2272a3c5bd6dSspeer 227344961713Sgirish if (nd->nd_free_count <= 1) { 227444961713Sgirish if ((nde = (NDE *)KMEM_ZALLOC(nd->nd_size + 227544961713Sgirish NDE_ALLOC_SIZE, KM_NOSLEEP)) == NULL) 227644961713Sgirish return (B_FALSE); 227744961713Sgirish nd->nd_free_count += NDE_ALLOC_COUNT; 227844961713Sgirish if (nd->nd_tbl) { 227944961713Sgirish bcopy((char *)nd->nd_tbl, (char *)nde, nd->nd_size); 228044961713Sgirish KMEM_FREE((char *)nd->nd_tbl, nd->nd_size); 228144961713Sgirish } else { 228244961713Sgirish nd->nd_free_count--; 228344961713Sgirish nde->nde_name = "?"; 228444961713Sgirish nde->nde_get_pfi = nxge_nd_get_names; 228544961713Sgirish nde->nde_set_pfi = nxge_set_default; 228644961713Sgirish } 228744961713Sgirish nde->nde_data = (caddr_t)nd; 228844961713Sgirish nd->nd_tbl = nde; 228944961713Sgirish nd->nd_size += NDE_ALLOC_SIZE; 229044961713Sgirish } 229144961713Sgirish for (nde = nd->nd_tbl; nde->nde_name; nde++) 229244961713Sgirish noop; 229344961713Sgirish nd->nd_free_count--; 229444961713Sgirish fill_it: 229544961713Sgirish nde->nde_name = name; 229644961713Sgirish nde->nde_get_pfi = get_pfi; 229744961713Sgirish nde->nde_set_pfi = set_pfi; 229844961713Sgirish nde->nde_data = data; 229944961713Sgirish NXGE_DEBUG_MSG((NULL, NDD2_CTL, " <== nxge_nd_load")); 230044961713Sgirish 230144961713Sgirish return (B_TRUE); 230244961713Sgirish } 230344961713Sgirish 230444961713Sgirish /* 230544961713Sgirish * Free the table pointed to by 'pparam' 230644961713Sgirish */ 230744961713Sgirish void 230844961713Sgirish nxge_nd_free(caddr_t *pparam) 230944961713Sgirish { 2310a3c5bd6dSspeer ND *nd; 231144961713Sgirish 231244961713Sgirish if ((nd = (ND *)*pparam) != NULL) { 231344961713Sgirish if (nd->nd_tbl) 231444961713Sgirish KMEM_FREE((char *)nd->nd_tbl, nd->nd_size); 231544961713Sgirish KMEM_FREE((char *)nd, sizeof (ND)); 231644961713Sgirish *pparam = nil(caddr_t); 231744961713Sgirish } 231844961713Sgirish } 231944961713Sgirish 232044961713Sgirish int 232144961713Sgirish nxge_nd_getset(p_nxge_t nxgep, queue_t *q, caddr_t param, p_mblk_t mp) 232244961713Sgirish { 2323a3c5bd6dSspeer int err; 2324a3c5bd6dSspeer IOCP iocp; 2325a3c5bd6dSspeer p_mblk_t mp1, mp2; 2326a3c5bd6dSspeer ND *nd; 2327a3c5bd6dSspeer NDE *nde; 2328a3c5bd6dSspeer char *valp; 2329a3c5bd6dSspeer size_t avail; 233044961713Sgirish 233144961713Sgirish if (!param) { 233244961713Sgirish return (B_FALSE); 233344961713Sgirish } 2334a3c5bd6dSspeer 233544961713Sgirish nd = (ND *)param; 233644961713Sgirish iocp = (IOCP)mp->b_rptr; 233744961713Sgirish if ((iocp->ioc_count == 0) || !(mp1 = mp->b_cont)) { 233844961713Sgirish mp->b_datap->db_type = M_IOCACK; 233944961713Sgirish iocp->ioc_count = 0; 234044961713Sgirish iocp->ioc_error = EINVAL; 234144961713Sgirish return (B_FALSE); 234244961713Sgirish } 2343a3c5bd6dSspeer 234444961713Sgirish /* 234544961713Sgirish * NOTE - logic throughout nd_xxx assumes single data block for ioctl. 234644961713Sgirish * However, existing code sends in some big buffers. 234744961713Sgirish */ 234844961713Sgirish avail = iocp->ioc_count; 234944961713Sgirish if (mp1->b_cont) { 235044961713Sgirish freemsg(mp1->b_cont); 235144961713Sgirish mp1->b_cont = NULL; 235244961713Sgirish } 235344961713Sgirish 235444961713Sgirish mp1->b_datap->db_lim[-1] = '\0'; /* Force null termination */ 235544961713Sgirish for (valp = (char *)mp1->b_rptr; *valp != '\0'; valp++) { 235644961713Sgirish if (*valp == '-') 235744961713Sgirish *valp = '_'; 235844961713Sgirish } 235944961713Sgirish 236044961713Sgirish valp = (char *)mp1->b_rptr; 236144961713Sgirish 236244961713Sgirish for (nde = nd->nd_tbl; /* */; nde++) { 236344961713Sgirish if (!nde->nde_name) 236444961713Sgirish return (B_FALSE); 236544961713Sgirish if (strcmp(nde->nde_name, valp) == 0) 236644961713Sgirish break; 236744961713Sgirish } 236844961713Sgirish err = EINVAL; 236944961713Sgirish while (*valp++) 237044961713Sgirish noop; 237144961713Sgirish if (!*valp || valp >= (char *)mp1->b_wptr) 237244961713Sgirish valp = nilp(char); 237344961713Sgirish switch (iocp->ioc_cmd) { 237444961713Sgirish case ND_GET: 237544961713Sgirish /* 237644961713Sgirish * (temporary) hack: "*valp" is size of user buffer for 237744961713Sgirish * copyout. If result of action routine is too big, free 237844961713Sgirish * excess and return ioc_rval as buffer size needed. 237944961713Sgirish * Return as many mblocks as will fit, free the rest. For 238044961713Sgirish * backward compatibility, assume size of original ioctl 238144961713Sgirish * buffer if "*valp" bad or not given. 238244961713Sgirish */ 238344961713Sgirish if (valp) 238444961713Sgirish avail = mi_strtol(valp, (char **)0, 10); 238544961713Sgirish /* 238644961713Sgirish * We overwrite the name/value with the reply data 238744961713Sgirish */ 238844961713Sgirish mp2 = mp1; 238944961713Sgirish while (mp2) { 239044961713Sgirish mp2->b_wptr = mp2->b_rptr; 239144961713Sgirish mp2 = mp2->b_cont; 239244961713Sgirish } 239344961713Sgirish 2394846a903dSml if (nde->nde_get_pfi) { 2395846a903dSml err = (*nde->nde_get_pfi)(nxgep, q, mp1, nde->nde_data); 2396846a903dSml } 239744961713Sgirish 239844961713Sgirish if (!err) { 239944961713Sgirish size_t size_out = 0; 240044961713Sgirish size_t excess; 240144961713Sgirish 240244961713Sgirish iocp->ioc_rval = 0; 240344961713Sgirish 240444961713Sgirish /* Tack on the null */ 240544961713Sgirish err = nxge_mk_mblk_tail_space(mp1, &mp2, 1); 240644961713Sgirish if (!err) { 240744961713Sgirish *mp2->b_wptr++ = '\0'; 240844961713Sgirish size_out = msgdsize(mp1); 240944961713Sgirish excess = size_out - avail; 241044961713Sgirish if (excess > 0) { 241144961713Sgirish iocp->ioc_rval = (int)size_out; 241244961713Sgirish size_out -= excess; 241344961713Sgirish (void) adjmsg(mp1, -(excess + 1)); 241444961713Sgirish err = nxge_mk_mblk_tail_space( 241544961713Sgirish mp1, &mp2, 1); 241644961713Sgirish if (!err) 241744961713Sgirish *mp2->b_wptr++ = '\0'; 241844961713Sgirish else 241944961713Sgirish size_out = 0; 242044961713Sgirish } 242144961713Sgirish } else 242244961713Sgirish size_out = 0; 242344961713Sgirish iocp->ioc_count = size_out; 242444961713Sgirish } 242544961713Sgirish break; 242644961713Sgirish 242744961713Sgirish case ND_SET: 242844961713Sgirish if (valp) { 242944961713Sgirish if (nde->nde_set_pfi) { 243044961713Sgirish err = (*nde->nde_set_pfi)(nxgep, q, mp1, valp, 243144961713Sgirish nde->nde_data); 243244961713Sgirish iocp->ioc_count = 0; 243344961713Sgirish freemsg(mp1); 243444961713Sgirish mp->b_cont = NULL; 243544961713Sgirish } 243644961713Sgirish } 243744961713Sgirish break; 243844961713Sgirish 243944961713Sgirish default: 244044961713Sgirish break; 244144961713Sgirish } 244244961713Sgirish iocp->ioc_error = err; 244344961713Sgirish mp->b_datap->db_type = M_IOCACK; 244444961713Sgirish return (B_TRUE); 244544961713Sgirish } 244644961713Sgirish 244744961713Sgirish /* ARGSUSED */ 244844961713Sgirish int 244944961713Sgirish nxge_nd_get_names(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t param) 245044961713Sgirish { 2451a3c5bd6dSspeer ND *nd; 2452a3c5bd6dSspeer NDE *nde; 2453a3c5bd6dSspeer char *rwtag; 2454a3c5bd6dSspeer boolean_t get_ok, set_ok; 2455a3c5bd6dSspeer size_t param_len; 2456a3c5bd6dSspeer int status = 0; 245744961713Sgirish 245844961713Sgirish nd = (ND *)param; 245944961713Sgirish if (!nd) 246044961713Sgirish return (ENOENT); 246144961713Sgirish 246244961713Sgirish for (nde = nd->nd_tbl; nde->nde_name; nde++) { 246344961713Sgirish get_ok = (nde->nde_get_pfi != nxge_get_default) && 246444961713Sgirish (nde->nde_get_pfi != NULL); 246544961713Sgirish set_ok = (nde->nde_set_pfi != nxge_set_default) && 246644961713Sgirish (nde->nde_set_pfi != NULL); 246744961713Sgirish if (get_ok) { 246844961713Sgirish if (set_ok) 246944961713Sgirish rwtag = "read and write"; 247044961713Sgirish else 247144961713Sgirish rwtag = "read only"; 247244961713Sgirish } else if (set_ok) 247344961713Sgirish rwtag = "write only"; 247444961713Sgirish else { 247544961713Sgirish continue; 247644961713Sgirish } 247744961713Sgirish param_len = strlen(rwtag); 247844961713Sgirish param_len += strlen(nde->nde_name); 247944961713Sgirish param_len += 4; 248044961713Sgirish 248144961713Sgirish (void) mi_mpprintf(mp, "%s (%s)", nde->nde_name, rwtag); 248244961713Sgirish } 248344961713Sgirish return (status); 248444961713Sgirish } 248544961713Sgirish 248644961713Sgirish /* ARGSUSED */ 248744961713Sgirish int 248844961713Sgirish nxge_get_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t data) 248944961713Sgirish { 249044961713Sgirish return (EACCES); 249144961713Sgirish } 249244961713Sgirish 249344961713Sgirish /* ARGSUSED */ 249444961713Sgirish int 249544961713Sgirish nxge_set_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, char *value, 2496a3c5bd6dSspeer caddr_t data) 249744961713Sgirish { 249844961713Sgirish return (EACCES); 249944961713Sgirish } 250044961713Sgirish 250144961713Sgirish void 250244961713Sgirish nxge_param_ioctl(p_nxge_t nxgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 250344961713Sgirish { 250444961713Sgirish int cmd; 250544961713Sgirish int status = B_FALSE; 250644961713Sgirish 250744961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_ioctl")); 250844961713Sgirish cmd = iocp->ioc_cmd; 2509a3c5bd6dSspeer 251044961713Sgirish switch (cmd) { 251144961713Sgirish default: 251244961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, 251344961713Sgirish "nxge_param_ioctl: bad cmd 0x%0x", cmd)); 251444961713Sgirish break; 251544961713Sgirish 251644961713Sgirish case ND_GET: 251744961713Sgirish case ND_SET: 251844961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, 251944961713Sgirish "nxge_param_ioctl: cmd 0x%0x", cmd)); 252044961713Sgirish if (!nxge_nd_getset(nxgep, wq, nxgep->param_list, mp)) { 252144961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, 252244961713Sgirish "false ret from nxge_nd_getset")); 252344961713Sgirish break; 252444961713Sgirish } 252544961713Sgirish status = B_TRUE; 252644961713Sgirish break; 252744961713Sgirish } 252844961713Sgirish 252944961713Sgirish if (status) { 253044961713Sgirish qreply(wq, mp); 253144961713Sgirish } else { 253244961713Sgirish miocnak(wq, mp, 0, EINVAL); 253344961713Sgirish } 253444961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_ioctl")); 253544961713Sgirish } 253644961713Sgirish 253744961713Sgirish /* ARGSUSED */ 253844961713Sgirish static boolean_t 253944961713Sgirish nxge_param_link_update(p_nxge_t nxgep) 254044961713Sgirish { 254144961713Sgirish p_nxge_param_t param_arr; 254244961713Sgirish nxge_param_index_t i; 254344961713Sgirish boolean_t update_xcvr; 254444961713Sgirish boolean_t update_dev; 254544961713Sgirish int instance; 254644961713Sgirish boolean_t status = B_TRUE; 254744961713Sgirish 254844961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_link_update")); 254944961713Sgirish 255044961713Sgirish param_arr = nxgep->param_arr; 255144961713Sgirish instance = nxgep->instance; 255244961713Sgirish update_xcvr = B_FALSE; 255344961713Sgirish for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) { 255444961713Sgirish update_xcvr |= param_arr[i].value; 255544961713Sgirish } 255644961713Sgirish 255744961713Sgirish if (update_xcvr) { 255844961713Sgirish update_xcvr = B_FALSE; 255944961713Sgirish for (i = param_autoneg; i < param_enable_ipg0; i++) { 256044961713Sgirish update_xcvr |= 256144961713Sgirish (param_arr[i].value != param_arr[i].old_value); 256244961713Sgirish param_arr[i].old_value = param_arr[i].value; 256344961713Sgirish } 256444961713Sgirish if (update_xcvr) { 256544961713Sgirish RW_ENTER_WRITER(&nxgep->filter_lock); 256644961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 256744961713Sgirish (void) nxge_link_init(nxgep); 256844961713Sgirish (void) nxge_mac_init(nxgep); 256944961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 257044961713Sgirish RW_EXIT(&nxgep->filter_lock); 257144961713Sgirish } 257244961713Sgirish } else { 257344961713Sgirish cmn_err(CE_WARN, " Last setting will leave nxge%d with " 257444961713Sgirish " no link capabilities.", instance); 257544961713Sgirish cmn_err(CE_WARN, " Restoring previous setting."); 257644961713Sgirish for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) 257744961713Sgirish param_arr[i].value = param_arr[i].old_value; 257844961713Sgirish } 2579a3c5bd6dSspeer 258044961713Sgirish update_dev = B_FALSE; 258144961713Sgirish 258244961713Sgirish if (update_dev) { 258344961713Sgirish RW_ENTER_WRITER(&nxgep->filter_lock); 258444961713Sgirish (void) nxge_rx_mac_disable(nxgep); 258544961713Sgirish (void) nxge_tx_mac_disable(nxgep); 258644961713Sgirish (void) nxge_tx_mac_enable(nxgep); 258744961713Sgirish (void) nxge_rx_mac_enable(nxgep); 258844961713Sgirish RW_EXIT(&nxgep->filter_lock); 258944961713Sgirish } 259044961713Sgirish 259144961713Sgirish nxge_param_hw_update_exit: 259244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 259344961713Sgirish "<== nxge_param_link_update status = 0x%08x", status)); 259444961713Sgirish return (status); 259544961713Sgirish } 2596