144961713Sgirish /* 244961713Sgirish * CDDL HEADER START 344961713Sgirish * 444961713Sgirish * The contents of this file are subject to the terms of the 544961713Sgirish * Common Development and Distribution License (the "License"). 644961713Sgirish * You may not use this file except in compliance with the License. 744961713Sgirish * 844961713Sgirish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 944961713Sgirish * or http://www.opensolaris.org/os/licensing. 1044961713Sgirish * See the License for the specific language governing permissions 1144961713Sgirish * and limitations under the License. 1244961713Sgirish * 1344961713Sgirish * When distributing Covered Code, include this CDDL HEADER in each 1444961713Sgirish * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1544961713Sgirish * If applicable, add the following below this CDDL HEADER, with the 1644961713Sgirish * fields enclosed by brackets "[]" replaced with your own identifying 1744961713Sgirish * information: Portions Copyright [yyyy] [name of copyright owner] 1844961713Sgirish * 1944961713Sgirish * CDDL HEADER END 2044961713Sgirish */ 2144961713Sgirish /* 22a3c5bd6dSspeer * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 2344961713Sgirish * Use is subject to license terms. 2444961713Sgirish */ 2544961713Sgirish 2644961713Sgirish #pragma ident "%Z%%M% %I% %E% SMI" 2744961713Sgirish 2844961713Sgirish #include <sys/nxge/nxge_impl.h> 2944961713Sgirish #include <inet/common.h> 3044961713Sgirish #include <inet/mi.h> 3144961713Sgirish #include <inet/nd.h> 3244961713Sgirish 3344961713Sgirish extern uint64_t npi_debug_level; 3444961713Sgirish 35a3c5bd6dSspeer #define NXGE_PARAM_MAC_RW \ 36a3c5bd6dSspeer NXGE_PARAM_RW | NXGE_PARAM_MAC | \ 3744961713Sgirish NXGE_PARAM_NDD_WR_OK | NXGE_PARAM_READ_PROP 3844961713Sgirish 39a3c5bd6dSspeer #define NXGE_PARAM_MAC_DONT_SHOW \ 40a3c5bd6dSspeer NXGE_PARAM_RW | NXGE_PARAM_MAC | NXGE_PARAM_DONT_SHOW 4144961713Sgirish 42a3c5bd6dSspeer #define NXGE_PARAM_RXDMA_RW \ 43a3c5bd6dSspeer NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_NDD_WR_OK | \ 44a3c5bd6dSspeer NXGE_PARAM_READ_PROP 4544961713Sgirish 46a3c5bd6dSspeer #define NXGE_PARAM_RXDMA_RWC \ 47a3c5bd6dSspeer NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_INIT_ONLY | \ 48a3c5bd6dSspeer NXGE_PARAM_READ_PROP 4944961713Sgirish 50a3c5bd6dSspeer #define NXGE_PARAM_L2CLASS_CFG \ 51a3c5bd6dSspeer NXGE_PARAM_RW | NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_READ_PROP | \ 52a3c5bd6dSspeer NXGE_PARAM_NDD_WR_OK 5344961713Sgirish 54a3c5bd6dSspeer #define NXGE_PARAM_CLASS_RWS \ 55a3c5bd6dSspeer NXGE_PARAM_RWS | NXGE_PARAM_READ_PROP 5644961713Sgirish 5744961713Sgirish #define NXGE_PARAM_ARRAY_INIT_SIZE 0x20ULL 5844961713Sgirish 5944961713Sgirish #define SET_RX_INTR_TIME_DISABLE 0 6044961713Sgirish #define SET_RX_INTR_TIME_ENABLE 1 6144961713Sgirish #define SET_RX_INTR_PKTS 2 6244961713Sgirish 6344961713Sgirish #define BASE_ANY 0 64a3c5bd6dSspeer #define BASE_BINARY 2 6544961713Sgirish #define BASE_HEX 16 6644961713Sgirish #define BASE_DECIMAL 10 6744961713Sgirish #define ALL_FF_64 0xFFFFFFFFFFFFFFFFULL 6844961713Sgirish #define ALL_FF_32 0xFFFFFFFFUL 6944961713Sgirish 7044961713Sgirish #define NXGE_NDD_INFODUMP_BUFF_SIZE 2048 /* is 2k enough? */ 7144961713Sgirish #define NXGE_NDD_INFODUMP_BUFF_8K 8192 7244961713Sgirish #define NXGE_NDD_INFODUMP_BUFF_16K 0x2000 7344961713Sgirish #define NXGE_NDD_INFODUMP_BUFF_64K 0x8000 7444961713Sgirish 7544961713Sgirish #define PARAM_OUTOF_RANGE(vptr, eptr, rval, pa) \ 7644961713Sgirish ((vptr == eptr) || (rval < pa->minimum) || (rval > pa->maximum)) 7744961713Sgirish 7844961713Sgirish #define ADVANCE_PRINT_BUFFER(pmp, plen, rlen) { \ 7944961713Sgirish ((mblk_t *)pmp)->b_wptr += plen; \ 8044961713Sgirish rlen -= plen; \ 81a3c5bd6dSspeer } 8244961713Sgirish 8344961713Sgirish static int nxge_param_rx_intr_pkts(p_nxge_t, queue_t *, 84a3c5bd6dSspeer mblk_t *, char *, caddr_t); 8544961713Sgirish static int nxge_param_rx_intr_time(p_nxge_t, queue_t *, 86a3c5bd6dSspeer mblk_t *, char *, caddr_t); 8744961713Sgirish static int nxge_param_set_mac(p_nxge_t, queue_t *, 88a3c5bd6dSspeer mblk_t *, char *, caddr_t); 8944961713Sgirish static int nxge_param_set_port_rdc(p_nxge_t, queue_t *, 90a3c5bd6dSspeer mblk_t *, char *, caddr_t); 9144961713Sgirish static int nxge_param_set_grp_rdc(p_nxge_t, queue_t *, 92a3c5bd6dSspeer mblk_t *, char *, caddr_t); 9344961713Sgirish static int nxge_param_set_ether_usr(p_nxge_t, 94a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 9544961713Sgirish static int nxge_param_set_ip_usr(p_nxge_t, 96a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 9744961713Sgirish static int nxge_param_set_ip_opt(p_nxge_t, 98a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 9944961713Sgirish static int nxge_param_set_vlan_rdcgrp(p_nxge_t, 100a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 10144961713Sgirish static int nxge_param_set_mac_rdcgrp(p_nxge_t, 102a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 10344961713Sgirish static int nxge_param_fflp_hash_init(p_nxge_t, 104a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 10544961713Sgirish static int nxge_param_llc_snap_enable(p_nxge_t, queue_t *, 106a3c5bd6dSspeer mblk_t *, char *, caddr_t); 10744961713Sgirish static int nxge_param_hash_lookup_enable(p_nxge_t, queue_t *, 108a3c5bd6dSspeer mblk_t *, char *, caddr_t); 10944961713Sgirish static int nxge_param_tcam_enable(p_nxge_t, queue_t *, 110a3c5bd6dSspeer mblk_t *, char *, caddr_t); 111*56d930aeSspeer static int nxge_param_get_fw_ver(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 11244961713Sgirish static int nxge_param_get_rxdma_info(p_nxge_t, queue_t *q, 113a3c5bd6dSspeer p_mblk_t, caddr_t); 11444961713Sgirish static int nxge_param_get_txdma_info(p_nxge_t, queue_t *q, 115a3c5bd6dSspeer p_mblk_t, caddr_t); 11644961713Sgirish static int nxge_param_get_vlan_rdcgrp(p_nxge_t, queue_t *, 117a3c5bd6dSspeer p_mblk_t, caddr_t); 11844961713Sgirish static int nxge_param_get_mac_rdcgrp(p_nxge_t, queue_t *, 119a3c5bd6dSspeer p_mblk_t, caddr_t); 12044961713Sgirish static int nxge_param_get_rxdma_rdcgrp_info(p_nxge_t, queue_t *, 121a3c5bd6dSspeer p_mblk_t, caddr_t); 12244961713Sgirish static int nxge_param_get_ip_opt(p_nxge_t, queue_t *, mblk_t *, caddr_t); 123a3c5bd6dSspeer static int nxge_param_get_mac(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 12444961713Sgirish static int nxge_param_get_debug_flag(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 12544961713Sgirish static int nxge_param_set_nxge_debug_flag(p_nxge_t, queue_t *, mblk_t *, 126a3c5bd6dSspeer char *, caddr_t); 12744961713Sgirish static int nxge_param_set_npi_debug_flag(p_nxge_t, 128a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 12944961713Sgirish static int nxge_param_dump_rdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 13044961713Sgirish static int nxge_param_dump_tdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 13144961713Sgirish static int nxge_param_dump_mac_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 13244961713Sgirish static int nxge_param_dump_ipp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 13344961713Sgirish static int nxge_param_dump_fflp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 13444961713Sgirish static int nxge_param_dump_vlan_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 13544961713Sgirish static int nxge_param_dump_rdc_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 13644961713Sgirish static int nxge_param_dump_ptrs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 13744961713Sgirish static boolean_t nxge_param_link_update(p_nxge_t); 13844961713Sgirish 13944961713Sgirish /* 14044961713Sgirish * Global array of Neptune changable parameters. 14144961713Sgirish * This array is initialized to correspond to the default 14244961713Sgirish * Neptune 4 port configuration. This array would be copied 14344961713Sgirish * into each port's parameter structure and modifed per 14444961713Sgirish * fcode and nxge.conf configuration. Later, the parameters are 14544961713Sgirish * exported to ndd to display and run-time configuration (at least 14644961713Sgirish * some of them). 14744961713Sgirish * 14844961713Sgirish */ 14944961713Sgirish 150a3c5bd6dSspeer static nxge_param_t nxge_param_arr[] = { 151a3c5bd6dSspeer /* 152a3c5bd6dSspeer * min max value old hw-name conf-name 153a3c5bd6dSspeer */ 154a3c5bd6dSspeer { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 155a3c5bd6dSspeer 0, 999, 1000, 0, "instance", "instance"}, 156a3c5bd6dSspeer 157a3c5bd6dSspeer { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 158a3c5bd6dSspeer 0, 999, 1000, 0, "main-instance", "main_instance"}, 159a3c5bd6dSspeer 160a3c5bd6dSspeer { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 161a3c5bd6dSspeer 0, 3, 0, 0, "function-number", "function_number"}, 162a3c5bd6dSspeer 163a3c5bd6dSspeer /* Partition Id */ 164a3c5bd6dSspeer { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 165a3c5bd6dSspeer 0, 8, 0, 0, "partition-id", "partition_id"}, 166a3c5bd6dSspeer 167a3c5bd6dSspeer /* Read Write Permission Mode */ 168a3c5bd6dSspeer { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 169a3c5bd6dSspeer 0, 2, 0, 0, "read-write-mode", "read_write_mode"}, 170a3c5bd6dSspeer 171*56d930aeSspeer { nxge_param_get_fw_ver, NULL, NXGE_PARAM_READ, 172*56d930aeSspeer 0, 32, 0, 0, "version", "fw_version"}, 173*56d930aeSspeer 174a3c5bd6dSspeer /* hw cfg types */ 175a3c5bd6dSspeer /* control the DMA config of Neptune/NIU */ 176a3c5bd6dSspeer { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 177a3c5bd6dSspeer CFG_DEFAULT, CFG_CUSTOM, CFG_DEFAULT, CFG_DEFAULT, 178a3c5bd6dSspeer "niu-cfg-type", "niu_cfg_type"}, 179a3c5bd6dSspeer 180a3c5bd6dSspeer /* control the TXDMA config of the Port controlled by tx-quick-cfg */ 181a3c5bd6dSspeer { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 182a3c5bd6dSspeer CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT, 183a3c5bd6dSspeer "tx-qcfg-type", "tx_qcfg_type"}, 184a3c5bd6dSspeer 185a3c5bd6dSspeer /* control the RXDMA config of the Port controlled by rx-quick-cfg */ 186a3c5bd6dSspeer { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 187a3c5bd6dSspeer CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT, 188a3c5bd6dSspeer "rx-qcfg-type", "rx_qcfg_type"}, 189a3c5bd6dSspeer 190a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, 191a3c5bd6dSspeer NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 192a3c5bd6dSspeer 0, 1, 0, 0, "master-cfg-enable", "master_cfg_enable"}, 193a3c5bd6dSspeer 194a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, 195a3c5bd6dSspeer NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 196a3c5bd6dSspeer 0, 1, 0, 0, "master-cfg-value", "master_cfg_value"}, 197a3c5bd6dSspeer 198a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 199a3c5bd6dSspeer 0, 1, 1, 1, "adv-autoneg-cap", "adv_autoneg_cap"}, 200a3c5bd6dSspeer 201a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 202a3c5bd6dSspeer 0, 1, 1, 1, "adv-10gfdx-cap", "adv_10gfdx_cap"}, 203a3c5bd6dSspeer 204a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 205a3c5bd6dSspeer 0, 1, 0, 0, "adv-10ghdx-cap", "adv_10ghdx_cap"}, 206a3c5bd6dSspeer 207a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 208a3c5bd6dSspeer 0, 1, 1, 1, "adv-1000fdx-cap", "adv_1000fdx_cap"}, 209a3c5bd6dSspeer 210a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 211a3c5bd6dSspeer 0, 1, 0, 0, "adv-1000hdx-cap", "adv_1000hdx_cap"}, 212a3c5bd6dSspeer 213a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 214a3c5bd6dSspeer 0, 1, 0, 0, "adv-100T4-cap", "adv_100T4_cap"}, 215a3c5bd6dSspeer 216a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 217a3c5bd6dSspeer 0, 1, 1, 1, "adv-100fdx-cap", "adv_100fdx_cap"}, 218a3c5bd6dSspeer 219a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 220a3c5bd6dSspeer 0, 1, 0, 0, "adv-100hdx-cap", "adv_100hdx_cap"}, 221a3c5bd6dSspeer 222a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 223a3c5bd6dSspeer 0, 1, 1, 1, "adv-10fdx-cap", "adv_10fdx_cap"}, 224a3c5bd6dSspeer 225a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 226a3c5bd6dSspeer 0, 1, 0, 0, "adv-10hdx-cap", "adv_10hdx_cap"}, 227a3c5bd6dSspeer 228a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 229a3c5bd6dSspeer 0, 1, 0, 0, "adv-asmpause-cap", "adv_asmpause_cap"}, 230a3c5bd6dSspeer 231a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 232a3c5bd6dSspeer 0, 1, 0, 0, "adv-pause-cap", "adv_pause_cap"}, 233a3c5bd6dSspeer 234a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 235a3c5bd6dSspeer 0, 1, 0, 0, "use-int-xcvr", "use_int_xcvr"}, 236a3c5bd6dSspeer 237a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 238a3c5bd6dSspeer 0, 1, 1, 1, "enable-ipg0", "enable_ipg0"}, 239a3c5bd6dSspeer 240a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 241a3c5bd6dSspeer 0, 255, 8, 8, "ipg0", "ipg0"}, 242a3c5bd6dSspeer 243a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 244a3c5bd6dSspeer 0, 255, 8, 8, "ipg1", "ipg1"}, 245a3c5bd6dSspeer 246a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 247a3c5bd6dSspeer 0, 255, 4, 4, "ipg2", "ipg2"}, 248a3c5bd6dSspeer 249a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 250a3c5bd6dSspeer 0, 1, 0, 0, "accept-jumbo", "accept_jumbo"}, 251a3c5bd6dSspeer 252a3c5bd6dSspeer /* Transmit DMA channels */ 253a3c5bd6dSspeer { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_READ_PROP, 254a3c5bd6dSspeer 0, 3, 0, 0, "tx-dma-weight", "tx_dma_weight"}, 255a3c5bd6dSspeer 256a3c5bd6dSspeer { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_READ_PROP, 257a3c5bd6dSspeer 0, 31, 0, 0, "tx-dma-channels-begin", "tx_dma_channels_begin"}, 258a3c5bd6dSspeer 259a3c5bd6dSspeer { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_READ_PROP, 260a3c5bd6dSspeer 0, 32, 0, 0, "tx-dma-channels", "tx_dma_channels"}, 261a3c5bd6dSspeer { nxge_param_get_txdma_info, NULL, 262a3c5bd6dSspeer NXGE_PARAM_READ | NXGE_PARAM_READ_PROP, 263a3c5bd6dSspeer 0, 32, 0, 0, "tx-dma-info", "tx_dma_info"}, 264a3c5bd6dSspeer 265a3c5bd6dSspeer /* Receive DMA channels */ 266a3c5bd6dSspeer { nxge_param_get_generic, NULL, 267a3c5bd6dSspeer NXGE_PARAM_READ | NXGE_PARAM_READ_PROP, 268a3c5bd6dSspeer 0, 31, 0, 0, "rx-dma-channels-begin", "rx_dma_channels_begin"}, 269a3c5bd6dSspeer 270a3c5bd6dSspeer { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_READ_PROP, 271a3c5bd6dSspeer 0, 32, 0, 0, "rx-dma-channels", "rx_dma_channels"}, 272a3c5bd6dSspeer 273a3c5bd6dSspeer { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_READ_PROP, 274a3c5bd6dSspeer 0, 65535, PT_DRR_WT_DEFAULT_10G, 0, 275a3c5bd6dSspeer "rx-drr-weight", "rx_drr_weight"}, 276a3c5bd6dSspeer 277a3c5bd6dSspeer { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_READ_PROP, 278a3c5bd6dSspeer 0, 1, 1, 0, "rx-full-header", "rx_full_header"}, 279a3c5bd6dSspeer 280a3c5bd6dSspeer { nxge_param_get_rxdma_info, NULL, NXGE_PARAM_READ, 281a3c5bd6dSspeer 0, 32, 0, 0, "rx-dma-info", "rx_dma_info"}, 282a3c5bd6dSspeer 283a3c5bd6dSspeer { nxge_param_get_rxdma_info, NULL, 284a3c5bd6dSspeer NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 285a3c5bd6dSspeer NXGE_RBR_RBB_MIN, NXGE_RBR_RBB_MAX, NXGE_RBR_RBB_DEFAULT, 0, 286a3c5bd6dSspeer "rx-rbr-size", "rx_rbr_size"}, 287a3c5bd6dSspeer 288a3c5bd6dSspeer { nxge_param_get_rxdma_info, NULL, 289a3c5bd6dSspeer NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 290a3c5bd6dSspeer NXGE_RCR_MIN, NXGE_RCR_MAX, NXGE_RCR_DEFAULT, 0, 291a3c5bd6dSspeer "rx-rcr-size", "rx_rcr_size"}, 292a3c5bd6dSspeer 293a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_port_rdc, NXGE_PARAM_RXDMA_RW, 294a3c5bd6dSspeer 0, 15, 0, 0, "default-port-rdc", "default_port_rdc"}, 295a3c5bd6dSspeer 296a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_rx_intr_time, NXGE_PARAM_RXDMA_RW, 297a3c5bd6dSspeer NXGE_RDC_RCR_TIMEOUT_MIN, NXGE_RDC_RCR_TIMEOUT_MAX, 298a3c5bd6dSspeer RXDMA_RCR_TO_DEFAULT, 0, "rxdma-intr-time", "rxdma_intr_time"}, 299a3c5bd6dSspeer 300a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_rx_intr_pkts, NXGE_PARAM_RXDMA_RW, 301a3c5bd6dSspeer NXGE_RDC_RCR_THRESHOLD_MIN, NXGE_RDC_RCR_THRESHOLD_MAX, 302a3c5bd6dSspeer RXDMA_RCR_PTHRES_DEFAULT, 0, 303a3c5bd6dSspeer "rxdma-intr-pkts", "rxdma_intr_pkts"}, 304a3c5bd6dSspeer 305a3c5bd6dSspeer { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP, 306a3c5bd6dSspeer 0, 8, 0, 0, "rx-rdc-grps-begin", "rx_rdc_grps_begin"}, 307a3c5bd6dSspeer 308a3c5bd6dSspeer { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP, 309a3c5bd6dSspeer 0, 8, 0, 0, "rx-rdc-grps", "rx_rdc_grps"}, 310a3c5bd6dSspeer 311a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_grp_rdc, NXGE_PARAM_RXDMA_RW, 312a3c5bd6dSspeer 0, 15, 0, 0, "default-grp0-rdc", "default_grp0_rdc"}, 313a3c5bd6dSspeer 314a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_grp_rdc, NXGE_PARAM_RXDMA_RW, 315a3c5bd6dSspeer 0, 15, 2, 0, "default-grp1-rdc", "default_grp1_rdc"}, 316a3c5bd6dSspeer 317a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_grp_rdc, NXGE_PARAM_RXDMA_RW, 318a3c5bd6dSspeer 0, 15, 4, 0, "default-grp2-rdc", "default_grp2_rdc"}, 319a3c5bd6dSspeer 320a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_grp_rdc, NXGE_PARAM_RXDMA_RW, 321a3c5bd6dSspeer 0, 15, 6, 0, "default-grp3-rdc", "default_grp3_rdc"}, 322a3c5bd6dSspeer 323a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_grp_rdc, NXGE_PARAM_RXDMA_RW, 324a3c5bd6dSspeer 0, 15, 8, 0, "default-grp4-rdc", "default_grp4_rdc"}, 325a3c5bd6dSspeer 326a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_grp_rdc, NXGE_PARAM_RXDMA_RW, 327a3c5bd6dSspeer 0, 15, 10, 0, "default-grp5-rdc", "default_grp5_rdc"}, 328a3c5bd6dSspeer 329a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_grp_rdc, NXGE_PARAM_RXDMA_RW, 330a3c5bd6dSspeer 0, 15, 12, 0, "default-grp6-rdc", "default_grp6_rdc"}, 331a3c5bd6dSspeer 332a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_grp_rdc, NXGE_PARAM_RXDMA_RW, 333a3c5bd6dSspeer 0, 15, 14, 0, "default-grp7-rdc", "default_grp7_rdc"}, 334a3c5bd6dSspeer 335a3c5bd6dSspeer { nxge_param_get_rxdma_rdcgrp_info, NULL, 336a3c5bd6dSspeer NXGE_PARAM_READ | NXGE_PARAM_CMPLX, 337a3c5bd6dSspeer 0, 8, 0, 0, "rdc-groups-info", "rdc_groups_info"}, 338a3c5bd6dSspeer 339a3c5bd6dSspeer /* Logical device groups */ 340a3c5bd6dSspeer { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 341a3c5bd6dSspeer 0, 63, 0, 0, "start-ldg", "start_ldg"}, 342a3c5bd6dSspeer 343a3c5bd6dSspeer { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 344a3c5bd6dSspeer 0, 64, 0, 0, "max-ldg", "max_ldg" }, 345a3c5bd6dSspeer 346a3c5bd6dSspeer /* MAC table information */ 347a3c5bd6dSspeer { nxge_param_get_mac_rdcgrp, nxge_param_set_mac_rdcgrp, 348a3c5bd6dSspeer NXGE_PARAM_L2CLASS_CFG, 349a3c5bd6dSspeer 0, 31, 0, 0, "mac-2rdc-grp", "mac_2rdc_grp"}, 350a3c5bd6dSspeer 351a3c5bd6dSspeer /* VLAN table information */ 352a3c5bd6dSspeer { nxge_param_get_vlan_rdcgrp, nxge_param_set_vlan_rdcgrp, 353a3c5bd6dSspeer NXGE_PARAM_L2CLASS_CFG, 354a3c5bd6dSspeer 0, 31, 0, 0, "vlan-2rdc-grp", "vlan_2rdc_grp"}, 355a3c5bd6dSspeer 356a3c5bd6dSspeer { nxge_param_get_generic, NULL, 357a3c5bd6dSspeer NXGE_PARAM_READ_PROP | NXGE_PARAM_READ | NXGE_PARAM_PROP_ARR32, 358a3c5bd6dSspeer 0, 0x0ffff, 0x0ffff, 0, "fcram-part-cfg", "fcram_part_cfg"}, 359a3c5bd6dSspeer 360a3c5bd6dSspeer { nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS, 361a3c5bd6dSspeer 0, 0x10, 0xa, 0, "fcram-access-ratio", "fcram_access_ratio"}, 362a3c5bd6dSspeer 363a3c5bd6dSspeer { nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS, 364a3c5bd6dSspeer 0, 0x10, 0xa, 0, "tcam-access-ratio", "tcam_access_ratio"}, 365a3c5bd6dSspeer 366a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_tcam_enable, 367a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS, 368a3c5bd6dSspeer 0, 0x1, 0x0, 0, "tcam-enable", "tcam_enable"}, 369a3c5bd6dSspeer 370a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_hash_lookup_enable, 371a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS, 372a3c5bd6dSspeer 0, 0x01, 0x0, 0, "hash-lookup-enable", "hash_lookup_enable"}, 373a3c5bd6dSspeer 374a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_llc_snap_enable, 375a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS, 376a3c5bd6dSspeer 0, 0x01, 0x01, 0, "llc-snap-enable", "llc_snap_enable"}, 377a3c5bd6dSspeer 378a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_fflp_hash_init, 379a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS, 380a3c5bd6dSspeer 0, ALL_FF_32, ALL_FF_32, 0, "h1-init-value", "h1_init_value"}, 381a3c5bd6dSspeer 382a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_fflp_hash_init, 383a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS, 384a3c5bd6dSspeer 0, 0x0ffff, 0x0ffff, 0, "h2-init-value", "h2_init_value"}, 385a3c5bd6dSspeer 386a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ether_usr, 387a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 388a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 389a3c5bd6dSspeer "class-cfg-ether-usr1", "class_cfg_ether_usr1"}, 390a3c5bd6dSspeer 391a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ether_usr, 392a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 393a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 394a3c5bd6dSspeer "class-cfg-ether-usr2", "class_cfg_ether_usr2"}, 395a3c5bd6dSspeer 396a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ip_usr, 397a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 398a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 399a3c5bd6dSspeer "class-cfg-ip-usr4", "class_cfg_ip_usr4"}, 400a3c5bd6dSspeer 401a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ip_usr, 402a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 403a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 404a3c5bd6dSspeer "class-cfg-ip-usr5", "class_cfg_ip_usr5"}, 405a3c5bd6dSspeer 406a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ip_usr, 407a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 408a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 409a3c5bd6dSspeer "class-cfg-ip-usr6", "class_cfg_ip_usr6"}, 410a3c5bd6dSspeer 411a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ip_usr, 412a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 413a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 414a3c5bd6dSspeer "class-cfg-ip-usr7", "class_cfg_ip_usr7"}, 415a3c5bd6dSspeer 416a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 417a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 418a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 419a3c5bd6dSspeer "class-opt-ip-usr4", "class_opt_ip_usr4"}, 420a3c5bd6dSspeer 421a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 422a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 423a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 424a3c5bd6dSspeer "class-opt-ip-usr5", "class_opt_ip_usr5"}, 425a3c5bd6dSspeer 426a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 427a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 428a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 429a3c5bd6dSspeer "class-opt-ip-usr6", "class_opt_ip_usr6"}, 430a3c5bd6dSspeer 431a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 432a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 433a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 434a3c5bd6dSspeer "class-opt-ip-usr7", "class_opt_ip_usr7"}, 435a3c5bd6dSspeer 436a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 437a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS, 438a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 439a3c5bd6dSspeer "class-opt-ipv4-tcp", "class_opt_ipv4_tcp"}, 440a3c5bd6dSspeer 441a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 442a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS, 443a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 444a3c5bd6dSspeer "class-opt-ipv4-udp", "class_opt_ipv4_udp"}, 445a3c5bd6dSspeer 446a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 447a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS, 448a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 449a3c5bd6dSspeer "class-opt-ipv4-ah", "class_opt_ipv4_ah"}, 450a3c5bd6dSspeer 451a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 452a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS, 453a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 454a3c5bd6dSspeer "class-opt-ipv4-sctp", "class_opt_ipv4_sctp"}, 455a3c5bd6dSspeer 456a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 457a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 458a3c5bd6dSspeer "class-opt-ipv6-tcp", "class_opt_ipv6_tcp"}, 459a3c5bd6dSspeer 460a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 461a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 462a3c5bd6dSspeer "class-opt-ipv6-udp", "class_opt_ipv6_udp"}, 463a3c5bd6dSspeer 464a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 465a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 466a3c5bd6dSspeer "class-opt-ipv6-ah", "class_opt_ipv6_ah"}, 467a3c5bd6dSspeer 468a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 469a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 470a3c5bd6dSspeer "class-opt-ipv6-sctp", "class_opt_ipv6_sctp"}, 471a3c5bd6dSspeer 472a3c5bd6dSspeer { nxge_param_get_debug_flag, nxge_param_set_nxge_debug_flag, 473a3c5bd6dSspeer NXGE_PARAM_RW, 474a3c5bd6dSspeer 0ULL, ALL_FF_64, 0ULL, 0ULL, 475a3c5bd6dSspeer "nxge-debug-flag", "nxge_debug_flag"}, 476a3c5bd6dSspeer 477a3c5bd6dSspeer { nxge_param_get_debug_flag, nxge_param_set_npi_debug_flag, 478a3c5bd6dSspeer NXGE_PARAM_RW, 479a3c5bd6dSspeer 0ULL, ALL_FF_64, 0ULL, 0ULL, 480a3c5bd6dSspeer "npi-debug-flag", "npi_debug_flag"}, 481a3c5bd6dSspeer 482a3c5bd6dSspeer { nxge_param_dump_tdc, NULL, NXGE_PARAM_READ, 483a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "dump-tdc", "dump_tdc"}, 484a3c5bd6dSspeer 485a3c5bd6dSspeer { nxge_param_dump_rdc, NULL, NXGE_PARAM_READ, 486a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "dump-rdc", "dump_rdc"}, 487a3c5bd6dSspeer 488a3c5bd6dSspeer { nxge_param_dump_mac_regs, NULL, NXGE_PARAM_READ, 489a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "dump-mac-regs", "dump_mac_regs"}, 490a3c5bd6dSspeer 491a3c5bd6dSspeer { nxge_param_dump_ipp_regs, NULL, NXGE_PARAM_READ, 492a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "dump-ipp-regs", "dump_ipp_regs"}, 493a3c5bd6dSspeer 494a3c5bd6dSspeer { nxge_param_dump_fflp_regs, NULL, NXGE_PARAM_READ, 495a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, 496a3c5bd6dSspeer "dump-fflp-regs", "dump_fflp_regs"}, 497a3c5bd6dSspeer 498a3c5bd6dSspeer { nxge_param_dump_vlan_table, NULL, NXGE_PARAM_READ, 499a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, 500a3c5bd6dSspeer "dump-vlan-table", "dump_vlan_table"}, 501a3c5bd6dSspeer 502a3c5bd6dSspeer { nxge_param_dump_rdc_table, NULL, NXGE_PARAM_READ, 503a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, 504a3c5bd6dSspeer "dump-rdc-table", "dump_rdc_table"}, 505a3c5bd6dSspeer 506a3c5bd6dSspeer { nxge_param_dump_ptrs, NULL, NXGE_PARAM_READ, 507a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "dump-ptrs", "dump_ptrs"}, 508a3c5bd6dSspeer 509a3c5bd6dSspeer { NULL, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 510a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "end", "end"}, 51144961713Sgirish }; 51244961713Sgirish 51344961713Sgirish extern void *nxge_list; 51444961713Sgirish 51544961713Sgirish void 51644961713Sgirish nxge_get_param_soft_properties(p_nxge_t nxgep) 51744961713Sgirish { 51844961713Sgirish 51944961713Sgirish p_nxge_param_t param_arr; 52044961713Sgirish uint_t prop_len; 52144961713Sgirish int i, j; 522a3c5bd6dSspeer uint32_t param_count; 523a3c5bd6dSspeer uint32_t *int_prop_val; 52444961713Sgirish 52544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, " ==> nxge_get_param_soft_properties")); 52644961713Sgirish 52744961713Sgirish param_arr = nxgep->param_arr; 52844961713Sgirish param_count = nxgep->param_count; 52944961713Sgirish for (i = 0; i < param_count; i++) { 53044961713Sgirish if ((param_arr[i].type & NXGE_PARAM_READ_PROP) == 0) 53144961713Sgirish continue; 53244961713Sgirish if ((param_arr[i].type & NXGE_PARAM_PROP_STR)) 53344961713Sgirish continue; 53444961713Sgirish if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 535a3c5bd6dSspeer (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 53644961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, 537a3c5bd6dSspeer nxgep->dip, 0, param_arr[i].fcode_name, 538a3c5bd6dSspeer (int **)&int_prop_val, 539a3c5bd6dSspeer (uint_t *)&prop_len) 540a3c5bd6dSspeer == DDI_PROP_SUCCESS) { 54144961713Sgirish uint32_t *cfg_value; 54244961713Sgirish uint64_t prop_count; 543a3c5bd6dSspeer 54444961713Sgirish if (prop_len > NXGE_PARAM_ARRAY_INIT_SIZE) 54544961713Sgirish prop_len = NXGE_PARAM_ARRAY_INIT_SIZE; 54644961713Sgirish cfg_value = (uint32_t *)param_arr[i].value; 54744961713Sgirish for (j = 0; j < prop_len; j++) { 54844961713Sgirish cfg_value[j] = int_prop_val[j]; 54944961713Sgirish } 55044961713Sgirish prop_count = prop_len; 55144961713Sgirish param_arr[i].type |= 55244961713Sgirish (prop_count << NXGE_PARAM_ARRAY_CNT_SHIFT); 55344961713Sgirish ddi_prop_free(int_prop_val); 55444961713Sgirish } 55544961713Sgirish continue; 55644961713Sgirish } 55744961713Sgirish 55844961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 559a3c5bd6dSspeer param_arr[i].fcode_name, 560a3c5bd6dSspeer (int **)&int_prop_val, 561a3c5bd6dSspeer &prop_len) == DDI_PROP_SUCCESS) { 56244961713Sgirish if ((*int_prop_val >= param_arr[i].minimum) && 563a3c5bd6dSspeer (*int_prop_val <= param_arr[i].maximum)) 56444961713Sgirish param_arr[i].value = *int_prop_val; 56544961713Sgirish #ifdef NXGE_DEBUG_ERROR 56644961713Sgirish else { 56744961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL, 568a3c5bd6dSspeer "nxge%d: 'prom' file parameter error\n", 569a3c5bd6dSspeer nxgep->instance)); 57044961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL, 571a3c5bd6dSspeer "Parameter keyword '%s'" 572a3c5bd6dSspeer " is outside valid range\n", 573a3c5bd6dSspeer param_arr[i].name)); 57444961713Sgirish } 57544961713Sgirish #endif 57644961713Sgirish ddi_prop_free(int_prop_val); 57744961713Sgirish } 57844961713Sgirish 57944961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 580a3c5bd6dSspeer param_arr[i].name, 581a3c5bd6dSspeer (int **)&int_prop_val, 582a3c5bd6dSspeer &prop_len) == DDI_PROP_SUCCESS) { 58344961713Sgirish if ((*int_prop_val >= param_arr[i].minimum) && 58444961713Sgirish (*int_prop_val <= param_arr[i].maximum)) 58544961713Sgirish param_arr[i].value = *int_prop_val; 58644961713Sgirish #ifdef NXGE_DEBUG_ERROR 58744961713Sgirish else { 58844961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL, 589a3c5bd6dSspeer "nxge%d: 'conf' file parameter error\n", 590a3c5bd6dSspeer nxgep->instance)); 59144961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL, 592a3c5bd6dSspeer "Parameter keyword '%s'" 593a3c5bd6dSspeer "is outside valid range\n", 594a3c5bd6dSspeer param_arr[i].name)); 59544961713Sgirish } 59644961713Sgirish #endif 59744961713Sgirish ddi_prop_free(int_prop_val); 59844961713Sgirish } 59944961713Sgirish } 60044961713Sgirish } 60144961713Sgirish 60244961713Sgirish static int 60344961713Sgirish nxge_private_param_register(p_nxge_t nxgep, p_nxge_param_t param_arr) 60444961713Sgirish { 60544961713Sgirish int status = B_TRUE; 60644961713Sgirish int channel; 60744961713Sgirish uint8_t grp; 60844961713Sgirish char *prop_name; 60944961713Sgirish char *end; 61044961713Sgirish uint32_t name_chars; 61144961713Sgirish 61244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 613a3c5bd6dSspeer "nxge_private_param_register %s", param_arr->name)); 61444961713Sgirish 61544961713Sgirish if ((param_arr->type & NXGE_PARAM_PRIV) != NXGE_PARAM_PRIV) 61644961713Sgirish return (B_TRUE); 617a3c5bd6dSspeer 61844961713Sgirish prop_name = param_arr->name; 61944961713Sgirish if (param_arr->type & NXGE_PARAM_RXDMA) { 62044961713Sgirish if (strncmp("rxdma_intr", prop_name, 10) == 0) 62144961713Sgirish return (B_TRUE); 62244961713Sgirish name_chars = strlen("default_grp"); 62344961713Sgirish if (strncmp("default_grp", prop_name, name_chars) == 0) { 62444961713Sgirish prop_name += name_chars; 62544961713Sgirish grp = mi_strtol(prop_name, &end, 10); 62644961713Sgirish /* now check if this rdcgrp is in config */ 62744961713Sgirish return (nxge_check_rdcgrp_port_member(nxgep, grp)); 62844961713Sgirish } 62944961713Sgirish name_chars = strlen(prop_name); 63044961713Sgirish if (strncmp("default_port_rdc", prop_name, name_chars) == 0) { 63144961713Sgirish return (B_TRUE); 63244961713Sgirish } 63344961713Sgirish return (B_FALSE); 63444961713Sgirish } 63544961713Sgirish 63644961713Sgirish if (param_arr->type & NXGE_PARAM_TXDMA) { 63744961713Sgirish name_chars = strlen("txdma"); 63844961713Sgirish if (strncmp("txdma", prop_name, name_chars) == 0) { 63944961713Sgirish prop_name += name_chars; 64044961713Sgirish channel = mi_strtol(prop_name, &end, 10); 64144961713Sgirish /* now check if this rdc is in config */ 64244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 64344961713Sgirish " nxge_private_param_register: %d", 64444961713Sgirish channel)); 64544961713Sgirish return (nxge_check_txdma_port_member(nxgep, channel)); 64644961713Sgirish } 64744961713Sgirish return (B_FALSE); 64844961713Sgirish } 64944961713Sgirish 65044961713Sgirish status = B_FALSE; 65144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD2_CTL, "<== nxge_private_param_register")); 65244961713Sgirish 65344961713Sgirish return (status); 65444961713Sgirish } 65544961713Sgirish 65644961713Sgirish void 65744961713Sgirish nxge_setup_param(p_nxge_t nxgep) 65844961713Sgirish { 65944961713Sgirish p_nxge_param_t param_arr; 66044961713Sgirish int i; 66144961713Sgirish pfi_t set_pfi; 66244961713Sgirish 66344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_setup_param")); 664a3c5bd6dSspeer 66544961713Sgirish /* 66644961713Sgirish * Make sure the param_instance is set to a valid device instance. 66744961713Sgirish */ 66844961713Sgirish if (nxge_param_arr[param_instance].value == 1000) 66944961713Sgirish nxge_param_arr[param_instance].value = nxgep->instance; 67044961713Sgirish 67144961713Sgirish param_arr = nxgep->param_arr; 67244961713Sgirish param_arr[param_instance].value = nxgep->instance; 67344961713Sgirish param_arr[param_function_number].value = nxgep->function_num; 67444961713Sgirish 67544961713Sgirish for (i = 0; i < nxgep->param_count; i++) { 67644961713Sgirish if ((param_arr[i].type & NXGE_PARAM_PRIV) && 677a3c5bd6dSspeer (nxge_private_param_register(nxgep, 678a3c5bd6dSspeer ¶m_arr[i]) == B_FALSE)) { 67944961713Sgirish param_arr[i].setf = NULL; 68044961713Sgirish param_arr[i].getf = NULL; 68144961713Sgirish } 68244961713Sgirish 68344961713Sgirish if (param_arr[i].type & NXGE_PARAM_CMPLX) 68444961713Sgirish param_arr[i].setf = NULL; 68544961713Sgirish 68644961713Sgirish if (param_arr[i].type & NXGE_PARAM_DONT_SHOW) { 68744961713Sgirish param_arr[i].setf = NULL; 68844961713Sgirish param_arr[i].getf = NULL; 68944961713Sgirish } 69044961713Sgirish 69144961713Sgirish set_pfi = (pfi_t)param_arr[i].setf; 69244961713Sgirish 693a3c5bd6dSspeer if ((set_pfi) && (param_arr[i].type & NXGE_PARAM_INIT_ONLY)) { 69444961713Sgirish set_pfi = NULL; 69544961713Sgirish } 69644961713Sgirish 697a3c5bd6dSspeer if (!nxge_nd_load(&nxgep->param_list, param_arr[i].name, 698a3c5bd6dSspeer (pfi_t)param_arr[i].getf, set_pfi, 69944961713Sgirish (caddr_t)¶m_arr[i])) { 70044961713Sgirish (void) nxge_nd_free(&nxgep->param_list); 70144961713Sgirish break; 70244961713Sgirish } 70344961713Sgirish } 70444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_setup_param")); 70544961713Sgirish } 70644961713Sgirish 70744961713Sgirish void 70844961713Sgirish nxge_init_param(p_nxge_t nxgep) 70944961713Sgirish { 71044961713Sgirish p_nxge_param_t param_arr; 71144961713Sgirish int i, alloc_size; 71244961713Sgirish uint64_t alloc_count; 71344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_init_param")); 71444961713Sgirish /* 71544961713Sgirish * Make sure the param_instance is set to a valid device instance. 71644961713Sgirish */ 71744961713Sgirish if (nxge_param_arr[param_instance].value == 1000) 71844961713Sgirish nxge_param_arr[param_instance].value = nxgep->instance; 71944961713Sgirish 72044961713Sgirish param_arr = nxgep->param_arr; 72144961713Sgirish if (param_arr == NULL) { 722a3c5bd6dSspeer param_arr = (p_nxge_param_t) 723a3c5bd6dSspeer KMEM_ZALLOC(sizeof (nxge_param_arr), KM_SLEEP); 72444961713Sgirish } 725a3c5bd6dSspeer 72644961713Sgirish for (i = 0; i < sizeof (nxge_param_arr)/sizeof (nxge_param_t); i++) { 72744961713Sgirish param_arr[i] = nxge_param_arr[i]; 72844961713Sgirish if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 72944961713Sgirish (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 73044961713Sgirish alloc_count = NXGE_PARAM_ARRAY_INIT_SIZE; 73144961713Sgirish alloc_size = alloc_count * sizeof (uint64_t); 73244961713Sgirish param_arr[i].value = 73344961713Sgirish (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP); 73444961713Sgirish param_arr[i].old_value = 73544961713Sgirish (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP); 73644961713Sgirish param_arr[i].type |= 73744961713Sgirish (alloc_count << NXGE_PARAM_ARRAY_ALLOC_SHIFT); 73844961713Sgirish } 73944961713Sgirish } 74044961713Sgirish 74144961713Sgirish nxgep->param_arr = param_arr; 74244961713Sgirish nxgep->param_count = sizeof (nxge_param_arr)/sizeof (nxge_param_t); 74344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_init_param: count %d", 744a3c5bd6dSspeer nxgep->param_count)); 74544961713Sgirish } 74644961713Sgirish 74744961713Sgirish void 74844961713Sgirish nxge_destroy_param(p_nxge_t nxgep) 74944961713Sgirish { 75044961713Sgirish int i; 75144961713Sgirish uint64_t free_size, free_count; 75244961713Sgirish 75344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_param")); 754a3c5bd6dSspeer 75544961713Sgirish /* 75644961713Sgirish * Make sure the param_instance is set to a valid device instance. 75744961713Sgirish */ 75844961713Sgirish if (nxge_param_arr[param_instance].value == nxgep->instance) { 75944961713Sgirish for (i = 0; i <= nxge_param_arr[param_instance].maximum; i++) { 76044961713Sgirish if ((ddi_get_soft_state(nxge_list, i) != NULL) && 76144961713Sgirish (i != nxgep->instance)) 76244961713Sgirish break; 76344961713Sgirish } 76444961713Sgirish nxge_param_arr[param_instance].value = i; 76544961713Sgirish } 76644961713Sgirish 76744961713Sgirish if (nxgep->param_list) 76844961713Sgirish nxge_nd_free(&nxgep->param_list); 76944961713Sgirish for (i = 0; i < nxgep->param_count; i++) 77044961713Sgirish if ((nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 77144961713Sgirish (nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 77244961713Sgirish free_count = ((nxgep->param_arr[i].type & 77344961713Sgirish NXGE_PARAM_ARRAY_ALLOC_MASK) >> 77444961713Sgirish NXGE_PARAM_ARRAY_ALLOC_SHIFT); 77544961713Sgirish free_count = NXGE_PARAM_ARRAY_INIT_SIZE; 77644961713Sgirish free_size = sizeof (uint64_t) * free_count; 77744961713Sgirish KMEM_FREE((void *)nxgep->param_arr[i].value, free_size); 77844961713Sgirish KMEM_FREE((void *)nxgep->param_arr[i].old_value, 779a3c5bd6dSspeer free_size); 78044961713Sgirish } 78144961713Sgirish 78244961713Sgirish KMEM_FREE(nxgep->param_arr, sizeof (nxge_param_arr)); 78344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_param")); 78444961713Sgirish } 78544961713Sgirish 78644961713Sgirish /* 78744961713Sgirish * Extracts the value from the 'nxge' parameter array and prints the 78844961713Sgirish * parameter value. cp points to the required parameter. 78944961713Sgirish */ 790a3c5bd6dSspeer 79144961713Sgirish /* ARGSUSED */ 79244961713Sgirish int 79344961713Sgirish nxge_param_get_generic(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 79444961713Sgirish { 79544961713Sgirish p_nxge_param_t pa = (p_nxge_param_t)cp; 79644961713Sgirish 797a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, NDD_CTL, 798a3c5bd6dSspeer "==> nxge_param_get_generic name %s ", pa->name)); 79944961713Sgirish 80044961713Sgirish if (pa->value > 0xffffffff) 801a3c5bd6dSspeer (void) mi_mpprintf(mp, "%x%x", 802a3c5bd6dSspeer (int)(pa->value >> 32), (int)(pa->value & 0xffffffff)); 80344961713Sgirish else 80444961713Sgirish (void) mi_mpprintf(mp, "%x", (int)pa->value); 80544961713Sgirish 80644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_generic")); 80744961713Sgirish return (0); 80844961713Sgirish } 80944961713Sgirish 81044961713Sgirish /* ARGSUSED */ 81144961713Sgirish static int 81244961713Sgirish nxge_param_get_mac(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 81344961713Sgirish { 81444961713Sgirish p_nxge_param_t pa = (p_nxge_param_t)cp; 81544961713Sgirish 81644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac")); 81744961713Sgirish 81844961713Sgirish (void) mi_mpprintf(mp, "%d", (uint32_t)pa->value); 81944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_mac")); 82044961713Sgirish return (0); 82144961713Sgirish } 82244961713Sgirish 823*56d930aeSspeer /* ARGSUSED */ 824*56d930aeSspeer static int 825*56d930aeSspeer nxge_param_get_fw_ver(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 826*56d930aeSspeer { 827*56d930aeSspeer NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_fw_ver")); 828*56d930aeSspeer 829*56d930aeSspeer (void) mi_mpprintf(mp, "Firmware version for nxge%d: %s\n", 830*56d930aeSspeer nxgep->instance, nxgep->vpd_info.ver); 831*56d930aeSspeer 832*56d930aeSspeer NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_fw_ver")); 833*56d930aeSspeer return (0); 834*56d930aeSspeer } 835*56d930aeSspeer 83644961713Sgirish /* ARGSUSED */ 83744961713Sgirish int 83844961713Sgirish nxge_param_get_txdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 83944961713Sgirish { 84044961713Sgirish 84144961713Sgirish uint_t print_len, buf_len; 84244961713Sgirish p_mblk_t np; 84344961713Sgirish int tdc; 84444961713Sgirish 84544961713Sgirish int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 84644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_txdma_info")); 84744961713Sgirish 848a3c5bd6dSspeer (void) mi_mpprintf(mp, "TXDMA Information for Port\t %d \n", 849a3c5bd6dSspeer nxgep->function_num); 85044961713Sgirish 85144961713Sgirish 85244961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 85344961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 85444961713Sgirish return (0); 85544961713Sgirish } 85644961713Sgirish 85744961713Sgirish buf_len = buff_alloc_size; 85844961713Sgirish mp->b_cont = np; 85944961713Sgirish 86044961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 861a3c5bd6dSspeer "Total TDCs\t %d\n", nxgep->ntdc); 86244961713Sgirish 86344961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 86444961713Sgirish buf_len -= print_len; 86544961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 866a3c5bd6dSspeer "TDC\t HW TDC\t\n"); 86744961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 868a3c5bd6dSspeer 86944961713Sgirish buf_len -= print_len; 87044961713Sgirish for (tdc = 0; tdc < nxgep->ntdc; tdc++) { 87144961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 87244961713Sgirish buf_len, "%d\t %d\n", 87344961713Sgirish tdc, nxgep->tdc[tdc]); 87444961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 87544961713Sgirish buf_len -= print_len; 87644961713Sgirish } 877a3c5bd6dSspeer 87844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_txdma_info")); 87944961713Sgirish return (0); 88044961713Sgirish } 88144961713Sgirish 88244961713Sgirish /* ARGSUSED */ 88344961713Sgirish int 88444961713Sgirish nxge_param_get_rxdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 88544961713Sgirish { 886a3c5bd6dSspeer uint_t print_len, buf_len; 887a3c5bd6dSspeer p_mblk_t np; 888a3c5bd6dSspeer int rdc; 88944961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 89044961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 891a3c5bd6dSspeer int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 89244961713Sgirish p_rx_rcr_rings_t rx_rcr_rings; 89344961713Sgirish p_rx_rcr_ring_t *rcr_rings; 89444961713Sgirish p_rx_rbr_rings_t rx_rbr_rings; 89544961713Sgirish p_rx_rbr_ring_t *rbr_rings; 89644961713Sgirish 89744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rxdma_info")); 89844961713Sgirish 899a3c5bd6dSspeer (void) mi_mpprintf(mp, "RXDMA Information for Port\t %d \n", 900a3c5bd6dSspeer nxgep->function_num); 90144961713Sgirish 90244961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 90344961713Sgirish /* The following may work even if we cannot get a large buf. */ 90444961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 90544961713Sgirish return (0); 90644961713Sgirish } 90744961713Sgirish 90844961713Sgirish buf_len = buff_alloc_size; 90944961713Sgirish mp->b_cont = np; 91044961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 91144961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 91244961713Sgirish 91344961713Sgirish rx_rcr_rings = nxgep->rx_rcr_rings; 91444961713Sgirish rcr_rings = rx_rcr_rings->rcr_rings; 91544961713Sgirish rx_rbr_rings = nxgep->rx_rbr_rings; 91644961713Sgirish rbr_rings = rx_rbr_rings->rbr_rings; 91744961713Sgirish 91844961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 919a3c5bd6dSspeer "Total RDCs\t %d\n", p_cfgp->max_rdcs); 92044961713Sgirish 92144961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 92244961713Sgirish buf_len -= print_len; 92344961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 924a3c5bd6dSspeer "RDC\t HW RDC\t Timeout\t Packets RBR ptr \t" 925a3c5bd6dSspeer "chunks\t RCR ptr\n"); 926a3c5bd6dSspeer 92744961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 92844961713Sgirish buf_len -= print_len; 92944961713Sgirish for (rdc = 0; rdc < p_cfgp->max_rdcs; rdc++) { 93044961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 931a3c5bd6dSspeer " %d\t %d\t %x\t\t %x\t $%p\t 0x%x\t $%p\n", 932a3c5bd6dSspeer rdc, nxgep->rdc[rdc], 933a3c5bd6dSspeer p_dma_cfgp->rcr_timeout[rdc], 934a3c5bd6dSspeer p_dma_cfgp->rcr_threshold[rdc], 935a3c5bd6dSspeer rbr_rings[rdc], 936a3c5bd6dSspeer rbr_rings[rdc]->num_blocks, rcr_rings[rdc]); 937a3c5bd6dSspeer ((mblk_t *)np)->b_wptr += print_len; 938a3c5bd6dSspeer buf_len -= print_len; 93944961713Sgirish } 940a3c5bd6dSspeer 94144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rxdma_info")); 94244961713Sgirish return (0); 94344961713Sgirish } 94444961713Sgirish 94544961713Sgirish /* ARGSUSED */ 94644961713Sgirish int 94744961713Sgirish nxge_param_get_rxdma_rdcgrp_info(p_nxge_t nxgep, queue_t *q, 948a3c5bd6dSspeer p_mblk_t mp, caddr_t cp) 94944961713Sgirish { 950a3c5bd6dSspeer uint_t print_len, buf_len; 951a3c5bd6dSspeer p_mblk_t np; 952a3c5bd6dSspeer int offset, rdc, i, rdc_grp; 95344961713Sgirish p_nxge_rdc_grp_t rdc_grp_p; 95444961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 95544961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 95644961713Sgirish 95744961713Sgirish int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 95844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 959a3c5bd6dSspeer "==> nxge_param_get_rxdma_rdcgrp_info")); 96044961713Sgirish 96144961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 96244961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 96344961713Sgirish 964a3c5bd6dSspeer (void) mi_mpprintf(mp, "RXDMA RDC Group Information for Port\t %d \n", 965a3c5bd6dSspeer nxgep->function_num); 96644961713Sgirish 96744961713Sgirish rdc_grp = p_cfgp->start_rdc_grpid; 96844961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 96944961713Sgirish /* The following may work even if we cannot get a large buf. */ 97044961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 97144961713Sgirish return (0); 97244961713Sgirish } 97344961713Sgirish 97444961713Sgirish buf_len = buff_alloc_size; 97544961713Sgirish mp->b_cont = np; 97644961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 977a3c5bd6dSspeer "Total RDC Groups\t %d \n" 978a3c5bd6dSspeer "start RDC group\t %d\n", 979a3c5bd6dSspeer p_cfgp->max_rdc_grpids, 980a3c5bd6dSspeer p_cfgp->start_rdc_grpid); 98144961713Sgirish 98244961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 98344961713Sgirish buf_len -= print_len; 98444961713Sgirish 98544961713Sgirish for (i = 0, rdc_grp = p_cfgp->start_rdc_grpid; 98644961713Sgirish rdc_grp < (p_cfgp->max_rdc_grpids + p_cfgp->start_rdc_grpid); 98744961713Sgirish rdc_grp++, i++) { 98844961713Sgirish rdc_grp_p = &p_dma_cfgp->rdc_grps[i]; 98944961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 990a3c5bd6dSspeer "\nRDC Group Info for Group [%d] %d\n" 991a3c5bd6dSspeer "RDC Count %d\tstart RDC %d\n" 992a3c5bd6dSspeer "RDC Group Population Information" 993a3c5bd6dSspeer " (offsets 0 - 15)\n", 994a3c5bd6dSspeer i, rdc_grp, rdc_grp_p->max_rdcs, 995a3c5bd6dSspeer rdc_grp_p->start_rdc); 99644961713Sgirish 99744961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 99844961713Sgirish buf_len -= print_len; 99944961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1000a3c5bd6dSspeer buf_len, "\n"); 100144961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 100244961713Sgirish buf_len -= print_len; 100344961713Sgirish 100444961713Sgirish for (rdc = 0; rdc < rdc_grp_p->max_rdcs; rdc++) { 100544961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1006a3c5bd6dSspeer buf_len, "[%d]=%d ", rdc, 1007a3c5bd6dSspeer rdc_grp_p->start_rdc + rdc); 100844961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 100944961713Sgirish buf_len -= print_len; 101044961713Sgirish } 101144961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 101244961713Sgirish buf_len, "\n"); 101344961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 101444961713Sgirish buf_len -= print_len; 101544961713Sgirish 101644961713Sgirish for (offset = 0; offset < 16; offset++) { 101744961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1018a3c5bd6dSspeer buf_len, " %2d ", 1019a3c5bd6dSspeer rdc_grp_p->rdc[offset]); 102044961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 102144961713Sgirish buf_len -= print_len; 102244961713Sgirish } 102344961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1024a3c5bd6dSspeer buf_len, "\n"); 102544961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 102644961713Sgirish buf_len -= print_len; 102744961713Sgirish } 102844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1029a3c5bd6dSspeer "<== nxge_param_get_rxdma_rdcgrp_info")); 103044961713Sgirish return (0); 103144961713Sgirish } 103244961713Sgirish 103344961713Sgirish int 103444961713Sgirish nxge_mk_mblk_tail_space(p_mblk_t mp, p_mblk_t *nmp, size_t size) 103544961713Sgirish { 103644961713Sgirish p_mblk_t tmp; 103744961713Sgirish 103844961713Sgirish tmp = mp; 103944961713Sgirish while (tmp->b_cont) 104044961713Sgirish tmp = tmp->b_cont; 104144961713Sgirish if ((tmp->b_wptr + size) >= tmp->b_datap->db_lim) { 104244961713Sgirish tmp->b_cont = allocb(1024, BPRI_HI); 104344961713Sgirish tmp = tmp->b_cont; 104444961713Sgirish if (!tmp) 104544961713Sgirish return (ENOMEM); 104644961713Sgirish } 1047a3c5bd6dSspeer 104844961713Sgirish *nmp = tmp; 104944961713Sgirish return (0); 105044961713Sgirish } 105144961713Sgirish 105244961713Sgirish /* 105344961713Sgirish * Sets the ge parameter to the value in the nxge_param_register using 105444961713Sgirish * nxge_nd_load(). 105544961713Sgirish */ 1056a3c5bd6dSspeer 105744961713Sgirish /* ARGSUSED */ 105844961713Sgirish int 105944961713Sgirish nxge_param_set_generic(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 106044961713Sgirish char *value, caddr_t cp) 106144961713Sgirish { 106244961713Sgirish char *end; 106344961713Sgirish uint32_t new_value; 106444961713Sgirish p_nxge_param_t pa = (p_nxge_param_t)cp; 106544961713Sgirish 106644961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, " ==> nxge_param_set_generic")); 106744961713Sgirish new_value = (uint32_t)mi_strtol(value, &end, 10); 106844961713Sgirish if (end == value || new_value < pa->minimum || 106944961713Sgirish new_value > pa->maximum) { 107044961713Sgirish return (EINVAL); 107144961713Sgirish } 107244961713Sgirish pa->value = new_value; 107344961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, " <== nxge_param_set_generic")); 107444961713Sgirish return (0); 107544961713Sgirish } 107644961713Sgirish 107744961713Sgirish /* 107844961713Sgirish * Sets the ge parameter to the value in the nxge_param_register using 107944961713Sgirish * nxge_nd_load(). 108044961713Sgirish */ 108144961713Sgirish 1082a3c5bd6dSspeer /* ARGSUSED */ 108344961713Sgirish int 1084a3c5bd6dSspeer nxge_param_set_instance(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1085a3c5bd6dSspeer char *value, caddr_t cp) 108644961713Sgirish { 108744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " ==> nxge_param_set_instance")); 108844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_set_instance")); 108944961713Sgirish return (0); 109044961713Sgirish } 109144961713Sgirish 109244961713Sgirish /* 109344961713Sgirish * Sets the ge parameter to the value in the nxge_param_register using 109444961713Sgirish * nxge_nd_load(). 109544961713Sgirish */ 109644961713Sgirish 1097a3c5bd6dSspeer /* ARGSUSED */ 109844961713Sgirish int 1099a3c5bd6dSspeer nxge_param_set_mac(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1100a3c5bd6dSspeer char *value, caddr_t cp) 110144961713Sgirish { 1102a3c5bd6dSspeer char *end; 1103a3c5bd6dSspeer uint32_t new_value; 1104a3c5bd6dSspeer int status = 0; 1105a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 110644961713Sgirish 110744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac")); 110844961713Sgirish new_value = (uint32_t)mi_strtol(value, &end, BASE_DECIMAL); 110944961713Sgirish if (PARAM_OUTOF_RANGE(value, end, new_value, pa)) { 111044961713Sgirish return (EINVAL); 111144961713Sgirish } 111244961713Sgirish 111344961713Sgirish if (pa->value != new_value) { 111444961713Sgirish pa->old_value = pa->value; 111544961713Sgirish pa->value = new_value; 111644961713Sgirish } 111744961713Sgirish 111844961713Sgirish if (!nxge_param_link_update(nxgep)) { 111944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 112044961713Sgirish " false ret from nxge_param_link_update")); 112144961713Sgirish status = EINVAL; 112244961713Sgirish } 112344961713Sgirish 112444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac")); 112544961713Sgirish return (status); 112644961713Sgirish } 112744961713Sgirish 112844961713Sgirish /* ARGSUSED */ 112944961713Sgirish static int 1130a3c5bd6dSspeer nxge_param_rx_intr_pkts(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1131a3c5bd6dSspeer char *value, caddr_t cp) 113244961713Sgirish { 1133a3c5bd6dSspeer char *end; 1134a3c5bd6dSspeer uint32_t cfg_value; 1135a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 113614ea4bb7Ssd 113744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_pkts")); 113844961713Sgirish 113914ea4bb7Ssd cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 114044961713Sgirish 114114ea4bb7Ssd if ((cfg_value > NXGE_RDC_RCR_THRESHOLD_MAX) || 114214ea4bb7Ssd (cfg_value < NXGE_RDC_RCR_THRESHOLD_MIN)) { 114344961713Sgirish return (EINVAL); 114444961713Sgirish } 114514ea4bb7Ssd 114614ea4bb7Ssd if ((pa->value != cfg_value)) { 114714ea4bb7Ssd pa->old_value = pa->value; 114814ea4bb7Ssd pa->value = cfg_value; 114914ea4bb7Ssd nxgep->intr_threshold = pa->value; 115044961713Sgirish } 115114ea4bb7Ssd 115244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_pkts")); 115344961713Sgirish return (0); 115444961713Sgirish } 115544961713Sgirish 115644961713Sgirish /* ARGSUSED */ 115744961713Sgirish static int 1158a3c5bd6dSspeer nxge_param_rx_intr_time(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1159a3c5bd6dSspeer char *value, caddr_t cp) 116044961713Sgirish { 1161a3c5bd6dSspeer char *end; 1162a3c5bd6dSspeer uint32_t cfg_value; 1163a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 116444961713Sgirish 116544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_time")); 116644961713Sgirish 116714ea4bb7Ssd cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 116844961713Sgirish 116914ea4bb7Ssd if ((cfg_value > NXGE_RDC_RCR_TIMEOUT_MAX) || 117014ea4bb7Ssd (cfg_value < NXGE_RDC_RCR_TIMEOUT_MIN)) { 117144961713Sgirish return (EINVAL); 117244961713Sgirish } 117344961713Sgirish 117414ea4bb7Ssd if ((pa->value != cfg_value)) { 117514ea4bb7Ssd pa->old_value = pa->value; 117614ea4bb7Ssd pa->value = cfg_value; 117714ea4bb7Ssd nxgep->intr_timeout = pa->value; 117844961713Sgirish } 117944961713Sgirish 118044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_time")); 118144961713Sgirish return (0); 118244961713Sgirish } 118344961713Sgirish 118444961713Sgirish /* ARGSUSED */ 118544961713Sgirish static int 118644961713Sgirish nxge_param_set_mac_rdcgrp(p_nxge_t nxgep, queue_t *q, 1187a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 118844961713Sgirish { 1189a3c5bd6dSspeer char *end; 1190a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1191a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1192a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 119344961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 119444961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 1195a3c5bd6dSspeer uint32_t *val_ptr, *old_val_ptr; 1196a3c5bd6dSspeer nxge_param_map_t *mac_map; 1197a3c5bd6dSspeer p_nxge_class_pt_cfg_t p_class_cfgp; 1198a3c5bd6dSspeer nxge_mv_cfg_t *mac_host_info; 119944961713Sgirish 120044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac_rdcgrp ")); 120144961713Sgirish 120244961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 120344961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 120444961713Sgirish p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 120544961713Sgirish mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 120644961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1207a3c5bd6dSspeer 1208a3c5bd6dSspeer /* 1209a3c5bd6dSspeer * now do decoding 1210a3c5bd6dSspeer */ 121144961713Sgirish mac_map = (nxge_param_map_t *)&cfg_value; 1212a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, NDD_CTL, " cfg_value %x id %x map_to %x", 1213a3c5bd6dSspeer cfg_value, mac_map->param_id, mac_map->map_to)); 121444961713Sgirish 121544961713Sgirish if ((mac_map->param_id < p_cfgp->max_macs) && 1216a3c5bd6dSspeer (mac_map->map_to < (p_cfgp->max_rdc_grpids + 1217a3c5bd6dSspeer p_cfgp->start_rdc_grpid)) && (mac_map->map_to >= 1218a3c5bd6dSspeer p_cfgp->start_rdc_grpid)) { 121944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1220a3c5bd6dSspeer " nxge_param_set_mac_rdcgrp mapping" 1221a3c5bd6dSspeer " id %d grp %d", mac_map->param_id, mac_map->map_to)); 122244961713Sgirish val_ptr = (uint32_t *)pa->value; 122344961713Sgirish old_val_ptr = (uint32_t *)pa->old_value; 122444961713Sgirish if (val_ptr[mac_map->param_id] != cfg_value) { 122544961713Sgirish old_val_ptr[mac_map->param_id] = 122644961713Sgirish val_ptr[mac_map->param_id]; 122744961713Sgirish val_ptr[mac_map->param_id] = cfg_value; 122844961713Sgirish mac_host_info[mac_map->param_id].mpr_npr = 122944961713Sgirish mac_map->pref; 123044961713Sgirish mac_host_info[mac_map->param_id].flag = 1; 123144961713Sgirish mac_host_info[mac_map->param_id].rdctbl = 123244961713Sgirish mac_map->map_to; 123344961713Sgirish cfg_it = B_TRUE; 123444961713Sgirish } 123544961713Sgirish } else { 123644961713Sgirish return (EINVAL); 123744961713Sgirish } 123844961713Sgirish 123944961713Sgirish if (cfg_it == B_TRUE) { 124044961713Sgirish status = nxge_logical_mac_assign_rdc_table(nxgep, 124144961713Sgirish (uint8_t)mac_map->param_id); 124244961713Sgirish if (status != NXGE_OK) 124344961713Sgirish return (EINVAL); 124444961713Sgirish } 124544961713Sgirish 124644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac_rdcgrp")); 124744961713Sgirish return (0); 124844961713Sgirish } 124944961713Sgirish 125044961713Sgirish /* ARGSUSED */ 125144961713Sgirish static int 125244961713Sgirish nxge_param_set_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q, 1253a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 125444961713Sgirish { 1255a3c5bd6dSspeer char *end; 1256a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1257a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1258a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 125944961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 126044961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 1261a3c5bd6dSspeer uint32_t *val_ptr, *old_val_ptr; 1262a3c5bd6dSspeer nxge_param_map_t *vmap, *old_map; 1263a3c5bd6dSspeer p_nxge_class_pt_cfg_t p_class_cfgp; 1264a3c5bd6dSspeer uint64_t cfgd_vlans; 1265a3c5bd6dSspeer int i, inc = 0, cfg_position; 1266a3c5bd6dSspeer nxge_mv_cfg_t *vlan_tbl; 126744961713Sgirish 126844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp ")); 126944961713Sgirish 127044961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 127144961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 127244961713Sgirish p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 127344961713Sgirish vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 127444961713Sgirish 127544961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1276a3c5bd6dSspeer 1277a3c5bd6dSspeer /* now do decoding */ 127844961713Sgirish cfgd_vlans = ((pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >> 1279a3c5bd6dSspeer NXGE_PARAM_ARRAY_CNT_SHIFT); 128044961713Sgirish 128144961713Sgirish if (cfgd_vlans == NXGE_PARAM_ARRAY_INIT_SIZE) { 128244961713Sgirish /* 128344961713Sgirish * for now, we process only upto max 128444961713Sgirish * NXGE_PARAM_ARRAY_INIT_SIZE parameters 128544961713Sgirish * In the future, we may want to expand 128644961713Sgirish * the storage array and continue 128744961713Sgirish */ 128844961713Sgirish return (EINVAL); 128944961713Sgirish } 1290a3c5bd6dSspeer 129144961713Sgirish vmap = (nxge_param_map_t *)&cfg_value; 129244961713Sgirish if ((vmap->param_id) && 129344961713Sgirish (vmap->param_id < NXGE_MAX_VLANS) && 129444961713Sgirish (vmap->map_to < p_cfgp->max_rdc_grpids)) { 129544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1296a3c5bd6dSspeer "nxge_param_set_vlan_rdcgrp mapping" 1297a3c5bd6dSspeer " id %d grp %d", 1298a3c5bd6dSspeer vmap->param_id, vmap->map_to)); 129944961713Sgirish val_ptr = (uint32_t *)pa->value; 130044961713Sgirish old_val_ptr = (uint32_t *)pa->old_value; 130144961713Sgirish 130244961713Sgirish /* search to see if this vlan id is already configured */ 130344961713Sgirish for (i = 0; i < cfgd_vlans; i++) { 130444961713Sgirish old_map = (nxge_param_map_t *)&val_ptr[i]; 130544961713Sgirish if ((old_map->param_id == 0) || 130644961713Sgirish (vmap->param_id == old_map->param_id) || 130744961713Sgirish (vlan_tbl[vmap->param_id].flag)) { 130844961713Sgirish cfg_position = i; 130944961713Sgirish break; 131044961713Sgirish } 131144961713Sgirish } 131244961713Sgirish 131344961713Sgirish if (cfgd_vlans == 0) { 131444961713Sgirish cfg_position = 0; 131544961713Sgirish inc++; 131644961713Sgirish } 131744961713Sgirish 131844961713Sgirish if (i == cfgd_vlans) { 131944961713Sgirish cfg_position = i; 132044961713Sgirish inc++; 132144961713Sgirish } 132244961713Sgirish 132344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 1324a3c5bd6dSspeer "set_vlan_rdcgrp mapping" 1325a3c5bd6dSspeer " i %d cfgd_vlans %llx position %d ", 1326a3c5bd6dSspeer i, cfgd_vlans, cfg_position)); 132744961713Sgirish if (val_ptr[cfg_position] != cfg_value) { 132844961713Sgirish old_val_ptr[cfg_position] = val_ptr[cfg_position]; 132944961713Sgirish val_ptr[cfg_position] = cfg_value; 133044961713Sgirish vlan_tbl[vmap->param_id].mpr_npr = vmap->pref; 133144961713Sgirish vlan_tbl[vmap->param_id].flag = 1; 133244961713Sgirish vlan_tbl[vmap->param_id].rdctbl = 133344961713Sgirish vmap->map_to + p_cfgp->start_rdc_grpid; 133444961713Sgirish cfg_it = B_TRUE; 133544961713Sgirish if (inc) { 133644961713Sgirish cfgd_vlans++; 133744961713Sgirish pa->type &= ~NXGE_PARAM_ARRAY_CNT_MASK; 133844961713Sgirish pa->type |= (cfgd_vlans << 133944961713Sgirish NXGE_PARAM_ARRAY_CNT_SHIFT); 134044961713Sgirish 134144961713Sgirish } 134244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 1343a3c5bd6dSspeer "after: param_set_vlan_rdcgrp " 1344a3c5bd6dSspeer " cfg_vlans %llx position %d \n", 1345a3c5bd6dSspeer cfgd_vlans, cfg_position)); 134644961713Sgirish } 134744961713Sgirish } else { 134844961713Sgirish return (EINVAL); 134944961713Sgirish } 135044961713Sgirish 135144961713Sgirish if (cfg_it == B_TRUE) { 135244961713Sgirish status = nxge_fflp_config_vlan_table(nxgep, 1353a3c5bd6dSspeer (uint16_t)vmap->param_id); 135444961713Sgirish if (status != NXGE_OK) 135544961713Sgirish return (EINVAL); 135644961713Sgirish } 135744961713Sgirish 135844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_vlan_rdcgrp")); 135944961713Sgirish return (0); 136044961713Sgirish } 136144961713Sgirish 136244961713Sgirish /* ARGSUSED */ 136344961713Sgirish static int 136444961713Sgirish nxge_param_get_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q, 1365a3c5bd6dSspeer mblk_t *mp, caddr_t cp) 136644961713Sgirish { 136744961713Sgirish 1368a3c5bd6dSspeer uint_t print_len, buf_len; 1369a3c5bd6dSspeer p_mblk_t np; 1370a3c5bd6dSspeer int i; 1371a3c5bd6dSspeer uint32_t *val_ptr; 1372a3c5bd6dSspeer nxge_param_map_t *vmap; 1373a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 137444961713Sgirish p_nxge_class_pt_cfg_t p_class_cfgp; 137544961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 137644961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 1377a3c5bd6dSspeer uint64_t cfgd_vlans = 0; 1378a3c5bd6dSspeer nxge_mv_cfg_t *vlan_tbl; 1379a3c5bd6dSspeer int buff_alloc_size = 1380a3c5bd6dSspeer NXGE_NDD_INFODUMP_BUFF_SIZE * 32; 138144961713Sgirish 138244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp ")); 1383a3c5bd6dSspeer (void) mi_mpprintf(mp, "VLAN RDC Mapping Information for Port\t %d \n", 1384a3c5bd6dSspeer nxgep->function_num); 138544961713Sgirish 138644961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 138744961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 138844961713Sgirish return (0); 138944961713Sgirish } 1390a3c5bd6dSspeer 139144961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 139244961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 139344961713Sgirish 139444961713Sgirish buf_len = buff_alloc_size; 139544961713Sgirish mp->b_cont = np; 139644961713Sgirish cfgd_vlans = (pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >> 139744961713Sgirish NXGE_PARAM_ARRAY_CNT_SHIFT; 139844961713Sgirish 139944961713Sgirish i = (int)cfgd_vlans; 140044961713Sgirish p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 140144961713Sgirish vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 140244961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1403a3c5bd6dSspeer "Configured VLANs %d\n" 1404a3c5bd6dSspeer "VLAN ID\t RDC GRP (Actual/Port)\t" 1405a3c5bd6dSspeer " Prefernce\n", i); 140644961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 140744961713Sgirish buf_len -= print_len; 140844961713Sgirish 140944961713Sgirish val_ptr = (uint32_t *)pa->value; 141044961713Sgirish 141144961713Sgirish for (i = 0; i < cfgd_vlans; i++) { 141244961713Sgirish vmap = (nxge_param_map_t *)&val_ptr[i]; 141344961713Sgirish if (p_class_cfgp->vlan_tbl[vmap->param_id].flag) { 141444961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1415a3c5bd6dSspeer buf_len, 1416a3c5bd6dSspeer " %d\t\t %d/%d\t\t %d\n", 1417a3c5bd6dSspeer vmap->param_id, 1418a3c5bd6dSspeer vlan_tbl[vmap->param_id].rdctbl, 1419a3c5bd6dSspeer vlan_tbl[vmap->param_id].rdctbl - 1420a3c5bd6dSspeer p_cfgp->start_rdc_grpid, 1421a3c5bd6dSspeer vlan_tbl[vmap->param_id].mpr_npr); 142244961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 142344961713Sgirish buf_len -= print_len; 142444961713Sgirish } 142544961713Sgirish } 142644961713Sgirish 142744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_vlan_rdcgrp")); 142844961713Sgirish return (0); 142944961713Sgirish } 143044961713Sgirish 143144961713Sgirish /* ARGSUSED */ 143244961713Sgirish static int 143344961713Sgirish nxge_param_get_mac_rdcgrp(p_nxge_t nxgep, queue_t *q, 1434a3c5bd6dSspeer mblk_t *mp, caddr_t cp) 143544961713Sgirish { 1436a3c5bd6dSspeer uint_t print_len, buf_len; 1437a3c5bd6dSspeer p_mblk_t np; 1438a3c5bd6dSspeer int i; 143944961713Sgirish p_nxge_class_pt_cfg_t p_class_cfgp; 144044961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 144144961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 1442a3c5bd6dSspeer nxge_mv_cfg_t *mac_host_info; 144344961713Sgirish 144444961713Sgirish int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE * 32; 144544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac_rdcgrp ")); 144644961713Sgirish (void) mi_mpprintf(mp, 1447a3c5bd6dSspeer "MAC ADDR RDC Mapping Information for Port\t %d\n", 1448a3c5bd6dSspeer nxgep->function_num); 144944961713Sgirish 145044961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 145144961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 145244961713Sgirish return (0); 145344961713Sgirish } 145444961713Sgirish 145544961713Sgirish buf_len = buff_alloc_size; 145644961713Sgirish mp->b_cont = np; 145744961713Sgirish p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 145844961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 145944961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 146044961713Sgirish mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 146144961713Sgirish print_len = snprintf((char *)np->b_wptr, buf_len, 1462a3c5bd6dSspeer "MAC ID\t RDC GRP (Actual/Port)\t" 1463a3c5bd6dSspeer " Prefernce\n"); 146444961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 146544961713Sgirish buf_len -= print_len; 146644961713Sgirish for (i = 0; i < p_cfgp->max_macs; i++) { 146744961713Sgirish if (mac_host_info[i].flag) { 146844961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1469a3c5bd6dSspeer buf_len, 1470a3c5bd6dSspeer " %d\t %d/%d\t\t %d\n", 1471a3c5bd6dSspeer i, mac_host_info[i].rdctbl, 1472a3c5bd6dSspeer mac_host_info[i].rdctbl - 1473a3c5bd6dSspeer p_cfgp->start_rdc_grpid, 1474a3c5bd6dSspeer mac_host_info[i].mpr_npr); 147544961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 147644961713Sgirish buf_len -= print_len; 147744961713Sgirish } 147844961713Sgirish } 147944961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1480a3c5bd6dSspeer "Done Info Dumping \n"); 148144961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 148244961713Sgirish buf_len -= print_len; 148344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_macrdcgrp")); 148444961713Sgirish return (0); 148544961713Sgirish } 148644961713Sgirish 148744961713Sgirish /* ARGSUSED */ 148844961713Sgirish static int 148944961713Sgirish nxge_param_tcam_enable(p_nxge_t nxgep, queue_t *q, 1490a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 149144961713Sgirish { 1492a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1493a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1494a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 1495a3c5bd6dSspeer char *end; 149644961713Sgirish 149744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_tcam_enable")); 149844961713Sgirish 149944961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 150044961713Sgirish if (pa->value != cfg_value) { 150144961713Sgirish pa->old_value = pa->value; 150244961713Sgirish pa->value = cfg_value; 150344961713Sgirish cfg_it = B_TRUE; 150444961713Sgirish } 150544961713Sgirish 150644961713Sgirish if (cfg_it == B_TRUE) { 150744961713Sgirish if (pa->value) 150844961713Sgirish status = nxge_fflp_config_tcam_enable(nxgep); 150944961713Sgirish else 151044961713Sgirish status = nxge_fflp_config_tcam_disable(nxgep); 151144961713Sgirish if (status != NXGE_OK) 151244961713Sgirish return (EINVAL); 151344961713Sgirish } 151444961713Sgirish 151544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_tcam_enable")); 151644961713Sgirish return (0); 151744961713Sgirish } 151844961713Sgirish 151944961713Sgirish /* ARGSUSED */ 152044961713Sgirish static int 152144961713Sgirish nxge_param_hash_lookup_enable(p_nxge_t nxgep, queue_t *q, 1522a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 152344961713Sgirish { 1524a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1525a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1526a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 1527a3c5bd6dSspeer char *end; 152844961713Sgirish 152944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_hash_lookup_enable")); 153044961713Sgirish 153144961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 153244961713Sgirish if (pa->value != cfg_value) { 153344961713Sgirish pa->old_value = pa->value; 153444961713Sgirish pa->value = cfg_value; 153544961713Sgirish cfg_it = B_TRUE; 153644961713Sgirish } 153744961713Sgirish 153844961713Sgirish if (cfg_it == B_TRUE) { 153944961713Sgirish if (pa->value) 154044961713Sgirish status = nxge_fflp_config_hash_lookup_enable(nxgep); 154144961713Sgirish else 154244961713Sgirish status = nxge_fflp_config_hash_lookup_disable(nxgep); 154344961713Sgirish if (status != NXGE_OK) 154444961713Sgirish return (EINVAL); 154544961713Sgirish } 154644961713Sgirish 154744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_hash_lookup_enable")); 154844961713Sgirish return (0); 154944961713Sgirish } 155044961713Sgirish 155144961713Sgirish /* ARGSUSED */ 155244961713Sgirish static int 155344961713Sgirish nxge_param_llc_snap_enable(p_nxge_t nxgep, queue_t *q, 1554a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 155544961713Sgirish { 1556a3c5bd6dSspeer char *end; 1557a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1558a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1559a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 156044961713Sgirish 156144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_llc_snap_enable")); 156244961713Sgirish 156344961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 156444961713Sgirish if (pa->value != cfg_value) { 156544961713Sgirish pa->old_value = pa->value; 156644961713Sgirish pa->value = cfg_value; 156744961713Sgirish cfg_it = B_TRUE; 156844961713Sgirish } 156944961713Sgirish 157044961713Sgirish if (cfg_it == B_TRUE) { 157144961713Sgirish if (pa->value) 157244961713Sgirish status = nxge_fflp_config_tcam_enable(nxgep); 157344961713Sgirish else 157444961713Sgirish status = nxge_fflp_config_tcam_disable(nxgep); 157544961713Sgirish if (status != NXGE_OK) 157644961713Sgirish return (EINVAL); 157744961713Sgirish } 157844961713Sgirish 157944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_llc_snap_enable")); 158044961713Sgirish return (0); 158144961713Sgirish } 158244961713Sgirish 158344961713Sgirish /* ARGSUSED */ 158444961713Sgirish static int 158544961713Sgirish nxge_param_set_ether_usr(p_nxge_t nxgep, queue_t *q, 1586a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 158744961713Sgirish { 1588a3c5bd6dSspeer char *end; 1589a3c5bd6dSspeer uint8_t ether_class; 1590a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1591a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1592a3c5bd6dSspeer uint8_t cfg_it = B_FALSE; 159344961713Sgirish 159444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ether_usr")); 159544961713Sgirish 159644961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 159744961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 159844961713Sgirish return (EINVAL); 159944961713Sgirish } 1600a3c5bd6dSspeer 160144961713Sgirish if (pa->value != cfg_value) { 160244961713Sgirish pa->old_value = pa->value; 160344961713Sgirish pa->value = cfg_value; 160444961713Sgirish cfg_it = B_TRUE; 160544961713Sgirish } 160644961713Sgirish 160744961713Sgirish /* do the actual hw setup */ 160844961713Sgirish if (cfg_it == B_TRUE) { 160944961713Sgirish ether_class = mi_strtol(pa->name, &end, 10); 161044961713Sgirish #ifdef lint 161144961713Sgirish ether_class = ether_class; 161244961713Sgirish #endif 161344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_ether_usr")); 161444961713Sgirish } 1615a3c5bd6dSspeer 161644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ether_usr")); 161744961713Sgirish return (status); 161844961713Sgirish } 161944961713Sgirish 162044961713Sgirish /* ARGSUSED */ 162144961713Sgirish static int 162244961713Sgirish nxge_param_set_ip_usr(p_nxge_t nxgep, queue_t *q, 1623a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 162444961713Sgirish { 1625a3c5bd6dSspeer char *end; 1626a3c5bd6dSspeer tcam_class_t class; 1627a3c5bd6dSspeer uint32_t status, cfg_value; 1628a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1629a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 163044961713Sgirish 163144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_usr")); 163244961713Sgirish 163344961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 163444961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 163544961713Sgirish return (EINVAL); 163644961713Sgirish } 163744961713Sgirish 163844961713Sgirish if (pa->value != cfg_value) { 163944961713Sgirish pa->old_value = pa->value; 164044961713Sgirish pa->value = cfg_value; 164144961713Sgirish cfg_it = B_TRUE; 164244961713Sgirish } 164344961713Sgirish 164444961713Sgirish /* do the actual hw setup with cfg_value. */ 164544961713Sgirish if (cfg_it == B_TRUE) { 164644961713Sgirish class = mi_strtol(pa->name, &end, 10); 164744961713Sgirish status = nxge_fflp_ip_usr_class_config(nxgep, class, pa->value); 164844961713Sgirish } 164944961713Sgirish 165044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_usr")); 165144961713Sgirish return (status); 165244961713Sgirish } 165344961713Sgirish 1654a3c5bd6dSspeer /* ARGSUSED */ 165544961713Sgirish static int 165644961713Sgirish nxge_class_name_2value(p_nxge_t nxgep, char *name) 165744961713Sgirish { 1658a3c5bd6dSspeer int i; 1659a3c5bd6dSspeer int class_instance = param_class_opt_ip_usr4; 1660a3c5bd6dSspeer p_nxge_param_t param_arr; 1661a3c5bd6dSspeer 166244961713Sgirish param_arr = nxgep->param_arr; 166344961713Sgirish for (i = TCAM_CLASS_IP_USER_4; i <= TCAM_CLASS_SCTP_IPV6; i++) { 166444961713Sgirish if (strcmp(param_arr[class_instance].name, name) == 0) 166544961713Sgirish return (i); 166644961713Sgirish class_instance++; 166744961713Sgirish } 166844961713Sgirish return (-1); 166944961713Sgirish } 167044961713Sgirish 167144961713Sgirish /* ARGSUSED */ 167244961713Sgirish static int 167344961713Sgirish nxge_param_set_ip_opt(p_nxge_t nxgep, queue_t *q, 1674a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 167544961713Sgirish { 1676a3c5bd6dSspeer char *end; 1677a3c5bd6dSspeer uint32_t status, cfg_value; 1678a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1679a3c5bd6dSspeer tcam_class_t class; 1680a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 168144961713Sgirish 168244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_opt")); 168344961713Sgirish 168444961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 168544961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 168644961713Sgirish return (EINVAL); 168744961713Sgirish } 168844961713Sgirish 168944961713Sgirish if (pa->value != cfg_value) { 169044961713Sgirish pa->old_value = pa->value; 169144961713Sgirish pa->value = cfg_value; 169244961713Sgirish cfg_it = B_TRUE; 169344961713Sgirish } 169444961713Sgirish 169544961713Sgirish if (cfg_it == B_TRUE) { 1696a3c5bd6dSspeer /* do the actual hw setup */ 169744961713Sgirish class = nxge_class_name_2value(nxgep, pa->name); 169844961713Sgirish if (class == -1) 169944961713Sgirish return (EINVAL); 170044961713Sgirish 170144961713Sgirish status = nxge_fflp_ip_class_config(nxgep, class, pa->value); 170244961713Sgirish if (status != NXGE_OK) 170344961713Sgirish return (EINVAL); 170444961713Sgirish } 170544961713Sgirish 170644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_opt")); 170744961713Sgirish return (0); 170844961713Sgirish } 170944961713Sgirish 171044961713Sgirish /* ARGSUSED */ 171144961713Sgirish static int 171244961713Sgirish nxge_param_get_ip_opt(p_nxge_t nxgep, queue_t *q, 1713a3c5bd6dSspeer mblk_t *mp, caddr_t cp) 171444961713Sgirish { 171544961713Sgirish uint32_t status, cfg_value; 171644961713Sgirish p_nxge_param_t pa = (p_nxge_param_t)cp; 171744961713Sgirish tcam_class_t class; 171844961713Sgirish 171944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_ip_opt")); 172044961713Sgirish 1721a3c5bd6dSspeer /* do the actual hw setup */ 172244961713Sgirish class = nxge_class_name_2value(nxgep, pa->name); 172344961713Sgirish if (class == -1) 172444961713Sgirish return (EINVAL); 1725a3c5bd6dSspeer 172644961713Sgirish cfg_value = 0; 172744961713Sgirish status = nxge_fflp_ip_class_config_get(nxgep, class, &cfg_value); 172844961713Sgirish if (status != NXGE_OK) 172944961713Sgirish return (EINVAL); 1730a3c5bd6dSspeer 173144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1732a3c5bd6dSspeer "nxge_param_get_ip_opt_get %x ", cfg_value)); 173344961713Sgirish 1734a3c5bd6dSspeer pa->value = cfg_value; 173544961713Sgirish (void) mi_mpprintf(mp, "%x", cfg_value); 1736a3c5bd6dSspeer 173744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_ip_opt status ")); 173844961713Sgirish return (0); 173944961713Sgirish } 174044961713Sgirish 174144961713Sgirish /* ARGSUSED */ 174244961713Sgirish static int 174344961713Sgirish nxge_param_fflp_hash_init(p_nxge_t nxgep, queue_t *q, 1744a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 174544961713Sgirish { 1746a3c5bd6dSspeer char *end; 1747a3c5bd6dSspeer uint32_t status, cfg_value; 1748a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1749a3c5bd6dSspeer tcam_class_t class; 1750a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 175144961713Sgirish 175244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_fflp_hash_init")); 175344961713Sgirish 175444961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 175544961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 175644961713Sgirish return (EINVAL); 175744961713Sgirish } 175844961713Sgirish 175944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1760a3c5bd6dSspeer "nxge_param_fflp_hash_init value %x", cfg_value)); 1761a3c5bd6dSspeer 176244961713Sgirish if (pa->value != cfg_value) { 176344961713Sgirish pa->old_value = pa->value; 176444961713Sgirish pa->value = cfg_value; 176544961713Sgirish cfg_it = B_TRUE; 176644961713Sgirish } 176744961713Sgirish 176844961713Sgirish if (cfg_it == B_TRUE) { 176944961713Sgirish char *h_name; 1770a3c5bd6dSspeer 177144961713Sgirish /* do the actual hw setup */ 177244961713Sgirish h_name = pa->name; 177344961713Sgirish h_name++; 177444961713Sgirish class = mi_strtol(h_name, &end, 10); 177544961713Sgirish switch (class) { 177644961713Sgirish case 1: 177744961713Sgirish status = nxge_fflp_set_hash1(nxgep, 1778a3c5bd6dSspeer (uint32_t)pa->value); 177944961713Sgirish break; 178044961713Sgirish case 2: 178144961713Sgirish status = nxge_fflp_set_hash2(nxgep, 1782a3c5bd6dSspeer (uint16_t)pa->value); 178344961713Sgirish break; 178444961713Sgirish 178544961713Sgirish default: 178644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1787a3c5bd6dSspeer " nxge_param_fflp_hash_init" 1788a3c5bd6dSspeer " %s Wrong hash var %d", 1789a3c5bd6dSspeer pa->name, class)); 179044961713Sgirish return (EINVAL); 179144961713Sgirish } 179244961713Sgirish if (status != NXGE_OK) 179344961713Sgirish return (EINVAL); 179444961713Sgirish } 179544961713Sgirish 179644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_fflp_hash_init")); 179744961713Sgirish return (0); 179844961713Sgirish } 179944961713Sgirish 180044961713Sgirish /* ARGSUSED */ 180144961713Sgirish static int 180244961713Sgirish nxge_param_set_grp_rdc(p_nxge_t nxgep, queue_t *q, 1803a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 180444961713Sgirish { 1805a3c5bd6dSspeer char *end; 1806a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1807a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1808a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 1809a3c5bd6dSspeer int rdc_grp; 1810a3c5bd6dSspeer uint8_t real_rdc; 181144961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 181244961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 181344961713Sgirish p_nxge_rdc_grp_t rdc_grp_p; 181444961713Sgirish 181544961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 181644961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 181744961713Sgirish 181844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_grp_rdc")); 181944961713Sgirish 182044961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 182144961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 182244961713Sgirish return (EINVAL); 182344961713Sgirish } 1824a3c5bd6dSspeer 182544961713Sgirish if (cfg_value >= p_cfgp->max_rdcs) { 182644961713Sgirish return (EINVAL); 182744961713Sgirish } 1828a3c5bd6dSspeer 182944961713Sgirish if (pa->value != cfg_value) { 183044961713Sgirish pa->old_value = pa->value; 183144961713Sgirish pa->value = cfg_value; 183244961713Sgirish cfg_it = B_TRUE; 183344961713Sgirish } 183444961713Sgirish 183544961713Sgirish if (cfg_it == B_TRUE) { 183644961713Sgirish char *grp_name; 183744961713Sgirish grp_name = pa->name; 183844961713Sgirish grp_name += strlen("default-grp"); 183944961713Sgirish rdc_grp = mi_strtol(grp_name, &end, 10); 184044961713Sgirish rdc_grp_p = &p_dma_cfgp->rdc_grps[rdc_grp]; 184144961713Sgirish real_rdc = rdc_grp_p->start_rdc + cfg_value; 184244961713Sgirish if (nxge_check_rxdma_rdcgrp_member(nxgep, rdc_grp, 1843a3c5bd6dSspeer cfg_value) == B_FALSE) { 184444961713Sgirish pa->value = pa->old_value; 184544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1846a3c5bd6dSspeer " nxge_param_set_grp_rdc" 1847a3c5bd6dSspeer " %d read %d actual %d outof range", 1848a3c5bd6dSspeer rdc_grp, cfg_value, real_rdc)); 184944961713Sgirish return (EINVAL); 185044961713Sgirish } 185144961713Sgirish status = nxge_rxdma_cfg_rdcgrp_default_rdc(nxgep, rdc_grp, 185244961713Sgirish real_rdc); 185344961713Sgirish if (status != NXGE_OK) 185444961713Sgirish return (EINVAL); 185544961713Sgirish } 185644961713Sgirish 185744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_grp_rdc")); 185844961713Sgirish return (0); 185944961713Sgirish } 186044961713Sgirish 186144961713Sgirish /* ARGSUSED */ 186244961713Sgirish static int 186344961713Sgirish nxge_param_set_port_rdc(p_nxge_t nxgep, queue_t *q, 1864a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 186544961713Sgirish { 1866a3c5bd6dSspeer char *end; 1867a3c5bd6dSspeer uint32_t status = B_TRUE, cfg_value; 1868a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1869a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 187044961713Sgirish 187144961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 187244961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 187344961713Sgirish 187444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_port_rdc")); 187544961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 187644961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 187744961713Sgirish 187844961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 187944961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 188044961713Sgirish return (EINVAL); 188144961713Sgirish } 1882a3c5bd6dSspeer 188344961713Sgirish if (pa->value != cfg_value) { 188444961713Sgirish if (cfg_value >= p_cfgp->max_rdcs) 188544961713Sgirish return (EINVAL); 188644961713Sgirish pa->old_value = pa->value; 188744961713Sgirish pa->value = cfg_value; 188844961713Sgirish cfg_it = B_TRUE; 188944961713Sgirish } 189044961713Sgirish 189144961713Sgirish if (cfg_it == B_TRUE) { 189244961713Sgirish status = nxge_rxdma_cfg_port_default_rdc(nxgep, 1893a3c5bd6dSspeer nxgep->function_num, 1894a3c5bd6dSspeer nxgep->rdc[cfg_value]); 189544961713Sgirish if (status != NXGE_OK) 189644961713Sgirish return (EINVAL); 189744961713Sgirish } 189844961713Sgirish 189944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_port_rdc")); 190044961713Sgirish return (0); 190144961713Sgirish } 190244961713Sgirish 190344961713Sgirish /* ARGSUSED */ 190444961713Sgirish static int 190544961713Sgirish nxge_param_set_nxge_debug_flag(p_nxge_t nxgep, queue_t *q, 1906a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 190744961713Sgirish { 190844961713Sgirish char *end; 190944961713Sgirish uint32_t status = 0; 191044961713Sgirish uint64_t cfg_value = 0; 191144961713Sgirish p_nxge_param_t pa = (p_nxge_param_t)cp; 191244961713Sgirish uint32_t cfg_it = B_FALSE; 191344961713Sgirish 191444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_nxge_debug_flag")); 191544961713Sgirish cfg_value = mi_strtol(value, &end, BASE_HEX); 191644961713Sgirish 191744961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 191844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1919a3c5bd6dSspeer " nxge_param_set_nxge_debug_flag" 1920a3c5bd6dSspeer " outof range %llx", cfg_value)); 192144961713Sgirish return (EINVAL); 192244961713Sgirish } 192344961713Sgirish if (pa->value != cfg_value) { 192444961713Sgirish pa->old_value = pa->value; 192544961713Sgirish pa->value = cfg_value; 192644961713Sgirish cfg_it = B_TRUE; 192744961713Sgirish } 192844961713Sgirish 192944961713Sgirish if (cfg_it == B_TRUE) { 193044961713Sgirish nxgep->nxge_debug_level = pa->value; 193144961713Sgirish } 1932a3c5bd6dSspeer 193344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_nxge_debug_flag")); 193444961713Sgirish return (status); 193544961713Sgirish } 193644961713Sgirish 193744961713Sgirish /* ARGSUSED */ 193844961713Sgirish static int 193944961713Sgirish nxge_param_get_debug_flag(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 194044961713Sgirish { 1941a3c5bd6dSspeer int status = 0; 1942a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 194344961713Sgirish 194444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_debug_flag")); 194544961713Sgirish 194644961713Sgirish if (pa->value > 0xffffffff) 194744961713Sgirish (void) mi_mpprintf(mp, "%x%x", (int)(pa->value >> 32), 1948a3c5bd6dSspeer (int)(pa->value & 0xffffffff)); 194944961713Sgirish else 195044961713Sgirish (void) mi_mpprintf(mp, "%x", (int)pa->value); 195144961713Sgirish 195244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_debug_flag")); 195344961713Sgirish return (status); 195444961713Sgirish } 195544961713Sgirish 195644961713Sgirish /* ARGSUSED */ 195744961713Sgirish static int 195844961713Sgirish nxge_param_set_npi_debug_flag(p_nxge_t nxgep, queue_t *q, 1959a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 196044961713Sgirish { 1961a3c5bd6dSspeer char *end; 1962a3c5bd6dSspeer uint32_t status = 0; 1963a3c5bd6dSspeer uint64_t cfg_value = 0; 1964a3c5bd6dSspeer p_nxge_param_t pa; 1965a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 196644961713Sgirish 196744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_npi_debug_flag")); 196844961713Sgirish cfg_value = mi_strtol(value, &end, BASE_HEX); 196944961713Sgirish pa = (p_nxge_param_t)cp; 197044961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 197144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_npi_debug_flag" 197244961713Sgirish " outof range %llx", cfg_value)); 197344961713Sgirish return (EINVAL); 197444961713Sgirish } 197544961713Sgirish if (pa->value != cfg_value) { 197644961713Sgirish pa->old_value = pa->value; 197744961713Sgirish pa->value = cfg_value; 197844961713Sgirish cfg_it = B_TRUE; 197944961713Sgirish } 198044961713Sgirish 198144961713Sgirish if (cfg_it == B_TRUE) { 198244961713Sgirish npi_debug_level = pa->value; 198344961713Sgirish } 198444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_debug_flag")); 198544961713Sgirish return (status); 198644961713Sgirish } 198744961713Sgirish 198844961713Sgirish /* ARGSUSED */ 198944961713Sgirish static int 199044961713Sgirish nxge_param_dump_rdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 199144961713Sgirish { 1992a3c5bd6dSspeer uint_t rdc; 199344961713Sgirish 199444961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_rdc")); 199544961713Sgirish 199644961713Sgirish (void) npi_rxdma_dump_fzc_regs(NXGE_DEV_NPI_HANDLE(nxgep)); 199744961713Sgirish for (rdc = 0; rdc < nxgep->nrdc; rdc++) 199844961713Sgirish (void) nxge_dump_rxdma_channel(nxgep, nxgep->rdc[rdc]); 199944961713Sgirish 200044961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_rdc")); 200144961713Sgirish return (0); 200244961713Sgirish } 200344961713Sgirish 200444961713Sgirish /* ARGSUSED */ 200544961713Sgirish static int 200644961713Sgirish nxge_param_dump_tdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 200744961713Sgirish { 200844961713Sgirish uint_t tdc; 200944961713Sgirish 201044961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_tdc")); 201144961713Sgirish 201244961713Sgirish for (tdc = 0; tdc < nxgep->ntdc; tdc++) 201344961713Sgirish (void) nxge_txdma_regs_dump(nxgep, nxgep->tdc[tdc]); 201444961713Sgirish 201544961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_tdc")); 201644961713Sgirish return (0); 201744961713Sgirish } 201844961713Sgirish 201944961713Sgirish /* ARGSUSED */ 202044961713Sgirish static int 202144961713Sgirish nxge_param_dump_fflp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 202244961713Sgirish { 202344961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_fflp_regs")); 202444961713Sgirish 202544961713Sgirish (void) npi_fflp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep)); 202644961713Sgirish 202744961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_fflp_regs")); 202844961713Sgirish return (0); 202944961713Sgirish } 203044961713Sgirish 203144961713Sgirish /* ARGSUSED */ 203244961713Sgirish static int 203344961713Sgirish nxge_param_dump_mac_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 203444961713Sgirish { 203544961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_mac_regs")); 203644961713Sgirish 203744961713Sgirish (void) npi_mac_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep), 2038a3c5bd6dSspeer nxgep->function_num); 203944961713Sgirish 204044961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_mac_regs")); 204144961713Sgirish return (0); 204244961713Sgirish } 204344961713Sgirish 204444961713Sgirish /* ARGSUSED */ 204544961713Sgirish static int 204644961713Sgirish nxge_param_dump_ipp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 204744961713Sgirish { 204844961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_ipp_regs")); 204944961713Sgirish 2050a3c5bd6dSspeer (void) npi_ipp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep), 2051a3c5bd6dSspeer nxgep->function_num); 205244961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ipp_regs")); 205344961713Sgirish return (0); 205444961713Sgirish } 205544961713Sgirish 205644961713Sgirish /* ARGSUSED */ 205744961713Sgirish static int 205844961713Sgirish nxge_param_dump_vlan_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 205944961713Sgirish { 206044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_vlan_table")); 206144961713Sgirish 206244961713Sgirish (void) npi_fflp_vlan_tbl_dump(NXGE_DEV_NPI_HANDLE(nxgep)); 206344961713Sgirish 206444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_vlan_table")); 206544961713Sgirish return (0); 206644961713Sgirish } 206744961713Sgirish 206844961713Sgirish /* ARGSUSED */ 206944961713Sgirish static int 207044961713Sgirish nxge_param_dump_rdc_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 207144961713Sgirish { 2072a3c5bd6dSspeer uint8_t table; 207344961713Sgirish 207444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_rdc_table")); 207544961713Sgirish for (table = 0; table < NXGE_MAX_RDC_GROUPS; table++) { 207644961713Sgirish (void) npi_rxdma_dump_rdc_table(NXGE_DEV_NPI_HANDLE(nxgep), 207744961713Sgirish table); 207844961713Sgirish } 2079a3c5bd6dSspeer 208044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_rdc_table")); 208144961713Sgirish return (0); 208244961713Sgirish } 208344961713Sgirish 208444961713Sgirish typedef struct block_info { 208544961713Sgirish char *name; 208644961713Sgirish uint32_t offset; 208744961713Sgirish } block_info_t; 208844961713Sgirish 208944961713Sgirish block_info_t reg_block[] = { 209044961713Sgirish {"PIO", PIO}, 209144961713Sgirish {"FZC_PIO", FZC_PIO}, 209244961713Sgirish {"FZC_XMAC", FZC_MAC}, 209344961713Sgirish {"FZC_IPP", FZC_IPP}, 209444961713Sgirish {"FFLP", FFLP}, 209544961713Sgirish {"FZC_FFLP", FZC_FFLP}, 209644961713Sgirish {"PIO_VADDR", PIO_VADDR}, 209744961713Sgirish {"ZCP", ZCP}, 209844961713Sgirish {"FZC_ZCP", FZC_ZCP}, 209944961713Sgirish {"DMC", DMC}, 210044961713Sgirish {"FZC_DMC", FZC_DMC}, 210144961713Sgirish {"TXC", TXC}, 210244961713Sgirish {"FZC_TXC", FZC_TXC}, 210344961713Sgirish {"PIO_LDSV", PIO_LDSV}, 210444961713Sgirish {"PIO_LDGIM", PIO_LDGIM}, 210544961713Sgirish {"PIO_IMASK0", PIO_IMASK0}, 210644961713Sgirish {"PIO_IMASK1", PIO_IMASK1}, 210744961713Sgirish {"FZC_PROM", FZC_PROM}, 210844961713Sgirish {"END", ALL_FF_32}, 210944961713Sgirish }; 211044961713Sgirish 211144961713Sgirish /* ARGSUSED */ 211244961713Sgirish static int 211344961713Sgirish nxge_param_dump_ptrs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 211444961713Sgirish { 2115a3c5bd6dSspeer uint_t print_len, buf_len; 2116a3c5bd6dSspeer p_mblk_t np; 2117a3c5bd6dSspeer int rdc, tdc, block; 2118a3c5bd6dSspeer uint64_t base; 211944961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 212044961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 2121a3c5bd6dSspeer int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_8K; 212244961713Sgirish p_tx_ring_t *tx_rings; 212344961713Sgirish p_rx_rcr_rings_t rx_rcr_rings; 212444961713Sgirish p_rx_rcr_ring_t *rcr_rings; 212544961713Sgirish p_rx_rbr_rings_t rx_rbr_rings; 212644961713Sgirish p_rx_rbr_ring_t *rbr_rings; 212744961713Sgirish 2128a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, IOC_CTL, 2129a3c5bd6dSspeer "==> nxge_param_dump_ptrs")); 213044961713Sgirish 2131a3c5bd6dSspeer (void) mi_mpprintf(mp, "ptr information for Port\t %d \n", 2132a3c5bd6dSspeer nxgep->function_num); 213344961713Sgirish 213444961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 213544961713Sgirish /* The following may work even if we cannot get a large buf. */ 213644961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 213744961713Sgirish return (0); 213844961713Sgirish } 213944961713Sgirish 214044961713Sgirish buf_len = buff_alloc_size; 214144961713Sgirish mp->b_cont = np; 214244961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 214344961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 214444961713Sgirish 214544961713Sgirish rx_rcr_rings = nxgep->rx_rcr_rings; 214644961713Sgirish rcr_rings = rx_rcr_rings->rcr_rings; 214744961713Sgirish rx_rbr_rings = nxgep->rx_rbr_rings; 214844961713Sgirish rbr_rings = rx_rbr_rings->rbr_rings; 214944961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2150a3c5bd6dSspeer "nxgep (nxge_t) $%p\n" 2151a3c5bd6dSspeer "dev_regs (dev_regs_t) $%p\n", 2152a3c5bd6dSspeer nxgep, nxgep->dev_regs); 215344961713Sgirish 215444961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2155a3c5bd6dSspeer 2156a3c5bd6dSspeer /* do register pointers */ 215744961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2158a3c5bd6dSspeer "reg base (npi_reg_ptr_t) $%p\t " 2159a3c5bd6dSspeer "pci reg (npi_reg_ptr_t) $%p\n", 2160a3c5bd6dSspeer nxgep->dev_regs->nxge_regp, 2161a3c5bd6dSspeer nxgep->dev_regs->nxge_pciregp); 216244961713Sgirish 216344961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 216444961713Sgirish 216544961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2166a3c5bd6dSspeer "\nBlock \t Offset \n"); 216744961713Sgirish 216844961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 216944961713Sgirish block = 0; 217044961713Sgirish base = (uint64_t)nxgep->dev_regs->nxge_regp; 217144961713Sgirish while (reg_block[block].offset != ALL_FF_32) { 217244961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2173a3c5bd6dSspeer "%9s\t 0x%llx\n", 2174a3c5bd6dSspeer reg_block[block].name, 2175a3c5bd6dSspeer (unsigned long long)(reg_block[block].offset + base)); 217644961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 217744961713Sgirish block++; 217844961713Sgirish } 217944961713Sgirish 218044961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2181a3c5bd6dSspeer "\nRDC\t rcrp (rx_rcr_ring_t)\t " 2182a3c5bd6dSspeer "rbrp (rx_rbr_ring_t)\n"); 218344961713Sgirish 218444961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 218544961713Sgirish 218644961713Sgirish for (rdc = 0; rdc < p_cfgp->max_rdcs; rdc++) { 218744961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2188a3c5bd6dSspeer " %d\t $%p\t\t $%p\n", 2189a3c5bd6dSspeer rdc, rcr_rings[rdc], 2190a3c5bd6dSspeer rbr_rings[rdc]); 219144961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 219244961713Sgirish } 219344961713Sgirish 219444961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 219544961713Sgirish "\nTDC\t tdcp (tx_ring_t)\n"); 219644961713Sgirish 219744961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 219844961713Sgirish tx_rings = nxgep->tx_rings->rings; 219944961713Sgirish for (tdc = 0; tdc < p_cfgp->max_tdcs; tdc++) { 220044961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2201a3c5bd6dSspeer " %d\t $%p\n", tdc, tx_rings[tdc]); 220244961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 220344961713Sgirish } 220444961713Sgirish 2205a3c5bd6dSspeer print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, "\n\n"); 220644961713Sgirish 220744961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 220844961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ptrs")); 220944961713Sgirish return (0); 221044961713Sgirish } 221144961713Sgirish 221244961713Sgirish /* 221344961713Sgirish * Load 'name' into the named dispatch table pointed to by 'ndp'. 221444961713Sgirish * 'ndp' should be the address of a char pointer cell. If the table 221544961713Sgirish * does not exist (*ndp == 0), a new table is allocated and 'ndp' 221644961713Sgirish * is stuffed. If there is not enough space in the table for a new 221744961713Sgirish * entry, more space is allocated. 221844961713Sgirish */ 2219a3c5bd6dSspeer /* ARGSUSED */ 222044961713Sgirish boolean_t 222144961713Sgirish nxge_nd_load(caddr_t *pparam, char *name, 2222a3c5bd6dSspeer pfi_t get_pfi, pfi_t set_pfi, caddr_t data) 222344961713Sgirish { 222444961713Sgirish ND *nd; 222544961713Sgirish NDE *nde; 222644961713Sgirish 222744961713Sgirish NXGE_DEBUG_MSG((NULL, NDD2_CTL, " ==> nxge_nd_load")); 222844961713Sgirish if (!pparam) 222944961713Sgirish return (B_FALSE); 2230a3c5bd6dSspeer 223144961713Sgirish if ((nd = (ND *)*pparam) == NULL) { 2232a3c5bd6dSspeer if ((nd = (ND *)KMEM_ZALLOC(sizeof (ND), KM_NOSLEEP)) == NULL) 223344961713Sgirish return (B_FALSE); 223444961713Sgirish *pparam = (caddr_t)nd; 223544961713Sgirish } 2236a3c5bd6dSspeer 223744961713Sgirish if (nd->nd_tbl) { 223844961713Sgirish for (nde = nd->nd_tbl; nde->nde_name; nde++) { 223944961713Sgirish if (strcmp(name, nde->nde_name) == 0) 224044961713Sgirish goto fill_it; 224144961713Sgirish } 224244961713Sgirish } 2243a3c5bd6dSspeer 224444961713Sgirish if (nd->nd_free_count <= 1) { 224544961713Sgirish if ((nde = (NDE *)KMEM_ZALLOC(nd->nd_size + 224644961713Sgirish NDE_ALLOC_SIZE, KM_NOSLEEP)) == NULL) 224744961713Sgirish return (B_FALSE); 224844961713Sgirish nd->nd_free_count += NDE_ALLOC_COUNT; 224944961713Sgirish if (nd->nd_tbl) { 225044961713Sgirish bcopy((char *)nd->nd_tbl, (char *)nde, nd->nd_size); 225144961713Sgirish KMEM_FREE((char *)nd->nd_tbl, nd->nd_size); 225244961713Sgirish } else { 225344961713Sgirish nd->nd_free_count--; 225444961713Sgirish nde->nde_name = "?"; 225544961713Sgirish nde->nde_get_pfi = nxge_nd_get_names; 225644961713Sgirish nde->nde_set_pfi = nxge_set_default; 225744961713Sgirish } 225844961713Sgirish nde->nde_data = (caddr_t)nd; 225944961713Sgirish nd->nd_tbl = nde; 226044961713Sgirish nd->nd_size += NDE_ALLOC_SIZE; 226144961713Sgirish } 226244961713Sgirish for (nde = nd->nd_tbl; nde->nde_name; nde++) 226344961713Sgirish noop; 226444961713Sgirish nd->nd_free_count--; 226544961713Sgirish fill_it: 226644961713Sgirish nde->nde_name = name; 226744961713Sgirish nde->nde_get_pfi = get_pfi; 226844961713Sgirish nde->nde_set_pfi = set_pfi; 226944961713Sgirish nde->nde_data = data; 227044961713Sgirish NXGE_DEBUG_MSG((NULL, NDD2_CTL, " <== nxge_nd_load")); 227144961713Sgirish 227244961713Sgirish return (B_TRUE); 227344961713Sgirish } 227444961713Sgirish 227544961713Sgirish /* 227644961713Sgirish * Free the table pointed to by 'pparam' 227744961713Sgirish */ 227844961713Sgirish void 227944961713Sgirish nxge_nd_free(caddr_t *pparam) 228044961713Sgirish { 2281a3c5bd6dSspeer ND *nd; 228244961713Sgirish 228344961713Sgirish if ((nd = (ND *)*pparam) != NULL) { 228444961713Sgirish if (nd->nd_tbl) 228544961713Sgirish KMEM_FREE((char *)nd->nd_tbl, nd->nd_size); 228644961713Sgirish KMEM_FREE((char *)nd, sizeof (ND)); 228744961713Sgirish *pparam = nil(caddr_t); 228844961713Sgirish } 228944961713Sgirish } 229044961713Sgirish 229144961713Sgirish int 229244961713Sgirish nxge_nd_getset(p_nxge_t nxgep, queue_t *q, caddr_t param, p_mblk_t mp) 229344961713Sgirish { 2294a3c5bd6dSspeer int err; 2295a3c5bd6dSspeer IOCP iocp; 2296a3c5bd6dSspeer p_mblk_t mp1, mp2; 2297a3c5bd6dSspeer ND *nd; 2298a3c5bd6dSspeer NDE *nde; 2299a3c5bd6dSspeer char *valp; 2300a3c5bd6dSspeer size_t avail; 230144961713Sgirish 230244961713Sgirish if (!param) { 230344961713Sgirish return (B_FALSE); 230444961713Sgirish } 2305a3c5bd6dSspeer 230644961713Sgirish nd = (ND *)param; 230744961713Sgirish iocp = (IOCP)mp->b_rptr; 230844961713Sgirish if ((iocp->ioc_count == 0) || !(mp1 = mp->b_cont)) { 230944961713Sgirish mp->b_datap->db_type = M_IOCACK; 231044961713Sgirish iocp->ioc_count = 0; 231144961713Sgirish iocp->ioc_error = EINVAL; 231244961713Sgirish return (B_FALSE); 231344961713Sgirish } 2314a3c5bd6dSspeer 231544961713Sgirish /* 231644961713Sgirish * NOTE - logic throughout nd_xxx assumes single data block for ioctl. 231744961713Sgirish * However, existing code sends in some big buffers. 231844961713Sgirish */ 231944961713Sgirish avail = iocp->ioc_count; 232044961713Sgirish if (mp1->b_cont) { 232144961713Sgirish freemsg(mp1->b_cont); 232244961713Sgirish mp1->b_cont = NULL; 232344961713Sgirish } 232444961713Sgirish 232544961713Sgirish mp1->b_datap->db_lim[-1] = '\0'; /* Force null termination */ 232644961713Sgirish for (valp = (char *)mp1->b_rptr; *valp != '\0'; valp++) { 232744961713Sgirish if (*valp == '-') 232844961713Sgirish *valp = '_'; 232944961713Sgirish } 233044961713Sgirish 233144961713Sgirish valp = (char *)mp1->b_rptr; 233244961713Sgirish 233344961713Sgirish for (nde = nd->nd_tbl; /* */; nde++) { 233444961713Sgirish if (!nde->nde_name) 233544961713Sgirish return (B_FALSE); 233644961713Sgirish if (strcmp(nde->nde_name, valp) == 0) 233744961713Sgirish break; 233844961713Sgirish } 233944961713Sgirish err = EINVAL; 234044961713Sgirish while (*valp++) 234144961713Sgirish noop; 234244961713Sgirish if (!*valp || valp >= (char *)mp1->b_wptr) 234344961713Sgirish valp = nilp(char); 234444961713Sgirish switch (iocp->ioc_cmd) { 234544961713Sgirish case ND_GET: 234644961713Sgirish /* 234744961713Sgirish * (temporary) hack: "*valp" is size of user buffer for 234844961713Sgirish * copyout. If result of action routine is too big, free 234944961713Sgirish * excess and return ioc_rval as buffer size needed. 235044961713Sgirish * Return as many mblocks as will fit, free the rest. For 235144961713Sgirish * backward compatibility, assume size of original ioctl 235244961713Sgirish * buffer if "*valp" bad or not given. 235344961713Sgirish */ 235444961713Sgirish if (valp) 235544961713Sgirish avail = mi_strtol(valp, (char **)0, 10); 235644961713Sgirish /* 235744961713Sgirish * We overwrite the name/value with the reply data 235844961713Sgirish */ 235944961713Sgirish mp2 = mp1; 236044961713Sgirish while (mp2) { 236144961713Sgirish mp2->b_wptr = mp2->b_rptr; 236244961713Sgirish mp2 = mp2->b_cont; 236344961713Sgirish } 236444961713Sgirish 236544961713Sgirish err = (*nde->nde_get_pfi)(nxgep, q, mp1, nde->nde_data); 236644961713Sgirish 236744961713Sgirish if (!err) { 236844961713Sgirish size_t size_out = 0; 236944961713Sgirish size_t excess; 237044961713Sgirish 237144961713Sgirish iocp->ioc_rval = 0; 237244961713Sgirish 237344961713Sgirish /* Tack on the null */ 237444961713Sgirish err = nxge_mk_mblk_tail_space(mp1, &mp2, 1); 237544961713Sgirish if (!err) { 237644961713Sgirish *mp2->b_wptr++ = '\0'; 237744961713Sgirish size_out = msgdsize(mp1); 237844961713Sgirish excess = size_out - avail; 237944961713Sgirish if (excess > 0) { 238044961713Sgirish iocp->ioc_rval = (int)size_out; 238144961713Sgirish size_out -= excess; 238244961713Sgirish (void) adjmsg(mp1, -(excess + 1)); 238344961713Sgirish err = nxge_mk_mblk_tail_space( 238444961713Sgirish mp1, &mp2, 1); 238544961713Sgirish if (!err) 238644961713Sgirish *mp2->b_wptr++ = '\0'; 238744961713Sgirish else 238844961713Sgirish size_out = 0; 238944961713Sgirish } 239044961713Sgirish } else 239144961713Sgirish size_out = 0; 239244961713Sgirish iocp->ioc_count = size_out; 239344961713Sgirish } 239444961713Sgirish break; 239544961713Sgirish 239644961713Sgirish case ND_SET: 239744961713Sgirish if (valp) { 239844961713Sgirish if (nde->nde_set_pfi) { 239944961713Sgirish err = (*nde->nde_set_pfi)(nxgep, q, mp1, valp, 240044961713Sgirish nde->nde_data); 240144961713Sgirish iocp->ioc_count = 0; 240244961713Sgirish freemsg(mp1); 240344961713Sgirish mp->b_cont = NULL; 240444961713Sgirish } 240544961713Sgirish } 240644961713Sgirish break; 240744961713Sgirish 240844961713Sgirish default: 240944961713Sgirish break; 241044961713Sgirish } 241144961713Sgirish iocp->ioc_error = err; 241244961713Sgirish mp->b_datap->db_type = M_IOCACK; 241344961713Sgirish return (B_TRUE); 241444961713Sgirish } 241544961713Sgirish 241644961713Sgirish /* ARGSUSED */ 241744961713Sgirish int 241844961713Sgirish nxge_nd_get_names(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t param) 241944961713Sgirish { 2420a3c5bd6dSspeer ND *nd; 2421a3c5bd6dSspeer NDE *nde; 2422a3c5bd6dSspeer char *rwtag; 2423a3c5bd6dSspeer boolean_t get_ok, set_ok; 2424a3c5bd6dSspeer size_t param_len; 2425a3c5bd6dSspeer int status = 0; 242644961713Sgirish 242744961713Sgirish nd = (ND *)param; 242844961713Sgirish if (!nd) 242944961713Sgirish return (ENOENT); 243044961713Sgirish 243144961713Sgirish for (nde = nd->nd_tbl; nde->nde_name; nde++) { 243244961713Sgirish get_ok = (nde->nde_get_pfi != nxge_get_default) && 243344961713Sgirish (nde->nde_get_pfi != NULL); 243444961713Sgirish set_ok = (nde->nde_set_pfi != nxge_set_default) && 243544961713Sgirish (nde->nde_set_pfi != NULL); 243644961713Sgirish if (get_ok) { 243744961713Sgirish if (set_ok) 243844961713Sgirish rwtag = "read and write"; 243944961713Sgirish else 244044961713Sgirish rwtag = "read only"; 244144961713Sgirish } else if (set_ok) 244244961713Sgirish rwtag = "write only"; 244344961713Sgirish else { 244444961713Sgirish continue; 244544961713Sgirish } 244644961713Sgirish param_len = strlen(rwtag); 244744961713Sgirish param_len += strlen(nde->nde_name); 244844961713Sgirish param_len += 4; 244944961713Sgirish 245044961713Sgirish (void) mi_mpprintf(mp, "%s (%s)", nde->nde_name, rwtag); 245144961713Sgirish } 245244961713Sgirish return (status); 245344961713Sgirish } 245444961713Sgirish 245544961713Sgirish /* ARGSUSED */ 245644961713Sgirish int 245744961713Sgirish nxge_get_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t data) 245844961713Sgirish { 245944961713Sgirish return (EACCES); 246044961713Sgirish } 246144961713Sgirish 246244961713Sgirish /* ARGSUSED */ 246344961713Sgirish int 246444961713Sgirish nxge_set_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, char *value, 2465a3c5bd6dSspeer caddr_t data) 246644961713Sgirish { 246744961713Sgirish return (EACCES); 246844961713Sgirish } 246944961713Sgirish 247044961713Sgirish void 247144961713Sgirish nxge_param_ioctl(p_nxge_t nxgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 247244961713Sgirish { 247344961713Sgirish int cmd; 247444961713Sgirish int status = B_FALSE; 247544961713Sgirish 247644961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_ioctl")); 247744961713Sgirish cmd = iocp->ioc_cmd; 2478a3c5bd6dSspeer 247944961713Sgirish switch (cmd) { 248044961713Sgirish default: 248144961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, 248244961713Sgirish "nxge_param_ioctl: bad cmd 0x%0x", cmd)); 248344961713Sgirish break; 248444961713Sgirish 248544961713Sgirish case ND_GET: 248644961713Sgirish case ND_SET: 248744961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, 248844961713Sgirish "nxge_param_ioctl: cmd 0x%0x", cmd)); 248944961713Sgirish if (!nxge_nd_getset(nxgep, wq, nxgep->param_list, mp)) { 249044961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, 249144961713Sgirish "false ret from nxge_nd_getset")); 249244961713Sgirish break; 249344961713Sgirish } 249444961713Sgirish status = B_TRUE; 249544961713Sgirish break; 249644961713Sgirish } 249744961713Sgirish 249844961713Sgirish if (status) { 249944961713Sgirish qreply(wq, mp); 250044961713Sgirish } else { 250144961713Sgirish miocnak(wq, mp, 0, EINVAL); 250244961713Sgirish } 250344961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_ioctl")); 250444961713Sgirish } 250544961713Sgirish 250644961713Sgirish /* ARGSUSED */ 250744961713Sgirish static boolean_t 250844961713Sgirish nxge_param_link_update(p_nxge_t nxgep) 250944961713Sgirish { 251044961713Sgirish p_nxge_param_t param_arr; 251144961713Sgirish nxge_param_index_t i; 251244961713Sgirish boolean_t update_xcvr; 251344961713Sgirish boolean_t update_dev; 251444961713Sgirish int instance; 251544961713Sgirish boolean_t status = B_TRUE; 251644961713Sgirish 251744961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_link_update")); 251844961713Sgirish 251944961713Sgirish param_arr = nxgep->param_arr; 252044961713Sgirish instance = nxgep->instance; 252144961713Sgirish update_xcvr = B_FALSE; 252244961713Sgirish for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) { 252344961713Sgirish update_xcvr |= param_arr[i].value; 252444961713Sgirish } 252544961713Sgirish 252644961713Sgirish if (update_xcvr) { 252744961713Sgirish update_xcvr = B_FALSE; 252844961713Sgirish for (i = param_autoneg; i < param_enable_ipg0; i++) { 252944961713Sgirish update_xcvr |= 253044961713Sgirish (param_arr[i].value != param_arr[i].old_value); 253144961713Sgirish param_arr[i].old_value = param_arr[i].value; 253244961713Sgirish } 253344961713Sgirish if (update_xcvr) { 253444961713Sgirish RW_ENTER_WRITER(&nxgep->filter_lock); 253544961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 253644961713Sgirish (void) nxge_link_init(nxgep); 253744961713Sgirish (void) nxge_mac_init(nxgep); 253844961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 253944961713Sgirish RW_EXIT(&nxgep->filter_lock); 254044961713Sgirish } 254144961713Sgirish } else { 254244961713Sgirish cmn_err(CE_WARN, " Last setting will leave nxge%d with " 254344961713Sgirish " no link capabilities.", instance); 254444961713Sgirish cmn_err(CE_WARN, " Restoring previous setting."); 254544961713Sgirish for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) 254644961713Sgirish param_arr[i].value = param_arr[i].old_value; 254744961713Sgirish } 2548a3c5bd6dSspeer 254944961713Sgirish update_dev = B_FALSE; 255044961713Sgirish 255144961713Sgirish if (update_dev) { 255244961713Sgirish RW_ENTER_WRITER(&nxgep->filter_lock); 255344961713Sgirish (void) nxge_rx_mac_disable(nxgep); 255444961713Sgirish (void) nxge_tx_mac_disable(nxgep); 255544961713Sgirish (void) nxge_tx_mac_enable(nxgep); 255644961713Sgirish (void) nxge_rx_mac_enable(nxgep); 255744961713Sgirish RW_EXIT(&nxgep->filter_lock); 255844961713Sgirish } 255944961713Sgirish 256044961713Sgirish nxge_param_hw_update_exit: 256144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 256244961713Sgirish "<== nxge_param_link_update status = 0x%08x", status)); 256344961713Sgirish return (status); 256444961713Sgirish } 2565