144961713Sgirish /* 244961713Sgirish * CDDL HEADER START 344961713Sgirish * 444961713Sgirish * The contents of this file are subject to the terms of the 544961713Sgirish * Common Development and Distribution License (the "License"). 644961713Sgirish * You may not use this file except in compliance with the License. 744961713Sgirish * 844961713Sgirish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 944961713Sgirish * or http://www.opensolaris.org/os/licensing. 1044961713Sgirish * See the License for the specific language governing permissions 1144961713Sgirish * and limitations under the License. 1244961713Sgirish * 1344961713Sgirish * When distributing Covered Code, include this CDDL HEADER in each 1444961713Sgirish * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1544961713Sgirish * If applicable, add the following below this CDDL HEADER, with the 1644961713Sgirish * fields enclosed by brackets "[]" replaced with your own identifying 1744961713Sgirish * information: Portions Copyright [yyyy] [name of copyright owner] 1844961713Sgirish * 1944961713Sgirish * CDDL HEADER END 2044961713Sgirish */ 2144961713Sgirish /* 223d16f8e7Sml * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 2344961713Sgirish * Use is subject to license terms. 2444961713Sgirish */ 2544961713Sgirish 2644961713Sgirish #pragma ident "%Z%%M% %I% %E% SMI" 2744961713Sgirish 2844961713Sgirish #include <sys/nxge/nxge_impl.h> 29678453a8Sspeer #include <sys/nxge/nxge_hio.h> 30678453a8Sspeer 3144961713Sgirish #include <inet/common.h> 3244961713Sgirish #include <inet/mi.h> 3344961713Sgirish #include <inet/nd.h> 3444961713Sgirish 3544961713Sgirish extern uint64_t npi_debug_level; 3644961713Sgirish 37a3c5bd6dSspeer #define NXGE_PARAM_MAC_RW \ 38a3c5bd6dSspeer NXGE_PARAM_RW | NXGE_PARAM_MAC | \ 3944961713Sgirish NXGE_PARAM_NDD_WR_OK | NXGE_PARAM_READ_PROP 4044961713Sgirish 41a3c5bd6dSspeer #define NXGE_PARAM_MAC_DONT_SHOW \ 42a3c5bd6dSspeer NXGE_PARAM_RW | NXGE_PARAM_MAC | NXGE_PARAM_DONT_SHOW 4344961713Sgirish 44a3c5bd6dSspeer #define NXGE_PARAM_RXDMA_RW \ 45a3c5bd6dSspeer NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_NDD_WR_OK | \ 46a3c5bd6dSspeer NXGE_PARAM_READ_PROP 4744961713Sgirish 48a3c5bd6dSspeer #define NXGE_PARAM_RXDMA_RWC \ 49a3c5bd6dSspeer NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_INIT_ONLY | \ 50a3c5bd6dSspeer NXGE_PARAM_READ_PROP 5144961713Sgirish 52a3c5bd6dSspeer #define NXGE_PARAM_L2CLASS_CFG \ 53a3c5bd6dSspeer NXGE_PARAM_RW | NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_READ_PROP | \ 54a3c5bd6dSspeer NXGE_PARAM_NDD_WR_OK 5544961713Sgirish 56a3c5bd6dSspeer #define NXGE_PARAM_CLASS_RWS \ 57a3c5bd6dSspeer NXGE_PARAM_RWS | NXGE_PARAM_READ_PROP 5844961713Sgirish 5944961713Sgirish #define NXGE_PARAM_ARRAY_INIT_SIZE 0x20ULL 6044961713Sgirish 6144961713Sgirish #define SET_RX_INTR_TIME_DISABLE 0 6244961713Sgirish #define SET_RX_INTR_TIME_ENABLE 1 6344961713Sgirish #define SET_RX_INTR_PKTS 2 6444961713Sgirish 6544961713Sgirish #define BASE_ANY 0 66a3c5bd6dSspeer #define BASE_BINARY 2 6744961713Sgirish #define BASE_HEX 16 6844961713Sgirish #define BASE_DECIMAL 10 6944961713Sgirish #define ALL_FF_64 0xFFFFFFFFFFFFFFFFULL 7044961713Sgirish #define ALL_FF_32 0xFFFFFFFFUL 7144961713Sgirish 7244961713Sgirish #define NXGE_NDD_INFODUMP_BUFF_SIZE 2048 /* is 2k enough? */ 7344961713Sgirish #define NXGE_NDD_INFODUMP_BUFF_8K 8192 7444961713Sgirish #define NXGE_NDD_INFODUMP_BUFF_16K 0x2000 7544961713Sgirish #define NXGE_NDD_INFODUMP_BUFF_64K 0x8000 7644961713Sgirish 7744961713Sgirish #define PARAM_OUTOF_RANGE(vptr, eptr, rval, pa) \ 7844961713Sgirish ((vptr == eptr) || (rval < pa->minimum) || (rval > pa->maximum)) 7944961713Sgirish 8044961713Sgirish #define ADVANCE_PRINT_BUFFER(pmp, plen, rlen) { \ 8144961713Sgirish ((mblk_t *)pmp)->b_wptr += plen; \ 8244961713Sgirish rlen -= plen; \ 83a3c5bd6dSspeer } 8444961713Sgirish 85*4045d941Ssowmini int nxge_param_set_mac(p_nxge_t, queue_t *, 86a3c5bd6dSspeer mblk_t *, char *, caddr_t); 8744961713Sgirish static int nxge_param_set_port_rdc(p_nxge_t, queue_t *, 88a3c5bd6dSspeer mblk_t *, char *, caddr_t); 8944961713Sgirish static int nxge_param_set_grp_rdc(p_nxge_t, queue_t *, 90a3c5bd6dSspeer mblk_t *, char *, caddr_t); 9144961713Sgirish static int nxge_param_set_ether_usr(p_nxge_t, 92a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 9344961713Sgirish static int nxge_param_set_ip_usr(p_nxge_t, 94a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 9544961713Sgirish static int nxge_param_set_vlan_rdcgrp(p_nxge_t, 96a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 9744961713Sgirish static int nxge_param_set_mac_rdcgrp(p_nxge_t, 98a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 9944961713Sgirish static int nxge_param_fflp_hash_init(p_nxge_t, 100a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 10144961713Sgirish static int nxge_param_llc_snap_enable(p_nxge_t, queue_t *, 102a3c5bd6dSspeer mblk_t *, char *, caddr_t); 10344961713Sgirish static int nxge_param_hash_lookup_enable(p_nxge_t, queue_t *, 104a3c5bd6dSspeer mblk_t *, char *, caddr_t); 10544961713Sgirish static int nxge_param_tcam_enable(p_nxge_t, queue_t *, 106a3c5bd6dSspeer mblk_t *, char *, caddr_t); 10756d930aeSspeer static int nxge_param_get_fw_ver(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 1082e59129aSraghus static int nxge_param_get_port_mode(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 10944961713Sgirish static int nxge_param_get_rxdma_info(p_nxge_t, queue_t *q, 110a3c5bd6dSspeer p_mblk_t, caddr_t); 11144961713Sgirish static int nxge_param_get_txdma_info(p_nxge_t, queue_t *q, 112a3c5bd6dSspeer p_mblk_t, caddr_t); 11344961713Sgirish static int nxge_param_get_vlan_rdcgrp(p_nxge_t, queue_t *, 114a3c5bd6dSspeer p_mblk_t, caddr_t); 11544961713Sgirish static int nxge_param_get_mac_rdcgrp(p_nxge_t, queue_t *, 116a3c5bd6dSspeer p_mblk_t, caddr_t); 11744961713Sgirish static int nxge_param_get_rxdma_rdcgrp_info(p_nxge_t, queue_t *, 118a3c5bd6dSspeer p_mblk_t, caddr_t); 11944961713Sgirish static int nxge_param_get_ip_opt(p_nxge_t, queue_t *, mblk_t *, caddr_t); 120a3c5bd6dSspeer static int nxge_param_get_mac(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 12144961713Sgirish static int nxge_param_get_debug_flag(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 12244961713Sgirish static int nxge_param_set_nxge_debug_flag(p_nxge_t, queue_t *, mblk_t *, 123a3c5bd6dSspeer char *, caddr_t); 12444961713Sgirish static int nxge_param_set_npi_debug_flag(p_nxge_t, 125a3c5bd6dSspeer queue_t *, mblk_t *, char *, caddr_t); 12644961713Sgirish static int nxge_param_dump_rdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 12744961713Sgirish static int nxge_param_dump_tdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 12844961713Sgirish static int nxge_param_dump_mac_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 12944961713Sgirish static int nxge_param_dump_ipp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 13044961713Sgirish static int nxge_param_dump_fflp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 13144961713Sgirish static int nxge_param_dump_vlan_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 13244961713Sgirish static int nxge_param_dump_rdc_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 13344961713Sgirish static int nxge_param_dump_ptrs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 1341bd6825cSml static void nxge_param_sync(p_nxge_t); 13544961713Sgirish 13644961713Sgirish /* 13744961713Sgirish * Global array of Neptune changable parameters. 13844961713Sgirish * This array is initialized to correspond to the default 13944961713Sgirish * Neptune 4 port configuration. This array would be copied 14044961713Sgirish * into each port's parameter structure and modifed per 14144961713Sgirish * fcode and nxge.conf configuration. Later, the parameters are 14244961713Sgirish * exported to ndd to display and run-time configuration (at least 14344961713Sgirish * some of them). 14444961713Sgirish * 14544961713Sgirish */ 14644961713Sgirish 147a3c5bd6dSspeer static nxge_param_t nxge_param_arr[] = { 148a3c5bd6dSspeer /* 149a3c5bd6dSspeer * min max value old hw-name conf-name 150a3c5bd6dSspeer */ 151846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 152a3c5bd6dSspeer 0, 999, 1000, 0, "instance", "instance"}, 153a3c5bd6dSspeer 154846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 155a3c5bd6dSspeer 0, 999, 1000, 0, "main-instance", "main_instance"}, 156a3c5bd6dSspeer 157a3c5bd6dSspeer { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 158a3c5bd6dSspeer 0, 3, 0, 0, "function-number", "function_number"}, 159a3c5bd6dSspeer 160a3c5bd6dSspeer /* Partition Id */ 161846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 162a3c5bd6dSspeer 0, 8, 0, 0, "partition-id", "partition_id"}, 163a3c5bd6dSspeer 164a3c5bd6dSspeer /* Read Write Permission Mode */ 165846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 166a3c5bd6dSspeer 0, 2, 0, 0, "read-write-mode", "read_write_mode"}, 167a3c5bd6dSspeer 16856d930aeSspeer { nxge_param_get_fw_ver, NULL, NXGE_PARAM_READ, 16956d930aeSspeer 0, 32, 0, 0, "version", "fw_version"}, 17056d930aeSspeer 1712e59129aSraghus { nxge_param_get_port_mode, NULL, NXGE_PARAM_READ, 1722e59129aSraghus 0, 32, 0, 0, "port-mode", "port_mode"}, 1732e59129aSraghus 174a3c5bd6dSspeer /* hw cfg types */ 175a3c5bd6dSspeer /* control the DMA config of Neptune/NIU */ 176846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 177a3c5bd6dSspeer CFG_DEFAULT, CFG_CUSTOM, CFG_DEFAULT, CFG_DEFAULT, 178a3c5bd6dSspeer "niu-cfg-type", "niu_cfg_type"}, 179a3c5bd6dSspeer 180a3c5bd6dSspeer /* control the TXDMA config of the Port controlled by tx-quick-cfg */ 181846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 182a3c5bd6dSspeer CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT, 183a3c5bd6dSspeer "tx-qcfg-type", "tx_qcfg_type"}, 184a3c5bd6dSspeer 185a3c5bd6dSspeer /* control the RXDMA config of the Port controlled by rx-quick-cfg */ 186846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 187a3c5bd6dSspeer CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT, 188a3c5bd6dSspeer "rx-qcfg-type", "rx_qcfg_type"}, 189a3c5bd6dSspeer 190a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, 191a3c5bd6dSspeer NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 192a3c5bd6dSspeer 0, 1, 0, 0, "master-cfg-enable", "master_cfg_enable"}, 193a3c5bd6dSspeer 194a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, 195846a903dSml NXGE_PARAM_DONT_SHOW, 196a3c5bd6dSspeer 0, 1, 0, 0, "master-cfg-value", "master_cfg_value"}, 197a3c5bd6dSspeer 198a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 199a3c5bd6dSspeer 0, 1, 1, 1, "adv-autoneg-cap", "adv_autoneg_cap"}, 200a3c5bd6dSspeer 201a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 202a3c5bd6dSspeer 0, 1, 1, 1, "adv-10gfdx-cap", "adv_10gfdx_cap"}, 203a3c5bd6dSspeer 204a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 205a3c5bd6dSspeer 0, 1, 0, 0, "adv-10ghdx-cap", "adv_10ghdx_cap"}, 206a3c5bd6dSspeer 207a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 208a3c5bd6dSspeer 0, 1, 1, 1, "adv-1000fdx-cap", "adv_1000fdx_cap"}, 209a3c5bd6dSspeer 210a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 211a3c5bd6dSspeer 0, 1, 0, 0, "adv-1000hdx-cap", "adv_1000hdx_cap"}, 212a3c5bd6dSspeer 213a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 214a3c5bd6dSspeer 0, 1, 0, 0, "adv-100T4-cap", "adv_100T4_cap"}, 215a3c5bd6dSspeer 216a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 217a3c5bd6dSspeer 0, 1, 1, 1, "adv-100fdx-cap", "adv_100fdx_cap"}, 218a3c5bd6dSspeer 219a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 220a3c5bd6dSspeer 0, 1, 0, 0, "adv-100hdx-cap", "adv_100hdx_cap"}, 221a3c5bd6dSspeer 222a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 223a3c5bd6dSspeer 0, 1, 1, 1, "adv-10fdx-cap", "adv_10fdx_cap"}, 224a3c5bd6dSspeer 225a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 226a3c5bd6dSspeer 0, 1, 0, 0, "adv-10hdx-cap", "adv_10hdx_cap"}, 227a3c5bd6dSspeer 228846a903dSml { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 229a3c5bd6dSspeer 0, 1, 0, 0, "adv-asmpause-cap", "adv_asmpause_cap"}, 230a3c5bd6dSspeer 231a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 232a3c5bd6dSspeer 0, 1, 0, 0, "adv-pause-cap", "adv_pause_cap"}, 233a3c5bd6dSspeer 234846a903dSml { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 235a3c5bd6dSspeer 0, 1, 0, 0, "use-int-xcvr", "use_int_xcvr"}, 236a3c5bd6dSspeer 237846a903dSml { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 238a3c5bd6dSspeer 0, 1, 1, 1, "enable-ipg0", "enable_ipg0"}, 239a3c5bd6dSspeer 240846a903dSml { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 241a3c5bd6dSspeer 0, 255, 8, 8, "ipg0", "ipg0"}, 242a3c5bd6dSspeer 243846a903dSml { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 244a3c5bd6dSspeer 0, 255, 8, 8, "ipg1", "ipg1"}, 245a3c5bd6dSspeer 246846a903dSml { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 247a3c5bd6dSspeer 0, 255, 4, 4, "ipg2", "ipg2"}, 248a3c5bd6dSspeer 249a3c5bd6dSspeer { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 250a3c5bd6dSspeer 0, 1, 0, 0, "accept-jumbo", "accept_jumbo"}, 251a3c5bd6dSspeer 252a3c5bd6dSspeer /* Transmit DMA channels */ 253846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 254846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 255a3c5bd6dSspeer 0, 3, 0, 0, "tx-dma-weight", "tx_dma_weight"}, 256a3c5bd6dSspeer 257846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 258846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 259a3c5bd6dSspeer 0, 31, 0, 0, "tx-dma-channels-begin", "tx_dma_channels_begin"}, 260a3c5bd6dSspeer 261846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 262846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 263a3c5bd6dSspeer 0, 32, 0, 0, "tx-dma-channels", "tx_dma_channels"}, 264a3c5bd6dSspeer { nxge_param_get_txdma_info, NULL, 265846a903dSml NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 266a3c5bd6dSspeer 0, 32, 0, 0, "tx-dma-info", "tx_dma_info"}, 267a3c5bd6dSspeer 268a3c5bd6dSspeer /* Receive DMA channels */ 269a3c5bd6dSspeer { nxge_param_get_generic, NULL, 270846a903dSml NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 271a3c5bd6dSspeer 0, 31, 0, 0, "rx-dma-channels-begin", "rx_dma_channels_begin"}, 272a3c5bd6dSspeer 273846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 274846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 275a3c5bd6dSspeer 0, 32, 0, 0, "rx-dma-channels", "rx_dma_channels"}, 276a3c5bd6dSspeer 277846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 278846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 279a3c5bd6dSspeer 0, 65535, PT_DRR_WT_DEFAULT_10G, 0, 280a3c5bd6dSspeer "rx-drr-weight", "rx_drr_weight"}, 281a3c5bd6dSspeer 282846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 283846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 284a3c5bd6dSspeer 0, 1, 1, 0, "rx-full-header", "rx_full_header"}, 285a3c5bd6dSspeer 286846a903dSml { nxge_param_get_rxdma_info, NULL, NXGE_PARAM_READ | 287846a903dSml NXGE_PARAM_DONT_SHOW, 288a3c5bd6dSspeer 0, 32, 0, 0, "rx-dma-info", "rx_dma_info"}, 289a3c5bd6dSspeer 290a3c5bd6dSspeer { nxge_param_get_rxdma_info, NULL, 291a3c5bd6dSspeer NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 292a3c5bd6dSspeer NXGE_RBR_RBB_MIN, NXGE_RBR_RBB_MAX, NXGE_RBR_RBB_DEFAULT, 0, 293a3c5bd6dSspeer "rx-rbr-size", "rx_rbr_size"}, 294a3c5bd6dSspeer 295a3c5bd6dSspeer { nxge_param_get_rxdma_info, NULL, 296a3c5bd6dSspeer NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 297a3c5bd6dSspeer NXGE_RCR_MIN, NXGE_RCR_MAX, NXGE_RCR_DEFAULT, 0, 298a3c5bd6dSspeer "rx-rcr-size", "rx_rcr_size"}, 299a3c5bd6dSspeer 300846a903dSml { nxge_param_get_generic, nxge_param_set_port_rdc, 301846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 302a3c5bd6dSspeer 0, 15, 0, 0, "default-port-rdc", "default_port_rdc"}, 303a3c5bd6dSspeer 304a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_rx_intr_time, NXGE_PARAM_RXDMA_RW, 305a3c5bd6dSspeer NXGE_RDC_RCR_TIMEOUT_MIN, NXGE_RDC_RCR_TIMEOUT_MAX, 306a3c5bd6dSspeer RXDMA_RCR_TO_DEFAULT, 0, "rxdma-intr-time", "rxdma_intr_time"}, 307a3c5bd6dSspeer 308a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_rx_intr_pkts, NXGE_PARAM_RXDMA_RW, 309a3c5bd6dSspeer NXGE_RDC_RCR_THRESHOLD_MIN, NXGE_RDC_RCR_THRESHOLD_MAX, 310a3c5bd6dSspeer RXDMA_RCR_PTHRES_DEFAULT, 0, 311a3c5bd6dSspeer "rxdma-intr-pkts", "rxdma_intr_pkts"}, 312a3c5bd6dSspeer 313846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP | 314846a903dSml NXGE_PARAM_DONT_SHOW, 315a3c5bd6dSspeer 0, 8, 0, 0, "rx-rdc-grps-begin", "rx_rdc_grps_begin"}, 316a3c5bd6dSspeer 317846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP | 318846a903dSml NXGE_PARAM_DONT_SHOW, 319a3c5bd6dSspeer 0, 8, 0, 0, "rx-rdc-grps", "rx_rdc_grps"}, 320a3c5bd6dSspeer 321846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 322846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 323a3c5bd6dSspeer 0, 15, 0, 0, "default-grp0-rdc", "default_grp0_rdc"}, 324a3c5bd6dSspeer 325846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 326846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 327a3c5bd6dSspeer 0, 15, 2, 0, "default-grp1-rdc", "default_grp1_rdc"}, 328a3c5bd6dSspeer 329846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 330846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 331a3c5bd6dSspeer 0, 15, 4, 0, "default-grp2-rdc", "default_grp2_rdc"}, 332a3c5bd6dSspeer 333846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 334846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 335a3c5bd6dSspeer 0, 15, 6, 0, "default-grp3-rdc", "default_grp3_rdc"}, 336a3c5bd6dSspeer 337846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 338846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 339a3c5bd6dSspeer 0, 15, 8, 0, "default-grp4-rdc", "default_grp4_rdc"}, 340a3c5bd6dSspeer 341846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 342846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 343a3c5bd6dSspeer 0, 15, 10, 0, "default-grp5-rdc", "default_grp5_rdc"}, 344a3c5bd6dSspeer 345846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 346846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 347a3c5bd6dSspeer 0, 15, 12, 0, "default-grp6-rdc", "default_grp6_rdc"}, 348a3c5bd6dSspeer 349846a903dSml { nxge_param_get_generic, nxge_param_set_grp_rdc, 350846a903dSml NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 351a3c5bd6dSspeer 0, 15, 14, 0, "default-grp7-rdc", "default_grp7_rdc"}, 352a3c5bd6dSspeer 353a3c5bd6dSspeer { nxge_param_get_rxdma_rdcgrp_info, NULL, 354846a903dSml NXGE_PARAM_READ | NXGE_PARAM_CMPLX | NXGE_PARAM_DONT_SHOW, 355a3c5bd6dSspeer 0, 8, 0, 0, "rdc-groups-info", "rdc_groups_info"}, 356a3c5bd6dSspeer 357a3c5bd6dSspeer /* Logical device groups */ 358846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 359a3c5bd6dSspeer 0, 63, 0, 0, "start-ldg", "start_ldg"}, 360a3c5bd6dSspeer 361846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 362a3c5bd6dSspeer 0, 64, 0, 0, "max-ldg", "max_ldg" }, 363a3c5bd6dSspeer 364a3c5bd6dSspeer /* MAC table information */ 365a3c5bd6dSspeer { nxge_param_get_mac_rdcgrp, nxge_param_set_mac_rdcgrp, 366846a903dSml NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW, 367a3c5bd6dSspeer 0, 31, 0, 0, "mac-2rdc-grp", "mac_2rdc_grp"}, 368a3c5bd6dSspeer 369a3c5bd6dSspeer /* VLAN table information */ 370a3c5bd6dSspeer { nxge_param_get_vlan_rdcgrp, nxge_param_set_vlan_rdcgrp, 371846a903dSml NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW, 372a3c5bd6dSspeer 0, 31, 0, 0, "vlan-2rdc-grp", "vlan_2rdc_grp"}, 373a3c5bd6dSspeer 374a3c5bd6dSspeer { nxge_param_get_generic, NULL, 375846a903dSml NXGE_PARAM_READ_PROP | NXGE_PARAM_READ | 376846a903dSml NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_DONT_SHOW, 377a3c5bd6dSspeer 0, 0x0ffff, 0x0ffff, 0, "fcram-part-cfg", "fcram_part_cfg"}, 378a3c5bd6dSspeer 379846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS | 380846a903dSml NXGE_PARAM_DONT_SHOW, 381a3c5bd6dSspeer 0, 0x10, 0xa, 0, "fcram-access-ratio", "fcram_access_ratio"}, 382a3c5bd6dSspeer 383846a903dSml { nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS | 384846a903dSml NXGE_PARAM_DONT_SHOW, 385a3c5bd6dSspeer 0, 0x10, 0xa, 0, "tcam-access-ratio", "tcam_access_ratio"}, 386a3c5bd6dSspeer 387a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_tcam_enable, 388846a903dSml NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 389a3c5bd6dSspeer 0, 0x1, 0x0, 0, "tcam-enable", "tcam_enable"}, 390a3c5bd6dSspeer 391a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_hash_lookup_enable, 392846a903dSml NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 393a3c5bd6dSspeer 0, 0x01, 0x0, 0, "hash-lookup-enable", "hash_lookup_enable"}, 394a3c5bd6dSspeer 395a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_llc_snap_enable, 396846a903dSml NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 397a3c5bd6dSspeer 0, 0x01, 0x01, 0, "llc-snap-enable", "llc_snap_enable"}, 398a3c5bd6dSspeer 399a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_fflp_hash_init, 400846a903dSml NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 401a3c5bd6dSspeer 0, ALL_FF_32, ALL_FF_32, 0, "h1-init-value", "h1_init_value"}, 402a3c5bd6dSspeer 403a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_fflp_hash_init, 404846a903dSml NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 405a3c5bd6dSspeer 0, 0x0ffff, 0x0ffff, 0, "h2-init-value", "h2_init_value"}, 406a3c5bd6dSspeer 407a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ether_usr, 408a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 409a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 410a3c5bd6dSspeer "class-cfg-ether-usr1", "class_cfg_ether_usr1"}, 411a3c5bd6dSspeer 412a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ether_usr, 413a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 414a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 415a3c5bd6dSspeer "class-cfg-ether-usr2", "class_cfg_ether_usr2"}, 416a3c5bd6dSspeer 417a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ip_usr, 418a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 419a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 420a3c5bd6dSspeer "class-cfg-ip-usr4", "class_cfg_ip_usr4"}, 421a3c5bd6dSspeer 422a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ip_usr, 423a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 424a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 425a3c5bd6dSspeer "class-cfg-ip-usr5", "class_cfg_ip_usr5"}, 426a3c5bd6dSspeer 427a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ip_usr, 428a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 429a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 430a3c5bd6dSspeer "class-cfg-ip-usr6", "class_cfg_ip_usr6"}, 431a3c5bd6dSspeer 432a3c5bd6dSspeer { nxge_param_get_generic, nxge_param_set_ip_usr, 433a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 434a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 435a3c5bd6dSspeer "class-cfg-ip-usr7", "class_cfg_ip_usr7"}, 436a3c5bd6dSspeer 437a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 438a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 439a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 440a3c5bd6dSspeer "class-opt-ip-usr4", "class_opt_ip_usr4"}, 441a3c5bd6dSspeer 442a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 443a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 444a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 445a3c5bd6dSspeer "class-opt-ip-usr5", "class_opt_ip_usr5"}, 446a3c5bd6dSspeer 447a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 448a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 449a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 450a3c5bd6dSspeer "class-opt-ip-usr6", "class_opt_ip_usr6"}, 451a3c5bd6dSspeer 452a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 453a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 454a3c5bd6dSspeer 0, ALL_FF_32, 0x0, 0, 455a3c5bd6dSspeer "class-opt-ip-usr7", "class_opt_ip_usr7"}, 456a3c5bd6dSspeer 457a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 458a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS, 459a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 460a3c5bd6dSspeer "class-opt-ipv4-tcp", "class_opt_ipv4_tcp"}, 461a3c5bd6dSspeer 462a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 463a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS, 464a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 465a3c5bd6dSspeer "class-opt-ipv4-udp", "class_opt_ipv4_udp"}, 466a3c5bd6dSspeer 467a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 468a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS, 469a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 470a3c5bd6dSspeer "class-opt-ipv4-ah", "class_opt_ipv4_ah"}, 471a3c5bd6dSspeer 472a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 473a3c5bd6dSspeer NXGE_PARAM_CLASS_RWS, 474a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 475a3c5bd6dSspeer "class-opt-ipv4-sctp", "class_opt_ipv4_sctp"}, 476a3c5bd6dSspeer 477a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 478a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 479a3c5bd6dSspeer "class-opt-ipv6-tcp", "class_opt_ipv6_tcp"}, 480a3c5bd6dSspeer 481a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 482a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 483a3c5bd6dSspeer "class-opt-ipv6-udp", "class_opt_ipv6_udp"}, 484a3c5bd6dSspeer 485a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 486a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 487a3c5bd6dSspeer "class-opt-ipv6-ah", "class_opt_ipv6_ah"}, 488a3c5bd6dSspeer 489a3c5bd6dSspeer { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 490a3c5bd6dSspeer 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 491a3c5bd6dSspeer "class-opt-ipv6-sctp", "class_opt_ipv6_sctp"}, 492a3c5bd6dSspeer 493a3c5bd6dSspeer { nxge_param_get_debug_flag, nxge_param_set_nxge_debug_flag, 494846a903dSml NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 495a3c5bd6dSspeer 0ULL, ALL_FF_64, 0ULL, 0ULL, 496a3c5bd6dSspeer "nxge-debug-flag", "nxge_debug_flag"}, 497a3c5bd6dSspeer 498a3c5bd6dSspeer { nxge_param_get_debug_flag, nxge_param_set_npi_debug_flag, 499846a903dSml NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 500a3c5bd6dSspeer 0ULL, ALL_FF_64, 0ULL, 0ULL, 501a3c5bd6dSspeer "npi-debug-flag", "npi_debug_flag"}, 502a3c5bd6dSspeer 503846a903dSml { nxge_param_dump_tdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 504a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "dump-tdc", "dump_tdc"}, 505a3c5bd6dSspeer 506846a903dSml { nxge_param_dump_rdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 507a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "dump-rdc", "dump_rdc"}, 508a3c5bd6dSspeer 509846a903dSml { nxge_param_dump_mac_regs, NULL, NXGE_PARAM_READ | 510846a903dSml NXGE_PARAM_DONT_SHOW, 511a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "dump-mac-regs", "dump_mac_regs"}, 512a3c5bd6dSspeer 513846a903dSml { nxge_param_dump_ipp_regs, NULL, NXGE_PARAM_READ | 514846a903dSml NXGE_PARAM_DONT_SHOW, 515a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "dump-ipp-regs", "dump_ipp_regs"}, 516a3c5bd6dSspeer 517846a903dSml { nxge_param_dump_fflp_regs, NULL, NXGE_PARAM_READ | 518846a903dSml NXGE_PARAM_DONT_SHOW, 519a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, 520a3c5bd6dSspeer "dump-fflp-regs", "dump_fflp_regs"}, 521a3c5bd6dSspeer 522846a903dSml { nxge_param_dump_vlan_table, NULL, NXGE_PARAM_READ | 523846a903dSml NXGE_PARAM_DONT_SHOW, 524a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, 525a3c5bd6dSspeer "dump-vlan-table", "dump_vlan_table"}, 526a3c5bd6dSspeer 527846a903dSml { nxge_param_dump_rdc_table, NULL, NXGE_PARAM_READ | 528846a903dSml NXGE_PARAM_DONT_SHOW, 529a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, 530a3c5bd6dSspeer "dump-rdc-table", "dump_rdc_table"}, 531a3c5bd6dSspeer 532846a903dSml { nxge_param_dump_ptrs, NULL, NXGE_PARAM_READ | 533846a903dSml NXGE_PARAM_DONT_SHOW, 534a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "dump-ptrs", "dump_ptrs"}, 535a3c5bd6dSspeer 536a3c5bd6dSspeer { NULL, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 537a3c5bd6dSspeer 0, 0x0fffffff, 0x0fffffff, 0, "end", "end"}, 53844961713Sgirish }; 53944961713Sgirish 54044961713Sgirish extern void *nxge_list; 54144961713Sgirish 54244961713Sgirish void 54344961713Sgirish nxge_get_param_soft_properties(p_nxge_t nxgep) 54444961713Sgirish { 54544961713Sgirish 54644961713Sgirish p_nxge_param_t param_arr; 54744961713Sgirish uint_t prop_len; 54844961713Sgirish int i, j; 549a3c5bd6dSspeer uint32_t param_count; 550a3c5bd6dSspeer uint32_t *int_prop_val; 55144961713Sgirish 55244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, " ==> nxge_get_param_soft_properties")); 55344961713Sgirish 55444961713Sgirish param_arr = nxgep->param_arr; 55544961713Sgirish param_count = nxgep->param_count; 55644961713Sgirish for (i = 0; i < param_count; i++) { 55744961713Sgirish if ((param_arr[i].type & NXGE_PARAM_READ_PROP) == 0) 55844961713Sgirish continue; 55944961713Sgirish if ((param_arr[i].type & NXGE_PARAM_PROP_STR)) 56044961713Sgirish continue; 56144961713Sgirish if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 562*4045d941Ssowmini (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 56344961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, 564*4045d941Ssowmini nxgep->dip, 0, param_arr[i].fcode_name, 565*4045d941Ssowmini (int **)&int_prop_val, 566*4045d941Ssowmini (uint_t *)&prop_len) 567*4045d941Ssowmini == DDI_PROP_SUCCESS) { 56844961713Sgirish uint32_t *cfg_value; 56944961713Sgirish uint64_t prop_count; 570a3c5bd6dSspeer 57144961713Sgirish if (prop_len > NXGE_PARAM_ARRAY_INIT_SIZE) 57244961713Sgirish prop_len = NXGE_PARAM_ARRAY_INIT_SIZE; 573adfcba55Sjoycey #if defined(__i386) 574adfcba55Sjoycey cfg_value = 575*4045d941Ssowmini (uint32_t *)(int32_t)param_arr[i].value; 576adfcba55Sjoycey #else 57744961713Sgirish cfg_value = (uint32_t *)param_arr[i].value; 578adfcba55Sjoycey #endif 57944961713Sgirish for (j = 0; j < prop_len; j++) { 58044961713Sgirish cfg_value[j] = int_prop_val[j]; 58144961713Sgirish } 58244961713Sgirish prop_count = prop_len; 58344961713Sgirish param_arr[i].type |= 58444961713Sgirish (prop_count << NXGE_PARAM_ARRAY_CNT_SHIFT); 58544961713Sgirish ddi_prop_free(int_prop_val); 58644961713Sgirish } 58744961713Sgirish continue; 58844961713Sgirish } 58944961713Sgirish 59044961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 591*4045d941Ssowmini param_arr[i].fcode_name, 592*4045d941Ssowmini (int **)&int_prop_val, 593*4045d941Ssowmini &prop_len) == DDI_PROP_SUCCESS) { 59444961713Sgirish if ((*int_prop_val >= param_arr[i].minimum) && 595*4045d941Ssowmini (*int_prop_val <= param_arr[i].maximum)) 59644961713Sgirish param_arr[i].value = *int_prop_val; 59744961713Sgirish #ifdef NXGE_DEBUG_ERROR 59844961713Sgirish else { 59944961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL, 600*4045d941Ssowmini "nxge%d: 'prom' file parameter error\n", 601*4045d941Ssowmini nxgep->instance)); 60244961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL, 603*4045d941Ssowmini "Parameter keyword '%s'" 604*4045d941Ssowmini " is outside valid range\n", 605*4045d941Ssowmini param_arr[i].name)); 60644961713Sgirish } 60744961713Sgirish #endif 60844961713Sgirish ddi_prop_free(int_prop_val); 60944961713Sgirish } 61044961713Sgirish 61144961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 612*4045d941Ssowmini param_arr[i].name, 613*4045d941Ssowmini (int **)&int_prop_val, 614*4045d941Ssowmini &prop_len) == DDI_PROP_SUCCESS) { 61544961713Sgirish if ((*int_prop_val >= param_arr[i].minimum) && 616*4045d941Ssowmini (*int_prop_val <= param_arr[i].maximum)) 61744961713Sgirish param_arr[i].value = *int_prop_val; 61844961713Sgirish #ifdef NXGE_DEBUG_ERROR 61944961713Sgirish else { 62044961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL, 621*4045d941Ssowmini "nxge%d: 'conf' file parameter error\n", 622*4045d941Ssowmini nxgep->instance)); 62344961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL, 624*4045d941Ssowmini "Parameter keyword '%s'" 625*4045d941Ssowmini "is outside valid range\n", 626*4045d941Ssowmini param_arr[i].name)); 62744961713Sgirish } 62844961713Sgirish #endif 62944961713Sgirish ddi_prop_free(int_prop_val); 63044961713Sgirish } 63144961713Sgirish } 63244961713Sgirish } 63344961713Sgirish 63444961713Sgirish static int 63544961713Sgirish nxge_private_param_register(p_nxge_t nxgep, p_nxge_param_t param_arr) 63644961713Sgirish { 63744961713Sgirish int status = B_TRUE; 63844961713Sgirish int channel; 63944961713Sgirish uint8_t grp; 64044961713Sgirish char *prop_name; 64144961713Sgirish char *end; 64244961713Sgirish uint32_t name_chars; 64344961713Sgirish 64444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 645*4045d941Ssowmini "nxge_private_param_register %s", param_arr->name)); 64644961713Sgirish 64744961713Sgirish if ((param_arr->type & NXGE_PARAM_PRIV) != NXGE_PARAM_PRIV) 64844961713Sgirish return (B_TRUE); 649a3c5bd6dSspeer 65044961713Sgirish prop_name = param_arr->name; 65144961713Sgirish if (param_arr->type & NXGE_PARAM_RXDMA) { 65244961713Sgirish if (strncmp("rxdma_intr", prop_name, 10) == 0) 65344961713Sgirish return (B_TRUE); 65444961713Sgirish name_chars = strlen("default_grp"); 65544961713Sgirish if (strncmp("default_grp", prop_name, name_chars) == 0) { 65644961713Sgirish prop_name += name_chars; 65744961713Sgirish grp = mi_strtol(prop_name, &end, 10); 65844961713Sgirish /* now check if this rdcgrp is in config */ 65944961713Sgirish return (nxge_check_rdcgrp_port_member(nxgep, grp)); 66044961713Sgirish } 66144961713Sgirish name_chars = strlen(prop_name); 66244961713Sgirish if (strncmp("default_port_rdc", prop_name, name_chars) == 0) { 66344961713Sgirish return (B_TRUE); 66444961713Sgirish } 66544961713Sgirish return (B_FALSE); 66644961713Sgirish } 66744961713Sgirish 66844961713Sgirish if (param_arr->type & NXGE_PARAM_TXDMA) { 66944961713Sgirish name_chars = strlen("txdma"); 67044961713Sgirish if (strncmp("txdma", prop_name, name_chars) == 0) { 67144961713Sgirish prop_name += name_chars; 67244961713Sgirish channel = mi_strtol(prop_name, &end, 10); 67344961713Sgirish /* now check if this rdc is in config */ 67444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 675*4045d941Ssowmini " nxge_private_param_register: %d", 676*4045d941Ssowmini channel)); 67744961713Sgirish return (nxge_check_txdma_port_member(nxgep, channel)); 67844961713Sgirish } 67944961713Sgirish return (B_FALSE); 68044961713Sgirish } 68144961713Sgirish 68244961713Sgirish status = B_FALSE; 68344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD2_CTL, "<== nxge_private_param_register")); 68444961713Sgirish 68544961713Sgirish return (status); 68644961713Sgirish } 68744961713Sgirish 68844961713Sgirish void 68944961713Sgirish nxge_setup_param(p_nxge_t nxgep) 69044961713Sgirish { 69144961713Sgirish p_nxge_param_t param_arr; 69244961713Sgirish int i; 69344961713Sgirish pfi_t set_pfi; 69444961713Sgirish 69544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_setup_param")); 696a3c5bd6dSspeer 69744961713Sgirish /* 69844961713Sgirish * Make sure the param_instance is set to a valid device instance. 69944961713Sgirish */ 70044961713Sgirish if (nxge_param_arr[param_instance].value == 1000) 70144961713Sgirish nxge_param_arr[param_instance].value = nxgep->instance; 70244961713Sgirish 70344961713Sgirish param_arr = nxgep->param_arr; 70444961713Sgirish param_arr[param_instance].value = nxgep->instance; 70544961713Sgirish param_arr[param_function_number].value = nxgep->function_num; 70644961713Sgirish 70744961713Sgirish for (i = 0; i < nxgep->param_count; i++) { 70844961713Sgirish if ((param_arr[i].type & NXGE_PARAM_PRIV) && 709*4045d941Ssowmini (nxge_private_param_register(nxgep, 710*4045d941Ssowmini ¶m_arr[i]) == B_FALSE)) { 71144961713Sgirish param_arr[i].setf = NULL; 71244961713Sgirish param_arr[i].getf = NULL; 71344961713Sgirish } 71444961713Sgirish 71544961713Sgirish if (param_arr[i].type & NXGE_PARAM_CMPLX) 71644961713Sgirish param_arr[i].setf = NULL; 71744961713Sgirish 71844961713Sgirish if (param_arr[i].type & NXGE_PARAM_DONT_SHOW) { 71944961713Sgirish param_arr[i].setf = NULL; 72044961713Sgirish param_arr[i].getf = NULL; 72144961713Sgirish } 72244961713Sgirish 72344961713Sgirish set_pfi = (pfi_t)param_arr[i].setf; 72444961713Sgirish 725a3c5bd6dSspeer if ((set_pfi) && (param_arr[i].type & NXGE_PARAM_INIT_ONLY)) { 72644961713Sgirish set_pfi = NULL; 72744961713Sgirish } 72844961713Sgirish 72944961713Sgirish } 73044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_setup_param")); 73144961713Sgirish } 73244961713Sgirish 73344961713Sgirish void 73444961713Sgirish nxge_init_param(p_nxge_t nxgep) 73544961713Sgirish { 73644961713Sgirish p_nxge_param_t param_arr; 73744961713Sgirish int i, alloc_size; 73844961713Sgirish uint64_t alloc_count; 73944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_init_param")); 74044961713Sgirish /* 74144961713Sgirish * Make sure the param_instance is set to a valid device instance. 74244961713Sgirish */ 74344961713Sgirish if (nxge_param_arr[param_instance].value == 1000) 74444961713Sgirish nxge_param_arr[param_instance].value = nxgep->instance; 74544961713Sgirish 74644961713Sgirish param_arr = nxgep->param_arr; 74744961713Sgirish if (param_arr == NULL) { 748a3c5bd6dSspeer param_arr = (p_nxge_param_t) 749*4045d941Ssowmini KMEM_ZALLOC(sizeof (nxge_param_arr), KM_SLEEP); 75044961713Sgirish } 751a3c5bd6dSspeer 75244961713Sgirish for (i = 0; i < sizeof (nxge_param_arr)/sizeof (nxge_param_t); i++) { 75344961713Sgirish param_arr[i] = nxge_param_arr[i]; 75444961713Sgirish if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 755*4045d941Ssowmini (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 75644961713Sgirish alloc_count = NXGE_PARAM_ARRAY_INIT_SIZE; 75744961713Sgirish alloc_size = alloc_count * sizeof (uint64_t); 75844961713Sgirish param_arr[i].value = 759adfcba55Sjoycey #if defined(__i386) 760*4045d941Ssowmini (uint64_t)(uint32_t)KMEM_ZALLOC(alloc_size, 761*4045d941Ssowmini KM_SLEEP); 762adfcba55Sjoycey #else 7631bd6825cSml (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP); 764adfcba55Sjoycey #endif 76544961713Sgirish param_arr[i].old_value = 766adfcba55Sjoycey #if defined(__i386) 767*4045d941Ssowmini (uint64_t)(uint32_t)KMEM_ZALLOC(alloc_size, 768*4045d941Ssowmini KM_SLEEP); 769adfcba55Sjoycey #else 770*4045d941Ssowmini (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP); 771adfcba55Sjoycey #endif 77244961713Sgirish param_arr[i].type |= 773*4045d941Ssowmini (alloc_count << NXGE_PARAM_ARRAY_ALLOC_SHIFT); 77444961713Sgirish } 77544961713Sgirish } 77644961713Sgirish 77744961713Sgirish nxgep->param_arr = param_arr; 77844961713Sgirish nxgep->param_count = sizeof (nxge_param_arr)/sizeof (nxge_param_t); 7791bd6825cSml 7801bd6825cSml nxge_param_sync(nxgep); 7811bd6825cSml 78244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_init_param: count %d", 783*4045d941Ssowmini nxgep->param_count)); 78444961713Sgirish } 78544961713Sgirish 78644961713Sgirish void 78744961713Sgirish nxge_destroy_param(p_nxge_t nxgep) 78844961713Sgirish { 78944961713Sgirish int i; 79044961713Sgirish uint64_t free_size, free_count; 79144961713Sgirish 79244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_param")); 793a3c5bd6dSspeer 79459ac0c16Sdavemq if (nxgep->param_arr == NULL) 79559ac0c16Sdavemq return; 79644961713Sgirish /* 79744961713Sgirish * Make sure the param_instance is set to a valid device instance. 79844961713Sgirish */ 79944961713Sgirish if (nxge_param_arr[param_instance].value == nxgep->instance) { 80044961713Sgirish for (i = 0; i <= nxge_param_arr[param_instance].maximum; i++) { 80144961713Sgirish if ((ddi_get_soft_state(nxge_list, i) != NULL) && 802*4045d941Ssowmini (i != nxgep->instance)) 80344961713Sgirish break; 80444961713Sgirish } 80544961713Sgirish nxge_param_arr[param_instance].value = i; 80644961713Sgirish } 80744961713Sgirish 80844961713Sgirish for (i = 0; i < nxgep->param_count; i++) 80944961713Sgirish if ((nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 810*4045d941Ssowmini (nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 81144961713Sgirish free_count = ((nxgep->param_arr[i].type & 812*4045d941Ssowmini NXGE_PARAM_ARRAY_ALLOC_MASK) >> 813*4045d941Ssowmini NXGE_PARAM_ARRAY_ALLOC_SHIFT); 81444961713Sgirish free_count = NXGE_PARAM_ARRAY_INIT_SIZE; 81544961713Sgirish free_size = sizeof (uint64_t) * free_count; 816adfcba55Sjoycey #if defined(__i386) 817adfcba55Sjoycey KMEM_FREE((void *)(uint32_t)nxgep->param_arr[i].value, 818*4045d941Ssowmini free_size); 819adfcba55Sjoycey #else 82044961713Sgirish KMEM_FREE((void *)nxgep->param_arr[i].value, free_size); 821adfcba55Sjoycey #endif 822adfcba55Sjoycey #if defined(__i386) 823adfcba55Sjoycey KMEM_FREE((void *)(uint32_t) 824*4045d941Ssowmini nxgep->param_arr[i].old_value, free_size); 825adfcba55Sjoycey #else 82644961713Sgirish KMEM_FREE((void *)nxgep->param_arr[i].old_value, 827*4045d941Ssowmini free_size); 828adfcba55Sjoycey #endif 82944961713Sgirish } 83044961713Sgirish 83144961713Sgirish KMEM_FREE(nxgep->param_arr, sizeof (nxge_param_arr)); 83244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_param")); 83344961713Sgirish } 83444961713Sgirish 83544961713Sgirish /* 83644961713Sgirish * Extracts the value from the 'nxge' parameter array and prints the 83744961713Sgirish * parameter value. cp points to the required parameter. 83844961713Sgirish */ 839a3c5bd6dSspeer 84044961713Sgirish /* ARGSUSED */ 84144961713Sgirish int 84244961713Sgirish nxge_param_get_generic(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 84344961713Sgirish { 84444961713Sgirish p_nxge_param_t pa = (p_nxge_param_t)cp; 84544961713Sgirish 846a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, NDD_CTL, 847*4045d941Ssowmini "==> nxge_param_get_generic name %s ", pa->name)); 84844961713Sgirish 84944961713Sgirish if (pa->value > 0xffffffff) 850a3c5bd6dSspeer (void) mi_mpprintf(mp, "%x%x", 851*4045d941Ssowmini (int)(pa->value >> 32), (int)(pa->value & 0xffffffff)); 85244961713Sgirish else 85344961713Sgirish (void) mi_mpprintf(mp, "%x", (int)pa->value); 85444961713Sgirish 85544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_generic")); 85644961713Sgirish return (0); 85744961713Sgirish } 85844961713Sgirish 85944961713Sgirish /* ARGSUSED */ 86044961713Sgirish static int 86144961713Sgirish nxge_param_get_mac(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 86244961713Sgirish { 86344961713Sgirish p_nxge_param_t pa = (p_nxge_param_t)cp; 86444961713Sgirish 86544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac")); 86644961713Sgirish 86744961713Sgirish (void) mi_mpprintf(mp, "%d", (uint32_t)pa->value); 86844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_mac")); 86944961713Sgirish return (0); 87044961713Sgirish } 87144961713Sgirish 87256d930aeSspeer /* ARGSUSED */ 87356d930aeSspeer static int 87456d930aeSspeer nxge_param_get_fw_ver(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 87556d930aeSspeer { 87656d930aeSspeer NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_fw_ver")); 87756d930aeSspeer 87856d930aeSspeer (void) mi_mpprintf(mp, "Firmware version for nxge%d: %s\n", 87956d930aeSspeer nxgep->instance, nxgep->vpd_info.ver); 88056d930aeSspeer 88156d930aeSspeer NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_fw_ver")); 88256d930aeSspeer return (0); 88356d930aeSspeer } 88456d930aeSspeer 8852e59129aSraghus /* ARGSUSED */ 8862e59129aSraghus static int 8872e59129aSraghus nxge_param_get_port_mode(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 8882e59129aSraghus { 8892e59129aSraghus NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_port_mode")); 8902e59129aSraghus 8912e59129aSraghus switch (nxgep->mac.portmode) { 8922e59129aSraghus case PORT_1G_COPPER: 8932d17280bSsbehera (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Copper %s\n", 8942d17280bSsbehera nxgep->instance, 8952d17280bSsbehera nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 8962e59129aSraghus break; 8972e59129aSraghus case PORT_1G_FIBER: 8982d17280bSsbehera (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Fiber %s\n", 8992d17280bSsbehera nxgep->instance, 9002d17280bSsbehera nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 9012e59129aSraghus break; 9022e59129aSraghus case PORT_10G_COPPER: 9032d17280bSsbehera (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Copper " 9042d17280bSsbehera "%s\n", nxgep->instance, 9052d17280bSsbehera nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 9062e59129aSraghus break; 9072e59129aSraghus case PORT_10G_FIBER: 9082d17280bSsbehera (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Fiber %s\n", 9092d17280bSsbehera nxgep->instance, 9102d17280bSsbehera nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 9112e59129aSraghus break; 9122e59129aSraghus case PORT_10G_SERDES: 9132d17280bSsbehera (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Serdes " 9142d17280bSsbehera "%s\n", nxgep->instance, 9152d17280bSsbehera nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 9162e59129aSraghus break; 9172e59129aSraghus case PORT_1G_SERDES: 9182d17280bSsbehera (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Serdes %s\n", 9192d17280bSsbehera nxgep->instance, 9202d17280bSsbehera nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 9212e59129aSraghus break; 9222e59129aSraghus case PORT_1G_RGMII_FIBER: 9232e59129aSraghus (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G RGMII " 9242d17280bSsbehera "Fiber %s\n", nxgep->instance, 9252d17280bSsbehera nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 9262d17280bSsbehera break; 9272d17280bSsbehera case PORT_HSP_MODE: 9282d17280bSsbehera (void) mi_mpprintf(mp, "Port mode for nxge%d: Hot Swappable " 9292d17280bSsbehera "PHY, Currently NOT present\n", nxgep->instance); 9302e59129aSraghus break; 9312e59129aSraghus default: 9322d17280bSsbehera (void) mi_mpprintf(mp, "Port mode for nxge%d: Unknown %s\n", 9332d17280bSsbehera nxgep->instance, 9342d17280bSsbehera nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 9352e59129aSraghus break; 9362e59129aSraghus } 9372e59129aSraghus 9383d16f8e7Sml (void) mi_mpprintf(mp, "Software LSO for nxge%d: %s\n", 9393d16f8e7Sml nxgep->instance, 9403d16f8e7Sml nxgep->soft_lso_enable ? "enable" : "disable"); 9413d16f8e7Sml 9422e59129aSraghus NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_port_mode")); 9432e59129aSraghus return (0); 9442e59129aSraghus } 9452e59129aSraghus 94644961713Sgirish /* ARGSUSED */ 94744961713Sgirish int 94844961713Sgirish nxge_param_get_txdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 94944961713Sgirish { 95044961713Sgirish 951678453a8Sspeer uint_t print_len, buf_len; 95244961713Sgirish p_mblk_t np; 95344961713Sgirish 95444961713Sgirish int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 955678453a8Sspeer int tdc; 956678453a8Sspeer 957678453a8Sspeer nxge_grp_set_t *set; 958678453a8Sspeer 95944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_txdma_info")); 96044961713Sgirish 961a3c5bd6dSspeer (void) mi_mpprintf(mp, "TXDMA Information for Port\t %d \n", 962*4045d941Ssowmini nxgep->function_num); 96344961713Sgirish 96444961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 96544961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 96644961713Sgirish return (0); 96744961713Sgirish } 96844961713Sgirish 96944961713Sgirish buf_len = buff_alloc_size; 97044961713Sgirish mp->b_cont = np; 971678453a8Sspeer print_len = 0; 97244961713Sgirish 97344961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 97444961713Sgirish buf_len -= print_len; 97544961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 976*4045d941Ssowmini "TDC\t HW TDC\t\n"); 97744961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 97844961713Sgirish buf_len -= print_len; 979678453a8Sspeer 980678453a8Sspeer set = &nxgep->tx_set; 981678453a8Sspeer for (tdc = 0; tdc < NXGE_MAX_RDCS; tdc++) { 982678453a8Sspeer if ((1 << tdc) & set->owned.map) { 983678453a8Sspeer print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 984678453a8Sspeer buf_len, "%d\n", tdc); 985678453a8Sspeer ((mblk_t *)np)->b_wptr += print_len; 986678453a8Sspeer buf_len -= print_len; 987678453a8Sspeer } 98844961713Sgirish } 989a3c5bd6dSspeer 99044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_txdma_info")); 99144961713Sgirish return (0); 99244961713Sgirish } 99344961713Sgirish 99444961713Sgirish /* ARGSUSED */ 99544961713Sgirish int 99644961713Sgirish nxge_param_get_rxdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 99744961713Sgirish { 998a3c5bd6dSspeer uint_t print_len, buf_len; 999a3c5bd6dSspeer p_mblk_t np; 1000a3c5bd6dSspeer int rdc; 100144961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 100244961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 1003a3c5bd6dSspeer int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 100444961713Sgirish p_rx_rcr_rings_t rx_rcr_rings; 100544961713Sgirish p_rx_rcr_ring_t *rcr_rings; 100644961713Sgirish p_rx_rbr_rings_t rx_rbr_rings; 100744961713Sgirish p_rx_rbr_ring_t *rbr_rings; 1008678453a8Sspeer nxge_grp_set_t *set; 100944961713Sgirish 101044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rxdma_info")); 101144961713Sgirish 1012a3c5bd6dSspeer (void) mi_mpprintf(mp, "RXDMA Information for Port\t %d \n", 1013*4045d941Ssowmini nxgep->function_num); 101444961713Sgirish 101544961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 101644961713Sgirish /* The following may work even if we cannot get a large buf. */ 101744961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 101844961713Sgirish return (0); 101944961713Sgirish } 102044961713Sgirish 102144961713Sgirish buf_len = buff_alloc_size; 102244961713Sgirish mp->b_cont = np; 102344961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 102444961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 102544961713Sgirish 102644961713Sgirish rx_rcr_rings = nxgep->rx_rcr_rings; 102744961713Sgirish rcr_rings = rx_rcr_rings->rcr_rings; 102844961713Sgirish rx_rbr_rings = nxgep->rx_rbr_rings; 102944961713Sgirish rbr_rings = rx_rbr_rings->rbr_rings; 103044961713Sgirish 103144961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1032*4045d941Ssowmini "Total RDCs\t %d\n", p_cfgp->max_rdcs); 103344961713Sgirish 103444961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 103544961713Sgirish buf_len -= print_len; 103644961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1037*4045d941Ssowmini "RDC\t HW RDC\t Timeout\t Packets RBR ptr \t" 1038*4045d941Ssowmini "chunks\t RCR ptr\n"); 1039a3c5bd6dSspeer 104044961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 104144961713Sgirish buf_len -= print_len; 1042678453a8Sspeer 1043678453a8Sspeer set = &nxgep->rx_set; 1044678453a8Sspeer for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 1045678453a8Sspeer if ((1 << rdc) & set->owned.map) { 1046678453a8Sspeer print_len = snprintf((char *) 1047678453a8Sspeer ((mblk_t *)np)->b_wptr, buf_len, 1048678453a8Sspeer " %d\t %x\t\t %x\t $%p\t 0x%x\t $%p\n", 1049678453a8Sspeer rdc, 1050678453a8Sspeer p_dma_cfgp->rcr_timeout[rdc], 1051678453a8Sspeer p_dma_cfgp->rcr_threshold[rdc], 1052678453a8Sspeer rbr_rings[rdc], 1053678453a8Sspeer rbr_rings[rdc]->num_blocks, rcr_rings[rdc]); 1054a3c5bd6dSspeer ((mblk_t *)np)->b_wptr += print_len; 1055a3c5bd6dSspeer buf_len -= print_len; 1056678453a8Sspeer } 105744961713Sgirish } 1058a3c5bd6dSspeer 105944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rxdma_info")); 106044961713Sgirish return (0); 106144961713Sgirish } 106244961713Sgirish 106344961713Sgirish /* ARGSUSED */ 106444961713Sgirish int 106544961713Sgirish nxge_param_get_rxdma_rdcgrp_info(p_nxge_t nxgep, queue_t *q, 1066a3c5bd6dSspeer p_mblk_t mp, caddr_t cp) 106744961713Sgirish { 1068a3c5bd6dSspeer uint_t print_len, buf_len; 1069a3c5bd6dSspeer p_mblk_t np; 1070a3c5bd6dSspeer int offset, rdc, i, rdc_grp; 107144961713Sgirish p_nxge_rdc_grp_t rdc_grp_p; 107244961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 107344961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 107444961713Sgirish 107544961713Sgirish int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 107644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1077*4045d941Ssowmini "==> nxge_param_get_rxdma_rdcgrp_info")); 107844961713Sgirish 107944961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 108044961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 108144961713Sgirish 1082a3c5bd6dSspeer (void) mi_mpprintf(mp, "RXDMA RDC Group Information for Port\t %d \n", 1083*4045d941Ssowmini nxgep->function_num); 108444961713Sgirish 1085678453a8Sspeer rdc_grp = p_cfgp->def_mac_rxdma_grpid; 108644961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 108744961713Sgirish /* The following may work even if we cannot get a large buf. */ 108844961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 108944961713Sgirish return (0); 109044961713Sgirish } 109144961713Sgirish 109244961713Sgirish buf_len = buff_alloc_size; 109344961713Sgirish mp->b_cont = np; 109444961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1095*4045d941Ssowmini "Total RDC Groups\t %d \n" 1096*4045d941Ssowmini "default RDC group\t %d\n", 1097*4045d941Ssowmini p_cfgp->max_rdc_grpids, 1098*4045d941Ssowmini p_cfgp->def_mac_rxdma_grpid); 109944961713Sgirish 110044961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 110144961713Sgirish buf_len -= print_len; 110244961713Sgirish 1103678453a8Sspeer for (i = 0; i < NXGE_MAX_RDCS; i++) { 1104678453a8Sspeer if (p_cfgp->grpids[i]) { 1105678453a8Sspeer rdc_grp_p = &p_dma_cfgp->rdc_grps[i]; 110644961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1107678453a8Sspeer buf_len, 1108678453a8Sspeer "\nRDC Group Info for Group [%d] %d\n" 1109678453a8Sspeer "RDC Count %d\tstart RDC %d\n" 1110678453a8Sspeer "RDC Group Population Information" 1111678453a8Sspeer " (offsets 0 - 15)\n", 1112678453a8Sspeer i, rdc_grp, rdc_grp_p->max_rdcs, 1113678453a8Sspeer rdc_grp_p->start_rdc); 1114678453a8Sspeer 1115678453a8Sspeer ((mblk_t *)np)->b_wptr += print_len; 1116678453a8Sspeer buf_len -= print_len; 1117678453a8Sspeer print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1118678453a8Sspeer buf_len, "\n"); 1119678453a8Sspeer ((mblk_t *)np)->b_wptr += print_len; 1120678453a8Sspeer buf_len -= print_len; 1121678453a8Sspeer 1122678453a8Sspeer for (rdc = 0; rdc < rdc_grp_p->max_rdcs; rdc++) { 1123678453a8Sspeer print_len = snprintf( 1124*4045d941Ssowmini (char *)((mblk_t *)np)->b_wptr, 1125*4045d941Ssowmini buf_len, "[%d]=%d ", rdc, 1126*4045d941Ssowmini rdc_grp_p->start_rdc + rdc); 1127678453a8Sspeer ((mblk_t *)np)->b_wptr += print_len; 1128678453a8Sspeer buf_len -= print_len; 1129678453a8Sspeer } 1130678453a8Sspeer print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1131678453a8Sspeer buf_len, "\n"); 113244961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 113344961713Sgirish buf_len -= print_len; 113444961713Sgirish 1135678453a8Sspeer for (offset = 0; offset < 16; offset++) { 1136678453a8Sspeer print_len = snprintf( 1137*4045d941Ssowmini (char *)((mblk_t *)np)->b_wptr, 1138*4045d941Ssowmini buf_len, " %c", 1139*4045d941Ssowmini rdc_grp_p->map & (1 << offset) ? 1140*4045d941Ssowmini '1' : '0'); 1141678453a8Sspeer ((mblk_t *)np)->b_wptr += print_len; 1142678453a8Sspeer buf_len -= print_len; 1143678453a8Sspeer } 114444961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1145678453a8Sspeer buf_len, "\n"); 114644961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 114744961713Sgirish buf_len -= print_len; 114844961713Sgirish } 114944961713Sgirish } 115044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1151*4045d941Ssowmini "<== nxge_param_get_rxdma_rdcgrp_info")); 115244961713Sgirish return (0); 115344961713Sgirish } 115444961713Sgirish 115544961713Sgirish int 115644961713Sgirish nxge_mk_mblk_tail_space(p_mblk_t mp, p_mblk_t *nmp, size_t size) 115744961713Sgirish { 115844961713Sgirish p_mblk_t tmp; 115944961713Sgirish 116044961713Sgirish tmp = mp; 116144961713Sgirish while (tmp->b_cont) 116244961713Sgirish tmp = tmp->b_cont; 116344961713Sgirish if ((tmp->b_wptr + size) >= tmp->b_datap->db_lim) { 116444961713Sgirish tmp->b_cont = allocb(1024, BPRI_HI); 116544961713Sgirish tmp = tmp->b_cont; 116644961713Sgirish if (!tmp) 116744961713Sgirish return (ENOMEM); 116844961713Sgirish } 1169a3c5bd6dSspeer 117044961713Sgirish *nmp = tmp; 117144961713Sgirish return (0); 117244961713Sgirish } 117344961713Sgirish 1174a3c5bd6dSspeer 117544961713Sgirish /* ARGSUSED */ 117644961713Sgirish int 117744961713Sgirish nxge_param_set_generic(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 117844961713Sgirish char *value, caddr_t cp) 117944961713Sgirish { 118044961713Sgirish char *end; 118144961713Sgirish uint32_t new_value; 118244961713Sgirish p_nxge_param_t pa = (p_nxge_param_t)cp; 118344961713Sgirish 118444961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, " ==> nxge_param_set_generic")); 118544961713Sgirish new_value = (uint32_t)mi_strtol(value, &end, 10); 118644961713Sgirish if (end == value || new_value < pa->minimum || 1187*4045d941Ssowmini new_value > pa->maximum) { 118844961713Sgirish return (EINVAL); 118944961713Sgirish } 119044961713Sgirish pa->value = new_value; 119144961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, " <== nxge_param_set_generic")); 119244961713Sgirish return (0); 119344961713Sgirish } 119444961713Sgirish 119544961713Sgirish 1196a3c5bd6dSspeer /* ARGSUSED */ 119744961713Sgirish int 1198a3c5bd6dSspeer nxge_param_set_instance(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1199a3c5bd6dSspeer char *value, caddr_t cp) 120044961713Sgirish { 120144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " ==> nxge_param_set_instance")); 120244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_set_instance")); 120344961713Sgirish return (0); 120444961713Sgirish } 120544961713Sgirish 120644961713Sgirish 1207a3c5bd6dSspeer /* ARGSUSED */ 120844961713Sgirish int 1209a3c5bd6dSspeer nxge_param_set_mac(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1210a3c5bd6dSspeer char *value, caddr_t cp) 121144961713Sgirish { 1212a3c5bd6dSspeer char *end; 1213a3c5bd6dSspeer uint32_t new_value; 1214a3c5bd6dSspeer int status = 0; 1215a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 121644961713Sgirish 121744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac")); 121844961713Sgirish new_value = (uint32_t)mi_strtol(value, &end, BASE_DECIMAL); 121944961713Sgirish if (PARAM_OUTOF_RANGE(value, end, new_value, pa)) { 122044961713Sgirish return (EINVAL); 122144961713Sgirish } 122244961713Sgirish 122344961713Sgirish if (pa->value != new_value) { 122444961713Sgirish pa->old_value = pa->value; 122544961713Sgirish pa->value = new_value; 122644961713Sgirish } 122744961713Sgirish 122844961713Sgirish if (!nxge_param_link_update(nxgep)) { 122944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1230*4045d941Ssowmini " false ret from nxge_param_link_update")); 123144961713Sgirish status = EINVAL; 123244961713Sgirish } 123344961713Sgirish 123444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac")); 123544961713Sgirish return (status); 123644961713Sgirish } 123744961713Sgirish 123844961713Sgirish /* ARGSUSED */ 12391bd6825cSml int 1240a3c5bd6dSspeer nxge_param_rx_intr_pkts(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1241a3c5bd6dSspeer char *value, caddr_t cp) 124244961713Sgirish { 1243a3c5bd6dSspeer char *end; 1244a3c5bd6dSspeer uint32_t cfg_value; 1245a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 124614ea4bb7Ssd 124744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_pkts")); 124844961713Sgirish 124914ea4bb7Ssd cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 125044961713Sgirish 125114ea4bb7Ssd if ((cfg_value > NXGE_RDC_RCR_THRESHOLD_MAX) || 1252*4045d941Ssowmini (cfg_value < NXGE_RDC_RCR_THRESHOLD_MIN)) { 125344961713Sgirish return (EINVAL); 125444961713Sgirish } 125514ea4bb7Ssd 125614ea4bb7Ssd if ((pa->value != cfg_value)) { 125714ea4bb7Ssd pa->old_value = pa->value; 125814ea4bb7Ssd pa->value = cfg_value; 125914ea4bb7Ssd nxgep->intr_threshold = pa->value; 126044961713Sgirish } 126114ea4bb7Ssd 126244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_pkts")); 126344961713Sgirish return (0); 126444961713Sgirish } 126544961713Sgirish 126644961713Sgirish /* ARGSUSED */ 12671bd6825cSml int 1268a3c5bd6dSspeer nxge_param_rx_intr_time(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1269a3c5bd6dSspeer char *value, caddr_t cp) 127044961713Sgirish { 1271a3c5bd6dSspeer char *end; 1272a3c5bd6dSspeer uint32_t cfg_value; 1273a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 127444961713Sgirish 127544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_time")); 127644961713Sgirish 127714ea4bb7Ssd cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 127844961713Sgirish 127914ea4bb7Ssd if ((cfg_value > NXGE_RDC_RCR_TIMEOUT_MAX) || 1280*4045d941Ssowmini (cfg_value < NXGE_RDC_RCR_TIMEOUT_MIN)) { 128144961713Sgirish return (EINVAL); 128244961713Sgirish } 128344961713Sgirish 128414ea4bb7Ssd if ((pa->value != cfg_value)) { 128514ea4bb7Ssd pa->old_value = pa->value; 128614ea4bb7Ssd pa->value = cfg_value; 128714ea4bb7Ssd nxgep->intr_timeout = pa->value; 128844961713Sgirish } 128944961713Sgirish 129044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_time")); 129144961713Sgirish return (0); 129244961713Sgirish } 129344961713Sgirish 129444961713Sgirish /* ARGSUSED */ 129544961713Sgirish static int 129644961713Sgirish nxge_param_set_mac_rdcgrp(p_nxge_t nxgep, queue_t *q, 1297a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 129844961713Sgirish { 1299a3c5bd6dSspeer char *end; 1300a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1301a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1302a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 130344961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 130444961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 1305a3c5bd6dSspeer uint32_t *val_ptr, *old_val_ptr; 1306a3c5bd6dSspeer nxge_param_map_t *mac_map; 1307a3c5bd6dSspeer p_nxge_class_pt_cfg_t p_class_cfgp; 1308a3c5bd6dSspeer nxge_mv_cfg_t *mac_host_info; 130944961713Sgirish 131044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac_rdcgrp ")); 131144961713Sgirish 131244961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 131344961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 131444961713Sgirish p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 131544961713Sgirish mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 131644961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1317a3c5bd6dSspeer 1318a3c5bd6dSspeer /* 1319a3c5bd6dSspeer * now do decoding 1320a3c5bd6dSspeer */ 132144961713Sgirish mac_map = (nxge_param_map_t *)&cfg_value; 1322a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, NDD_CTL, " cfg_value %x id %x map_to %x", 1323*4045d941Ssowmini cfg_value, mac_map->param_id, mac_map->map_to)); 132444961713Sgirish 132544961713Sgirish if ((mac_map->param_id < p_cfgp->max_macs) && 1326678453a8Sspeer p_cfgp->grpids[mac_map->map_to]) { 132744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1328678453a8Sspeer " nxge_param_set_mac_rdcgrp mapping" 1329678453a8Sspeer " id %d grp %d", mac_map->param_id, mac_map->map_to)); 1330adfcba55Sjoycey #if defined(__i386) 1331adfcba55Sjoycey val_ptr = (uint32_t *)(uint32_t)pa->value; 1332adfcba55Sjoycey #else 133344961713Sgirish val_ptr = (uint32_t *)pa->value; 1334adfcba55Sjoycey #endif 1335adfcba55Sjoycey #if defined(__i386) 1336adfcba55Sjoycey old_val_ptr = (uint32_t *)(uint32_t)pa->old_value; 1337adfcba55Sjoycey #else 133844961713Sgirish old_val_ptr = (uint32_t *)pa->old_value; 1339adfcba55Sjoycey #endif 134044961713Sgirish if (val_ptr[mac_map->param_id] != cfg_value) { 134144961713Sgirish old_val_ptr[mac_map->param_id] = 1342678453a8Sspeer val_ptr[mac_map->param_id]; 134344961713Sgirish val_ptr[mac_map->param_id] = cfg_value; 134444961713Sgirish mac_host_info[mac_map->param_id].mpr_npr = 1345678453a8Sspeer mac_map->pref; 134644961713Sgirish mac_host_info[mac_map->param_id].flag = 1; 134744961713Sgirish mac_host_info[mac_map->param_id].rdctbl = 1348678453a8Sspeer mac_map->map_to; 134944961713Sgirish cfg_it = B_TRUE; 135044961713Sgirish } 135144961713Sgirish } else { 135244961713Sgirish return (EINVAL); 135344961713Sgirish } 135444961713Sgirish 135544961713Sgirish if (cfg_it == B_TRUE) { 135644961713Sgirish status = nxge_logical_mac_assign_rdc_table(nxgep, 1357678453a8Sspeer (uint8_t)mac_map->param_id); 135844961713Sgirish if (status != NXGE_OK) 135944961713Sgirish return (EINVAL); 136044961713Sgirish } 136144961713Sgirish 136244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac_rdcgrp")); 136344961713Sgirish return (0); 136444961713Sgirish } 136544961713Sgirish 136644961713Sgirish /* ARGSUSED */ 136744961713Sgirish static int 136844961713Sgirish nxge_param_set_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q, 1369a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 137044961713Sgirish { 1371a3c5bd6dSspeer char *end; 1372a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1373a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1374a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 137544961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 137644961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 1377a3c5bd6dSspeer uint32_t *val_ptr, *old_val_ptr; 1378a3c5bd6dSspeer nxge_param_map_t *vmap, *old_map; 1379a3c5bd6dSspeer p_nxge_class_pt_cfg_t p_class_cfgp; 1380a3c5bd6dSspeer uint64_t cfgd_vlans; 1381a3c5bd6dSspeer int i, inc = 0, cfg_position; 1382a3c5bd6dSspeer nxge_mv_cfg_t *vlan_tbl; 138344961713Sgirish 138444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp ")); 138544961713Sgirish 138644961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 138744961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 138844961713Sgirish p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 138944961713Sgirish vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 139044961713Sgirish 139144961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1392a3c5bd6dSspeer 1393a3c5bd6dSspeer /* now do decoding */ 139444961713Sgirish cfgd_vlans = ((pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >> 1395*4045d941Ssowmini NXGE_PARAM_ARRAY_CNT_SHIFT); 139644961713Sgirish 139744961713Sgirish if (cfgd_vlans == NXGE_PARAM_ARRAY_INIT_SIZE) { 139844961713Sgirish /* 139944961713Sgirish * for now, we process only upto max 140044961713Sgirish * NXGE_PARAM_ARRAY_INIT_SIZE parameters 140144961713Sgirish * In the future, we may want to expand 140244961713Sgirish * the storage array and continue 140344961713Sgirish */ 140444961713Sgirish return (EINVAL); 140544961713Sgirish } 1406a3c5bd6dSspeer 140744961713Sgirish vmap = (nxge_param_map_t *)&cfg_value; 140844961713Sgirish if ((vmap->param_id) && 1409*4045d941Ssowmini (vmap->param_id < NXGE_MAX_VLANS) && 1410*4045d941Ssowmini (vmap->map_to < p_cfgp->max_rdc_grpids)) { 141144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1412*4045d941Ssowmini "nxge_param_set_vlan_rdcgrp mapping" 1413*4045d941Ssowmini " id %d grp %d", 1414*4045d941Ssowmini vmap->param_id, vmap->map_to)); 1415adfcba55Sjoycey #if defined(__i386) 1416adfcba55Sjoycey val_ptr = (uint32_t *)(uint32_t)pa->value; 1417adfcba55Sjoycey #else 141844961713Sgirish val_ptr = (uint32_t *)pa->value; 1419adfcba55Sjoycey #endif 1420adfcba55Sjoycey #if defined(__i386) 1421adfcba55Sjoycey old_val_ptr = (uint32_t *)(uint32_t)pa->old_value; 1422adfcba55Sjoycey #else 142344961713Sgirish old_val_ptr = (uint32_t *)pa->old_value; 1424adfcba55Sjoycey #endif 142544961713Sgirish 142644961713Sgirish /* search to see if this vlan id is already configured */ 142744961713Sgirish for (i = 0; i < cfgd_vlans; i++) { 142844961713Sgirish old_map = (nxge_param_map_t *)&val_ptr[i]; 142944961713Sgirish if ((old_map->param_id == 0) || 1430*4045d941Ssowmini (vmap->param_id == old_map->param_id) || 1431*4045d941Ssowmini (vlan_tbl[vmap->param_id].flag)) { 143244961713Sgirish cfg_position = i; 143344961713Sgirish break; 143444961713Sgirish } 143544961713Sgirish } 143644961713Sgirish 143744961713Sgirish if (cfgd_vlans == 0) { 143844961713Sgirish cfg_position = 0; 143944961713Sgirish inc++; 144044961713Sgirish } 144144961713Sgirish 144244961713Sgirish if (i == cfgd_vlans) { 144344961713Sgirish cfg_position = i; 144444961713Sgirish inc++; 144544961713Sgirish } 144644961713Sgirish 144744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 1448*4045d941Ssowmini "set_vlan_rdcgrp mapping" 1449*4045d941Ssowmini " i %d cfgd_vlans %llx position %d ", 1450*4045d941Ssowmini i, cfgd_vlans, cfg_position)); 145144961713Sgirish if (val_ptr[cfg_position] != cfg_value) { 145244961713Sgirish old_val_ptr[cfg_position] = val_ptr[cfg_position]; 145344961713Sgirish val_ptr[cfg_position] = cfg_value; 145444961713Sgirish vlan_tbl[vmap->param_id].mpr_npr = vmap->pref; 145544961713Sgirish vlan_tbl[vmap->param_id].flag = 1; 145644961713Sgirish vlan_tbl[vmap->param_id].rdctbl = 1457678453a8Sspeer vmap->map_to + p_cfgp->def_mac_rxdma_grpid; 145844961713Sgirish cfg_it = B_TRUE; 145944961713Sgirish if (inc) { 146044961713Sgirish cfgd_vlans++; 146144961713Sgirish pa->type &= ~NXGE_PARAM_ARRAY_CNT_MASK; 146244961713Sgirish pa->type |= (cfgd_vlans << 1463*4045d941Ssowmini NXGE_PARAM_ARRAY_CNT_SHIFT); 146444961713Sgirish 146544961713Sgirish } 146644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 1467*4045d941Ssowmini "after: param_set_vlan_rdcgrp " 1468*4045d941Ssowmini " cfg_vlans %llx position %d \n", 1469*4045d941Ssowmini cfgd_vlans, cfg_position)); 147044961713Sgirish } 147144961713Sgirish } else { 147244961713Sgirish return (EINVAL); 147344961713Sgirish } 147444961713Sgirish 147544961713Sgirish if (cfg_it == B_TRUE) { 147644961713Sgirish status = nxge_fflp_config_vlan_table(nxgep, 1477*4045d941Ssowmini (uint16_t)vmap->param_id); 147844961713Sgirish if (status != NXGE_OK) 147944961713Sgirish return (EINVAL); 148044961713Sgirish } 148144961713Sgirish 148244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_vlan_rdcgrp")); 148344961713Sgirish return (0); 148444961713Sgirish } 148544961713Sgirish 148644961713Sgirish /* ARGSUSED */ 148744961713Sgirish static int 148844961713Sgirish nxge_param_get_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q, 1489a3c5bd6dSspeer mblk_t *mp, caddr_t cp) 149044961713Sgirish { 149144961713Sgirish 1492a3c5bd6dSspeer uint_t print_len, buf_len; 1493a3c5bd6dSspeer p_mblk_t np; 1494a3c5bd6dSspeer int i; 1495a3c5bd6dSspeer uint32_t *val_ptr; 1496a3c5bd6dSspeer nxge_param_map_t *vmap; 1497a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 149844961713Sgirish p_nxge_class_pt_cfg_t p_class_cfgp; 149944961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 150044961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 1501a3c5bd6dSspeer uint64_t cfgd_vlans = 0; 1502a3c5bd6dSspeer nxge_mv_cfg_t *vlan_tbl; 1503a3c5bd6dSspeer int buff_alloc_size = 1504*4045d941Ssowmini NXGE_NDD_INFODUMP_BUFF_SIZE * 32; 150544961713Sgirish 150644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp ")); 1507a3c5bd6dSspeer (void) mi_mpprintf(mp, "VLAN RDC Mapping Information for Port\t %d \n", 1508*4045d941Ssowmini nxgep->function_num); 150944961713Sgirish 151044961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 151144961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 151244961713Sgirish return (0); 151344961713Sgirish } 1514a3c5bd6dSspeer 151544961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 151644961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 151744961713Sgirish 151844961713Sgirish buf_len = buff_alloc_size; 151944961713Sgirish mp->b_cont = np; 152044961713Sgirish cfgd_vlans = (pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >> 1521*4045d941Ssowmini NXGE_PARAM_ARRAY_CNT_SHIFT; 152244961713Sgirish 152344961713Sgirish i = (int)cfgd_vlans; 152444961713Sgirish p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 152544961713Sgirish vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 152644961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1527*4045d941Ssowmini "Configured VLANs %d\n" 1528*4045d941Ssowmini "VLAN ID\t RDC GRP (Actual/Port)\t" 1529*4045d941Ssowmini " Prefernce\n", i); 153044961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 153144961713Sgirish buf_len -= print_len; 1532adfcba55Sjoycey #if defined(__i386) 1533adfcba55Sjoycey val_ptr = (uint32_t *)(uint32_t)pa->value; 1534adfcba55Sjoycey #else 153544961713Sgirish val_ptr = (uint32_t *)pa->value; 1536adfcba55Sjoycey #endif 153744961713Sgirish 153844961713Sgirish for (i = 0; i < cfgd_vlans; i++) { 153944961713Sgirish vmap = (nxge_param_map_t *)&val_ptr[i]; 154044961713Sgirish if (p_class_cfgp->vlan_tbl[vmap->param_id].flag) { 154144961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1542*4045d941Ssowmini buf_len, 1543*4045d941Ssowmini " %d\t\t %d/%d\t\t %d\n", 1544*4045d941Ssowmini vmap->param_id, 1545*4045d941Ssowmini vlan_tbl[vmap->param_id].rdctbl, 1546*4045d941Ssowmini vlan_tbl[vmap->param_id].rdctbl - 1547*4045d941Ssowmini p_cfgp->def_mac_rxdma_grpid, 1548*4045d941Ssowmini vlan_tbl[vmap->param_id].mpr_npr); 154944961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 155044961713Sgirish buf_len -= print_len; 155144961713Sgirish } 155244961713Sgirish } 155344961713Sgirish 155444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_vlan_rdcgrp")); 155544961713Sgirish return (0); 155644961713Sgirish } 155744961713Sgirish 155844961713Sgirish /* ARGSUSED */ 155944961713Sgirish static int 156044961713Sgirish nxge_param_get_mac_rdcgrp(p_nxge_t nxgep, queue_t *q, 1561a3c5bd6dSspeer mblk_t *mp, caddr_t cp) 156244961713Sgirish { 1563a3c5bd6dSspeer uint_t print_len, buf_len; 1564a3c5bd6dSspeer p_mblk_t np; 1565a3c5bd6dSspeer int i; 156644961713Sgirish p_nxge_class_pt_cfg_t p_class_cfgp; 156744961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 156844961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 1569a3c5bd6dSspeer nxge_mv_cfg_t *mac_host_info; 157044961713Sgirish 157144961713Sgirish int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE * 32; 157244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac_rdcgrp ")); 157344961713Sgirish (void) mi_mpprintf(mp, 1574*4045d941Ssowmini "MAC ADDR RDC Mapping Information for Port\t %d\n", 1575*4045d941Ssowmini nxgep->function_num); 157644961713Sgirish 157744961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 157844961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 157944961713Sgirish return (0); 158044961713Sgirish } 158144961713Sgirish 158244961713Sgirish buf_len = buff_alloc_size; 158344961713Sgirish mp->b_cont = np; 158444961713Sgirish p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 158544961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 158644961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 158744961713Sgirish mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 158844961713Sgirish print_len = snprintf((char *)np->b_wptr, buf_len, 1589*4045d941Ssowmini "MAC ID\t RDC GRP (Actual/Port)\t" 1590*4045d941Ssowmini " Prefernce\n"); 159144961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 159244961713Sgirish buf_len -= print_len; 159344961713Sgirish for (i = 0; i < p_cfgp->max_macs; i++) { 159444961713Sgirish if (mac_host_info[i].flag) { 159544961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1596*4045d941Ssowmini buf_len, 1597*4045d941Ssowmini " %d\t %d/%d\t\t %d\n", 1598*4045d941Ssowmini i, mac_host_info[i].rdctbl, 1599*4045d941Ssowmini mac_host_info[i].rdctbl - 1600*4045d941Ssowmini p_cfgp->def_mac_rxdma_grpid, 1601*4045d941Ssowmini mac_host_info[i].mpr_npr); 160244961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 160344961713Sgirish buf_len -= print_len; 160444961713Sgirish } 160544961713Sgirish } 160644961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1607*4045d941Ssowmini "Done Info Dumping \n"); 160844961713Sgirish ((mblk_t *)np)->b_wptr += print_len; 160944961713Sgirish buf_len -= print_len; 161044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_macrdcgrp")); 161144961713Sgirish return (0); 161244961713Sgirish } 161344961713Sgirish 161444961713Sgirish /* ARGSUSED */ 161544961713Sgirish static int 161644961713Sgirish nxge_param_tcam_enable(p_nxge_t nxgep, queue_t *q, 1617a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 161844961713Sgirish { 1619a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1620a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1621a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 1622a3c5bd6dSspeer char *end; 162344961713Sgirish 162444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_tcam_enable")); 162544961713Sgirish 162644961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 162744961713Sgirish if (pa->value != cfg_value) { 162844961713Sgirish pa->old_value = pa->value; 162944961713Sgirish pa->value = cfg_value; 163044961713Sgirish cfg_it = B_TRUE; 163144961713Sgirish } 163244961713Sgirish 163344961713Sgirish if (cfg_it == B_TRUE) { 163444961713Sgirish if (pa->value) 163544961713Sgirish status = nxge_fflp_config_tcam_enable(nxgep); 163644961713Sgirish else 163744961713Sgirish status = nxge_fflp_config_tcam_disable(nxgep); 163844961713Sgirish if (status != NXGE_OK) 163944961713Sgirish return (EINVAL); 164044961713Sgirish } 164144961713Sgirish 164244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_tcam_enable")); 164344961713Sgirish return (0); 164444961713Sgirish } 164544961713Sgirish 164644961713Sgirish /* ARGSUSED */ 164744961713Sgirish static int 164844961713Sgirish nxge_param_hash_lookup_enable(p_nxge_t nxgep, queue_t *q, 1649a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 165044961713Sgirish { 1651a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1652a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1653a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 1654a3c5bd6dSspeer char *end; 165544961713Sgirish 165644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_hash_lookup_enable")); 165744961713Sgirish 165844961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 165944961713Sgirish if (pa->value != cfg_value) { 166044961713Sgirish pa->old_value = pa->value; 166144961713Sgirish pa->value = cfg_value; 166244961713Sgirish cfg_it = B_TRUE; 166344961713Sgirish } 166444961713Sgirish 166544961713Sgirish if (cfg_it == B_TRUE) { 166644961713Sgirish if (pa->value) 166744961713Sgirish status = nxge_fflp_config_hash_lookup_enable(nxgep); 166844961713Sgirish else 166944961713Sgirish status = nxge_fflp_config_hash_lookup_disable(nxgep); 167044961713Sgirish if (status != NXGE_OK) 167144961713Sgirish return (EINVAL); 167244961713Sgirish } 167344961713Sgirish 167444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_hash_lookup_enable")); 167544961713Sgirish return (0); 167644961713Sgirish } 167744961713Sgirish 167844961713Sgirish /* ARGSUSED */ 167944961713Sgirish static int 168044961713Sgirish nxge_param_llc_snap_enable(p_nxge_t nxgep, queue_t *q, 1681a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 168244961713Sgirish { 1683a3c5bd6dSspeer char *end; 1684a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1685a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1686a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 168744961713Sgirish 168844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_llc_snap_enable")); 168944961713Sgirish 169044961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 169144961713Sgirish if (pa->value != cfg_value) { 169244961713Sgirish pa->old_value = pa->value; 169344961713Sgirish pa->value = cfg_value; 169444961713Sgirish cfg_it = B_TRUE; 169544961713Sgirish } 169644961713Sgirish 169744961713Sgirish if (cfg_it == B_TRUE) { 169844961713Sgirish if (pa->value) 169944961713Sgirish status = nxge_fflp_config_tcam_enable(nxgep); 170044961713Sgirish else 170144961713Sgirish status = nxge_fflp_config_tcam_disable(nxgep); 170244961713Sgirish if (status != NXGE_OK) 170344961713Sgirish return (EINVAL); 170444961713Sgirish } 170544961713Sgirish 170644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_llc_snap_enable")); 170744961713Sgirish return (0); 170844961713Sgirish } 170944961713Sgirish 171044961713Sgirish /* ARGSUSED */ 171144961713Sgirish static int 171244961713Sgirish nxge_param_set_ether_usr(p_nxge_t nxgep, queue_t *q, 1713a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 171444961713Sgirish { 1715a3c5bd6dSspeer char *end; 1716a3c5bd6dSspeer uint8_t ether_class; 1717a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1718a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1719a3c5bd6dSspeer uint8_t cfg_it = B_FALSE; 172044961713Sgirish 172144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ether_usr")); 172244961713Sgirish 172344961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 172444961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 172544961713Sgirish return (EINVAL); 172644961713Sgirish } 1727a3c5bd6dSspeer 172844961713Sgirish if (pa->value != cfg_value) { 172944961713Sgirish pa->old_value = pa->value; 173044961713Sgirish pa->value = cfg_value; 173144961713Sgirish cfg_it = B_TRUE; 173244961713Sgirish } 173344961713Sgirish 173444961713Sgirish /* do the actual hw setup */ 173544961713Sgirish if (cfg_it == B_TRUE) { 173644961713Sgirish ether_class = mi_strtol(pa->name, &end, 10); 173744961713Sgirish #ifdef lint 173844961713Sgirish ether_class = ether_class; 173944961713Sgirish #endif 174044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_ether_usr")); 174144961713Sgirish } 1742a3c5bd6dSspeer 174344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ether_usr")); 174444961713Sgirish return (status); 174544961713Sgirish } 174644961713Sgirish 174744961713Sgirish /* ARGSUSED */ 174844961713Sgirish static int 174944961713Sgirish nxge_param_set_ip_usr(p_nxge_t nxgep, queue_t *q, 1750a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 175144961713Sgirish { 1752a3c5bd6dSspeer char *end; 1753a3c5bd6dSspeer tcam_class_t class; 1754a3c5bd6dSspeer uint32_t status, cfg_value; 1755a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1756a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 175744961713Sgirish 175844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_usr")); 175944961713Sgirish 176044961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 176144961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 176244961713Sgirish return (EINVAL); 176344961713Sgirish } 176444961713Sgirish 176544961713Sgirish if (pa->value != cfg_value) { 176644961713Sgirish pa->old_value = pa->value; 176744961713Sgirish pa->value = cfg_value; 176844961713Sgirish cfg_it = B_TRUE; 176944961713Sgirish } 177044961713Sgirish 177144961713Sgirish /* do the actual hw setup with cfg_value. */ 177244961713Sgirish if (cfg_it == B_TRUE) { 177344961713Sgirish class = mi_strtol(pa->name, &end, 10); 177444961713Sgirish status = nxge_fflp_ip_usr_class_config(nxgep, class, pa->value); 177544961713Sgirish } 177644961713Sgirish 177744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_usr")); 177844961713Sgirish return (status); 177944961713Sgirish } 178044961713Sgirish 1781a3c5bd6dSspeer /* ARGSUSED */ 178244961713Sgirish static int 178344961713Sgirish nxge_class_name_2value(p_nxge_t nxgep, char *name) 178444961713Sgirish { 1785a3c5bd6dSspeer int i; 1786a3c5bd6dSspeer int class_instance = param_class_opt_ip_usr4; 1787a3c5bd6dSspeer p_nxge_param_t param_arr; 1788a3c5bd6dSspeer 178944961713Sgirish param_arr = nxgep->param_arr; 179044961713Sgirish for (i = TCAM_CLASS_IP_USER_4; i <= TCAM_CLASS_SCTP_IPV6; i++) { 179144961713Sgirish if (strcmp(param_arr[class_instance].name, name) == 0) 179244961713Sgirish return (i); 179344961713Sgirish class_instance++; 179444961713Sgirish } 179544961713Sgirish return (-1); 179644961713Sgirish } 179744961713Sgirish 179844961713Sgirish /* ARGSUSED */ 17991bd6825cSml int 180044961713Sgirish nxge_param_set_ip_opt(p_nxge_t nxgep, queue_t *q, 1801a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 180244961713Sgirish { 1803a3c5bd6dSspeer char *end; 1804a3c5bd6dSspeer uint32_t status, cfg_value; 1805a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1806a3c5bd6dSspeer tcam_class_t class; 1807a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 180844961713Sgirish 180944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_opt")); 181044961713Sgirish 181144961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 181244961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 181344961713Sgirish return (EINVAL); 181444961713Sgirish } 181544961713Sgirish 181644961713Sgirish if (pa->value != cfg_value) { 181744961713Sgirish pa->old_value = pa->value; 181844961713Sgirish pa->value = cfg_value; 181944961713Sgirish cfg_it = B_TRUE; 182044961713Sgirish } 182144961713Sgirish 182244961713Sgirish if (cfg_it == B_TRUE) { 1823a3c5bd6dSspeer /* do the actual hw setup */ 182444961713Sgirish class = nxge_class_name_2value(nxgep, pa->name); 182544961713Sgirish if (class == -1) 182644961713Sgirish return (EINVAL); 182744961713Sgirish 182844961713Sgirish status = nxge_fflp_ip_class_config(nxgep, class, pa->value); 182944961713Sgirish if (status != NXGE_OK) 183044961713Sgirish return (EINVAL); 183144961713Sgirish } 183244961713Sgirish 183344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_opt")); 183444961713Sgirish return (0); 183544961713Sgirish } 183644961713Sgirish 183744961713Sgirish /* ARGSUSED */ 183844961713Sgirish static int 183944961713Sgirish nxge_param_get_ip_opt(p_nxge_t nxgep, queue_t *q, 1840a3c5bd6dSspeer mblk_t *mp, caddr_t cp) 184144961713Sgirish { 184244961713Sgirish uint32_t status, cfg_value; 184344961713Sgirish p_nxge_param_t pa = (p_nxge_param_t)cp; 184444961713Sgirish tcam_class_t class; 184544961713Sgirish 184644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_ip_opt")); 184744961713Sgirish 1848a3c5bd6dSspeer /* do the actual hw setup */ 184944961713Sgirish class = nxge_class_name_2value(nxgep, pa->name); 185044961713Sgirish if (class == -1) 185144961713Sgirish return (EINVAL); 1852a3c5bd6dSspeer 185344961713Sgirish cfg_value = 0; 185444961713Sgirish status = nxge_fflp_ip_class_config_get(nxgep, class, &cfg_value); 185544961713Sgirish if (status != NXGE_OK) 185644961713Sgirish return (EINVAL); 1857a3c5bd6dSspeer 185844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1859*4045d941Ssowmini "nxge_param_get_ip_opt_get %x ", cfg_value)); 186044961713Sgirish 1861a3c5bd6dSspeer pa->value = cfg_value; 186244961713Sgirish (void) mi_mpprintf(mp, "%x", cfg_value); 1863a3c5bd6dSspeer 186444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_ip_opt status ")); 186544961713Sgirish return (0); 186644961713Sgirish } 186744961713Sgirish 186844961713Sgirish /* ARGSUSED */ 186944961713Sgirish static int 187044961713Sgirish nxge_param_fflp_hash_init(p_nxge_t nxgep, queue_t *q, 1871a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 187244961713Sgirish { 1873a3c5bd6dSspeer char *end; 1874a3c5bd6dSspeer uint32_t status, cfg_value; 1875a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1876a3c5bd6dSspeer tcam_class_t class; 1877a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 187844961713Sgirish 187944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_fflp_hash_init")); 188044961713Sgirish 188144961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 188244961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 188344961713Sgirish return (EINVAL); 188444961713Sgirish } 188544961713Sgirish 188644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1887*4045d941Ssowmini "nxge_param_fflp_hash_init value %x", cfg_value)); 1888a3c5bd6dSspeer 188944961713Sgirish if (pa->value != cfg_value) { 189044961713Sgirish pa->old_value = pa->value; 189144961713Sgirish pa->value = cfg_value; 189244961713Sgirish cfg_it = B_TRUE; 189344961713Sgirish } 189444961713Sgirish 189544961713Sgirish if (cfg_it == B_TRUE) { 189644961713Sgirish char *h_name; 1897a3c5bd6dSspeer 189844961713Sgirish /* do the actual hw setup */ 189944961713Sgirish h_name = pa->name; 190044961713Sgirish h_name++; 190144961713Sgirish class = mi_strtol(h_name, &end, 10); 190244961713Sgirish switch (class) { 190344961713Sgirish case 1: 190444961713Sgirish status = nxge_fflp_set_hash1(nxgep, 1905*4045d941Ssowmini (uint32_t)pa->value); 190644961713Sgirish break; 190744961713Sgirish case 2: 190844961713Sgirish status = nxge_fflp_set_hash2(nxgep, 1909*4045d941Ssowmini (uint16_t)pa->value); 191044961713Sgirish break; 191144961713Sgirish 191244961713Sgirish default: 191344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1914*4045d941Ssowmini " nxge_param_fflp_hash_init" 1915*4045d941Ssowmini " %s Wrong hash var %d", 1916*4045d941Ssowmini pa->name, class)); 191744961713Sgirish return (EINVAL); 191844961713Sgirish } 191944961713Sgirish if (status != NXGE_OK) 192044961713Sgirish return (EINVAL); 192144961713Sgirish } 192244961713Sgirish 192344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_fflp_hash_init")); 192444961713Sgirish return (0); 192544961713Sgirish } 192644961713Sgirish 192744961713Sgirish /* ARGSUSED */ 192844961713Sgirish static int 192944961713Sgirish nxge_param_set_grp_rdc(p_nxge_t nxgep, queue_t *q, 1930a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 193144961713Sgirish { 1932a3c5bd6dSspeer char *end; 1933a3c5bd6dSspeer uint32_t status = 0, cfg_value; 1934a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1935a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 1936a3c5bd6dSspeer int rdc_grp; 1937a3c5bd6dSspeer uint8_t real_rdc; 193844961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 193944961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 194044961713Sgirish p_nxge_rdc_grp_t rdc_grp_p; 194144961713Sgirish 194244961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 194344961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 194444961713Sgirish 194544961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_grp_rdc")); 194644961713Sgirish 194744961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 194844961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 194944961713Sgirish return (EINVAL); 195044961713Sgirish } 1951a3c5bd6dSspeer 195244961713Sgirish if (cfg_value >= p_cfgp->max_rdcs) { 195344961713Sgirish return (EINVAL); 195444961713Sgirish } 1955a3c5bd6dSspeer 195644961713Sgirish if (pa->value != cfg_value) { 195744961713Sgirish pa->old_value = pa->value; 195844961713Sgirish pa->value = cfg_value; 195944961713Sgirish cfg_it = B_TRUE; 196044961713Sgirish } 196144961713Sgirish 196244961713Sgirish if (cfg_it == B_TRUE) { 196344961713Sgirish char *grp_name; 196444961713Sgirish grp_name = pa->name; 196544961713Sgirish grp_name += strlen("default-grp"); 196644961713Sgirish rdc_grp = mi_strtol(grp_name, &end, 10); 196744961713Sgirish rdc_grp_p = &p_dma_cfgp->rdc_grps[rdc_grp]; 196844961713Sgirish real_rdc = rdc_grp_p->start_rdc + cfg_value; 196944961713Sgirish if (nxge_check_rxdma_rdcgrp_member(nxgep, rdc_grp, 1970*4045d941Ssowmini cfg_value) == B_FALSE) { 197144961713Sgirish pa->value = pa->old_value; 197244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1973*4045d941Ssowmini " nxge_param_set_grp_rdc" 1974*4045d941Ssowmini " %d read %d actual %d outof range", 1975*4045d941Ssowmini rdc_grp, cfg_value, real_rdc)); 197644961713Sgirish return (EINVAL); 197744961713Sgirish } 197844961713Sgirish status = nxge_rxdma_cfg_rdcgrp_default_rdc(nxgep, rdc_grp, 1979*4045d941Ssowmini real_rdc); 198044961713Sgirish if (status != NXGE_OK) 198144961713Sgirish return (EINVAL); 198244961713Sgirish } 198344961713Sgirish 198444961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_grp_rdc")); 198544961713Sgirish return (0); 198644961713Sgirish } 198744961713Sgirish 198844961713Sgirish /* ARGSUSED */ 198944961713Sgirish static int 199044961713Sgirish nxge_param_set_port_rdc(p_nxge_t nxgep, queue_t *q, 1991a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 199244961713Sgirish { 1993a3c5bd6dSspeer char *end; 1994a3c5bd6dSspeer uint32_t status = B_TRUE, cfg_value; 1995a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 1996a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 199744961713Sgirish 199844961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 199944961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 200044961713Sgirish 200144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_port_rdc")); 200244961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 200344961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 200444961713Sgirish 200544961713Sgirish cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 200644961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 200744961713Sgirish return (EINVAL); 200844961713Sgirish } 2009a3c5bd6dSspeer 201044961713Sgirish if (pa->value != cfg_value) { 201144961713Sgirish if (cfg_value >= p_cfgp->max_rdcs) 201244961713Sgirish return (EINVAL); 201344961713Sgirish pa->old_value = pa->value; 201444961713Sgirish pa->value = cfg_value; 201544961713Sgirish cfg_it = B_TRUE; 201644961713Sgirish } 201744961713Sgirish 201844961713Sgirish if (cfg_it == B_TRUE) { 2019678453a8Sspeer int rdc; 2020678453a8Sspeer if ((rdc = nxge_dci_map(nxgep, VP_BOUND_RX, cfg_value)) < 0) 2021678453a8Sspeer return (EINVAL); 202244961713Sgirish status = nxge_rxdma_cfg_port_default_rdc(nxgep, 2023678453a8Sspeer nxgep->function_num, rdc); 202444961713Sgirish if (status != NXGE_OK) 202544961713Sgirish return (EINVAL); 202644961713Sgirish } 202744961713Sgirish 202844961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_port_rdc")); 202944961713Sgirish return (0); 203044961713Sgirish } 203144961713Sgirish 203244961713Sgirish /* ARGSUSED */ 203344961713Sgirish static int 203444961713Sgirish nxge_param_set_nxge_debug_flag(p_nxge_t nxgep, queue_t *q, 2035a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 203644961713Sgirish { 203744961713Sgirish char *end; 203844961713Sgirish uint32_t status = 0; 203944961713Sgirish uint64_t cfg_value = 0; 204044961713Sgirish p_nxge_param_t pa = (p_nxge_param_t)cp; 204144961713Sgirish uint32_t cfg_it = B_FALSE; 204244961713Sgirish 204344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_nxge_debug_flag")); 204444961713Sgirish cfg_value = mi_strtol(value, &end, BASE_HEX); 204544961713Sgirish 204644961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 204744961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, 2048*4045d941Ssowmini " nxge_param_set_nxge_debug_flag" 2049*4045d941Ssowmini " outof range %llx", cfg_value)); 205044961713Sgirish return (EINVAL); 205144961713Sgirish } 205244961713Sgirish if (pa->value != cfg_value) { 205344961713Sgirish pa->old_value = pa->value; 205444961713Sgirish pa->value = cfg_value; 205544961713Sgirish cfg_it = B_TRUE; 205644961713Sgirish } 205744961713Sgirish 205844961713Sgirish if (cfg_it == B_TRUE) { 205944961713Sgirish nxgep->nxge_debug_level = pa->value; 206044961713Sgirish } 2061a3c5bd6dSspeer 206244961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_nxge_debug_flag")); 206344961713Sgirish return (status); 206444961713Sgirish } 206544961713Sgirish 206644961713Sgirish /* ARGSUSED */ 206744961713Sgirish static int 206844961713Sgirish nxge_param_get_debug_flag(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 206944961713Sgirish { 2070a3c5bd6dSspeer int status = 0; 2071a3c5bd6dSspeer p_nxge_param_t pa = (p_nxge_param_t)cp; 207244961713Sgirish 207344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_debug_flag")); 207444961713Sgirish 207544961713Sgirish if (pa->value > 0xffffffff) 207644961713Sgirish (void) mi_mpprintf(mp, "%x%x", (int)(pa->value >> 32), 2077*4045d941Ssowmini (int)(pa->value & 0xffffffff)); 207844961713Sgirish else 207944961713Sgirish (void) mi_mpprintf(mp, "%x", (int)pa->value); 208044961713Sgirish 208144961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_debug_flag")); 208244961713Sgirish return (status); 208344961713Sgirish } 208444961713Sgirish 208544961713Sgirish /* ARGSUSED */ 208644961713Sgirish static int 208744961713Sgirish nxge_param_set_npi_debug_flag(p_nxge_t nxgep, queue_t *q, 2088a3c5bd6dSspeer mblk_t *mp, char *value, caddr_t cp) 208944961713Sgirish { 2090a3c5bd6dSspeer char *end; 2091a3c5bd6dSspeer uint32_t status = 0; 2092a3c5bd6dSspeer uint64_t cfg_value = 0; 2093a3c5bd6dSspeer p_nxge_param_t pa; 2094a3c5bd6dSspeer uint32_t cfg_it = B_FALSE; 209544961713Sgirish 209644961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_npi_debug_flag")); 209744961713Sgirish cfg_value = mi_strtol(value, &end, BASE_HEX); 209844961713Sgirish pa = (p_nxge_param_t)cp; 209944961713Sgirish if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 210044961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_npi_debug_flag" 2101*4045d941Ssowmini " outof range %llx", cfg_value)); 210244961713Sgirish return (EINVAL); 210344961713Sgirish } 210444961713Sgirish if (pa->value != cfg_value) { 210544961713Sgirish pa->old_value = pa->value; 210644961713Sgirish pa->value = cfg_value; 210744961713Sgirish cfg_it = B_TRUE; 210844961713Sgirish } 210944961713Sgirish 211044961713Sgirish if (cfg_it == B_TRUE) { 211144961713Sgirish npi_debug_level = pa->value; 211244961713Sgirish } 211344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_debug_flag")); 211444961713Sgirish return (status); 211544961713Sgirish } 211644961713Sgirish 211744961713Sgirish /* ARGSUSED */ 211844961713Sgirish static int 211944961713Sgirish nxge_param_dump_rdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 212044961713Sgirish { 2121678453a8Sspeer nxge_grp_set_t *set = &nxgep->rx_set; 2122678453a8Sspeer int rdc; 212344961713Sgirish 212444961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_rdc")); 212544961713Sgirish 2126678453a8Sspeer if (!isLDOMguest(nxgep)) 2127*4045d941Ssowmini (void) npi_rxdma_dump_fzc_regs(NXGE_DEV_NPI_HANDLE(nxgep)); 2128678453a8Sspeer 2129678453a8Sspeer for (rdc = 0; rdc < NXGE_MAX_TDCS; rdc++) { 2130678453a8Sspeer if ((1 << rdc) & set->owned.map) { 2131678453a8Sspeer (void) nxge_dump_rxdma_channel(nxgep, rdc); 2132678453a8Sspeer } 2133678453a8Sspeer } 213444961713Sgirish 213544961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_rdc")); 213644961713Sgirish return (0); 213744961713Sgirish } 213844961713Sgirish 213944961713Sgirish /* ARGSUSED */ 214044961713Sgirish static int 214144961713Sgirish nxge_param_dump_tdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 214244961713Sgirish { 2143678453a8Sspeer nxge_grp_set_t *set = &nxgep->tx_set; 2144678453a8Sspeer int tdc; 214544961713Sgirish 214644961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_tdc")); 214744961713Sgirish 2148678453a8Sspeer for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) { 2149678453a8Sspeer if ((1 << tdc) & set->owned.map) { 2150678453a8Sspeer (void) nxge_txdma_regs_dump(nxgep, tdc); 2151678453a8Sspeer } 2152678453a8Sspeer } 215344961713Sgirish 215444961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_tdc")); 215544961713Sgirish return (0); 215644961713Sgirish } 215744961713Sgirish 215844961713Sgirish /* ARGSUSED */ 215944961713Sgirish static int 216044961713Sgirish nxge_param_dump_fflp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 216144961713Sgirish { 216244961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_fflp_regs")); 216344961713Sgirish 216444961713Sgirish (void) npi_fflp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep)); 216544961713Sgirish 216644961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_fflp_regs")); 216744961713Sgirish return (0); 216844961713Sgirish } 216944961713Sgirish 217044961713Sgirish /* ARGSUSED */ 217144961713Sgirish static int 217244961713Sgirish nxge_param_dump_mac_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 217344961713Sgirish { 217444961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_mac_regs")); 217544961713Sgirish 217644961713Sgirish (void) npi_mac_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep), 2177*4045d941Ssowmini nxgep->function_num); 217844961713Sgirish 217944961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_mac_regs")); 218044961713Sgirish return (0); 218144961713Sgirish } 218244961713Sgirish 218344961713Sgirish /* ARGSUSED */ 218444961713Sgirish static int 218544961713Sgirish nxge_param_dump_ipp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 218644961713Sgirish { 218744961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_ipp_regs")); 218844961713Sgirish 2189a3c5bd6dSspeer (void) npi_ipp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep), 2190*4045d941Ssowmini nxgep->function_num); 219144961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ipp_regs")); 219244961713Sgirish return (0); 219344961713Sgirish } 219444961713Sgirish 219544961713Sgirish /* ARGSUSED */ 219644961713Sgirish static int 219744961713Sgirish nxge_param_dump_vlan_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 219844961713Sgirish { 219944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_vlan_table")); 220044961713Sgirish 220144961713Sgirish (void) npi_fflp_vlan_tbl_dump(NXGE_DEV_NPI_HANDLE(nxgep)); 220244961713Sgirish 220344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_vlan_table")); 220444961713Sgirish return (0); 220544961713Sgirish } 220644961713Sgirish 220744961713Sgirish /* ARGSUSED */ 220844961713Sgirish static int 220944961713Sgirish nxge_param_dump_rdc_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 221044961713Sgirish { 2211a3c5bd6dSspeer uint8_t table; 221244961713Sgirish 221344961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_rdc_table")); 221444961713Sgirish for (table = 0; table < NXGE_MAX_RDC_GROUPS; table++) { 221544961713Sgirish (void) npi_rxdma_dump_rdc_table(NXGE_DEV_NPI_HANDLE(nxgep), 2216*4045d941Ssowmini table); 221744961713Sgirish } 2218a3c5bd6dSspeer 221944961713Sgirish NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_rdc_table")); 222044961713Sgirish return (0); 222144961713Sgirish } 222244961713Sgirish 222344961713Sgirish typedef struct block_info { 222444961713Sgirish char *name; 222544961713Sgirish uint32_t offset; 222644961713Sgirish } block_info_t; 222744961713Sgirish 222844961713Sgirish block_info_t reg_block[] = { 222944961713Sgirish {"PIO", PIO}, 223044961713Sgirish {"FZC_PIO", FZC_PIO}, 223144961713Sgirish {"FZC_XMAC", FZC_MAC}, 223244961713Sgirish {"FZC_IPP", FZC_IPP}, 223344961713Sgirish {"FFLP", FFLP}, 223444961713Sgirish {"FZC_FFLP", FZC_FFLP}, 223544961713Sgirish {"PIO_VADDR", PIO_VADDR}, 223644961713Sgirish {"ZCP", ZCP}, 223744961713Sgirish {"FZC_ZCP", FZC_ZCP}, 223844961713Sgirish {"DMC", DMC}, 223944961713Sgirish {"FZC_DMC", FZC_DMC}, 224044961713Sgirish {"TXC", TXC}, 224144961713Sgirish {"FZC_TXC", FZC_TXC}, 224244961713Sgirish {"PIO_LDSV", PIO_LDSV}, 224344961713Sgirish {"PIO_LDGIM", PIO_LDGIM}, 224444961713Sgirish {"PIO_IMASK0", PIO_IMASK0}, 224544961713Sgirish {"PIO_IMASK1", PIO_IMASK1}, 224644961713Sgirish {"FZC_PROM", FZC_PROM}, 224744961713Sgirish {"END", ALL_FF_32}, 224844961713Sgirish }; 224944961713Sgirish 225044961713Sgirish /* ARGSUSED */ 225144961713Sgirish static int 225244961713Sgirish nxge_param_dump_ptrs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 225344961713Sgirish { 2254a3c5bd6dSspeer uint_t print_len, buf_len; 2255a3c5bd6dSspeer p_mblk_t np; 2256a3c5bd6dSspeer int rdc, tdc, block; 2257a3c5bd6dSspeer uint64_t base; 225844961713Sgirish p_nxge_dma_pt_cfg_t p_dma_cfgp; 225944961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 2260a3c5bd6dSspeer int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_8K; 226144961713Sgirish p_tx_ring_t *tx_rings; 226244961713Sgirish p_rx_rcr_rings_t rx_rcr_rings; 226344961713Sgirish p_rx_rcr_ring_t *rcr_rings; 226444961713Sgirish p_rx_rbr_rings_t rx_rbr_rings; 226544961713Sgirish p_rx_rbr_ring_t *rbr_rings; 226644961713Sgirish 2267a3c5bd6dSspeer NXGE_DEBUG_MSG((nxgep, IOC_CTL, 2268*4045d941Ssowmini "==> nxge_param_dump_ptrs")); 226944961713Sgirish 2270a3c5bd6dSspeer (void) mi_mpprintf(mp, "ptr information for Port\t %d \n", 2271*4045d941Ssowmini nxgep->function_num); 227244961713Sgirish 227344961713Sgirish if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 227444961713Sgirish /* The following may work even if we cannot get a large buf. */ 227544961713Sgirish (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 227644961713Sgirish return (0); 227744961713Sgirish } 227844961713Sgirish 227944961713Sgirish buf_len = buff_alloc_size; 228044961713Sgirish mp->b_cont = np; 228144961713Sgirish p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 228244961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 228344961713Sgirish 228444961713Sgirish rx_rcr_rings = nxgep->rx_rcr_rings; 228544961713Sgirish rcr_rings = rx_rcr_rings->rcr_rings; 228644961713Sgirish rx_rbr_rings = nxgep->rx_rbr_rings; 228744961713Sgirish rbr_rings = rx_rbr_rings->rbr_rings; 228844961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2289*4045d941Ssowmini "nxgep (nxge_t) $%p\n" 2290*4045d941Ssowmini "dev_regs (dev_regs_t) $%p\n", 2291*4045d941Ssowmini nxgep, nxgep->dev_regs); 229244961713Sgirish 229344961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2294a3c5bd6dSspeer 2295a3c5bd6dSspeer /* do register pointers */ 229644961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2297*4045d941Ssowmini "reg base (npi_reg_ptr_t) $%p\t " 2298*4045d941Ssowmini "pci reg (npi_reg_ptr_t) $%p\n", 2299*4045d941Ssowmini nxgep->dev_regs->nxge_regp, 2300*4045d941Ssowmini nxgep->dev_regs->nxge_pciregp); 230144961713Sgirish 230244961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 230344961713Sgirish 230444961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2305*4045d941Ssowmini "\nBlock \t Offset \n"); 230644961713Sgirish 230744961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 230844961713Sgirish block = 0; 2309adfcba55Sjoycey #if defined(__i386) 2310adfcba55Sjoycey base = (uint64_t)(uint32_t)nxgep->dev_regs->nxge_regp; 2311adfcba55Sjoycey #else 231244961713Sgirish base = (uint64_t)nxgep->dev_regs->nxge_regp; 2313adfcba55Sjoycey #endif 231444961713Sgirish while (reg_block[block].offset != ALL_FF_32) { 231544961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2316*4045d941Ssowmini "%9s\t 0x%llx\n", 2317*4045d941Ssowmini reg_block[block].name, 2318*4045d941Ssowmini (unsigned long long)(reg_block[block].offset + base)); 231944961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 232044961713Sgirish block++; 232144961713Sgirish } 232244961713Sgirish 232344961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2324*4045d941Ssowmini "\nRDC\t rcrp (rx_rcr_ring_t)\t " 2325*4045d941Ssowmini "rbrp (rx_rbr_ring_t)\n"); 232644961713Sgirish 232744961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 232844961713Sgirish 232944961713Sgirish for (rdc = 0; rdc < p_cfgp->max_rdcs; rdc++) { 233044961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2331*4045d941Ssowmini " %d\t $%p\t\t $%p\n", 2332*4045d941Ssowmini rdc, rcr_rings[rdc], 2333*4045d941Ssowmini rbr_rings[rdc]); 233444961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 233544961713Sgirish } 233644961713Sgirish 233744961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2338*4045d941Ssowmini "\nTDC\t tdcp (tx_ring_t)\n"); 233944961713Sgirish 234044961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 234144961713Sgirish tx_rings = nxgep->tx_rings->rings; 2342678453a8Sspeer for (tdc = 0; tdc < p_cfgp->tdc.count; tdc++) { 234344961713Sgirish print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2344*4045d941Ssowmini " %d\t $%p\n", tdc, tx_rings[tdc]); 234544961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 234644961713Sgirish } 234744961713Sgirish 2348a3c5bd6dSspeer print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, "\n\n"); 234944961713Sgirish 235044961713Sgirish ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 235144961713Sgirish NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ptrs")); 235244961713Sgirish return (0); 235344961713Sgirish } 235444961713Sgirish 235544961713Sgirish 235644961713Sgirish /* ARGSUSED */ 235744961713Sgirish int 235844961713Sgirish nxge_nd_get_names(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t param) 235944961713Sgirish { 2360a3c5bd6dSspeer ND *nd; 2361a3c5bd6dSspeer NDE *nde; 2362a3c5bd6dSspeer char *rwtag; 2363a3c5bd6dSspeer boolean_t get_ok, set_ok; 2364a3c5bd6dSspeer size_t param_len; 2365a3c5bd6dSspeer int status = 0; 236644961713Sgirish 236744961713Sgirish nd = (ND *)param; 236844961713Sgirish if (!nd) 236944961713Sgirish return (ENOENT); 237044961713Sgirish 237144961713Sgirish for (nde = nd->nd_tbl; nde->nde_name; nde++) { 237244961713Sgirish get_ok = (nde->nde_get_pfi != nxge_get_default) && 2373*4045d941Ssowmini (nde->nde_get_pfi != NULL); 237444961713Sgirish set_ok = (nde->nde_set_pfi != nxge_set_default) && 2375*4045d941Ssowmini (nde->nde_set_pfi != NULL); 237644961713Sgirish if (get_ok) { 237744961713Sgirish if (set_ok) 237844961713Sgirish rwtag = "read and write"; 237944961713Sgirish else 238044961713Sgirish rwtag = "read only"; 238144961713Sgirish } else if (set_ok) 238244961713Sgirish rwtag = "write only"; 238344961713Sgirish else { 238444961713Sgirish continue; 238544961713Sgirish } 238644961713Sgirish param_len = strlen(rwtag); 238744961713Sgirish param_len += strlen(nde->nde_name); 238844961713Sgirish param_len += 4; 238944961713Sgirish 239044961713Sgirish (void) mi_mpprintf(mp, "%s (%s)", nde->nde_name, rwtag); 239144961713Sgirish } 239244961713Sgirish return (status); 239344961713Sgirish } 239444961713Sgirish 239544961713Sgirish /* ARGSUSED */ 239644961713Sgirish int 239744961713Sgirish nxge_get_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t data) 239844961713Sgirish { 239944961713Sgirish return (EACCES); 240044961713Sgirish } 240144961713Sgirish 240244961713Sgirish /* ARGSUSED */ 240344961713Sgirish int 240444961713Sgirish nxge_set_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, char *value, 2405a3c5bd6dSspeer caddr_t data) 240644961713Sgirish { 240744961713Sgirish return (EACCES); 240844961713Sgirish } 240944961713Sgirish 24101bd6825cSml boolean_t 241144961713Sgirish nxge_param_link_update(p_nxge_t nxgep) 241244961713Sgirish { 241344961713Sgirish p_nxge_param_t param_arr; 241444961713Sgirish nxge_param_index_t i; 241544961713Sgirish boolean_t update_xcvr; 241644961713Sgirish boolean_t update_dev; 241744961713Sgirish int instance; 241844961713Sgirish boolean_t status = B_TRUE; 241944961713Sgirish 24201bd6825cSml NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_link_update")); 242144961713Sgirish 242244961713Sgirish param_arr = nxgep->param_arr; 242344961713Sgirish instance = nxgep->instance; 242444961713Sgirish update_xcvr = B_FALSE; 242544961713Sgirish for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) { 242644961713Sgirish update_xcvr |= param_arr[i].value; 242744961713Sgirish } 242844961713Sgirish 242944961713Sgirish if (update_xcvr) { 243044961713Sgirish update_xcvr = B_FALSE; 243144961713Sgirish for (i = param_autoneg; i < param_enable_ipg0; i++) { 243244961713Sgirish update_xcvr |= 2433*4045d941Ssowmini (param_arr[i].value != param_arr[i].old_value); 243444961713Sgirish param_arr[i].old_value = param_arr[i].value; 243544961713Sgirish } 243644961713Sgirish if (update_xcvr) { 24371bd6825cSml NXGE_DEBUG_MSG((nxgep, NDD_CTL, 24381bd6825cSml "==> nxge_param_link_update: update xcvr")); 243944961713Sgirish RW_ENTER_WRITER(&nxgep->filter_lock); 244044961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 244144961713Sgirish (void) nxge_link_init(nxgep); 244244961713Sgirish (void) nxge_mac_init(nxgep); 244344961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 244444961713Sgirish RW_EXIT(&nxgep->filter_lock); 244544961713Sgirish } 244644961713Sgirish } else { 244744961713Sgirish cmn_err(CE_WARN, " Last setting will leave nxge%d with " 2448*4045d941Ssowmini " no link capabilities.", instance); 244944961713Sgirish cmn_err(CE_WARN, " Restoring previous setting."); 245044961713Sgirish for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) 245144961713Sgirish param_arr[i].value = param_arr[i].old_value; 245244961713Sgirish } 2453a3c5bd6dSspeer 245444961713Sgirish update_dev = B_FALSE; 245544961713Sgirish 245644961713Sgirish if (update_dev) { 245744961713Sgirish RW_ENTER_WRITER(&nxgep->filter_lock); 24581bd6825cSml NXGE_DEBUG_MSG((nxgep, NDD_CTL, 24591bd6825cSml "==> nxge_param_link_update: update dev")); 246044961713Sgirish (void) nxge_rx_mac_disable(nxgep); 246144961713Sgirish (void) nxge_tx_mac_disable(nxgep); 246244961713Sgirish (void) nxge_tx_mac_enable(nxgep); 246344961713Sgirish (void) nxge_rx_mac_enable(nxgep); 246444961713Sgirish RW_EXIT(&nxgep->filter_lock); 246544961713Sgirish } 246644961713Sgirish 246744961713Sgirish nxge_param_hw_update_exit: 246844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 2469*4045d941Ssowmini "<== nxge_param_link_update status = 0x%08x", status)); 247044961713Sgirish return (status); 247144961713Sgirish } 24721bd6825cSml 24731bd6825cSml /* 24741bd6825cSml * synchronize the adv* and en* parameters. 24751bd6825cSml * 24761bd6825cSml * See comments in <sys/dld.h> for details of the *_en_* 24771bd6825cSml * parameters. The usage of ndd for setting adv parameters will 24781bd6825cSml * synchronize all the en parameters with the nxge parameters, 24791bd6825cSml * implicitly disabling any settings made via dladm. 24801bd6825cSml */ 24811bd6825cSml static void 24821bd6825cSml nxge_param_sync(p_nxge_t nxgep) 24831bd6825cSml { 24841bd6825cSml p_nxge_param_t param_arr; 24851bd6825cSml param_arr = nxgep->param_arr; 24861bd6825cSml 24871bd6825cSml nxgep->param_en_pause = param_arr[param_anar_pause].value; 24881bd6825cSml nxgep->param_en_1000fdx = param_arr[param_anar_1000fdx].value; 24891bd6825cSml nxgep->param_en_100fdx = param_arr[param_anar_100fdx].value; 24901bd6825cSml nxgep->param_en_10fdx = param_arr[param_anar_10fdx].value; 24911bd6825cSml } 24921bd6825cSml 24931bd6825cSml /* ARGSUSED */ 24941bd6825cSml int 24951bd6825cSml nxge_dld_get_ip_opt(p_nxge_t nxgep, caddr_t cp) 24961bd6825cSml { 24971bd6825cSml uint32_t status, cfg_value; 24981bd6825cSml p_nxge_param_t pa = (p_nxge_param_t)cp; 24991bd6825cSml tcam_class_t class; 25001bd6825cSml 25011bd6825cSml NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_dld_get_ip_opt")); 25021bd6825cSml 25031bd6825cSml /* do the actual hw setup */ 25041bd6825cSml class = nxge_class_name_2value(nxgep, pa->name); 25051bd6825cSml if (class == -1) 25061bd6825cSml return (EINVAL); 25071bd6825cSml 25081bd6825cSml cfg_value = 0; 25091bd6825cSml status = nxge_fflp_ip_class_config_get(nxgep, class, &cfg_value); 25101bd6825cSml if (status != NXGE_OK) 25111bd6825cSml return (EINVAL); 25121bd6825cSml 25131bd6825cSml NXGE_DEBUG_MSG((nxgep, NDD_CTL, 25141bd6825cSml "nxge_param_get_ip_opt_get %x ", cfg_value)); 25151bd6825cSml 25161bd6825cSml pa->value = cfg_value; 25171bd6825cSml 25181bd6825cSml NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_ip_opt status ")); 25191bd6825cSml return (0); 25201bd6825cSml } 2521