14496171girish/*
24496171girish * CDDL HEADER START
34496171girish *
44496171girish * The contents of this file are subject to the terms of the
54496171girish * Common Development and Distribution License (the "License").
64496171girish * You may not use this file except in compliance with the License.
74496171girish *
84496171girish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
94496171girish * or http://www.opensolaris.org/os/licensing.
104496171girish * See the License for the specific language governing permissions
114496171girish * and limitations under the License.
124496171girish *
134496171girish * When distributing Covered Code, include this CDDL HEADER in each
144496171girish * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
154496171girish * If applicable, add the following below this CDDL HEADER, with the
164496171girish * fields enclosed by brackets "[]" replaced with your own identifying
174496171girish * information: Portions Copyright [yyyy] [name of copyright owner]
184496171girish *
194496171girish * CDDL HEADER END
204496171girish */
214496171girish/*
227b26d9fSantwona Behera * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
234496171girish * Use is subject to license terms.
244496171girish */
254496171girish
264496171girish#include <sys/nxge/nxge_impl.h>
27678453aspeer#include <sys/nxge/nxge_hio.h>
28678453aspeer
294496171girish#include <inet/common.h>
304496171girish#include <inet/mi.h>
314496171girish#include <inet/nd.h>
324496171girish
334496171girishextern uint64_t npi_debug_level;
344496171girish
35a3c5bd6speer#define	NXGE_PARAM_MAC_RW \
36a3c5bd6speer	NXGE_PARAM_RW | NXGE_PARAM_MAC | \
374496171girish	NXGE_PARAM_NDD_WR_OK | NXGE_PARAM_READ_PROP
384496171girish
39a3c5bd6speer#define	NXGE_PARAM_MAC_DONT_SHOW \
40a3c5bd6speer	NXGE_PARAM_RW | NXGE_PARAM_MAC | NXGE_PARAM_DONT_SHOW
414496171girish
42a3c5bd6speer#define	NXGE_PARAM_RXDMA_RW \
43a3c5bd6speer	NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_NDD_WR_OK | \
44a3c5bd6speer	NXGE_PARAM_READ_PROP
454496171girish
46a3c5bd6speer#define	NXGE_PARAM_RXDMA_RWC \
47a3c5bd6speer	NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_INIT_ONLY | \
48a3c5bd6speer	NXGE_PARAM_READ_PROP
494496171girish
50a3c5bd6speer#define	NXGE_PARAM_L2CLASS_CFG \
51a3c5bd6speer	NXGE_PARAM_RW | NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_READ_PROP | \
52a3c5bd6speer	NXGE_PARAM_NDD_WR_OK
534496171girish
54a3c5bd6speer#define	NXGE_PARAM_CLASS_RWS \
55a3c5bd6speer	NXGE_PARAM_RWS |  NXGE_PARAM_READ_PROP
564496171girish
574496171girish#define	NXGE_PARAM_ARRAY_INIT_SIZE	0x20ULL
584496171girish
594496171girish#define	SET_RX_INTR_TIME_DISABLE 0
604496171girish#define	SET_RX_INTR_TIME_ENABLE 1
614496171girish#define	SET_RX_INTR_PKTS 2
624496171girish
634496171girish#define	BASE_ANY	0
64a3c5bd6speer#define	BASE_BINARY 	2
654496171girish#define	BASE_HEX	16
664496171girish#define	BASE_DECIMAL	10
674496171girish#define	ALL_FF_64	0xFFFFFFFFFFFFFFFFULL
684496171girish#define	ALL_FF_32	0xFFFFFFFFUL
694496171girish
704496171girish#define	NXGE_NDD_INFODUMP_BUFF_SIZE	2048 /* is 2k enough? */
714496171girish#define	NXGE_NDD_INFODUMP_BUFF_8K	8192
724496171girish#define	NXGE_NDD_INFODUMP_BUFF_16K	0x2000
734496171girish#define	NXGE_NDD_INFODUMP_BUFF_64K	0x8000
744496171girish
754496171girish#define	PARAM_OUTOF_RANGE(vptr, eptr, rval, pa)	\
764496171girish	((vptr == eptr) || (rval < pa->minimum) || (rval > pa->maximum))
774496171girish
784496171girish#define	ADVANCE_PRINT_BUFFER(pmp, plen, rlen) { \
794496171girish	((mblk_t *)pmp)->b_wptr += plen; \
804496171girish	rlen -= plen; \
81a3c5bd6speer}
824496171girish
834045d94sowminiint nxge_param_set_mac(p_nxge_t, queue_t *,
84a3c5bd6speer	mblk_t *, char *, caddr_t);
854496171girishstatic int nxge_param_set_port_rdc(p_nxge_t, queue_t *,
86a3c5bd6speer	mblk_t *, char *, caddr_t);
874496171girishstatic int nxge_param_set_grp_rdc(p_nxge_t, queue_t *,
88a3c5bd6speer	mblk_t *, char *, caddr_t);
894496171girishstatic int nxge_param_set_ether_usr(p_nxge_t,
90a3c5bd6speer	queue_t *, mblk_t *, char *, caddr_t);
914496171girishstatic int nxge_param_set_ip_usr(p_nxge_t,
92a3c5bd6speer	queue_t *, mblk_t *, char *, caddr_t);
934496171girishstatic int nxge_param_set_vlan_rdcgrp(p_nxge_t,
94a3c5bd6speer	queue_t *, mblk_t *, char *, caddr_t);
954496171girishstatic int nxge_param_set_mac_rdcgrp(p_nxge_t,
96a3c5bd6speer	queue_t *, mblk_t *, char *, caddr_t);
974496171girishstatic int nxge_param_fflp_hash_init(p_nxge_t,
98a3c5bd6speer	queue_t *, mblk_t *, char *, caddr_t);
994496171girishstatic int nxge_param_llc_snap_enable(p_nxge_t, queue_t *,
100a3c5bd6speer	mblk_t *, char *, caddr_t);
1014496171girishstatic int nxge_param_hash_lookup_enable(p_nxge_t, queue_t *,
102a3c5bd6speer	mblk_t *, char *, caddr_t);
1034496171girishstatic int nxge_param_tcam_enable(p_nxge_t, queue_t *,
104a3c5bd6speer	mblk_t *, char *, caddr_t);
10556d930aspeerstatic int nxge_param_get_fw_ver(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
1062e59129raghusstatic int nxge_param_get_port_mode(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
1074496171girishstatic int nxge_param_get_rxdma_info(p_nxge_t, queue_t *q,
108a3c5bd6speer	p_mblk_t, caddr_t);
1094496171girishstatic int nxge_param_get_txdma_info(p_nxge_t, queue_t *q,
110a3c5bd6speer	p_mblk_t, caddr_t);
1114496171girishstatic int nxge_param_get_vlan_rdcgrp(p_nxge_t, queue_t *,
112a3c5bd6speer	p_mblk_t, caddr_t);
1134496171girishstatic int nxge_param_get_mac_rdcgrp(p_nxge_t, queue_t *,
114a3c5bd6speer	p_mblk_t, caddr_t);
1154496171girishstatic int nxge_param_get_rxdma_rdcgrp_info(p_nxge_t, queue_t *,
116a3c5bd6speer	p_mblk_t, caddr_t);
117c1f9c6eSantwona Beherastatic int nxge_param_get_rx_intr_time(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
118c1f9c6eSantwona Beherastatic int nxge_param_get_rx_intr_pkts(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
1194496171girishstatic int nxge_param_get_ip_opt(p_nxge_t, queue_t *, mblk_t *, caddr_t);
120a3c5bd6speerstatic int nxge_param_get_mac(p_nxge_t, queue_t *q, p_mblk_t, caddr_t);
1214496171girishstatic int nxge_param_get_debug_flag(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
1224496171girishstatic int nxge_param_set_nxge_debug_flag(p_nxge_t, queue_t *, mblk_t *,
123a3c5bd6speer	char *, caddr_t);
1244496171girishstatic int nxge_param_set_npi_debug_flag(p_nxge_t,
125a3c5bd6speer	queue_t *, mblk_t *, char *, caddr_t);
1264496171girishstatic int nxge_param_dump_rdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t);
1274496171girishstatic int nxge_param_dump_tdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t);
1284496171girishstatic int nxge_param_dump_mac_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
1294496171girishstatic int nxge_param_dump_ipp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
1304496171girishstatic int nxge_param_dump_fflp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
1314496171girishstatic int nxge_param_dump_vlan_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
1324496171girishstatic int nxge_param_dump_rdc_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
1334496171girishstatic int nxge_param_dump_ptrs(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
1341bd6825mlstatic void nxge_param_sync(p_nxge_t);
1354496171girish
1364496171girish/*
1374496171girish * Global array of Neptune changable parameters.
1384496171girish * This array is initialized to correspond to the default
1394496171girish * Neptune 4 port configuration. This array would be copied
1404496171girish * into each port's parameter structure and modifed per
1414496171girish * fcode and nxge.conf configuration. Later, the parameters are
1424496171girish * exported to ndd to display and run-time configuration (at least
1434496171girish * some of them).
1444496171girish *
1450016185yc * Parameters with DONT_SHOW are not shown by ndd.
1460016185yc *
1474496171girish */
1484496171girish
149a3c5bd6speerstatic nxge_param_t	nxge_param_arr[] = {
150a3c5bd6speer	/*
151a3c5bd6speer	 * min	max	value	old	hw-name	conf-name
152a3c5bd6speer	 */
153846a903ml	{ nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW,
154a3c5bd6speer		0, 999, 1000, 0, "instance", "instance"},
155a3c5bd6speer
156846a903ml	{ nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW,
157a3c5bd6speer		0, 999, 1000, 0, "main-instance", "main_instance"},
158a3c5bd6speer
159a3c5bd6speer	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ,
160a3c5bd6speer		0, 3, 0, 0, "function-number", "function_number"},
161a3c5bd6speer
162a3c5bd6speer	/* Partition Id */
163846a903ml	{ nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW,
164a3c5bd6speer		0, 8, 0, 0, "partition-id", "partition_id"},
165a3c5bd6speer
166a3c5bd6speer	/* Read Write Permission Mode */
167846a903ml	{ nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW,
168a3c5bd6speer		0, 2, 0, 0, "read-write-mode", "read_write_mode"},
169a3c5bd6speer
17056d930aspeer	{ nxge_param_get_fw_ver, NULL, NXGE_PARAM_READ,
17156d930aspeer		0, 32, 0, 0, "version",	"fw_version"},
17256d930aspeer
1732e59129raghus	{ nxge_param_get_port_mode, NULL, NXGE_PARAM_READ,
1742e59129raghus		0, 32, 0, 0, "port-mode", "port_mode"},
1752e59129raghus
176a3c5bd6speer	/* hw cfg types */
177a3c5bd6speer	/* control the DMA config of Neptune/NIU */
178846a903ml	{ nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW,
179a3c5bd6speer		CFG_DEFAULT, CFG_CUSTOM, CFG_DEFAULT, CFG_DEFAULT,
180a3c5bd6speer		"niu-cfg-type", "niu_cfg_type"},
181a3c5bd6speer
182a3c5bd6speer	/* control the TXDMA config of the Port controlled by tx-quick-cfg */
183846a903ml	{ nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW,
184a3c5bd6speer		CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT,
185a3c5bd6speer		"tx-qcfg-type", "tx_qcfg_type"},
186a3c5bd6speer
187a3c5bd6speer	/* control the RXDMA config of the Port controlled by rx-quick-cfg */
188846a903ml	{ nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW,
189a3c5bd6speer		CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT,
190a3c5bd6speer		"rx-qcfg-type", "rx_qcfg_type"},
191a3c5bd6speer
192a3c5bd6speer	{ nxge_param_get_mac, nxge_param_set_mac,
193a3c5bd6speer		NXGE_PARAM_RW  | NXGE_PARAM_DONT_SHOW,
194a3c5bd6speer		0, 1, 0, 0, "master-cfg-enable", "master_cfg_enable"},
195a3c5bd6speer
196a3c5bd6speer	{ nxge_param_get_mac, nxge_param_set_mac,
197846a903ml		NXGE_PARAM_DONT_SHOW,
198a3c5bd6speer		0, 1, 0, 0, "master-cfg-value", "master_cfg_value"},
199a3c5bd6speer
200a3c5bd6speer	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW,
201a3c5bd6speer		0, 1, 1, 1, "adv-autoneg-cap", "adv_autoneg_cap"},
202a3c5bd6speer
203a3c5bd6speer	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW,
204a3c5bd6speer		0, 1, 1, 1, "adv-10gfdx-cap", "adv_10gfdx_cap"},
205a3c5bd6speer
206a3c5bd6speer	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW,
207a3c5bd6speer		0, 1, 0, 0, "adv-10ghdx-cap", "adv_10ghdx_cap"},
208a3c5bd6speer
209a3c5bd6speer	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW,
210a3c5bd6speer		0, 1, 1, 1, "adv-1000fdx-cap", "adv_1000fdx_cap"},
211a3c5bd6speer
212a3c5bd6speer	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW,
213a3c5bd6speer		0, 1, 0, 0, "adv-1000hdx-cap",	"adv_1000hdx_cap"},
214a3c5bd6speer
215a3c5bd6speer	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW,
216a3c5bd6speer		0, 1, 0, 0, "adv-100T4-cap", "adv_100T4_cap"},
217a3c5bd6speer
218a3c5bd6speer	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW,
219a3c5bd6speer		0, 1, 1, 1, "adv-100fdx-cap", "adv_100fdx_cap"},
220a3c5bd6speer
221a3c5bd6speer	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW,
222a3c5bd6speer		0, 1, 0, 0, "adv-100hdx-cap", "adv_100hdx_cap"},
223a3c5bd6speer
224a3c5bd6speer	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW,
225a3c5bd6speer		0, 1, 1, 1, "adv-10fdx-cap", "adv_10fdx_cap"},
226a3c5bd6speer
227a3c5bd6speer	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW,
228a3c5bd6speer		0, 1, 0, 0, "adv-10hdx-cap", "adv_10hdx_cap"},
229a3c5bd6speer
230846a903ml	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW,
231a3c5bd6speer		0, 1, 0, 0, "adv-asmpause-cap",	"adv_asmpause_cap"},
232a3c5bd6speer
233a3c5bd6speer	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW,
234a3c5bd6speer		0, 1, 0, 0, "adv-pause-cap", "adv_pause_cap"},
235a3c5bd6speer
236846a903ml	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW,
237a3c5bd6speer		0, 1, 0, 0, "use-int-xcvr", "use_int_xcvr"},
238a3c5bd6speer
239846a903ml	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW,
240a3c5bd6speer		0, 1, 1, 1, "enable-ipg0", "enable_ipg0"},
241a3c5bd6speer
242846a903ml	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW,
243a3c5bd6speer		0, 255,	8, 8, "ipg0", "ipg0"},
244a3c5bd6speer
245846a903ml	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW,
246a3c5bd6speer		0, 255,	8, 8, "ipg1", "ipg1"},
247a3c5bd6speer
248846a903ml	{ nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW,
249a3c5bd6speer		0, 255,	4, 4, "ipg2", "ipg2"},
250a3c5bd6speer
251a3c5bd6speer	/* Transmit DMA channels */
252846a903ml	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ |
253846a903ml		NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
254a3c5bd6speer		0, 3, 0, 0, "tx-dma-weight", "tx_dma_weight"},
255a3c5bd6speer
256846a903ml	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ |
257846a903ml		NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
258a3c5bd6speer		0, 31, 0, 0, "tx-dma-channels-begin", "tx_dma_channels_begin"},
259a3c5bd6speer
260846a903ml	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ |
261846a903ml		NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
262a3c5bd6speer		0, 32, 0, 0, "tx-dma-channels", "tx_dma_channels"},
263a3c5bd6speer	{ nxge_param_get_txdma_info, NULL,
264846a903ml		NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
265a3c5bd6speer		0, 32, 0, 0, "tx-dma-info", "tx_dma_info"},
266a3c5bd6speer
267a3c5bd6speer	/* Receive DMA channels */
268a3c5bd6speer	{ nxge_param_get_generic, NULL,
269846a903ml		NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
270a3c5bd6speer		0, 31, 0, 0, "rx-dma-channels-begin", "rx_dma_channels_begin"},
271a3c5bd6speer
272846a903ml	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ |
273846a903ml		NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
274a3c5bd6speer		0, 32, 0, 0, "rx-dma-channels",	"rx_dma_channels"},
275a3c5bd6speer
276846a903ml	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ |
277846a903ml		NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
278a3c5bd6speer		0, 65535, PT_DRR_WT_DEFAULT_10G, 0,
279a3c5bd6speer		"rx-drr-weight", "rx_drr_weight"},
280a3c5bd6speer
281846a903ml	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ |
282846a903ml		NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW,
283a3c5bd6speer		0, 1, 1, 0, "rx-full-header", "rx_full_header"},
284a3c5bd6speer
285846a903ml	{ nxge_param_get_rxdma_info, NULL, NXGE_PARAM_READ |
286846a903ml		NXGE_PARAM_DONT_SHOW,
287a3c5bd6speer		0, 32, 0, 0, "rx-dma-info", "rx_dma_info"},
288a3c5bd6speer
289a3c5bd6speer	{ nxge_param_get_rxdma_info, NULL,
290a3c5bd6speer		NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW,
291a3c5bd6speer		NXGE_RBR_RBB_MIN, NXGE_RBR_RBB_MAX, NXGE_RBR_RBB_DEFAULT, 0,
292a3c5bd6speer		"rx-rbr-size", "rx_rbr_size"},
293a3c5bd6speer
294a3c5bd6speer	{ nxge_param_get_rxdma_info, NULL,
295a3c5bd6speer		NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW,
296a3c5bd6speer		NXGE_RCR_MIN, NXGE_RCR_MAX, NXGE_RCR_DEFAULT, 0,
297a3c5bd6speer		"rx-rcr-size", "rx_rcr_size"},
298a3c5bd6speer
299846a903ml	{ nxge_param_get_generic, nxge_param_set_port_rdc,
300846a903ml		NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
301a3c5bd6speer		0, 15, 0, 0, "default-port-rdc", "default_port_rdc"},
302a3c5bd6speer
303c1f9c6eSantwona Behera	{ nxge_param_get_rx_intr_time, nxge_param_rx_intr_time,
304c1f9c6eSantwona Behera		NXGE_PARAM_RXDMA_RW,
305a3c5bd6speer		NXGE_RDC_RCR_TIMEOUT_MIN, NXGE_RDC_RCR_TIMEOUT_MAX,
3067b26d9fSantwona Behera		NXGE_RDC_RCR_TIMEOUT, 0, "rxdma-intr-time", "rxdma_intr_time"},
307a3c5bd6speer
308c1f9c6eSantwona Behera	{ nxge_param_get_rx_intr_pkts, nxge_param_rx_intr_pkts,
309c1f9c6eSantwona Behera		NXGE_PARAM_RXDMA_RW,
310a3c5bd6speer		NXGE_RDC_RCR_THRESHOLD_MIN, NXGE_RDC_RCR_THRESHOLD_MAX,
3117b26d9fSantwona Behera		NXGE_RDC_RCR_THRESHOLD, 0,
312a3c5bd6speer		"rxdma-intr-pkts", "rxdma_intr_pkts"},
313a3c5bd6speer
314846a903ml	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP |
315846a903ml		NXGE_PARAM_DONT_SHOW,
316a3c5bd6speer		0, 8, 0, 0, "rx-rdc-grps-begin", "rx_rdc_grps_begin"},
317a3c5bd6speer
318846a903ml	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP |
319846a903ml		NXGE_PARAM_DONT_SHOW,
320a3c5bd6speer		0, 8, 0, 0, "rx-rdc-grps", "rx_rdc_grps"},
321a3c5bd6speer
322846a903ml	{ nxge_param_get_generic, nxge_param_set_grp_rdc,
323846a903ml		NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
324a3c5bd6speer		0, 15, 0, 0, "default-grp0-rdc", "default_grp0_rdc"},
325a3c5bd6speer
326846a903ml	{ nxge_param_get_generic, nxge_param_set_grp_rdc,
327846a903ml		NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
328a3c5bd6speer		0, 15,	2, 0, "default-grp1-rdc", "default_grp1_rdc"},
329a3c5bd6speer
330846a903ml	{ nxge_param_get_generic, nxge_param_set_grp_rdc,
331846a903ml		NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
332a3c5bd6speer		0, 15, 4, 0, "default-grp2-rdc", "default_grp2_rdc"},
333a3c5bd6speer
334846a903ml	{ nxge_param_get_generic, nxge_param_set_grp_rdc,
335846a903ml		NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
336a3c5bd6speer		0, 15, 6, 0, "default-grp3-rdc", "default_grp3_rdc"},
337a3c5bd6speer
338846a903ml	{ nxge_param_get_generic, nxge_param_set_grp_rdc,
339846a903ml		NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
340a3c5bd6speer		0, 15, 8, 0, "default-grp4-rdc", "default_grp4_rdc"},
341a3c5bd6speer
342846a903ml	{ nxge_param_get_generic, nxge_param_set_grp_rdc,
343846a903ml		NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
344a3c5bd6speer		0, 15, 10, 0, "default-grp5-rdc", "default_grp5_rdc"},
345a3c5bd6speer
346846a903ml	{ nxge_param_get_generic, nxge_param_set_grp_rdc,
347846a903ml		NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
348a3c5bd6speer		0, 15, 12, 0, "default-grp6-rdc", "default_grp6_rdc"},
349a3c5bd6speer
350846a903ml	{ nxge_param_get_generic, nxge_param_set_grp_rdc,
351846a903ml		NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW,
352a3c5bd6speer		0, 15, 14, 0, "default-grp7-rdc", "default_grp7_rdc"},
353a3c5bd6speer
354a3c5bd6speer	{ nxge_param_get_rxdma_rdcgrp_info, NULL,
355846a903ml		NXGE_PARAM_READ | NXGE_PARAM_CMPLX | NXGE_PARAM_DONT_SHOW,
356a3c5bd6speer		0, 8, 0, 0, "rdc-groups-info", "rdc_groups_info"},
357a3c5bd6speer
358a3c5bd6speer	/* Logical device groups */
359846a903ml	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW,
360a3c5bd6speer		0, 63, 0, 0, "start-ldg", "start_ldg"},
361a3c5bd6speer
362846a903ml	{ nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW,
363a3c5bd6speer		0, 64, 0, 0, "max-ldg", "max_ldg" },
364a3c5bd6speer
365a3c5bd6speer	/* MAC table information */
366a3c5bd6speer	{ nxge_param_get_mac_rdcgrp, nxge_param_set_mac_rdcgrp,
367846a903ml		NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW,
368a3c5bd6speer		0, 31, 0, 0, "mac-2rdc-grp", "mac_2rdc_grp"},
369a3c5bd6speer
370a3c5bd6speer	/* VLAN table information */
371a3c5bd6speer	{ nxge_param_get_vlan_rdcgrp, nxge_param_set_vlan_rdcgrp,
372846a903ml		NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW,
373a3c5bd6speer		0, 31, 0, 0, "vlan-2rdc-grp", "vlan_2rdc_grp"},
374a3c5bd6speer
375a3c5bd6speer	{ nxge_param_get_generic, NULL,
376846a903ml		NXGE_PARAM_READ_PROP | NXGE_PARAM_READ |
377846a903ml		NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_DONT_SHOW,
378a3c5bd6speer		0, 0x0ffff, 0x0ffff, 0, "fcram-part-cfg", "fcram_part_cfg"},
379a3c5bd6speer
380846a903ml	{ nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS |
381846a903ml		NXGE_PARAM_DONT_SHOW,
382a3c5bd6speer		0, 0x10, 0xa, 0, "fcram-access-ratio", "fcram_access_ratio"},
383a3c5bd6speer
384846a903ml	{ nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS |
385846a903ml		NXGE_PARAM_DONT_SHOW,
386a3c5bd6speer		0, 0x10, 0xa, 0, "tcam-access-ratio", "tcam_access_ratio"},
387a3c5bd6speer
388a3c5bd6speer	{ nxge_param_get_generic, nxge_param_tcam_enable,
389846a903ml		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
390a3c5bd6speer		0, 0x1, 0x0, 0, "tcam-enable", "tcam_enable"},
391a3c5bd6speer
392a3c5bd6speer	{ nxge_param_get_generic, nxge_param_hash_lookup_enable,
393846a903ml		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
394a3c5bd6speer		0, 0x01, 0x0, 0, "hash-lookup-enable", "hash_lookup_enable"},
395a3c5bd6speer
396a3c5bd6speer	{ nxge_param_get_generic, nxge_param_llc_snap_enable,
397846a903ml		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
398a3c5bd6speer		0, 0x01, 0x01, 0, "llc-snap-enable", "llc_snap_enable"},
399a3c5bd6speer
400a3c5bd6speer	{ nxge_param_get_generic, nxge_param_fflp_hash_init,
401846a903ml		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
402a3c5bd6speer		0, ALL_FF_32, ALL_FF_32, 0, "h1-init-value", "h1_init_value"},
403a3c5bd6speer
404a3c5bd6speer	{ nxge_param_get_generic,	nxge_param_fflp_hash_init,
405846a903ml		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
406a3c5bd6speer		0, 0x0ffff, 0x0ffff, 0, "h2-init-value", "h2_init_value"},
407a3c5bd6speer
408a3c5bd6speer	{ nxge_param_get_generic, nxge_param_set_ether_usr,
409a3c5bd6speer		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
410a3c5bd6speer		0, ALL_FF_32, 0x0, 0,
411a3c5bd6speer		"class-cfg-ether-usr1", "class_cfg_ether_usr1"},
412a3c5bd6speer
413a3c5bd6speer	{ nxge_param_get_generic, nxge_param_set_ether_usr,
414a3c5bd6speer		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
415a3c5bd6speer		0, ALL_FF_32, 0x0, 0,
416a3c5bd6speer		"class-cfg-ether-usr2", "class_cfg_ether_usr2"},
417a3c5bd6speer
418a3c5bd6speer	{ nxge_param_get_generic, nxge_param_set_ip_usr,
419a3c5bd6speer		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
420a3c5bd6speer		0, ALL_FF_32, 0x0, 0,
421a3c5bd6speer		"class-cfg-ip-usr4", "class_cfg_ip_usr4"},
422a3c5bd6speer
423a3c5bd6speer	{ nxge_param_get_generic, nxge_param_set_ip_usr,
424a3c5bd6speer		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
425a3c5bd6speer		0, ALL_FF_32, 0x0, 0,
426a3c5bd6speer		"class-cfg-ip-usr5", "class_cfg_ip_usr5"},
427a3c5bd6speer
428a3c5bd6speer	{ nxge_param_get_generic, nxge_param_set_ip_usr,
429a3c5bd6speer		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
430a3c5bd6speer		0, ALL_FF_32, 0x0, 0,
431a3c5bd6speer		"class-cfg-ip-usr6", "class_cfg_ip_usr6"},
432a3c5bd6speer
433a3c5bd6speer	{ nxge_param_get_generic, nxge_param_set_ip_usr,
434a3c5bd6speer		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
435a3c5bd6speer		0, ALL_FF_32, 0x0, 0,
436a3c5bd6speer		"class-cfg-ip-usr7", "class_cfg_ip_usr7"},
437a3c5bd6speer
438a3c5bd6speer	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt,
439a3c5bd6speer		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
440a3c5bd6speer		0, ALL_FF_32, 0x0, 0,
441a3c5bd6speer		"class-opt-ip-usr4", "class_opt_ip_usr4"},
442a3c5bd6speer
443a3c5bd6speer	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt,
444a3c5bd6speer		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
445a3c5bd6speer		0, ALL_FF_32, 0x0, 0,
446a3c5bd6speer		"class-opt-ip-usr5", "class_opt_ip_usr5"},
447a3c5bd6speer
448a3c5bd6speer	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt,
449a3c5bd6speer		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
450a3c5bd6speer		0, ALL_FF_32, 0x0, 0,
451a3c5bd6speer		"class-opt-ip-usr6", "class_opt_ip_usr6"},
452a3c5bd6speer
453a3c5bd6speer	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt,
454a3c5bd6speer		NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW,
455a3c5bd6speer		0, ALL_FF_32, 0x0, 0,
456a3c5bd6speer		"class-opt-ip-usr7", "class_opt_ip_usr7"},
457a3c5bd6speer
458a3c5bd6speer	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt,
459a3c5bd6speer		NXGE_PARAM_CLASS_RWS,
460a3c5bd6speer		0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
461a3c5bd6speer		"class-opt-ipv4-tcp", "class_opt_ipv4_tcp"},
462a3c5bd6speer
463a3c5bd6speer	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt,
464a3c5bd6speer		NXGE_PARAM_CLASS_RWS,
465a3c5bd6speer		0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
466a3c5bd6speer		"class-opt-ipv4-udp", "class_opt_ipv4_udp"},
467a3c5bd6speer
468a3c5bd6speer	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt,
469a3c5bd6speer		NXGE_PARAM_CLASS_RWS,
470a3c5bd6speer		0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
471a3c5bd6speer		"class-opt-ipv4-ah", "class_opt_ipv4_ah"},
472a3c5bd6speer
473a3c5bd6speer	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt,
474a3c5bd6speer		NXGE_PARAM_CLASS_RWS,
475a3c5bd6speer		0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
476a3c5bd6speer		"class-opt-ipv4-sctp", "class_opt_ipv4_sctp"},
477a3c5bd6speer
478a3c5bd6speer	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS,
479a3c5bd6speer		0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
480a3c5bd6speer		"class-opt-ipv6-tcp", "class_opt_ipv6_tcp"},
481a3c5bd6speer
482a3c5bd6speer	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS,
483a3c5bd6speer		0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
484a3c5bd6speer		"class-opt-ipv6-udp", "class_opt_ipv6_udp"},
485a3c5bd6speer
486a3c5bd6speer	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS,
487a3c5bd6speer		0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
488a3c5bd6speer		"class-opt-ipv6-ah", "class_opt_ipv6_ah"},
489a3c5bd6speer
490a3c5bd6speer	{ nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS,
491a3c5bd6speer		0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
492a3c5bd6speer		"class-opt-ipv6-sctp",	"class_opt_ipv6_sctp"},
493a3c5bd6speer
494a3c5bd6speer	{ nxge_param_get_debug_flag, nxge_param_set_nxge_debug_flag,
495846a903ml		NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW,
496a3c5bd6speer		0ULL, ALL_FF_64, 0ULL, 0ULL,
497a3c5bd6speer		"nxge-debug-flag", "nxge_debug_flag"},
498a3c5bd6speer
499a3c5bd6speer	{ nxge_param_get_debug_flag, nxge_param_set_npi_debug_flag,
500846a903ml		NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW,
501a3c5bd6speer		0ULL, ALL_FF_64, 0ULL, 0ULL,
502a3c5bd6speer		"npi-debug-flag", "npi_debug_flag"},
503a3c5bd6speer
504846a903ml	{ nxge_param_dump_tdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW,
505a3c5bd6speer		0, 0x0fffffff, 0x0fffffff, 0, "dump-tdc", "dump_tdc"},
506a3c5bd6speer
507846a903ml	{ nxge_param_dump_rdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW,
508a3c5bd6speer		0, 0x0fffffff, 0x0fffffff, 0, "dump-rdc", "dump_rdc"},
509a3c5bd6speer
510846a903ml	{ nxge_param_dump_mac_regs, NULL, NXGE_PARAM_READ |
511846a903ml		NXGE_PARAM_DONT_SHOW,
512a3c5bd6speer		0, 0x0fffffff, 0x0fffffff, 0, "dump-mac-regs", "dump_mac_regs"},
513a3c5bd6speer
514846a903ml	{ nxge_param_dump_ipp_regs, NULL, NXGE_PARAM_READ |
515846a903ml		NXGE_PARAM_DONT_SHOW,
516a3c5bd6speer		0, 0x0fffffff, 0x0fffffff, 0, "dump-ipp-regs", "dump_ipp_regs"},
517a3c5bd6speer
518846a903ml	{ nxge_param_dump_fflp_regs, NULL, NXGE_PARAM_READ |
519846a903ml		NXGE_PARAM_DONT_SHOW,
520a3c5bd6speer		0, 0x0fffffff, 0x0fffffff, 0,
521a3c5bd6speer		"dump-fflp-regs", "dump_fflp_regs"},
522a3c5bd6speer
523846a903ml	{ nxge_param_dump_vlan_table, NULL, NXGE_PARAM_READ |
524846a903ml		NXGE_PARAM_DONT_SHOW,
525a3c5bd6speer		0, 0x0fffffff, 0x0fffffff, 0,
526a3c5bd6speer		"dump-vlan-table", "dump_vlan_table"},
527a3c5bd6speer
528846a903ml	{ nxge_param_dump_rdc_table, NULL, NXGE_PARAM_READ |
529846a903ml		NXGE_PARAM_DONT_SHOW,
530a3c5bd6speer		0, 0x0fffffff, 0x0fffffff, 0,
531a3c5bd6speer		"dump-rdc-table", "dump_rdc_table"},
532a3c5bd6speer
533846a903ml	{ nxge_param_dump_ptrs,	NULL, NXGE_PARAM_READ |
534846a903ml		NXGE_PARAM_DONT_SHOW,
535a3c5bd6speer		0, 0x0fffffff, 0x0fffffff, 0, "dump-ptrs", "dump_ptrs"},
536a3c5bd6speer
537a3c5bd6speer	{  NULL, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW,
538a3c5bd6speer		0, 0x0fffffff, 0x0fffffff, 0, "end", "end"},
5394496171girish};
5404496171girish
5414496171girishextern void 		*nxge_list;
5424496171girish
5434496171girishvoid
5444496171girishnxge_get_param_soft_properties(p_nxge_t nxgep)
5454496171girish{
5464496171girish
5474496171girish	p_nxge_param_t 		param_arr;
5484496171girish	uint_t 			prop_len;
5494496171girish	int 			i, j;
550a3c5bd6speer	uint32_t		param_count;
551a3c5bd6speer	uint32_t		*int_prop_val;
5524496171girish
5534496171girish	NXGE_DEBUG_MSG((nxgep, DDI_CTL, " ==> nxge_get_param_soft_properties"));
5544496171girish
5554496171girish	param_arr = nxgep->param_arr;
5564496171girish	param_count = nxgep->param_count;
5574496171girish	for (i = 0; i < param_count; i++) {
5584496171girish		if ((param_arr[i].type & NXGE_PARAM_READ_PROP) == 0)
5594496171girish			continue;
5604496171girish		if ((param_arr[i].type & NXGE_PARAM_PROP_STR))
5614496171girish			continue;
5624496171girish		if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) ||
5634045d94sowmini		    (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) {
5644496171girish			if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY,
5654045d94sowmini			    nxgep->dip, 0, param_arr[i].fcode_name,
5664045d94sowmini			    (int **)&int_prop_val,
5674045d94sowmini			    (uint_t *)&prop_len)
5684045d94sowmini			    == DDI_PROP_SUCCESS) {
5694496171girish				uint32_t *cfg_value;
5704496171girish				uint64_t prop_count;
571a3c5bd6speer
5724496171girish				if (prop_len > NXGE_PARAM_ARRAY_INIT_SIZE)
5734496171girish					prop_len = NXGE_PARAM_ARRAY_INIT_SIZE;
574adfcba5joycey#if defined(__i386)
575adfcba5joycey				cfg_value =
5764045d94sowmini				    (uint32_t *)(int32_t)param_arr[i].value;
577adfcba5joycey#else
5784496171girish				cfg_value = (uint32_t *)param_arr[i].value;
579adfcba5joycey#endif
5804496171girish				for (j = 0; j < prop_len; j++) {
5814496171girish					cfg_value[j] = int_prop_val[j];
5824496171girish				}
5834496171girish				prop_count = prop_len;
5844496171girish				param_arr[i].type |=
5854496171girish				    (prop_count << NXGE_PARAM_ARRAY_CNT_SHIFT);
5864496171girish				ddi_prop_free(int_prop_val);
5874496171girish			}
5884496171girish			continue;
5894496171girish		}
5904496171girish
5914496171girish		if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0,
5924045d94sowmini		    param_arr[i].fcode_name,
5934045d94sowmini		    (int **)&int_prop_val,
5944045d94sowmini		    &prop_len) == DDI_PROP_SUCCESS) {
5954496171girish			if ((*int_prop_val >= param_arr[i].minimum) &&
5964045d94sowmini			    (*int_prop_val <= param_arr[i].maximum))
5974496171girish				param_arr[i].value = *int_prop_val;
5984496171girish#ifdef NXGE_DEBUG_ERROR
5994496171girish			else {
6004496171girish				NXGE_DEBUG_MSG((nxgep, OBP_CTL,
6014045d94sowmini				    "nxge%d: 'prom' file parameter error\n",
6024045d94sowmini				    nxgep->instance));
6034496171girish				NXGE_DEBUG_MSG((nxgep, OBP_CTL,
6044045d94sowmini				    "Parameter keyword '%s'"
6054045d94sowmini				    " is outside valid range\n",
6064045d94sowmini				    param_arr[i].name));
6074496171girish			}
6084496171girish#endif
6094496171girish			ddi_prop_free(int_prop_val);
6104496171girish		}
6114496171girish
6124496171girish		if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0,
6134045d94sowmini		    param_arr[i].name,
6144045d94sowmini		    (int **)&int_prop_val,
6154045d94sowmini		    &prop_len) == DDI_PROP_SUCCESS) {
6164496171girish			if ((*int_prop_val >= param_arr[i].minimum) &&
6174045d94sowmini			    (*int_prop_val <= param_arr[i].maximum))
6184496171girish				param_arr[i].value = *int_prop_val;
6194496171girish#ifdef NXGE_DEBUG_ERROR
6204496171girish			else {
6214496171girish				NXGE_DEBUG_MSG((nxgep, OBP_CTL,
6224045d94sowmini				    "nxge%d: 'conf' file parameter error\n",
6234045d94sowmini				    nxgep->instance));
6244496171girish				NXGE_DEBUG_MSG((nxgep, OBP_CTL,
6254045d94sowmini				    "Parameter keyword '%s'"
6264045d94sowmini				    "is outside valid range\n",
6274045d94sowmini				    param_arr[i].name));
6284496171girish			}
6294496171girish#endif
6304496171girish			ddi_prop_free(int_prop_val);
6314496171girish		}
6324496171girish	}
6334496171girish}
6344496171girish
6354496171girishstatic int
6364496171girishnxge_private_param_register(p_nxge_t nxgep, p_nxge_param_t param_arr)
6374496171girish{
6384496171girish	int status = B_TRUE;
6394496171girish	int channel;
6404496171girish	uint8_t grp;
6414496171girish	char *prop_name;
6424496171girish	char *end;
6434496171girish	uint32_t name_chars;
6444496171girish
6454496171girish	NXGE_DEBUG_MSG((nxgep, NDD2_CTL,
6464045d94sowmini	    "nxge_private_param_register %s", param_arr->name));
6474496171girish
6484496171girish	if ((param_arr->type & NXGE_PARAM_PRIV) != NXGE_PARAM_PRIV)
6494496171girish		return (B_TRUE);
650a3c5bd6speer
6514496171girish	prop_name =  param_arr->name;
6524496171girish	if (param_arr->type & NXGE_PARAM_RXDMA) {
6534496171girish		if (strncmp("rxdma_intr", prop_name, 10) == 0)
6544496171girish			return (B_TRUE);
6554496171girish		name_chars = strlen("default_grp");
6564496171girish		if (strncmp("default_grp", prop_name, name_chars) == 0) {
6574496171girish			prop_name += name_chars;
6584496171girish			grp = mi_strtol(prop_name, &end, 10);
6594496171girish				/* now check if this rdcgrp is in config */
6604496171girish			return (nxge_check_rdcgrp_port_member(nxgep, grp));
6614496171girish		}
6624496171girish		name_chars = strlen(prop_name);
6634496171girish		if (strncmp("default_port_rdc", prop_name, name_chars) == 0) {
6644496171girish			return (B_TRUE);
6654496171girish		}
6664496171girish		return (B_FALSE);
6674496171girish	}
6684496171girish
6694496171girish	if (param_arr->type & NXGE_PARAM_TXDMA) {
6704496171girish		name_chars = strlen("txdma");
6714496171girish		if (strncmp("txdma", prop_name, name_chars) == 0) {
6724496171girish			prop_name += name_chars;
6734496171girish			channel = mi_strtol(prop_name, &end, 10);
6744496171girish				/* now check if this rdc is in config */
6754496171girish			NXGE_DEBUG_MSG((nxgep, NDD2_CTL,
6764045d94sowmini			    " nxge_private_param_register: %d",
6774045d94sowmini			    channel));
6784496171girish			return (nxge_check_txdma_port_member(nxgep, channel));
6794496171girish		}
6804496171girish		return (B_FALSE);
6814496171girish	}
6824496171girish
6834496171girish	status = B_FALSE;
6844496171girish	NXGE_DEBUG_MSG((nxgep, NDD2_CTL, "<== nxge_private_param_register"));
6854496171girish
6864496171girish	return (status);
6874496171girish}
6884496171girish
6894496171girishvoid
6904496171girishnxge_setup_param(p_nxge_t nxgep)
6914496171girish{
6924496171girish	p_nxge_param_t param_arr;
6934496171girish	int i;
6944496171girish	pfi_t set_pfi;
6954496171girish
6964496171girish	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_setup_param"));
697a3c5bd6speer
6984496171girish	/*
6994496171girish	 * Make sure the param_instance is set to a valid device instance.
7004496171girish	 */
7014496171girish	if (nxge_param_arr[param_instance].value == 1000)
7024496171girish		nxge_param_arr[param_instance].value = nxgep->instance;
7034496171girish
7044496171girish	param_arr = nxgep->param_arr;
7054496171girish	param_arr[param_instance].value = nxgep->instance;
7064496171girish	param_arr[param_function_number].value = nxgep->function_num;
7074496171girish
7084496171girish	for (i = 0; i < nxgep->param_count; i++) {
7094496171girish		if ((param_arr[i].type & NXGE_PARAM_PRIV) &&
7104045d94sowmini		    (nxge_private_param_register(nxgep,
7114045d94sowmini		    &param_arr[i]) == B_FALSE)) {
7124496171girish			param_arr[i].setf = NULL;
7134496171girish			param_arr[i].getf = NULL;
7144496171girish		}
7154496171girish
7164496171girish		if (param_arr[i].type & NXGE_PARAM_CMPLX)
7174496171girish			param_arr[i].setf = NULL;
7184496171girish
7194496171girish		if (param_arr[i].type & NXGE_PARAM_DONT_SHOW) {
7204496171girish			param_arr[i].setf = NULL;
7214496171girish			param_arr[i].getf = NULL;
7224496171girish		}
7234496171girish
7244496171girish		set_pfi = (pfi_t)param_arr[i].setf;
7254496171girish
726a3c5bd6speer		if ((set_pfi) && (param_arr[i].type & NXGE_PARAM_INIT_ONLY)) {
7274496171girish			set_pfi = NULL;
7284496171girish		}
7294496171girish
7304496171girish	}
7314496171girish	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_setup_param"));
7324496171girish}
7334496171girish
7344496171girishvoid
7354496171girishnxge_init_param(p_nxge_t nxgep)
7364496171girish{
7374496171girish	p_nxge_param_t param_arr;
7384496171girish	int i, alloc_size;
7394496171girish	uint64_t alloc_count;
7404496171girish	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_init_param"));
7414496171girish	/*
7424496171girish	 * Make sure the param_instance is set to a valid device instance.
7434496171girish	 */
7444496171girish	if (nxge_param_arr[param_instance].value == 1000)
7454496171girish		nxge_param_arr[param_instance].value = nxgep->instance;
7464496171girish
7474496171girish	param_arr = nxgep->param_arr;
7484496171girish	if (param_arr == NULL) {
749a3c5bd6speer		param_arr = (p_nxge_param_t)
7504045d94sowmini		    KMEM_ZALLOC(sizeof (nxge_param_arr), KM_SLEEP);
7514496171girish	}
752a3c5bd6speer
7534496171girish	for (i = 0; i < sizeof (nxge_param_arr)/sizeof (nxge_param_t); i++) {
7544496171girish		param_arr[i] = nxge_param_arr[i];
7554496171girish		if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) ||
7564045d94sowmini		    (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) {
7574496171girish			alloc_count = NXGE_PARAM_ARRAY_INIT_SIZE;
7584496171girish			alloc_size = alloc_count * sizeof (uint64_t);
7594496171girish			param_arr[i].value =
760adfcba5joycey#if defined(__i386)
7614045d94sowmini			    (uint64_t)(uint32_t)KMEM_ZALLOC(alloc_size,
7624045d94sowmini			    KM_SLEEP);
763adfcba5joycey#else
7641bd6825ml			(uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP);
765adfcba5joycey#endif
7664496171girish			param_arr[i].old_value =
767adfcba5joycey#if defined(__i386)
7684045d94sowmini			    (uint64_t)(uint32_t)KMEM_ZALLOC(alloc_size,
7694045d94sowmini			    KM_SLEEP);
770adfcba5joycey#else
7714045d94sowmini			(uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP);
772adfcba5joycey#endif
7734496171girish			param_arr[i].type |=
7744045d94sowmini			    (alloc_count << NXGE_PARAM_ARRAY_ALLOC_SHIFT);
7754496171girish		}
7764496171girish	}
7774496171girish
7784496171girish	nxgep->param_arr = param_arr;
7794496171girish	nxgep->param_count = sizeof (nxge_param_arr)/sizeof (nxge_param_t);
7801bd6825ml
7811bd6825ml	nxge_param_sync(nxgep);
7821bd6825ml
7834496171girish	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_init_param: count %d",
7844045d94sowmini	    nxgep->param_count));
7854496171girish}
7864496171girish
7874496171girishvoid
7884496171girishnxge_destroy_param(p_nxge_t nxgep)
7894496171girish{
7904496171girish	int i;
7914496171girish	uint64_t free_size, free_count;
7924496171girish
7934496171girish	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_param"));
794a3c5bd6speer
79559ac0c1davemq	if (nxgep->param_arr == NULL)
79659ac0c1davemq		return;
7974496171girish	/*
7984496171girish	 * Make sure the param_instance is set to a valid device instance.
7994496171girish	 */
8004496171girish	if (nxge_param_arr[param_instance].value == nxgep->instance) {
8014496171girish		for (i = 0; i <= nxge_param_arr[param_instance].maximum; i++) {
8024496171girish			if ((ddi_get_soft_state(nxge_list, i) != NULL) &&
8034045d94sowmini			    (i != nxgep->instance))
8044496171girish				break;
8054496171girish		}
8064496171girish		nxge_param_arr[param_instance].value = i;
8074496171girish	}
8084496171girish
8094496171girish	for (i = 0; i < nxgep->param_count; i++)
8104496171girish		if ((nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR32) ||
8114045d94sowmini		    (nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR64)) {
8124496171girish			free_count = ((nxgep->param_arr[i].type &
8134045d94sowmini			    NXGE_PARAM_ARRAY_ALLOC_MASK) >>
8144045d94sowmini			    NXGE_PARAM_ARRAY_ALLOC_SHIFT);
8154496171girish			free_count = NXGE_PARAM_ARRAY_INIT_SIZE;
8164496171girish			free_size = sizeof (uint64_t) * free_count;
817adfcba5joycey#if defined(__i386)
818adfcba5joycey			KMEM_FREE((void *)(uint32_t)nxgep->param_arr[i].value,
8194045d94sowmini			    free_size);
820adfcba5joycey#else
8214496171girish			KMEM_FREE((void *)nxgep->param_arr[i].value, free_size);
822adfcba5joycey#endif
823adfcba5joycey#if defined(__i386)
824adfcba5joycey			KMEM_FREE((void *)(uint32_t)
8254045d94sowmini			    nxgep->param_arr[i].old_value, free_size);
826adfcba5joycey#else
8274496171girish			KMEM_FREE((void *)nxgep->param_arr[i].old_value,
8284045d94sowmini			    free_size);
829adfcba5joycey#endif
8304496171girish		}
8314496171girish
8324496171girish	KMEM_FREE(nxgep->param_arr, sizeof (nxge_param_arr));
8334496171girish	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_param"));
8344496171girish}
8354496171girish
8364496171girish/*
8374496171girish * Extracts the value from the 'nxge' parameter array and prints the
8384496171girish * parameter value. cp points to the required parameter.
8394496171girish */
840a3c5bd6speer
8414496171girish/* ARGSUSED */
8424496171girishint
8434496171girishnxge_param_get_generic(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
8444496171girish{
8454496171girish	p_nxge_param_t pa = (p_nxge_param_t)cp;
8464496171girish
847a3c5bd6speer	NXGE_DEBUG_MSG((nxgep, NDD_CTL,
8484045d94sowmini	    "==> nxge_param_get_generic name %s ", pa->name));
8494496171girish
8504496171girish	if (pa->value > 0xffffffff)
851a3c5bd6speer		(void) mi_mpprintf(mp, "%x%x",
8524045d94sowmini		    (int)(pa->value >> 32), (int)(pa->value & 0xffffffff));
8534496171girish	else
8544496171girish		(void) mi_mpprintf(mp, "%x", (int)pa->value);
8554496171girish
8564496171girish	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_generic"));
8574496171girish	return (0);
8584496171girish}
8594496171girish
8604496171girish/* ARGSUSED */
8614496171girishstatic int
8624496171girishnxge_param_get_mac(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
8634496171girish{
8644496171girish	p_nxge_param_t pa = (p_nxge_param_t)cp;
8654496171girish
8664496171girish	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac"));
8674496171girish
8684496171girish	(void) mi_mpprintf(mp, "%d", (uint32_t)pa->value);
8694496171girish	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_mac"));
8704496171girish	return (0);
8714496171girish}
8724496171girish
8734496171girish/* ARGSUSED */
87456d930aspeerstatic int
87556d930aspeernxge_param_get_fw_ver(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
87656d930aspeer{
87756d930aspeer	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_fw_ver"));
87856d930aspeer
87956d930aspeer	(void) mi_mpprintf(mp, "Firmware version for nxge%d:  %s\n",
88056d930aspeer	    nxgep->instance, nxgep->vpd_info.ver);
88156d930aspeer
88256d930aspeer	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_fw_ver"));
88356d930aspeer	return (0);
88456d930aspeer}
88556d930aspeer
88656d930aspeer/* ARGSUSED */
8872e59129raghusstatic int
8882e59129raghusnxge_param_get_port_mode(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
8892e59129raghus{
8902e59129raghus	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_port_mode"));
8912e59129raghus
8922e59129raghus	switch (nxgep->mac.portmode) {
8932e59129raghus	case PORT_1G_COPPER:
8942d17280sbehera		(void) mi_mpprintf(mp, "Port mode for nxge%d:  1G Copper %s\n",
8952d17280sbehera		    nxgep->instance,
8962d17280sbehera		    nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
8972e59129raghus		break;
8982e59129raghus	case PORT_1G_FIBER:
8992d17280sbehera		(void) mi_mpprintf(mp, "Port mode for nxge%d:  1G Fiber %s\n",
9002d17280sbehera		    nxgep->instance,
9012d17280sbehera		    nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
9022e59129raghus		break;
9032e59129raghus	case PORT_10G_COPPER:
9042d17280sbehera		(void) mi_mpprintf(mp, "Port mode for nxge%d:  10G Copper "
9052d17280sbehera		    "%s\n", nxgep->instance,
9062d17280sbehera		    nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
9072e59129raghus		break;
9082e59129raghus	case PORT_10G_FIBER:
9092d17280sbehera		(void) mi_mpprintf(mp, "Port mode for nxge%d:  10G Fiber %s\n",
9102d17280sbehera		    nxgep->instance,
9112d17280sbehera		    nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
9122e59129raghus		break;
9132e59129raghus	case PORT_10G_SERDES:
9142d17280sbehera		(void) mi_mpprintf(mp, "Port mode for nxge%d:  10G Serdes "
9152d17280sbehera		    "%s\n", nxgep->instance,
9162d17280sbehera		    nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
9172e59129raghus		break;
9182e59129raghus	case PORT_1G_SERDES:
9192d17280sbehera		(void) mi_mpprintf(mp, "Port mode for nxge%d:  1G Serdes %s\n",
9202d17280sbehera		    nxgep->instance,
9212d17280sbehera		    nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
9222e59129raghus		break;
9232e59129raghus	case PORT_1G_RGMII_FIBER:
9242e59129raghus		(void) mi_mpprintf(mp, "Port mode for nxge%d:  1G RGMII "
9252d17280sbehera		    "Fiber %s\n", nxgep->instance,
9262d17280sbehera		    nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
9272d17280sbehera		break;
9282d17280sbehera	case PORT_HSP_MODE:
9292d17280sbehera		(void) mi_mpprintf(mp, "Port mode for nxge%d:  Hot Swappable "
9302d17280sbehera		    "PHY, Currently NOT present\n", nxgep->instance);
9312e59129raghus		break;
9320016185yc	case PORT_10G_TN1010:
9330016185yc		(void) mi_mpprintf(mp, "Port mode for nxge%d:"
9340016185yc		    " 10G Copper with TN1010 %s\n", nxgep->instance,
9350016185yc		    nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
9360016185yc		break;
9370016185yc	case PORT_1G_TN1010:
938c6e5ef5yc		(void) mi_mpprintf(mp, "Port mode for nxge%d:"
9390016185yc		    " 1G Copper with TN1010 %s\n", nxgep->instance,
9400016185yc		    nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
9410016185yc		break;
9422e59129raghus	default:
9432d17280sbehera		(void) mi_mpprintf(mp, "Port mode for nxge%d:  Unknown %s\n",
9442d17280sbehera		    nxgep->instance,
9452d17280sbehera		    nxgep->hot_swappable_phy ? "[Hot Swappable]" : "");
9462e59129raghus		break;
9472e59129raghus	}
9482e59129raghus
9493d16f8eml	(void) mi_mpprintf(mp, "Software LSO for nxge%d: %s\n",
9503d16f8eml	    nxgep->instance,
9513d16f8eml	    nxgep->soft_lso_enable ? "enable" : "disable");
9523d16f8eml
9532e59129raghus	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_port_mode"));
9542e59129raghus	return (0);
9552e59129raghus}
9562e59129raghus
9572e59129raghus/* ARGSUSED */
958c1f9c6eSantwona Beherastatic int
959c1f9c6eSantwona Beheranxge_param_get_rx_intr_time(p_nxge_t nxgep, queue_t *q, mblk_t *mp, caddr_t cp)
960c1f9c6eSantwona Behera{
961c1f9c6eSantwona Behera	p_nxge_param_t pa = (p_nxge_param_t)cp;
962c1f9c6eSantwona Behera
963c1f9c6eSantwona Behera	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rx_intr_time"));
964c1f9c6eSantwona Behera
965c1f9c6eSantwona Behera	pa->value = (uint32_t)nxgep->intr_timeout;
966c1f9c6eSantwona Behera	(void) mi_mpprintf(mp, "%d", (uint32_t)nxgep->intr_timeout);
967c1f9c6eSantwona Behera
968c1f9c6eSantwona Behera	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rx_intr_time"));
969c1f9c6eSantwona Behera	return (0);
970c1f9c6eSantwona Behera}
971c1f9c6eSantwona Behera
972c1f9c6eSantwona Behera/* ARGSUSED */
973c1f9c6eSantwona Beherastatic int
974c1f9c6eSantwona Beheranxge_param_get_rx_intr_pkts(p_nxge_t nxgep, queue_t *q, mblk_t *mp, caddr_t cp)
975c1f9c6eSantwona Behera{
976c1f9c6eSantwona Behera	p_nxge_param_t pa = (p_nxge_param_t)cp;
977c1f9c6eSantwona Behera
978c1f9c6eSantwona Behera	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rx_intr_pkts"));
979c1f9c6eSantwona Behera
980c1f9c6eSantwona Behera	pa->value = (uint32_t)nxgep->intr_threshold;
981c1f9c6eSantwona Behera	(void) mi_mpprintf(mp, "%d", (uint32_t)nxgep->intr_threshold);
982c1f9c6eSantwona Behera
983c1f9c6eSantwona Behera	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rx_intr_pkts"));
984c1f9c6eSantwona Behera	return (0);
985c1f9c6eSantwona Behera}
986c1f9c6eSantwona Behera
987c1f9c6eSantwona Behera/* ARGSUSED */
9884496171girishint
9894496171girishnxge_param_get_txdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
9904496171girish{
9914496171girish
992678453aspeer	uint_t print_len, buf_len;
9934496171girish	p_mblk_t np;
9944496171girish
9954496171girish	int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE;
996678453aspeer	int tdc;
997678453aspeer
998678453aspeer	nxge_grp_set_t *set;
999678453aspeer
10004496171girish	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_txdma_info"));
10014496171girish
1002a3c5bd6speer	(void) mi_mpprintf(mp, "TXDMA Information for Port\t %d \n",
10034045d94sowmini	    nxgep->function_num);
10044496171girish
10054496171girish	if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) {
10064496171girish		(void) mi_mpprintf(mp, "%s\n", "out of buffer");
10074496171girish		return (0);
10084496171girish	}
10094496171girish
10104496171girish	buf_len = buff_alloc_size;
10114496171girish	mp->b_cont = np;
1012678453aspeer	print_len = 0;
10134496171girish
10144496171girish	print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
10154045d94sowmini	    "TDC\t HW TDC\t\n");
10164496171girish	((mblk_t *)np)->b_wptr += print_len;
10174496171girish	buf_len -= print_len;
1018678453aspeer
1019678453aspeer	set = &nxgep->tx_set;
1020da14cebEric Cheng	for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) {
1021678453aspeer		if ((1 << tdc) & set->owned.map) {
1022678453aspeer			print_len = snprintf((char *)((mblk_t *)np)->b_wptr,
1023678453aspeer			    buf_len, "%d\n", tdc);
1024678453aspeer			((mblk_t *)np)->b_wptr += print_len;
1025678453aspeer			buf_len -= print_len;
1026678453aspeer		}
10274496171girish	}
1028a3c5bd6speer
10294496171girish	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_txdma_info"));
10304496171girish	return (0);
10314496171girish}
10324496171girish
10334496171girish/* ARGSUSED */
10344496171girishint
10354496171girishnxge_param_get_rxdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp)
10364496171girish{
1037a3c5bd6speer	uint_t			print_len, buf_len;
1038a3c5bd6speer	p_mblk_t		np;
1039a3c5bd6speer	int			rdc;
10404496171girish	p_nxge_dma_pt_cfg_t	p_dma_cfgp;
10414496171girish	p_nxge_hw_pt_cfg_t	p_cfgp;
1042a3c5bd6speer	int			buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE;
10434496171girish	p_rx_rcr_rings_t 	rx_rcr_rings;
10444496171girish	p_rx_rcr_ring_t		*rcr_rings;
10454496171girish	p_rx_rbr_rings_t 	rx_rbr_rings;
10464496171girish	p_rx_rbr_ring_t		*rbr_rings;
1047678453aspeer	nxge_grp_set_t		*set;
10484496171girish
10494496171girish	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rxdma_info"));
10504496171girish
1051a3c5bd6speer	(void) mi_mpprintf(mp, "RXDMA Information for Port\t %d \n",
10524045d94sowmini	    nxgep->function_num);
10534496171girish
10544496171girish	if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) {
10554496171girish		/* The following may work even if we cannot get a large buf. */
10564496171girish		(void) mi_mpprintf(mp, "%s\n", "out of buffer");
10574496171girish		return (0);
10584496171girish	}
10594496171girish
10604496171girish	buf_len = buff_alloc_size;
10614496171girish	mp->b_cont = np;
10624496171girish	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
10634496171girish	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
10644496171girish
10654496171girish	rx_rcr_rings = nxgep->rx_rcr_rings;
10664496171girish	rcr_rings = rx_rcr_rings->rcr_rings;
10674496171girish	rx_rbr_rings = nxgep->rx_rbr_rings;
10684496171girish	rbr_rings = rx_rbr_rings->rbr_rings;
10694496171girish
10704496171girish	print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
10714045d94sowmini	    "Total RDCs\t %d\n", p_cfgp->max_rdcs);
10724496171girish
10734496171girish	((mblk_t *)np)->b_wptr += print_len;
10744496171girish	buf_len -= print_len;
10754496171girish	print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
10764045d94sowmini	    "RDC\t HW RDC\t Timeout\t Packets RBR ptr \t"
10774045d94sowmini	    "chunks\t RCR ptr\n");
1078a3c5bd6speer
10794496171girish	((mblk_t *)np)->b_wptr += print_len;
10804496171girish	buf_len -= print_len;
1081678453aspeer
1082678453aspeer	set = &nxgep->rx_set;
1083678453aspeer	for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) {
1084678453aspeer		if ((1 << rdc) & set->owned.map) {
1085678453aspeer			print_len = snprintf((char *)
1086678453aspeer			    ((mblk_t *)np)->b_wptr, buf_len,
1087678453aspeer			    " %d\t   %x\t\t %x\t $%p\t 0x%x\t $%p\n",
1088678453aspeer			    rdc,
1089678453aspeer			    p_dma_cfgp->rcr_timeout[rdc],
1090678453aspeer			    p_dma_cfgp->rcr_threshold[rdc],
10918793b36Nick Todd			    (void *)rbr_rings[rdc],
10928793b36Nick Todd			    rbr_rings[rdc]->num_blocks, (void *)rcr_rings[rdc]);
1093a3c5bd6speer			((mblk_t *)np)->b_wptr += print_len;
1094a3c5bd6speer			buf_len -= print_len;
1095678453aspeer		}
10964496171girish	}
1097a3c5bd6speer
10984496171girish	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rxdma_info"));
10994496171girish	return (0);
11004496171girish}
11014496171girish
11024496171girish/* ARGSUSED */
11034496171girishint
11044496171girishnxge_param_get_rxdma_rdcgrp_info(p_nxge_t nxgep, queue_t *q,
1105fe054a6Toomas Soome    p_mblk_t mp, caddr_t cp)
11064496171girish{
1107a3c5bd6speer	uint_t			print_len, buf_len;
1108a3c5bd6speer	p_mblk_t		np;
1109a3c5bd6speer	int			offset, rdc, i, rdc_grp;
11104496171girish	p_nxge_rdc_grp_t	rdc_grp_p;
11114496171girish	p_nxge_dma_pt_cfg_t	p_dma_cfgp;
11124496171girish	p_nxge_hw_pt_cfg_t	p_cfgp;
11134496171girish
11144496171girish	int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE;
11154496171girish	NXGE_DEBUG_MSG((nxgep, NDD_CTL,
11164045d94sowmini	    "==> nxge_param_get_rxdma_rdcgrp_info"));
11174496171girish
11184496171girish	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
11194496171girish	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
11204496171girish
1121a3c5bd6speer	(void) mi_mpprintf(mp, "RXDMA RDC Group Information for Port\t %d \n",
11224045d94sowmini	    nxgep->function_num);
11234496171girish
1124678453aspeer	rdc_grp = p_cfgp->def_mac_rxdma_grpid;
11254496171girish	if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) {
11264496171girish		/* The following may work even if we cannot get a large buf. */
11274496171girish		(void) mi_mpprintf(mp, "%s\n", "out of buffer");
11284496171girish		return (0);
11294496171girish	}
11304496171girish
11314496171girish	buf_len = buff_alloc_size;
11324496171girish	mp->b_cont = np;
11334496171girish	print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
11344045d94sowmini	    "Total RDC Groups\t %d \n"
11354045d94sowmini	    "default RDC group\t %d\n",
11364045d94sowmini	    p_cfgp->max_rdc_grpids,
11374045d94sowmini	    p_cfgp->def_mac_rxdma_grpid);
11384496171girish
11394496171girish	((mblk_t *)np)->b_wptr += print_len;
11404496171girish	buf_len -= print_len;
11414496171girish
11427b26d9fSantwona Behera	for (i = 0; i < NXGE_MAX_RDC_GROUPS; i++) {
1143678453aspeer		if (p_cfgp->grpids[i]) {
1144678453aspeer			rdc_grp_p = &p_dma_cfgp->rdc_grps[i];
11454496171girish			print_len = snprintf((char *)((mblk_t *)np)->b_wptr,
1146678453aspeer			    buf_len,
1147678453aspeer			    "\nRDC Group Info for Group [%d] %d\n"
1148678453aspeer			    "RDC Count %d\tstart RDC %d\n"
1149678453aspeer			    "RDC Group Population Information"
1150678453aspeer			    " (offsets 0 - 15)\n",
1151678453aspeer			    i, rdc_grp, rdc_grp_p->max_rdcs,
1152678453aspeer			    rdc_grp_p->start_rdc);
1153678453aspeer
1154678453aspeer			((mblk_t *)np)->b_wptr += print_len;
1155678453aspeer			buf_len -= print_len;
1156678453aspeer			print_len = snprintf((char *)((mblk_t *)np)->b_wptr,
1157678453aspeer			    buf_len, "\n");
1158678453aspeer			((mblk_t *)np)->b_wptr += print_len;
1159678453aspeer			buf_len -= print_len;
1160678453aspeer
1161678453aspeer			for (rdc = 0; rdc < rdc_grp_p->max_rdcs; rdc++) {
1162678453aspeer				print_len = snprintf(
11634045d94sowmini				    (char *)((mblk_t *)np)->b_wptr,
11644045d94sowmini				    buf_len, "[%d]=%d ", rdc,
11654045d94sowmini				    rdc_grp_p->start_rdc + rdc);
1166678453aspeer				((mblk_t *)np)->b_wptr += print_len;
1167678453aspeer				buf_len -= print_len;
1168678453aspeer			}
1169678453aspeer			print_len = snprintf((char *)((mblk_t *)np)->b_wptr,
1170678453aspeer			    buf_len, "\n");
11714496171girish			((mblk_t *)np)->b_wptr += print_len;
11724496171girish			buf_len -= print_len;
11734496171girish
1174678453aspeer			for (offset = 0; offset < 16; offset++) {
1175678453aspeer				print_len = snprintf(
11764045d94sowmini				    (char *)((mblk_t *)np)->b_wptr,
11774045d94sowmini				    buf_len, " %c",
11784045d94sowmini				    rdc_grp_p->map & (1 << offset) ?
11794045d94sowmini				    '1' : '0');
1180678453aspeer				((mblk_t *)np)->b_wptr += print_len;
1181678453aspeer				buf_len -= print_len;
1182678453aspeer			}
11834496171girish			print_len = snprintf((char *)((mblk_t *)np)->b_wptr,
1184678453aspeer			    buf_len, "\n");
11854496171girish			((mblk_t *)np)->b_wptr += print_len;
11864496171girish			buf_len -= print_len;
11874496171girish		}
11884496171girish	}
11894496171girish	NXGE_DEBUG_MSG((nxgep, NDD_CTL,
11904045d94sowmini	    "<== nxge_param_get_rxdma_rdcgrp_info"));
11914496171girish	return (0);
11924496171girish}
11934496171girish
11944496171girishint
11954496171girishnxge_mk_mblk_tail_space(p_mblk_t mp, p_mblk_t *nmp, size_t size)
11964496171girish{
11974496171girish	p_mblk_t tmp;
11984496171girish
11994496171girish	tmp = mp;
12004496171girish	while (tmp->b_cont)
12014496171girish		tmp = tmp->b_cont;
12024496171girish	if ((tmp->b_wptr + size) >= tmp->b_datap->db_lim) {
12034496171girish		tmp->b_cont = allocb(1024, BPRI_HI);
12044496171girish		tmp = tmp->b_cont;
12054496171girish		if (!tmp)
12064496171girish			return (ENOMEM);
12074496171girish	}
1208a3c5bd6speer
12094496171girish	*nmp = tmp;
12104496171girish	return (0);
12114496171girish}
12124496171girish
1213a3c5bd6speer
12144496171girish/* ARGSUSED */
12154496171girishint
12164496171girishnxge_param_set_generic(p_nxge_t nxgep, queue_t *q, mblk_t *mp,
1217fe054a6Toomas Soome    char *value, caddr_t cp)
12184496171girish{
12194496171girish	char *end;
12204496171girish	uint32_t new_value;
12214496171girish	p_nxge_param_t pa = (p_nxge_param_t)cp;
12224496171girish
12234496171girish	NXGE_DEBUG_MSG((nxgep, IOC_CTL, " ==> nxge_param_set_generic"));
12244496171girish	new_value = (uint32_t)mi_strtol(value, &end, 10);
12254496171girish	if (end == value || new_value < pa->minimum ||
12264045d94sowmini	    new_value > pa->maximum) {
12274496171girish			return (EINVAL);
12284496171girish	}
12294496171girish	pa->value = new_value;
12304496171girish	NXGE_DEBUG_MSG((nxgep, IOC_CTL, " <== nxge_param_set_generic"));
12314496171girish	return (0);
12324496171girish}
12334496171girish
12344496171girish
1235a3c5bd6speer/* ARGSUSED */
12364496171girishint
1237a3c5bd6speernxge_param_set_instance(p_nxge_t nxgep, queue_t *q, mblk_t *mp,
1238fe054a6Toomas Soome    char *value, caddr_t cp)
12394496171girish{
12404496171girish	NXGE_DEBUG_MSG((nxgep, NDD_CTL, " ==> nxge_param_set_instance"));
12414496171girish	NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_set_instance"));
12424496171girish	return (0);
12434496171girish}
12444496171girish
12454496171girish
1246a3c5bd6speer/* ARGSUSED */
12474496171girishint
1248a3c5bd6speernxge_param_set_mac(p_nxge_t nxgep, queue_t *q, mblk_t *mp,
1249fe054a6Toomas Soome    char *value, caddr_t cp)
12504496171girish{
1251a3c5bd6speer	char		*end;
1252a3c5bd6speer	uint32_t	new_value;
1253a3c5bd6speer	int		status = 0;
1254a3c5bd6speer	p_nxge_param_t	pa = (p_nxge_param_t)cp;
12554496171girish
12564496171girish	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac"));
12574496171girish	new_value = (uint32_t)mi_strtol(value, &end, BASE_DECIMAL);
12584496171girish	if (PARAM_OUTOF_RANGE(value, end, new_value, pa)) {
12594496171girish		return (EINVAL);
12604496171girish	}
12614496171girish
12624496171girish	if (pa->value != new_value) {
12634496171girish		pa->old_value = pa->value;
12644496171girish		pa->value = new_value;
12654496171girish	}
12664496171girish
12674496171girish	if (!nxge_param_link_update(nxgep)) {
12684496171girish		NXGE_DEBUG_MSG((nxgep, NDD_CTL,
12694045d94sowmini		    " false ret from nxge_param_link_update"));
12704496171girish		status = EINVAL;
12714496171girish	}
12724496171girish
12734496171girish	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac"));
12744496171girish	return (status);
12754496171girish}
12764496171girish
12774496171girish/* ARGSUSED */
12781bd6825mlint
1279a3c5bd6speernxge_param_rx_intr_pkts(p_nxge_t nxgep, queue_t *q, mblk_t *mp,
1280fe054a6Toomas Soome    char *value, caddr_t cp)
12814496171girish{
1282a3c5bd6speer	char		*end;
1283a3c5bd6speer	uint32_t	cfg_value;
1284a3c5bd6speer	p_nxge_param_t	pa = (p_nxge_param_t)cp;
128514ea4bbsd
12864496171girish	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_pkts"));
12874496171girish
128814ea4bbsd	cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY);
12894496171girish
129014ea4bbsd	if ((cfg_value > NXGE_RDC_RCR_THRESHOLD_MAX) ||
12914045d94sowmini	    (cfg_value < NXGE_RDC_RCR_THRESHOLD_MIN)) {
12924496171girish		return (EINVAL);
12934496171girish	}
129414ea4bbsd
129514ea4bbsd	if ((pa->value != cfg_value)) {
129614ea4bbsd		pa->old_value = pa->value;
129714ea4bbsd		pa->value = cfg_value;
129814ea4bbsd		nxgep->intr_threshold = pa->value;
12994496171girish	}
130014ea4bbsd
13014496171girish	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_pkts"));
13024496171girish	return (0);
13034496171girish}
13044496171girish
13054496171girish/* ARGSUSED */
13061bd6825mlint
1307a3c5bd6speernxge_param_rx_intr_time(p_nxge_t nxgep, queue_t *q, mblk_t *mp,
1308fe054a6Toomas Soome    char *value, caddr_t cp)
13094496171girish{
1310a3c5bd6speer	char		*end;
1311a3c5bd6speer	uint32_t	cfg_value;
1312a3c5bd6speer	p_nxge_param_t	pa = (p_nxge_param_t)cp;
13134496171girish
13144496171girish	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_time"));
13154496171girish
131614ea4bbsd	cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY);
13174496171girish
131814ea4bbsd	if ((cfg_value > NXGE_RDC_RCR_TIMEOUT_MAX) ||
13194045d94sowmini	    (cfg_value < NXGE_RDC_RCR_TIMEOUT_MIN)) {
13204496171girish		return (EINVAL);
13214496171girish	}
13224496171girish
132314ea4bbsd	if ((pa->value != cfg_value)) {
132414ea4bbsd		pa->old_value = pa->value;
132514ea4bbsd		pa->value = cfg_value;
132614ea4bbsd		nxgep->intr_timeout = pa->value;
13274496171girish	}
13284496171girish
13294496171girish	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_time"));
13304496171girish	return (0);
13314496171girish}
13324496171girish
13334496171girish/* ARGSUSED */
13344496171girishstatic int
13354496171girishnxge_param_set_mac_rdcgrp(p_nxge_t nxgep, queue_t *q,
1336fe054a6Toomas Soome    mblk_t *mp, char *value, caddr_t cp)
13374496171girish{
1338a3c5bd6speer	char			 *end;
1339a3c5bd6speer	uint32_t		status = 0, cfg_value;
1340a3c5bd6speer	p_nxge_param_t		pa = (p_nxge_param_t)cp;
1341a3c5bd6speer	uint32_t		cfg_it = B_FALSE;
13424496171girish	p_nxge_dma_pt_cfg_t	p_dma_cfgp;
13434496171girish	p_nxge_hw_pt_cfg_t	p_cfgp;
1344a3c5bd6speer	uint32_t		*val_ptr, *old_val_ptr;
1345a3c5bd6speer	nxge_param_map_t	*mac_map;
1346a3c5bd6speer	p_nxge_class_pt_cfg_t	p_class_cfgp;
1347a3c5bd6speer	nxge_mv_cfg_t		*mac_host_info;
13484496171girish
13494496171girish	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac_rdcgrp "));
13504496171girish
13514496171girish	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
13524496171girish	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
13534496171girish	p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
13544496171girish	mac_host_info = (nxge_mv_cfg_t	*)&p_class_cfgp->mac_host_info[0];
13554496171girish	cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX);
1356a3c5bd6speer
1357a3c5bd6speer	/*
1358a3c5bd6speer	 * now do decoding
1359a3c5bd6speer	 */
13604496171girish	mac_map = (nxge_param_map_t *)&cfg_value;
1361a3c5bd6speer	NXGE_DEBUG_MSG((nxgep, NDD_CTL, " cfg_value %x id %x map_to %x",
13624045d94sowmini	    cfg_value, mac_map->param_id, mac_map->map_to));
13634496171girish
13644496171girish	if ((mac_map->param_id < p_cfgp->max_macs) &&
1365678453aspeer	    p_cfgp->grpids[mac_map->map_to]) {
13664496171girish		NXGE_DEBUG_MSG((nxgep, NDD_CTL,
1367678453aspeer		    " nxge_param_set_mac_rdcgrp mapping"
1368678453aspeer		    " id %d grp %d", mac_map->param_id, mac_map->map_to));
1369adfcba5joycey#if defined(__i386)
1370adfcba5joycey		val_ptr = (uint32_t *)(uint32_t)pa->value;
1371adfcba5joycey#else
13724496171girish		val_ptr = (uint32_t *)pa->value;
1373adfcba5joycey#endif
1374adfcba5joycey#if defined(__i386)
1375adfcba5joycey		old_val_ptr = (uint32_t *)(uint32_t)pa->old_value;
1376adfcba5joycey#else
13774496171girish		old_val_ptr = (uint32_t *)pa->old_value;
1378adfcba5joycey#endif
13794496171girish		if (val_ptr[mac_map->param_id] != cfg_value) {
13804496171girish			old_val_ptr[mac_map->param_id] =
1381678453aspeer			    val_ptr[mac_map->param_id];
13824496171girish			val_ptr[mac_map->param_id] = cfg_value;
13834496171girish			mac_host_info[mac_map->param_id].mpr_npr =
1384678453aspeer			    mac_map->pref;
13854496171girish			mac_host_info[mac_map->param_id].flag = 1;
13864496171girish			mac_host_info[mac_map->param_id].rdctbl =
1387678453aspeer			    mac_map->map_to;
13884496171girish			cfg_it = B_TRUE;
13894496171girish		}
13904496171girish	} else {
13914496171girish		return (EINVAL);
13924496171girish	}
13934496171girish
13944496171girish	if (cfg_it == B_TRUE) {
13954496171girish		status = nxge_logical_mac_assign_rdc_table(nxgep,
1396678453aspeer		    (uint8_t)mac_map->param_id);
13974496171girish		if (status != NXGE_OK)
13984496171girish			return (EINVAL);
13994496171girish	}
14004496171girish
14014496171girish	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac_rdcgrp"));
14024496171girish	return (0);
14034496171girish}
14044496171girish
14054496171girish/* ARGSUSED */
14064496171girishstatic int
14074496171girishnxge_param_set_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q,
1408fe054a6Toomas Soome    mblk_t *mp, char *value, caddr_t cp)
14094496171girish{
1410a3c5bd6speer	char			*end;
1411a3c5bd6speer	uint32_t		status = 0, cfg_value;
1412a3c5bd6speer	p_nxge_param_t		pa = (p_nxge_param_t)cp;
1413a3c5bd6speer	uint32_t		cfg_it = B_FALSE;
14144496171girish	p_nxge_dma_pt_cfg_t	p_dma_cfgp;
14154496171girish	p_nxge_hw_pt_cfg_t	p_cfgp;
1416a3c5bd6speer	uint32_t		*val_ptr, *old_val_ptr;
1417a3c5bd6speer	nxge_param_map_t	*vmap, *old_map;
1418a3c5bd6speer	p_nxge_class_pt_cfg_t	p_class_cfgp;
1419a3c5bd6speer	uint64_t		cfgd_vlans;
1420a3c5bd6speer	int			i, inc = 0, cfg_position;
1421a3c5bd6speer	nxge_mv_cfg_t		*vlan_tbl;
14224496171girish
14234496171girish	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp "));
14244496171girish
14254496171girish	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
14264496171girish	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
14274496171girish	p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
14284496171girish	vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0];
14294496171girish
14304496171girish	cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX);
1431a3c5bd6speer
1432a3c5bd6speer	/* now do decoding */
14334496171girish	cfgd_vlans = ((pa->type &  NXGE_PARAM_ARRAY_CNT_MASK) >>
14344045d94sowmini	    NXGE_PARAM_ARRAY_CNT_SHIFT);
14354496171girish
14364496171girish	if (cfgd_vlans == NXGE_PARAM_ARRAY_INIT_SIZE) {
14374496171girish		/*
14384496171girish		 * for now, we process only upto max
14394496171girish		 * NXGE_PARAM_ARRAY_INIT_SIZE parameters
14404496171girish		 * In the future, we may want to expand
14414496171girish		 * the storage array and continue
14424496171girish		 */
14434496171girish		return (EINVAL);
14444496171girish	}
1445a3c5bd6speer
14464496171girish	vmap = (nxge_param_map_t *)&cfg_value;
14474496171girish	if ((vmap->param_id) &&
14484045d94sowmini	    (vmap->param_id < NXGE_MAX_VLANS) &&
14494045d94sowmini	    (vmap->map_to < p_cfgp->max_rdc_grpids)) {
14504496171girish		NXGE_DEBUG_MSG((nxgep, NDD_CTL,
14514045d94sowmini		    "nxge_param_set_vlan_rdcgrp mapping"
14524045d94sowmini		    " id %d grp %d",
14534045d94sowmini		    vmap->param_id, vmap->map_to));
1454adfcba5joycey#if defined(__i386)
1455adfcba5joycey		val_ptr = (uint32_t *)(uint32_t)pa->value;
1456adfcba5joycey#else
14574496171girish		val_ptr = (uint32_t *)pa->value;
1458adfcba5joycey#endif
1459adfcba5joycey#if defined(__i386)
1460adfcba5joycey		old_val_ptr = (uint32_t *)(uint32_t)pa->old_value;
1461adfcba5joycey#else
14624496171girish		old_val_ptr = (uint32_t *)pa->old_value;
1463adfcba5joycey#endif
14644496171girish
14654496171girish		/* search to see if this vlan id is already configured */
14664496171girish		for (i = 0; i < cfgd_vlans; i++) {
14674496171girish			old_map = (nxge_param_map_t *)&val_ptr[i];
14684496171girish			if ((old_map->param_id == 0) ||
14694045d94sowmini			    (vmap->param_id == old_map->param_id) ||
14704045d94sowmini			    (vlan_tbl[vmap->param_id].flag)) {
14714496171girish				cfg_position = i;
14724496171girish				break;
14734496171girish			}
14744496171girish		}
14754496171girish
14764496171girish		if (cfgd_vlans == 0) {
14774496171girish			cfg_position = 0;
14784496171girish			inc++;
14794496171girish		}
14804496171girish
14814496171girish		if (i == cfgd_vlans) {
14824496171girish			cfg_position = i;
14834496171girish			inc++;
14844496171girish		}
14854496171girish
14864496171girish		NXGE_DEBUG_MSG((nxgep, NDD2_CTL,
14874045d94sowmini		    "set_vlan_rdcgrp mapping"
14884045d94sowmini		    " i %d cfgd_vlans %llx position %d ",
14894045d94sowmini		    i, cfgd_vlans, cfg_position));
14904496171girish		if (val_ptr[cfg_position] != cfg_value) {
14914496171girish			old_val_ptr[cfg_position] = val_ptr[cfg_position];
14924496171girish			val_ptr[cfg_position] = cfg_value;
14934496171girish			vlan_tbl[vmap->param_id].mpr_npr = vmap->pref;
14944496171girish			vlan_tbl[vmap->param_id].flag = 1;
14954496171girish			vlan_tbl[vmap->param_id].rdctbl =
1496678453aspeer			    vmap->map_to + p_cfgp->def_mac_rxdma_grpid;
14974496171girish			cfg_it = B_TRUE;
14984496171girish			if (inc) {
14994496171girish				cfgd_vlans++;
15004496171girish				pa->type &= ~NXGE_PARAM_ARRAY_CNT_MASK;
15014496171girish				pa->type |= (cfgd_vlans <<
15024045d94sowmini				    NXGE_PARAM_ARRAY_CNT_SHIFT);
15034496171girish
15044496171girish			}
15054496171girish			NXGE_DEBUG_MSG((nxgep, NDD2_CTL,
15064045d94sowmini			    "after: param_set_vlan_rdcgrp "
15074045d94sowmini			    " cfg_vlans %llx position %d \n",
15084045d94sowmini			    cfgd_vlans, cfg_position));
15094496171girish		}
15104496171girish	} else {
15114496171girish		return (EINVAL);
15124496171girish	}
15134496171girish
15144496171girish	if (cfg_it == B_TRUE) {
15154496171girish		status = nxge_fflp_config_vlan_table(nxgep,
15164045d94sowmini		    (uint16_t)vmap->param_id);
15174496171girish		if (status != NXGE_OK)
15184496171girish			return (EINVAL);
15194496171girish	}
15204496171girish
15214496171girish	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_vlan_rdcgrp"));
15224496171girish	return (0);
15234496171girish}
15244496171girish
15254496171girish/* ARGSUSED */
15264496171girishstatic int
15274496171girishnxge_param_get_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q,
1528fe054a6Toomas Soome    mblk_t *mp, caddr_t cp)
15294496171girish{
15304496171girish
1531a3c5bd6speer	uint_t 			print_len, buf_len;
1532a3c5bd6speer	p_mblk_t		np;
1533a3c5bd6speer	int			i;
1534a3c5bd6speer	uint32_t		*val_ptr;
1535a3c5bd6speer	nxge_param_map_t	*vmap;
1536a3c5bd6speer	p_nxge_param_t		pa = (p_nxge_param_t)cp;
15374496171girish	p_nxge_class_pt_cfg_t 	p_class_cfgp;
15384496171girish	p_nxge_dma_pt_cfg_t	p_dma_cfgp;
15394496171girish	p_nxge_hw_pt_cfg_t	p_cfgp;
1540a3c5bd6speer	uint64_t		cfgd_vlans = 0;
1541a3c5bd6speer	nxge_mv_cfg_t		*vlan_tbl;
1542a3c5bd6speer	int			buff_alloc_size =
15434045d94sowmini	    NXGE_NDD_INFODUMP_BUFF_SIZE * 32;
15444496171girish
15454496171girish	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp "));
1546a3c5bd6speer	(void) mi_mpprintf(mp, "VLAN RDC Mapping Information for Port\t %d \n",
15474045d94sowmini	    nxgep->function_num);
15484496171girish
15494496171girish	if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) {
15504496171girish		(void) mi_mpprintf(mp, "%s\n", "out of buffer");
15514496171girish		return (0);
15524496171girish	}
1553a3c5bd6speer
15544496171girish	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
15554496171girish	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
15564496171girish
15574496171girish	buf_len = buff_alloc_size;
15584496171girish	mp->b_cont = np;
15594496171girish	cfgd_vlans = (pa->type &  NXGE_PARAM_ARRAY_CNT_MASK) >>
15604045d94sowmini	    NXGE_PARAM_ARRAY_CNT_SHIFT;
15614496171girish
15624496171girish	i = (int)cfgd_vlans;
15634496171girish	p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
15644496171girish	vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0];
15654496171girish	print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len,
15664045d94sowmini	    "Configured VLANs %d\n"
15674045d94sowmini	    "VLAN ID\t RDC GRP (Actual/Port)\t"
15684045d94sowmini	    " Prefernce\n", i);
15694496171girish	((mblk_t *)np)->b_wptr += print_len;
15704496171girish	buf_len -= print_len;
1571adfcba5joycey#if defined(__i386)
1572adfcba5joycey	val_ptr = (uint32_t *)(uint32_t)pa->value;
1573adfcba5joycey#else
15744496171girish	val_ptr = (uint32_t *)pa->value;
1575adfcba5joycey#endif
15764496171girish
15774496171girish	for (i = 0; i < cfgd_vlans; i++) {
15784496171girish		vmap = (nxge_param_map_t *)&val_ptr[i];
15794496171girish		if (p_class_cfgp->vlan_tbl[vmap->param_id].flag) {
15804496171girish			print_len = snprintf((char *)((mblk_t *)np)->b_wptr,
15814045d94sowmini			    buf_len,
15824045d94sowmini			    "  %d\t\t %d/%d\t\t %d\n",
15834045d94sowmini			    vmap->param_id,
15844045d94sowmini			    vlan_tbl[vmap->param_id].rdctbl,
15854045d94sowmini			    vlan_tbl[vmap->param_id].rdctbl -
15864045d94sowmini			    p_cfgp->def_mac_rxdma_grpid,
15874045d94sowmini			    vlan_tbl[vmap->param_id].mpr_npr);
15884496171girish			((mblk_t *)np)->b_wptr += print_len;
15894496171girish			buf_len -= print_len;
15904496171girish		}
15914496171girish	}
15924496171girish
15934496171girish	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_vlan_rdcgrp"));
15944496171girish	return (0);
15954496171girish}
15964496171girish
15974496171girish/* ARGSUSED */
15984496171girishstatic int
15994496171girishnxge_param_get_mac_rdcgrp(p_nxge_t nxgep, queue_t *q,
1600fe054a6Toomas Soome    mblk_t *mp, caddr_t cp)
16014496171girish{
1602a3c5bd6speer	uint_t			print_len, buf_len;
1603a3c5bd6speer	p_mblk_t		np;
1604a3c5bd6speer	int			i;
16054496171girish	p_nxge_class_pt_cfg_t 	p_class_cfgp;
16064496171girish	p_nxge_dma_pt_cfg_t	p_dma_cfgp;
16074496171girish	p_nxge_hw_pt_cfg_t	p_cfgp;
1608a3c5bd6speer	nxge_mv_cfg_t		*mac_host_info;
16094496171girish
16104496171girish	int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE * 32;
16114496171girish	NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac_rdcgrp "));
16124496171girish	(void) mi_mpprintf(mp,
16134045d94sowmini	    "MAC ADDR RDC Mapping Information for Port\t %d\n",
16144045d94sowmini	    nxgep->function_num);
16154496171girish
16164496171girish	if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) {
16174496171girish		(void) mi_mpprintf(mp, "%s\n", "out of buffer");
16184496171girish		return (0);
16194496171girish	}
16204496171girish
16214496171girish	buf_len = buff_alloc_size;
16224496171girish	mp->b_cont = np;
16234496171girish	p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
16244496171girish	p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
16254496171girish	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
16264496171girish	mac_host_info = (nxge_mv_cfg_t	*)&p_class_cfgp->mac_host_info[0];
16274496171girish	print_len = snprintf((char *)np->b_wptr, buf_len,
16284045d94sowmini	    "MAC ID\t RDC GRP (Actual/Port)\t"
16294045d94sowmini	    " Prefernce\n");
16304496171girish	((mblk_t *)np)->b_wptr += print_len;
16314496171girish	buf_len -= print_len;
16324496171girish	for (i = 0; i < p_cfgp->max_macs; i++) {
16334496171girish		if (mac_host_info[i].flag) {
16344496171girish			print_len = snprintf((char *)((mblk_t *)np)->b_wptr,
1635