144961713Sgirish /* 244961713Sgirish * CDDL HEADER START 344961713Sgirish * 444961713Sgirish * The contents of this file are subject to the terms of the 544961713Sgirish * Common Development and Distribution License (the "License"). 644961713Sgirish * You may not use this file except in compliance with the License. 744961713Sgirish * 844961713Sgirish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 944961713Sgirish * or http://www.opensolaris.org/os/licensing. 1044961713Sgirish * See the License for the specific language governing permissions 1144961713Sgirish * and limitations under the License. 1244961713Sgirish * 1344961713Sgirish * When distributing Covered Code, include this CDDL HEADER in each 1444961713Sgirish * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1544961713Sgirish * If applicable, add the following below this CDDL HEADER, with the 1644961713Sgirish * fields enclosed by brackets "[]" replaced with your own identifying 1744961713Sgirish * information: Portions Copyright [yyyy] [name of copyright owner] 1844961713Sgirish * 1944961713Sgirish * CDDL HEADER END 2044961713Sgirish */ 2144961713Sgirish /* 229d587972SSantwona Behera * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved. 23238d8f47SDale Ghent * Copyright 2016 OmniTI Computer Consulting, Inc. All rights reserved. 2444961713Sgirish */ 2544961713Sgirish 2644961713Sgirish /* 2744961713Sgirish * SunOs MT STREAMS NIU/Neptune 10Gb Ethernet Device Driver. 2844961713Sgirish */ 2944961713Sgirish #include <sys/nxge/nxge_impl.h> 30678453a8Sspeer #include <sys/nxge/nxge_hio.h> 31678453a8Sspeer #include <sys/nxge/nxge_rxdma.h> 3214ea4bb7Ssd #include <sys/pcie.h> 3344961713Sgirish 34*86ef0a63SRichard Lowe uint32_t nxge_use_partition = 0; /* debug partition flag */ 35*86ef0a63SRichard Lowe uint32_t nxge_dma_obp_props_only = 1; /* use obp published props */ 36*86ef0a63SRichard Lowe uint32_t nxge_use_rdc_intr = 1; /* debug to assign rdc intr */ 3744961713Sgirish /* 38ec090658Sml * PSARC/2007/453 MSI-X interrupt limit override 3944961713Sgirish */ 40ec090658Sml uint32_t nxge_msi_enable = 2; 4144961713Sgirish 426f157acbSml /* 436f157acbSml * Software workaround for a Neptune (PCI-E) 446f157acbSml * hardware interrupt bug which the hardware 456f157acbSml * may generate spurious interrupts after the 466f157acbSml * device interrupt handler was removed. If this flag 476f157acbSml * is enabled, the driver will reset the 486f157acbSml * hardware when devices are being detached. 496f157acbSml */ 506f157acbSml uint32_t nxge_peu_reset_enable = 0; 516f157acbSml 52b4d05839Sml /* 53b4d05839Sml * Software workaround for the hardware 54b4d05839Sml * checksum bugs that affect packet transmission 55b4d05839Sml * and receive: 56b4d05839Sml * 57b4d05839Sml * Usage of nxge_cksum_offload: 58b4d05839Sml * 59b4d05839Sml * (1) nxge_cksum_offload = 0 (default): 60b4d05839Sml * - transmits packets: 61b4d05839Sml * TCP: uses the hardware checksum feature. 62b4d05839Sml * UDP: driver will compute the software checksum 63b4d05839Sml * based on the partial checksum computed 64b4d05839Sml * by the IP layer. 65b4d05839Sml * - receives packets 66b4d05839Sml * TCP: marks packets checksum flags based on hardware result. 67b4d05839Sml * UDP: will not mark checksum flags. 68b4d05839Sml * 69b4d05839Sml * (2) nxge_cksum_offload = 1: 70b4d05839Sml * - transmit packets: 71b4d05839Sml * TCP/UDP: uses the hardware checksum feature. 72b4d05839Sml * - receives packets 73b4d05839Sml * TCP/UDP: marks packet checksum flags based on hardware result. 74b4d05839Sml * 75b4d05839Sml * (3) nxge_cksum_offload = 2: 76b4d05839Sml * - The driver will not register its checksum capability. 77b4d05839Sml * Checksum for both TCP and UDP will be computed 78b4d05839Sml * by the stack. 79b4d05839Sml * - The software LSO is not allowed in this case. 80b4d05839Sml * 81b4d05839Sml * (4) nxge_cksum_offload > 2: 82b4d05839Sml * - Will be treated as it is set to 2 83b4d05839Sml * (stack will compute the checksum). 84b4d05839Sml * 85b4d05839Sml * (5) If the hardware bug is fixed, this workaround 86b4d05839Sml * needs to be updated accordingly to reflect 87b4d05839Sml * the new hardware revision. 88b4d05839Sml */ 89b4d05839Sml uint32_t nxge_cksum_offload = 0; 90678453a8Sspeer 9144961713Sgirish /* 9244961713Sgirish * Globals: tunable parameters (/etc/system or adb) 9344961713Sgirish * 9444961713Sgirish */ 95*86ef0a63SRichard Lowe uint32_t nxge_rbr_size = NXGE_RBR_RBB_DEFAULT; 96*86ef0a63SRichard Lowe uint32_t nxge_rbr_spare_size = 0; 97*86ef0a63SRichard Lowe uint32_t nxge_rcr_size = NXGE_RCR_DEFAULT; 984df55fdeSJanie Lu uint16_t nxge_rdc_buf_offset = SW_OFFSET_NO_OFFSET; 99*86ef0a63SRichard Lowe uint32_t nxge_tx_ring_size = NXGE_TX_RING_DEFAULT; 100*86ef0a63SRichard Lowe boolean_t nxge_no_msg = B_TRUE; /* control message display */ 101*86ef0a63SRichard Lowe uint32_t nxge_no_link_notify = 0; /* control DL_NOTIFY */ 102*86ef0a63SRichard Lowe uint32_t nxge_bcopy_thresh = TX_BCOPY_MAX; 103*86ef0a63SRichard Lowe uint32_t nxge_dvma_thresh = TX_FASTDVMA_MIN; 104*86ef0a63SRichard Lowe uint32_t nxge_dma_stream_thresh = TX_STREAM_MIN; 10544961713Sgirish uint32_t nxge_jumbo_mtu = TX_JUMBO_MTU; 1061f8914d5Sml nxge_tx_mode_t nxge_tx_scheme = NXGE_USE_SERIAL; 10744961713Sgirish 10830ac2e7bSml /* MAX LSO size */ 10930ac2e7bSml #define NXGE_LSO_MAXLEN 65535 11030ac2e7bSml uint32_t nxge_lso_max = NXGE_LSO_MAXLEN; 11130ac2e7bSml 11244961713Sgirish 11344961713Sgirish /* 11444961713Sgirish * Add tunable to reduce the amount of time spent in the 11544961713Sgirish * ISR doing Rx Processing. 11644961713Sgirish */ 11744961713Sgirish uint32_t nxge_max_rx_pkts = 1024; 11844961713Sgirish 11944961713Sgirish /* 12044961713Sgirish * Tunables to manage the receive buffer blocks. 12144961713Sgirish * 12244961713Sgirish * nxge_rx_threshold_hi: copy all buffers. 12344961713Sgirish * nxge_rx_bcopy_size_type: receive buffer block size type. 12444961713Sgirish * nxge_rx_threshold_lo: copy only up to tunable block size type. 12544961713Sgirish */ 12644961713Sgirish nxge_rxbuf_threshold_t nxge_rx_threshold_hi = NXGE_RX_COPY_6; 12744961713Sgirish nxge_rxbuf_type_t nxge_rx_buf_size_type = RCR_PKTBUFSZ_0; 12844961713Sgirish nxge_rxbuf_threshold_t nxge_rx_threshold_lo = NXGE_RX_COPY_3; 12944961713Sgirish 130d00f30bbSspeer uint32_t nxge_use_kmem_alloc = 1; 131678453a8Sspeer 13244961713Sgirish rtrace_t npi_rtracebuf; 13344961713Sgirish 134d6d3405fSml /* 135d6d3405fSml * The hardware sometimes fails to allow enough time for the link partner 136d6d3405fSml * to send an acknowledgement for packets that the hardware sent to it. The 137d6d3405fSml * hardware resends the packets earlier than it should be in those instances. 138d6d3405fSml * This behavior caused some switches to acknowledge the wrong packets 139d6d3405fSml * and it triggered the fatal error. 140d6d3405fSml * This software workaround is to set the replay timer to a value 141d6d3405fSml * suggested by the hardware team. 142d6d3405fSml * 143d6d3405fSml * PCI config space replay timer register: 144d6d3405fSml * The following replay timeout value is 0xc 145d6d3405fSml * for bit 14:18. 146d6d3405fSml */ 147d6d3405fSml #define PCI_REPLAY_TIMEOUT_CFG_OFFSET 0xb8 148d6d3405fSml #define PCI_REPLAY_TIMEOUT_SHIFT 14 149d6d3405fSml 150d6d3405fSml uint32_t nxge_set_replay_timer = 1; 151d6d3405fSml uint32_t nxge_replay_timeout = 0xc; 152d6d3405fSml 153cf020df9Sml /* 154cf020df9Sml * The transmit serialization sometimes causes 155cf020df9Sml * longer sleep before calling the driver transmit 156cf020df9Sml * function as it sleeps longer than it should. 157cf020df9Sml * The performace group suggests that a time wait tunable 158cf020df9Sml * can be used to set the maximum wait time when needed 159cf020df9Sml * and the default is set to 1 tick. 160cf020df9Sml */ 161cf020df9Sml uint32_t nxge_tx_serial_maxsleep = 1; 162cf020df9Sml 16344961713Sgirish #if defined(sun4v) 16444961713Sgirish /* 16544961713Sgirish * Hypervisor N2/NIU services information. 16644961713Sgirish */ 1674df55fdeSJanie Lu /* 1684df55fdeSJanie Lu * The following is the default API supported: 1694df55fdeSJanie Lu * major 1 and minor 1. 1704df55fdeSJanie Lu * 1714df55fdeSJanie Lu * Please update the MAX_NIU_MAJORS, 1724df55fdeSJanie Lu * MAX_NIU_MINORS, and minor number supported 1734df55fdeSJanie Lu * when the newer Hypervior API interfaces 1744df55fdeSJanie Lu * are added. Also, please update nxge_hsvc_register() 1754df55fdeSJanie Lu * if needed. 1764df55fdeSJanie Lu */ 17744961713Sgirish static hsvc_info_t niu_hsvc = { 17844961713Sgirish HSVC_REV_1, NULL, HSVC_GROUP_NIU, NIU_MAJOR_VER, 17944961713Sgirish NIU_MINOR_VER, "nxge" 18044961713Sgirish }; 181678453a8Sspeer 182678453a8Sspeer static int nxge_hsvc_register(p_nxge_t); 18344961713Sgirish #endif 18444961713Sgirish 18544961713Sgirish /* 18644961713Sgirish * Function Prototypes 18744961713Sgirish */ 18844961713Sgirish static int nxge_attach(dev_info_t *, ddi_attach_cmd_t); 18944961713Sgirish static int nxge_detach(dev_info_t *, ddi_detach_cmd_t); 19044961713Sgirish static void nxge_unattach(p_nxge_t); 19119397407SSherry Moore static int nxge_quiesce(dev_info_t *); 19244961713Sgirish 19344961713Sgirish #if NXGE_PROPERTY 19444961713Sgirish static void nxge_remove_hard_properties(p_nxge_t); 19544961713Sgirish #endif 19644961713Sgirish 197678453a8Sspeer /* 198678453a8Sspeer * These two functions are required by nxge_hio.c 199678453a8Sspeer */ 200da14cebeSEric Cheng extern int nxge_m_mmac_remove(void *arg, int slot); 201651ce697SMichael Speer extern void nxge_grp_cleanup(p_nxge_t nxge); 202678453a8Sspeer 20344961713Sgirish static nxge_status_t nxge_setup_system_dma_pages(p_nxge_t); 20444961713Sgirish 20544961713Sgirish static nxge_status_t nxge_setup_mutexes(p_nxge_t); 20644961713Sgirish static void nxge_destroy_mutexes(p_nxge_t); 20744961713Sgirish 20844961713Sgirish static nxge_status_t nxge_map_regs(p_nxge_t nxgep); 20944961713Sgirish static void nxge_unmap_regs(p_nxge_t nxgep); 21044961713Sgirish #ifdef NXGE_DEBUG 21144961713Sgirish static void nxge_test_map_regs(p_nxge_t nxgep); 21244961713Sgirish #endif 21344961713Sgirish 21444961713Sgirish static nxge_status_t nxge_add_intrs(p_nxge_t nxgep); 21544961713Sgirish static void nxge_remove_intrs(p_nxge_t nxgep); 21644961713Sgirish 21744961713Sgirish static nxge_status_t nxge_add_intrs_adv(p_nxge_t nxgep); 21844961713Sgirish static nxge_status_t nxge_add_intrs_adv_type(p_nxge_t, uint32_t); 21944961713Sgirish static nxge_status_t nxge_add_intrs_adv_type_fix(p_nxge_t, uint32_t); 22044961713Sgirish static void nxge_intrs_enable(p_nxge_t nxgep); 22144961713Sgirish static void nxge_intrs_disable(p_nxge_t nxgep); 22244961713Sgirish 22344961713Sgirish static void nxge_suspend(p_nxge_t); 22444961713Sgirish static nxge_status_t nxge_resume(p_nxge_t); 22544961713Sgirish 22644961713Sgirish static nxge_status_t nxge_setup_dev(p_nxge_t); 22744961713Sgirish static void nxge_destroy_dev(p_nxge_t); 22844961713Sgirish 22944961713Sgirish static nxge_status_t nxge_alloc_mem_pool(p_nxge_t); 23044961713Sgirish static void nxge_free_mem_pool(p_nxge_t); 23144961713Sgirish 232678453a8Sspeer nxge_status_t nxge_alloc_rx_mem_pool(p_nxge_t); 23344961713Sgirish static void nxge_free_rx_mem_pool(p_nxge_t); 23444961713Sgirish 235678453a8Sspeer nxge_status_t nxge_alloc_tx_mem_pool(p_nxge_t); 23644961713Sgirish static void nxge_free_tx_mem_pool(p_nxge_t); 23744961713Sgirish 23844961713Sgirish static nxge_status_t nxge_dma_mem_alloc(p_nxge_t, dma_method_t, 23944961713Sgirish struct ddi_dma_attr *, 24044961713Sgirish size_t, ddi_device_acc_attr_t *, uint_t, 24144961713Sgirish p_nxge_dma_common_t); 24244961713Sgirish 24344961713Sgirish static void nxge_dma_mem_free(p_nxge_dma_common_t); 244678453a8Sspeer static void nxge_dma_free_rx_data_buf(p_nxge_dma_common_t); 24544961713Sgirish 24644961713Sgirish static nxge_status_t nxge_alloc_rx_buf_dma(p_nxge_t, uint16_t, 24744961713Sgirish p_nxge_dma_common_t *, size_t, size_t, uint32_t *); 24844961713Sgirish static void nxge_free_rx_buf_dma(p_nxge_t, p_nxge_dma_common_t, uint32_t); 24944961713Sgirish 25044961713Sgirish static nxge_status_t nxge_alloc_rx_cntl_dma(p_nxge_t, uint16_t, 25144961713Sgirish p_nxge_dma_common_t *, size_t); 25244961713Sgirish static void nxge_free_rx_cntl_dma(p_nxge_t, p_nxge_dma_common_t); 25344961713Sgirish 254678453a8Sspeer extern nxge_status_t nxge_alloc_tx_buf_dma(p_nxge_t, uint16_t, 25544961713Sgirish p_nxge_dma_common_t *, size_t, size_t, uint32_t *); 25644961713Sgirish static void nxge_free_tx_buf_dma(p_nxge_t, p_nxge_dma_common_t, uint32_t); 25744961713Sgirish 258678453a8Sspeer extern nxge_status_t nxge_alloc_tx_cntl_dma(p_nxge_t, uint16_t, 25944961713Sgirish p_nxge_dma_common_t *, 26044961713Sgirish size_t); 26144961713Sgirish static void nxge_free_tx_cntl_dma(p_nxge_t, p_nxge_dma_common_t); 26244961713Sgirish 26344961713Sgirish static int nxge_init_common_dev(p_nxge_t); 26444961713Sgirish static void nxge_uninit_common_dev(p_nxge_t); 2654045d941Ssowmini extern int nxge_param_set_mac(p_nxge_t, queue_t *, mblk_t *, 2664045d941Ssowmini char *, caddr_t); 267e759c33aSMichael Speer #if defined(sun4v) 268e759c33aSMichael Speer extern nxge_status_t nxge_hio_rdc_enable(p_nxge_t nxgep); 269e759c33aSMichael Speer extern nxge_status_t nxge_hio_rdc_intr_arm(p_nxge_t nxge, boolean_t arm); 270e759c33aSMichael Speer #endif 27144961713Sgirish 27244961713Sgirish /* 27344961713Sgirish * The next declarations are for the GLDv3 interface. 27444961713Sgirish */ 27544961713Sgirish static int nxge_m_start(void *); 27644961713Sgirish static void nxge_m_stop(void *); 27744961713Sgirish static int nxge_m_multicst(void *, boolean_t, const uint8_t *); 27844961713Sgirish static int nxge_m_promisc(void *, boolean_t); 27944961713Sgirish static void nxge_m_ioctl(void *, queue_t *, mblk_t *); 28063f531d1SSriharsha Basavapatna nxge_status_t nxge_mac_register(p_nxge_t); 281da14cebeSEric Cheng static int nxge_altmac_set(p_nxge_t nxgep, uint8_t *mac_addr, 282da14cebeSEric Cheng int slot, int rdctbl, boolean_t usetbl); 283da14cebeSEric Cheng void nxge_mmac_kstat_update(p_nxge_t nxgep, int slot, 28458324dfcSspeer boolean_t factory); 285da14cebeSEric Cheng 286da14cebeSEric Cheng static void nxge_m_getfactaddr(void *, uint_t, uint8_t *); 2871bd6825cSml static boolean_t nxge_m_getcapab(void *, mac_capab_t, void *); 2881bd6825cSml static int nxge_m_setprop(void *, const char *, mac_prop_id_t, 2891bd6825cSml uint_t, const void *); 2901bd6825cSml static int nxge_m_getprop(void *, const char *, mac_prop_id_t, 2910dc2366fSVenugopal Iyer uint_t, void *); 2920dc2366fSVenugopal Iyer static void nxge_m_propinfo(void *, const char *, mac_prop_id_t, 2930dc2366fSVenugopal Iyer mac_prop_info_handle_t); 2940dc2366fSVenugopal Iyer static void nxge_priv_propinfo(const char *, mac_prop_info_handle_t); 2951bd6825cSml static int nxge_set_priv_prop(nxge_t *, const char *, uint_t, 2961bd6825cSml const void *); 2970dc2366fSVenugopal Iyer static int nxge_get_priv_prop(nxge_t *, const char *, uint_t, void *); 298da14cebeSEric Cheng static void nxge_fill_ring(void *, mac_ring_type_t, const int, const int, 299da14cebeSEric Cheng mac_ring_info_t *, mac_ring_handle_t); 300da14cebeSEric Cheng static void nxge_group_add_ring(mac_group_driver_t, mac_ring_driver_t, 301da14cebeSEric Cheng mac_ring_type_t); 302da14cebeSEric Cheng static void nxge_group_rem_ring(mac_group_driver_t, mac_ring_driver_t, 303da14cebeSEric Cheng mac_ring_type_t); 3044045d941Ssowmini 3056f157acbSml static void nxge_niu_peu_reset(p_nxge_t nxgep); 306d6d3405fSml static void nxge_set_pci_replay_timeout(nxge_t *); 3074045d941Ssowmini 3080dc2366fSVenugopal Iyer char *nxge_priv_props[] = { 3090dc2366fSVenugopal Iyer "_adv_10gfdx_cap", 3100dc2366fSVenugopal Iyer "_adv_pause_cap", 3110dc2366fSVenugopal Iyer "_function_number", 3120dc2366fSVenugopal Iyer "_fw_version", 3130dc2366fSVenugopal Iyer "_port_mode", 3140dc2366fSVenugopal Iyer "_hot_swap_phy", 3150dc2366fSVenugopal Iyer "_rxdma_intr_time", 3160dc2366fSVenugopal Iyer "_rxdma_intr_pkts", 3170dc2366fSVenugopal Iyer "_class_opt_ipv4_tcp", 3180dc2366fSVenugopal Iyer "_class_opt_ipv4_udp", 3190dc2366fSVenugopal Iyer "_class_opt_ipv4_ah", 3200dc2366fSVenugopal Iyer "_class_opt_ipv4_sctp", 3210dc2366fSVenugopal Iyer "_class_opt_ipv6_tcp", 3220dc2366fSVenugopal Iyer "_class_opt_ipv6_udp", 3230dc2366fSVenugopal Iyer "_class_opt_ipv6_ah", 3240dc2366fSVenugopal Iyer "_class_opt_ipv6_sctp", 3250dc2366fSVenugopal Iyer "_soft_lso_enable", 3260dc2366fSVenugopal Iyer NULL 3274045d941Ssowmini }; 3284045d941Ssowmini 32944961713Sgirish #define NXGE_NEPTUNE_MAGIC 0x4E584745UL 33044961713Sgirish #define MAX_DUMP_SZ 256 33144961713Sgirish 3321bd6825cSml #define NXGE_M_CALLBACK_FLAGS \ 3330dc2366fSVenugopal Iyer (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP | MC_PROPINFO) 33444961713Sgirish 335678453a8Sspeer mac_callbacks_t nxge_m_callbacks = { 33644961713Sgirish NXGE_M_CALLBACK_FLAGS, 33744961713Sgirish nxge_m_stat, 33844961713Sgirish nxge_m_start, 33944961713Sgirish nxge_m_stop, 34044961713Sgirish nxge_m_promisc, 34144961713Sgirish nxge_m_multicst, 342da14cebeSEric Cheng NULL, 343da14cebeSEric Cheng NULL, 3440dc2366fSVenugopal Iyer NULL, 34544961713Sgirish nxge_m_ioctl, 3461bd6825cSml nxge_m_getcapab, 3471bd6825cSml NULL, 3481bd6825cSml NULL, 3491bd6825cSml nxge_m_setprop, 3500dc2366fSVenugopal Iyer nxge_m_getprop, 3510dc2366fSVenugopal Iyer nxge_m_propinfo 35244961713Sgirish }; 35344961713Sgirish 35444961713Sgirish void 35544961713Sgirish nxge_err_inject(p_nxge_t, queue_t *, mblk_t *); 35644961713Sgirish 357ec090658Sml /* PSARC/2007/453 MSI-X interrupt limit override. */ 358ec090658Sml #define NXGE_MSIX_REQUEST_10G 8 359ec090658Sml #define NXGE_MSIX_REQUEST_1G 2 360ec090658Sml static int nxge_create_msi_property(p_nxge_t); 361ef755e7aStc /* 362ef755e7aStc * For applications that care about the 363ef755e7aStc * latency, it was requested by PAE and the 364ef755e7aStc * customers that the driver has tunables that 365ef755e7aStc * allow the user to tune it to a higher number 366ef755e7aStc * interrupts to spread the interrupts among 367ef755e7aStc * multiple channels. The DDI framework limits 368ef755e7aStc * the maximum number of MSI-X resources to allocate 369ef755e7aStc * to 8 (ddi_msix_alloc_limit). If more than 8 370ef755e7aStc * is set, ddi_msix_alloc_limit must be set accordingly. 371ef755e7aStc * The default number of MSI interrupts are set to 372ef755e7aStc * 8 for 10G and 2 for 1G link. 373ef755e7aStc */ 374ef755e7aStc #define NXGE_MSIX_MAX_ALLOWED 32 375ef755e7aStc uint32_t nxge_msix_10g_intrs = NXGE_MSIX_REQUEST_10G; 376ef755e7aStc uint32_t nxge_msix_1g_intrs = NXGE_MSIX_REQUEST_1G; 377ec090658Sml 37844961713Sgirish /* 37944961713Sgirish * These global variables control the message 38044961713Sgirish * output. 38144961713Sgirish */ 38244961713Sgirish out_dbgmsg_t nxge_dbgmsg_out = DBG_CONSOLE | STR_LOG; 383678453a8Sspeer uint64_t nxge_debug_level; 38444961713Sgirish 38544961713Sgirish /* 38644961713Sgirish * This list contains the instance structures for the Neptune 38744961713Sgirish * devices present in the system. The lock exists to guarantee 38844961713Sgirish * mutually exclusive access to the list. 38944961713Sgirish */ 390*86ef0a63SRichard Lowe void *nxge_list = NULL; 39144961713Sgirish void *nxge_hw_list = NULL; 392*86ef0a63SRichard Lowe nxge_os_mutex_t nxge_common_lock; 393*86ef0a63SRichard Lowe nxge_os_mutex_t nxgedebuglock; 39444961713Sgirish 395*86ef0a63SRichard Lowe extern uint64_t npi_debug_level; 39644961713Sgirish 39744961713Sgirish extern nxge_status_t nxge_ldgv_init(p_nxge_t, int *, int *); 39844961713Sgirish extern nxge_status_t nxge_ldgv_init_n2(p_nxge_t, int *, int *); 39944961713Sgirish extern nxge_status_t nxge_ldgv_uninit(p_nxge_t); 40044961713Sgirish extern nxge_status_t nxge_intr_ldgv_init(p_nxge_t); 40144961713Sgirish extern void nxge_fm_init(p_nxge_t, 40244961713Sgirish ddi_device_acc_attr_t *, 40344961713Sgirish ddi_dma_attr_t *); 40444961713Sgirish extern void nxge_fm_fini(p_nxge_t); 40558324dfcSspeer extern npi_status_t npi_mac_altaddr_disable(npi_handle_t, uint8_t, uint8_t); 40644961713Sgirish 40744961713Sgirish /* 40844961713Sgirish * Count used to maintain the number of buffers being used 40944961713Sgirish * by Neptune instances and loaned up to the upper layers. 41044961713Sgirish */ 41144961713Sgirish uint32_t nxge_mblks_pending = 0; 41244961713Sgirish 41344961713Sgirish /* 41444961713Sgirish * Device register access attributes for PIO. 41544961713Sgirish */ 41644961713Sgirish static ddi_device_acc_attr_t nxge_dev_reg_acc_attr = { 417837c1ac4SStephen Hanson DDI_DEVICE_ATTR_V1, 41844961713Sgirish DDI_STRUCTURE_LE_ACC, 41944961713Sgirish DDI_STRICTORDER_ACC, 420837c1ac4SStephen Hanson DDI_DEFAULT_ACC 42144961713Sgirish }; 42244961713Sgirish 42344961713Sgirish /* 42444961713Sgirish * Device descriptor access attributes for DMA. 42544961713Sgirish */ 42644961713Sgirish static ddi_device_acc_attr_t nxge_dev_desc_dma_acc_attr = { 42744961713Sgirish DDI_DEVICE_ATTR_V0, 42844961713Sgirish DDI_STRUCTURE_LE_ACC, 42944961713Sgirish DDI_STRICTORDER_ACC 43044961713Sgirish }; 43144961713Sgirish 43244961713Sgirish /* 43344961713Sgirish * Device buffer access attributes for DMA. 43444961713Sgirish */ 43544961713Sgirish static ddi_device_acc_attr_t nxge_dev_buf_dma_acc_attr = { 43644961713Sgirish DDI_DEVICE_ATTR_V0, 43744961713Sgirish DDI_STRUCTURE_BE_ACC, 43844961713Sgirish DDI_STRICTORDER_ACC 43944961713Sgirish }; 44044961713Sgirish 44144961713Sgirish ddi_dma_attr_t nxge_desc_dma_attr = { 44244961713Sgirish DMA_ATTR_V0, /* version number. */ 44344961713Sgirish 0, /* low address */ 44444961713Sgirish 0xffffffffffffffff, /* high address */ 44544961713Sgirish 0xffffffffffffffff, /* address counter max */ 44644961713Sgirish #ifndef NIU_PA_WORKAROUND 44744961713Sgirish 0x100000, /* alignment */ 44844961713Sgirish #else 44944961713Sgirish 0x2000, 45044961713Sgirish #endif 45144961713Sgirish 0xfc00fc, /* dlim_burstsizes */ 45244961713Sgirish 0x1, /* minimum transfer size */ 45344961713Sgirish 0xffffffffffffffff, /* maximum transfer size */ 45444961713Sgirish 0xffffffffffffffff, /* maximum segment size */ 45544961713Sgirish 1, /* scatter/gather list length */ 45644961713Sgirish (unsigned int) 1, /* granularity */ 45744961713Sgirish 0 /* attribute flags */ 45844961713Sgirish }; 45944961713Sgirish 46044961713Sgirish ddi_dma_attr_t nxge_tx_dma_attr = { 46144961713Sgirish DMA_ATTR_V0, /* version number. */ 46244961713Sgirish 0, /* low address */ 46344961713Sgirish 0xffffffffffffffff, /* high address */ 46444961713Sgirish 0xffffffffffffffff, /* address counter max */ 46544961713Sgirish #if defined(_BIG_ENDIAN) 46644961713Sgirish 0x2000, /* alignment */ 46744961713Sgirish #else 46844961713Sgirish 0x1000, /* alignment */ 46944961713Sgirish #endif 47044961713Sgirish 0xfc00fc, /* dlim_burstsizes */ 47144961713Sgirish 0x1, /* minimum transfer size */ 47244961713Sgirish 0xffffffffffffffff, /* maximum transfer size */ 47344961713Sgirish 0xffffffffffffffff, /* maximum segment size */ 47444961713Sgirish 5, /* scatter/gather list length */ 47544961713Sgirish (unsigned int) 1, /* granularity */ 47644961713Sgirish 0 /* attribute flags */ 47744961713Sgirish }; 47844961713Sgirish 47944961713Sgirish ddi_dma_attr_t nxge_rx_dma_attr = { 48044961713Sgirish DMA_ATTR_V0, /* version number. */ 48144961713Sgirish 0, /* low address */ 48244961713Sgirish 0xffffffffffffffff, /* high address */ 48344961713Sgirish 0xffffffffffffffff, /* address counter max */ 48444961713Sgirish 0x2000, /* alignment */ 48544961713Sgirish 0xfc00fc, /* dlim_burstsizes */ 48644961713Sgirish 0x1, /* minimum transfer size */ 48744961713Sgirish 0xffffffffffffffff, /* maximum transfer size */ 48844961713Sgirish 0xffffffffffffffff, /* maximum segment size */ 48944961713Sgirish 1, /* scatter/gather list length */ 49044961713Sgirish (unsigned int) 1, /* granularity */ 4910e2bd521Ssbehera DDI_DMA_RELAXED_ORDERING /* attribute flags */ 49244961713Sgirish }; 49344961713Sgirish 49444961713Sgirish ddi_dma_lim_t nxge_dma_limits = { 49544961713Sgirish (uint_t)0, /* dlim_addr_lo */ 49644961713Sgirish (uint_t)0xffffffff, /* dlim_addr_hi */ 49744961713Sgirish (uint_t)0xffffffff, /* dlim_cntr_max */ 49844961713Sgirish (uint_t)0xfc00fc, /* dlim_burstsizes for 32 and 64 bit xfers */ 49944961713Sgirish 0x1, /* dlim_minxfer */ 50044961713Sgirish 1024 /* dlim_speed */ 50144961713Sgirish }; 50244961713Sgirish 50344961713Sgirish dma_method_t nxge_force_dma = DVMA; 50444961713Sgirish 50544961713Sgirish /* 50644961713Sgirish * dma chunk sizes. 50744961713Sgirish * 50844961713Sgirish * Try to allocate the largest possible size 50944961713Sgirish * so that fewer number of dma chunks would be managed 51044961713Sgirish */ 51144961713Sgirish #ifdef NIU_PA_WORKAROUND 51244961713Sgirish size_t alloc_sizes [] = {0x2000}; 51344961713Sgirish #else 51444961713Sgirish size_t alloc_sizes [] = {0x1000, 0x2000, 0x4000, 0x8000, 51544961713Sgirish 0x10000, 0x20000, 0x40000, 0x80000, 51630ac2e7bSml 0x100000, 0x200000, 0x400000, 0x800000, 51730ac2e7bSml 0x1000000, 0x2000000, 0x4000000}; 51844961713Sgirish #endif 51944961713Sgirish 52044961713Sgirish /* 52144961713Sgirish * Translate "dev_t" to a pointer to the associated "dev_info_t". 52244961713Sgirish */ 52344961713Sgirish 524678453a8Sspeer extern void nxge_get_environs(nxge_t *); 525678453a8Sspeer 52644961713Sgirish static int 52744961713Sgirish nxge_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 52844961713Sgirish { 52944961713Sgirish p_nxge_t nxgep = NULL; 53044961713Sgirish int instance; 53144961713Sgirish int status = DDI_SUCCESS; 53244961713Sgirish uint8_t portn; 53358324dfcSspeer nxge_mmac_t *mmac_info; 53444961713Sgirish 53544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_attach")); 53644961713Sgirish 53744961713Sgirish /* 53844961713Sgirish * Get the device instance since we'll need to setup 53944961713Sgirish * or retrieve a soft state for this instance. 54044961713Sgirish */ 54144961713Sgirish instance = ddi_get_instance(dip); 54244961713Sgirish 54344961713Sgirish switch (cmd) { 54444961713Sgirish case DDI_ATTACH: 54544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_ATTACH")); 54644961713Sgirish break; 54744961713Sgirish 54844961713Sgirish case DDI_RESUME: 54944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_RESUME")); 55044961713Sgirish nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance); 55144961713Sgirish if (nxgep == NULL) { 55244961713Sgirish status = DDI_FAILURE; 55344961713Sgirish break; 55444961713Sgirish } 55544961713Sgirish if (nxgep->dip != dip) { 55644961713Sgirish status = DDI_FAILURE; 55744961713Sgirish break; 55844961713Sgirish } 55944961713Sgirish if (nxgep->suspended == DDI_PM_SUSPEND) { 56044961713Sgirish status = ddi_dev_is_needed(nxgep->dip, 0, 1); 56144961713Sgirish } else { 56256d930aeSspeer status = nxge_resume(nxgep); 56344961713Sgirish } 56444961713Sgirish goto nxge_attach_exit; 56544961713Sgirish 56644961713Sgirish case DDI_PM_RESUME: 56744961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_PM_RESUME")); 56844961713Sgirish nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance); 56944961713Sgirish if (nxgep == NULL) { 57044961713Sgirish status = DDI_FAILURE; 57144961713Sgirish break; 57244961713Sgirish } 57344961713Sgirish if (nxgep->dip != dip) { 57444961713Sgirish status = DDI_FAILURE; 57544961713Sgirish break; 57644961713Sgirish } 57756d930aeSspeer status = nxge_resume(nxgep); 57844961713Sgirish goto nxge_attach_exit; 57944961713Sgirish 58044961713Sgirish default: 58144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing unknown")); 58244961713Sgirish status = DDI_FAILURE; 58344961713Sgirish goto nxge_attach_exit; 58444961713Sgirish } 58544961713Sgirish 58644961713Sgirish 58744961713Sgirish if (ddi_soft_state_zalloc(nxge_list, instance) == DDI_FAILURE) { 58844961713Sgirish status = DDI_FAILURE; 58944961713Sgirish goto nxge_attach_exit; 59044961713Sgirish } 59144961713Sgirish 59244961713Sgirish nxgep = ddi_get_soft_state(nxge_list, instance); 59344961713Sgirish if (nxgep == NULL) { 5942e59129aSraghus status = NXGE_ERROR; 5952e59129aSraghus goto nxge_attach_fail2; 59644961713Sgirish } 59744961713Sgirish 59898ecde52Stm nxgep->nxge_magic = NXGE_MAGIC; 59998ecde52Stm 60044961713Sgirish nxgep->drv_state = 0; 60144961713Sgirish nxgep->dip = dip; 60244961713Sgirish nxgep->instance = instance; 60344961713Sgirish nxgep->p_dip = ddi_get_parent(dip); 60444961713Sgirish nxgep->nxge_debug_level = nxge_debug_level; 60544961713Sgirish npi_debug_level = nxge_debug_level; 60644961713Sgirish 607678453a8Sspeer /* Are we a guest running in a Hybrid I/O environment? */ 608678453a8Sspeer nxge_get_environs(nxgep); 60944961713Sgirish 61044961713Sgirish status = nxge_map_regs(nxgep); 611678453a8Sspeer 61244961713Sgirish if (status != NXGE_OK) { 61344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_map_regs failed")); 6142e59129aSraghus goto nxge_attach_fail3; 61544961713Sgirish } 61644961713Sgirish 617837c1ac4SStephen Hanson nxge_fm_init(nxgep, &nxge_dev_reg_acc_attr, &nxge_rx_dma_attr); 618678453a8Sspeer 619678453a8Sspeer /* Create & initialize the per-Neptune data structure */ 620678453a8Sspeer /* (even if we're a guest). */ 62144961713Sgirish status = nxge_init_common_dev(nxgep); 62244961713Sgirish if (status != NXGE_OK) { 62344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6244045d941Ssowmini "nxge_init_common_dev failed")); 6252e59129aSraghus goto nxge_attach_fail4; 62644961713Sgirish } 62744961713Sgirish 628d6d3405fSml /* 629d6d3405fSml * Software workaround: set the replay timer. 630d6d3405fSml */ 631d6d3405fSml if (nxgep->niu_type != N2_NIU) { 632d6d3405fSml nxge_set_pci_replay_timeout(nxgep); 633d6d3405fSml } 634d6d3405fSml 635678453a8Sspeer #if defined(sun4v) 636678453a8Sspeer /* This is required by nxge_hio_init(), which follows. */ 637678453a8Sspeer if ((status = nxge_hsvc_register(nxgep)) != DDI_SUCCESS) 6389d5b8bc5SMichael Speer goto nxge_attach_fail4; 639678453a8Sspeer #endif 640678453a8Sspeer 641678453a8Sspeer if ((status = nxge_hio_init(nxgep)) != NXGE_OK) { 642678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6434045d941Ssowmini "nxge_hio_init failed")); 644678453a8Sspeer goto nxge_attach_fail4; 645678453a8Sspeer } 646678453a8Sspeer 64759ac0c16Sdavemq if (nxgep->niu_type == NEPTUNE_2_10GF) { 64859ac0c16Sdavemq if (nxgep->function_num > 1) { 6494202ea4bSsbehera NXGE_DEBUG_MSG((nxgep, DDI_CTL, "Unsupported" 65059ac0c16Sdavemq " function %d. Only functions 0 and 1 are " 65159ac0c16Sdavemq "supported for this card.", nxgep->function_num)); 65259ac0c16Sdavemq status = NXGE_ERROR; 6532e59129aSraghus goto nxge_attach_fail4; 65459ac0c16Sdavemq } 65559ac0c16Sdavemq } 65659ac0c16Sdavemq 657678453a8Sspeer if (isLDOMguest(nxgep)) { 658678453a8Sspeer /* 659678453a8Sspeer * Use the function number here. 660678453a8Sspeer */ 661678453a8Sspeer nxgep->mac.portnum = nxgep->function_num; 662678453a8Sspeer nxgep->mac.porttype = PORT_TYPE_LOGICAL; 663678453a8Sspeer 664678453a8Sspeer /* XXX We'll set the MAC address counts to 1 for now. */ 665678453a8Sspeer mmac_info = &nxgep->nxge_mmac_info; 666678453a8Sspeer mmac_info->num_mmac = 1; 667678453a8Sspeer mmac_info->naddrfree = 1; 66858324dfcSspeer } else { 669678453a8Sspeer portn = NXGE_GET_PORT_NUM(nxgep->function_num); 670678453a8Sspeer nxgep->mac.portnum = portn; 671678453a8Sspeer if ((portn == 0) || (portn == 1)) 672678453a8Sspeer nxgep->mac.porttype = PORT_TYPE_XMAC; 673678453a8Sspeer else 674678453a8Sspeer nxgep->mac.porttype = PORT_TYPE_BMAC; 675678453a8Sspeer /* 676678453a8Sspeer * Neptune has 4 ports, the first 2 ports use XMAC (10G MAC) 677678453a8Sspeer * internally, the rest 2 ports use BMAC (1G "Big" MAC). 678678453a8Sspeer * The two types of MACs have different characterizations. 679678453a8Sspeer */ 680678453a8Sspeer mmac_info = &nxgep->nxge_mmac_info; 681678453a8Sspeer if (nxgep->function_num < 2) { 682678453a8Sspeer mmac_info->num_mmac = XMAC_MAX_ALT_ADDR_ENTRY; 683678453a8Sspeer mmac_info->naddrfree = XMAC_MAX_ALT_ADDR_ENTRY; 684678453a8Sspeer } else { 685678453a8Sspeer mmac_info->num_mmac = BMAC_MAX_ALT_ADDR_ENTRY; 686678453a8Sspeer mmac_info->naddrfree = BMAC_MAX_ALT_ADDR_ENTRY; 687678453a8Sspeer } 68858324dfcSspeer } 68944961713Sgirish /* 69044961713Sgirish * Setup the Ndd parameters for the this instance. 69144961713Sgirish */ 69244961713Sgirish nxge_init_param(nxgep); 69344961713Sgirish 69444961713Sgirish /* 69544961713Sgirish * Setup Register Tracing Buffer. 69644961713Sgirish */ 69744961713Sgirish npi_rtrace_buf_init((rtrace_t *)&npi_rtracebuf); 69844961713Sgirish 69944961713Sgirish /* init stats ptr */ 70044961713Sgirish nxge_init_statsp(nxgep); 70156d930aeSspeer 7022e59129aSraghus /* 703678453a8Sspeer * Copy the vpd info from eeprom to a local data 704678453a8Sspeer * structure, and then check its validity. 7052e59129aSraghus */ 706678453a8Sspeer if (!isLDOMguest(nxgep)) { 707678453a8Sspeer int *regp; 708678453a8Sspeer uint_t reglen; 709678453a8Sspeer int rv; 71056d930aeSspeer 711678453a8Sspeer nxge_vpd_info_get(nxgep); 71244961713Sgirish 713678453a8Sspeer /* Find the NIU config handle. */ 714678453a8Sspeer rv = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, 715678453a8Sspeer ddi_get_parent(nxgep->dip), DDI_PROP_DONTPASS, 716678453a8Sspeer "reg", ®p, ®len); 717678453a8Sspeer 718678453a8Sspeer if (rv != DDI_PROP_SUCCESS) { 719678453a8Sspeer goto nxge_attach_fail5; 720678453a8Sspeer } 721678453a8Sspeer /* 722678453a8Sspeer * The address_hi, that is the first int, in the reg 723678453a8Sspeer * property consists of config handle, but need to remove 724678453a8Sspeer * the bits 28-31 which are OBP specific info. 725678453a8Sspeer */ 726678453a8Sspeer nxgep->niu_cfg_hdl = (*regp) & 0xFFFFFFF; 727678453a8Sspeer ddi_prop_free(regp); 72844961713Sgirish } 72944961713Sgirish 73048056c53SMichael Speer /* 73148056c53SMichael Speer * Set the defaults for the MTU size. 73248056c53SMichael Speer */ 73348056c53SMichael Speer nxge_hw_id_init(nxgep); 73448056c53SMichael Speer 735678453a8Sspeer if (isLDOMguest(nxgep)) { 736678453a8Sspeer uchar_t *prop_val; 737678453a8Sspeer uint_t prop_len; 7387b1f684aSSriharsha Basavapatna uint32_t max_frame_size; 73944961713Sgirish 740678453a8Sspeer extern void nxge_get_logical_props(p_nxge_t); 741678453a8Sspeer 742678453a8Sspeer nxgep->statsp->mac_stats.xcvr_inuse = LOGICAL_XCVR; 743678453a8Sspeer nxgep->mac.portmode = PORT_LOGICAL; 744678453a8Sspeer (void) ddi_prop_update_string(DDI_DEV_T_NONE, nxgep->dip, 745678453a8Sspeer "phy-type", "virtual transceiver"); 746678453a8Sspeer 747678453a8Sspeer nxgep->nports = 1; 748678453a8Sspeer nxgep->board_ver = 0; /* XXX What? */ 749678453a8Sspeer 750678453a8Sspeer /* 751678453a8Sspeer * local-mac-address property gives us info on which 752678453a8Sspeer * specific MAC address the Hybrid resource is associated 753678453a8Sspeer * with. 754678453a8Sspeer */ 755678453a8Sspeer if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0, 756678453a8Sspeer "local-mac-address", &prop_val, 757678453a8Sspeer &prop_len) != DDI_PROP_SUCCESS) { 758678453a8Sspeer goto nxge_attach_fail5; 759678453a8Sspeer } 760*86ef0a63SRichard Lowe if (prop_len != ETHERADDRL) { 761678453a8Sspeer ddi_prop_free(prop_val); 762678453a8Sspeer goto nxge_attach_fail5; 763678453a8Sspeer } 764678453a8Sspeer ether_copy(prop_val, nxgep->hio_mac_addr); 765678453a8Sspeer ddi_prop_free(prop_val); 766678453a8Sspeer nxge_get_logical_props(nxgep); 767678453a8Sspeer 7687b1f684aSSriharsha Basavapatna /* 7697b1f684aSSriharsha Basavapatna * Enable Jumbo property based on the "max-frame-size" 7707b1f684aSSriharsha Basavapatna * property value. 7717b1f684aSSriharsha Basavapatna */ 7727b1f684aSSriharsha Basavapatna max_frame_size = ddi_prop_get_int(DDI_DEV_T_ANY, 7737b1f684aSSriharsha Basavapatna nxgep->dip, DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, 7747b1f684aSSriharsha Basavapatna "max-frame-size", NXGE_MTU_DEFAULT_MAX); 7757b1f684aSSriharsha Basavapatna if ((max_frame_size > NXGE_MTU_DEFAULT_MAX) && 7767b1f684aSSriharsha Basavapatna (max_frame_size <= TX_JUMBO_MTU)) { 7777b1f684aSSriharsha Basavapatna nxgep->mac.is_jumbo = B_TRUE; 7787b1f684aSSriharsha Basavapatna nxgep->mac.maxframesize = (uint16_t)max_frame_size; 7797b1f684aSSriharsha Basavapatna nxgep->mac.default_mtu = nxgep->mac.maxframesize - 7807b1f684aSSriharsha Basavapatna NXGE_EHEADER_VLAN_CRC; 7817b1f684aSSriharsha Basavapatna } 782678453a8Sspeer } else { 783678453a8Sspeer status = nxge_xcvr_find(nxgep); 784678453a8Sspeer 785678453a8Sspeer if (status != NXGE_OK) { 786678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_attach: " 7874045d941Ssowmini " Couldn't determine card type" 7884045d941Ssowmini " .... exit ")); 789678453a8Sspeer goto nxge_attach_fail5; 790678453a8Sspeer } 791678453a8Sspeer 792678453a8Sspeer status = nxge_get_config_properties(nxgep); 793678453a8Sspeer 794678453a8Sspeer if (status != NXGE_OK) { 795678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 7964045d941Ssowmini "get_hw create failed")); 797678453a8Sspeer goto nxge_attach_fail; 798678453a8Sspeer } 79944961713Sgirish } 80044961713Sgirish 80144961713Sgirish /* 80244961713Sgirish * Setup the Kstats for the driver. 80344961713Sgirish */ 80444961713Sgirish nxge_setup_kstats(nxgep); 80544961713Sgirish 806678453a8Sspeer if (!isLDOMguest(nxgep)) 807678453a8Sspeer nxge_setup_param(nxgep); 80844961713Sgirish 80944961713Sgirish status = nxge_setup_system_dma_pages(nxgep); 81044961713Sgirish if (status != NXGE_OK) { 81144961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "set dma page failed")); 81244961713Sgirish goto nxge_attach_fail; 81344961713Sgirish } 81444961713Sgirish 815678453a8Sspeer 816678453a8Sspeer if (!isLDOMguest(nxgep)) 817678453a8Sspeer nxge_hw_init_niu_common(nxgep); 81844961713Sgirish 81944961713Sgirish status = nxge_setup_mutexes(nxgep); 82044961713Sgirish if (status != NXGE_OK) { 82144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "set mutex failed")); 82244961713Sgirish goto nxge_attach_fail; 82344961713Sgirish } 82444961713Sgirish 825678453a8Sspeer #if defined(sun4v) 826678453a8Sspeer if (isLDOMguest(nxgep)) { 827678453a8Sspeer /* Find our VR & channel sets. */ 828678453a8Sspeer status = nxge_hio_vr_add(nxgep); 829ef523517SMichael Speer if (status != DDI_SUCCESS) { 830ef523517SMichael Speer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 831330cd344SMichael Speer "nxge_hio_vr_add failed")); 832330cd344SMichael Speer (void) hsvc_unregister(&nxgep->niu_hsvc); 833330cd344SMichael Speer nxgep->niu_hsvc_available = B_FALSE; 834ef523517SMichael Speer goto nxge_attach_fail; 835330cd344SMichael Speer } 836678453a8Sspeer goto nxge_attach_exit; 837678453a8Sspeer } 838678453a8Sspeer #endif 839678453a8Sspeer 84044961713Sgirish status = nxge_setup_dev(nxgep); 84144961713Sgirish if (status != DDI_SUCCESS) { 84244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "set dev failed")); 84344961713Sgirish goto nxge_attach_fail; 84444961713Sgirish } 84544961713Sgirish 84644961713Sgirish status = nxge_add_intrs(nxgep); 84744961713Sgirish if (status != DDI_SUCCESS) { 84844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "add_intr failed")); 84944961713Sgirish goto nxge_attach_fail; 85044961713Sgirish } 851330cd344SMichael Speer 85200161856Syc /* If a guest, register with vio_net instead. */ 8532e59129aSraghus if ((status = nxge_mac_register(nxgep)) != NXGE_OK) { 85444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 855678453a8Sspeer "unable to register to mac layer (%d)", status)); 85644961713Sgirish goto nxge_attach_fail; 85744961713Sgirish } 85844961713Sgirish 85944961713Sgirish mac_link_update(nxgep->mach, LINK_STATE_UNKNOWN); 86044961713Sgirish 861678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DDI_CTL, 862678453a8Sspeer "registered to mac (instance %d)", instance)); 86344961713Sgirish 86400161856Syc /* nxge_link_monitor calls xcvr.check_link recursively */ 86544961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 86644961713Sgirish 86744961713Sgirish goto nxge_attach_exit; 86844961713Sgirish 86944961713Sgirish nxge_attach_fail: 87044961713Sgirish nxge_unattach(nxgep); 8712e59129aSraghus goto nxge_attach_fail1; 8722e59129aSraghus 8732e59129aSraghus nxge_attach_fail5: 8742e59129aSraghus /* 8752e59129aSraghus * Tear down the ndd parameters setup. 8762e59129aSraghus */ 8772e59129aSraghus nxge_destroy_param(nxgep); 8782e59129aSraghus 8792e59129aSraghus /* 8802e59129aSraghus * Tear down the kstat setup. 8812e59129aSraghus */ 8822e59129aSraghus nxge_destroy_kstats(nxgep); 8832e59129aSraghus 8842e59129aSraghus nxge_attach_fail4: 8852e59129aSraghus if (nxgep->nxge_hw_p) { 8862e59129aSraghus nxge_uninit_common_dev(nxgep); 8872e59129aSraghus nxgep->nxge_hw_p = NULL; 8882e59129aSraghus } 8892e59129aSraghus 8902e59129aSraghus nxge_attach_fail3: 8912e59129aSraghus /* 8922e59129aSraghus * Unmap the register setup. 8932e59129aSraghus */ 8942e59129aSraghus nxge_unmap_regs(nxgep); 8952e59129aSraghus 8962e59129aSraghus nxge_fm_fini(nxgep); 8972e59129aSraghus 8982e59129aSraghus nxge_attach_fail2: 8992e59129aSraghus ddi_soft_state_free(nxge_list, nxgep->instance); 9002e59129aSraghus 9012e59129aSraghus nxge_attach_fail1: 90256d930aeSspeer if (status != NXGE_OK) 90356d930aeSspeer status = (NXGE_ERROR | NXGE_DDI_FAILED); 90444961713Sgirish nxgep = NULL; 90544961713Sgirish 90644961713Sgirish nxge_attach_exit: 90744961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_attach status = 0x%08x", 9084045d941Ssowmini status)); 90944961713Sgirish 91044961713Sgirish return (status); 91144961713Sgirish } 91244961713Sgirish 91344961713Sgirish static int 91444961713Sgirish nxge_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 91544961713Sgirish { 916*86ef0a63SRichard Lowe int status = DDI_SUCCESS; 917*86ef0a63SRichard Lowe int instance; 918*86ef0a63SRichard Lowe p_nxge_t nxgep = NULL; 91944961713Sgirish 92044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_detach")); 92144961713Sgirish instance = ddi_get_instance(dip); 92244961713Sgirish nxgep = ddi_get_soft_state(nxge_list, instance); 92344961713Sgirish if (nxgep == NULL) { 92444961713Sgirish status = DDI_FAILURE; 92544961713Sgirish goto nxge_detach_exit; 92644961713Sgirish } 92744961713Sgirish 92844961713Sgirish switch (cmd) { 92944961713Sgirish case DDI_DETACH: 93044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_DETACH")); 93144961713Sgirish break; 93244961713Sgirish 93344961713Sgirish case DDI_PM_SUSPEND: 93444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_PM_SUSPEND")); 93544961713Sgirish nxgep->suspended = DDI_PM_SUSPEND; 93644961713Sgirish nxge_suspend(nxgep); 93744961713Sgirish break; 93844961713Sgirish 93944961713Sgirish case DDI_SUSPEND: 94044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_SUSPEND")); 94144961713Sgirish if (nxgep->suspended != DDI_PM_SUSPEND) { 94244961713Sgirish nxgep->suspended = DDI_SUSPEND; 94344961713Sgirish nxge_suspend(nxgep); 94444961713Sgirish } 94544961713Sgirish break; 94644961713Sgirish 94744961713Sgirish default: 94844961713Sgirish status = DDI_FAILURE; 94944961713Sgirish } 95044961713Sgirish 95144961713Sgirish if (cmd != DDI_DETACH) 95244961713Sgirish goto nxge_detach_exit; 95344961713Sgirish 95444961713Sgirish /* 95544961713Sgirish * Stop the xcvr polling. 95644961713Sgirish */ 95744961713Sgirish nxgep->suspended = cmd; 95844961713Sgirish 95944961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 96044961713Sgirish 96163f531d1SSriharsha Basavapatna if (nxgep->mach && (status = mac_unregister(nxgep->mach)) != 0) { 96244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 9634045d941Ssowmini "<== nxge_detach status = 0x%08X", status)); 96444961713Sgirish return (DDI_FAILURE); 96544961713Sgirish } 96644961713Sgirish 96744961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 9684045d941Ssowmini "<== nxge_detach (mac_unregister) status = 0x%08X", status)); 96944961713Sgirish 97044961713Sgirish nxge_unattach(nxgep); 97144961713Sgirish nxgep = NULL; 97244961713Sgirish 97344961713Sgirish nxge_detach_exit: 97444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_detach status = 0x%08X", 9754045d941Ssowmini status)); 97644961713Sgirish 97744961713Sgirish return (status); 97844961713Sgirish } 97944961713Sgirish 98044961713Sgirish static void 98144961713Sgirish nxge_unattach(p_nxge_t nxgep) 98244961713Sgirish { 98344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_unattach")); 98444961713Sgirish 98544961713Sgirish if (nxgep == NULL || nxgep->dev_regs == NULL) { 98644961713Sgirish return; 98744961713Sgirish } 98844961713Sgirish 98998ecde52Stm nxgep->nxge_magic = 0; 99098ecde52Stm 99144961713Sgirish if (nxgep->nxge_timerid) { 99244961713Sgirish nxge_stop_timer(nxgep, nxgep->nxge_timerid); 99344961713Sgirish nxgep->nxge_timerid = 0; 99444961713Sgirish } 99544961713Sgirish 9966f157acbSml /* 9976f157acbSml * If this flag is set, it will affect the Neptune 9986f157acbSml * only. 9996f157acbSml */ 10006f157acbSml if ((nxgep->niu_type != N2_NIU) && nxge_peu_reset_enable) { 10016f157acbSml nxge_niu_peu_reset(nxgep); 10026f157acbSml } 10036f157acbSml 1004678453a8Sspeer #if defined(sun4v) 1005678453a8Sspeer if (isLDOMguest(nxgep)) { 1006d00f30bbSspeer (void) nxge_hio_vr_release(nxgep); 1007678453a8Sspeer } 1008678453a8Sspeer #endif 1009678453a8Sspeer 101053560810Ssbehera if (nxgep->nxge_hw_p) { 101153560810Ssbehera nxge_uninit_common_dev(nxgep); 101253560810Ssbehera nxgep->nxge_hw_p = NULL; 101353560810Ssbehera } 101453560810Ssbehera 101544961713Sgirish #if defined(sun4v) 101644961713Sgirish if (nxgep->niu_type == N2_NIU && nxgep->niu_hsvc_available == B_TRUE) { 101744961713Sgirish (void) hsvc_unregister(&nxgep->niu_hsvc); 101844961713Sgirish nxgep->niu_hsvc_available = B_FALSE; 101944961713Sgirish } 102044961713Sgirish #endif 102144961713Sgirish /* 102244961713Sgirish * Stop any further interrupts. 102344961713Sgirish */ 102444961713Sgirish nxge_remove_intrs(nxgep); 102544961713Sgirish 102644961713Sgirish /* 102744961713Sgirish * Stop the device and free resources. 102844961713Sgirish */ 1029678453a8Sspeer if (!isLDOMguest(nxgep)) { 1030678453a8Sspeer nxge_destroy_dev(nxgep); 1031678453a8Sspeer } 103244961713Sgirish 103344961713Sgirish /* 103444961713Sgirish * Tear down the ndd parameters setup. 103544961713Sgirish */ 103644961713Sgirish nxge_destroy_param(nxgep); 103744961713Sgirish 103844961713Sgirish /* 103944961713Sgirish * Tear down the kstat setup. 104044961713Sgirish */ 104144961713Sgirish nxge_destroy_kstats(nxgep); 104244961713Sgirish 10439d587972SSantwona Behera /* 10449d587972SSantwona Behera * Free any memory allocated for PHY properties 10459d587972SSantwona Behera */ 10469d587972SSantwona Behera if (nxgep->phy_prop.cnt > 0) { 10479d587972SSantwona Behera KMEM_FREE(nxgep->phy_prop.arr, 10489d587972SSantwona Behera sizeof (nxge_phy_mdio_val_t) * nxgep->phy_prop.cnt); 10499d587972SSantwona Behera nxgep->phy_prop.cnt = 0; 10509d587972SSantwona Behera } 10519d587972SSantwona Behera 105244961713Sgirish /* 105344961713Sgirish * Destroy all mutexes. 105444961713Sgirish */ 105544961713Sgirish nxge_destroy_mutexes(nxgep); 105644961713Sgirish 105744961713Sgirish /* 105844961713Sgirish * Remove the list of ndd parameters which 105944961713Sgirish * were setup during attach. 106044961713Sgirish */ 106144961713Sgirish if (nxgep->dip) { 106244961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL, 10634045d941Ssowmini " nxge_unattach: remove all properties")); 106444961713Sgirish 106544961713Sgirish (void) ddi_prop_remove_all(nxgep->dip); 106644961713Sgirish } 106744961713Sgirish 106844961713Sgirish #if NXGE_PROPERTY 106944961713Sgirish nxge_remove_hard_properties(nxgep); 107044961713Sgirish #endif 107144961713Sgirish 107244961713Sgirish /* 107344961713Sgirish * Unmap the register setup. 107444961713Sgirish */ 107544961713Sgirish nxge_unmap_regs(nxgep); 107644961713Sgirish 107744961713Sgirish nxge_fm_fini(nxgep); 107844961713Sgirish 107944961713Sgirish ddi_soft_state_free(nxge_list, nxgep->instance); 108044961713Sgirish 108144961713Sgirish NXGE_DEBUG_MSG((NULL, DDI_CTL, "<== nxge_unattach")); 108244961713Sgirish } 108344961713Sgirish 1084678453a8Sspeer #if defined(sun4v) 1085678453a8Sspeer int 10869d5b8bc5SMichael Speer nxge_hsvc_register(nxge_t *nxgep) 1087678453a8Sspeer { 1088678453a8Sspeer nxge_status_t status; 10894df55fdeSJanie Lu int i, j; 1090678453a8Sspeer 10914df55fdeSJanie Lu NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hsvc_register")); 10924df55fdeSJanie Lu if (nxgep->niu_type != N2_NIU) { 10934df55fdeSJanie Lu NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hsvc_register")); 10944df55fdeSJanie Lu return (DDI_SUCCESS); 1095678453a8Sspeer } 1096678453a8Sspeer 10974df55fdeSJanie Lu /* 10984df55fdeSJanie Lu * Currently, the NIU Hypervisor API supports two major versions: 10994df55fdeSJanie Lu * version 1 and 2. 11004df55fdeSJanie Lu * If Hypervisor introduces a higher major or minor version, 11014df55fdeSJanie Lu * please update NIU_MAJOR_HI and NIU_MINOR_HI accordingly. 11024df55fdeSJanie Lu */ 11034df55fdeSJanie Lu nxgep->niu_hsvc_available = B_FALSE; 11044df55fdeSJanie Lu bcopy(&niu_hsvc, &nxgep->niu_hsvc, 11054df55fdeSJanie Lu sizeof (hsvc_info_t)); 11064df55fdeSJanie Lu 11074df55fdeSJanie Lu for (i = NIU_MAJOR_HI; i > 0; i--) { 11084df55fdeSJanie Lu nxgep->niu_hsvc.hsvc_major = i; 11094df55fdeSJanie Lu for (j = NIU_MINOR_HI; j >= 0; j--) { 11104df55fdeSJanie Lu nxgep->niu_hsvc.hsvc_minor = j; 11114df55fdeSJanie Lu NXGE_DEBUG_MSG((nxgep, DDI_CTL, 11124df55fdeSJanie Lu "nxge_hsvc_register: %s: negotiating " 11134df55fdeSJanie Lu "hypervisor services revision %d " 11144df55fdeSJanie Lu "group: 0x%lx major: 0x%lx " 11154df55fdeSJanie Lu "minor: 0x%lx", 11164df55fdeSJanie Lu nxgep->niu_hsvc.hsvc_modname, 11174df55fdeSJanie Lu nxgep->niu_hsvc.hsvc_rev, 11184df55fdeSJanie Lu nxgep->niu_hsvc.hsvc_group, 11194df55fdeSJanie Lu nxgep->niu_hsvc.hsvc_major, 11204df55fdeSJanie Lu nxgep->niu_hsvc.hsvc_minor, 11214df55fdeSJanie Lu nxgep->niu_min_ver)); 11224df55fdeSJanie Lu 11234df55fdeSJanie Lu if ((status = hsvc_register(&nxgep->niu_hsvc, 11244df55fdeSJanie Lu &nxgep->niu_min_ver)) == 0) { 11254df55fdeSJanie Lu /* Use the supported minor */ 11264df55fdeSJanie Lu nxgep->niu_hsvc.hsvc_minor = nxgep->niu_min_ver; 11274df55fdeSJanie Lu NXGE_DEBUG_MSG((nxgep, DDI_CTL, 11284df55fdeSJanie Lu "nxge_hsvc_register: %s: negotiated " 11294df55fdeSJanie Lu "hypervisor services revision %d " 11304df55fdeSJanie Lu "group: 0x%lx major: 0x%lx " 11314df55fdeSJanie Lu "minor: 0x%lx (niu_min_ver 0x%lx)", 11324df55fdeSJanie Lu nxgep->niu_hsvc.hsvc_modname, 11334df55fdeSJanie Lu nxgep->niu_hsvc.hsvc_rev, 11344df55fdeSJanie Lu nxgep->niu_hsvc.hsvc_group, 11354df55fdeSJanie Lu nxgep->niu_hsvc.hsvc_major, 11364df55fdeSJanie Lu nxgep->niu_hsvc.hsvc_minor, 11374df55fdeSJanie Lu nxgep->niu_min_ver)); 11384df55fdeSJanie Lu 11394df55fdeSJanie Lu nxgep->niu_hsvc_available = B_TRUE; 11404df55fdeSJanie Lu NXGE_DEBUG_MSG((nxgep, DDI_CTL, 11414df55fdeSJanie Lu "<== nxge_hsvc_register: " 11424df55fdeSJanie Lu "NIU Hypervisor service enabled")); 11434df55fdeSJanie Lu return (DDI_SUCCESS); 11444df55fdeSJanie Lu } 11454df55fdeSJanie Lu 11464df55fdeSJanie Lu NXGE_DEBUG_MSG((nxgep, DDI_CTL, 11474df55fdeSJanie Lu "nxge_hsvc_register: %s: negotiated failed - " 11484df55fdeSJanie Lu "try lower major number " 11494df55fdeSJanie Lu "hypervisor services revision %d " 11504df55fdeSJanie Lu "group: 0x%lx major: 0x%lx minor: 0x%lx " 11514df55fdeSJanie Lu "errno: %d", 11524df55fdeSJanie Lu nxgep->niu_hsvc.hsvc_modname, 11534df55fdeSJanie Lu nxgep->niu_hsvc.hsvc_rev, 11544df55fdeSJanie Lu nxgep->niu_hsvc.hsvc_group, 11554df55fdeSJanie Lu nxgep->niu_hsvc.hsvc_major, 11564df55fdeSJanie Lu nxgep->niu_hsvc.hsvc_minor, status)); 11574df55fdeSJanie Lu } 11584df55fdeSJanie Lu } 11594df55fdeSJanie Lu 11604df55fdeSJanie Lu NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 11614df55fdeSJanie Lu "nxge_hsvc_register: %s: cannot negotiate " 11624df55fdeSJanie Lu "hypervisor services revision %d group: 0x%lx " 11634df55fdeSJanie Lu "major: 0x%lx minor: 0x%lx errno: %d", 11644df55fdeSJanie Lu niu_hsvc.hsvc_modname, niu_hsvc.hsvc_rev, 11654df55fdeSJanie Lu niu_hsvc.hsvc_group, niu_hsvc.hsvc_major, 11664df55fdeSJanie Lu niu_hsvc.hsvc_minor, status)); 11674df55fdeSJanie Lu 11684df55fdeSJanie Lu NXGE_DEBUG_MSG((nxgep, DDI_CTL, 11694df55fdeSJanie Lu "<== nxge_hsvc_register: Register to NIU Hypervisor failed")); 11704df55fdeSJanie Lu 11714df55fdeSJanie Lu return (DDI_FAILURE); 1172678453a8Sspeer } 1173678453a8Sspeer #endif 1174678453a8Sspeer 117544961713Sgirish static char n2_siu_name[] = "niu"; 117644961713Sgirish 117744961713Sgirish static nxge_status_t 117844961713Sgirish nxge_map_regs(p_nxge_t nxgep) 117944961713Sgirish { 118044961713Sgirish int ddi_status = DDI_SUCCESS; 1181*86ef0a63SRichard Lowe p_dev_regs_t dev_regs; 118244961713Sgirish char buf[MAXPATHLEN + 1]; 1183*86ef0a63SRichard Lowe char *devname; 118444961713Sgirish #ifdef NXGE_DEBUG 1185*86ef0a63SRichard Lowe char *sysname; 118644961713Sgirish #endif 118744961713Sgirish off_t regsize; 118844961713Sgirish nxge_status_t status = NXGE_OK; 118914ea4bb7Ssd #if !defined(_BIG_ENDIAN) 119014ea4bb7Ssd off_t pci_offset; 119114ea4bb7Ssd uint16_t pcie_devctl; 119214ea4bb7Ssd #endif 119344961713Sgirish 1194678453a8Sspeer if (isLDOMguest(nxgep)) { 1195678453a8Sspeer return (nxge_guest_regs_map(nxgep)); 1196678453a8Sspeer } 1197678453a8Sspeer 119844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_map_regs")); 119944961713Sgirish nxgep->dev_regs = NULL; 120044961713Sgirish dev_regs = KMEM_ZALLOC(sizeof (dev_regs_t), KM_SLEEP); 120144961713Sgirish dev_regs->nxge_regh = NULL; 120244961713Sgirish dev_regs->nxge_pciregh = NULL; 120344961713Sgirish dev_regs->nxge_msix_regh = NULL; 120444961713Sgirish dev_regs->nxge_vir_regh = NULL; 120544961713Sgirish dev_regs->nxge_vir2_regh = NULL; 120659ac0c16Sdavemq nxgep->niu_type = NIU_TYPE_NONE; 120744961713Sgirish 120844961713Sgirish devname = ddi_pathname(nxgep->dip, buf); 120944961713Sgirish ASSERT(strlen(devname) > 0); 121044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 12114045d941Ssowmini "nxge_map_regs: pathname devname %s", devname)); 121244961713Sgirish 121300161856Syc /* 121400161856Syc * The driver is running on a N2-NIU system if devname is something 121500161856Syc * like "/niu@80/network@0" 121600161856Syc */ 121744961713Sgirish if (strstr(devname, n2_siu_name)) { 121844961713Sgirish /* N2/NIU */ 121944961713Sgirish nxgep->niu_type = N2_NIU; 122044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 12214045d941Ssowmini "nxge_map_regs: N2/NIU devname %s", devname)); 12224df55fdeSJanie Lu /* 12234df55fdeSJanie Lu * Get function number: 12244df55fdeSJanie Lu * - N2/NIU: "/niu@80/network@0" and "/niu@80/network@1" 12254df55fdeSJanie Lu */ 122644961713Sgirish nxgep->function_num = 12274045d941Ssowmini (devname[strlen(devname) -1] == '1' ? 1 : 0); 122844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 12294045d941Ssowmini "nxge_map_regs: N2/NIU function number %d", 12304045d941Ssowmini nxgep->function_num)); 123144961713Sgirish } else { 123244961713Sgirish int *prop_val; 1233*86ef0a63SRichard Lowe uint_t prop_len; 1234*86ef0a63SRichard Lowe uint8_t func_num; 123544961713Sgirish 123644961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 12374045d941Ssowmini 0, "reg", 12384045d941Ssowmini &prop_val, &prop_len) != DDI_PROP_SUCCESS) { 123944961713Sgirish NXGE_DEBUG_MSG((nxgep, VPD_CTL, 12404045d941Ssowmini "Reg property not found")); 124144961713Sgirish ddi_status = DDI_FAILURE; 124244961713Sgirish goto nxge_map_regs_fail0; 124344961713Sgirish 124444961713Sgirish } else { 124544961713Sgirish func_num = (prop_val[0] >> 8) & 0x7; 124644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 12474045d941Ssowmini "Reg property found: fun # %d", 12484045d941Ssowmini func_num)); 124944961713Sgirish nxgep->function_num = func_num; 1250678453a8Sspeer if (isLDOMguest(nxgep)) { 1251678453a8Sspeer nxgep->function_num /= 2; 1252678453a8Sspeer return (NXGE_OK); 1253678453a8Sspeer } 125444961713Sgirish ddi_prop_free(prop_val); 125544961713Sgirish } 125644961713Sgirish } 125744961713Sgirish 125844961713Sgirish switch (nxgep->niu_type) { 125944961713Sgirish default: 126044961713Sgirish (void) ddi_dev_regsize(nxgep->dip, 0, ®size); 126144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 12624045d941Ssowmini "nxge_map_regs: pci config size 0x%x", regsize)); 126344961713Sgirish 126444961713Sgirish ddi_status = ddi_regs_map_setup(nxgep->dip, 0, 12654045d941Ssowmini (caddr_t *)&(dev_regs->nxge_pciregp), 0, 0, 12664045d941Ssowmini &nxge_dev_reg_acc_attr, &dev_regs->nxge_pciregh); 126744961713Sgirish if (ddi_status != DDI_SUCCESS) { 126844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 12694045d941Ssowmini "ddi_map_regs, nxge bus config regs failed")); 127044961713Sgirish goto nxge_map_regs_fail0; 127144961713Sgirish } 127244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 12734045d941Ssowmini "nxge_map_reg: PCI config addr 0x%0llx " 12744045d941Ssowmini " handle 0x%0llx", dev_regs->nxge_pciregp, 12754045d941Ssowmini dev_regs->nxge_pciregh)); 127644961713Sgirish /* 127744961713Sgirish * IMP IMP 127844961713Sgirish * workaround for bit swapping bug in HW 127944961713Sgirish * which ends up in no-snoop = yes 128044961713Sgirish * resulting, in DMA not synched properly 128144961713Sgirish */ 128244961713Sgirish #if !defined(_BIG_ENDIAN) 128314ea4bb7Ssd /* workarounds for x86 systems */ 128414ea4bb7Ssd pci_offset = 0x80 + PCIE_DEVCTL; 128548056c53SMichael Speer pcie_devctl = pci_config_get16(dev_regs->nxge_pciregh, 128648056c53SMichael Speer pci_offset); 128748056c53SMichael Speer pcie_devctl &= ~PCIE_DEVCTL_ENABLE_NO_SNOOP; 128814ea4bb7Ssd pcie_devctl |= PCIE_DEVCTL_RO_EN; 128914ea4bb7Ssd pci_config_put16(dev_regs->nxge_pciregh, pci_offset, 12904045d941Ssowmini pcie_devctl); 129144961713Sgirish #endif 129214ea4bb7Ssd 129344961713Sgirish (void) ddi_dev_regsize(nxgep->dip, 1, ®size); 129444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 12954045d941Ssowmini "nxge_map_regs: pio size 0x%x", regsize)); 129644961713Sgirish /* set up the device mapped register */ 129744961713Sgirish ddi_status = ddi_regs_map_setup(nxgep->dip, 1, 12984045d941Ssowmini (caddr_t *)&(dev_regs->nxge_regp), 0, 0, 12994045d941Ssowmini &nxge_dev_reg_acc_attr, &dev_regs->nxge_regh); 130044961713Sgirish if (ddi_status != DDI_SUCCESS) { 130144961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 13024045d941Ssowmini "ddi_map_regs for Neptune global reg failed")); 130344961713Sgirish goto nxge_map_regs_fail1; 130444961713Sgirish } 130544961713Sgirish 130644961713Sgirish /* set up the msi/msi-x mapped register */ 130744961713Sgirish (void) ddi_dev_regsize(nxgep->dip, 2, ®size); 130844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 13094045d941Ssowmini "nxge_map_regs: msix size 0x%x", regsize)); 131044961713Sgirish ddi_status = ddi_regs_map_setup(nxgep->dip, 2, 13114045d941Ssowmini (caddr_t *)&(dev_regs->nxge_msix_regp), 0, 0, 13124045d941Ssowmini &nxge_dev_reg_acc_attr, &dev_regs->nxge_msix_regh); 131344961713Sgirish if (ddi_status != DDI_SUCCESS) { 131444961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 13154045d941Ssowmini "ddi_map_regs for msi reg failed")); 131644961713Sgirish goto nxge_map_regs_fail2; 131744961713Sgirish } 131844961713Sgirish 131944961713Sgirish /* set up the vio region mapped register */ 132044961713Sgirish (void) ddi_dev_regsize(nxgep->dip, 3, ®size); 132144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 13224045d941Ssowmini "nxge_map_regs: vio size 0x%x", regsize)); 132344961713Sgirish ddi_status = ddi_regs_map_setup(nxgep->dip, 3, 13244045d941Ssowmini (caddr_t *)&(dev_regs->nxge_vir_regp), 0, 0, 13254045d941Ssowmini &nxge_dev_reg_acc_attr, &dev_regs->nxge_vir_regh); 132644961713Sgirish 132744961713Sgirish if (ddi_status != DDI_SUCCESS) { 132844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 13294045d941Ssowmini "ddi_map_regs for nxge vio reg failed")); 133044961713Sgirish goto nxge_map_regs_fail3; 133144961713Sgirish } 133244961713Sgirish nxgep->dev_regs = dev_regs; 133344961713Sgirish 133444961713Sgirish NPI_PCI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_pciregh); 133544961713Sgirish NPI_PCI_ADD_HANDLE_SET(nxgep, 13364045d941Ssowmini (npi_reg_ptr_t)dev_regs->nxge_pciregp); 133744961713Sgirish NPI_MSI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_msix_regh); 133844961713Sgirish NPI_MSI_ADD_HANDLE_SET(nxgep, 13394045d941Ssowmini (npi_reg_ptr_t)dev_regs->nxge_msix_regp); 134044961713Sgirish 134144961713Sgirish NPI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh); 134244961713Sgirish NPI_ADD_HANDLE_SET(nxgep, (npi_reg_ptr_t)dev_regs->nxge_regp); 134344961713Sgirish 134444961713Sgirish NPI_REG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh); 134544961713Sgirish NPI_REG_ADD_HANDLE_SET(nxgep, 13464045d941Ssowmini (npi_reg_ptr_t)dev_regs->nxge_regp); 134744961713Sgirish 134844961713Sgirish NPI_VREG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_vir_regh); 134944961713Sgirish NPI_VREG_ADD_HANDLE_SET(nxgep, 13504045d941Ssowmini (npi_reg_ptr_t)dev_regs->nxge_vir_regp); 135144961713Sgirish 135244961713Sgirish break; 135344961713Sgirish 135444961713Sgirish case N2_NIU: 135544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "ddi_map_regs, NIU")); 135644961713Sgirish /* 135744961713Sgirish * Set up the device mapped register (FWARC 2006/556) 135844961713Sgirish * (changed back to 1: reg starts at 1!) 135944961713Sgirish */ 136044961713Sgirish (void) ddi_dev_regsize(nxgep->dip, 1, ®size); 136144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 13624045d941Ssowmini "nxge_map_regs: dev size 0x%x", regsize)); 136344961713Sgirish ddi_status = ddi_regs_map_setup(nxgep->dip, 1, 13644045d941Ssowmini (caddr_t *)&(dev_regs->nxge_regp), 0, 0, 13654045d941Ssowmini &nxge_dev_reg_acc_attr, &dev_regs->nxge_regh); 136644961713Sgirish 136744961713Sgirish if (ddi_status != DDI_SUCCESS) { 136844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 13694045d941Ssowmini "ddi_map_regs for N2/NIU, global reg failed ")); 137044961713Sgirish goto nxge_map_regs_fail1; 137144961713Sgirish } 137244961713Sgirish 1373678453a8Sspeer /* set up the first vio region mapped register */ 137444961713Sgirish (void) ddi_dev_regsize(nxgep->dip, 2, ®size); 137544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 13764045d941Ssowmini "nxge_map_regs: vio (1) size 0x%x", regsize)); 137744961713Sgirish ddi_status = ddi_regs_map_setup(nxgep->dip, 2, 13784045d941Ssowmini (caddr_t *)&(dev_regs->nxge_vir_regp), 0, 0, 13794045d941Ssowmini &nxge_dev_reg_acc_attr, &dev_regs->nxge_vir_regh); 138044961713Sgirish 138144961713Sgirish if (ddi_status != DDI_SUCCESS) { 138244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 13834045d941Ssowmini "ddi_map_regs for nxge vio reg failed")); 138444961713Sgirish goto nxge_map_regs_fail2; 138544961713Sgirish } 1386678453a8Sspeer /* set up the second vio region mapped register */ 138744961713Sgirish (void) ddi_dev_regsize(nxgep->dip, 3, ®size); 138844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 13894045d941Ssowmini "nxge_map_regs: vio (3) size 0x%x", regsize)); 139044961713Sgirish ddi_status = ddi_regs_map_setup(nxgep->dip, 3, 13914045d941Ssowmini (caddr_t *)&(dev_regs->nxge_vir2_regp), 0, 0, 13924045d941Ssowmini &nxge_dev_reg_acc_attr, &dev_regs->nxge_vir2_regh); 139344961713Sgirish 139444961713Sgirish if (ddi_status != DDI_SUCCESS) { 139544961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 13964045d941Ssowmini "ddi_map_regs for nxge vio2 reg failed")); 139744961713Sgirish goto nxge_map_regs_fail3; 139844961713Sgirish } 139944961713Sgirish nxgep->dev_regs = dev_regs; 140044961713Sgirish 140144961713Sgirish NPI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh); 140244961713Sgirish NPI_ADD_HANDLE_SET(nxgep, (npi_reg_ptr_t)dev_regs->nxge_regp); 140344961713Sgirish 140444961713Sgirish NPI_REG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh); 140544961713Sgirish NPI_REG_ADD_HANDLE_SET(nxgep, 14064045d941Ssowmini (npi_reg_ptr_t)dev_regs->nxge_regp); 140744961713Sgirish 140844961713Sgirish NPI_VREG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_vir_regh); 140944961713Sgirish NPI_VREG_ADD_HANDLE_SET(nxgep, 14104045d941Ssowmini (npi_reg_ptr_t)dev_regs->nxge_vir_regp); 141144961713Sgirish 141244961713Sgirish NPI_V2REG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_vir2_regh); 141344961713Sgirish NPI_V2REG_ADD_HANDLE_SET(nxgep, 14144045d941Ssowmini (npi_reg_ptr_t)dev_regs->nxge_vir2_regp); 141544961713Sgirish 141644961713Sgirish break; 141744961713Sgirish } 141844961713Sgirish 141944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "nxge_map_reg: hardware addr 0x%0llx " 14204045d941Ssowmini " handle 0x%0llx", dev_regs->nxge_regp, dev_regs->nxge_regh)); 142144961713Sgirish 142244961713Sgirish goto nxge_map_regs_exit; 142344961713Sgirish nxge_map_regs_fail3: 142444961713Sgirish if (dev_regs->nxge_msix_regh) { 142544961713Sgirish ddi_regs_map_free(&dev_regs->nxge_msix_regh); 142644961713Sgirish } 142744961713Sgirish if (dev_regs->nxge_vir_regh) { 142844961713Sgirish ddi_regs_map_free(&dev_regs->nxge_regh); 142944961713Sgirish } 143044961713Sgirish nxge_map_regs_fail2: 143144961713Sgirish if (dev_regs->nxge_regh) { 143244961713Sgirish ddi_regs_map_free(&dev_regs->nxge_regh); 143344961713Sgirish } 143444961713Sgirish nxge_map_regs_fail1: 143544961713Sgirish if (dev_regs->nxge_pciregh) { 143644961713Sgirish ddi_regs_map_free(&dev_regs->nxge_pciregh); 143744961713Sgirish } 143844961713Sgirish nxge_map_regs_fail0: 143944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "Freeing register set memory")); 144044961713Sgirish kmem_free(dev_regs, sizeof (dev_regs_t)); 144144961713Sgirish 144244961713Sgirish nxge_map_regs_exit: 144344961713Sgirish if (ddi_status != DDI_SUCCESS) 144444961713Sgirish status |= (NXGE_ERROR | NXGE_DDI_FAILED); 144544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_map_regs")); 144644961713Sgirish return (status); 144744961713Sgirish } 144844961713Sgirish 144944961713Sgirish static void 145044961713Sgirish nxge_unmap_regs(p_nxge_t nxgep) 145144961713Sgirish { 145244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_unmap_regs")); 1453678453a8Sspeer 1454678453a8Sspeer if (isLDOMguest(nxgep)) { 1455678453a8Sspeer nxge_guest_regs_map_free(nxgep); 1456678453a8Sspeer return; 1457678453a8Sspeer } 1458678453a8Sspeer 145944961713Sgirish if (nxgep->dev_regs) { 146044961713Sgirish if (nxgep->dev_regs->nxge_pciregh) { 146144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 14624045d941Ssowmini "==> nxge_unmap_regs: bus")); 146344961713Sgirish ddi_regs_map_free(&nxgep->dev_regs->nxge_pciregh); 146444961713Sgirish nxgep->dev_regs->nxge_pciregh = NULL; 146544961713Sgirish } 146644961713Sgirish if (nxgep->dev_regs->nxge_regh) { 146744961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 14684045d941Ssowmini "==> nxge_unmap_regs: device registers")); 146944961713Sgirish ddi_regs_map_free(&nxgep->dev_regs->nxge_regh); 147044961713Sgirish nxgep->dev_regs->nxge_regh = NULL; 147144961713Sgirish } 147244961713Sgirish if (nxgep->dev_regs->nxge_msix_regh) { 147344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 14744045d941Ssowmini "==> nxge_unmap_regs: device interrupts")); 147544961713Sgirish ddi_regs_map_free(&nxgep->dev_regs->nxge_msix_regh); 147644961713Sgirish nxgep->dev_regs->nxge_msix_regh = NULL; 147744961713Sgirish } 147844961713Sgirish if (nxgep->dev_regs->nxge_vir_regh) { 147944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 14804045d941Ssowmini "==> nxge_unmap_regs: vio region")); 148144961713Sgirish ddi_regs_map_free(&nxgep->dev_regs->nxge_vir_regh); 148244961713Sgirish nxgep->dev_regs->nxge_vir_regh = NULL; 148344961713Sgirish } 148444961713Sgirish if (nxgep->dev_regs->nxge_vir2_regh) { 148544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 14864045d941Ssowmini "==> nxge_unmap_regs: vio2 region")); 148744961713Sgirish ddi_regs_map_free(&nxgep->dev_regs->nxge_vir2_regh); 148844961713Sgirish nxgep->dev_regs->nxge_vir2_regh = NULL; 148944961713Sgirish } 149044961713Sgirish 149144961713Sgirish kmem_free(nxgep->dev_regs, sizeof (dev_regs_t)); 149244961713Sgirish nxgep->dev_regs = NULL; 149344961713Sgirish } 149444961713Sgirish 149544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_unmap_regs")); 149644961713Sgirish } 149744961713Sgirish 149844961713Sgirish static nxge_status_t 149944961713Sgirish nxge_setup_mutexes(p_nxge_t nxgep) 150044961713Sgirish { 150144961713Sgirish int ddi_status = DDI_SUCCESS; 150244961713Sgirish nxge_status_t status = NXGE_OK; 150344961713Sgirish nxge_classify_t *classify_ptr; 150444961713Sgirish int partition; 150544961713Sgirish 150644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_setup_mutexes")); 150744961713Sgirish 150844961713Sgirish /* 150944961713Sgirish * Get the interrupt cookie so the mutexes can be 151058324dfcSspeer * Initialized. 151144961713Sgirish */ 1512678453a8Sspeer if (isLDOMguest(nxgep)) { 1513678453a8Sspeer nxgep->interrupt_cookie = 0; 1514678453a8Sspeer } else { 1515678453a8Sspeer ddi_status = ddi_get_iblock_cookie(nxgep->dip, 0, 1516678453a8Sspeer &nxgep->interrupt_cookie); 1517678453a8Sspeer 1518678453a8Sspeer if (ddi_status != DDI_SUCCESS) { 1519678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1520678453a8Sspeer "<== nxge_setup_mutexes: failed 0x%x", 1521678453a8Sspeer ddi_status)); 1522678453a8Sspeer goto nxge_setup_mutexes_exit; 1523678453a8Sspeer } 152444961713Sgirish } 152544961713Sgirish 152698ecde52Stm cv_init(&nxgep->poll_cv, NULL, CV_DRIVER, NULL); 152798ecde52Stm MUTEX_INIT(&nxgep->poll_lock, NULL, 152898ecde52Stm MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 152998ecde52Stm 153044961713Sgirish /* 153198ecde52Stm * Initialize mutexes for this device. 153244961713Sgirish */ 153344961713Sgirish MUTEX_INIT(nxgep->genlock, NULL, 15344045d941Ssowmini MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 153544961713Sgirish MUTEX_INIT(&nxgep->ouraddr_lock, NULL, 15364045d941Ssowmini MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 153744961713Sgirish MUTEX_INIT(&nxgep->mif_lock, NULL, 15384045d941Ssowmini MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1539678453a8Sspeer MUTEX_INIT(&nxgep->group_lock, NULL, 1540678453a8Sspeer MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 154144961713Sgirish RW_INIT(&nxgep->filter_lock, NULL, 15424045d941Ssowmini RW_DRIVER, (void *)nxgep->interrupt_cookie); 154344961713Sgirish 154444961713Sgirish classify_ptr = &nxgep->classifier; 154544961713Sgirish /* 154644961713Sgirish * FFLP Mutexes are never used in interrupt context 154744961713Sgirish * as fflp operation can take very long time to 154844961713Sgirish * complete and hence not suitable to invoke from interrupt 154944961713Sgirish * handlers. 155044961713Sgirish */ 155144961713Sgirish MUTEX_INIT(&classify_ptr->tcam_lock, NULL, 155259ac0c16Sdavemq NXGE_MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 15532e59129aSraghus if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) { 155444961713Sgirish MUTEX_INIT(&classify_ptr->fcram_lock, NULL, 155559ac0c16Sdavemq NXGE_MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 155644961713Sgirish for (partition = 0; partition < MAX_PARTITION; partition++) { 155744961713Sgirish MUTEX_INIT(&classify_ptr->hash_lock[partition], NULL, 155844961713Sgirish NXGE_MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 155944961713Sgirish } 156044961713Sgirish } 156144961713Sgirish 156244961713Sgirish nxge_setup_mutexes_exit: 156344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 156459ac0c16Sdavemq "<== nxge_setup_mutexes status = %x", status)); 156544961713Sgirish 156644961713Sgirish if (ddi_status != DDI_SUCCESS) 156744961713Sgirish status |= (NXGE_ERROR | NXGE_DDI_FAILED); 156844961713Sgirish 156944961713Sgirish return (status); 157044961713Sgirish } 157144961713Sgirish 157244961713Sgirish static void 157344961713Sgirish nxge_destroy_mutexes(p_nxge_t nxgep) 157444961713Sgirish { 157544961713Sgirish int partition; 157644961713Sgirish nxge_classify_t *classify_ptr; 157744961713Sgirish 157844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_mutexes")); 157944961713Sgirish RW_DESTROY(&nxgep->filter_lock); 1580678453a8Sspeer MUTEX_DESTROY(&nxgep->group_lock); 158144961713Sgirish MUTEX_DESTROY(&nxgep->mif_lock); 158244961713Sgirish MUTEX_DESTROY(&nxgep->ouraddr_lock); 158344961713Sgirish MUTEX_DESTROY(nxgep->genlock); 158444961713Sgirish 158544961713Sgirish classify_ptr = &nxgep->classifier; 158644961713Sgirish MUTEX_DESTROY(&classify_ptr->tcam_lock); 158744961713Sgirish 158898ecde52Stm /* Destroy all polling resources. */ 158998ecde52Stm MUTEX_DESTROY(&nxgep->poll_lock); 159098ecde52Stm cv_destroy(&nxgep->poll_cv); 159198ecde52Stm 159298ecde52Stm /* free data structures, based on HW type */ 15932e59129aSraghus if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) { 159444961713Sgirish MUTEX_DESTROY(&classify_ptr->fcram_lock); 159544961713Sgirish for (partition = 0; partition < MAX_PARTITION; partition++) { 159644961713Sgirish MUTEX_DESTROY(&classify_ptr->hash_lock[partition]); 159744961713Sgirish } 159844961713Sgirish } 159944961713Sgirish 160044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_mutexes")); 160144961713Sgirish } 160244961713Sgirish 160344961713Sgirish nxge_status_t 160444961713Sgirish nxge_init(p_nxge_t nxgep) 160544961713Sgirish { 1606678453a8Sspeer nxge_status_t status = NXGE_OK; 160744961713Sgirish 160844961713Sgirish NXGE_DEBUG_MSG((nxgep, STR_CTL, "==> nxge_init")); 160944961713Sgirish 161014ea4bb7Ssd if (nxgep->drv_state & STATE_HW_INITIALIZED) { 161114ea4bb7Ssd return (status); 161214ea4bb7Ssd } 161314ea4bb7Ssd 161444961713Sgirish /* 161544961713Sgirish * Allocate system memory for the receive/transmit buffer blocks 161644961713Sgirish * and receive/transmit descriptor rings. 161744961713Sgirish */ 161844961713Sgirish status = nxge_alloc_mem_pool(nxgep); 161944961713Sgirish if (status != NXGE_OK) { 162044961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "alloc mem failed\n")); 162144961713Sgirish goto nxge_init_fail1; 162244961713Sgirish } 162344961713Sgirish 1624678453a8Sspeer if (!isLDOMguest(nxgep)) { 1625678453a8Sspeer /* 1626678453a8Sspeer * Initialize and enable the TXC registers. 1627678453a8Sspeer * (Globally enable the Tx controller, 1628678453a8Sspeer * enable the port, configure the dma channel bitmap, 1629678453a8Sspeer * configure the max burst size). 1630678453a8Sspeer */ 1631678453a8Sspeer status = nxge_txc_init(nxgep); 1632678453a8Sspeer if (status != NXGE_OK) { 1633678453a8Sspeer NXGE_ERROR_MSG((nxgep, 1634678453a8Sspeer NXGE_ERR_CTL, "init txc failed\n")); 1635678453a8Sspeer goto nxge_init_fail2; 1636678453a8Sspeer } 163744961713Sgirish } 163844961713Sgirish 163944961713Sgirish /* 164044961713Sgirish * Initialize and enable TXDMA channels. 164144961713Sgirish */ 164244961713Sgirish status = nxge_init_txdma_channels(nxgep); 164344961713Sgirish if (status != NXGE_OK) { 164444961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init txdma failed\n")); 164544961713Sgirish goto nxge_init_fail3; 164644961713Sgirish } 164744961713Sgirish 164844961713Sgirish /* 164944961713Sgirish * Initialize and enable RXDMA channels. 165044961713Sgirish */ 165144961713Sgirish status = nxge_init_rxdma_channels(nxgep); 165244961713Sgirish if (status != NXGE_OK) { 165344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init rxdma failed\n")); 165444961713Sgirish goto nxge_init_fail4; 165544961713Sgirish } 165644961713Sgirish 1657678453a8Sspeer /* 1658678453a8Sspeer * The guest domain is now done. 1659678453a8Sspeer */ 1660678453a8Sspeer if (isLDOMguest(nxgep)) { 1661678453a8Sspeer nxgep->drv_state |= STATE_HW_INITIALIZED; 1662678453a8Sspeer goto nxge_init_exit; 1663678453a8Sspeer } 1664678453a8Sspeer 166544961713Sgirish /* 166644961713Sgirish * Initialize TCAM and FCRAM (Neptune). 166744961713Sgirish */ 166844961713Sgirish status = nxge_classify_init(nxgep); 166944961713Sgirish if (status != NXGE_OK) { 167044961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init classify failed\n")); 167144961713Sgirish goto nxge_init_fail5; 167244961713Sgirish } 167344961713Sgirish 167444961713Sgirish /* 167544961713Sgirish * Initialize ZCP 167644961713Sgirish */ 167744961713Sgirish status = nxge_zcp_init(nxgep); 167844961713Sgirish if (status != NXGE_OK) { 167944961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init ZCP failed\n")); 168044961713Sgirish goto nxge_init_fail5; 168144961713Sgirish } 168244961713Sgirish 168344961713Sgirish /* 168444961713Sgirish * Initialize IPP. 168544961713Sgirish */ 168644961713Sgirish status = nxge_ipp_init(nxgep); 168744961713Sgirish if (status != NXGE_OK) { 168844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init IPP failed\n")); 168944961713Sgirish goto nxge_init_fail5; 169044961713Sgirish } 169144961713Sgirish 169244961713Sgirish /* 169344961713Sgirish * Initialize the MAC block. 169444961713Sgirish */ 169544961713Sgirish status = nxge_mac_init(nxgep); 169644961713Sgirish if (status != NXGE_OK) { 169744961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init MAC failed\n")); 169844961713Sgirish goto nxge_init_fail5; 169944961713Sgirish } 170044961713Sgirish 170144961713Sgirish /* 1702e759c33aSMichael Speer * Enable the interrrupts for DDI. 170344961713Sgirish */ 1704e759c33aSMichael Speer nxge_intrs_enable(nxgep); 1705e759c33aSMichael Speer 170644961713Sgirish nxgep->drv_state |= STATE_HW_INITIALIZED; 170744961713Sgirish 170844961713Sgirish goto nxge_init_exit; 170944961713Sgirish 171044961713Sgirish nxge_init_fail5: 171144961713Sgirish nxge_uninit_rxdma_channels(nxgep); 171244961713Sgirish nxge_init_fail4: 171344961713Sgirish nxge_uninit_txdma_channels(nxgep); 171444961713Sgirish nxge_init_fail3: 1715678453a8Sspeer if (!isLDOMguest(nxgep)) { 1716678453a8Sspeer (void) nxge_txc_uninit(nxgep); 1717678453a8Sspeer } 171844961713Sgirish nxge_init_fail2: 171944961713Sgirish nxge_free_mem_pool(nxgep); 172044961713Sgirish nxge_init_fail1: 172144961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 17224045d941Ssowmini "<== nxge_init status (failed) = 0x%08x", status)); 172344961713Sgirish return (status); 172444961713Sgirish 172544961713Sgirish nxge_init_exit: 172644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_init status = 0x%08x", 17274045d941Ssowmini status)); 172844961713Sgirish return (status); 172944961713Sgirish } 173044961713Sgirish 173144961713Sgirish 173244961713Sgirish timeout_id_t 173344961713Sgirish nxge_start_timer(p_nxge_t nxgep, fptrv_t func, int msec) 173444961713Sgirish { 17354045d941Ssowmini if ((nxgep->suspended == 0) || (nxgep->suspended == DDI_RESUME)) { 173644961713Sgirish return (timeout(func, (caddr_t)nxgep, 17374045d941Ssowmini drv_usectohz(1000 * msec))); 173844961713Sgirish } 173944961713Sgirish return (NULL); 174044961713Sgirish } 174144961713Sgirish 174244961713Sgirish /*ARGSUSED*/ 174344961713Sgirish void 174444961713Sgirish nxge_stop_timer(p_nxge_t nxgep, timeout_id_t timerid) 174544961713Sgirish { 174644961713Sgirish if (timerid) { 174744961713Sgirish (void) untimeout(timerid); 174844961713Sgirish } 174944961713Sgirish } 175044961713Sgirish 175144961713Sgirish void 175244961713Sgirish nxge_uninit(p_nxge_t nxgep) 175344961713Sgirish { 175444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_uninit")); 175544961713Sgirish 175644961713Sgirish if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 175744961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 17584045d941Ssowmini "==> nxge_uninit: not initialized")); 175944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 17604045d941Ssowmini "<== nxge_uninit")); 176144961713Sgirish return; 176244961713Sgirish } 176344961713Sgirish 1764e759c33aSMichael Speer if (!isLDOMguest(nxgep)) { 1765e759c33aSMichael Speer /* 1766e759c33aSMichael Speer * Reset the receive MAC side. 1767e759c33aSMichael Speer */ 1768e759c33aSMichael Speer (void) nxge_rx_mac_disable(nxgep); 1769e759c33aSMichael Speer 1770e759c33aSMichael Speer /* 1771e759c33aSMichael Speer * Drain the IPP. 1772e759c33aSMichael Speer */ 1773e759c33aSMichael Speer (void) nxge_ipp_drain(nxgep); 1774e759c33aSMichael Speer } 1775e759c33aSMichael Speer 177644961713Sgirish /* stop timer */ 177744961713Sgirish if (nxgep->nxge_timerid) { 177844961713Sgirish nxge_stop_timer(nxgep, nxgep->nxge_timerid); 177944961713Sgirish nxgep->nxge_timerid = 0; 178044961713Sgirish } 178144961713Sgirish 178244961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 178344961713Sgirish (void) nxge_intr_hw_disable(nxgep); 178444961713Sgirish 178544961713Sgirish 178644961713Sgirish /* Disable and soft reset the IPP */ 1787678453a8Sspeer if (!isLDOMguest(nxgep)) 1788678453a8Sspeer (void) nxge_ipp_disable(nxgep); 178944961713Sgirish 1790a3c5bd6dSspeer /* Free classification resources */ 1791a3c5bd6dSspeer (void) nxge_classify_uninit(nxgep); 1792a3c5bd6dSspeer 179344961713Sgirish /* 179444961713Sgirish * Reset the transmit/receive DMA side. 179544961713Sgirish */ 179644961713Sgirish (void) nxge_txdma_hw_mode(nxgep, NXGE_DMA_STOP); 179744961713Sgirish (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_STOP); 179844961713Sgirish 179944961713Sgirish nxge_uninit_txdma_channels(nxgep); 180044961713Sgirish nxge_uninit_rxdma_channels(nxgep); 180144961713Sgirish 180244961713Sgirish /* 180344961713Sgirish * Reset the transmit MAC side. 180444961713Sgirish */ 180544961713Sgirish (void) nxge_tx_mac_disable(nxgep); 180644961713Sgirish 180744961713Sgirish nxge_free_mem_pool(nxgep); 180844961713Sgirish 18096f157acbSml /* 18106f157acbSml * Start the timer if the reset flag is not set. 18116f157acbSml * If this reset flag is set, the link monitor 18126f157acbSml * will not be started in order to stop furthur bus 18136f157acbSml * activities coming from this interface. 18146f157acbSml * The driver will start the monitor function 18156f157acbSml * if the interface was initialized again later. 18166f157acbSml */ 18176f157acbSml if (!nxge_peu_reset_enable) { 18186f157acbSml (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 18196f157acbSml } 182044961713Sgirish 182144961713Sgirish nxgep->drv_state &= ~STATE_HW_INITIALIZED; 182244961713Sgirish 182344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_uninit: " 18244045d941Ssowmini "nxge_mblks_pending %d", nxge_mblks_pending)); 182544961713Sgirish } 182644961713Sgirish 182744961713Sgirish void 182844961713Sgirish nxge_get64(p_nxge_t nxgep, p_mblk_t mp) 182944961713Sgirish { 183044961713Sgirish uint64_t reg; 183144961713Sgirish uint64_t regdata; 183244961713Sgirish int i, retry; 183344961713Sgirish 183444961713Sgirish bcopy((char *)mp->b_rptr, (char *)®, sizeof (uint64_t)); 183544961713Sgirish regdata = 0; 183644961713Sgirish retry = 1; 183744961713Sgirish 183844961713Sgirish for (i = 0; i < retry; i++) { 183944961713Sgirish NXGE_REG_RD64(nxgep->npi_handle, reg, ®data); 184044961713Sgirish } 184144961713Sgirish bcopy((char *)®data, (char *)mp->b_rptr, sizeof (uint64_t)); 184244961713Sgirish } 184344961713Sgirish 184444961713Sgirish void 184544961713Sgirish nxge_put64(p_nxge_t nxgep, p_mblk_t mp) 184644961713Sgirish { 184744961713Sgirish uint64_t reg; 184844961713Sgirish uint64_t buf[2]; 184944961713Sgirish 185044961713Sgirish bcopy((char *)mp->b_rptr, (char *)&buf[0], 2 * sizeof (uint64_t)); 185144961713Sgirish reg = buf[0]; 185244961713Sgirish 185344961713Sgirish NXGE_NPI_PIO_WRITE64(nxgep->npi_handle, reg, buf[1]); 185444961713Sgirish } 185544961713Sgirish 185644961713Sgirish /*ARGSUSED*/ 185744961713Sgirish /*VARARGS*/ 185844961713Sgirish void 185944961713Sgirish nxge_debug_msg(p_nxge_t nxgep, uint64_t level, char *fmt, ...) 186044961713Sgirish { 186144961713Sgirish char msg_buffer[1048]; 186244961713Sgirish char prefix_buffer[32]; 186344961713Sgirish int instance; 186444961713Sgirish uint64_t debug_level; 186544961713Sgirish int cmn_level = CE_CONT; 186644961713Sgirish va_list ap; 186744961713Sgirish 1868678453a8Sspeer if (nxgep && nxgep->nxge_debug_level != nxge_debug_level) { 1869678453a8Sspeer /* In case a developer has changed nxge_debug_level. */ 1870678453a8Sspeer if (nxgep->nxge_debug_level != nxge_debug_level) 1871678453a8Sspeer nxgep->nxge_debug_level = nxge_debug_level; 1872678453a8Sspeer } 1873678453a8Sspeer 187444961713Sgirish debug_level = (nxgep == NULL) ? nxge_debug_level : 18754045d941Ssowmini nxgep->nxge_debug_level; 187644961713Sgirish 187744961713Sgirish if ((level & debug_level) || 18784045d941Ssowmini (level == NXGE_NOTE) || 18794045d941Ssowmini (level == NXGE_ERR_CTL)) { 188044961713Sgirish /* do the msg processing */ 188144961713Sgirish MUTEX_ENTER(&nxgedebuglock); 188244961713Sgirish 188344961713Sgirish if ((level & NXGE_NOTE)) { 188444961713Sgirish cmn_level = CE_NOTE; 188544961713Sgirish } 188644961713Sgirish 188744961713Sgirish if (level & NXGE_ERR_CTL) { 188844961713Sgirish cmn_level = CE_WARN; 188944961713Sgirish } 189044961713Sgirish 189144961713Sgirish va_start(ap, fmt); 189244961713Sgirish (void) vsprintf(msg_buffer, fmt, ap); 189344961713Sgirish va_end(ap); 189444961713Sgirish if (nxgep == NULL) { 189544961713Sgirish instance = -1; 189644961713Sgirish (void) sprintf(prefix_buffer, "%s :", "nxge"); 189744961713Sgirish } else { 189844961713Sgirish instance = nxgep->instance; 189944961713Sgirish (void) sprintf(prefix_buffer, 19004045d941Ssowmini "%s%d :", "nxge", instance); 190144961713Sgirish } 190244961713Sgirish 190344961713Sgirish MUTEX_EXIT(&nxgedebuglock); 190444961713Sgirish cmn_err(cmn_level, "!%s %s\n", 19054045d941Ssowmini prefix_buffer, msg_buffer); 190644961713Sgirish 190744961713Sgirish } 190844961713Sgirish } 190944961713Sgirish 191044961713Sgirish char * 191144961713Sgirish nxge_dump_packet(char *addr, int size) 191244961713Sgirish { 191344961713Sgirish uchar_t *ap = (uchar_t *)addr; 191444961713Sgirish int i; 191544961713Sgirish static char etherbuf[1024]; 191644961713Sgirish char *cp = etherbuf; 191744961713Sgirish char digits[] = "0123456789abcdef"; 191844961713Sgirish 191944961713Sgirish if (!size) 192044961713Sgirish size = 60; 192144961713Sgirish 192244961713Sgirish if (size > MAX_DUMP_SZ) { 192344961713Sgirish /* Dump the leading bytes */ 192444961713Sgirish for (i = 0; i < MAX_DUMP_SZ/2; i++) { 192544961713Sgirish if (*ap > 0x0f) 192644961713Sgirish *cp++ = digits[*ap >> 4]; 192744961713Sgirish *cp++ = digits[*ap++ & 0xf]; 192844961713Sgirish *cp++ = ':'; 192944961713Sgirish } 193044961713Sgirish for (i = 0; i < 20; i++) 193144961713Sgirish *cp++ = '.'; 193244961713Sgirish /* Dump the last MAX_DUMP_SZ/2 bytes */ 193344961713Sgirish ap = (uchar_t *)(addr + (size - MAX_DUMP_SZ/2)); 193444961713Sgirish for (i = 0; i < MAX_DUMP_SZ/2; i++) { 193544961713Sgirish if (*ap > 0x0f) 193644961713Sgirish *cp++ = digits[*ap >> 4]; 193744961713Sgirish *cp++ = digits[*ap++ & 0xf]; 193844961713Sgirish *cp++ = ':'; 193944961713Sgirish } 194044961713Sgirish } else { 194144961713Sgirish for (i = 0; i < size; i++) { 194244961713Sgirish if (*ap > 0x0f) 194344961713Sgirish *cp++ = digits[*ap >> 4]; 194444961713Sgirish *cp++ = digits[*ap++ & 0xf]; 194544961713Sgirish *cp++ = ':'; 194644961713Sgirish } 194744961713Sgirish } 194844961713Sgirish *--cp = 0; 194944961713Sgirish return (etherbuf); 195044961713Sgirish } 195144961713Sgirish 195244961713Sgirish #ifdef NXGE_DEBUG 195344961713Sgirish static void 195444961713Sgirish nxge_test_map_regs(p_nxge_t nxgep) 195544961713Sgirish { 195644961713Sgirish ddi_acc_handle_t cfg_handle; 195744961713Sgirish p_pci_cfg_t cfg_ptr; 195844961713Sgirish ddi_acc_handle_t dev_handle; 195944961713Sgirish char *dev_ptr; 196044961713Sgirish ddi_acc_handle_t pci_config_handle; 196144961713Sgirish uint32_t regval; 196244961713Sgirish int i; 196344961713Sgirish 196444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_test_map_regs")); 196544961713Sgirish 196644961713Sgirish dev_handle = nxgep->dev_regs->nxge_regh; 196744961713Sgirish dev_ptr = (char *)nxgep->dev_regs->nxge_regp; 196844961713Sgirish 19692e59129aSraghus if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) { 197044961713Sgirish cfg_handle = nxgep->dev_regs->nxge_pciregh; 197144961713Sgirish cfg_ptr = (void *)nxgep->dev_regs->nxge_pciregp; 197244961713Sgirish 197344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 197459ac0c16Sdavemq "Neptune PCI regp cfg_ptr 0x%llx", (char *)cfg_ptr)); 197544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 197659ac0c16Sdavemq "Neptune PCI cfg_ptr vendor id ptr 0x%llx", 197759ac0c16Sdavemq &cfg_ptr->vendorid)); 197844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 197959ac0c16Sdavemq "\tvendorid 0x%x devid 0x%x", 198059ac0c16Sdavemq NXGE_PIO_READ16(cfg_handle, &cfg_ptr->vendorid, 0), 198159ac0c16Sdavemq NXGE_PIO_READ16(cfg_handle, &cfg_ptr->devid, 0))); 198244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 198359ac0c16Sdavemq "PCI BAR: base 0x%x base14 0x%x base 18 0x%x " 198459ac0c16Sdavemq "bar1c 0x%x", 1985*86ef0a63SRichard Lowe NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base, 0), 198659ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base14, 0), 198759ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base18, 0), 198859ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base1c, 0))); 198944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 199059ac0c16Sdavemq "\nNeptune PCI BAR: base20 0x%x base24 0x%x " 199159ac0c16Sdavemq "base 28 0x%x bar2c 0x%x\n", 199259ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base20, 0), 199359ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base24, 0), 199459ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base28, 0), 199559ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base2c, 0))); 199644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 199759ac0c16Sdavemq "\nNeptune PCI BAR: base30 0x%x\n", 199859ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base30, 0))); 199944961713Sgirish 200044961713Sgirish cfg_handle = nxgep->dev_regs->nxge_pciregh; 200144961713Sgirish cfg_ptr = (void *)nxgep->dev_regs->nxge_pciregp; 200244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 200359ac0c16Sdavemq "first 0x%llx second 0x%llx third 0x%llx " 200459ac0c16Sdavemq "last 0x%llx ", 200559ac0c16Sdavemq NXGE_PIO_READ64(dev_handle, 2006*86ef0a63SRichard Lowe (uint64_t *)(dev_ptr + 0), 0), 200759ac0c16Sdavemq NXGE_PIO_READ64(dev_handle, 2008*86ef0a63SRichard Lowe (uint64_t *)(dev_ptr + 8), 0), 200959ac0c16Sdavemq NXGE_PIO_READ64(dev_handle, 201059ac0c16Sdavemq (uint64_t *)(dev_ptr + 16), 0), 201159ac0c16Sdavemq NXGE_PIO_READ64(cfg_handle, 201259ac0c16Sdavemq (uint64_t *)(dev_ptr + 24), 0))); 201344961713Sgirish } 201444961713Sgirish } 201544961713Sgirish 201644961713Sgirish #endif 201744961713Sgirish 201844961713Sgirish static void 201944961713Sgirish nxge_suspend(p_nxge_t nxgep) 202044961713Sgirish { 202144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_suspend")); 202244961713Sgirish 202344961713Sgirish nxge_intrs_disable(nxgep); 202444961713Sgirish nxge_destroy_dev(nxgep); 202544961713Sgirish 202644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_suspend")); 202744961713Sgirish } 202844961713Sgirish 202944961713Sgirish static nxge_status_t 203044961713Sgirish nxge_resume(p_nxge_t nxgep) 203144961713Sgirish { 203244961713Sgirish nxge_status_t status = NXGE_OK; 203344961713Sgirish 203444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_resume")); 203544961713Sgirish 203691c98b31Sjoycey nxgep->suspended = DDI_RESUME; 203791c98b31Sjoycey (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 203891c98b31Sjoycey (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_START); 203991c98b31Sjoycey (void) nxge_txdma_hw_mode(nxgep, NXGE_DMA_START); 204091c98b31Sjoycey (void) nxge_rx_mac_enable(nxgep); 204191c98b31Sjoycey (void) nxge_tx_mac_enable(nxgep); 204291c98b31Sjoycey nxge_intrs_enable(nxgep); 204344961713Sgirish nxgep->suspended = 0; 204444961713Sgirish 204544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 20464045d941Ssowmini "<== nxge_resume status = 0x%x", status)); 204744961713Sgirish return (status); 204844961713Sgirish } 204944961713Sgirish 205044961713Sgirish static nxge_status_t 205144961713Sgirish nxge_setup_dev(p_nxge_t nxgep) 205244961713Sgirish { 205344961713Sgirish nxge_status_t status = NXGE_OK; 205444961713Sgirish 205544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_setup_dev port %d", 205659ac0c16Sdavemq nxgep->mac.portnum)); 205744961713Sgirish 205844961713Sgirish status = nxge_link_init(nxgep); 205914ea4bb7Ssd 206014ea4bb7Ssd if (fm_check_acc_handle(nxgep->dev_regs->nxge_regh) != DDI_FM_OK) { 206114ea4bb7Ssd NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 20624045d941Ssowmini "port%d Bad register acc handle", nxgep->mac.portnum)); 206314ea4bb7Ssd status = NXGE_ERROR; 206414ea4bb7Ssd } 206514ea4bb7Ssd 206644961713Sgirish if (status != NXGE_OK) { 206744961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 20684045d941Ssowmini " nxge_setup_dev status " 20694045d941Ssowmini "(xcvr init 0x%08x)", status)); 207044961713Sgirish goto nxge_setup_dev_exit; 207144961713Sgirish } 207244961713Sgirish 207344961713Sgirish nxge_setup_dev_exit: 207444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 20754045d941Ssowmini "<== nxge_setup_dev port %d status = 0x%08x", 20764045d941Ssowmini nxgep->mac.portnum, status)); 207744961713Sgirish 207844961713Sgirish return (status); 207944961713Sgirish } 208044961713Sgirish 208144961713Sgirish static void 208244961713Sgirish nxge_destroy_dev(p_nxge_t nxgep) 208344961713Sgirish { 208444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_dev")); 208544961713Sgirish 208644961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 208744961713Sgirish 208844961713Sgirish (void) nxge_hw_stop(nxgep); 208944961713Sgirish 209044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_dev")); 209144961713Sgirish } 209244961713Sgirish 209344961713Sgirish static nxge_status_t 209444961713Sgirish nxge_setup_system_dma_pages(p_nxge_t nxgep) 209544961713Sgirish { 2096*86ef0a63SRichard Lowe int ddi_status = DDI_SUCCESS; 2097*86ef0a63SRichard Lowe uint_t count; 2098*86ef0a63SRichard Lowe ddi_dma_cookie_t cookie; 2099*86ef0a63SRichard Lowe uint_t iommu_pagesize; 210044961713Sgirish nxge_status_t status = NXGE_OK; 210144961713Sgirish 2102678453a8Sspeer NXGE_ERROR_MSG((nxgep, DDI_CTL, "==> nxge_setup_system_dma_pages")); 210344961713Sgirish nxgep->sys_page_sz = ddi_ptob(nxgep->dip, (ulong_t)1); 210444961713Sgirish if (nxgep->niu_type != N2_NIU) { 210544961713Sgirish iommu_pagesize = dvma_pagesize(nxgep->dip); 210644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 21074045d941Ssowmini " nxge_setup_system_dma_pages: page %d (ddi_ptob %d) " 21084045d941Ssowmini " default_block_size %d iommu_pagesize %d", 21094045d941Ssowmini nxgep->sys_page_sz, 21104045d941Ssowmini ddi_ptob(nxgep->dip, (ulong_t)1), 21114045d941Ssowmini nxgep->rx_default_block_size, 21124045d941Ssowmini iommu_pagesize)); 211344961713Sgirish 211444961713Sgirish if (iommu_pagesize != 0) { 211544961713Sgirish if (nxgep->sys_page_sz == iommu_pagesize) { 211644961713Sgirish if (iommu_pagesize > 0x4000) 211744961713Sgirish nxgep->sys_page_sz = 0x4000; 211844961713Sgirish } else { 211944961713Sgirish if (nxgep->sys_page_sz > iommu_pagesize) 212044961713Sgirish nxgep->sys_page_sz = iommu_pagesize; 212144961713Sgirish } 212244961713Sgirish } 212344961713Sgirish } 212444961713Sgirish nxgep->sys_page_mask = ~(nxgep->sys_page_sz - 1); 212544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 21264045d941Ssowmini "==> nxge_setup_system_dma_pages: page %d (ddi_ptob %d) " 21274045d941Ssowmini "default_block_size %d page mask %d", 21284045d941Ssowmini nxgep->sys_page_sz, 21294045d941Ssowmini ddi_ptob(nxgep->dip, (ulong_t)1), 21304045d941Ssowmini nxgep->rx_default_block_size, 21314045d941Ssowmini nxgep->sys_page_mask)); 213244961713Sgirish 213344961713Sgirish 213444961713Sgirish switch (nxgep->sys_page_sz) { 213544961713Sgirish default: 213644961713Sgirish nxgep->sys_page_sz = 0x1000; 213744961713Sgirish nxgep->sys_page_mask = ~(nxgep->sys_page_sz - 1); 213844961713Sgirish nxgep->rx_default_block_size = 0x1000; 213944961713Sgirish nxgep->rx_bksize_code = RBR_BKSIZE_4K; 214044961713Sgirish break; 214144961713Sgirish case 0x1000: 214244961713Sgirish nxgep->rx_default_block_size = 0x1000; 214344961713Sgirish nxgep->rx_bksize_code = RBR_BKSIZE_4K; 214444961713Sgirish break; 214544961713Sgirish case 0x2000: 214644961713Sgirish nxgep->rx_default_block_size = 0x2000; 214744961713Sgirish nxgep->rx_bksize_code = RBR_BKSIZE_8K; 214844961713Sgirish break; 214944961713Sgirish case 0x4000: 215044961713Sgirish nxgep->rx_default_block_size = 0x4000; 215144961713Sgirish nxgep->rx_bksize_code = RBR_BKSIZE_16K; 215244961713Sgirish break; 215344961713Sgirish case 0x8000: 215444961713Sgirish nxgep->rx_default_block_size = 0x8000; 215544961713Sgirish nxgep->rx_bksize_code = RBR_BKSIZE_32K; 215644961713Sgirish break; 215744961713Sgirish } 215844961713Sgirish 215944961713Sgirish #ifndef USE_RX_BIG_BUF 216044961713Sgirish nxge_rx_dma_attr.dma_attr_align = nxgep->sys_page_sz; 216144961713Sgirish #else 216244961713Sgirish nxgep->rx_default_block_size = 0x2000; 216344961713Sgirish nxgep->rx_bksize_code = RBR_BKSIZE_8K; 216444961713Sgirish #endif 216544961713Sgirish /* 216644961713Sgirish * Get the system DMA burst size. 216744961713Sgirish */ 216844961713Sgirish ddi_status = ddi_dma_alloc_handle(nxgep->dip, &nxge_tx_dma_attr, 21694045d941Ssowmini DDI_DMA_DONTWAIT, 0, 21704045d941Ssowmini &nxgep->dmasparehandle); 217144961713Sgirish if (ddi_status != DDI_SUCCESS) { 217244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 21734045d941Ssowmini "ddi_dma_alloc_handle: failed " 21744045d941Ssowmini " status 0x%x", ddi_status)); 217544961713Sgirish goto nxge_get_soft_properties_exit; 217644961713Sgirish } 217744961713Sgirish 217844961713Sgirish ddi_status = ddi_dma_addr_bind_handle(nxgep->dmasparehandle, NULL, 21794045d941Ssowmini (caddr_t)nxgep->dmasparehandle, 21804045d941Ssowmini sizeof (nxgep->dmasparehandle), 21814045d941Ssowmini DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 21824045d941Ssowmini DDI_DMA_DONTWAIT, 0, 21834045d941Ssowmini &cookie, &count); 218444961713Sgirish if (ddi_status != DDI_DMA_MAPPED) { 218544961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 21864045d941Ssowmini "Binding spare handle to find system" 21874045d941Ssowmini " burstsize failed.")); 218844961713Sgirish ddi_status = DDI_FAILURE; 218944961713Sgirish goto nxge_get_soft_properties_fail1; 219044961713Sgirish } 219144961713Sgirish 219244961713Sgirish nxgep->sys_burst_sz = ddi_dma_burstsizes(nxgep->dmasparehandle); 219344961713Sgirish (void) ddi_dma_unbind_handle(nxgep->dmasparehandle); 219444961713Sgirish 219544961713Sgirish nxge_get_soft_properties_fail1: 219644961713Sgirish ddi_dma_free_handle(&nxgep->dmasparehandle); 219744961713Sgirish 219844961713Sgirish nxge_get_soft_properties_exit: 219944961713Sgirish 220044961713Sgirish if (ddi_status != DDI_SUCCESS) 220144961713Sgirish status |= (NXGE_ERROR | NXGE_DDI_FAILED); 220244961713Sgirish 220344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 22044045d941Ssowmini "<== nxge_setup_system_dma_pages status = 0x%08x", status)); 220544961713Sgirish return (status); 220644961713Sgirish } 220744961713Sgirish 220844961713Sgirish static nxge_status_t 220944961713Sgirish nxge_alloc_mem_pool(p_nxge_t nxgep) 221044961713Sgirish { 221144961713Sgirish nxge_status_t status = NXGE_OK; 221244961713Sgirish 221344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_alloc_mem_pool")); 221444961713Sgirish 221544961713Sgirish status = nxge_alloc_rx_mem_pool(nxgep); 221644961713Sgirish if (status != NXGE_OK) { 221744961713Sgirish return (NXGE_ERROR); 221844961713Sgirish } 221944961713Sgirish 222044961713Sgirish status = nxge_alloc_tx_mem_pool(nxgep); 222144961713Sgirish if (status != NXGE_OK) { 222244961713Sgirish nxge_free_rx_mem_pool(nxgep); 222344961713Sgirish return (NXGE_ERROR); 222444961713Sgirish } 222544961713Sgirish 222644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_alloc_mem_pool")); 222744961713Sgirish return (NXGE_OK); 222844961713Sgirish } 222944961713Sgirish 223044961713Sgirish static void 223144961713Sgirish nxge_free_mem_pool(p_nxge_t nxgep) 223244961713Sgirish { 223344961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM_CTL, "==> nxge_free_mem_pool")); 223444961713Sgirish 223544961713Sgirish nxge_free_rx_mem_pool(nxgep); 223644961713Sgirish nxge_free_tx_mem_pool(nxgep); 223744961713Sgirish 223844961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM_CTL, "<== nxge_free_mem_pool")); 223944961713Sgirish } 224044961713Sgirish 2241678453a8Sspeer nxge_status_t 224244961713Sgirish nxge_alloc_rx_mem_pool(p_nxge_t nxgep) 224344961713Sgirish { 2244678453a8Sspeer uint32_t rdc_max; 224544961713Sgirish p_nxge_dma_pt_cfg_t p_all_cfgp; 224644961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 224744961713Sgirish p_nxge_dma_pool_t dma_poolp; 224844961713Sgirish p_nxge_dma_common_t *dma_buf_p; 224944961713Sgirish p_nxge_dma_pool_t dma_cntl_poolp; 225044961713Sgirish p_nxge_dma_common_t *dma_cntl_p; 2251*86ef0a63SRichard Lowe uint32_t *num_chunks; /* per dma */ 225244961713Sgirish nxge_status_t status = NXGE_OK; 225344961713Sgirish 225444961713Sgirish uint32_t nxge_port_rbr_size; 225544961713Sgirish uint32_t nxge_port_rbr_spare_size; 225644961713Sgirish uint32_t nxge_port_rcr_size; 2257678453a8Sspeer uint32_t rx_cntl_alloc_size; 225844961713Sgirish 225944961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rx_mem_pool")); 226044961713Sgirish 226144961713Sgirish p_all_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 226244961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_all_cfgp->hw_config; 2263678453a8Sspeer rdc_max = NXGE_MAX_RDCS; 226444961713Sgirish 226544961713Sgirish /* 2266678453a8Sspeer * Allocate memory for the common DMA data structures. 226744961713Sgirish */ 226844961713Sgirish dma_poolp = (p_nxge_dma_pool_t)KMEM_ZALLOC(sizeof (nxge_dma_pool_t), 22694045d941Ssowmini KM_SLEEP); 227044961713Sgirish dma_buf_p = (p_nxge_dma_common_t *)KMEM_ZALLOC( 22714045d941Ssowmini sizeof (p_nxge_dma_common_t) * rdc_max, KM_SLEEP); 227244961713Sgirish 227344961713Sgirish dma_cntl_poolp = (p_nxge_dma_pool_t) 22744045d941Ssowmini KMEM_ZALLOC(sizeof (nxge_dma_pool_t), KM_SLEEP); 227544961713Sgirish dma_cntl_p = (p_nxge_dma_common_t *)KMEM_ZALLOC( 22764045d941Ssowmini sizeof (p_nxge_dma_common_t) * rdc_max, KM_SLEEP); 227744961713Sgirish 227844961713Sgirish num_chunks = (uint32_t *)KMEM_ZALLOC( 22794045d941Ssowmini sizeof (uint32_t) * rdc_max, KM_SLEEP); 228044961713Sgirish 228144961713Sgirish /* 2282678453a8Sspeer * Assume that each DMA channel will be configured with 2283678453a8Sspeer * the default block size. 2284678453a8Sspeer * rbr block counts are modulo the batch count (16). 228544961713Sgirish */ 228644961713Sgirish nxge_port_rbr_size = p_all_cfgp->rbr_size; 228744961713Sgirish nxge_port_rcr_size = p_all_cfgp->rcr_size; 228844961713Sgirish 228944961713Sgirish if (!nxge_port_rbr_size) { 229044961713Sgirish nxge_port_rbr_size = NXGE_RBR_RBB_DEFAULT; 229144961713Sgirish } 229244961713Sgirish if (nxge_port_rbr_size % NXGE_RXDMA_POST_BATCH) { 229344961713Sgirish nxge_port_rbr_size = (NXGE_RXDMA_POST_BATCH * 22944045d941Ssowmini (nxge_port_rbr_size / NXGE_RXDMA_POST_BATCH + 1)); 229544961713Sgirish } 229644961713Sgirish 229744961713Sgirish p_all_cfgp->rbr_size = nxge_port_rbr_size; 229844961713Sgirish nxge_port_rbr_spare_size = nxge_rbr_spare_size; 229944961713Sgirish 230044961713Sgirish if (nxge_port_rbr_spare_size % NXGE_RXDMA_POST_BATCH) { 230144961713Sgirish nxge_port_rbr_spare_size = (NXGE_RXDMA_POST_BATCH * 23024045d941Ssowmini (nxge_port_rbr_spare_size / NXGE_RXDMA_POST_BATCH + 1)); 230344961713Sgirish } 230430ac2e7bSml if (nxge_port_rbr_size > RBR_DEFAULT_MAX_BLKS) { 230530ac2e7bSml NXGE_DEBUG_MSG((nxgep, MEM_CTL, 230630ac2e7bSml "nxge_alloc_rx_mem_pool: RBR size too high %d, " 230730ac2e7bSml "set to default %d", 230830ac2e7bSml nxge_port_rbr_size, RBR_DEFAULT_MAX_BLKS)); 230930ac2e7bSml nxge_port_rbr_size = RBR_DEFAULT_MAX_BLKS; 231030ac2e7bSml } 231130ac2e7bSml if (nxge_port_rcr_size > RCR_DEFAULT_MAX) { 231230ac2e7bSml NXGE_DEBUG_MSG((nxgep, MEM_CTL, 231330ac2e7bSml "nxge_alloc_rx_mem_pool: RCR too high %d, " 231430ac2e7bSml "set to default %d", 231530ac2e7bSml nxge_port_rcr_size, RCR_DEFAULT_MAX)); 231630ac2e7bSml nxge_port_rcr_size = RCR_DEFAULT_MAX; 231730ac2e7bSml } 231844961713Sgirish 231944961713Sgirish /* 232044961713Sgirish * N2/NIU has limitation on the descriptor sizes (contiguous 232144961713Sgirish * memory allocation on data buffers to 4M (contig_mem_alloc) 232244961713Sgirish * and little endian for control buffers (must use the ddi/dki mem alloc 232344961713Sgirish * function). 232444961713Sgirish */ 232544961713Sgirish #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 232644961713Sgirish if (nxgep->niu_type == N2_NIU) { 232744961713Sgirish nxge_port_rbr_spare_size = 0; 232844961713Sgirish if ((nxge_port_rbr_size > NXGE_NIU_CONTIG_RBR_MAX) || 23294045d941Ssowmini (!ISP2(nxge_port_rbr_size))) { 233044961713Sgirish nxge_port_rbr_size = NXGE_NIU_CONTIG_RBR_MAX; 233144961713Sgirish } 233244961713Sgirish if ((nxge_port_rcr_size > NXGE_NIU_CONTIG_RCR_MAX) || 23334045d941Ssowmini (!ISP2(nxge_port_rcr_size))) { 233444961713Sgirish nxge_port_rcr_size = NXGE_NIU_CONTIG_RCR_MAX; 233544961713Sgirish } 233644961713Sgirish } 233744961713Sgirish #endif 233844961713Sgirish 233944961713Sgirish /* 234044961713Sgirish * Addresses of receive block ring, receive completion ring and the 234144961713Sgirish * mailbox must be all cache-aligned (64 bytes). 234244961713Sgirish */ 234344961713Sgirish rx_cntl_alloc_size = nxge_port_rbr_size + nxge_port_rbr_spare_size; 234444961713Sgirish rx_cntl_alloc_size *= (sizeof (rx_desc_t)); 234544961713Sgirish rx_cntl_alloc_size += (sizeof (rcr_entry_t) * nxge_port_rcr_size); 234644961713Sgirish rx_cntl_alloc_size += sizeof (rxdma_mailbox_t); 234744961713Sgirish 234844961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_alloc_rx_mem_pool: " 23494045d941Ssowmini "nxge_port_rbr_size = %d nxge_port_rbr_spare_size = %d " 23504045d941Ssowmini "nxge_port_rcr_size = %d " 23514045d941Ssowmini "rx_cntl_alloc_size = %d", 23524045d941Ssowmini nxge_port_rbr_size, nxge_port_rbr_spare_size, 23534045d941Ssowmini nxge_port_rcr_size, 23544045d941Ssowmini rx_cntl_alloc_size)); 235544961713Sgirish 235644961713Sgirish #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 235744961713Sgirish if (nxgep->niu_type == N2_NIU) { 2358678453a8Sspeer uint32_t rx_buf_alloc_size = (nxgep->rx_default_block_size * 2359678453a8Sspeer (nxge_port_rbr_size + nxge_port_rbr_spare_size)); 2360678453a8Sspeer 236144961713Sgirish if (!ISP2(rx_buf_alloc_size)) { 236244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 23634045d941Ssowmini "==> nxge_alloc_rx_mem_pool: " 23644045d941Ssowmini " must be power of 2")); 236544961713Sgirish status |= (NXGE_ERROR | NXGE_DDI_FAILED); 236644961713Sgirish goto nxge_alloc_rx_mem_pool_exit; 236744961713Sgirish } 236844961713Sgirish 236944961713Sgirish if (rx_buf_alloc_size > (1 << 22)) { 237044961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 23714045d941Ssowmini "==> nxge_alloc_rx_mem_pool: " 23724045d941Ssowmini " limit size to 4M")); 237344961713Sgirish status |= (NXGE_ERROR | NXGE_DDI_FAILED); 237444961713Sgirish goto nxge_alloc_rx_mem_pool_exit; 237544961713Sgirish } 237644961713Sgirish 237744961713Sgirish if (rx_cntl_alloc_size < 0x2000) { 237844961713Sgirish rx_cntl_alloc_size = 0x2000; 237944961713Sgirish } 238044961713Sgirish } 238144961713Sgirish #endif 238244961713Sgirish nxgep->nxge_port_rbr_size = nxge_port_rbr_size; 238344961713Sgirish nxgep->nxge_port_rcr_size = nxge_port_rcr_size; 2384678453a8Sspeer nxgep->nxge_port_rbr_spare_size = nxge_port_rbr_spare_size; 2385678453a8Sspeer nxgep->nxge_port_rx_cntl_alloc_size = rx_cntl_alloc_size; 238644961713Sgirish 2387678453a8Sspeer dma_poolp->ndmas = p_cfgp->max_rdcs; 238844961713Sgirish dma_poolp->num_chunks = num_chunks; 238944961713Sgirish dma_poolp->buf_allocated = B_TRUE; 239044961713Sgirish nxgep->rx_buf_pool_p = dma_poolp; 239144961713Sgirish dma_poolp->dma_buf_pool_p = dma_buf_p; 239244961713Sgirish 2393678453a8Sspeer dma_cntl_poolp->ndmas = p_cfgp->max_rdcs; 239444961713Sgirish dma_cntl_poolp->buf_allocated = B_TRUE; 239544961713Sgirish nxgep->rx_cntl_pool_p = dma_cntl_poolp; 239644961713Sgirish dma_cntl_poolp->dma_buf_pool_p = dma_cntl_p; 239744961713Sgirish 2398678453a8Sspeer /* Allocate the receive rings, too. */ 2399678453a8Sspeer nxgep->rx_rbr_rings = 24004045d941Ssowmini KMEM_ZALLOC(sizeof (rx_rbr_rings_t), KM_SLEEP); 2401678453a8Sspeer nxgep->rx_rbr_rings->rbr_rings = 24024045d941Ssowmini KMEM_ZALLOC(sizeof (p_rx_rbr_ring_t) * rdc_max, KM_SLEEP); 2403678453a8Sspeer nxgep->rx_rcr_rings = 24044045d941Ssowmini KMEM_ZALLOC(sizeof (rx_rcr_rings_t), KM_SLEEP); 2405678453a8Sspeer nxgep->rx_rcr_rings->rcr_rings = 24064045d941Ssowmini KMEM_ZALLOC(sizeof (p_rx_rcr_ring_t) * rdc_max, KM_SLEEP); 2407678453a8Sspeer nxgep->rx_mbox_areas_p = 24084045d941Ssowmini KMEM_ZALLOC(sizeof (rx_mbox_areas_t), KM_SLEEP); 2409678453a8Sspeer nxgep->rx_mbox_areas_p->rxmbox_areas = 24104045d941Ssowmini KMEM_ZALLOC(sizeof (p_rx_mbox_t) * rdc_max, KM_SLEEP); 2411678453a8Sspeer 2412678453a8Sspeer nxgep->rx_rbr_rings->ndmas = nxgep->rx_rcr_rings->ndmas = 2413678453a8Sspeer p_cfgp->max_rdcs; 241444961713Sgirish 241544961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 24164045d941Ssowmini "<== nxge_alloc_rx_mem_pool:status 0x%08x", status)); 241744961713Sgirish 2418678453a8Sspeer nxge_alloc_rx_mem_pool_exit: 2419678453a8Sspeer return (status); 2420678453a8Sspeer } 2421678453a8Sspeer 2422678453a8Sspeer /* 2423678453a8Sspeer * nxge_alloc_rxb 2424678453a8Sspeer * 2425678453a8Sspeer * Allocate buffers for an RDC. 2426678453a8Sspeer * 2427678453a8Sspeer * Arguments: 2428*86ef0a63SRichard Lowe * nxgep 2429*86ef0a63SRichard Lowe * channel The channel to map into our kernel space. 2430678453a8Sspeer * 2431678453a8Sspeer * Notes: 2432678453a8Sspeer * 2433678453a8Sspeer * NPI function calls: 2434678453a8Sspeer * 2435678453a8Sspeer * NXGE function calls: 2436678453a8Sspeer * 2437678453a8Sspeer * Registers accessed: 2438678453a8Sspeer * 2439678453a8Sspeer * Context: 2440678453a8Sspeer * 2441678453a8Sspeer * Taking apart: 2442678453a8Sspeer * 2443678453a8Sspeer * Open questions: 2444678453a8Sspeer * 2445678453a8Sspeer */ 2446678453a8Sspeer nxge_status_t 2447678453a8Sspeer nxge_alloc_rxb( 2448678453a8Sspeer p_nxge_t nxgep, 2449678453a8Sspeer int channel) 2450678453a8Sspeer { 2451678453a8Sspeer size_t rx_buf_alloc_size; 2452678453a8Sspeer nxge_status_t status = NXGE_OK; 2453678453a8Sspeer 2454678453a8Sspeer nxge_dma_common_t **data; 2455678453a8Sspeer nxge_dma_common_t **control; 2456*86ef0a63SRichard Lowe uint32_t *num_chunks; 2457678453a8Sspeer 2458678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rbb")); 2459678453a8Sspeer 2460678453a8Sspeer /* 2461678453a8Sspeer * Allocate memory for the receive buffers and descriptor rings. 2462678453a8Sspeer * Replace these allocation functions with the interface functions 2463678453a8Sspeer * provided by the partition manager if/when they are available. 2464678453a8Sspeer */ 2465678453a8Sspeer 2466678453a8Sspeer /* 2467678453a8Sspeer * Allocate memory for the receive buffer blocks. 2468678453a8Sspeer */ 2469678453a8Sspeer rx_buf_alloc_size = (nxgep->rx_default_block_size * 24704045d941Ssowmini (nxgep->nxge_port_rbr_size + nxgep->nxge_port_rbr_spare_size)); 2471678453a8Sspeer 2472678453a8Sspeer data = &nxgep->rx_buf_pool_p->dma_buf_pool_p[channel]; 2473678453a8Sspeer num_chunks = &nxgep->rx_buf_pool_p->num_chunks[channel]; 2474678453a8Sspeer 2475678453a8Sspeer if ((status = nxge_alloc_rx_buf_dma( 2476678453a8Sspeer nxgep, channel, data, rx_buf_alloc_size, 2477678453a8Sspeer nxgep->rx_default_block_size, num_chunks)) != NXGE_OK) { 2478678453a8Sspeer return (status); 247944961713Sgirish } 248044961713Sgirish 2481678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_alloc_rxb(): " 2482678453a8Sspeer "dma %d dma_buf_p %llx &dma_buf_p %llx", channel, *data, data)); 2483678453a8Sspeer 2484678453a8Sspeer /* 2485678453a8Sspeer * Allocate memory for descriptor rings and mailbox. 2486678453a8Sspeer */ 2487678453a8Sspeer control = &nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel]; 2488678453a8Sspeer 2489678453a8Sspeer if ((status = nxge_alloc_rx_cntl_dma( 2490678453a8Sspeer nxgep, channel, control, nxgep->nxge_port_rx_cntl_alloc_size)) 2491678453a8Sspeer != NXGE_OK) { 2492678453a8Sspeer nxge_free_rx_cntl_dma(nxgep, *control); 2493678453a8Sspeer (*data)->buf_alloc_state |= BUF_ALLOCATED_WAIT_FREE; 2494678453a8Sspeer nxge_free_rx_buf_dma(nxgep, *data, *num_chunks); 2495678453a8Sspeer return (status); 2496678453a8Sspeer } 249744961713Sgirish 249844961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 2499678453a8Sspeer "<== nxge_alloc_rx_mem_pool:status 0x%08x", status)); 250044961713Sgirish 250144961713Sgirish return (status); 250244961713Sgirish } 250344961713Sgirish 2504678453a8Sspeer void 2505678453a8Sspeer nxge_free_rxb( 2506678453a8Sspeer p_nxge_t nxgep, 2507678453a8Sspeer int channel) 2508678453a8Sspeer { 2509678453a8Sspeer nxge_dma_common_t *data; 2510678453a8Sspeer nxge_dma_common_t *control; 2511*86ef0a63SRichard Lowe uint32_t num_chunks; 2512678453a8Sspeer 2513678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rbb")); 2514678453a8Sspeer 2515678453a8Sspeer data = nxgep->rx_buf_pool_p->dma_buf_pool_p[channel]; 2516678453a8Sspeer num_chunks = nxgep->rx_buf_pool_p->num_chunks[channel]; 2517678453a8Sspeer nxge_free_rx_buf_dma(nxgep, data, num_chunks); 2518678453a8Sspeer 2519678453a8Sspeer nxgep->rx_buf_pool_p->dma_buf_pool_p[channel] = 0; 2520678453a8Sspeer nxgep->rx_buf_pool_p->num_chunks[channel] = 0; 2521678453a8Sspeer 2522678453a8Sspeer control = nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel]; 2523678453a8Sspeer nxge_free_rx_cntl_dma(nxgep, control); 2524678453a8Sspeer 2525678453a8Sspeer nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel] = 0; 2526678453a8Sspeer 2527678453a8Sspeer KMEM_FREE(data, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK); 2528678453a8Sspeer KMEM_FREE(control, sizeof (nxge_dma_common_t)); 2529678453a8Sspeer 2530678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_alloc_rbb")); 2531678453a8Sspeer } 2532678453a8Sspeer 253344961713Sgirish static void 253444961713Sgirish nxge_free_rx_mem_pool(p_nxge_t nxgep) 253544961713Sgirish { 2536678453a8Sspeer int rdc_max = NXGE_MAX_RDCS; 253744961713Sgirish 253844961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_free_rx_mem_pool")); 253944961713Sgirish 2540678453a8Sspeer if (!nxgep->rx_buf_pool_p || !nxgep->rx_buf_pool_p->buf_allocated) { 254144961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 25424045d941Ssowmini "<== nxge_free_rx_mem_pool " 25434045d941Ssowmini "(null rx buf pool or buf not allocated")); 254444961713Sgirish return; 254544961713Sgirish } 2546678453a8Sspeer if (!nxgep->rx_cntl_pool_p || !nxgep->rx_cntl_pool_p->buf_allocated) { 254744961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 25484045d941Ssowmini "<== nxge_free_rx_mem_pool " 25494045d941Ssowmini "(null rx cntl buf pool or cntl buf not allocated")); 255044961713Sgirish return; 255144961713Sgirish } 255244961713Sgirish 2553678453a8Sspeer KMEM_FREE(nxgep->rx_cntl_pool_p->dma_buf_pool_p, 2554678453a8Sspeer sizeof (p_nxge_dma_common_t) * rdc_max); 2555678453a8Sspeer KMEM_FREE(nxgep->rx_cntl_pool_p, sizeof (nxge_dma_pool_t)); 255644961713Sgirish 2557678453a8Sspeer KMEM_FREE(nxgep->rx_buf_pool_p->num_chunks, 2558678453a8Sspeer sizeof (uint32_t) * rdc_max); 2559678453a8Sspeer KMEM_FREE(nxgep->rx_buf_pool_p->dma_buf_pool_p, 2560678453a8Sspeer sizeof (p_nxge_dma_common_t) * rdc_max); 2561678453a8Sspeer KMEM_FREE(nxgep->rx_buf_pool_p, sizeof (nxge_dma_pool_t)); 256244961713Sgirish 2563678453a8Sspeer nxgep->rx_buf_pool_p = 0; 2564678453a8Sspeer nxgep->rx_cntl_pool_p = 0; 256544961713Sgirish 2566678453a8Sspeer KMEM_FREE(nxgep->rx_rbr_rings->rbr_rings, 2567678453a8Sspeer sizeof (p_rx_rbr_ring_t) * rdc_max); 2568678453a8Sspeer KMEM_FREE(nxgep->rx_rbr_rings, sizeof (rx_rbr_rings_t)); 2569678453a8Sspeer KMEM_FREE(nxgep->rx_rcr_rings->rcr_rings, 2570678453a8Sspeer sizeof (p_rx_rcr_ring_t) * rdc_max); 2571678453a8Sspeer KMEM_FREE(nxgep->rx_rcr_rings, sizeof (rx_rcr_rings_t)); 2572678453a8Sspeer KMEM_FREE(nxgep->rx_mbox_areas_p->rxmbox_areas, 2573678453a8Sspeer sizeof (p_rx_mbox_t) * rdc_max); 2574678453a8Sspeer KMEM_FREE(nxgep->rx_mbox_areas_p, sizeof (rx_mbox_areas_t)); 257544961713Sgirish 2576678453a8Sspeer nxgep->rx_rbr_rings = 0; 2577678453a8Sspeer nxgep->rx_rcr_rings = 0; 2578678453a8Sspeer nxgep->rx_mbox_areas_p = 0; 257944961713Sgirish 258044961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_free_rx_mem_pool")); 258144961713Sgirish } 258244961713Sgirish 258344961713Sgirish 258444961713Sgirish static nxge_status_t 258544961713Sgirish nxge_alloc_rx_buf_dma(p_nxge_t nxgep, uint16_t dma_channel, 2586*86ef0a63SRichard Lowe p_nxge_dma_common_t *dmap, 2587*86ef0a63SRichard Lowe size_t alloc_size, size_t block_size, uint32_t *num_chunks) 258844961713Sgirish { 2589*86ef0a63SRichard Lowe p_nxge_dma_common_t rx_dmap; 259044961713Sgirish nxge_status_t status = NXGE_OK; 259144961713Sgirish size_t total_alloc_size; 259244961713Sgirish size_t allocated = 0; 259344961713Sgirish int i, size_index, array_size; 2594678453a8Sspeer boolean_t use_kmem_alloc = B_FALSE; 259544961713Sgirish 259644961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rx_buf_dma")); 259744961713Sgirish 259844961713Sgirish rx_dmap = (p_nxge_dma_common_t) 25994045d941Ssowmini KMEM_ZALLOC(sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK, 26004045d941Ssowmini KM_SLEEP); 260144961713Sgirish 260244961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 26034045d941Ssowmini " alloc_rx_buf_dma rdc %d asize %x bsize %x bbuf %llx ", 26044045d941Ssowmini dma_channel, alloc_size, block_size, dmap)); 260544961713Sgirish 260644961713Sgirish total_alloc_size = alloc_size; 260744961713Sgirish 260844961713Sgirish #if defined(RX_USE_RECLAIM_POST) 260944961713Sgirish total_alloc_size = alloc_size + alloc_size/4; 261044961713Sgirish #endif 261144961713Sgirish 261244961713Sgirish i = 0; 261344961713Sgirish size_index = 0; 261444961713Sgirish array_size = sizeof (alloc_sizes)/sizeof (size_t); 26157b26d9ffSSantwona Behera while ((size_index < array_size) && 26167b26d9ffSSantwona Behera (alloc_sizes[size_index] < alloc_size)) 26174045d941Ssowmini size_index++; 261844961713Sgirish if (size_index >= array_size) { 261944961713Sgirish size_index = array_size - 1; 262044961713Sgirish } 262144961713Sgirish 2622678453a8Sspeer /* For Neptune, use kmem_alloc if the kmem flag is set. */ 2623678453a8Sspeer if (nxgep->niu_type != N2_NIU && nxge_use_kmem_alloc) { 2624678453a8Sspeer use_kmem_alloc = B_TRUE; 2625*86ef0a63SRichard Lowe #if defined(__x86) 2626678453a8Sspeer size_index = 0; 2627678453a8Sspeer #endif 2628678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2629678453a8Sspeer "==> nxge_alloc_rx_buf_dma: " 2630678453a8Sspeer "Neptune use kmem_alloc() - size_index %d", 2631678453a8Sspeer size_index)); 2632678453a8Sspeer } 2633678453a8Sspeer 263444961713Sgirish while ((allocated < total_alloc_size) && 26354045d941Ssowmini (size_index >= 0) && (i < NXGE_DMA_BLOCK)) { 263644961713Sgirish rx_dmap[i].dma_chunk_index = i; 263744961713Sgirish rx_dmap[i].block_size = block_size; 263844961713Sgirish rx_dmap[i].alength = alloc_sizes[size_index]; 263944961713Sgirish rx_dmap[i].orig_alength = rx_dmap[i].alength; 264044961713Sgirish rx_dmap[i].nblocks = alloc_sizes[size_index] / block_size; 264144961713Sgirish rx_dmap[i].dma_channel = dma_channel; 264244961713Sgirish rx_dmap[i].contig_alloc_type = B_FALSE; 2643678453a8Sspeer rx_dmap[i].kmem_alloc_type = B_FALSE; 2644678453a8Sspeer rx_dmap[i].buf_alloc_type = DDI_MEM_ALLOC; 264544961713Sgirish 264644961713Sgirish /* 264744961713Sgirish * N2/NIU: data buffers must be contiguous as the driver 264844961713Sgirish * needs to call Hypervisor api to set up 264944961713Sgirish * logical pages. 265044961713Sgirish */ 265144961713Sgirish if ((nxgep->niu_type == N2_NIU) && (NXGE_DMA_BLOCK == 1)) { 265244961713Sgirish rx_dmap[i].contig_alloc_type = B_TRUE; 2653678453a8Sspeer rx_dmap[i].buf_alloc_type = CONTIG_MEM_ALLOC; 2654678453a8Sspeer } else if (use_kmem_alloc) { 2655678453a8Sspeer /* For Neptune, use kmem_alloc */ 2656678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2657678453a8Sspeer "==> nxge_alloc_rx_buf_dma: " 2658678453a8Sspeer "Neptune use kmem_alloc()")); 2659678453a8Sspeer rx_dmap[i].kmem_alloc_type = B_TRUE; 2660678453a8Sspeer rx_dmap[i].buf_alloc_type = KMEM_ALLOC; 266144961713Sgirish } 266244961713Sgirish 266344961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 26644045d941Ssowmini "alloc_rx_buf_dma rdc %d chunk %d bufp %llx size %x " 26654045d941Ssowmini "i %d nblocks %d alength %d", 26664045d941Ssowmini dma_channel, i, &rx_dmap[i], block_size, 26674045d941Ssowmini i, rx_dmap[i].nblocks, 26684045d941Ssowmini rx_dmap[i].alength)); 266944961713Sgirish status = nxge_dma_mem_alloc(nxgep, nxge_force_dma, 26704045d941Ssowmini &nxge_rx_dma_attr, 26714045d941Ssowmini rx_dmap[i].alength, 26724045d941Ssowmini &nxge_dev_buf_dma_acc_attr, 26734045d941Ssowmini DDI_DMA_READ | DDI_DMA_STREAMING, 26744045d941Ssowmini (p_nxge_dma_common_t)(&rx_dmap[i])); 267544961713Sgirish if (status != NXGE_OK) { 267644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2677678453a8Sspeer "nxge_alloc_rx_buf_dma: Alloc Failed: " 2678678453a8Sspeer "dma %d size_index %d size requested %d", 2679678453a8Sspeer dma_channel, 2680678453a8Sspeer size_index, 2681678453a8Sspeer rx_dmap[i].alength)); 268244961713Sgirish size_index--; 268344961713Sgirish } else { 2684678453a8Sspeer rx_dmap[i].buf_alloc_state = BUF_ALLOCATED; 2685678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2686678453a8Sspeer " nxge_alloc_rx_buf_dma DONE alloc mem: " 2687678453a8Sspeer "dma %d dma_buf_p $%p kaddrp $%p alength %d " 2688678453a8Sspeer "buf_alloc_state %d alloc_type %d", 2689678453a8Sspeer dma_channel, 2690678453a8Sspeer &rx_dmap[i], 2691678453a8Sspeer rx_dmap[i].kaddrp, 2692678453a8Sspeer rx_dmap[i].alength, 2693678453a8Sspeer rx_dmap[i].buf_alloc_state, 2694678453a8Sspeer rx_dmap[i].buf_alloc_type)); 2695678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2696678453a8Sspeer " alloc_rx_buf_dma allocated rdc %d " 2697678453a8Sspeer "chunk %d size %x dvma %x bufp %llx kaddrp $%p", 2698678453a8Sspeer dma_channel, i, rx_dmap[i].alength, 2699678453a8Sspeer rx_dmap[i].ioaddr_pp, &rx_dmap[i], 2700678453a8Sspeer rx_dmap[i].kaddrp)); 270144961713Sgirish i++; 270244961713Sgirish allocated += alloc_sizes[size_index]; 270344961713Sgirish } 270444961713Sgirish } 270544961713Sgirish 270644961713Sgirish if (allocated < total_alloc_size) { 270730ac2e7bSml NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2708678453a8Sspeer "==> nxge_alloc_rx_buf_dma: not enough for channel %d " 270930ac2e7bSml "allocated 0x%x requested 0x%x", 271030ac2e7bSml dma_channel, 271130ac2e7bSml allocated, total_alloc_size)); 271230ac2e7bSml status = NXGE_ERROR; 271344961713Sgirish goto nxge_alloc_rx_mem_fail1; 271444961713Sgirish } 271544961713Sgirish 271630ac2e7bSml NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2717678453a8Sspeer "==> nxge_alloc_rx_buf_dma: Allocated for channel %d " 271830ac2e7bSml "allocated 0x%x requested 0x%x", 271930ac2e7bSml dma_channel, 272030ac2e7bSml allocated, total_alloc_size)); 272130ac2e7bSml 272244961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 27234045d941Ssowmini " alloc_rx_buf_dma rdc %d allocated %d chunks", 27244045d941Ssowmini dma_channel, i)); 272544961713Sgirish *num_chunks = i; 272644961713Sgirish *dmap = rx_dmap; 272744961713Sgirish 272844961713Sgirish goto nxge_alloc_rx_mem_exit; 272944961713Sgirish 273044961713Sgirish nxge_alloc_rx_mem_fail1: 273144961713Sgirish KMEM_FREE(rx_dmap, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK); 273244961713Sgirish 273344961713Sgirish nxge_alloc_rx_mem_exit: 273444961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 27354045d941Ssowmini "<== nxge_alloc_rx_buf_dma status 0x%08x", status)); 273644961713Sgirish 273744961713Sgirish return (status); 273844961713Sgirish } 273944961713Sgirish 274044961713Sgirish /*ARGSUSED*/ 274144961713Sgirish static void 274244961713Sgirish nxge_free_rx_buf_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap, 274344961713Sgirish uint32_t num_chunks) 274444961713Sgirish { 274544961713Sgirish int i; 274644961713Sgirish 274744961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 27484045d941Ssowmini "==> nxge_free_rx_buf_dma: # of chunks %d", num_chunks)); 274944961713Sgirish 2750678453a8Sspeer if (dmap == 0) 2751678453a8Sspeer return; 2752678453a8Sspeer 275344961713Sgirish for (i = 0; i < num_chunks; i++) { 275444961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 27554045d941Ssowmini "==> nxge_free_rx_buf_dma: chunk %d dmap 0x%llx", 27564045d941Ssowmini i, dmap)); 2757678453a8Sspeer nxge_dma_free_rx_data_buf(dmap++); 275844961713Sgirish } 275944961713Sgirish 276044961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_free_rx_buf_dma")); 276144961713Sgirish } 276244961713Sgirish 276344961713Sgirish /*ARGSUSED*/ 276444961713Sgirish static nxge_status_t 276544961713Sgirish nxge_alloc_rx_cntl_dma(p_nxge_t nxgep, uint16_t dma_channel, 276644961713Sgirish p_nxge_dma_common_t *dmap, size_t size) 276744961713Sgirish { 2768*86ef0a63SRichard Lowe p_nxge_dma_common_t rx_dmap; 276944961713Sgirish nxge_status_t status = NXGE_OK; 277044961713Sgirish 277144961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rx_cntl_dma")); 277244961713Sgirish 277344961713Sgirish rx_dmap = (p_nxge_dma_common_t) 27744045d941Ssowmini KMEM_ZALLOC(sizeof (nxge_dma_common_t), KM_SLEEP); 277544961713Sgirish 277644961713Sgirish rx_dmap->contig_alloc_type = B_FALSE; 2777678453a8Sspeer rx_dmap->kmem_alloc_type = B_FALSE; 277844961713Sgirish 277944961713Sgirish status = nxge_dma_mem_alloc(nxgep, nxge_force_dma, 27804045d941Ssowmini &nxge_desc_dma_attr, 27814045d941Ssowmini size, 27824045d941Ssowmini &nxge_dev_desc_dma_acc_attr, 27834045d941Ssowmini DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 27844045d941Ssowmini rx_dmap); 278544961713Sgirish if (status != NXGE_OK) { 278644961713Sgirish goto nxge_alloc_rx_cntl_dma_fail1; 278744961713Sgirish } 278844961713Sgirish 278944961713Sgirish *dmap = rx_dmap; 279044961713Sgirish goto nxge_alloc_rx_cntl_dma_exit; 279144961713Sgirish 279244961713Sgirish nxge_alloc_rx_cntl_dma_fail1: 279344961713Sgirish KMEM_FREE(rx_dmap, sizeof (nxge_dma_common_t)); 279444961713Sgirish 279544961713Sgirish nxge_alloc_rx_cntl_dma_exit: 279644961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 27974045d941Ssowmini "<== nxge_alloc_rx_cntl_dma status 0x%08x", status)); 279844961713Sgirish 2799678453a8Sspeer return (status); 2800678453a8Sspeer } 2801678453a8Sspeer 2802678453a8Sspeer /*ARGSUSED*/ 2803678453a8Sspeer static void 2804678453a8Sspeer nxge_free_rx_cntl_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap) 2805678453a8Sspeer { 2806678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_free_rx_cntl_dma")); 2807678453a8Sspeer 2808678453a8Sspeer if (dmap == 0) 2809678453a8Sspeer return; 2810678453a8Sspeer 2811678453a8Sspeer nxge_dma_mem_free(dmap); 2812678453a8Sspeer 2813678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_free_rx_cntl_dma")); 2814678453a8Sspeer } 2815678453a8Sspeer 2816678453a8Sspeer typedef struct { 2817678453a8Sspeer size_t tx_size; 2818678453a8Sspeer size_t cr_size; 2819678453a8Sspeer size_t threshhold; 2820678453a8Sspeer } nxge_tdc_sizes_t; 2821678453a8Sspeer 2822678453a8Sspeer static 2823678453a8Sspeer nxge_status_t 2824678453a8Sspeer nxge_tdc_sizes( 2825678453a8Sspeer nxge_t *nxgep, 2826678453a8Sspeer nxge_tdc_sizes_t *sizes) 2827678453a8Sspeer { 2828678453a8Sspeer uint32_t threshhold; /* The bcopy() threshhold */ 2829678453a8Sspeer size_t tx_size; /* Transmit buffer size */ 2830678453a8Sspeer size_t cr_size; /* Completion ring size */ 2831678453a8Sspeer 2832678453a8Sspeer /* 2833678453a8Sspeer * Assume that each DMA channel will be configured with the 2834678453a8Sspeer * default transmit buffer size for copying transmit data. 2835678453a8Sspeer * (If a packet is bigger than this, it will not be copied.) 2836678453a8Sspeer */ 2837678453a8Sspeer if (nxgep->niu_type == N2_NIU) { 2838678453a8Sspeer threshhold = TX_BCOPY_SIZE; 2839678453a8Sspeer } else { 2840678453a8Sspeer threshhold = nxge_bcopy_thresh; 2841678453a8Sspeer } 2842678453a8Sspeer tx_size = nxge_tx_ring_size * threshhold; 2843678453a8Sspeer 2844678453a8Sspeer cr_size = nxge_tx_ring_size * sizeof (tx_desc_t); 2845678453a8Sspeer cr_size += sizeof (txdma_mailbox_t); 2846678453a8Sspeer 2847678453a8Sspeer #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 2848678453a8Sspeer if (nxgep->niu_type == N2_NIU) { 2849678453a8Sspeer if (!ISP2(tx_size)) { 2850678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 28514045d941Ssowmini "==> nxge_tdc_sizes: Tx size" 28524045d941Ssowmini " must be power of 2")); 2853678453a8Sspeer return (NXGE_ERROR); 2854678453a8Sspeer } 2855678453a8Sspeer 2856678453a8Sspeer if (tx_size > (1 << 22)) { 2857678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 28584045d941Ssowmini "==> nxge_tdc_sizes: Tx size" 28594045d941Ssowmini " limited to 4M")); 2860678453a8Sspeer return (NXGE_ERROR); 2861678453a8Sspeer } 2862678453a8Sspeer 2863678453a8Sspeer if (cr_size < 0x2000) 2864678453a8Sspeer cr_size = 0x2000; 2865678453a8Sspeer } 2866678453a8Sspeer #endif 2867678453a8Sspeer 2868678453a8Sspeer sizes->threshhold = threshhold; 2869678453a8Sspeer sizes->tx_size = tx_size; 2870678453a8Sspeer sizes->cr_size = cr_size; 2871678453a8Sspeer 2872678453a8Sspeer return (NXGE_OK); 2873678453a8Sspeer } 2874678453a8Sspeer /* 2875678453a8Sspeer * nxge_alloc_txb 2876678453a8Sspeer * 2877678453a8Sspeer * Allocate buffers for an TDC. 2878678453a8Sspeer * 2879678453a8Sspeer * Arguments: 2880*86ef0a63SRichard Lowe * nxgep 2881*86ef0a63SRichard Lowe * channel The channel to map into our kernel space. 2882678453a8Sspeer * 2883678453a8Sspeer * Notes: 2884678453a8Sspeer * 2885678453a8Sspeer * NPI function calls: 2886678453a8Sspeer * 2887678453a8Sspeer * NXGE function calls: 2888678453a8Sspeer * 2889678453a8Sspeer * Registers accessed: 2890678453a8Sspeer * 2891678453a8Sspeer * Context: 2892678453a8Sspeer * 2893678453a8Sspeer * Taking apart: 2894678453a8Sspeer * 2895678453a8Sspeer * Open questions: 2896678453a8Sspeer * 2897678453a8Sspeer */ 2898678453a8Sspeer nxge_status_t 2899678453a8Sspeer nxge_alloc_txb( 2900678453a8Sspeer p_nxge_t nxgep, 2901678453a8Sspeer int channel) 2902678453a8Sspeer { 2903678453a8Sspeer nxge_dma_common_t **dma_buf_p; 2904678453a8Sspeer nxge_dma_common_t **dma_cntl_p; 2905*86ef0a63SRichard Lowe uint32_t *num_chunks; 2906678453a8Sspeer nxge_status_t status = NXGE_OK; 2907678453a8Sspeer 2908678453a8Sspeer nxge_tdc_sizes_t sizes; 2909678453a8Sspeer 2910678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_tbb")); 2911678453a8Sspeer 2912678453a8Sspeer if (nxge_tdc_sizes(nxgep, &sizes) != NXGE_OK) 2913678453a8Sspeer return (NXGE_ERROR); 2914678453a8Sspeer 2915678453a8Sspeer /* 2916678453a8Sspeer * Allocate memory for transmit buffers and descriptor rings. 2917678453a8Sspeer * Replace these allocation functions with the interface functions 2918678453a8Sspeer * provided by the partition manager Real Soon Now. 2919678453a8Sspeer */ 2920678453a8Sspeer dma_buf_p = &nxgep->tx_buf_pool_p->dma_buf_pool_p[channel]; 2921678453a8Sspeer num_chunks = &nxgep->tx_buf_pool_p->num_chunks[channel]; 2922678453a8Sspeer 2923678453a8Sspeer dma_cntl_p = &nxgep->tx_cntl_pool_p->dma_buf_pool_p[channel]; 2924678453a8Sspeer 2925678453a8Sspeer /* 2926678453a8Sspeer * Allocate memory for transmit buffers and descriptor rings. 2927678453a8Sspeer * Replace allocation functions with interface functions provided 2928678453a8Sspeer * by the partition manager when it is available. 2929678453a8Sspeer * 2930678453a8Sspeer * Allocate memory for the transmit buffer pool. 2931678453a8Sspeer */ 2932678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, 29334045d941Ssowmini "sizes: tx: %ld, cr:%ld, th:%ld", 29344045d941Ssowmini sizes.tx_size, sizes.cr_size, sizes.threshhold)); 2935678453a8Sspeer 2936678453a8Sspeer *num_chunks = 0; 2937678453a8Sspeer status = nxge_alloc_tx_buf_dma(nxgep, channel, dma_buf_p, 2938678453a8Sspeer sizes.tx_size, sizes.threshhold, num_chunks); 2939678453a8Sspeer if (status != NXGE_OK) { 2940678453a8Sspeer cmn_err(CE_NOTE, "nxge_alloc_tx_buf_dma failed!"); 2941678453a8Sspeer return (status); 2942678453a8Sspeer } 2943678453a8Sspeer 2944678453a8Sspeer /* 2945678453a8Sspeer * Allocate memory for descriptor rings and mailbox. 2946678453a8Sspeer */ 2947678453a8Sspeer status = nxge_alloc_tx_cntl_dma(nxgep, channel, dma_cntl_p, 2948678453a8Sspeer sizes.cr_size); 2949678453a8Sspeer if (status != NXGE_OK) { 2950678453a8Sspeer nxge_free_tx_buf_dma(nxgep, *dma_buf_p, *num_chunks); 2951678453a8Sspeer cmn_err(CE_NOTE, "nxge_alloc_tx_cntl_dma failed!"); 2952678453a8Sspeer return (status); 2953678453a8Sspeer } 2954678453a8Sspeer 2955678453a8Sspeer return (NXGE_OK); 2956678453a8Sspeer } 2957678453a8Sspeer 2958678453a8Sspeer void 2959678453a8Sspeer nxge_free_txb( 2960678453a8Sspeer p_nxge_t nxgep, 2961678453a8Sspeer int channel) 2962678453a8Sspeer { 2963678453a8Sspeer nxge_dma_common_t *data; 2964678453a8Sspeer nxge_dma_common_t *control; 2965*86ef0a63SRichard Lowe uint32_t num_chunks; 2966678453a8Sspeer 2967678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_free_txb")); 2968678453a8Sspeer 2969678453a8Sspeer data = nxgep->tx_buf_pool_p->dma_buf_pool_p[channel]; 2970678453a8Sspeer num_chunks = nxgep->tx_buf_pool_p->num_chunks[channel]; 2971678453a8Sspeer nxge_free_tx_buf_dma(nxgep, data, num_chunks); 2972678453a8Sspeer 2973678453a8Sspeer nxgep->tx_buf_pool_p->dma_buf_pool_p[channel] = 0; 2974678453a8Sspeer nxgep->tx_buf_pool_p->num_chunks[channel] = 0; 2975678453a8Sspeer 2976678453a8Sspeer control = nxgep->tx_cntl_pool_p->dma_buf_pool_p[channel]; 2977678453a8Sspeer nxge_free_tx_cntl_dma(nxgep, control); 297844961713Sgirish 2979678453a8Sspeer nxgep->tx_cntl_pool_p->dma_buf_pool_p[channel] = 0; 298044961713Sgirish 2981678453a8Sspeer KMEM_FREE(data, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK); 2982678453a8Sspeer KMEM_FREE(control, sizeof (nxge_dma_common_t)); 298344961713Sgirish 2984678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_free_txb")); 298544961713Sgirish } 298644961713Sgirish 2987678453a8Sspeer /* 2988678453a8Sspeer * nxge_alloc_tx_mem_pool 2989678453a8Sspeer * 2990678453a8Sspeer * This function allocates all of the per-port TDC control data structures. 2991678453a8Sspeer * The per-channel (TDC) data structures are allocated when needed. 2992678453a8Sspeer * 2993678453a8Sspeer * Arguments: 2994*86ef0a63SRichard Lowe * nxgep 2995678453a8Sspeer * 2996678453a8Sspeer * Notes: 2997678453a8Sspeer * 2998678453a8Sspeer * Context: 2999678453a8Sspeer * Any domain 3000678453a8Sspeer */ 3001678453a8Sspeer nxge_status_t 300244961713Sgirish nxge_alloc_tx_mem_pool(p_nxge_t nxgep) 300344961713Sgirish { 3004678453a8Sspeer nxge_hw_pt_cfg_t *p_cfgp; 3005678453a8Sspeer nxge_dma_pool_t *dma_poolp; 3006678453a8Sspeer nxge_dma_common_t **dma_buf_p; 3007678453a8Sspeer nxge_dma_pool_t *dma_cntl_poolp; 3008678453a8Sspeer nxge_dma_common_t **dma_cntl_p; 300944961713Sgirish uint32_t *num_chunks; /* per dma */ 3010678453a8Sspeer int tdc_max; 301144961713Sgirish 301244961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM_CTL, "==> nxge_alloc_tx_mem_pool")); 301344961713Sgirish 3014678453a8Sspeer p_cfgp = &nxgep->pt_config.hw_config; 3015678453a8Sspeer tdc_max = NXGE_MAX_TDCS; 301644961713Sgirish 301744961713Sgirish /* 301844961713Sgirish * Allocate memory for each transmit DMA channel. 301944961713Sgirish */ 302044961713Sgirish dma_poolp = (p_nxge_dma_pool_t)KMEM_ZALLOC(sizeof (nxge_dma_pool_t), 30214045d941Ssowmini KM_SLEEP); 302244961713Sgirish dma_buf_p = (p_nxge_dma_common_t *)KMEM_ZALLOC( 30234045d941Ssowmini sizeof (p_nxge_dma_common_t) * tdc_max, KM_SLEEP); 302444961713Sgirish 302544961713Sgirish dma_cntl_poolp = (p_nxge_dma_pool_t) 30264045d941Ssowmini KMEM_ZALLOC(sizeof (nxge_dma_pool_t), KM_SLEEP); 302744961713Sgirish dma_cntl_p = (p_nxge_dma_common_t *)KMEM_ZALLOC( 30284045d941Ssowmini sizeof (p_nxge_dma_common_t) * tdc_max, KM_SLEEP); 302944961713Sgirish 303030ac2e7bSml if (nxge_tx_ring_size > TDC_DEFAULT_MAX) { 303130ac2e7bSml NXGE_DEBUG_MSG((nxgep, MEM_CTL, 303230ac2e7bSml "nxge_alloc_tx_mem_pool: TDC too high %d, " 303330ac2e7bSml "set to default %d", 303430ac2e7bSml nxge_tx_ring_size, TDC_DEFAULT_MAX)); 303530ac2e7bSml nxge_tx_ring_size = TDC_DEFAULT_MAX; 303630ac2e7bSml } 303730ac2e7bSml 303844961713Sgirish #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 303944961713Sgirish /* 304044961713Sgirish * N2/NIU has limitation on the descriptor sizes (contiguous 304144961713Sgirish * memory allocation on data buffers to 4M (contig_mem_alloc) 304244961713Sgirish * and little endian for control buffers (must use the ddi/dki mem alloc 304344961713Sgirish * function). The transmit ring is limited to 8K (includes the 304444961713Sgirish * mailbox). 304544961713Sgirish */ 304644961713Sgirish if (nxgep->niu_type == N2_NIU) { 304744961713Sgirish if ((nxge_tx_ring_size > NXGE_NIU_CONTIG_TX_MAX) || 30484045d941Ssowmini (!ISP2(nxge_tx_ring_size))) { 304944961713Sgirish nxge_tx_ring_size = NXGE_NIU_CONTIG_TX_MAX; 305044961713Sgirish } 305144961713Sgirish } 305244961713Sgirish #endif 305344961713Sgirish 305444961713Sgirish nxgep->nxge_port_tx_ring_size = nxge_tx_ring_size; 305544961713Sgirish 305644961713Sgirish num_chunks = (uint32_t *)KMEM_ZALLOC( 30574045d941Ssowmini sizeof (uint32_t) * tdc_max, KM_SLEEP); 305844961713Sgirish 3059678453a8Sspeer dma_poolp->ndmas = p_cfgp->tdc.owned; 306044961713Sgirish dma_poolp->num_chunks = num_chunks; 306144961713Sgirish dma_poolp->dma_buf_pool_p = dma_buf_p; 306244961713Sgirish nxgep->tx_buf_pool_p = dma_poolp; 306344961713Sgirish 3064678453a8Sspeer dma_poolp->buf_allocated = B_TRUE; 3065678453a8Sspeer 3066678453a8Sspeer dma_cntl_poolp->ndmas = p_cfgp->tdc.owned; 306744961713Sgirish dma_cntl_poolp->dma_buf_pool_p = dma_cntl_p; 306844961713Sgirish nxgep->tx_cntl_pool_p = dma_cntl_poolp; 306944961713Sgirish 3070678453a8Sspeer dma_cntl_poolp->buf_allocated = B_TRUE; 307144961713Sgirish 3072678453a8Sspeer nxgep->tx_rings = 3073678453a8Sspeer KMEM_ZALLOC(sizeof (tx_rings_t), KM_SLEEP); 3074678453a8Sspeer nxgep->tx_rings->rings = 3075678453a8Sspeer KMEM_ZALLOC(sizeof (p_tx_ring_t) * tdc_max, KM_SLEEP); 3076678453a8Sspeer nxgep->tx_mbox_areas_p = 3077678453a8Sspeer KMEM_ZALLOC(sizeof (tx_mbox_areas_t), KM_SLEEP); 3078678453a8Sspeer nxgep->tx_mbox_areas_p->txmbox_areas_p = 3079678453a8Sspeer KMEM_ZALLOC(sizeof (p_tx_mbox_t) * tdc_max, KM_SLEEP); 308044961713Sgirish 3081678453a8Sspeer nxgep->tx_rings->ndmas = p_cfgp->tdc.owned; 308244961713Sgirish 308344961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM_CTL, 30844045d941Ssowmini "==> nxge_alloc_tx_mem_pool: ndmas %d poolp->ndmas %d", 30854045d941Ssowmini tdc_max, dma_poolp->ndmas)); 308644961713Sgirish 3087678453a8Sspeer return (NXGE_OK); 308844961713Sgirish } 308944961713Sgirish 3090678453a8Sspeer nxge_status_t 309144961713Sgirish nxge_alloc_tx_buf_dma(p_nxge_t nxgep, uint16_t dma_channel, 309244961713Sgirish p_nxge_dma_common_t *dmap, size_t alloc_size, 309344961713Sgirish size_t block_size, uint32_t *num_chunks) 309444961713Sgirish { 3095*86ef0a63SRichard Lowe p_nxge_dma_common_t tx_dmap; 309644961713Sgirish nxge_status_t status = NXGE_OK; 309744961713Sgirish size_t total_alloc_size; 309844961713Sgirish size_t allocated = 0; 309944961713Sgirish int i, size_index, array_size; 310044961713Sgirish 310144961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_tx_buf_dma")); 310244961713Sgirish 310344961713Sgirish tx_dmap = (p_nxge_dma_common_t) 31044045d941Ssowmini KMEM_ZALLOC(sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK, 31054045d941Ssowmini KM_SLEEP); 310644961713Sgirish 310744961713Sgirish total_alloc_size = alloc_size; 310844961713Sgirish i = 0; 310944961713Sgirish size_index = 0; 311044961713Sgirish array_size = sizeof (alloc_sizes) / sizeof (size_t); 31117b26d9ffSSantwona Behera while ((size_index < array_size) && 31127b26d9ffSSantwona Behera (alloc_sizes[size_index] < alloc_size)) 311344961713Sgirish size_index++; 311444961713Sgirish if (size_index >= array_size) { 311544961713Sgirish size_index = array_size - 1; 311644961713Sgirish } 311744961713Sgirish 311844961713Sgirish while ((allocated < total_alloc_size) && 31194045d941Ssowmini (size_index >= 0) && (i < NXGE_DMA_BLOCK)) { 312044961713Sgirish 312144961713Sgirish tx_dmap[i].dma_chunk_index = i; 312244961713Sgirish tx_dmap[i].block_size = block_size; 312344961713Sgirish tx_dmap[i].alength = alloc_sizes[size_index]; 312444961713Sgirish tx_dmap[i].orig_alength = tx_dmap[i].alength; 312544961713Sgirish tx_dmap[i].nblocks = alloc_sizes[size_index] / block_size; 312644961713Sgirish tx_dmap[i].dma_channel = dma_channel; 312744961713Sgirish tx_dmap[i].contig_alloc_type = B_FALSE; 3128678453a8Sspeer tx_dmap[i].kmem_alloc_type = B_FALSE; 312944961713Sgirish 313044961713Sgirish /* 313144961713Sgirish * N2/NIU: data buffers must be contiguous as the driver 313244961713Sgirish * needs to call Hypervisor api to set up 313344961713Sgirish * logical pages. 313444961713Sgirish */ 313544961713Sgirish if ((nxgep->niu_type == N2_NIU) && (NXGE_DMA_BLOCK == 1)) { 313644961713Sgirish tx_dmap[i].contig_alloc_type = B_TRUE; 313744961713Sgirish } 313844961713Sgirish 313944961713Sgirish status = nxge_dma_mem_alloc(nxgep, nxge_force_dma, 31404045d941Ssowmini &nxge_tx_dma_attr, 31414045d941Ssowmini tx_dmap[i].alength, 31424045d941Ssowmini &nxge_dev_buf_dma_acc_attr, 31434045d941Ssowmini DDI_DMA_WRITE | DDI_DMA_STREAMING, 31444045d941Ssowmini (p_nxge_dma_common_t)(&tx_dmap[i])); 314544961713Sgirish if (status != NXGE_OK) { 314644961713Sgirish size_index--; 314744961713Sgirish } else { 314844961713Sgirish i++; 314944961713Sgirish allocated += alloc_sizes[size_index]; 315044961713Sgirish } 315144961713Sgirish } 315244961713Sgirish 315344961713Sgirish if (allocated < total_alloc_size) { 315430ac2e7bSml NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 315530ac2e7bSml "==> nxge_alloc_tx_buf_dma: not enough channel %d: " 315630ac2e7bSml "allocated 0x%x requested 0x%x", 315730ac2e7bSml dma_channel, 315830ac2e7bSml allocated, total_alloc_size)); 315930ac2e7bSml status = NXGE_ERROR; 316044961713Sgirish goto nxge_alloc_tx_mem_fail1; 316144961713Sgirish } 316244961713Sgirish 316330ac2e7bSml NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 316430ac2e7bSml "==> nxge_alloc_tx_buf_dma: Allocated for channel %d: " 316530ac2e7bSml "allocated 0x%x requested 0x%x", 316630ac2e7bSml dma_channel, 316730ac2e7bSml allocated, total_alloc_size)); 316830ac2e7bSml 316944961713Sgirish *num_chunks = i; 317044961713Sgirish *dmap = tx_dmap; 317144961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 31724045d941Ssowmini "==> nxge_alloc_tx_buf_dma dmap 0x%016llx num chunks %d", 31734045d941Ssowmini *dmap, i)); 317444961713Sgirish goto nxge_alloc_tx_mem_exit; 317544961713Sgirish 317644961713Sgirish nxge_alloc_tx_mem_fail1: 317744961713Sgirish KMEM_FREE(tx_dmap, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK); 317844961713Sgirish 317944961713Sgirish nxge_alloc_tx_mem_exit: 318044961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 31814045d941Ssowmini "<== nxge_alloc_tx_buf_dma status 0x%08x", status)); 318244961713Sgirish 318344961713Sgirish return (status); 318444961713Sgirish } 318544961713Sgirish 318644961713Sgirish /*ARGSUSED*/ 318744961713Sgirish static void 318844961713Sgirish nxge_free_tx_buf_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap, 318944961713Sgirish uint32_t num_chunks) 319044961713Sgirish { 319144961713Sgirish int i; 319244961713Sgirish 319344961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM_CTL, "==> nxge_free_tx_buf_dma")); 319444961713Sgirish 3195678453a8Sspeer if (dmap == 0) 3196678453a8Sspeer return; 3197678453a8Sspeer 319844961713Sgirish for (i = 0; i < num_chunks; i++) { 319944961713Sgirish nxge_dma_mem_free(dmap++); 320044961713Sgirish } 320144961713Sgirish 320244961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM_CTL, "<== nxge_free_tx_buf_dma")); 320344961713Sgirish } 320444961713Sgirish 320544961713Sgirish /*ARGSUSED*/ 3206678453a8Sspeer nxge_status_t 320744961713Sgirish nxge_alloc_tx_cntl_dma(p_nxge_t nxgep, uint16_t dma_channel, 320844961713Sgirish p_nxge_dma_common_t *dmap, size_t size) 320944961713Sgirish { 3210*86ef0a63SRichard Lowe p_nxge_dma_common_t tx_dmap; 321144961713Sgirish nxge_status_t status = NXGE_OK; 321244961713Sgirish 321344961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_tx_cntl_dma")); 321444961713Sgirish tx_dmap = (p_nxge_dma_common_t) 32154045d941Ssowmini KMEM_ZALLOC(sizeof (nxge_dma_common_t), KM_SLEEP); 321644961713Sgirish 321744961713Sgirish tx_dmap->contig_alloc_type = B_FALSE; 3218678453a8Sspeer tx_dmap->kmem_alloc_type = B_FALSE; 321944961713Sgirish 322044961713Sgirish status = nxge_dma_mem_alloc(nxgep, nxge_force_dma, 32214045d941Ssowmini &nxge_desc_dma_attr, 32224045d941Ssowmini size, 32234045d941Ssowmini &nxge_dev_desc_dma_acc_attr, 32244045d941Ssowmini DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 32254045d941Ssowmini tx_dmap); 322644961713Sgirish if (status != NXGE_OK) { 322744961713Sgirish goto nxge_alloc_tx_cntl_dma_fail1; 322844961713Sgirish } 322944961713Sgirish 323044961713Sgirish *dmap = tx_dmap; 323144961713Sgirish goto nxge_alloc_tx_cntl_dma_exit; 323244961713Sgirish 323344961713Sgirish nxge_alloc_tx_cntl_dma_fail1: 323444961713Sgirish KMEM_FREE(tx_dmap, sizeof (nxge_dma_common_t)); 323544961713Sgirish 323644961713Sgirish nxge_alloc_tx_cntl_dma_exit: 323744961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 32384045d941Ssowmini "<== nxge_alloc_tx_cntl_dma status 0x%08x", status)); 323944961713Sgirish 324044961713Sgirish return (status); 324144961713Sgirish } 324244961713Sgirish 324344961713Sgirish /*ARGSUSED*/ 324444961713Sgirish static void 324544961713Sgirish nxge_free_tx_cntl_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap) 324644961713Sgirish { 324744961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_free_tx_cntl_dma")); 324844961713Sgirish 3249678453a8Sspeer if (dmap == 0) 3250678453a8Sspeer return; 3251678453a8Sspeer 325244961713Sgirish nxge_dma_mem_free(dmap); 325344961713Sgirish 325444961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_free_tx_cntl_dma")); 325544961713Sgirish } 325644961713Sgirish 3257678453a8Sspeer /* 3258678453a8Sspeer * nxge_free_tx_mem_pool 3259678453a8Sspeer * 3260678453a8Sspeer * This function frees all of the per-port TDC control data structures. 3261678453a8Sspeer * The per-channel (TDC) data structures are freed when the channel 3262678453a8Sspeer * is stopped. 3263678453a8Sspeer * 3264678453a8Sspeer * Arguments: 3265*86ef0a63SRichard Lowe * nxgep 3266678453a8Sspeer * 3267678453a8Sspeer * Notes: 3268678453a8Sspeer * 3269678453a8Sspeer * Context: 3270678453a8Sspeer * Any domain 3271678453a8Sspeer */ 327244961713Sgirish static void 327344961713Sgirish nxge_free_tx_mem_pool(p_nxge_t nxgep) 327444961713Sgirish { 3275678453a8Sspeer int tdc_max = NXGE_MAX_TDCS; 327644961713Sgirish 3277678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_free_tx_mem_pool")); 327844961713Sgirish 3279678453a8Sspeer if (!nxgep->tx_buf_pool_p || !nxgep->tx_buf_pool_p->buf_allocated) { 3280678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 32814045d941Ssowmini "<== nxge_free_tx_mem_pool " 32824045d941Ssowmini "(null tx buf pool or buf not allocated")); 328344961713Sgirish return; 328444961713Sgirish } 3285678453a8Sspeer if (!nxgep->tx_cntl_pool_p || !nxgep->tx_cntl_pool_p->buf_allocated) { 3286678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 32874045d941Ssowmini "<== nxge_free_tx_mem_pool " 32884045d941Ssowmini "(null tx cntl buf pool or cntl buf not allocated")); 328944961713Sgirish return; 329044961713Sgirish } 329144961713Sgirish 3292678453a8Sspeer /* 1. Free the mailboxes. */ 3293678453a8Sspeer KMEM_FREE(nxgep->tx_mbox_areas_p->txmbox_areas_p, 3294678453a8Sspeer sizeof (p_tx_mbox_t) * tdc_max); 3295678453a8Sspeer KMEM_FREE(nxgep->tx_mbox_areas_p, sizeof (tx_mbox_areas_t)); 329644961713Sgirish 3297678453a8Sspeer nxgep->tx_mbox_areas_p = 0; 329844961713Sgirish 3299678453a8Sspeer /* 2. Free the transmit ring arrays. */ 3300678453a8Sspeer KMEM_FREE(nxgep->tx_rings->rings, 3301678453a8Sspeer sizeof (p_tx_ring_t) * tdc_max); 3302678453a8Sspeer KMEM_FREE(nxgep->tx_rings, sizeof (tx_rings_t)); 330344961713Sgirish 3304678453a8Sspeer nxgep->tx_rings = 0; 330544961713Sgirish 3306678453a8Sspeer /* 3. Free the completion ring data structures. */ 3307678453a8Sspeer KMEM_FREE(nxgep->tx_cntl_pool_p->dma_buf_pool_p, 3308678453a8Sspeer sizeof (p_nxge_dma_common_t) * tdc_max); 3309678453a8Sspeer KMEM_FREE(nxgep->tx_cntl_pool_p, sizeof (nxge_dma_pool_t)); 331044961713Sgirish 3311678453a8Sspeer nxgep->tx_cntl_pool_p = 0; 331244961713Sgirish 3313678453a8Sspeer /* 4. Free the data ring data structures. */ 3314678453a8Sspeer KMEM_FREE(nxgep->tx_buf_pool_p->num_chunks, 3315678453a8Sspeer sizeof (uint32_t) * tdc_max); 3316678453a8Sspeer KMEM_FREE(nxgep->tx_buf_pool_p->dma_buf_pool_p, 3317678453a8Sspeer sizeof (p_nxge_dma_common_t) * tdc_max); 3318678453a8Sspeer KMEM_FREE(nxgep->tx_buf_pool_p, sizeof (nxge_dma_pool_t)); 331944961713Sgirish 3320678453a8Sspeer nxgep->tx_buf_pool_p = 0; 3321678453a8Sspeer 3322678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_free_tx_mem_pool")); 332344961713Sgirish } 332444961713Sgirish 332544961713Sgirish /*ARGSUSED*/ 332644961713Sgirish static nxge_status_t 332744961713Sgirish nxge_dma_mem_alloc(p_nxge_t nxgep, dma_method_t method, 3328*86ef0a63SRichard Lowe struct ddi_dma_attr *dma_attrp, 3329*86ef0a63SRichard Lowe size_t length, ddi_device_acc_attr_t *acc_attr_p, uint_t xfer_flags, 3330*86ef0a63SRichard Lowe p_nxge_dma_common_t dma_p) 333144961713Sgirish { 3332*86ef0a63SRichard Lowe caddr_t kaddrp; 333344961713Sgirish int ddi_status = DDI_SUCCESS; 333444961713Sgirish boolean_t contig_alloc_type; 3335678453a8Sspeer boolean_t kmem_alloc_type; 333644961713Sgirish 333744961713Sgirish contig_alloc_type = dma_p->contig_alloc_type; 333844961713Sgirish 333944961713Sgirish if (contig_alloc_type && (nxgep->niu_type != N2_NIU)) { 334044961713Sgirish /* 334144961713Sgirish * contig_alloc_type for contiguous memory only allowed 334244961713Sgirish * for N2/NIU. 334344961713Sgirish */ 334444961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 33454045d941Ssowmini "nxge_dma_mem_alloc: alloc type not allowed (%d)", 33464045d941Ssowmini dma_p->contig_alloc_type)); 334744961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 334844961713Sgirish } 334944961713Sgirish 335044961713Sgirish dma_p->dma_handle = NULL; 335144961713Sgirish dma_p->acc_handle = NULL; 335244961713Sgirish dma_p->kaddrp = dma_p->last_kaddrp = NULL; 335344961713Sgirish dma_p->first_ioaddr_pp = dma_p->last_ioaddr_pp = NULL; 335444961713Sgirish ddi_status = ddi_dma_alloc_handle(nxgep->dip, dma_attrp, 33554045d941Ssowmini DDI_DMA_DONTWAIT, NULL, &dma_p->dma_handle); 335644961713Sgirish if (ddi_status != DDI_SUCCESS) { 335744961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 33584045d941Ssowmini "nxge_dma_mem_alloc:ddi_dma_alloc_handle failed.")); 335944961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 336044961713Sgirish } 336144961713Sgirish 3362678453a8Sspeer kmem_alloc_type = dma_p->kmem_alloc_type; 3363678453a8Sspeer 336444961713Sgirish switch (contig_alloc_type) { 336544961713Sgirish case B_FALSE: 3366678453a8Sspeer switch (kmem_alloc_type) { 3367678453a8Sspeer case B_FALSE: 3368678453a8Sspeer ddi_status = ddi_dma_mem_alloc(dma_p->dma_handle, 33694045d941Ssowmini length, 33704045d941Ssowmini acc_attr_p, 33714045d941Ssowmini xfer_flags, 33724045d941Ssowmini DDI_DMA_DONTWAIT, 0, &kaddrp, &dma_p->alength, 33734045d941Ssowmini &dma_p->acc_handle); 3374678453a8Sspeer if (ddi_status != DDI_SUCCESS) { 3375678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3376678453a8Sspeer "nxge_dma_mem_alloc: " 3377678453a8Sspeer "ddi_dma_mem_alloc failed")); 3378678453a8Sspeer ddi_dma_free_handle(&dma_p->dma_handle); 3379678453a8Sspeer dma_p->dma_handle = NULL; 3380678453a8Sspeer return (NXGE_ERROR | NXGE_DDI_FAILED); 3381678453a8Sspeer } 3382678453a8Sspeer if (dma_p->alength < length) { 3383678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3384678453a8Sspeer "nxge_dma_mem_alloc:di_dma_mem_alloc " 3385678453a8Sspeer "< length.")); 338644961713Sgirish ddi_dma_mem_free(&dma_p->acc_handle); 3387678453a8Sspeer ddi_dma_free_handle(&dma_p->dma_handle); 338844961713Sgirish dma_p->acc_handle = NULL; 3389678453a8Sspeer dma_p->dma_handle = NULL; 3390678453a8Sspeer return (NXGE_ERROR); 339144961713Sgirish } 339244961713Sgirish 3393678453a8Sspeer ddi_status = ddi_dma_addr_bind_handle(dma_p->dma_handle, 3394678453a8Sspeer NULL, 3395678453a8Sspeer kaddrp, dma_p->alength, xfer_flags, 3396678453a8Sspeer DDI_DMA_DONTWAIT, 3397678453a8Sspeer 0, &dma_p->dma_cookie, &dma_p->ncookies); 3398678453a8Sspeer if (ddi_status != DDI_DMA_MAPPED) { 3399678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3400678453a8Sspeer "nxge_dma_mem_alloc: ddi_dma_addr_bind " 3401678453a8Sspeer "failed " 3402678453a8Sspeer "(staus 0x%x ncookies %d.)", ddi_status, 3403678453a8Sspeer dma_p->ncookies)); 3404678453a8Sspeer if (dma_p->acc_handle) { 3405678453a8Sspeer ddi_dma_mem_free(&dma_p->acc_handle); 3406678453a8Sspeer dma_p->acc_handle = NULL; 3407678453a8Sspeer } 3408678453a8Sspeer ddi_dma_free_handle(&dma_p->dma_handle); 3409678453a8Sspeer dma_p->dma_handle = NULL; 3410678453a8Sspeer return (NXGE_ERROR | NXGE_DDI_FAILED); 3411678453a8Sspeer } 3412678453a8Sspeer 3413678453a8Sspeer if (dma_p->ncookies != 1) { 3414678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, 3415678453a8Sspeer "nxge_dma_mem_alloc:ddi_dma_addr_bind " 3416678453a8Sspeer "> 1 cookie" 3417678453a8Sspeer "(staus 0x%x ncookies %d.)", ddi_status, 3418678453a8Sspeer dma_p->ncookies)); 3419330cd344SMichael Speer (void) ddi_dma_unbind_handle(dma_p->dma_handle); 3420678453a8Sspeer if (dma_p->acc_handle) { 3421678453a8Sspeer ddi_dma_mem_free(&dma_p->acc_handle); 3422678453a8Sspeer dma_p->acc_handle = NULL; 3423678453a8Sspeer } 3424678453a8Sspeer ddi_dma_free_handle(&dma_p->dma_handle); 3425678453a8Sspeer dma_p->dma_handle = NULL; 3426330cd344SMichael Speer dma_p->acc_handle = NULL; 3427678453a8Sspeer return (NXGE_ERROR); 3428678453a8Sspeer } 3429678453a8Sspeer break; 3430678453a8Sspeer 3431678453a8Sspeer case B_TRUE: 3432678453a8Sspeer kaddrp = KMEM_ALLOC(length, KM_NOSLEEP); 3433678453a8Sspeer if (kaddrp == NULL) { 3434678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3435678453a8Sspeer "nxge_dma_mem_alloc:ddi_dma_mem_alloc " 3436678453a8Sspeer "kmem alloc failed")); 3437678453a8Sspeer return (NXGE_ERROR); 3438678453a8Sspeer } 3439678453a8Sspeer 3440678453a8Sspeer dma_p->alength = length; 3441678453a8Sspeer ddi_status = ddi_dma_addr_bind_handle(dma_p->dma_handle, 3442678453a8Sspeer NULL, kaddrp, dma_p->alength, xfer_flags, 3443678453a8Sspeer DDI_DMA_DONTWAIT, 0, 3444678453a8Sspeer &dma_p->dma_cookie, &dma_p->ncookies); 3445678453a8Sspeer if (ddi_status != DDI_DMA_MAPPED) { 3446678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3447678453a8Sspeer "nxge_dma_mem_alloc:ddi_dma_addr_bind: " 3448678453a8Sspeer "(kmem_alloc) failed kaddrp $%p length %d " 3449678453a8Sspeer "(staus 0x%x (%d) ncookies %d.)", 3450678453a8Sspeer kaddrp, length, 3451678453a8Sspeer ddi_status, ddi_status, dma_p->ncookies)); 3452678453a8Sspeer KMEM_FREE(kaddrp, length); 3453678453a8Sspeer dma_p->acc_handle = NULL; 3454678453a8Sspeer ddi_dma_free_handle(&dma_p->dma_handle); 3455678453a8Sspeer dma_p->dma_handle = NULL; 3456678453a8Sspeer dma_p->kaddrp = NULL; 3457678453a8Sspeer return (NXGE_ERROR | NXGE_DDI_FAILED); 3458678453a8Sspeer } 3459678453a8Sspeer 3460678453a8Sspeer if (dma_p->ncookies != 1) { 3461678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, 3462678453a8Sspeer "nxge_dma_mem_alloc:ddi_dma_addr_bind " 3463678453a8Sspeer "(kmem_alloc) > 1 cookie" 3464678453a8Sspeer "(staus 0x%x ncookies %d.)", ddi_status, 34654045d941Ssowmini dma_p->ncookies)); 3466678453a8Sspeer (void) ddi_dma_unbind_handle(dma_p->dma_handle); 3467330cd344SMichael Speer KMEM_FREE(kaddrp, length); 3468678453a8Sspeer ddi_dma_free_handle(&dma_p->dma_handle); 3469678453a8Sspeer dma_p->dma_handle = NULL; 3470330cd344SMichael Speer dma_p->acc_handle = NULL; 3471678453a8Sspeer dma_p->kaddrp = NULL; 3472678453a8Sspeer return (NXGE_ERROR); 347344961713Sgirish } 3474678453a8Sspeer 3475678453a8Sspeer dma_p->kaddrp = kaddrp; 3476678453a8Sspeer 3477678453a8Sspeer NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 34784045d941Ssowmini "nxge_dma_mem_alloc: kmem_alloc dmap $%p " 34794045d941Ssowmini "kaddr $%p alength %d", 34804045d941Ssowmini dma_p, 34814045d941Ssowmini kaddrp, 34824045d941Ssowmini dma_p->alength)); 3483678453a8Sspeer break; 348444961713Sgirish } 348544961713Sgirish break; 348644961713Sgirish 348744961713Sgirish #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 348844961713Sgirish case B_TRUE: 348944961713Sgirish kaddrp = (caddr_t)contig_mem_alloc(length); 349044961713Sgirish if (kaddrp == NULL) { 349144961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 34924045d941Ssowmini "nxge_dma_mem_alloc:contig_mem_alloc failed.")); 349344961713Sgirish ddi_dma_free_handle(&dma_p->dma_handle); 349444961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 349544961713Sgirish } 349644961713Sgirish 349744961713Sgirish dma_p->alength = length; 349844961713Sgirish ddi_status = ddi_dma_addr_bind_handle(dma_p->dma_handle, NULL, 34994045d941Ssowmini kaddrp, dma_p->alength, xfer_flags, DDI_DMA_DONTWAIT, 0, 35004045d941Ssowmini &dma_p->dma_cookie, &dma_p->ncookies); 350144961713Sgirish if (ddi_status != DDI_DMA_MAPPED) { 350244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 35034045d941Ssowmini "nxge_dma_mem_alloc:di_dma_addr_bind failed " 35044045d941Ssowmini "(status 0x%x ncookies %d.)", ddi_status, 35054045d941Ssowmini dma_p->ncookies)); 350644961713Sgirish 350744961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 35084045d941Ssowmini "==> nxge_dma_mem_alloc: (not mapped)" 35094045d941Ssowmini "length %lu (0x%x) " 35104045d941Ssowmini "free contig kaddrp $%p " 35114045d941Ssowmini "va_to_pa $%p", 35124045d941Ssowmini length, length, 35134045d941Ssowmini kaddrp, 35144045d941Ssowmini va_to_pa(kaddrp))); 351544961713Sgirish 351644961713Sgirish 351744961713Sgirish contig_mem_free((void *)kaddrp, length); 351844961713Sgirish ddi_dma_free_handle(&dma_p->dma_handle); 351944961713Sgirish 352044961713Sgirish dma_p->dma_handle = NULL; 352144961713Sgirish dma_p->acc_handle = NULL; 35224df3b64dSToomas Soome dma_p->alength = 0; 352344961713Sgirish dma_p->kaddrp = NULL; 352444961713Sgirish 352544961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 352644961713Sgirish } 352744961713Sgirish 352844961713Sgirish if (dma_p->ncookies != 1 || 35294df3b64dSToomas Soome (dma_p->dma_cookie.dmac_laddress == 0)) { 353044961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 35314045d941Ssowmini "nxge_dma_mem_alloc:di_dma_addr_bind > 1 " 35324045d941Ssowmini "cookie or " 35334045d941Ssowmini "dmac_laddress is NULL $%p size %d " 35344045d941Ssowmini " (status 0x%x ncookies %d.)", 35354045d941Ssowmini ddi_status, 35364045d941Ssowmini dma_p->dma_cookie.dmac_laddress, 35374045d941Ssowmini dma_p->dma_cookie.dmac_size, 35384045d941Ssowmini dma_p->ncookies)); 353944961713Sgirish 354044961713Sgirish contig_mem_free((void *)kaddrp, length); 354156d930aeSspeer (void) ddi_dma_unbind_handle(dma_p->dma_handle); 354244961713Sgirish ddi_dma_free_handle(&dma_p->dma_handle); 354344961713Sgirish 354444961713Sgirish dma_p->alength = 0; 354544961713Sgirish dma_p->dma_handle = NULL; 354644961713Sgirish dma_p->acc_handle = NULL; 354744961713Sgirish dma_p->kaddrp = NULL; 354844961713Sgirish 354944961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 355044961713Sgirish } 355144961713Sgirish break; 355244961713Sgirish 355344961713Sgirish #else 355444961713Sgirish case B_TRUE: 355544961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 35564045d941Ssowmini "nxge_dma_mem_alloc: invalid alloc type for !sun4v")); 355744961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 355844961713Sgirish #endif 355944961713Sgirish } 356044961713Sgirish 356144961713Sgirish dma_p->kaddrp = kaddrp; 356244961713Sgirish dma_p->last_kaddrp = (unsigned char *)kaddrp + 35634045d941Ssowmini dma_p->alength - RXBUF_64B_ALIGNED; 356444961713Sgirish dma_p->ioaddr_pp = (unsigned char *)dma_p->dma_cookie.dmac_laddress; 356544961713Sgirish dma_p->last_ioaddr_pp = 35664045d941Ssowmini (unsigned char *)dma_p->dma_cookie.dmac_laddress + 35674045d941Ssowmini dma_p->alength - RXBUF_64B_ALIGNED; 356844961713Sgirish 356944961713Sgirish NPI_DMA_ACC_HANDLE_SET(dma_p, dma_p->acc_handle); 357044961713Sgirish 357144961713Sgirish #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 357244961713Sgirish dma_p->orig_ioaddr_pp = 35734045d941Ssowmini (unsigned char *)dma_p->dma_cookie.dmac_laddress; 357444961713Sgirish dma_p->orig_alength = length; 357544961713Sgirish dma_p->orig_kaddrp = kaddrp; 357644961713Sgirish dma_p->orig_vatopa = (uint64_t)va_to_pa(kaddrp); 357744961713Sgirish #endif 357844961713Sgirish 357944961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_dma_mem_alloc: " 35804045d941Ssowmini "dma buffer allocated: dma_p $%p " 35814045d941Ssowmini "return dmac_ladress from cookie $%p cookie dmac_size %d " 35824045d941Ssowmini "dma_p->ioaddr_p $%p " 35834045d941Ssowmini "dma_p->orig_ioaddr_p $%p " 35844045d941Ssowmini "orig_vatopa $%p " 35854045d941Ssowmini "alength %d (0x%x) " 35864045d941Ssowmini "kaddrp $%p " 35874045d941Ssowmini "length %d (0x%x)", 35884045d941Ssowmini dma_p, 35894045d941Ssowmini dma_p->dma_cookie.dmac_laddress, dma_p->dma_cookie.dmac_size, 35904045d941Ssowmini dma_p->ioaddr_pp, 35914045d941Ssowmini dma_p->orig_ioaddr_pp, 35924045d941Ssowmini dma_p->orig_vatopa, 35934045d941Ssowmini dma_p->alength, dma_p->alength, 35944045d941Ssowmini kaddrp, 35954045d941Ssowmini length, length)); 359644961713Sgirish 359744961713Sgirish return (NXGE_OK); 359844961713Sgirish } 359944961713Sgirish 360044961713Sgirish static void 360144961713Sgirish nxge_dma_mem_free(p_nxge_dma_common_t dma_p) 360244961713Sgirish { 360344961713Sgirish if (dma_p->dma_handle != NULL) { 360444961713Sgirish if (dma_p->ncookies) { 360544961713Sgirish (void) ddi_dma_unbind_handle(dma_p->dma_handle); 360644961713Sgirish dma_p->ncookies = 0; 360744961713Sgirish } 360844961713Sgirish ddi_dma_free_handle(&dma_p->dma_handle); 360944961713Sgirish dma_p->dma_handle = NULL; 361044961713Sgirish } 361144961713Sgirish 361244961713Sgirish if (dma_p->acc_handle != NULL) { 361344961713Sgirish ddi_dma_mem_free(&dma_p->acc_handle); 361444961713Sgirish dma_p->acc_handle = NULL; 361544961713Sgirish NPI_DMA_ACC_HANDLE_SET(dma_p, NULL); 361644961713Sgirish } 361744961713Sgirish 361844961713Sgirish #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 361944961713Sgirish if (dma_p->contig_alloc_type && 36204045d941Ssowmini dma_p->orig_kaddrp && dma_p->orig_alength) { 362144961713Sgirish NXGE_DEBUG_MSG((NULL, DMA_CTL, "nxge_dma_mem_free: " 36224045d941Ssowmini "kaddrp $%p (orig_kaddrp $%p)" 36234045d941Ssowmini "mem type %d ", 36244045d941Ssowmini "orig_alength %d " 36254045d941Ssowmini "alength 0x%x (%d)", 36264045d941Ssowmini dma_p->kaddrp, 36274045d941Ssowmini dma_p->orig_kaddrp, 36284045d941Ssowmini dma_p->contig_alloc_type, 36294045d941Ssowmini dma_p->orig_alength, 36304045d941Ssowmini dma_p->alength, dma_p->alength)); 363144961713Sgirish 363244961713Sgirish contig_mem_free(dma_p->orig_kaddrp, dma_p->orig_alength); 36334df3b64dSToomas Soome dma_p->orig_alength = 0; 363444961713Sgirish dma_p->orig_kaddrp = NULL; 363544961713Sgirish dma_p->contig_alloc_type = B_FALSE; 363644961713Sgirish } 363744961713Sgirish #endif 363844961713Sgirish dma_p->kaddrp = NULL; 3639b37cc459SToomas Soome dma_p->alength = 0; 364044961713Sgirish } 364144961713Sgirish 3642678453a8Sspeer static void 3643678453a8Sspeer nxge_dma_free_rx_data_buf(p_nxge_dma_common_t dma_p) 3644678453a8Sspeer { 3645678453a8Sspeer uint64_t kaddr; 3646678453a8Sspeer uint32_t buf_size; 3647678453a8Sspeer 3648678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, "==> nxge_dma_free_rx_data_buf")); 3649678453a8Sspeer 3650678453a8Sspeer if (dma_p->dma_handle != NULL) { 3651678453a8Sspeer if (dma_p->ncookies) { 3652678453a8Sspeer (void) ddi_dma_unbind_handle(dma_p->dma_handle); 3653678453a8Sspeer dma_p->ncookies = 0; 3654678453a8Sspeer } 3655678453a8Sspeer ddi_dma_free_handle(&dma_p->dma_handle); 3656678453a8Sspeer dma_p->dma_handle = NULL; 3657678453a8Sspeer } 3658678453a8Sspeer 3659678453a8Sspeer if (dma_p->acc_handle != NULL) { 3660678453a8Sspeer ddi_dma_mem_free(&dma_p->acc_handle); 3661678453a8Sspeer dma_p->acc_handle = NULL; 3662678453a8Sspeer NPI_DMA_ACC_HANDLE_SET(dma_p, NULL); 3663678453a8Sspeer } 3664678453a8Sspeer 3665678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, 3666678453a8Sspeer "==> nxge_dma_free_rx_data_buf: dmap $%p buf_alloc_state %d", 3667678453a8Sspeer dma_p, 3668678453a8Sspeer dma_p->buf_alloc_state)); 3669678453a8Sspeer 3670678453a8Sspeer if (!(dma_p->buf_alloc_state & BUF_ALLOCATED_WAIT_FREE)) { 3671678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, 3672678453a8Sspeer "<== nxge_dma_free_rx_data_buf: " 3673678453a8Sspeer "outstanding data buffers")); 3674678453a8Sspeer return; 3675678453a8Sspeer } 3676678453a8Sspeer 3677678453a8Sspeer #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 3678678453a8Sspeer if (dma_p->contig_alloc_type && 36794045d941Ssowmini dma_p->orig_kaddrp && dma_p->orig_alength) { 3680678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, "nxge_dma_free_rx_data_buf: " 3681678453a8Sspeer "kaddrp $%p (orig_kaddrp $%p)" 3682678453a8Sspeer "mem type %d ", 3683678453a8Sspeer "orig_alength %d " 3684678453a8Sspeer "alength 0x%x (%d)", 3685678453a8Sspeer dma_p->kaddrp, 3686678453a8Sspeer dma_p->orig_kaddrp, 3687678453a8Sspeer dma_p->contig_alloc_type, 3688678453a8Sspeer dma_p->orig_alength, 3689678453a8Sspeer dma_p->alength, dma_p->alength)); 3690678453a8Sspeer 3691678453a8Sspeer kaddr = (uint64_t)dma_p->orig_kaddrp; 3692678453a8Sspeer buf_size = dma_p->orig_alength; 3693678453a8Sspeer nxge_free_buf(CONTIG_MEM_ALLOC, kaddr, buf_size); 36944df3b64dSToomas Soome dma_p->orig_alength = 0; 3695678453a8Sspeer dma_p->orig_kaddrp = NULL; 3696678453a8Sspeer dma_p->contig_alloc_type = B_FALSE; 3697678453a8Sspeer dma_p->kaddrp = NULL; 36984df3b64dSToomas Soome dma_p->alength = 0; 3699678453a8Sspeer return; 3700678453a8Sspeer } 3701678453a8Sspeer #endif 3702678453a8Sspeer 3703678453a8Sspeer if (dma_p->kmem_alloc_type) { 3704678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, 3705678453a8Sspeer "nxge_dma_free_rx_data_buf: free kmem " 37064045d941Ssowmini "kaddrp $%p (orig_kaddrp $%p)" 37074045d941Ssowmini "alloc type %d " 37084045d941Ssowmini "orig_alength %d " 37094045d941Ssowmini "alength 0x%x (%d)", 37104045d941Ssowmini dma_p->kaddrp, 37114045d941Ssowmini dma_p->orig_kaddrp, 37124045d941Ssowmini dma_p->kmem_alloc_type, 37134045d941Ssowmini dma_p->orig_alength, 37144045d941Ssowmini dma_p->alength, dma_p->alength)); 3715678453a8Sspeer kaddr = (uint64_t)dma_p->kaddrp; 3716678453a8Sspeer buf_size = dma_p->orig_alength; 3717678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, 3718678453a8Sspeer "nxge_dma_free_rx_data_buf: free dmap $%p " 3719678453a8Sspeer "kaddr $%p buf_size %d", 3720678453a8Sspeer dma_p, 3721678453a8Sspeer kaddr, buf_size)); 3722678453a8Sspeer nxge_free_buf(KMEM_ALLOC, kaddr, buf_size); 3723678453a8Sspeer dma_p->alength = 0; 3724678453a8Sspeer dma_p->orig_alength = 0; 3725678453a8Sspeer dma_p->kaddrp = NULL; 3726678453a8Sspeer dma_p->kmem_alloc_type = B_FALSE; 3727678453a8Sspeer } 3728678453a8Sspeer 3729678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_dma_free_rx_data_buf")); 3730678453a8Sspeer } 3731678453a8Sspeer 373244961713Sgirish /* 373344961713Sgirish * nxge_m_start() -- start transmitting and receiving. 373444961713Sgirish * 373544961713Sgirish * This function is called by the MAC layer when the first 373644961713Sgirish * stream is open to prepare the hardware ready for sending 373744961713Sgirish * and transmitting packets. 373844961713Sgirish */ 373944961713Sgirish static int 374044961713Sgirish nxge_m_start(void *arg) 374144961713Sgirish { 3742*86ef0a63SRichard Lowe p_nxge_t nxgep = (p_nxge_t)arg; 374344961713Sgirish 374444961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_start")); 374544961713Sgirish 3746e759c33aSMichael Speer /* 3747e759c33aSMichael Speer * Are we already started? 3748e759c33aSMichael Speer */ 3749e759c33aSMichael Speer if (nxgep->nxge_mac_state == NXGE_MAC_STARTED) { 3750e759c33aSMichael Speer return (0); 3751e759c33aSMichael Speer } 3752e759c33aSMichael Speer 37536f157acbSml if (nxge_peu_reset_enable && !nxgep->nxge_link_poll_timerid) { 37546f157acbSml (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 37556f157acbSml } 37566f157acbSml 3757e759c33aSMichael Speer /* 3758e759c33aSMichael Speer * Make sure RX MAC is disabled while we initialize. 3759e759c33aSMichael Speer */ 3760e759c33aSMichael Speer if (!isLDOMguest(nxgep)) { 3761e759c33aSMichael Speer (void) nxge_rx_mac_disable(nxgep); 3762e759c33aSMichael Speer } 3763e759c33aSMichael Speer 3764e759c33aSMichael Speer /* 3765e759c33aSMichael Speer * Grab the global lock. 3766e759c33aSMichael Speer */ 376744961713Sgirish MUTEX_ENTER(nxgep->genlock); 3768e759c33aSMichael Speer 3769e759c33aSMichael Speer /* 3770e759c33aSMichael Speer * Initialize the driver and hardware. 3771e759c33aSMichael Speer */ 377214ea4bb7Ssd if (nxge_init(nxgep) != NXGE_OK) { 377344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 37744045d941Ssowmini "<== nxge_m_start: initialization failed")); 377544961713Sgirish MUTEX_EXIT(nxgep->genlock); 377644961713Sgirish return (EIO); 377744961713Sgirish } 377844961713Sgirish 377944961713Sgirish /* 378044961713Sgirish * Start timer to check the system error and tx hangs 378144961713Sgirish */ 3782678453a8Sspeer if (!isLDOMguest(nxgep)) 3783678453a8Sspeer nxgep->nxge_timerid = nxge_start_timer(nxgep, 3784678453a8Sspeer nxge_check_hw_state, NXGE_CHECK_TIMER); 3785e759c33aSMichael Speer #if defined(sun4v) 3786678453a8Sspeer else 3787678453a8Sspeer nxge_hio_start_timer(nxgep); 3788678453a8Sspeer #endif 378944961713Sgirish 3790a3c5bd6dSspeer nxgep->link_notify = B_TRUE; 3791774da109Stc nxgep->link_check_count = 0; 379244961713Sgirish nxgep->nxge_mac_state = NXGE_MAC_STARTED; 379344961713Sgirish 3794e759c33aSMichael Speer /* 3795e759c33aSMichael Speer * Let the global lock go, since we are intialized. 3796e759c33aSMichael Speer */ 379744961713Sgirish MUTEX_EXIT(nxgep->genlock); 3798e759c33aSMichael Speer 3799e759c33aSMichael Speer /* 3800e759c33aSMichael Speer * Let the MAC start receiving packets, now that 3801e759c33aSMichael Speer * we are initialized. 3802e759c33aSMichael Speer */ 3803e759c33aSMichael Speer if (!isLDOMguest(nxgep)) { 3804e759c33aSMichael Speer if (nxge_rx_mac_enable(nxgep) != NXGE_OK) { 3805e759c33aSMichael Speer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3806e759c33aSMichael Speer "<== nxge_m_start: enable of RX mac failed")); 3807e759c33aSMichael Speer return (EIO); 3808e759c33aSMichael Speer } 3809e759c33aSMichael Speer 3810e759c33aSMichael Speer /* 3811e759c33aSMichael Speer * Enable hardware interrupts. 3812e759c33aSMichael Speer */ 3813e759c33aSMichael Speer nxge_intr_hw_enable(nxgep); 3814e759c33aSMichael Speer } 3815e759c33aSMichael Speer #if defined(sun4v) 3816e759c33aSMichael Speer else { 3817e759c33aSMichael Speer /* 3818e759c33aSMichael Speer * In guest domain we enable RDCs and their interrupts as 3819e759c33aSMichael Speer * the last step. 3820e759c33aSMichael Speer */ 3821e759c33aSMichael Speer if (nxge_hio_rdc_enable(nxgep) != NXGE_OK) { 3822e759c33aSMichael Speer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3823e759c33aSMichael Speer "<== nxge_m_start: enable of RDCs failed")); 3824e759c33aSMichael Speer return (EIO); 3825e759c33aSMichael Speer } 3826e759c33aSMichael Speer 3827e759c33aSMichael Speer if (nxge_hio_rdc_intr_arm(nxgep, B_TRUE) != NXGE_OK) { 3828e759c33aSMichael Speer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3829e759c33aSMichael Speer "<== nxge_m_start: intrs enable for RDCs failed")); 3830e759c33aSMichael Speer return (EIO); 3831e759c33aSMichael Speer } 3832e759c33aSMichael Speer } 3833e759c33aSMichael Speer #endif 383444961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_start")); 383544961713Sgirish return (0); 383644961713Sgirish } 383744961713Sgirish 3838da14cebeSEric Cheng static boolean_t 3839da14cebeSEric Cheng nxge_check_groups_stopped(p_nxge_t nxgep) 3840da14cebeSEric Cheng { 3841da14cebeSEric Cheng int i; 3842da14cebeSEric Cheng 3843da14cebeSEric Cheng for (i = 0; i < NXGE_MAX_RDC_GROUPS; i++) { 3844da14cebeSEric Cheng if (nxgep->rx_hio_groups[i].started) 3845da14cebeSEric Cheng return (B_FALSE); 3846da14cebeSEric Cheng } 3847da14cebeSEric Cheng 3848da14cebeSEric Cheng return (B_TRUE); 3849da14cebeSEric Cheng } 3850da14cebeSEric Cheng 385144961713Sgirish /* 385244961713Sgirish * nxge_m_stop(): stop transmitting and receiving. 385344961713Sgirish */ 385444961713Sgirish static void 385544961713Sgirish nxge_m_stop(void *arg) 385644961713Sgirish { 3857*86ef0a63SRichard Lowe p_nxge_t nxgep = (p_nxge_t)arg; 3858da14cebeSEric Cheng boolean_t groups_stopped; 385944961713Sgirish 386044961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_stop")); 386144961713Sgirish 3862e759c33aSMichael Speer /* 3863e759c33aSMichael Speer * Are the groups stopped? 3864e759c33aSMichael Speer */ 3865da14cebeSEric Cheng groups_stopped = nxge_check_groups_stopped(nxgep); 3866e759c33aSMichael Speer ASSERT(groups_stopped == B_TRUE); 3867da14cebeSEric Cheng if (!groups_stopped) { 3868da14cebeSEric Cheng cmn_err(CE_WARN, "nxge(%d): groups are not stopped!\n", 3869da14cebeSEric Cheng nxgep->instance); 3870da14cebeSEric Cheng return; 3871da14cebeSEric Cheng } 3872da14cebeSEric Cheng 3873e759c33aSMichael Speer if (!isLDOMguest(nxgep)) { 3874e759c33aSMichael Speer /* 3875e759c33aSMichael Speer * Disable the RX mac. 3876e759c33aSMichael Speer */ 3877e759c33aSMichael Speer (void) nxge_rx_mac_disable(nxgep); 3878e759c33aSMichael Speer 3879e759c33aSMichael Speer /* 3880e759c33aSMichael Speer * Wait for the IPP to drain. 3881e759c33aSMichael Speer */ 3882e759c33aSMichael Speer (void) nxge_ipp_drain(nxgep); 3883e759c33aSMichael Speer 3884e759c33aSMichael Speer /* 3885e759c33aSMichael Speer * Disable hardware interrupts. 3886e759c33aSMichael Speer */ 3887e759c33aSMichael Speer nxge_intr_hw_disable(nxgep); 3888e759c33aSMichael Speer } 3889e759c33aSMichael Speer #if defined(sun4v) 3890e759c33aSMichael Speer else { 3891e759c33aSMichael Speer (void) nxge_hio_rdc_intr_arm(nxgep, B_FALSE); 3892e759c33aSMichael Speer } 3893e759c33aSMichael Speer #endif 3894e759c33aSMichael Speer 3895e759c33aSMichael Speer /* 3896e759c33aSMichael Speer * Grab the global lock. 3897e759c33aSMichael Speer */ 3898d7cf53fcSmisaki Miyashita MUTEX_ENTER(nxgep->genlock); 3899d7cf53fcSmisaki Miyashita 3900e759c33aSMichael Speer nxgep->nxge_mac_state = NXGE_MAC_STOPPING; 390144961713Sgirish if (nxgep->nxge_timerid) { 390244961713Sgirish nxge_stop_timer(nxgep, nxgep->nxge_timerid); 390344961713Sgirish nxgep->nxge_timerid = 0; 390444961713Sgirish } 3905a3c5bd6dSspeer 3906e759c33aSMichael Speer /* 3907e759c33aSMichael Speer * Clean up. 3908e759c33aSMichael Speer */ 390944961713Sgirish nxge_uninit(nxgep); 391044961713Sgirish 391144961713Sgirish nxgep->nxge_mac_state = NXGE_MAC_STOPPED; 391244961713Sgirish 3913e759c33aSMichael Speer /* 3914e759c33aSMichael Speer * Let go of the global lock. 3915e759c33aSMichael Speer */ 391644961713Sgirish MUTEX_EXIT(nxgep->genlock); 391744961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_stop")); 391844961713Sgirish } 391944961713Sgirish 392044961713Sgirish static int 392144961713Sgirish nxge_m_multicst(void *arg, boolean_t add, const uint8_t *mca) 392244961713Sgirish { 3923*86ef0a63SRichard Lowe p_nxge_t nxgep = (p_nxge_t)arg; 3924*86ef0a63SRichard Lowe struct ether_addr addrp; 392544961713Sgirish 392644961713Sgirish NXGE_DEBUG_MSG((nxgep, MAC_CTL, 39274045d941Ssowmini "==> nxge_m_multicst: add %d", add)); 392844961713Sgirish 392944961713Sgirish bcopy(mca, (uint8_t *)&addrp, ETHERADDRL); 393044961713Sgirish if (add) { 393144961713Sgirish if (nxge_add_mcast_addr(nxgep, &addrp)) { 393244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 39334045d941Ssowmini "<== nxge_m_multicst: add multicast failed")); 393444961713Sgirish return (EINVAL); 393544961713Sgirish } 393644961713Sgirish } else { 393744961713Sgirish if (nxge_del_mcast_addr(nxgep, &addrp)) { 393844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 39394045d941Ssowmini "<== nxge_m_multicst: del multicast failed")); 394044961713Sgirish return (EINVAL); 394144961713Sgirish } 394244961713Sgirish } 394344961713Sgirish 394444961713Sgirish NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_m_multicst")); 394544961713Sgirish 394644961713Sgirish return (0); 394744961713Sgirish } 394844961713Sgirish 394944961713Sgirish static int 395044961713Sgirish nxge_m_promisc(void *arg, boolean_t on) 395144961713Sgirish { 3952*86ef0a63SRichard Lowe p_nxge_t nxgep = (p_nxge_t)arg; 395344961713Sgirish 395444961713Sgirish NXGE_DEBUG_MSG((nxgep, MAC_CTL, 39554045d941Ssowmini "==> nxge_m_promisc: on %d", on)); 395644961713Sgirish 395744961713Sgirish if (nxge_set_promisc(nxgep, on)) { 395844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 39594045d941Ssowmini "<== nxge_m_promisc: set promisc failed")); 396044961713Sgirish return (EINVAL); 396144961713Sgirish } 396244961713Sgirish 396344961713Sgirish NXGE_DEBUG_MSG((nxgep, MAC_CTL, 39644045d941Ssowmini "<== nxge_m_promisc: on %d", on)); 396544961713Sgirish 396644961713Sgirish return (0); 396744961713Sgirish } 396844961713Sgirish 396944961713Sgirish static void 3970*86ef0a63SRichard Lowe nxge_m_ioctl(void *arg, queue_t *wq, mblk_t *mp) 397144961713Sgirish { 3972*86ef0a63SRichard Lowe p_nxge_t nxgep = (p_nxge_t)arg; 3973*86ef0a63SRichard Lowe struct iocblk *iocp; 3974*86ef0a63SRichard Lowe boolean_t need_privilege; 3975*86ef0a63SRichard Lowe int err; 3976*86ef0a63SRichard Lowe int cmd; 397744961713Sgirish 397844961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_ioctl")); 397944961713Sgirish 398044961713Sgirish iocp = (struct iocblk *)mp->b_rptr; 398144961713Sgirish iocp->ioc_error = 0; 398244961713Sgirish need_privilege = B_TRUE; 398344961713Sgirish cmd = iocp->ioc_cmd; 398444961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_ioctl: cmd 0x%08x", cmd)); 398544961713Sgirish switch (cmd) { 398644961713Sgirish default: 398744961713Sgirish miocnak(wq, mp, 0, EINVAL); 398844961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_ioctl: invalid")); 398944961713Sgirish return; 399044961713Sgirish 399144961713Sgirish case LB_GET_INFO_SIZE: 399244961713Sgirish case LB_GET_INFO: 399344961713Sgirish case LB_GET_MODE: 399444961713Sgirish need_privilege = B_FALSE; 399544961713Sgirish break; 399644961713Sgirish case LB_SET_MODE: 399744961713Sgirish break; 399844961713Sgirish 399944961713Sgirish 400044961713Sgirish case NXGE_GET_MII: 400144961713Sgirish case NXGE_PUT_MII: 400244961713Sgirish case NXGE_GET64: 400344961713Sgirish case NXGE_PUT64: 400444961713Sgirish case NXGE_GET_TX_RING_SZ: 400544961713Sgirish case NXGE_GET_TX_DESC: 400644961713Sgirish case NXGE_TX_SIDE_RESET: 400744961713Sgirish case NXGE_RX_SIDE_RESET: 400844961713Sgirish case NXGE_GLOBAL_RESET: 400944961713Sgirish case NXGE_RESET_MAC: 401044961713Sgirish case NXGE_TX_REGS_DUMP: 401144961713Sgirish case NXGE_RX_REGS_DUMP: 401244961713Sgirish case NXGE_INT_REGS_DUMP: 401344961713Sgirish case NXGE_VIR_INT_REGS_DUMP: 401444961713Sgirish case NXGE_PUT_TCAM: 401544961713Sgirish case NXGE_GET_TCAM: 401644961713Sgirish case NXGE_RTRACE: 401744961713Sgirish case NXGE_RDUMP: 40184df55fdeSJanie Lu case NXGE_RX_CLASS: 40194df55fdeSJanie Lu case NXGE_RX_HASH: 402044961713Sgirish 402144961713Sgirish need_privilege = B_FALSE; 402244961713Sgirish break; 402344961713Sgirish case NXGE_INJECT_ERR: 402444961713Sgirish cmn_err(CE_NOTE, "!nxge_m_ioctl: Inject error\n"); 402544961713Sgirish nxge_err_inject(nxgep, wq, mp); 402644961713Sgirish break; 402744961713Sgirish } 402844961713Sgirish 402944961713Sgirish if (need_privilege) { 403056d930aeSspeer err = secpolicy_net_config(iocp->ioc_cr, B_FALSE); 403144961713Sgirish if (err != 0) { 403244961713Sgirish miocnak(wq, mp, 0, err); 403344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 40344045d941Ssowmini "<== nxge_m_ioctl: no priv")); 403544961713Sgirish return; 403644961713Sgirish } 403744961713Sgirish } 403844961713Sgirish 403944961713Sgirish switch (cmd) { 404044961713Sgirish 404144961713Sgirish case LB_GET_MODE: 404244961713Sgirish case LB_SET_MODE: 404344961713Sgirish case LB_GET_INFO_SIZE: 404444961713Sgirish case LB_GET_INFO: 404544961713Sgirish nxge_loopback_ioctl(nxgep, wq, mp, iocp); 404644961713Sgirish break; 404744961713Sgirish 404844961713Sgirish case NXGE_GET_MII: 404944961713Sgirish case NXGE_PUT_MII: 405044961713Sgirish case NXGE_PUT_TCAM: 405144961713Sgirish case NXGE_GET_TCAM: 405244961713Sgirish case NXGE_GET64: 405344961713Sgirish case NXGE_PUT64: 405444961713Sgirish case NXGE_GET_TX_RING_SZ: 405544961713Sgirish case NXGE_GET_TX_DESC: 405644961713Sgirish case NXGE_TX_SIDE_RESET: 405744961713Sgirish case NXGE_RX_SIDE_RESET: 405844961713Sgirish case NXGE_GLOBAL_RESET: 405944961713Sgirish case NXGE_RESET_MAC: 406044961713Sgirish case NXGE_TX_REGS_DUMP: 406144961713Sgirish case NXGE_RX_REGS_DUMP: 406244961713Sgirish case NXGE_INT_REGS_DUMP: 406344961713Sgirish case NXGE_VIR_INT_REGS_DUMP: 406444961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 40654045d941Ssowmini "==> nxge_m_ioctl: cmd 0x%x", cmd)); 406644961713Sgirish nxge_hw_ioctl(nxgep, wq, mp, iocp); 406744961713Sgirish break; 40684df55fdeSJanie Lu case NXGE_RX_CLASS: 40694df55fdeSJanie Lu if (nxge_rxclass_ioctl(nxgep, wq, mp->b_cont) < 0) 40704df55fdeSJanie Lu miocnak(wq, mp, 0, EINVAL); 40714df55fdeSJanie Lu else 40724df55fdeSJanie Lu miocack(wq, mp, sizeof (rx_class_cfg_t), 0); 40734df55fdeSJanie Lu break; 40744df55fdeSJanie Lu case NXGE_RX_HASH: 40754df55fdeSJanie Lu 40764df55fdeSJanie Lu if (nxge_rxhash_ioctl(nxgep, wq, mp->b_cont) < 0) 40774df55fdeSJanie Lu miocnak(wq, mp, 0, EINVAL); 40784df55fdeSJanie Lu else 40794df55fdeSJanie Lu miocack(wq, mp, sizeof (cfg_cmd_t), 0); 40804df55fdeSJanie Lu break; 408144961713Sgirish } 408244961713Sgirish 408344961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_ioctl")); 408444961713Sgirish } 408544961713Sgirish 408644961713Sgirish extern void nxge_rx_hw_blank(void *arg, time_t ticks, uint_t count); 408744961713Sgirish 4088678453a8Sspeer void 4089da14cebeSEric Cheng nxge_mmac_kstat_update(p_nxge_t nxgep, int slot, boolean_t factory) 409058324dfcSspeer { 409158324dfcSspeer p_nxge_mmac_stats_t mmac_stats; 409258324dfcSspeer int i; 409358324dfcSspeer nxge_mmac_t *mmac_info; 409458324dfcSspeer 409558324dfcSspeer mmac_info = &nxgep->nxge_mmac_info; 409658324dfcSspeer 409758324dfcSspeer mmac_stats = &nxgep->statsp->mmac_stats; 409858324dfcSspeer mmac_stats->mmac_max_cnt = mmac_info->num_mmac; 409958324dfcSspeer mmac_stats->mmac_avail_cnt = mmac_info->naddrfree; 410058324dfcSspeer 410158324dfcSspeer for (i = 0; i < ETHERADDRL; i++) { 410258324dfcSspeer if (factory) { 410358324dfcSspeer mmac_stats->mmac_avail_pool[slot-1].ether_addr_octet[i] 41044045d941Ssowmini = mmac_info->factory_mac_pool[slot][ 41054045d941Ssowmini (ETHERADDRL-1) - i]; 410658324dfcSspeer } else { 410758324dfcSspeer mmac_stats->mmac_avail_pool[slot-1].ether_addr_octet[i] 41084045d941Ssowmini = mmac_info->mac_pool[slot].addr[ 41094045d941Ssowmini (ETHERADDRL - 1) - i]; 411058324dfcSspeer } 411158324dfcSspeer } 411258324dfcSspeer } 411358324dfcSspeer 411458324dfcSspeer /* 411558324dfcSspeer * nxge_altmac_set() -- Set an alternate MAC address 411658324dfcSspeer */ 4117da14cebeSEric Cheng static int 4118da14cebeSEric Cheng nxge_altmac_set(p_nxge_t nxgep, uint8_t *maddr, int slot, 4119*86ef0a63SRichard Lowe int rdctbl, boolean_t usetbl) 412058324dfcSspeer { 412158324dfcSspeer uint8_t addrn; 412258324dfcSspeer uint8_t portn; 412358324dfcSspeer npi_mac_addr_t altmac; 41247b9fa28bSspeer hostinfo_t mac_rdc; 41257b9fa28bSspeer p_nxge_class_pt_cfg_t clscfgp; 412658324dfcSspeer 4127da14cebeSEric Cheng 412858324dfcSspeer altmac.w2 = ((uint16_t)maddr[0] << 8) | ((uint16_t)maddr[1] & 0x0ff); 412958324dfcSspeer altmac.w1 = ((uint16_t)maddr[2] << 8) | ((uint16_t)maddr[3] & 0x0ff); 413058324dfcSspeer altmac.w0 = ((uint16_t)maddr[4] << 8) | ((uint16_t)maddr[5] & 0x0ff); 413158324dfcSspeer 413258324dfcSspeer portn = nxgep->mac.portnum; 413358324dfcSspeer addrn = (uint8_t)slot - 1; 413458324dfcSspeer 4135da14cebeSEric Cheng if (npi_mac_altaddr_entry(nxgep->npi_handle, OP_SET, 4136da14cebeSEric Cheng nxgep->function_num, addrn, &altmac) != NPI_SUCCESS) 413758324dfcSspeer return (EIO); 41387b9fa28bSspeer 41397b9fa28bSspeer /* 41407b9fa28bSspeer * Set the rdc table number for the host info entry 41417b9fa28bSspeer * for this mac address slot. 41427b9fa28bSspeer */ 41437b9fa28bSspeer clscfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 41447b9fa28bSspeer mac_rdc.value = 0; 4145da14cebeSEric Cheng if (usetbl) 4146da14cebeSEric Cheng mac_rdc.bits.w0.rdc_tbl_num = rdctbl; 4147da14cebeSEric Cheng else 4148da14cebeSEric Cheng mac_rdc.bits.w0.rdc_tbl_num = 4149da14cebeSEric Cheng clscfgp->mac_host_info[addrn].rdctbl; 41507b9fa28bSspeer mac_rdc.bits.w0.mac_pref = clscfgp->mac_host_info[addrn].mpr_npr; 41517b9fa28bSspeer 41527b9fa28bSspeer if (npi_mac_hostinfo_entry(nxgep->npi_handle, OP_SET, 41537b9fa28bSspeer nxgep->function_num, addrn, &mac_rdc) != NPI_SUCCESS) { 41547b9fa28bSspeer return (EIO); 41557b9fa28bSspeer } 41567b9fa28bSspeer 415758324dfcSspeer /* 415858324dfcSspeer * Enable comparison with the alternate MAC address. 415958324dfcSspeer * While the first alternate addr is enabled by bit 1 of register 416058324dfcSspeer * BMAC_ALTAD_CMPEN, it is enabled by bit 0 of register 416158324dfcSspeer * XMAC_ADDR_CMPEN, so slot needs to be converted to addrn 416258324dfcSspeer * accordingly before calling npi_mac_altaddr_entry. 416358324dfcSspeer */ 416458324dfcSspeer if (portn == XMAC_PORT_0 || portn == XMAC_PORT_1) 416558324dfcSspeer addrn = (uint8_t)slot - 1; 416658324dfcSspeer else 416758324dfcSspeer addrn = (uint8_t)slot; 416858324dfcSspeer 4169da14cebeSEric Cheng if (npi_mac_altaddr_enable(nxgep->npi_handle, 4170da14cebeSEric Cheng nxgep->function_num, addrn) != NPI_SUCCESS) { 417158324dfcSspeer return (EIO); 4172da14cebeSEric Cheng } 4173da14cebeSEric Cheng 417458324dfcSspeer return (0); 417558324dfcSspeer } 417658324dfcSspeer 417758324dfcSspeer /* 4178da14cebeSEric Cheng * nxeg_m_mmac_add_g() - find an unused address slot, set the address 417958324dfcSspeer * value to the one specified, enable the port to start filtering on 4180*86ef0a63SRichard Lowe * the new MAC address. Returns 0 on success. 418158324dfcSspeer */ 4182678453a8Sspeer int 4183da14cebeSEric Cheng nxge_m_mmac_add_g(void *arg, const uint8_t *maddr, int rdctbl, 4184*86ef0a63SRichard Lowe boolean_t usetbl) 418558324dfcSspeer { 418658324dfcSspeer p_nxge_t nxgep = arg; 4187da14cebeSEric Cheng int slot; 418858324dfcSspeer nxge_mmac_t *mmac_info; 418958324dfcSspeer int err; 419058324dfcSspeer nxge_status_t status; 419158324dfcSspeer 419258324dfcSspeer mutex_enter(nxgep->genlock); 419358324dfcSspeer 419458324dfcSspeer /* 419558324dfcSspeer * Make sure that nxge is initialized, if _start() has 419658324dfcSspeer * not been called. 419758324dfcSspeer */ 419858324dfcSspeer if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 419958324dfcSspeer status = nxge_init(nxgep); 420058324dfcSspeer if (status != NXGE_OK) { 420158324dfcSspeer mutex_exit(nxgep->genlock); 420258324dfcSspeer return (ENXIO); 420358324dfcSspeer } 420458324dfcSspeer } 420558324dfcSspeer 420658324dfcSspeer mmac_info = &nxgep->nxge_mmac_info; 420758324dfcSspeer if (mmac_info->naddrfree == 0) { 420858324dfcSspeer mutex_exit(nxgep->genlock); 420958324dfcSspeer return (ENOSPC); 421058324dfcSspeer } 4211da14cebeSEric Cheng 421258324dfcSspeer /* 4213*86ef0a63SRichard Lowe * Search for the first available slot. Because naddrfree 421458324dfcSspeer * is not zero, we are guaranteed to find one. 421558324dfcSspeer * Each of the first two ports of Neptune has 16 alternate 4216678453a8Sspeer * MAC slots but only the first 7 (of 15) slots have assigned factory 421758324dfcSspeer * MAC addresses. We first search among the slots without bundled 421858324dfcSspeer * factory MACs. If we fail to find one in that range, then we 4219*86ef0a63SRichard Lowe * search the slots with bundled factory MACs. A factory MAC 422058324dfcSspeer * will be wasted while the slot is used with a user MAC address. 422158324dfcSspeer * But the slot could be used by factory MAC again after calling 422258324dfcSspeer * nxge_m_mmac_remove and nxge_m_mmac_reserve. 422358324dfcSspeer */ 4224da14cebeSEric Cheng for (slot = 0; slot <= mmac_info->num_mmac; slot++) { 4225da14cebeSEric Cheng if (!(mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED)) 4226da14cebeSEric Cheng break; 422758324dfcSspeer } 4228da14cebeSEric Cheng 422958324dfcSspeer ASSERT(slot <= mmac_info->num_mmac); 4230e857d0f3SMichael Speer 4231da14cebeSEric Cheng if ((err = nxge_altmac_set(nxgep, (uint8_t *)maddr, slot, rdctbl, 4232da14cebeSEric Cheng usetbl)) != 0) { 423358324dfcSspeer mutex_exit(nxgep->genlock); 423458324dfcSspeer return (err); 423558324dfcSspeer } 4236e857d0f3SMichael Speer 4237da14cebeSEric Cheng bcopy(maddr, mmac_info->mac_pool[slot].addr, ETHERADDRL); 423858324dfcSspeer mmac_info->mac_pool[slot].flags |= MMAC_SLOT_USED; 423958324dfcSspeer mmac_info->mac_pool[slot].flags &= ~MMAC_VENDOR_ADDR; 424058324dfcSspeer mmac_info->naddrfree--; 424158324dfcSspeer nxge_mmac_kstat_update(nxgep, slot, B_FALSE); 424258324dfcSspeer 424358324dfcSspeer mutex_exit(nxgep->genlock); 424458324dfcSspeer return (0); 424558324dfcSspeer } 424658324dfcSspeer 424758324dfcSspeer /* 424858324dfcSspeer * Remove the specified mac address and update the HW not to filter 424958324dfcSspeer * the mac address anymore. 425058324dfcSspeer */ 4251678453a8Sspeer int 4252da14cebeSEric Cheng nxge_m_mmac_remove(void *arg, int slot) 425358324dfcSspeer { 425458324dfcSspeer p_nxge_t nxgep = arg; 425558324dfcSspeer nxge_mmac_t *mmac_info; 425658324dfcSspeer uint8_t addrn; 425758324dfcSspeer uint8_t portn; 425858324dfcSspeer int err = 0; 425958324dfcSspeer nxge_status_t status; 426058324dfcSspeer 426158324dfcSspeer mutex_enter(nxgep->genlock); 426258324dfcSspeer 426358324dfcSspeer /* 426458324dfcSspeer * Make sure that nxge is initialized, if _start() has 426558324dfcSspeer * not been called. 426658324dfcSspeer */ 426758324dfcSspeer if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 426858324dfcSspeer status = nxge_init(nxgep); 426958324dfcSspeer if (status != NXGE_OK) { 427058324dfcSspeer mutex_exit(nxgep->genlock); 427158324dfcSspeer return (ENXIO); 427258324dfcSspeer } 427358324dfcSspeer } 427458324dfcSspeer 427558324dfcSspeer mmac_info = &nxgep->nxge_mmac_info; 427658324dfcSspeer if (slot < 1 || slot > mmac_info->num_mmac) { 427758324dfcSspeer mutex_exit(nxgep->genlock); 427858324dfcSspeer return (EINVAL); 427958324dfcSspeer } 428058324dfcSspeer 428158324dfcSspeer portn = nxgep->mac.portnum; 428258324dfcSspeer if (portn == XMAC_PORT_0 || portn == XMAC_PORT_1) 428358324dfcSspeer addrn = (uint8_t)slot - 1; 428458324dfcSspeer else 428558324dfcSspeer addrn = (uint8_t)slot; 428658324dfcSspeer 428758324dfcSspeer if (mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED) { 428858324dfcSspeer if (npi_mac_altaddr_disable(nxgep->npi_handle, portn, addrn) 42894045d941Ssowmini == NPI_SUCCESS) { 429058324dfcSspeer mmac_info->naddrfree++; 429158324dfcSspeer mmac_info->mac_pool[slot].flags &= ~MMAC_SLOT_USED; 429258324dfcSspeer /* 429358324dfcSspeer * Regardless if the MAC we just stopped filtering 429458324dfcSspeer * is a user addr or a facory addr, we must set 429558324dfcSspeer * the MMAC_VENDOR_ADDR flag if this slot has an 429658324dfcSspeer * associated factory MAC to indicate that a factory 429758324dfcSspeer * MAC is available. 429858324dfcSspeer */ 429958324dfcSspeer if (slot <= mmac_info->num_factory_mmac) { 430058324dfcSspeer mmac_info->mac_pool[slot].flags 43014045d941Ssowmini |= MMAC_VENDOR_ADDR; 430258324dfcSspeer } 430358324dfcSspeer /* 430458324dfcSspeer * Clear mac_pool[slot].addr so that kstat shows 0 430558324dfcSspeer * alternate MAC address if the slot is not used. 430658324dfcSspeer * (But nxge_m_mmac_get returns the factory MAC even 430758324dfcSspeer * when the slot is not used!) 430858324dfcSspeer */ 430958324dfcSspeer bzero(mmac_info->mac_pool[slot].addr, ETHERADDRL); 431058324dfcSspeer nxge_mmac_kstat_update(nxgep, slot, B_FALSE); 431158324dfcSspeer } else { 431258324dfcSspeer err = EIO; 431358324dfcSspeer } 431458324dfcSspeer } else { 431558324dfcSspeer err = EINVAL; 431658324dfcSspeer } 431758324dfcSspeer 431858324dfcSspeer mutex_exit(nxgep->genlock); 431958324dfcSspeer return (err); 432058324dfcSspeer } 432158324dfcSspeer 432258324dfcSspeer /* 4323da14cebeSEric Cheng * The callback to query all the factory addresses. naddr must be the same as 4324da14cebeSEric Cheng * the number of factory addresses (returned by MAC_CAPAB_MULTIFACTADDR), and 4325da14cebeSEric Cheng * mcm_addr is the space allocated for keep all the addresses, whose size is 4326da14cebeSEric Cheng * naddr * MAXMACADDRLEN. 432758324dfcSspeer */ 4328da14cebeSEric Cheng static void 4329da14cebeSEric Cheng nxge_m_getfactaddr(void *arg, uint_t naddr, uint8_t *addr) 433058324dfcSspeer { 4331da14cebeSEric Cheng nxge_t *nxgep = arg; 4332da14cebeSEric Cheng nxge_mmac_t *mmac_info; 4333da14cebeSEric Cheng int i; 433458324dfcSspeer 433558324dfcSspeer mutex_enter(nxgep->genlock); 433658324dfcSspeer 433758324dfcSspeer mmac_info = &nxgep->nxge_mmac_info; 4338da14cebeSEric Cheng ASSERT(naddr == mmac_info->num_factory_mmac); 433958324dfcSspeer 4340da14cebeSEric Cheng for (i = 0; i < naddr; i++) { 4341da14cebeSEric Cheng bcopy(mmac_info->factory_mac_pool[i + 1], 4342da14cebeSEric Cheng addr + i * MAXMACADDRLEN, ETHERADDRL); 434358324dfcSspeer } 434458324dfcSspeer 434558324dfcSspeer mutex_exit(nxgep->genlock); 434658324dfcSspeer } 434758324dfcSspeer 4348da14cebeSEric Cheng 434944961713Sgirish static boolean_t 435044961713Sgirish nxge_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 435144961713Sgirish { 435258324dfcSspeer nxge_t *nxgep = arg; 435358324dfcSspeer uint32_t *txflags = cap_data; 435444961713Sgirish 435558324dfcSspeer switch (cap) { 435658324dfcSspeer case MAC_CAPAB_HCKSUM: 4357678453a8Sspeer NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4358b4d05839Sml "==> nxge_m_getcapab: checksum %d", nxge_cksum_offload)); 4359b4d05839Sml if (nxge_cksum_offload <= 1) { 4360678453a8Sspeer *txflags = HCKSUM_INET_PARTIAL; 4361678453a8Sspeer } 436244961713Sgirish break; 4363678453a8Sspeer 4364da14cebeSEric Cheng case MAC_CAPAB_MULTIFACTADDR: { 4365da14cebeSEric Cheng mac_capab_multifactaddr_t *mfacp = cap_data; 436644961713Sgirish 436763f531d1SSriharsha Basavapatna if (!isLDOMguest(nxgep)) { 436863f531d1SSriharsha Basavapatna mutex_enter(nxgep->genlock); 436963f531d1SSriharsha Basavapatna mfacp->mcm_naddr = 437063f531d1SSriharsha Basavapatna nxgep->nxge_mmac_info.num_factory_mmac; 437163f531d1SSriharsha Basavapatna mfacp->mcm_getaddr = nxge_m_getfactaddr; 437263f531d1SSriharsha Basavapatna mutex_exit(nxgep->genlock); 437363f531d1SSriharsha Basavapatna } 437458324dfcSspeer break; 4375da14cebeSEric Cheng } 4376678453a8Sspeer 437730ac2e7bSml case MAC_CAPAB_LSO: { 437830ac2e7bSml mac_capab_lso_t *cap_lso = cap_data; 437930ac2e7bSml 43803d16f8e7Sml if (nxgep->soft_lso_enable) { 4381b4d05839Sml if (nxge_cksum_offload <= 1) { 4382b4d05839Sml cap_lso->lso_flags = LSO_TX_BASIC_TCP_IPV4; 4383b4d05839Sml if (nxge_lso_max > NXGE_LSO_MAXLEN) { 4384b4d05839Sml nxge_lso_max = NXGE_LSO_MAXLEN; 4385b4d05839Sml } 4386b4d05839Sml cap_lso->lso_basic_tcp_ipv4.lso_max = 4387b4d05839Sml nxge_lso_max; 438830ac2e7bSml } 438930ac2e7bSml break; 439030ac2e7bSml } else { 439130ac2e7bSml return (B_FALSE); 439230ac2e7bSml } 439330ac2e7bSml } 439430ac2e7bSml 4395678453a8Sspeer case MAC_CAPAB_RINGS: { 4396da14cebeSEric Cheng mac_capab_rings_t *cap_rings = cap_data; 4397da14cebeSEric Cheng p_nxge_hw_pt_cfg_t p_cfgp = &nxgep->pt_config.hw_config; 4398678453a8Sspeer 4399da14cebeSEric Cheng mutex_enter(nxgep->genlock); 4400da14cebeSEric Cheng if (cap_rings->mr_type == MAC_RING_TYPE_RX) { 4401*86ef0a63SRichard Lowe if (isLDOMguest(nxgep)) { 440263f531d1SSriharsha Basavapatna cap_rings->mr_group_type = 440363f531d1SSriharsha Basavapatna MAC_GROUP_TYPE_STATIC; 440463f531d1SSriharsha Basavapatna cap_rings->mr_rnum = 440563f531d1SSriharsha Basavapatna NXGE_HIO_SHARE_MAX_CHANNELS; 440663f531d1SSriharsha Basavapatna cap_rings->mr_rget = nxge_fill_ring; 440763f531d1SSriharsha Basavapatna cap_rings->mr_gnum = 1; 440863f531d1SSriharsha Basavapatna cap_rings->mr_gget = nxge_hio_group_get; 440963f531d1SSriharsha Basavapatna cap_rings->mr_gaddring = NULL; 441063f531d1SSriharsha Basavapatna cap_rings->mr_gremring = NULL; 441163f531d1SSriharsha Basavapatna } else { 441263f531d1SSriharsha Basavapatna /* 441363f531d1SSriharsha Basavapatna * Service Domain. 441463f531d1SSriharsha Basavapatna */ 441563f531d1SSriharsha Basavapatna cap_rings->mr_group_type = 441663f531d1SSriharsha Basavapatna MAC_GROUP_TYPE_DYNAMIC; 441763f531d1SSriharsha Basavapatna cap_rings->mr_rnum = p_cfgp->max_rdcs; 441863f531d1SSriharsha Basavapatna cap_rings->mr_rget = nxge_fill_ring; 441963f531d1SSriharsha Basavapatna cap_rings->mr_gnum = p_cfgp->max_rdc_grpids; 442063f531d1SSriharsha Basavapatna cap_rings->mr_gget = nxge_hio_group_get; 442163f531d1SSriharsha Basavapatna cap_rings->mr_gaddring = nxge_group_add_ring; 442263f531d1SSriharsha Basavapatna cap_rings->mr_gremring = nxge_group_rem_ring; 442363f531d1SSriharsha Basavapatna } 4424da14cebeSEric Cheng 4425da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, RX_CTL, 4426da14cebeSEric Cheng "==> nxge_m_getcapab: rx nrings[%d] ngroups[%d]", 4427da14cebeSEric Cheng p_cfgp->max_rdcs, p_cfgp->max_rdc_grpids)); 4428da14cebeSEric Cheng } else { 442963f531d1SSriharsha Basavapatna /* 443063f531d1SSriharsha Basavapatna * TX Rings. 443163f531d1SSriharsha Basavapatna */ 443263f531d1SSriharsha Basavapatna if (isLDOMguest(nxgep)) { 443363f531d1SSriharsha Basavapatna cap_rings->mr_group_type = 443463f531d1SSriharsha Basavapatna MAC_GROUP_TYPE_STATIC; 443563f531d1SSriharsha Basavapatna cap_rings->mr_rnum = 443663f531d1SSriharsha Basavapatna NXGE_HIO_SHARE_MAX_CHANNELS; 443763f531d1SSriharsha Basavapatna cap_rings->mr_rget = nxge_fill_ring; 443863f531d1SSriharsha Basavapatna cap_rings->mr_gnum = 0; 443963f531d1SSriharsha Basavapatna cap_rings->mr_gget = NULL; 444063f531d1SSriharsha Basavapatna cap_rings->mr_gaddring = NULL; 444163f531d1SSriharsha Basavapatna cap_rings->mr_gremring = NULL; 444263f531d1SSriharsha Basavapatna } else { 444363f531d1SSriharsha Basavapatna /* 444463f531d1SSriharsha Basavapatna * Service Domain. 444563f531d1SSriharsha Basavapatna */ 444663f531d1SSriharsha Basavapatna cap_rings->mr_group_type = 444763f531d1SSriharsha Basavapatna MAC_GROUP_TYPE_DYNAMIC; 444863f531d1SSriharsha Basavapatna cap_rings->mr_rnum = p_cfgp->tdc.count; 444963f531d1SSriharsha Basavapatna cap_rings->mr_rget = nxge_fill_ring; 445063f531d1SSriharsha Basavapatna 445163f531d1SSriharsha Basavapatna /* 445263f531d1SSriharsha Basavapatna * Share capable. 445363f531d1SSriharsha Basavapatna * 445463f531d1SSriharsha Basavapatna * Do not report the default group: hence -1 445563f531d1SSriharsha Basavapatna */ 4456da14cebeSEric Cheng cap_rings->mr_gnum = 4457da14cebeSEric Cheng NXGE_MAX_TDC_GROUPS / nxgep->nports - 1; 445863f531d1SSriharsha Basavapatna cap_rings->mr_gget = nxge_hio_group_get; 445963f531d1SSriharsha Basavapatna cap_rings->mr_gaddring = nxge_group_add_ring; 446063f531d1SSriharsha Basavapatna cap_rings->mr_gremring = nxge_group_rem_ring; 4461678453a8Sspeer } 4462da14cebeSEric Cheng 4463da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, TX_CTL, 4464da14cebeSEric Cheng "==> nxge_m_getcapab: tx rings # of rings %d", 4465da14cebeSEric Cheng p_cfgp->tdc.count)); 4466da14cebeSEric Cheng } 4467da14cebeSEric Cheng mutex_exit(nxgep->genlock); 4468678453a8Sspeer break; 4469678453a8Sspeer } 4470678453a8Sspeer 4471da14cebeSEric Cheng #if defined(sun4v) 4472678453a8Sspeer case MAC_CAPAB_SHARES: { 4473678453a8Sspeer mac_capab_share_t *mshares = (mac_capab_share_t *)cap_data; 4474678453a8Sspeer 4475678453a8Sspeer /* 4476678453a8Sspeer * Only the service domain driver responds to 4477678453a8Sspeer * this capability request. 4478678453a8Sspeer */ 4479da14cebeSEric Cheng mutex_enter(nxgep->genlock); 4480678453a8Sspeer if (isLDOMservice(nxgep)) { 4481678453a8Sspeer mshares->ms_snum = 3; 4482678453a8Sspeer mshares->ms_handle = (void *)nxgep; 4483678453a8Sspeer mshares->ms_salloc = nxge_hio_share_alloc; 4484678453a8Sspeer mshares->ms_sfree = nxge_hio_share_free; 4485da14cebeSEric Cheng mshares->ms_sadd = nxge_hio_share_add_group; 4486da14cebeSEric Cheng mshares->ms_sremove = nxge_hio_share_rem_group; 4487678453a8Sspeer mshares->ms_squery = nxge_hio_share_query; 4488da14cebeSEric Cheng mshares->ms_sbind = nxge_hio_share_bind; 4489da14cebeSEric Cheng mshares->ms_sunbind = nxge_hio_share_unbind; 4490da14cebeSEric Cheng mutex_exit(nxgep->genlock); 4491da14cebeSEric Cheng } else { 4492da14cebeSEric Cheng mutex_exit(nxgep->genlock); 4493678453a8Sspeer return (B_FALSE); 4494da14cebeSEric Cheng } 4495678453a8Sspeer break; 4496678453a8Sspeer } 4497678453a8Sspeer #endif 449844961713Sgirish default: 449944961713Sgirish return (B_FALSE); 450044961713Sgirish } 450144961713Sgirish return (B_TRUE); 450244961713Sgirish } 450344961713Sgirish 45041bd6825cSml static boolean_t 45051bd6825cSml nxge_param_locked(mac_prop_id_t pr_num) 45061bd6825cSml { 45071bd6825cSml /* 45081bd6825cSml * All adv_* parameters are locked (read-only) while 45091bd6825cSml * the device is in any sort of loopback mode ... 45101bd6825cSml */ 45111bd6825cSml switch (pr_num) { 45123fd94f8cSam case MAC_PROP_ADV_1000FDX_CAP: 45133fd94f8cSam case MAC_PROP_EN_1000FDX_CAP: 45143fd94f8cSam case MAC_PROP_ADV_1000HDX_CAP: 45153fd94f8cSam case MAC_PROP_EN_1000HDX_CAP: 45163fd94f8cSam case MAC_PROP_ADV_100FDX_CAP: 45173fd94f8cSam case MAC_PROP_EN_100FDX_CAP: 45183fd94f8cSam case MAC_PROP_ADV_100HDX_CAP: 45193fd94f8cSam case MAC_PROP_EN_100HDX_CAP: 45203fd94f8cSam case MAC_PROP_ADV_10FDX_CAP: 45213fd94f8cSam case MAC_PROP_EN_10FDX_CAP: 45223fd94f8cSam case MAC_PROP_ADV_10HDX_CAP: 45233fd94f8cSam case MAC_PROP_EN_10HDX_CAP: 45243fd94f8cSam case MAC_PROP_AUTONEG: 45253fd94f8cSam case MAC_PROP_FLOWCTRL: 45261bd6825cSml return (B_TRUE); 45271bd6825cSml } 45281bd6825cSml return (B_FALSE); 45291bd6825cSml } 45301bd6825cSml 45311bd6825cSml /* 45321bd6825cSml * callback functions for set/get of properties 45331bd6825cSml */ 45341bd6825cSml static int 45351bd6825cSml nxge_m_setprop(void *barg, const char *pr_name, mac_prop_id_t pr_num, 45361bd6825cSml uint_t pr_valsize, const void *pr_val) 45371bd6825cSml { 45381bd6825cSml nxge_t *nxgep = barg; 45390dc2366fSVenugopal Iyer p_nxge_param_t param_arr = nxgep->param_arr; 45400dc2366fSVenugopal Iyer p_nxge_stats_t statsp = nxgep->statsp; 45411bd6825cSml int err = 0; 45421bd6825cSml 45431bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_setprop")); 45440dc2366fSVenugopal Iyer 45451bd6825cSml mutex_enter(nxgep->genlock); 45461bd6825cSml if (statsp->port_stats.lb_mode != nxge_lb_normal && 45471bd6825cSml nxge_param_locked(pr_num)) { 45481bd6825cSml /* 45491bd6825cSml * All adv_* parameters are locked (read-only) 45501bd6825cSml * while the device is in any sort of loopback mode. 45511bd6825cSml */ 45521bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 45531bd6825cSml "==> nxge_m_setprop: loopback mode: read only")); 45541bd6825cSml mutex_exit(nxgep->genlock); 45551bd6825cSml return (EBUSY); 45561bd6825cSml } 45571bd6825cSml 45581bd6825cSml switch (pr_num) { 45590dc2366fSVenugopal Iyer case MAC_PROP_EN_1000FDX_CAP: 45600dc2366fSVenugopal Iyer nxgep->param_en_1000fdx = 45610dc2366fSVenugopal Iyer param_arr[param_anar_1000fdx].value = *(uint8_t *)pr_val; 45620dc2366fSVenugopal Iyer goto reprogram; 45631bd6825cSml 45640dc2366fSVenugopal Iyer case MAC_PROP_EN_100FDX_CAP: 45650dc2366fSVenugopal Iyer nxgep->param_en_100fdx = 45660dc2366fSVenugopal Iyer param_arr[param_anar_100fdx].value = *(uint8_t *)pr_val; 45670dc2366fSVenugopal Iyer goto reprogram; 45681bd6825cSml 45690dc2366fSVenugopal Iyer case MAC_PROP_EN_10FDX_CAP: 45700dc2366fSVenugopal Iyer nxgep->param_en_10fdx = 45710dc2366fSVenugopal Iyer param_arr[param_anar_10fdx].value = *(uint8_t *)pr_val; 45720dc2366fSVenugopal Iyer goto reprogram; 45731bd6825cSml 45740dc2366fSVenugopal Iyer case MAC_PROP_AUTONEG: 45750dc2366fSVenugopal Iyer param_arr[param_autoneg].value = *(uint8_t *)pr_val; 45760dc2366fSVenugopal Iyer goto reprogram; 45771bd6825cSml 45780dc2366fSVenugopal Iyer case MAC_PROP_MTU: { 45790dc2366fSVenugopal Iyer uint32_t cur_mtu, new_mtu, old_framesize; 45801bd6825cSml 45810dc2366fSVenugopal Iyer cur_mtu = nxgep->mac.default_mtu; 45820dc2366fSVenugopal Iyer ASSERT(pr_valsize >= sizeof (new_mtu)); 45830dc2366fSVenugopal Iyer bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 45841bd6825cSml 45850dc2366fSVenugopal Iyer NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 45860dc2366fSVenugopal Iyer "==> nxge_m_setprop: set MTU: %d is_jumbo %d", 45870dc2366fSVenugopal Iyer new_mtu, nxgep->mac.is_jumbo)); 45881bd6825cSml 45890dc2366fSVenugopal Iyer if (new_mtu == cur_mtu) { 45900dc2366fSVenugopal Iyer err = 0; 45910dc2366fSVenugopal Iyer break; 45920dc2366fSVenugopal Iyer } 45931bd6825cSml 45940dc2366fSVenugopal Iyer if (nxgep->nxge_mac_state == NXGE_MAC_STARTED) { 45950dc2366fSVenugopal Iyer err = EBUSY; 45960dc2366fSVenugopal Iyer break; 45970dc2366fSVenugopal Iyer } 45981bd6825cSml 45990dc2366fSVenugopal Iyer if ((new_mtu < NXGE_DEFAULT_MTU) || 46000dc2366fSVenugopal Iyer (new_mtu > NXGE_MAXIMUM_MTU)) { 46010dc2366fSVenugopal Iyer err = EINVAL; 46020dc2366fSVenugopal Iyer break; 46030dc2366fSVenugopal Iyer } 460448056c53SMichael Speer 46050dc2366fSVenugopal Iyer old_framesize = (uint32_t)nxgep->mac.maxframesize; 46060dc2366fSVenugopal Iyer nxgep->mac.maxframesize = (uint16_t) 46070dc2366fSVenugopal Iyer (new_mtu + NXGE_EHEADER_VLAN_CRC); 46080dc2366fSVenugopal Iyer if (nxge_mac_set_framesize(nxgep)) { 46090dc2366fSVenugopal Iyer nxgep->mac.maxframesize = 46100dc2366fSVenugopal Iyer (uint16_t)old_framesize; 46110dc2366fSVenugopal Iyer err = EINVAL; 46120dc2366fSVenugopal Iyer break; 46130dc2366fSVenugopal Iyer } 46141bd6825cSml 46150dc2366fSVenugopal Iyer nxgep->mac.default_mtu = new_mtu; 46160dc2366fSVenugopal Iyer nxgep->mac.is_jumbo = (new_mtu > NXGE_DEFAULT_MTU); 46171bd6825cSml 46180dc2366fSVenugopal Iyer NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 46190dc2366fSVenugopal Iyer "==> nxge_m_setprop: set MTU: %d maxframe %d", 46200dc2366fSVenugopal Iyer new_mtu, nxgep->mac.maxframesize)); 46210dc2366fSVenugopal Iyer break; 46220dc2366fSVenugopal Iyer } 46231bd6825cSml 46240dc2366fSVenugopal Iyer case MAC_PROP_FLOWCTRL: { 46250dc2366fSVenugopal Iyer link_flowctrl_t fl; 46261bd6825cSml 46270dc2366fSVenugopal Iyer ASSERT(pr_valsize >= sizeof (fl)); 46280dc2366fSVenugopal Iyer bcopy(pr_val, &fl, sizeof (fl)); 462948056c53SMichael Speer 46300dc2366fSVenugopal Iyer switch (fl) { 46310dc2366fSVenugopal Iyer case LINK_FLOWCTRL_NONE: 46320dc2366fSVenugopal Iyer param_arr[param_anar_pause].value = 0; 46331bd6825cSml break; 46341bd6825cSml 46350dc2366fSVenugopal Iyer case LINK_FLOWCTRL_RX: 46360dc2366fSVenugopal Iyer param_arr[param_anar_pause].value = 1; 46370dc2366fSVenugopal Iyer break; 46381bd6825cSml 46390dc2366fSVenugopal Iyer case LINK_FLOWCTRL_TX: 46400dc2366fSVenugopal Iyer case LINK_FLOWCTRL_BI: 46410dc2366fSVenugopal Iyer err = EINVAL; 46420dc2366fSVenugopal Iyer break; 46430dc2366fSVenugopal Iyer default: 46440dc2366fSVenugopal Iyer err = EINVAL; 46450dc2366fSVenugopal Iyer break; 46460dc2366fSVenugopal Iyer } 46470dc2366fSVenugopal Iyer reprogram: 46480dc2366fSVenugopal Iyer if ((err == 0) && !isLDOMguest(nxgep)) { 46490dc2366fSVenugopal Iyer if (!nxge_param_link_update(nxgep)) { 46501bd6825cSml err = EINVAL; 46511bd6825cSml } 46520dc2366fSVenugopal Iyer } else { 46530dc2366fSVenugopal Iyer err = EINVAL; 46540dc2366fSVenugopal Iyer } 46550dc2366fSVenugopal Iyer break; 46560dc2366fSVenugopal Iyer } 46571bd6825cSml 46580dc2366fSVenugopal Iyer case MAC_PROP_PRIVATE: 46590dc2366fSVenugopal Iyer NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 46600dc2366fSVenugopal Iyer "==> nxge_m_setprop: private property")); 46610dc2366fSVenugopal Iyer err = nxge_set_priv_prop(nxgep, pr_name, pr_valsize, pr_val); 46620dc2366fSVenugopal Iyer break; 46634045d941Ssowmini 46640dc2366fSVenugopal Iyer default: 46650dc2366fSVenugopal Iyer err = ENOTSUP; 46660dc2366fSVenugopal Iyer break; 46671bd6825cSml } 46681bd6825cSml 46691bd6825cSml mutex_exit(nxgep->genlock); 46701bd6825cSml 46711bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 46721bd6825cSml "<== nxge_m_setprop (return %d)", err)); 46731bd6825cSml return (err); 46741bd6825cSml } 46751bd6825cSml 46761bd6825cSml static int 46771bd6825cSml nxge_m_getprop(void *barg, const char *pr_name, mac_prop_id_t pr_num, 46780dc2366fSVenugopal Iyer uint_t pr_valsize, void *pr_val) 46791bd6825cSml { 4680*86ef0a63SRichard Lowe nxge_t *nxgep = barg; 46811bd6825cSml p_nxge_param_t param_arr = nxgep->param_arr; 46821bd6825cSml p_nxge_stats_t statsp = nxgep->statsp; 46831bd6825cSml 46841bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 46851bd6825cSml "==> nxge_m_getprop: pr_num %d", pr_num)); 46864045d941Ssowmini 46870dc2366fSVenugopal Iyer switch (pr_num) { 46880dc2366fSVenugopal Iyer case MAC_PROP_DUPLEX: 46890dc2366fSVenugopal Iyer *(uint8_t *)pr_val = statsp->mac_stats.link_duplex; 46900dc2366fSVenugopal Iyer break; 46914045d941Ssowmini 46920dc2366fSVenugopal Iyer case MAC_PROP_SPEED: { 46930dc2366fSVenugopal Iyer uint64_t val = statsp->mac_stats.link_speed * 1000000ull; 4694afdda45fSVasumathi Sundaram - Sun Microsystems 46950dc2366fSVenugopal Iyer ASSERT(pr_valsize >= sizeof (val)); 46960dc2366fSVenugopal Iyer bcopy(&val, pr_val, sizeof (val)); 46970dc2366fSVenugopal Iyer break; 46984045d941Ssowmini } 46994045d941Ssowmini 47000dc2366fSVenugopal Iyer case MAC_PROP_STATUS: { 47010dc2366fSVenugopal Iyer link_state_t state = statsp->mac_stats.link_up ? 47020dc2366fSVenugopal Iyer LINK_STATE_UP : LINK_STATE_DOWN; 47031bd6825cSml 47040dc2366fSVenugopal Iyer ASSERT(pr_valsize >= sizeof (state)); 47050dc2366fSVenugopal Iyer bcopy(&state, pr_val, sizeof (state)); 47060dc2366fSVenugopal Iyer break; 47070dc2366fSVenugopal Iyer } 47081bd6825cSml 47090dc2366fSVenugopal Iyer case MAC_PROP_AUTONEG: 47100dc2366fSVenugopal Iyer *(uint8_t *)pr_val = param_arr[param_autoneg].value; 47110dc2366fSVenugopal Iyer break; 47121bd6825cSml 47130dc2366fSVenugopal Iyer case MAC_PROP_FLOWCTRL: { 47140dc2366fSVenugopal Iyer link_flowctrl_t fl = param_arr[param_anar_pause].value != 0 ? 47150dc2366fSVenugopal Iyer LINK_FLOWCTRL_RX : LINK_FLOWCTRL_NONE; 47161bd6825cSml 47170dc2366fSVenugopal Iyer ASSERT(pr_valsize >= sizeof (fl)); 47180dc2366fSVenugopal Iyer bcopy(&fl, pr_val, sizeof (fl)); 47190dc2366fSVenugopal Iyer break; 47200dc2366fSVenugopal Iyer } 47211bd6825cSml 47220dc2366fSVenugopal Iyer case MAC_PROP_ADV_1000FDX_CAP: 47230dc2366fSVenugopal Iyer *(uint8_t *)pr_val = param_arr[param_anar_1000fdx].value; 47240dc2366fSVenugopal Iyer break; 47251bd6825cSml 47260dc2366fSVenugopal Iyer case MAC_PROP_EN_1000FDX_CAP: 47270dc2366fSVenugopal Iyer *(uint8_t *)pr_val = nxgep->param_en_1000fdx; 47280dc2366fSVenugopal Iyer break; 47291bd6825cSml 47300dc2366fSVenugopal Iyer case MAC_PROP_ADV_100FDX_CAP: 47310dc2366fSVenugopal Iyer *(uint8_t *)pr_val = param_arr[param_anar_100fdx].value; 47320dc2366fSVenugopal Iyer break; 47331bd6825cSml 47340dc2366fSVenugopal Iyer case MAC_PROP_EN_100FDX_CAP: 47350dc2366fSVenugopal Iyer *(uint8_t *)pr_val = nxgep->param_en_100fdx; 47360dc2366fSVenugopal Iyer break; 47371bd6825cSml 47380dc2366fSVenugopal Iyer case MAC_PROP_ADV_10FDX_CAP: 47390dc2366fSVenugopal Iyer *(uint8_t *)pr_val = param_arr[param_anar_10fdx].value; 47400dc2366fSVenugopal Iyer break; 47411bd6825cSml 47420dc2366fSVenugopal Iyer case MAC_PROP_EN_10FDX_CAP: 47430dc2366fSVenugopal Iyer *(uint8_t *)pr_val = nxgep->param_en_10fdx; 47440dc2366fSVenugopal Iyer break; 47451bd6825cSml 47460dc2366fSVenugopal Iyer case MAC_PROP_PRIVATE: 47470dc2366fSVenugopal Iyer return (nxge_get_priv_prop(nxgep, pr_name, pr_valsize, 47480dc2366fSVenugopal Iyer pr_val)); 47491bd6825cSml 47500dc2366fSVenugopal Iyer default: 47510dc2366fSVenugopal Iyer return (ENOTSUP); 47520dc2366fSVenugopal Iyer } 47531bd6825cSml 47540dc2366fSVenugopal Iyer return (0); 47550dc2366fSVenugopal Iyer } 4756f0f2c3a5SGirish Moodalbail 47570dc2366fSVenugopal Iyer static void 47580dc2366fSVenugopal Iyer nxge_m_propinfo(void *barg, const char *pr_name, mac_prop_id_t pr_num, 47590dc2366fSVenugopal Iyer mac_prop_info_handle_t prh) 47600dc2366fSVenugopal Iyer { 47610dc2366fSVenugopal Iyer nxge_t *nxgep = barg; 47620dc2366fSVenugopal Iyer p_nxge_stats_t statsp = nxgep->statsp; 47630dc2366fSVenugopal Iyer 47640dc2366fSVenugopal Iyer /* 47650dc2366fSVenugopal Iyer * By default permissions are read/write unless specified 47660dc2366fSVenugopal Iyer * otherwise by the driver. 47670dc2366fSVenugopal Iyer */ 47680dc2366fSVenugopal Iyer 47690dc2366fSVenugopal Iyer switch (pr_num) { 47700dc2366fSVenugopal Iyer case MAC_PROP_DUPLEX: 47710dc2366fSVenugopal Iyer case MAC_PROP_SPEED: 47720dc2366fSVenugopal Iyer case MAC_PROP_STATUS: 47730dc2366fSVenugopal Iyer case MAC_PROP_EN_1000HDX_CAP: 47740dc2366fSVenugopal Iyer case MAC_PROP_EN_100HDX_CAP: 47750dc2366fSVenugopal Iyer case MAC_PROP_EN_10HDX_CAP: 47760dc2366fSVenugopal Iyer case MAC_PROP_ADV_1000FDX_CAP: 47770dc2366fSVenugopal Iyer case MAC_PROP_ADV_1000HDX_CAP: 47780dc2366fSVenugopal Iyer case MAC_PROP_ADV_100FDX_CAP: 47790dc2366fSVenugopal Iyer case MAC_PROP_ADV_100HDX_CAP: 47800dc2366fSVenugopal Iyer case MAC_PROP_ADV_10FDX_CAP: 47810dc2366fSVenugopal Iyer case MAC_PROP_ADV_10HDX_CAP: 47820dc2366fSVenugopal Iyer /* 47830dc2366fSVenugopal Iyer * Note that read-only properties don't need to 47840dc2366fSVenugopal Iyer * provide default values since they cannot be 47850dc2366fSVenugopal Iyer * changed by the administrator. 47860dc2366fSVenugopal Iyer */ 47870dc2366fSVenugopal Iyer mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 47880dc2366fSVenugopal Iyer break; 47890dc2366fSVenugopal Iyer 47900dc2366fSVenugopal Iyer case MAC_PROP_EN_1000FDX_CAP: 47910dc2366fSVenugopal Iyer case MAC_PROP_EN_100FDX_CAP: 47920dc2366fSVenugopal Iyer case MAC_PROP_EN_10FDX_CAP: 47930dc2366fSVenugopal Iyer mac_prop_info_set_default_uint8(prh, 1); 47940dc2366fSVenugopal Iyer break; 47950dc2366fSVenugopal Iyer 47960dc2366fSVenugopal Iyer case MAC_PROP_AUTONEG: 47970dc2366fSVenugopal Iyer mac_prop_info_set_default_uint8(prh, 1); 47980dc2366fSVenugopal Iyer break; 47990dc2366fSVenugopal Iyer 48000dc2366fSVenugopal Iyer case MAC_PROP_FLOWCTRL: 48010dc2366fSVenugopal Iyer mac_prop_info_set_default_link_flowctrl(prh, LINK_FLOWCTRL_RX); 48020dc2366fSVenugopal Iyer break; 48030dc2366fSVenugopal Iyer 48040dc2366fSVenugopal Iyer case MAC_PROP_MTU: 48050dc2366fSVenugopal Iyer mac_prop_info_set_range_uint32(prh, 48060dc2366fSVenugopal Iyer NXGE_DEFAULT_MTU, NXGE_MAXIMUM_MTU); 48070dc2366fSVenugopal Iyer break; 48080dc2366fSVenugopal Iyer 48090dc2366fSVenugopal Iyer case MAC_PROP_PRIVATE: 48100dc2366fSVenugopal Iyer nxge_priv_propinfo(pr_name, prh); 48110dc2366fSVenugopal Iyer break; 48120dc2366fSVenugopal Iyer } 48130dc2366fSVenugopal Iyer 48140dc2366fSVenugopal Iyer mutex_enter(nxgep->genlock); 48150dc2366fSVenugopal Iyer if (statsp->port_stats.lb_mode != nxge_lb_normal && 48160dc2366fSVenugopal Iyer nxge_param_locked(pr_num)) { 48170dc2366fSVenugopal Iyer /* 48180dc2366fSVenugopal Iyer * Some properties are locked (read-only) while the 48190dc2366fSVenugopal Iyer * device is in any sort of loopback mode. 48200dc2366fSVenugopal Iyer */ 48210dc2366fSVenugopal Iyer mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 48221bd6825cSml } 48230dc2366fSVenugopal Iyer mutex_exit(nxgep->genlock); 48240dc2366fSVenugopal Iyer } 48251bd6825cSml 48260dc2366fSVenugopal Iyer static void 48270dc2366fSVenugopal Iyer nxge_priv_propinfo(const char *pr_name, mac_prop_info_handle_t prh) 48280dc2366fSVenugopal Iyer { 48290dc2366fSVenugopal Iyer char valstr[64]; 48301bd6825cSml 48310dc2366fSVenugopal Iyer bzero(valstr, sizeof (valstr)); 48320dc2366fSVenugopal Iyer 48330dc2366fSVenugopal Iyer if (strcmp(pr_name, "_function_number") == 0 || 48340dc2366fSVenugopal Iyer strcmp(pr_name, "_fw_version") == 0 || 48350dc2366fSVenugopal Iyer strcmp(pr_name, "_port_mode") == 0 || 48360dc2366fSVenugopal Iyer strcmp(pr_name, "_hot_swap_phy") == 0) { 48370dc2366fSVenugopal Iyer mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ); 48380dc2366fSVenugopal Iyer 48390dc2366fSVenugopal Iyer } else if (strcmp(pr_name, "_rxdma_intr_time") == 0) { 48400dc2366fSVenugopal Iyer (void) snprintf(valstr, sizeof (valstr), 48410dc2366fSVenugopal Iyer "%d", RXDMA_RCR_TO_DEFAULT); 48420dc2366fSVenugopal Iyer 48430dc2366fSVenugopal Iyer } else if (strcmp(pr_name, "_rxdma_intr_pkts") == 0) { 48440dc2366fSVenugopal Iyer (void) snprintf(valstr, sizeof (valstr), 48450dc2366fSVenugopal Iyer "%d", RXDMA_RCR_PTHRES_DEFAULT); 48460dc2366fSVenugopal Iyer 4847*86ef0a63SRichard Lowe } else if (strcmp(pr_name, "_class_opt_ipv4_tcp") == 0 || 48480dc2366fSVenugopal Iyer strcmp(pr_name, "_class_opt_ipv4_udp") == 0 || 48490dc2366fSVenugopal Iyer strcmp(pr_name, "_class_opt_ipv4_ah") == 0 || 48500dc2366fSVenugopal Iyer strcmp(pr_name, "_class_opt_ipv4_sctp") == 0 || 48510dc2366fSVenugopal Iyer strcmp(pr_name, "_class_opt_ipv6_tcp") == 0 || 48520dc2366fSVenugopal Iyer strcmp(pr_name, "_class_opt_ipv6_udp") == 0 || 48530dc2366fSVenugopal Iyer strcmp(pr_name, "_class_opt_ipv6_ah") == 0 || 48540dc2366fSVenugopal Iyer strcmp(pr_name, "_class_opt_ipv6_sctp") == 0) { 48550dc2366fSVenugopal Iyer (void) snprintf(valstr, sizeof (valstr), "%x", 48560dc2366fSVenugopal Iyer NXGE_CLASS_FLOW_GEN_SERVER); 48570dc2366fSVenugopal Iyer 48580dc2366fSVenugopal Iyer } else if (strcmp(pr_name, "_soft_lso_enable") == 0) { 48590dc2366fSVenugopal Iyer (void) snprintf(valstr, sizeof (valstr), "%d", 0); 48600dc2366fSVenugopal Iyer 4861*86ef0a63SRichard Lowe } else if (strcmp(pr_name, "_adv_10gfdx_cap") == 0) { 48620dc2366fSVenugopal Iyer (void) snprintf(valstr, sizeof (valstr), "%d", 1); 48630dc2366fSVenugopal Iyer 48640dc2366fSVenugopal Iyer } else if (strcmp(pr_name, "_adv_pause_cap") == 0) { 48650dc2366fSVenugopal Iyer (void) snprintf(valstr, sizeof (valstr), "%d", 1); 48660dc2366fSVenugopal Iyer } 48670dc2366fSVenugopal Iyer 48680dc2366fSVenugopal Iyer if (strlen(valstr) > 0) 48690dc2366fSVenugopal Iyer mac_prop_info_set_default_str(prh, valstr); 48701bd6825cSml } 48711bd6825cSml 48721bd6825cSml /* ARGSUSED */ 48731bd6825cSml static int 48741bd6825cSml nxge_set_priv_prop(p_nxge_t nxgep, const char *pr_name, uint_t pr_valsize, 48751bd6825cSml const void *pr_val) 48761bd6825cSml { 48771bd6825cSml p_nxge_param_t param_arr = nxgep->param_arr; 48781bd6825cSml int err = 0; 48791bd6825cSml long result; 48801bd6825cSml 48811bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 48821bd6825cSml "==> nxge_set_priv_prop: name %s", pr_name)); 48831bd6825cSml 48841bd6825cSml /* Blanking */ 48851bd6825cSml if (strcmp(pr_name, "_rxdma_intr_time") == 0) { 48861bd6825cSml err = nxge_param_rx_intr_time(nxgep, NULL, NULL, 48871bd6825cSml (char *)pr_val, 48881bd6825cSml (caddr_t)¶m_arr[param_rxdma_intr_time]); 48891bd6825cSml if (err) { 48901bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 48911bd6825cSml "<== nxge_set_priv_prop: " 48921bd6825cSml "unable to set (%s)", pr_name)); 48931bd6825cSml err = EINVAL; 48941bd6825cSml } else { 48951bd6825cSml err = 0; 48961bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 48971bd6825cSml "<== nxge_set_priv_prop: " 48981bd6825cSml "set (%s)", pr_name)); 48991bd6825cSml } 49001bd6825cSml 49011bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 49021bd6825cSml "<== nxge_set_priv_prop: name %s (value %d)", 49031bd6825cSml pr_name, result)); 49041bd6825cSml 49051bd6825cSml return (err); 49061bd6825cSml } 49071bd6825cSml 49081bd6825cSml if (strcmp(pr_name, "_rxdma_intr_pkts") == 0) { 49091bd6825cSml err = nxge_param_rx_intr_pkts(nxgep, NULL, NULL, 49101bd6825cSml (char *)pr_val, 49111bd6825cSml (caddr_t)¶m_arr[param_rxdma_intr_pkts]); 49121bd6825cSml if (err) { 49131bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 49141bd6825cSml "<== nxge_set_priv_prop: " 49151bd6825cSml "unable to set (%s)", pr_name)); 49161bd6825cSml err = EINVAL; 49171bd6825cSml } else { 49181bd6825cSml err = 0; 49191bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 49201bd6825cSml "<== nxge_set_priv_prop: " 49211bd6825cSml "set (%s)", pr_name)); 49221bd6825cSml } 49231bd6825cSml 49241bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 49251bd6825cSml "<== nxge_set_priv_prop: name %s (value %d)", 49261bd6825cSml pr_name, result)); 49271bd6825cSml 49281bd6825cSml return (err); 49291bd6825cSml } 49301bd6825cSml 49311bd6825cSml /* Classification */ 49321bd6825cSml if (strcmp(pr_name, "_class_opt_ipv4_tcp") == 0) { 49331bd6825cSml if (pr_val == NULL) { 49341bd6825cSml err = EINVAL; 49351bd6825cSml return (err); 49361bd6825cSml } 49371bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 49381bd6825cSml 49391bd6825cSml err = nxge_param_set_ip_opt(nxgep, NULL, 49401bd6825cSml NULL, (char *)pr_val, 49411bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv4_tcp]); 49421bd6825cSml 49431bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 49441bd6825cSml "<== nxge_set_priv_prop: name %s (value 0x%x)", 49451bd6825cSml pr_name, result)); 49461bd6825cSml 49471bd6825cSml return (err); 49481bd6825cSml } 49491bd6825cSml 49501bd6825cSml if (strcmp(pr_name, "_class_opt_ipv4_udp") == 0) { 49511bd6825cSml if (pr_val == NULL) { 49521bd6825cSml err = EINVAL; 49531bd6825cSml return (err); 49541bd6825cSml } 49551bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 49561bd6825cSml 49571bd6825cSml err = nxge_param_set_ip_opt(nxgep, NULL, 49581bd6825cSml NULL, (char *)pr_val, 49591bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv4_udp]); 49601bd6825cSml 49611bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 49621bd6825cSml "<== nxge_set_priv_prop: name %s (value 0x%x)", 49631bd6825cSml pr_name, result)); 49641bd6825cSml 49651bd6825cSml return (err); 49661bd6825cSml } 49671bd6825cSml if (strcmp(pr_name, "_class_opt_ipv4_ah") == 0) { 49681bd6825cSml if (pr_val == NULL) { 49691bd6825cSml err = EINVAL; 49701bd6825cSml return (err); 49711bd6825cSml } 49721bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 49731bd6825cSml 49741bd6825cSml err = nxge_param_set_ip_opt(nxgep, NULL, 49751bd6825cSml NULL, (char *)pr_val, 49761bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv4_ah]); 49771bd6825cSml 49781bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 49791bd6825cSml "<== nxge_set_priv_prop: name %s (value 0x%x)", 49801bd6825cSml pr_name, result)); 49811bd6825cSml 49821bd6825cSml return (err); 49831bd6825cSml } 49841bd6825cSml if (strcmp(pr_name, "_class_opt_ipv4_sctp") == 0) { 49851bd6825cSml if (pr_val == NULL) { 49861bd6825cSml err = EINVAL; 49871bd6825cSml return (err); 49881bd6825cSml } 49891bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 49901bd6825cSml 49911bd6825cSml err = nxge_param_set_ip_opt(nxgep, NULL, 49921bd6825cSml NULL, (char *)pr_val, 49931bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv4_sctp]); 49941bd6825cSml 49951bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 49961bd6825cSml "<== nxge_set_priv_prop: name %s (value 0x%x)", 49971bd6825cSml pr_name, result)); 49981bd6825cSml 49991bd6825cSml return (err); 50001bd6825cSml } 50011bd6825cSml 50021bd6825cSml if (strcmp(pr_name, "_class_opt_ipv6_tcp") == 0) { 50031bd6825cSml if (pr_val == NULL) { 50041bd6825cSml err = EINVAL; 50051bd6825cSml return (err); 50061bd6825cSml } 50071bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 50081bd6825cSml 50091bd6825cSml err = nxge_param_set_ip_opt(nxgep, NULL, 50101bd6825cSml NULL, (char *)pr_val, 50111bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv6_tcp]); 50121bd6825cSml 50131bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 50141bd6825cSml "<== nxge_set_priv_prop: name %s (value 0x%x)", 50151bd6825cSml pr_name, result)); 50161bd6825cSml 50171bd6825cSml return (err); 50181bd6825cSml } 50191bd6825cSml 50201bd6825cSml if (strcmp(pr_name, "_class_opt_ipv6_udp") == 0) { 50211bd6825cSml if (pr_val == NULL) { 50221bd6825cSml err = EINVAL; 50231bd6825cSml return (err); 50241bd6825cSml } 50251bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 50261bd6825cSml 50271bd6825cSml err = nxge_param_set_ip_opt(nxgep, NULL, 50281bd6825cSml NULL, (char *)pr_val, 50291bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv6_udp]); 50301bd6825cSml 50311bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 50321bd6825cSml "<== nxge_set_priv_prop: name %s (value 0x%x)", 50331bd6825cSml pr_name, result)); 50341bd6825cSml 50351bd6825cSml return (err); 50361bd6825cSml } 50371bd6825cSml if (strcmp(pr_name, "_class_opt_ipv6_ah") == 0) { 50381bd6825cSml if (pr_val == NULL) { 50391bd6825cSml err = EINVAL; 50401bd6825cSml return (err); 50411bd6825cSml } 50421bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 50431bd6825cSml 50441bd6825cSml err = nxge_param_set_ip_opt(nxgep, NULL, 50451bd6825cSml NULL, (char *)pr_val, 50461bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv6_ah]); 50471bd6825cSml 50481bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 50491bd6825cSml "<== nxge_set_priv_prop: name %s (value 0x%x)", 50501bd6825cSml pr_name, result)); 50511bd6825cSml 50521bd6825cSml return (err); 50531bd6825cSml } 50541bd6825cSml if (strcmp(pr_name, "_class_opt_ipv6_sctp") == 0) { 50551bd6825cSml if (pr_val == NULL) { 50561bd6825cSml err = EINVAL; 50571bd6825cSml return (err); 50581bd6825cSml } 50591bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 50601bd6825cSml 50611bd6825cSml err = nxge_param_set_ip_opt(nxgep, NULL, 50621bd6825cSml NULL, (char *)pr_val, 50631bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv6_sctp]); 50641bd6825cSml 50651bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 50661bd6825cSml "<== nxge_set_priv_prop: name %s (value 0x%x)", 50671bd6825cSml pr_name, result)); 50681bd6825cSml 50691bd6825cSml return (err); 50701bd6825cSml } 50711bd6825cSml 50721bd6825cSml if (strcmp(pr_name, "_soft_lso_enable") == 0) { 50731bd6825cSml if (pr_val == NULL) { 50741bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 50751bd6825cSml "==> nxge_set_priv_prop: name %s (null)", pr_name)); 50761bd6825cSml err = EINVAL; 50771bd6825cSml return (err); 50781bd6825cSml } 50791bd6825cSml 50801bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 50811bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 50821bd6825cSml "<== nxge_set_priv_prop: name %s " 50831bd6825cSml "(lso %d pr_val %s value %d)", 50841bd6825cSml pr_name, nxgep->soft_lso_enable, pr_val, result)); 50851bd6825cSml 50861bd6825cSml if (result > 1 || result < 0) { 50871bd6825cSml err = EINVAL; 50881bd6825cSml } else { 50891bd6825cSml if (nxgep->soft_lso_enable == (uint32_t)result) { 50901bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 50911bd6825cSml "no change (%d %d)", 50921bd6825cSml nxgep->soft_lso_enable, result)); 50931bd6825cSml return (0); 50941bd6825cSml } 50951bd6825cSml } 50961bd6825cSml 50971bd6825cSml nxgep->soft_lso_enable = (int)result; 50981bd6825cSml 50991bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 51001bd6825cSml "<== nxge_set_priv_prop: name %s (value %d)", 51011bd6825cSml pr_name, result)); 51021bd6825cSml 51031bd6825cSml return (err); 51041bd6825cSml } 510500161856Syc /* 510600161856Syc * Commands like "ndd -set /dev/nxge0 adv_10gfdx_cap 1" cause the 510700161856Syc * following code to be executed. 510800161856Syc */ 51094045d941Ssowmini if (strcmp(pr_name, "_adv_10gfdx_cap") == 0) { 51104045d941Ssowmini err = nxge_param_set_mac(nxgep, NULL, NULL, (char *)pr_val, 51114045d941Ssowmini (caddr_t)¶m_arr[param_anar_10gfdx]); 51124045d941Ssowmini return (err); 51134045d941Ssowmini } 51144045d941Ssowmini if (strcmp(pr_name, "_adv_pause_cap") == 0) { 51154045d941Ssowmini err = nxge_param_set_mac(nxgep, NULL, NULL, (char *)pr_val, 51164045d941Ssowmini (caddr_t)¶m_arr[param_anar_pause]); 51174045d941Ssowmini return (err); 51184045d941Ssowmini } 51191bd6825cSml 5120238d8f47SDale Ghent return (ENOTSUP); 51211bd6825cSml } 51221bd6825cSml 51231bd6825cSml static int 51240dc2366fSVenugopal Iyer nxge_get_priv_prop(p_nxge_t nxgep, const char *pr_name, uint_t pr_valsize, 51250dc2366fSVenugopal Iyer void *pr_val) 51261bd6825cSml { 51271bd6825cSml p_nxge_param_t param_arr = nxgep->param_arr; 51281bd6825cSml char valstr[MAXNAMELEN]; 5129238d8f47SDale Ghent int err = ENOTSUP; 51301bd6825cSml uint_t strsize; 51311bd6825cSml 51321bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 51331bd6825cSml "==> nxge_get_priv_prop: property %s", pr_name)); 51341bd6825cSml 51351bd6825cSml /* function number */ 51361bd6825cSml if (strcmp(pr_name, "_function_number") == 0) { 51374045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%d", 51384045d941Ssowmini nxgep->function_num); 51391bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 51401bd6825cSml "==> nxge_get_priv_prop: name %s " 51411bd6825cSml "(value %d valstr %s)", 51421bd6825cSml pr_name, nxgep->function_num, valstr)); 51431bd6825cSml 51441bd6825cSml err = 0; 51451bd6825cSml goto done; 51461bd6825cSml } 51471bd6825cSml 51481bd6825cSml /* Neptune firmware version */ 51491bd6825cSml if (strcmp(pr_name, "_fw_version") == 0) { 51504045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%s", 51514045d941Ssowmini nxgep->vpd_info.ver); 51521bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 51531bd6825cSml "==> nxge_get_priv_prop: name %s " 51541bd6825cSml "(value %d valstr %s)", 51551bd6825cSml pr_name, nxgep->vpd_info.ver, valstr)); 51561bd6825cSml 51571bd6825cSml err = 0; 51581bd6825cSml goto done; 51591bd6825cSml } 51601bd6825cSml 51611bd6825cSml /* port PHY mode */ 51621bd6825cSml if (strcmp(pr_name, "_port_mode") == 0) { 51631bd6825cSml switch (nxgep->mac.portmode) { 51641bd6825cSml case PORT_1G_COPPER: 51654045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "1G copper %s", 51661bd6825cSml nxgep->hot_swappable_phy ? 51671bd6825cSml "[Hot Swappable]" : ""); 51681bd6825cSml break; 51691bd6825cSml case PORT_1G_FIBER: 51704045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "1G fiber %s", 51711bd6825cSml nxgep->hot_swappable_phy ? 51721bd6825cSml "[hot swappable]" : ""); 51731bd6825cSml break; 51741bd6825cSml case PORT_10G_COPPER: 51754045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), 51764045d941Ssowmini "10G copper %s", 51771bd6825cSml nxgep->hot_swappable_phy ? 51781bd6825cSml "[hot swappable]" : ""); 51791bd6825cSml break; 51801bd6825cSml case PORT_10G_FIBER: 51814045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "10G fiber %s", 51821bd6825cSml nxgep->hot_swappable_phy ? 51831bd6825cSml "[hot swappable]" : ""); 51841bd6825cSml break; 51851bd6825cSml case PORT_10G_SERDES: 51864045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), 51874045d941Ssowmini "10G serdes %s", nxgep->hot_swappable_phy ? 51881bd6825cSml "[hot swappable]" : ""); 51891bd6825cSml break; 51901bd6825cSml case PORT_1G_SERDES: 51914045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "1G serdes %s", 51921bd6825cSml nxgep->hot_swappable_phy ? 51931bd6825cSml "[hot swappable]" : ""); 51941bd6825cSml break; 519500161856Syc case PORT_1G_TN1010: 519600161856Syc (void) snprintf(valstr, sizeof (valstr), 519700161856Syc "1G TN1010 copper %s", nxgep->hot_swappable_phy ? 519800161856Syc "[hot swappable]" : ""); 519900161856Syc break; 520000161856Syc case PORT_10G_TN1010: 520100161856Syc (void) snprintf(valstr, sizeof (valstr), 520200161856Syc "10G TN1010 copper %s", nxgep->hot_swappable_phy ? 520300161856Syc "[hot swappable]" : ""); 520400161856Syc break; 52051bd6825cSml case PORT_1G_RGMII_FIBER: 52064045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), 52074045d941Ssowmini "1G rgmii fiber %s", nxgep->hot_swappable_phy ? 52081bd6825cSml "[hot swappable]" : ""); 52091bd6825cSml break; 52101bd6825cSml case PORT_HSP_MODE: 52114045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), 5212c2d37b8bSml "phy not present[hot swappable]"); 52131bd6825cSml break; 52141bd6825cSml default: 52154045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "unknown %s", 52161bd6825cSml nxgep->hot_swappable_phy ? 52171bd6825cSml "[hot swappable]" : ""); 52181bd6825cSml break; 52191bd6825cSml } 52201bd6825cSml 52211bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 52221bd6825cSml "==> nxge_get_priv_prop: name %s (value %s)", 52231bd6825cSml pr_name, valstr)); 52241bd6825cSml 52251bd6825cSml err = 0; 52261bd6825cSml goto done; 52271bd6825cSml } 52281bd6825cSml 52291bd6825cSml /* Hot swappable PHY */ 52301bd6825cSml if (strcmp(pr_name, "_hot_swap_phy") == 0) { 52314045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%s", 52321bd6825cSml nxgep->hot_swappable_phy ? 52331bd6825cSml "yes" : "no"); 52341bd6825cSml 52351bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 52361bd6825cSml "==> nxge_get_priv_prop: name %s " 52371bd6825cSml "(value %d valstr %s)", 52381bd6825cSml pr_name, nxgep->hot_swappable_phy, valstr)); 52391bd6825cSml 52401bd6825cSml err = 0; 52411bd6825cSml goto done; 52421bd6825cSml } 52431bd6825cSml 52441bd6825cSml 52451bd6825cSml /* Receive Interrupt Blanking Parameters */ 52461bd6825cSml if (strcmp(pr_name, "_rxdma_intr_time") == 0) { 52474045d941Ssowmini err = 0; 52484045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%d", 52494045d941Ssowmini nxgep->intr_timeout); 52501bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 52511bd6825cSml "==> nxge_get_priv_prop: name %s (value %d)", 52521bd6825cSml pr_name, 52531bd6825cSml (uint32_t)nxgep->intr_timeout)); 52541bd6825cSml goto done; 52551bd6825cSml } 52561bd6825cSml 52571bd6825cSml if (strcmp(pr_name, "_rxdma_intr_pkts") == 0) { 52584045d941Ssowmini err = 0; 52594045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%d", 52604045d941Ssowmini nxgep->intr_threshold); 52611bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 52621bd6825cSml "==> nxge_get_priv_prop: name %s (value %d)", 52631bd6825cSml pr_name, (uint32_t)nxgep->intr_threshold)); 52641bd6825cSml 52651bd6825cSml goto done; 52661bd6825cSml } 52671bd6825cSml 52681bd6825cSml /* Classification and Load Distribution Configuration */ 52691bd6825cSml if (strcmp(pr_name, "_class_opt_ipv4_tcp") == 0) { 52701bd6825cSml err = nxge_dld_get_ip_opt(nxgep, 52711bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv4_tcp]); 52721bd6825cSml 52734045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 52741bd6825cSml (int)param_arr[param_class_opt_ipv4_tcp].value); 52751bd6825cSml 52761bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 52771bd6825cSml "==> nxge_get_priv_prop: %s", valstr)); 52781bd6825cSml goto done; 52791bd6825cSml } 52801bd6825cSml 52811bd6825cSml if (strcmp(pr_name, "_class_opt_ipv4_udp") == 0) { 52821bd6825cSml err = nxge_dld_get_ip_opt(nxgep, 52831bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv4_udp]); 52841bd6825cSml 52854045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 52861bd6825cSml (int)param_arr[param_class_opt_ipv4_udp].value); 52871bd6825cSml 52881bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 52891bd6825cSml "==> nxge_get_priv_prop: %s", valstr)); 52901bd6825cSml goto done; 52911bd6825cSml } 52921bd6825cSml if (strcmp(pr_name, "_class_opt_ipv4_ah") == 0) { 52931bd6825cSml err = nxge_dld_get_ip_opt(nxgep, 52941bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv4_ah]); 52951bd6825cSml 52964045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 52971bd6825cSml (int)param_arr[param_class_opt_ipv4_ah].value); 52981bd6825cSml 52991bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 53001bd6825cSml "==> nxge_get_priv_prop: %s", valstr)); 53011bd6825cSml goto done; 53021bd6825cSml } 53031bd6825cSml 53041bd6825cSml if (strcmp(pr_name, "_class_opt_ipv4_sctp") == 0) { 53051bd6825cSml err = nxge_dld_get_ip_opt(nxgep, 53061bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv4_sctp]); 53071bd6825cSml 53084045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 53091bd6825cSml (int)param_arr[param_class_opt_ipv4_sctp].value); 53101bd6825cSml 53111bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 53121bd6825cSml "==> nxge_get_priv_prop: %s", valstr)); 53131bd6825cSml goto done; 53141bd6825cSml } 53151bd6825cSml 53161bd6825cSml if (strcmp(pr_name, "_class_opt_ipv6_tcp") == 0) { 53171bd6825cSml err = nxge_dld_get_ip_opt(nxgep, 53181bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv6_tcp]); 53191bd6825cSml 53204045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 53211bd6825cSml (int)param_arr[param_class_opt_ipv6_tcp].value); 53221bd6825cSml 53231bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 53241bd6825cSml "==> nxge_get_priv_prop: %s", valstr)); 53251bd6825cSml goto done; 53261bd6825cSml } 53271bd6825cSml 53281bd6825cSml if (strcmp(pr_name, "_class_opt_ipv6_udp") == 0) { 53291bd6825cSml err = nxge_dld_get_ip_opt(nxgep, 53301bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv6_udp]); 53311bd6825cSml 53324045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 53331bd6825cSml (int)param_arr[param_class_opt_ipv6_udp].value); 53341bd6825cSml 53351bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 53361bd6825cSml "==> nxge_get_priv_prop: %s", valstr)); 53371bd6825cSml goto done; 53381bd6825cSml } 53391bd6825cSml 53401bd6825cSml if (strcmp(pr_name, "_class_opt_ipv6_ah") == 0) { 53411bd6825cSml err = nxge_dld_get_ip_opt(nxgep, 53421bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv6_ah]); 53431bd6825cSml 53444045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 53451bd6825cSml (int)param_arr[param_class_opt_ipv6_ah].value); 53461bd6825cSml 53471bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 53481bd6825cSml "==> nxge_get_priv_prop: %s", valstr)); 53491bd6825cSml goto done; 53501bd6825cSml } 53511bd6825cSml 53521bd6825cSml if (strcmp(pr_name, "_class_opt_ipv6_sctp") == 0) { 53531bd6825cSml err = nxge_dld_get_ip_opt(nxgep, 53541bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv6_sctp]); 53551bd6825cSml 53564045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 53571bd6825cSml (int)param_arr[param_class_opt_ipv6_sctp].value); 53581bd6825cSml 53591bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 53601bd6825cSml "==> nxge_get_priv_prop: %s", valstr)); 53611bd6825cSml goto done; 53621bd6825cSml } 53631bd6825cSml 53641bd6825cSml /* Software LSO */ 53651bd6825cSml if (strcmp(pr_name, "_soft_lso_enable") == 0) { 53664045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), 53674045d941Ssowmini "%d", nxgep->soft_lso_enable); 53681bd6825cSml err = 0; 53691bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 53701bd6825cSml "==> nxge_get_priv_prop: name %s (value %d)", 53711bd6825cSml pr_name, nxgep->soft_lso_enable)); 53721bd6825cSml 53731bd6825cSml goto done; 53741bd6825cSml } 53754045d941Ssowmini if (strcmp(pr_name, "_adv_10gfdx_cap") == 0) { 53764045d941Ssowmini err = 0; 53770dc2366fSVenugopal Iyer if (nxgep->param_arr[param_anar_10gfdx].value != 0) { 53784045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%d", 1); 53794045d941Ssowmini goto done; 53804045d941Ssowmini } else { 53814045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%d", 0); 53824045d941Ssowmini goto done; 53834045d941Ssowmini } 53844045d941Ssowmini } 53854045d941Ssowmini if (strcmp(pr_name, "_adv_pause_cap") == 0) { 53864045d941Ssowmini err = 0; 53870dc2366fSVenugopal Iyer if (nxgep->param_arr[param_anar_pause].value != 0) { 53884045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%d", 1); 53894045d941Ssowmini goto done; 53904045d941Ssowmini } else { 53914045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%d", 0); 53924045d941Ssowmini goto done; 53934045d941Ssowmini } 53944045d941Ssowmini } 53951bd6825cSml 53961bd6825cSml done: 53971bd6825cSml if (err == 0) { 53981bd6825cSml strsize = (uint_t)strlen(valstr); 53991bd6825cSml if (pr_valsize < strsize) { 54001bd6825cSml err = ENOBUFS; 54011bd6825cSml } else { 54021bd6825cSml (void) strlcpy(pr_val, valstr, pr_valsize); 54031bd6825cSml } 54041bd6825cSml } 54051bd6825cSml 54061bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 54071bd6825cSml "<== nxge_get_priv_prop: return %d", err)); 54081bd6825cSml return (err); 54091bd6825cSml } 54101bd6825cSml 541144961713Sgirish /* 541244961713Sgirish * Module loading and removing entry points. 541344961713Sgirish */ 541444961713Sgirish 54156f157acbSml DDI_DEFINE_STREAM_OPS(nxge_dev_ops, nulldev, nulldev, nxge_attach, nxge_detach, 541619397407SSherry Moore nodev, NULL, D_MP, NULL, nxge_quiesce); 541744961713Sgirish 54182e59129aSraghus #define NXGE_DESC_VER "Sun NIU 10Gb Ethernet" 541944961713Sgirish 542044961713Sgirish /* 542144961713Sgirish * Module linkage information for the kernel. 542244961713Sgirish */ 5423*86ef0a63SRichard Lowe static struct modldrv nxge_modldrv = { 542444961713Sgirish &mod_driverops, 542544961713Sgirish NXGE_DESC_VER, 542644961713Sgirish &nxge_dev_ops 542744961713Sgirish }; 542844961713Sgirish 542944961713Sgirish static struct modlinkage modlinkage = { 543044961713Sgirish MODREV_1, (void *) &nxge_modldrv, NULL 543144961713Sgirish }; 543244961713Sgirish 543344961713Sgirish int 543444961713Sgirish _init(void) 543544961713Sgirish { 543644961713Sgirish int status; 543744961713Sgirish 54383b2d9860SMichael Speer MUTEX_INIT(&nxgedebuglock, NULL, MUTEX_DRIVER, NULL); 54393b2d9860SMichael Speer 544044961713Sgirish NXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _init")); 54413b2d9860SMichael Speer 544244961713Sgirish mac_init_ops(&nxge_dev_ops, "nxge"); 54433b2d9860SMichael Speer 544444961713Sgirish status = ddi_soft_state_init(&nxge_list, sizeof (nxge_t), 0); 544544961713Sgirish if (status != 0) { 544644961713Sgirish NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 54474045d941Ssowmini "failed to init device soft state")); 544844961713Sgirish goto _init_exit; 544944961713Sgirish } 54503b2d9860SMichael Speer 545144961713Sgirish status = mod_install(&modlinkage); 545244961713Sgirish if (status != 0) { 545344961713Sgirish ddi_soft_state_fini(&nxge_list); 545444961713Sgirish NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, "Mod install failed")); 545544961713Sgirish goto _init_exit; 545644961713Sgirish } 545744961713Sgirish 545844961713Sgirish MUTEX_INIT(&nxge_common_lock, NULL, MUTEX_DRIVER, NULL); 545944961713Sgirish 54603b2d9860SMichael Speer NXGE_DEBUG_MSG((NULL, MOD_CTL, "<== _init status = 0x%X", status)); 54613b2d9860SMichael Speer return (status); 546244961713Sgirish 54633b2d9860SMichael Speer _init_exit: 54643b2d9860SMichael Speer NXGE_DEBUG_MSG((NULL, MOD_CTL, "<== _init status = 0x%X", status)); 54653b2d9860SMichael Speer MUTEX_DESTROY(&nxgedebuglock); 546644961713Sgirish return (status); 546744961713Sgirish } 546844961713Sgirish 546944961713Sgirish int 547044961713Sgirish _fini(void) 547144961713Sgirish { 547244961713Sgirish int status; 547344961713Sgirish 547444961713Sgirish NXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _fini")); 547544961713Sgirish NXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _fini: mod_remove")); 5476a3c5bd6dSspeer 5477a3c5bd6dSspeer if (nxge_mblks_pending) 5478a3c5bd6dSspeer return (EBUSY); 5479a3c5bd6dSspeer 548044961713Sgirish status = mod_remove(&modlinkage); 548144961713Sgirish if (status != DDI_SUCCESS) { 548244961713Sgirish NXGE_DEBUG_MSG((NULL, MOD_CTL, 54834045d941Ssowmini "Module removal failed 0x%08x", 54844045d941Ssowmini status)); 548544961713Sgirish goto _fini_exit; 548644961713Sgirish } 548744961713Sgirish 548844961713Sgirish mac_fini_ops(&nxge_dev_ops); 548944961713Sgirish 549044961713Sgirish ddi_soft_state_fini(&nxge_list); 549144961713Sgirish 54923b2d9860SMichael Speer NXGE_DEBUG_MSG((NULL, MOD_CTL, "<== _fini status = 0x%08x", status)); 54933b2d9860SMichael Speer 549444961713Sgirish MUTEX_DESTROY(&nxge_common_lock); 54953b2d9860SMichael Speer MUTEX_DESTROY(&nxgedebuglock); 54963b2d9860SMichael Speer return (status); 549744961713Sgirish 54983b2d9860SMichael Speer _fini_exit: 54993b2d9860SMichael Speer NXGE_DEBUG_MSG((NULL, MOD_CTL, "<== _fini status = 0x%08x", status)); 550044961713Sgirish return (status); 550144961713Sgirish } 550244961713Sgirish 550344961713Sgirish int 550444961713Sgirish _info(struct modinfo *modinfop) 550544961713Sgirish { 550644961713Sgirish int status; 550744961713Sgirish 550844961713Sgirish NXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _info")); 550944961713Sgirish status = mod_info(&modlinkage, modinfop); 551044961713Sgirish NXGE_DEBUG_MSG((NULL, MOD_CTL, " _info status = 0x%X", status)); 551144961713Sgirish 551244961713Sgirish return (status); 551344961713Sgirish } 551444961713Sgirish 5515da14cebeSEric Cheng /*ARGSUSED*/ 5516da14cebeSEric Cheng static int 5517da14cebeSEric Cheng nxge_tx_ring_start(mac_ring_driver_t rdriver, uint64_t mr_gen_num) 5518da14cebeSEric Cheng { 5519da14cebeSEric Cheng p_nxge_ring_handle_t rhp = (p_nxge_ring_handle_t)rdriver; 5520da14cebeSEric Cheng p_nxge_t nxgep = rhp->nxgep; 5521da14cebeSEric Cheng uint32_t channel; 5522da14cebeSEric Cheng p_tx_ring_t ring; 5523da14cebeSEric Cheng 5524da14cebeSEric Cheng channel = nxgep->pt_config.hw_config.tdc.start + rhp->index; 5525da14cebeSEric Cheng ring = nxgep->tx_rings->rings[channel]; 5526da14cebeSEric Cheng 5527da14cebeSEric Cheng MUTEX_ENTER(&ring->lock); 55280dc2366fSVenugopal Iyer ASSERT(ring->tx_ring_handle == NULL); 5529da14cebeSEric Cheng ring->tx_ring_handle = rhp->ring_handle; 5530da14cebeSEric Cheng MUTEX_EXIT(&ring->lock); 5531da14cebeSEric Cheng 5532da14cebeSEric Cheng return (0); 5533da14cebeSEric Cheng } 5534da14cebeSEric Cheng 5535da14cebeSEric Cheng static void 5536da14cebeSEric Cheng nxge_tx_ring_stop(mac_ring_driver_t rdriver) 5537da14cebeSEric Cheng { 5538da14cebeSEric Cheng p_nxge_ring_handle_t rhp = (p_nxge_ring_handle_t)rdriver; 5539da14cebeSEric Cheng p_nxge_t nxgep = rhp->nxgep; 5540da14cebeSEric Cheng uint32_t channel; 5541da14cebeSEric Cheng p_tx_ring_t ring; 5542da14cebeSEric Cheng 5543da14cebeSEric Cheng channel = nxgep->pt_config.hw_config.tdc.start + rhp->index; 5544da14cebeSEric Cheng ring = nxgep->tx_rings->rings[channel]; 5545da14cebeSEric Cheng 5546da14cebeSEric Cheng MUTEX_ENTER(&ring->lock); 55470dc2366fSVenugopal Iyer ASSERT(ring->tx_ring_handle != NULL); 5548da14cebeSEric Cheng ring->tx_ring_handle = (mac_ring_handle_t)NULL; 5549da14cebeSEric Cheng MUTEX_EXIT(&ring->lock); 5550da14cebeSEric Cheng } 5551da14cebeSEric Cheng 55520dc2366fSVenugopal Iyer int 5553da14cebeSEric Cheng nxge_rx_ring_start(mac_ring_driver_t rdriver, uint64_t mr_gen_num) 5554da14cebeSEric Cheng { 5555da14cebeSEric Cheng p_nxge_ring_handle_t rhp = (p_nxge_ring_handle_t)rdriver; 5556da14cebeSEric Cheng p_nxge_t nxgep = rhp->nxgep; 5557da14cebeSEric Cheng uint32_t channel; 5558da14cebeSEric Cheng p_rx_rcr_ring_t ring; 5559da14cebeSEric Cheng int i; 5560da14cebeSEric Cheng 5561da14cebeSEric Cheng channel = nxgep->pt_config.hw_config.start_rdc + rhp->index; 5562*86ef0a63SRichard Lowe ring = nxgep->rx_rcr_rings->rcr_rings[channel]; 5563da14cebeSEric Cheng 5564da14cebeSEric Cheng MUTEX_ENTER(&ring->lock); 5565da14cebeSEric Cheng 55660dc2366fSVenugopal Iyer if (ring->started) { 55670dc2366fSVenugopal Iyer ASSERT(ring->started == B_FALSE); 5568da14cebeSEric Cheng MUTEX_EXIT(&ring->lock); 5569da14cebeSEric Cheng return (0); 5570da14cebeSEric Cheng } 5571da14cebeSEric Cheng 5572da14cebeSEric Cheng /* set rcr_ring */ 5573da14cebeSEric Cheng for (i = 0; i < nxgep->ldgvp->maxldvs; i++) { 55740dc2366fSVenugopal Iyer if ((nxgep->ldgvp->ldvp[i].is_rxdma) && 5575da14cebeSEric Cheng (nxgep->ldgvp->ldvp[i].channel == channel)) { 5576da14cebeSEric Cheng ring->ldvp = &nxgep->ldgvp->ldvp[i]; 5577da14cebeSEric Cheng ring->ldgp = nxgep->ldgvp->ldvp[i].ldgp; 5578da14cebeSEric Cheng } 5579da14cebeSEric Cheng } 5580da14cebeSEric Cheng 5581da14cebeSEric Cheng ring->rcr_mac_handle = rhp->ring_handle; 5582da14cebeSEric Cheng ring->rcr_gen_num = mr_gen_num; 55830dc2366fSVenugopal Iyer ring->started = B_TRUE; 55840dc2366fSVenugopal Iyer rhp->ring_gen_num = mr_gen_num; 5585da14cebeSEric Cheng MUTEX_EXIT(&ring->lock); 5586da14cebeSEric Cheng 5587da14cebeSEric Cheng return (0); 5588da14cebeSEric Cheng } 5589da14cebeSEric Cheng 5590da14cebeSEric Cheng static void 5591da14cebeSEric Cheng nxge_rx_ring_stop(mac_ring_driver_t rdriver) 5592da14cebeSEric Cheng { 5593da14cebeSEric Cheng p_nxge_ring_handle_t rhp = (p_nxge_ring_handle_t)rdriver; 5594da14cebeSEric Cheng p_nxge_t nxgep = rhp->nxgep; 5595da14cebeSEric Cheng uint32_t channel; 5596da14cebeSEric Cheng p_rx_rcr_ring_t ring; 5597da14cebeSEric Cheng 5598da14cebeSEric Cheng channel = nxgep->pt_config.hw_config.start_rdc + rhp->index; 5599*86ef0a63SRichard Lowe ring = nxgep->rx_rcr_rings->rcr_rings[channel]; 5600da14cebeSEric Cheng 5601da14cebeSEric Cheng MUTEX_ENTER(&ring->lock); 56020dc2366fSVenugopal Iyer ASSERT(ring->started == B_TRUE); 5603da14cebeSEric Cheng ring->rcr_mac_handle = NULL; 56040dc2366fSVenugopal Iyer ring->ldvp = NULL; 56050dc2366fSVenugopal Iyer ring->ldgp = NULL; 56060dc2366fSVenugopal Iyer ring->started = B_FALSE; 5607da14cebeSEric Cheng MUTEX_EXIT(&ring->lock); 5608da14cebeSEric Cheng } 5609da14cebeSEric Cheng 56100dc2366fSVenugopal Iyer static int 56110dc2366fSVenugopal Iyer nxge_ring_get_htable_idx(p_nxge_t nxgep, mac_ring_type_t type, uint32_t channel) 56120dc2366fSVenugopal Iyer { 56130dc2366fSVenugopal Iyer int i; 56140dc2366fSVenugopal Iyer 56150dc2366fSVenugopal Iyer #if defined(sun4v) 56160dc2366fSVenugopal Iyer if (isLDOMguest(nxgep)) { 56170dc2366fSVenugopal Iyer return (nxge_hio_get_dc_htable_idx(nxgep, 56180dc2366fSVenugopal Iyer (type == MAC_RING_TYPE_TX) ? VP_BOUND_TX : VP_BOUND_RX, 56190dc2366fSVenugopal Iyer channel)); 56200dc2366fSVenugopal Iyer } 56210dc2366fSVenugopal Iyer #endif 56220dc2366fSVenugopal Iyer 56230dc2366fSVenugopal Iyer ASSERT(nxgep->ldgvp != NULL); 56240dc2366fSVenugopal Iyer 56250dc2366fSVenugopal Iyer switch (type) { 56260dc2366fSVenugopal Iyer case MAC_RING_TYPE_TX: 56270dc2366fSVenugopal Iyer for (i = 0; i < nxgep->ldgvp->maxldvs; i++) { 56280dc2366fSVenugopal Iyer if ((nxgep->ldgvp->ldvp[i].is_txdma) && 56290dc2366fSVenugopal Iyer (nxgep->ldgvp->ldvp[i].channel == channel)) { 56300dc2366fSVenugopal Iyer return ((int) 56310dc2366fSVenugopal Iyer nxgep->ldgvp->ldvp[i].ldgp->htable_idx); 56320dc2366fSVenugopal Iyer } 56330dc2366fSVenugopal Iyer } 56340dc2366fSVenugopal Iyer break; 56350dc2366fSVenugopal Iyer 56360dc2366fSVenugopal Iyer case MAC_RING_TYPE_RX: 56370dc2366fSVenugopal Iyer for (i = 0; i < nxgep->ldgvp->maxldvs; i++) { 56380dc2366fSVenugopal Iyer if ((nxgep->ldgvp->ldvp[i].is_rxdma) && 56390dc2366fSVenugopal Iyer (nxgep->ldgvp->ldvp[i].channel == channel)) { 56400dc2366fSVenugopal Iyer return ((int) 56410dc2366fSVenugopal Iyer nxgep->ldgvp->ldvp[i].ldgp->htable_idx); 56420dc2366fSVenugopal Iyer } 56430dc2366fSVenugopal Iyer } 56440dc2366fSVenugopal Iyer } 56450dc2366fSVenugopal Iyer 56460dc2366fSVenugopal Iyer return (-1); 56470dc2366fSVenugopal Iyer } 56480dc2366fSVenugopal Iyer 5649da14cebeSEric Cheng /* 5650da14cebeSEric Cheng * Callback funtion for MAC layer to register all rings. 5651da14cebeSEric Cheng */ 5652da14cebeSEric Cheng static void 5653da14cebeSEric Cheng nxge_fill_ring(void *arg, mac_ring_type_t rtype, const int rg_index, 5654da14cebeSEric Cheng const int index, mac_ring_info_t *infop, mac_ring_handle_t rh) 5655da14cebeSEric Cheng { 5656da14cebeSEric Cheng p_nxge_t nxgep = (p_nxge_t)arg; 5657da14cebeSEric Cheng p_nxge_hw_pt_cfg_t p_cfgp = &nxgep->pt_config.hw_config; 56580dc2366fSVenugopal Iyer p_nxge_intr_t intrp; 56590dc2366fSVenugopal Iyer uint32_t channel; 56600dc2366fSVenugopal Iyer int htable_idx; 56610dc2366fSVenugopal Iyer p_nxge_ring_handle_t rhandlep; 56620dc2366fSVenugopal Iyer 56630dc2366fSVenugopal Iyer ASSERT(nxgep != NULL); 56640dc2366fSVenugopal Iyer ASSERT(p_cfgp != NULL); 56650dc2366fSVenugopal Iyer ASSERT(infop != NULL); 5666da14cebeSEric Cheng 56670dc2366fSVenugopal Iyer NXGE_DEBUG_MSG((nxgep, DDI_CTL, 5668da14cebeSEric Cheng "==> nxge_fill_ring 0x%x index %d", rtype, index)); 5669da14cebeSEric Cheng 56700dc2366fSVenugopal Iyer 5671da14cebeSEric Cheng switch (rtype) { 5672da14cebeSEric Cheng case MAC_RING_TYPE_TX: { 56730dc2366fSVenugopal Iyer mac_intr_t *mintr = &infop->mri_intr; 5674da14cebeSEric Cheng 5675da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, TX_CTL, 5676da14cebeSEric Cheng "==> nxge_fill_ring (TX) 0x%x index %d ntdcs %d", 5677da14cebeSEric Cheng rtype, index, p_cfgp->tdc.count)); 5678da14cebeSEric Cheng 5679da14cebeSEric Cheng ASSERT((index >= 0) && (index < p_cfgp->tdc.count)); 5680da14cebeSEric Cheng rhandlep = &nxgep->tx_ring_handles[index]; 5681da14cebeSEric Cheng rhandlep->nxgep = nxgep; 5682da14cebeSEric Cheng rhandlep->index = index; 5683da14cebeSEric Cheng rhandlep->ring_handle = rh; 5684da14cebeSEric Cheng 56850dc2366fSVenugopal Iyer channel = nxgep->pt_config.hw_config.tdc.start + index; 56860dc2366fSVenugopal Iyer rhandlep->channel = channel; 56870dc2366fSVenugopal Iyer intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 56880dc2366fSVenugopal Iyer htable_idx = nxge_ring_get_htable_idx(nxgep, rtype, 56890dc2366fSVenugopal Iyer channel); 56900dc2366fSVenugopal Iyer if (htable_idx >= 0) 56910dc2366fSVenugopal Iyer mintr->mi_ddi_handle = intrp->htable[htable_idx]; 56920dc2366fSVenugopal Iyer else 56930dc2366fSVenugopal Iyer mintr->mi_ddi_handle = NULL; 56940dc2366fSVenugopal Iyer 5695da14cebeSEric Cheng infop->mri_driver = (mac_ring_driver_t)rhandlep; 5696da14cebeSEric Cheng infop->mri_start = nxge_tx_ring_start; 5697da14cebeSEric Cheng infop->mri_stop = nxge_tx_ring_stop; 5698da14cebeSEric Cheng infop->mri_tx = nxge_tx_ring_send; 56990dc2366fSVenugopal Iyer infop->mri_stat = nxge_tx_ring_stat; 57000dc2366fSVenugopal Iyer infop->mri_flags = MAC_RING_TX_SERIALIZE; 5701da14cebeSEric Cheng break; 5702da14cebeSEric Cheng } 57030dc2366fSVenugopal Iyer 5704da14cebeSEric Cheng case MAC_RING_TYPE_RX: { 5705da14cebeSEric Cheng mac_intr_t nxge_mac_intr; 57060dc2366fSVenugopal Iyer int nxge_rindex; 57070dc2366fSVenugopal Iyer p_nxge_intr_t intrp; 57080dc2366fSVenugopal Iyer 57090dc2366fSVenugopal Iyer intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 5710da14cebeSEric Cheng 5711da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, RX_CTL, 5712da14cebeSEric Cheng "==> nxge_fill_ring (RX) 0x%x index %d nrdcs %d", 5713da14cebeSEric Cheng rtype, index, p_cfgp->max_rdcs)); 5714da14cebeSEric Cheng 5715da14cebeSEric Cheng /* 5716da14cebeSEric Cheng * 'index' is the ring index within the group. 5717da14cebeSEric Cheng * Find the ring index in the nxge instance. 5718da14cebeSEric Cheng */ 5719da14cebeSEric Cheng nxge_rindex = nxge_get_rxring_index(nxgep, rg_index, index); 57200dc2366fSVenugopal Iyer channel = nxgep->pt_config.hw_config.start_rdc + index; 57210dc2366fSVenugopal Iyer intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 5722da14cebeSEric Cheng 5723da14cebeSEric Cheng ASSERT((nxge_rindex >= 0) && (nxge_rindex < p_cfgp->max_rdcs)); 5724da14cebeSEric Cheng rhandlep = &nxgep->rx_ring_handles[nxge_rindex]; 5725da14cebeSEric Cheng rhandlep->nxgep = nxgep; 5726da14cebeSEric Cheng rhandlep->index = nxge_rindex; 5727da14cebeSEric Cheng rhandlep->ring_handle = rh; 57280dc2366fSVenugopal Iyer rhandlep->channel = channel; 5729da14cebeSEric Cheng 5730da14cebeSEric Cheng /* 5731da14cebeSEric Cheng * Entrypoint to enable interrupt (disable poll) and 5732da14cebeSEric Cheng * disable interrupt (enable poll). 5733da14cebeSEric Cheng */ 57340dc2366fSVenugopal Iyer bzero(&nxge_mac_intr, sizeof (nxge_mac_intr)); 5735da14cebeSEric Cheng nxge_mac_intr.mi_handle = (mac_intr_handle_t)rhandlep; 5736da14cebeSEric Cheng nxge_mac_intr.mi_enable = (mac_intr_enable_t)nxge_disable_poll; 5737da14cebeSEric Cheng nxge_mac_intr.mi_disable = (mac_intr_disable_t)nxge_enable_poll; 57380dc2366fSVenugopal Iyer 57390dc2366fSVenugopal Iyer htable_idx = nxge_ring_get_htable_idx(nxgep, rtype, 57400dc2366fSVenugopal Iyer channel); 57410dc2366fSVenugopal Iyer if (htable_idx >= 0) 57420dc2366fSVenugopal Iyer nxge_mac_intr.mi_ddi_handle = intrp->htable[htable_idx]; 57430dc2366fSVenugopal Iyer else 57440dc2366fSVenugopal Iyer nxge_mac_intr.mi_ddi_handle = NULL; 57450dc2366fSVenugopal Iyer 5746da14cebeSEric Cheng infop->mri_driver = (mac_ring_driver_t)rhandlep; 5747da14cebeSEric Cheng infop->mri_start = nxge_rx_ring_start; 5748da14cebeSEric Cheng infop->mri_stop = nxge_rx_ring_stop; 57490dc2366fSVenugopal Iyer infop->mri_intr = nxge_mac_intr; 5750da14cebeSEric Cheng infop->mri_poll = nxge_rx_poll; 57510dc2366fSVenugopal Iyer infop->mri_stat = nxge_rx_ring_stat; 57520dc2366fSVenugopal Iyer infop->mri_flags = MAC_RING_RX_ENQUEUE; 5753da14cebeSEric Cheng break; 5754da14cebeSEric Cheng } 57550dc2366fSVenugopal Iyer 5756da14cebeSEric Cheng default: 5757da14cebeSEric Cheng break; 5758da14cebeSEric Cheng } 5759da14cebeSEric Cheng 57600dc2366fSVenugopal Iyer NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_fill_ring 0x%x", rtype)); 5761da14cebeSEric Cheng } 5762da14cebeSEric Cheng 5763da14cebeSEric Cheng static void 5764da14cebeSEric Cheng nxge_group_add_ring(mac_group_driver_t gh, mac_ring_driver_t rh, 5765da14cebeSEric Cheng mac_ring_type_t type) 5766da14cebeSEric Cheng { 5767da14cebeSEric Cheng nxge_ring_group_t *rgroup = (nxge_ring_group_t *)gh; 5768da14cebeSEric Cheng nxge_ring_handle_t *rhandle = (nxge_ring_handle_t *)rh; 5769da14cebeSEric Cheng nxge_t *nxge; 5770da14cebeSEric Cheng nxge_grp_t *grp; 5771da14cebeSEric Cheng nxge_rdc_grp_t *rdc_grp; 5772da14cebeSEric Cheng uint16_t channel; /* device-wise ring id */ 5773da14cebeSEric Cheng int dev_gindex; 5774da14cebeSEric Cheng int rv; 5775da14cebeSEric Cheng 5776da14cebeSEric Cheng nxge = rgroup->nxgep; 5777da14cebeSEric Cheng 5778da14cebeSEric Cheng switch (type) { 5779da14cebeSEric Cheng case MAC_RING_TYPE_TX: 5780da14cebeSEric Cheng /* 5781da14cebeSEric Cheng * nxge_grp_dc_add takes a channel number which is a 5782da14cebeSEric Cheng * "devise" ring ID. 5783da14cebeSEric Cheng */ 5784da14cebeSEric Cheng channel = nxge->pt_config.hw_config.tdc.start + rhandle->index; 5785da14cebeSEric Cheng 5786da14cebeSEric Cheng /* 5787da14cebeSEric Cheng * Remove the ring from the default group 5788da14cebeSEric Cheng */ 5789da14cebeSEric Cheng if (rgroup->gindex != 0) { 5790da14cebeSEric Cheng (void) nxge_grp_dc_remove(nxge, VP_BOUND_TX, channel); 5791da14cebeSEric Cheng } 5792da14cebeSEric Cheng 5793da14cebeSEric Cheng /* 5794da14cebeSEric Cheng * nxge->tx_set.group[] is an array of groups indexed by 5795da14cebeSEric Cheng * a "port" group ID. 5796da14cebeSEric Cheng */ 5797da14cebeSEric Cheng grp = nxge->tx_set.group[rgroup->gindex]; 5798da14cebeSEric Cheng rv = nxge_grp_dc_add(nxge, grp, VP_BOUND_TX, channel); 5799da14cebeSEric Cheng if (rv != 0) { 5800da14cebeSEric Cheng NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, 5801da14cebeSEric Cheng "nxge_group_add_ring: nxge_grp_dc_add failed")); 5802da14cebeSEric Cheng } 5803da14cebeSEric Cheng break; 5804da14cebeSEric Cheng 5805da14cebeSEric Cheng case MAC_RING_TYPE_RX: 5806da14cebeSEric Cheng /* 5807da14cebeSEric Cheng * nxge->rx_set.group[] is an array of groups indexed by 5808da14cebeSEric Cheng * a "port" group ID. 5809da14cebeSEric Cheng */ 5810da14cebeSEric Cheng grp = nxge->rx_set.group[rgroup->gindex]; 5811da14cebeSEric Cheng 5812da14cebeSEric Cheng dev_gindex = nxge->pt_config.hw_config.def_mac_rxdma_grpid + 5813da14cebeSEric Cheng rgroup->gindex; 5814da14cebeSEric Cheng rdc_grp = &nxge->pt_config.rdc_grps[dev_gindex]; 5815da14cebeSEric Cheng 5816da14cebeSEric Cheng /* 5817da14cebeSEric Cheng * nxge_grp_dc_add takes a channel number which is a 5818da14cebeSEric Cheng * "devise" ring ID. 5819da14cebeSEric Cheng */ 5820da14cebeSEric Cheng channel = nxge->pt_config.hw_config.start_rdc + rhandle->index; 5821da14cebeSEric Cheng rv = nxge_grp_dc_add(nxge, grp, VP_BOUND_RX, channel); 5822da14cebeSEric Cheng if (rv != 0) { 5823da14cebeSEric Cheng NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, 5824da14cebeSEric Cheng "nxge_group_add_ring: nxge_grp_dc_add failed")); 5825da14cebeSEric Cheng } 5826da14cebeSEric Cheng 5827da14cebeSEric Cheng rdc_grp->map |= (1 << channel); 5828da14cebeSEric Cheng rdc_grp->max_rdcs++; 5829da14cebeSEric Cheng 58304ba491f5SMichael Speer (void) nxge_init_fzc_rdc_tbl(nxge, rdc_grp, rgroup->rdctbl); 5831da14cebeSEric Cheng break; 5832da14cebeSEric Cheng } 5833da14cebeSEric Cheng } 5834da14cebeSEric Cheng 5835da14cebeSEric Cheng static void 5836da14cebeSEric Cheng nxge_group_rem_ring(mac_group_driver_t gh, mac_ring_driver_t rh, 5837da14cebeSEric Cheng mac_ring_type_t type) 5838da14cebeSEric Cheng { 5839da14cebeSEric Cheng nxge_ring_group_t *rgroup = (nxge_ring_group_t *)gh; 5840da14cebeSEric Cheng nxge_ring_handle_t *rhandle = (nxge_ring_handle_t *)rh; 5841da14cebeSEric Cheng nxge_t *nxge; 5842da14cebeSEric Cheng uint16_t channel; /* device-wise ring id */ 5843da14cebeSEric Cheng nxge_rdc_grp_t *rdc_grp; 5844da14cebeSEric Cheng int dev_gindex; 5845da14cebeSEric Cheng 5846da14cebeSEric Cheng nxge = rgroup->nxgep; 5847da14cebeSEric Cheng 5848da14cebeSEric Cheng switch (type) { 5849da14cebeSEric Cheng case MAC_RING_TYPE_TX: 5850da14cebeSEric Cheng dev_gindex = nxge->pt_config.hw_config.def_mac_txdma_grpid + 5851da14cebeSEric Cheng rgroup->gindex; 5852da14cebeSEric Cheng channel = nxge->pt_config.hw_config.tdc.start + rhandle->index; 5853da14cebeSEric Cheng nxge_grp_dc_remove(nxge, VP_BOUND_TX, channel); 5854da14cebeSEric Cheng 5855da14cebeSEric Cheng /* 5856da14cebeSEric Cheng * Add the ring back to the default group 5857da14cebeSEric Cheng */ 5858da14cebeSEric Cheng if (rgroup->gindex != 0) { 5859da14cebeSEric Cheng nxge_grp_t *grp; 5860da14cebeSEric Cheng grp = nxge->tx_set.group[0]; 5861da14cebeSEric Cheng (void) nxge_grp_dc_add(nxge, grp, VP_BOUND_TX, channel); 5862da14cebeSEric Cheng } 5863da14cebeSEric Cheng break; 5864da14cebeSEric Cheng 5865da14cebeSEric Cheng case MAC_RING_TYPE_RX: 5866da14cebeSEric Cheng dev_gindex = nxge->pt_config.hw_config.def_mac_rxdma_grpid + 5867da14cebeSEric Cheng rgroup->gindex; 5868da14cebeSEric Cheng rdc_grp = &nxge->pt_config.rdc_grps[dev_gindex]; 5869da14cebeSEric Cheng channel = rdc_grp->start_rdc + rhandle->index; 5870da14cebeSEric Cheng nxge_grp_dc_remove(nxge, VP_BOUND_RX, channel); 5871da14cebeSEric Cheng 5872da14cebeSEric Cheng rdc_grp->map &= ~(1 << channel); 5873da14cebeSEric Cheng rdc_grp->max_rdcs--; 5874da14cebeSEric Cheng 58754ba491f5SMichael Speer (void) nxge_init_fzc_rdc_tbl(nxge, rdc_grp, rgroup->rdctbl); 5876da14cebeSEric Cheng break; 5877da14cebeSEric Cheng } 5878da14cebeSEric Cheng } 5879da14cebeSEric Cheng 5880da14cebeSEric Cheng 588144961713Sgirish /*ARGSUSED*/ 588244961713Sgirish static nxge_status_t 588344961713Sgirish nxge_add_intrs(p_nxge_t nxgep) 588444961713Sgirish { 588544961713Sgirish 588644961713Sgirish int intr_types; 588744961713Sgirish int type = 0; 588844961713Sgirish int ddi_status = DDI_SUCCESS; 588944961713Sgirish nxge_status_t status = NXGE_OK; 589044961713Sgirish 589144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs")); 589244961713Sgirish 589344961713Sgirish nxgep->nxge_intr_type.intr_registered = B_FALSE; 589444961713Sgirish nxgep->nxge_intr_type.intr_enabled = B_FALSE; 589544961713Sgirish nxgep->nxge_intr_type.msi_intx_cnt = 0; 589644961713Sgirish nxgep->nxge_intr_type.intr_added = 0; 589744961713Sgirish nxgep->nxge_intr_type.niu_msi_enable = B_FALSE; 589844961713Sgirish nxgep->nxge_intr_type.intr_type = 0; 589944961713Sgirish 590044961713Sgirish if (nxgep->niu_type == N2_NIU) { 590144961713Sgirish nxgep->nxge_intr_type.niu_msi_enable = B_TRUE; 590244961713Sgirish } else if (nxge_msi_enable) { 590344961713Sgirish nxgep->nxge_intr_type.niu_msi_enable = B_TRUE; 590444961713Sgirish } 590544961713Sgirish 590644961713Sgirish /* Get the supported interrupt types */ 590744961713Sgirish if ((ddi_status = ddi_intr_get_supported_types(nxgep->dip, &intr_types)) 59084045d941Ssowmini != DDI_SUCCESS) { 590944961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_add_intrs: " 59104045d941Ssowmini "ddi_intr_get_supported_types failed: status 0x%08x", 59114045d941Ssowmini ddi_status)); 591244961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 591344961713Sgirish } 591444961713Sgirish nxgep->nxge_intr_type.intr_types = intr_types; 591544961713Sgirish 591644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 59174045d941Ssowmini "ddi_intr_get_supported_types: 0x%08x", intr_types)); 591844961713Sgirish 591944961713Sgirish /* 592044961713Sgirish * Solaris MSIX is not supported yet. use MSI for now. 592144961713Sgirish * nxge_msi_enable (1): 592244961713Sgirish * 1 - MSI 2 - MSI-X others - FIXED 592344961713Sgirish */ 592444961713Sgirish switch (nxge_msi_enable) { 592544961713Sgirish default: 592644961713Sgirish type = DDI_INTR_TYPE_FIXED; 592744961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: " 59284045d941Ssowmini "use fixed (intx emulation) type %08x", 59294045d941Ssowmini type)); 593044961713Sgirish break; 593144961713Sgirish 593244961713Sgirish case 2: 593344961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: " 59344045d941Ssowmini "ddi_intr_get_supported_types: 0x%08x", intr_types)); 593544961713Sgirish if (intr_types & DDI_INTR_TYPE_MSIX) { 593644961713Sgirish type = DDI_INTR_TYPE_MSIX; 593744961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 59384045d941Ssowmini "ddi_intr_get_supported_types: MSIX 0x%08x", 59394045d941Ssowmini type)); 594044961713Sgirish } else if (intr_types & DDI_INTR_TYPE_MSI) { 594144961713Sgirish type = DDI_INTR_TYPE_MSI; 594244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 59434045d941Ssowmini "ddi_intr_get_supported_types: MSI 0x%08x", 59444045d941Ssowmini type)); 594544961713Sgirish } else if (intr_types & DDI_INTR_TYPE_FIXED) { 594644961713Sgirish type = DDI_INTR_TYPE_FIXED; 594744961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: " 59484045d941Ssowmini "ddi_intr_get_supported_types: MSXED0x%08x", 59494045d941Ssowmini type)); 595044961713Sgirish } 595144961713Sgirish break; 595244961713Sgirish 595344961713Sgirish case 1: 595444961713Sgirish if (intr_types & DDI_INTR_TYPE_MSI) { 595544961713Sgirish type = DDI_INTR_TYPE_MSI; 595644961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: " 59574045d941Ssowmini "ddi_intr_get_supported_types: MSI 0x%08x", 59584045d941Ssowmini type)); 595944961713Sgirish } else if (intr_types & DDI_INTR_TYPE_MSIX) { 596044961713Sgirish type = DDI_INTR_TYPE_MSIX; 596144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 59624045d941Ssowmini "ddi_intr_get_supported_types: MSIX 0x%08x", 59634045d941Ssowmini type)); 596444961713Sgirish } else if (intr_types & DDI_INTR_TYPE_FIXED) { 596544961713Sgirish type = DDI_INTR_TYPE_FIXED; 596644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 59674045d941Ssowmini "ddi_intr_get_supported_types: MSXED0x%08x", 59684045d941Ssowmini type)); 596944961713Sgirish } 597044961713Sgirish } 597144961713Sgirish 597244961713Sgirish nxgep->nxge_intr_type.intr_type = type; 597344961713Sgirish if ((type == DDI_INTR_TYPE_MSIX || type == DDI_INTR_TYPE_MSI || 59744045d941Ssowmini type == DDI_INTR_TYPE_FIXED) && 59754045d941Ssowmini nxgep->nxge_intr_type.niu_msi_enable) { 597644961713Sgirish if ((status = nxge_add_intrs_adv(nxgep)) != DDI_SUCCESS) { 597744961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 59784045d941Ssowmini " nxge_add_intrs: " 59794045d941Ssowmini " nxge_add_intrs_adv failed: status 0x%08x", 59804045d941Ssowmini status)); 598144961713Sgirish return (status); 598244961713Sgirish } else { 598344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 59844045d941Ssowmini "interrupts registered : type %d", type)); 598544961713Sgirish nxgep->nxge_intr_type.intr_registered = B_TRUE; 598644961713Sgirish 598744961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 59884045d941Ssowmini "\nAdded advanced nxge add_intr_adv " 59894045d941Ssowmini "intr type 0x%x\n", type)); 599044961713Sgirish 599144961713Sgirish return (status); 599244961713Sgirish } 599344961713Sgirish } 599444961713Sgirish 599544961713Sgirish if (!nxgep->nxge_intr_type.intr_registered) { 599644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "==> nxge_add_intrs: " 59974045d941Ssowmini "failed to register interrupts")); 599844961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 599944961713Sgirish } 600044961713Sgirish 600144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_add_intrs")); 600244961713Sgirish return (status); 600344961713Sgirish } 600444961713Sgirish 600544961713Sgirish static nxge_status_t 600644961713Sgirish nxge_add_intrs_adv(p_nxge_t nxgep) 600744961713Sgirish { 600844961713Sgirish int intr_type; 600944961713Sgirish p_nxge_intr_t intrp; 601044961713Sgirish 601144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs_adv")); 601244961713Sgirish 601344961713Sgirish intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 601444961713Sgirish intr_type = intrp->intr_type; 601544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs_adv: type 0x%x", 60164045d941Ssowmini intr_type)); 601744961713Sgirish 601844961713Sgirish switch (intr_type) { 601944961713Sgirish case DDI_INTR_TYPE_MSI: /* 0x2 */ 602044961713Sgirish case DDI_INTR_TYPE_MSIX: /* 0x4 */ 602144961713Sgirish return (nxge_add_intrs_adv_type(nxgep, intr_type)); 602244961713Sgirish 602344961713Sgirish case DDI_INTR_TYPE_FIXED: /* 0x1 */ 602444961713Sgirish return (nxge_add_intrs_adv_type_fix(nxgep, intr_type)); 602544961713Sgirish 602644961713Sgirish default: 602744961713Sgirish return (NXGE_ERROR); 602844961713Sgirish } 602944961713Sgirish } 603044961713Sgirish 603144961713Sgirish 603244961713Sgirish /*ARGSUSED*/ 603344961713Sgirish static nxge_status_t 603444961713Sgirish nxge_add_intrs_adv_type(p_nxge_t nxgep, uint32_t int_type) 603544961713Sgirish { 603644961713Sgirish dev_info_t *dip = nxgep->dip; 603744961713Sgirish p_nxge_ldg_t ldgp; 603844961713Sgirish p_nxge_intr_t intrp; 6039e3d11eeeSToomas Soome ddi_intr_handler_t *inthandler; 604044961713Sgirish void *arg1, *arg2; 604144961713Sgirish int behavior; 6042ec090658Sml int nintrs, navail, nrequest; 604344961713Sgirish int nactual, nrequired; 604444961713Sgirish int inum = 0; 604544961713Sgirish int x, y; 604644961713Sgirish int ddi_status = DDI_SUCCESS; 604744961713Sgirish nxge_status_t status = NXGE_OK; 604844961713Sgirish 604944961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs_adv_type")); 605044961713Sgirish intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 605144961713Sgirish intrp->start_inum = 0; 605244961713Sgirish 605344961713Sgirish ddi_status = ddi_intr_get_nintrs(dip, int_type, &nintrs); 605444961713Sgirish if ((ddi_status != DDI_SUCCESS) || (nintrs == 0)) { 605544961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 60564045d941Ssowmini "ddi_intr_get_nintrs() failed, status: 0x%x%, " 60574045d941Ssowmini "nintrs: %d", ddi_status, nintrs)); 605844961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 605944961713Sgirish } 606044961713Sgirish 606144961713Sgirish ddi_status = ddi_intr_get_navail(dip, int_type, &navail); 606244961713Sgirish if ((ddi_status != DDI_SUCCESS) || (navail == 0)) { 606344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 60644045d941Ssowmini "ddi_intr_get_navail() failed, status: 0x%x%, " 60654045d941Ssowmini "nintrs: %d", ddi_status, navail)); 606644961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 606744961713Sgirish } 606844961713Sgirish 606944961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 60704045d941Ssowmini "ddi_intr_get_navail() returned: nintrs %d, navail %d", 60714045d941Ssowmini nintrs, navail)); 607244961713Sgirish 6073ec090658Sml /* PSARC/2007/453 MSI-X interrupt limit override */ 6074ec090658Sml if (int_type == DDI_INTR_TYPE_MSIX) { 6075ec090658Sml nrequest = nxge_create_msi_property(nxgep); 6076ec090658Sml if (nrequest < navail) { 6077ec090658Sml navail = nrequest; 6078ec090658Sml NXGE_DEBUG_MSG((nxgep, INT_CTL, 6079ec090658Sml "nxge_add_intrs_adv_type: nintrs %d " 6080ec090658Sml "navail %d (nrequest %d)", 6081ec090658Sml nintrs, navail, nrequest)); 6082ec090658Sml } 6083ec090658Sml } 6084ec090658Sml 608544961713Sgirish if (int_type == DDI_INTR_TYPE_MSI && !ISP2(navail)) { 608644961713Sgirish /* MSI must be power of 2 */ 608744961713Sgirish if ((navail & 16) == 16) { 608844961713Sgirish navail = 16; 608944961713Sgirish } else if ((navail & 8) == 8) { 609044961713Sgirish navail = 8; 609144961713Sgirish } else if ((navail & 4) == 4) { 609244961713Sgirish navail = 4; 609344961713Sgirish } else if ((navail & 2) == 2) { 609444961713Sgirish navail = 2; 609544961713Sgirish } else { 609644961713Sgirish navail = 1; 609744961713Sgirish } 609844961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 60994045d941Ssowmini "ddi_intr_get_navail(): (msi power of 2) nintrs %d, " 61004045d941Ssowmini "navail %d", nintrs, navail)); 610144961713Sgirish } 610244961713Sgirish 610344961713Sgirish behavior = ((int_type == DDI_INTR_TYPE_FIXED) ? DDI_INTR_ALLOC_STRICT : 61044045d941Ssowmini DDI_INTR_ALLOC_NORMAL); 610544961713Sgirish intrp->intr_size = navail * sizeof (ddi_intr_handle_t); 610644961713Sgirish intrp->htable = kmem_alloc(intrp->intr_size, KM_SLEEP); 610744961713Sgirish ddi_status = ddi_intr_alloc(dip, intrp->htable, int_type, inum, 61084045d941Ssowmini navail, &nactual, behavior); 610944961713Sgirish if (ddi_status != DDI_SUCCESS || nactual == 0) { 611044961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 61114045d941Ssowmini " ddi_intr_alloc() failed: %d", 61124045d941Ssowmini ddi_status)); 611344961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 611444961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 611544961713Sgirish } 611644961713Sgirish 611744961713Sgirish if ((ddi_status = ddi_intr_get_pri(intrp->htable[0], 61184045d941Ssowmini (uint_t *)&intrp->pri)) != DDI_SUCCESS) { 611944961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 61204045d941Ssowmini " ddi_intr_get_pri() failed: %d", 61214045d941Ssowmini ddi_status)); 612244961713Sgirish /* Free already allocated interrupts */ 612344961713Sgirish for (y = 0; y < nactual; y++) { 612444961713Sgirish (void) ddi_intr_free(intrp->htable[y]); 612544961713Sgirish } 612644961713Sgirish 612744961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 612844961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 612944961713Sgirish } 613044961713Sgirish 613144961713Sgirish nrequired = 0; 613244961713Sgirish switch (nxgep->niu_type) { 613344961713Sgirish default: 613444961713Sgirish status = nxge_ldgv_init(nxgep, &nactual, &nrequired); 613544961713Sgirish break; 613644961713Sgirish 613744961713Sgirish case N2_NIU: 613844961713Sgirish status = nxge_ldgv_init_n2(nxgep, &nactual, &nrequired); 613944961713Sgirish break; 614044961713Sgirish } 614144961713Sgirish 614244961713Sgirish if (status != NXGE_OK) { 614344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 61444045d941Ssowmini "nxge_add_intrs_adv_typ:nxge_ldgv_init " 61454045d941Ssowmini "failed: 0x%x", status)); 614644961713Sgirish /* Free already allocated interrupts */ 614744961713Sgirish for (y = 0; y < nactual; y++) { 614844961713Sgirish (void) ddi_intr_free(intrp->htable[y]); 614944961713Sgirish } 615044961713Sgirish 615144961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 615244961713Sgirish return (status); 615344961713Sgirish } 615444961713Sgirish 615544961713Sgirish ldgp = nxgep->ldgvp->ldgp; 615644961713Sgirish for (x = 0; x < nrequired; x++, ldgp++) { 615744961713Sgirish ldgp->vector = (uint8_t)x; 615844961713Sgirish ldgp->intdata = SID_DATA(ldgp->func, x); 615944961713Sgirish arg1 = ldgp->ldvp; 616044961713Sgirish arg2 = nxgep; 616144961713Sgirish if (ldgp->nldvs == 1) { 6162e3d11eeeSToomas Soome inthandler = ldgp->ldvp->ldv_intr_handler; 616344961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 61644045d941Ssowmini "nxge_add_intrs_adv_type: " 61654045d941Ssowmini "arg1 0x%x arg2 0x%x: " 61664045d941Ssowmini "1-1 int handler (entry %d intdata 0x%x)\n", 61674045d941Ssowmini arg1, arg2, 61684045d941Ssowmini x, ldgp->intdata)); 616944961713Sgirish } else if (ldgp->nldvs > 1) { 6170e3d11eeeSToomas Soome inthandler = ldgp->sys_intr_handler; 617144961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 61724045d941Ssowmini "nxge_add_intrs_adv_type: " 61734045d941Ssowmini "arg1 0x%x arg2 0x%x: " 61744045d941Ssowmini "nldevs %d int handler " 61754045d941Ssowmini "(entry %d intdata 0x%x)\n", 61764045d941Ssowmini arg1, arg2, 61774045d941Ssowmini ldgp->nldvs, x, ldgp->intdata)); 6178e3d11eeeSToomas Soome } else { 6179e3d11eeeSToomas Soome inthandler = NULL; 618044961713Sgirish } 618144961713Sgirish 618244961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 61834045d941Ssowmini "==> nxge_add_intrs_adv_type: ddi_add_intr(inum) #%d " 61844045d941Ssowmini "htable 0x%llx", x, intrp->htable[x])); 618544961713Sgirish 618644961713Sgirish if ((ddi_status = ddi_intr_add_handler(intrp->htable[x], 6187e3d11eeeSToomas Soome inthandler, arg1, arg2)) != DDI_SUCCESS) { 618844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 61894045d941Ssowmini "==> nxge_add_intrs_adv_type: failed #%d " 61904045d941Ssowmini "status 0x%x", x, ddi_status)); 619144961713Sgirish for (y = 0; y < intrp->intr_added; y++) { 619244961713Sgirish (void) ddi_intr_remove_handler( 61934045d941Ssowmini intrp->htable[y]); 619444961713Sgirish } 619544961713Sgirish /* Free already allocated intr */ 619644961713Sgirish for (y = 0; y < nactual; y++) { 619744961713Sgirish (void) ddi_intr_free(intrp->htable[y]); 619844961713Sgirish } 619944961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 620044961713Sgirish 620144961713Sgirish (void) nxge_ldgv_uninit(nxgep); 620244961713Sgirish 620344961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 620444961713Sgirish } 62050dc2366fSVenugopal Iyer 62060dc2366fSVenugopal Iyer ldgp->htable_idx = x; 620744961713Sgirish intrp->intr_added++; 620844961713Sgirish } 620944961713Sgirish 621044961713Sgirish intrp->msi_intx_cnt = nactual; 621144961713Sgirish 621244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 62134045d941Ssowmini "Requested: %d, Allowed: %d msi_intx_cnt %d intr_added %d", 62144045d941Ssowmini navail, nactual, 62154045d941Ssowmini intrp->msi_intx_cnt, 62164045d941Ssowmini intrp->intr_added)); 621744961713Sgirish 621844961713Sgirish (void) ddi_intr_get_cap(intrp->htable[0], &intrp->intr_cap); 621944961713Sgirish 622044961713Sgirish (void) nxge_intr_ldgv_init(nxgep); 622144961713Sgirish 622244961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_add_intrs_adv_type")); 622344961713Sgirish 622444961713Sgirish return (status); 622544961713Sgirish } 622644961713Sgirish 622744961713Sgirish /*ARGSUSED*/ 622844961713Sgirish static nxge_status_t 622944961713Sgirish nxge_add_intrs_adv_type_fix(p_nxge_t nxgep, uint32_t int_type) 623044961713Sgirish { 623144961713Sgirish dev_info_t *dip = nxgep->dip; 623244961713Sgirish p_nxge_ldg_t ldgp; 623344961713Sgirish p_nxge_intr_t intrp; 6234e3d11eeeSToomas Soome ddi_intr_handler_t *inthandler; 623544961713Sgirish void *arg1, *arg2; 623644961713Sgirish int behavior; 623744961713Sgirish int nintrs, navail; 623844961713Sgirish int nactual, nrequired; 623944961713Sgirish int inum = 0; 624044961713Sgirish int x, y; 624144961713Sgirish int ddi_status = DDI_SUCCESS; 624244961713Sgirish nxge_status_t status = NXGE_OK; 624344961713Sgirish 624444961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs_adv_type_fix")); 624544961713Sgirish intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 624644961713Sgirish intrp->start_inum = 0; 624744961713Sgirish 624844961713Sgirish ddi_status = ddi_intr_get_nintrs(dip, int_type, &nintrs); 624944961713Sgirish if ((ddi_status != DDI_SUCCESS) || (nintrs == 0)) { 625044961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 62514045d941Ssowmini "ddi_intr_get_nintrs() failed, status: 0x%x%, " 62524045d941Ssowmini "nintrs: %d", status, nintrs)); 625344961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 625444961713Sgirish } 625544961713Sgirish 625644961713Sgirish ddi_status = ddi_intr_get_navail(dip, int_type, &navail); 625744961713Sgirish if ((ddi_status != DDI_SUCCESS) || (navail == 0)) { 625844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 62594045d941Ssowmini "ddi_intr_get_navail() failed, status: 0x%x%, " 62604045d941Ssowmini "nintrs: %d", ddi_status, navail)); 626144961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 626244961713Sgirish } 626344961713Sgirish 626444961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 62654045d941Ssowmini "ddi_intr_get_navail() returned: nintrs %d, naavail %d", 62664045d941Ssowmini nintrs, navail)); 626744961713Sgirish 626844961713Sgirish behavior = ((int_type == DDI_INTR_TYPE_FIXED) ? DDI_INTR_ALLOC_STRICT : 62694045d941Ssowmini DDI_INTR_ALLOC_NORMAL); 627044961713Sgirish intrp->intr_size = navail * sizeof (ddi_intr_handle_t); 627144961713Sgirish intrp->htable = kmem_alloc(intrp->intr_size, KM_SLEEP); 627244961713Sgirish ddi_status = ddi_intr_alloc(dip, intrp->htable, int_type, inum, 62734045d941Ssowmini navail, &nactual, behavior); 627444961713Sgirish if (ddi_status != DDI_SUCCESS || nactual == 0) { 627544961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 62764045d941Ssowmini " ddi_intr_alloc() failed: %d", 62774045d941Ssowmini ddi_status)); 627844961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 627944961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 628044961713Sgirish } 628144961713Sgirish 628244961713Sgirish if ((ddi_status = ddi_intr_get_pri(intrp->htable[0], 62834045d941Ssowmini (uint_t *)&intrp->pri)) != DDI_SUCCESS) { 628444961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 62854045d941Ssowmini " ddi_intr_get_pri() failed: %d", 62864045d941Ssowmini ddi_status)); 628744961713Sgirish /* Free already allocated interrupts */ 628844961713Sgirish for (y = 0; y < nactual; y++) { 628944961713Sgirish (void) ddi_intr_free(intrp->htable[y]); 629044961713Sgirish } 629144961713Sgirish 629244961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 629344961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 629444961713Sgirish } 629544961713Sgirish 629644961713Sgirish nrequired = 0; 629744961713Sgirish switch (nxgep->niu_type) { 629844961713Sgirish default: 629944961713Sgirish status = nxge_ldgv_init(nxgep, &nactual, &nrequired); 630044961713Sgirish break; 630144961713Sgirish 630244961713Sgirish case N2_NIU: 630344961713Sgirish status = nxge_ldgv_init_n2(nxgep, &nactual, &nrequired); 630444961713Sgirish break; 630544961713Sgirish } 630644961713Sgirish 630744961713Sgirish if (status != NXGE_OK) { 630844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 63094045d941Ssowmini "nxge_add_intrs_adv_type_fix:nxge_ldgv_init " 63104045d941Ssowmini "failed: 0x%x", status)); 631144961713Sgirish /* Free already allocated interrupts */ 631244961713Sgirish for (y = 0; y < nactual; y++) { 631344961713Sgirish (void) ddi_intr_free(intrp->htable[y]); 631444961713Sgirish } 631544961713Sgirish 631644961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 631744961713Sgirish return (status); 631844961713Sgirish } 631944961713Sgirish 632044961713Sgirish ldgp = nxgep->ldgvp->ldgp; 632144961713Sgirish for (x = 0; x < nrequired; x++, ldgp++) { 632244961713Sgirish ldgp->vector = (uint8_t)x; 632344961713Sgirish if (nxgep->niu_type != N2_NIU) { 632444961713Sgirish ldgp->intdata = SID_DATA(ldgp->func, x); 632544961713Sgirish } 632644961713Sgirish 632744961713Sgirish arg1 = ldgp->ldvp; 632844961713Sgirish arg2 = nxgep; 632944961713Sgirish if (ldgp->nldvs == 1) { 6330e3d11eeeSToomas Soome inthandler = ldgp->ldvp->ldv_intr_handler; 633144961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 63324045d941Ssowmini "nxge_add_intrs_adv_type_fix: " 63334045d941Ssowmini "1-1 int handler(%d) ldg %d ldv %d " 63344045d941Ssowmini "arg1 $%p arg2 $%p\n", 63354045d941Ssowmini x, ldgp->ldg, ldgp->ldvp->ldv, 63364045d941Ssowmini arg1, arg2)); 633744961713Sgirish } else if (ldgp->nldvs > 1) { 6338e3d11eeeSToomas Soome inthandler = ldgp->sys_intr_handler; 633944961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 63404045d941Ssowmini "nxge_add_intrs_adv_type_fix: " 63414045d941Ssowmini "shared ldv %d int handler(%d) ldv %d ldg %d" 63424045d941Ssowmini "arg1 0x%016llx arg2 0x%016llx\n", 63434045d941Ssowmini x, ldgp->nldvs, ldgp->ldg, ldgp->ldvp->ldv, 63444045d941Ssowmini arg1, arg2)); 6345e3d11eeeSToomas Soome } else { 6346e3d11eeeSToomas Soome inthandler = NULL; 634744961713Sgirish } 634844961713Sgirish 634944961713Sgirish if ((ddi_status = ddi_intr_add_handler(intrp->htable[x], 6350e3d11eeeSToomas Soome inthandler, arg1, arg2)) != DDI_SUCCESS) { 635144961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 63524045d941Ssowmini "==> nxge_add_intrs_adv_type_fix: failed #%d " 63534045d941Ssowmini "status 0x%x", x, ddi_status)); 635444961713Sgirish for (y = 0; y < intrp->intr_added; y++) { 635544961713Sgirish (void) ddi_intr_remove_handler( 63564045d941Ssowmini intrp->htable[y]); 635744961713Sgirish } 635844961713Sgirish for (y = 0; y < nactual; y++) { 635944961713Sgirish (void) ddi_intr_free(intrp->htable[y]); 636044961713Sgirish } 636144961713Sgirish /* Free already allocated intr */ 636244961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 636344961713Sgirish 636444961713Sgirish (void) nxge_ldgv_uninit(nxgep); 636544961713Sgirish 636644961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 636744961713Sgirish } 63680dc2366fSVenugopal Iyer 63690dc2366fSVenugopal Iyer ldgp->htable_idx = x; 637044961713Sgirish intrp->intr_added++; 637144961713Sgirish } 637244961713Sgirish 637344961713Sgirish intrp->msi_intx_cnt = nactual; 637444961713Sgirish 637544961713Sgirish (void) ddi_intr_get_cap(intrp->htable[0], &intrp->intr_cap); 637644961713Sgirish 637744961713Sgirish status = nxge_intr_ldgv_init(nxgep); 637844961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_add_intrs_adv_type_fix")); 637944961713Sgirish 638044961713Sgirish return (status); 638144961713Sgirish } 638244961713Sgirish 638344961713Sgirish static void 638444961713Sgirish nxge_remove_intrs(p_nxge_t nxgep) 638544961713Sgirish { 638644961713Sgirish int i, inum; 638744961713Sgirish p_nxge_intr_t intrp; 638844961713Sgirish 638944961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_remove_intrs")); 639044961713Sgirish intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 639144961713Sgirish if (!intrp->intr_registered) { 639244961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 63934045d941Ssowmini "<== nxge_remove_intrs: interrupts not registered")); 639444961713Sgirish return; 639544961713Sgirish } 639644961713Sgirish 639744961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_remove_intrs:advanced")); 639844961713Sgirish 639944961713Sgirish if (intrp->intr_cap & DDI_INTR_FLAG_BLOCK) { 640044961713Sgirish (void) ddi_intr_block_disable(intrp->htable, 64014045d941Ssowmini intrp->intr_added); 640244961713Sgirish } else { 640344961713Sgirish for (i = 0; i < intrp->intr_added; i++) { 640444961713Sgirish (void) ddi_intr_disable(intrp->htable[i]); 640544961713Sgirish } 640644961713Sgirish } 640744961713Sgirish 640844961713Sgirish for (inum = 0; inum < intrp->intr_added; inum++) { 640944961713Sgirish if (intrp->htable[inum]) { 641044961713Sgirish (void) ddi_intr_remove_handler(intrp->htable[inum]); 641144961713Sgirish } 641244961713Sgirish } 641344961713Sgirish 641444961713Sgirish for (inum = 0; inum < intrp->msi_intx_cnt; inum++) { 641544961713Sgirish if (intrp->htable[inum]) { 641644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 64174045d941Ssowmini "nxge_remove_intrs: ddi_intr_free inum %d " 64184045d941Ssowmini "msi_intx_cnt %d intr_added %d", 64194045d941Ssowmini inum, 64204045d941Ssowmini intrp->msi_intx_cnt, 64214045d941Ssowmini intrp->intr_added)); 642244961713Sgirish 642344961713Sgirish (void) ddi_intr_free(intrp->htable[inum]); 642444961713Sgirish } 642544961713Sgirish } 642644961713Sgirish 642744961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 642844961713Sgirish intrp->intr_registered = B_FALSE; 642944961713Sgirish intrp->intr_enabled = B_FALSE; 643044961713Sgirish intrp->msi_intx_cnt = 0; 643144961713Sgirish intrp->intr_added = 0; 643244961713Sgirish 6433a3c5bd6dSspeer (void) nxge_ldgv_uninit(nxgep); 6434a3c5bd6dSspeer 6435ec090658Sml (void) ddi_prop_remove(DDI_DEV_T_NONE, nxgep->dip, 6436ec090658Sml "#msix-request"); 6437ec090658Sml 643844961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_remove_intrs")); 643944961713Sgirish } 644044961713Sgirish 644144961713Sgirish /*ARGSUSED*/ 644244961713Sgirish static void 644344961713Sgirish nxge_intrs_enable(p_nxge_t nxgep) 644444961713Sgirish { 644544961713Sgirish p_nxge_intr_t intrp; 644644961713Sgirish int i; 644744961713Sgirish int status; 644844961713Sgirish 644944961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_enable")); 645044961713Sgirish 645144961713Sgirish intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 645244961713Sgirish 645344961713Sgirish if (!intrp->intr_registered) { 645444961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_intrs_enable: " 64554045d941Ssowmini "interrupts are not registered")); 645644961713Sgirish return; 645744961713Sgirish } 645844961713Sgirish 645944961713Sgirish if (intrp->intr_enabled) { 646044961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 64614045d941Ssowmini "<== nxge_intrs_enable: already enabled")); 646244961713Sgirish return; 646344961713Sgirish } 646444961713Sgirish 646544961713Sgirish if (intrp->intr_cap & DDI_INTR_FLAG_BLOCK) { 646644961713Sgirish status = ddi_intr_block_enable(intrp->htable, 64674045d941Ssowmini intrp->intr_added); 646844961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_enable " 64694045d941Ssowmini "block enable - status 0x%x total inums #%d\n", 64704045d941Ssowmini status, intrp->intr_added)); 647144961713Sgirish } else { 647244961713Sgirish for (i = 0; i < intrp->intr_added; i++) { 647344961713Sgirish status = ddi_intr_enable(intrp->htable[i]); 647444961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_enable " 64754045d941Ssowmini "ddi_intr_enable:enable - status 0x%x " 64764045d941Ssowmini "total inums %d enable inum #%d\n", 64774045d941Ssowmini status, intrp->intr_added, i)); 647844961713Sgirish if (status == DDI_SUCCESS) { 647944961713Sgirish intrp->intr_enabled = B_TRUE; 648044961713Sgirish } 648144961713Sgirish } 648244961713Sgirish } 648344961713Sgirish 648444961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intrs_enable")); 648544961713Sgirish } 648644961713Sgirish 648744961713Sgirish /*ARGSUSED*/ 648844961713Sgirish static void 648944961713Sgirish nxge_intrs_disable(p_nxge_t nxgep) 649044961713Sgirish { 649144961713Sgirish p_nxge_intr_t intrp; 649244961713Sgirish int i; 649344961713Sgirish 649444961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_disable")); 649544961713Sgirish 649644961713Sgirish intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 649744961713Sgirish 649844961713Sgirish if (!intrp->intr_registered) { 649944961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intrs_disable: " 65004045d941Ssowmini "interrupts are not registered")); 650144961713Sgirish return; 650244961713Sgirish } 650344961713Sgirish 650444961713Sgirish if (intrp->intr_cap & DDI_INTR_FLAG_BLOCK) { 650544961713Sgirish (void) ddi_intr_block_disable(intrp->htable, 65064045d941Ssowmini intrp->intr_added); 650744961713Sgirish } else { 650844961713Sgirish for (i = 0; i < intrp->intr_added; i++) { 650944961713Sgirish (void) ddi_intr_disable(intrp->htable[i]); 651044961713Sgirish } 651144961713Sgirish } 651244961713Sgirish 651344961713Sgirish intrp->intr_enabled = B_FALSE; 651444961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intrs_disable")); 651544961713Sgirish } 651644961713Sgirish 651763f531d1SSriharsha Basavapatna nxge_status_t 651844961713Sgirish nxge_mac_register(p_nxge_t nxgep) 651944961713Sgirish { 652044961713Sgirish mac_register_t *macp; 652144961713Sgirish int status; 652244961713Sgirish 652344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_mac_register")); 652444961713Sgirish 652544961713Sgirish if ((macp = mac_alloc(MAC_VERSION)) == NULL) 652644961713Sgirish return (NXGE_ERROR); 652744961713Sgirish 652844961713Sgirish macp->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 652944961713Sgirish macp->m_driver = nxgep; 653044961713Sgirish macp->m_dip = nxgep->dip; 653163f531d1SSriharsha Basavapatna if (!isLDOMguest(nxgep)) { 653263f531d1SSriharsha Basavapatna macp->m_src_addr = nxgep->ouraddr.ether_addr_octet; 653363f531d1SSriharsha Basavapatna } else { 653463f531d1SSriharsha Basavapatna macp->m_src_addr = KMEM_ZALLOC(MAXMACADDRLEN, KM_SLEEP); 653563f531d1SSriharsha Basavapatna macp->m_dst_addr = KMEM_ZALLOC(MAXMACADDRLEN, KM_SLEEP); 653663f531d1SSriharsha Basavapatna (void) memset(macp->m_src_addr, 0xff, sizeof (MAXMACADDRLEN)); 653763f531d1SSriharsha Basavapatna } 653844961713Sgirish macp->m_callbacks = &nxge_m_callbacks; 653944961713Sgirish macp->m_min_sdu = 0; 65401bd6825cSml nxgep->mac.default_mtu = nxgep->mac.maxframesize - 65411bd6825cSml NXGE_EHEADER_VLAN_CRC; 65421bd6825cSml macp->m_max_sdu = nxgep->mac.default_mtu; 6543d62bc4baSyz macp->m_margin = VLAN_TAGSZ; 65444045d941Ssowmini macp->m_priv_props = nxge_priv_props; 65450dc2366fSVenugopal Iyer if (isLDOMguest(nxgep)) 65460dc2366fSVenugopal Iyer macp->m_v12n = MAC_VIRT_LEVEL1; 65470dc2366fSVenugopal Iyer else 65480dc2366fSVenugopal Iyer macp->m_v12n = MAC_VIRT_HIO | MAC_VIRT_LEVEL1; 654944961713Sgirish 65501bd6825cSml NXGE_DEBUG_MSG((nxgep, MAC_CTL, 65511bd6825cSml "==> nxge_mac_register: instance %d " 65521bd6825cSml "max_sdu %d margin %d maxframe %d (header %d)", 65531bd6825cSml nxgep->instance, 65541bd6825cSml macp->m_max_sdu, macp->m_margin, 65551bd6825cSml nxgep->mac.maxframesize, 65561bd6825cSml NXGE_EHEADER_VLAN_CRC)); 65571bd6825cSml 655844961713Sgirish status = mac_register(macp, &nxgep->mach); 655963f531d1SSriharsha Basavapatna if (isLDOMguest(nxgep)) { 656063f531d1SSriharsha Basavapatna KMEM_FREE(macp->m_src_addr, MAXMACADDRLEN); 656163f531d1SSriharsha Basavapatna KMEM_FREE(macp->m_dst_addr, MAXMACADDRLEN); 656263f531d1SSriharsha Basavapatna } 656344961713Sgirish mac_free(macp); 656444961713Sgirish 656544961713Sgirish if (status != 0) { 656644961713Sgirish cmn_err(CE_WARN, 65674045d941Ssowmini "!nxge_mac_register failed (status %d instance %d)", 65684045d941Ssowmini status, nxgep->instance); 656944961713Sgirish return (NXGE_ERROR); 657044961713Sgirish } 657144961713Sgirish 657244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_mac_register success " 65734045d941Ssowmini "(instance %d)", nxgep->instance)); 657444961713Sgirish 657544961713Sgirish return (NXGE_OK); 657644961713Sgirish } 657744961713Sgirish 657844961713Sgirish void 657944961713Sgirish nxge_err_inject(p_nxge_t nxgep, queue_t *wq, mblk_t *mp) 658044961713Sgirish { 658144961713Sgirish ssize_t size; 658244961713Sgirish mblk_t *nmp; 658344961713Sgirish uint8_t blk_id; 658444961713Sgirish uint8_t chan; 658544961713Sgirish uint32_t err_id; 658644961713Sgirish err_inject_t *eip; 658744961713Sgirish 658844961713Sgirish NXGE_DEBUG_MSG((nxgep, STR_CTL, "==> nxge_err_inject")); 658944961713Sgirish 659044961713Sgirish size = 1024; 659144961713Sgirish nmp = mp->b_cont; 659244961713Sgirish eip = (err_inject_t *)nmp->b_rptr; 659344961713Sgirish blk_id = eip->blk_id; 659444961713Sgirish err_id = eip->err_id; 659544961713Sgirish chan = eip->chan; 659644961713Sgirish cmn_err(CE_NOTE, "!blk_id = 0x%x\n", blk_id); 659744961713Sgirish cmn_err(CE_NOTE, "!err_id = 0x%x\n", err_id); 659844961713Sgirish cmn_err(CE_NOTE, "!chan = 0x%x\n", chan); 659944961713Sgirish switch (blk_id) { 660044961713Sgirish case MAC_BLK_ID: 660144961713Sgirish break; 660244961713Sgirish case TXMAC_BLK_ID: 660344961713Sgirish break; 660444961713Sgirish case RXMAC_BLK_ID: 660544961713Sgirish break; 660644961713Sgirish case MIF_BLK_ID: 660744961713Sgirish break; 660844961713Sgirish case IPP_BLK_ID: 660944961713Sgirish nxge_ipp_inject_err(nxgep, err_id); 661044961713Sgirish break; 661144961713Sgirish case TXC_BLK_ID: 661244961713Sgirish nxge_txc_inject_err(nxgep, err_id); 661344961713Sgirish break; 661444961713Sgirish case TXDMA_BLK_ID: 661544961713Sgirish nxge_txdma_inject_err(nxgep, err_id, chan); 661644961713Sgirish break; 661744961713Sgirish case RXDMA_BLK_ID: 661844961713Sgirish nxge_rxdma_inject_err(nxgep, err_id, chan); 661944961713Sgirish break; 662044961713Sgirish case ZCP_BLK_ID: 662144961713Sgirish nxge_zcp_inject_err(nxgep, err_id); 662244961713Sgirish break; 662344961713Sgirish case ESPC_BLK_ID: 662444961713Sgirish break; 662544961713Sgirish case FFLP_BLK_ID: 662644961713Sgirish break; 662744961713Sgirish case PHY_BLK_ID: 662844961713Sgirish break; 662944961713Sgirish case ETHER_SERDES_BLK_ID: 663044961713Sgirish break; 663144961713Sgirish case PCIE_SERDES_BLK_ID: 663244961713Sgirish break; 663344961713Sgirish case VIR_BLK_ID: 663444961713Sgirish break; 663544961713Sgirish } 663644961713Sgirish 663744961713Sgirish nmp->b_wptr = nmp->b_rptr + size; 663844961713Sgirish NXGE_DEBUG_MSG((nxgep, STR_CTL, "<== nxge_err_inject")); 663944961713Sgirish 664044961713Sgirish miocack(wq, mp, (int)size, 0); 664144961713Sgirish } 664244961713Sgirish 664344961713Sgirish static int 664444961713Sgirish nxge_init_common_dev(p_nxge_t nxgep) 664544961713Sgirish { 664644961713Sgirish p_nxge_hw_list_t hw_p; 6647*86ef0a63SRichard Lowe dev_info_t *p_dip; 664844961713Sgirish 6649ef523517SMichael Speer ASSERT(nxgep != NULL); 6650ef523517SMichael Speer 665144961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, "==> nxge_init_common_device")); 665244961713Sgirish 665344961713Sgirish p_dip = nxgep->p_dip; 665444961713Sgirish MUTEX_ENTER(&nxge_common_lock); 665544961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 66564045d941Ssowmini "==> nxge_init_common_dev:func # %d", 66574045d941Ssowmini nxgep->function_num)); 665844961713Sgirish /* 665944961713Sgirish * Loop through existing per neptune hardware list. 666044961713Sgirish */ 666144961713Sgirish for (hw_p = nxge_hw_list; hw_p; hw_p = hw_p->next) { 666244961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 66634045d941Ssowmini "==> nxge_init_common_device:func # %d " 66644045d941Ssowmini "hw_p $%p parent dip $%p", 66654045d941Ssowmini nxgep->function_num, 66664045d941Ssowmini hw_p, 66674045d941Ssowmini p_dip)); 666844961713Sgirish if (hw_p->parent_devp == p_dip) { 666944961713Sgirish nxgep->nxge_hw_p = hw_p; 667044961713Sgirish hw_p->ndevs++; 667144961713Sgirish hw_p->nxge_p[nxgep->function_num] = nxgep; 667244961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 66734045d941Ssowmini "==> nxge_init_common_device:func # %d " 66744045d941Ssowmini "hw_p $%p parent dip $%p " 66754045d941Ssowmini "ndevs %d (found)", 66764045d941Ssowmini nxgep->function_num, 66774045d941Ssowmini hw_p, 66784045d941Ssowmini p_dip, 66794045d941Ssowmini hw_p->ndevs)); 668044961713Sgirish break; 668144961713Sgirish } 668244961713Sgirish } 668344961713Sgirish 668444961713Sgirish if (hw_p == NULL) { 668523b952a3SSantwona Behera 668623b952a3SSantwona Behera char **prop_val; 668723b952a3SSantwona Behera uint_t prop_len; 668823b952a3SSantwona Behera int i; 668923b952a3SSantwona Behera 669044961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 66914045d941Ssowmini "==> nxge_init_common_device:func # %d " 66924045d941Ssowmini "parent dip $%p (new)", 66934045d941Ssowmini nxgep->function_num, 66944045d941Ssowmini p_dip)); 669544961713Sgirish hw_p = kmem_zalloc(sizeof (nxge_hw_list_t), KM_SLEEP); 669644961713Sgirish hw_p->parent_devp = p_dip; 669744961713Sgirish hw_p->magic = NXGE_NEPTUNE_MAGIC; 669844961713Sgirish nxgep->nxge_hw_p = hw_p; 669944961713Sgirish hw_p->ndevs++; 670044961713Sgirish hw_p->nxge_p[nxgep->function_num] = nxgep; 670144961713Sgirish hw_p->next = nxge_hw_list; 670259ac0c16Sdavemq if (nxgep->niu_type == N2_NIU) { 670359ac0c16Sdavemq hw_p->niu_type = N2_NIU; 670459ac0c16Sdavemq hw_p->platform_type = P_NEPTUNE_NIU; 67054df55fdeSJanie Lu hw_p->tcam_size = TCAM_NIU_TCAM_MAX_ENTRY; 670659ac0c16Sdavemq } else { 670759ac0c16Sdavemq hw_p->niu_type = NIU_TYPE_NONE; 67082e59129aSraghus hw_p->platform_type = P_NEPTUNE_NONE; 67094df55fdeSJanie Lu hw_p->tcam_size = TCAM_NXGE_TCAM_MAX_ENTRY; 671059ac0c16Sdavemq } 671144961713Sgirish 67124df55fdeSJanie Lu hw_p->tcam = KMEM_ZALLOC(sizeof (tcam_flow_spec_t) * 67134df55fdeSJanie Lu hw_p->tcam_size, KM_SLEEP); 67144df55fdeSJanie Lu 671544961713Sgirish MUTEX_INIT(&hw_p->nxge_cfg_lock, NULL, MUTEX_DRIVER, NULL); 671644961713Sgirish MUTEX_INIT(&hw_p->nxge_tcam_lock, NULL, MUTEX_DRIVER, NULL); 671744961713Sgirish MUTEX_INIT(&hw_p->nxge_vlan_lock, NULL, MUTEX_DRIVER, NULL); 671844961713Sgirish MUTEX_INIT(&hw_p->nxge_mdio_lock, NULL, MUTEX_DRIVER, NULL); 671944961713Sgirish 672044961713Sgirish nxge_hw_list = hw_p; 672159ac0c16Sdavemq 672223b952a3SSantwona Behera if (ddi_prop_lookup_string_array(DDI_DEV_T_ANY, nxgep->dip, 0, 672323b952a3SSantwona Behera "compatible", &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 672423b952a3SSantwona Behera for (i = 0; i < prop_len; i++) { 672523b952a3SSantwona Behera if ((strcmp((caddr_t)prop_val[i], 672623b952a3SSantwona Behera NXGE_ROCK_COMPATIBLE) == 0)) { 672723b952a3SSantwona Behera hw_p->platform_type = P_NEPTUNE_ROCK; 672823b952a3SSantwona Behera NXGE_DEBUG_MSG((nxgep, MOD_CTL, 672923b952a3SSantwona Behera "ROCK hw_p->platform_type %d", 673023b952a3SSantwona Behera hw_p->platform_type)); 673123b952a3SSantwona Behera break; 673223b952a3SSantwona Behera } 673323b952a3SSantwona Behera NXGE_DEBUG_MSG((nxgep, MOD_CTL, 673423b952a3SSantwona Behera "nxge_init_common_dev: read compatible" 673523b952a3SSantwona Behera " property[%d] val[%s]", 673623b952a3SSantwona Behera i, (caddr_t)prop_val[i])); 673723b952a3SSantwona Behera } 673823b952a3SSantwona Behera } 673923b952a3SSantwona Behera 674023b952a3SSantwona Behera ddi_prop_free(prop_val); 674123b952a3SSantwona Behera 674259ac0c16Sdavemq (void) nxge_scan_ports_phy(nxgep, nxge_hw_list); 674344961713Sgirish } 674444961713Sgirish 674544961713Sgirish MUTEX_EXIT(&nxge_common_lock); 674659ac0c16Sdavemq 67472e59129aSraghus nxgep->platform_type = hw_p->platform_type; 674823b952a3SSantwona Behera NXGE_DEBUG_MSG((nxgep, MOD_CTL, "nxgep->platform_type %d", 674923b952a3SSantwona Behera nxgep->platform_type)); 675059ac0c16Sdavemq if (nxgep->niu_type != N2_NIU) { 675159ac0c16Sdavemq nxgep->niu_type = hw_p->niu_type; 675259ac0c16Sdavemq } 675359ac0c16Sdavemq 675444961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 67554045d941Ssowmini "==> nxge_init_common_device (nxge_hw_list) $%p", 67564045d941Ssowmini nxge_hw_list)); 675744961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, "<== nxge_init_common_device")); 675844961713Sgirish 675944961713Sgirish return (NXGE_OK); 676044961713Sgirish } 676144961713Sgirish 676244961713Sgirish static void 676344961713Sgirish nxge_uninit_common_dev(p_nxge_t nxgep) 676444961713Sgirish { 676544961713Sgirish p_nxge_hw_list_t hw_p, h_hw_p; 67660b0beae0Sspeer p_nxge_dma_pt_cfg_t p_dma_cfgp; 67670b0beae0Sspeer p_nxge_hw_pt_cfg_t p_cfgp; 6768*86ef0a63SRichard Lowe dev_info_t *p_dip; 676944961713Sgirish 6770ef523517SMichael Speer ASSERT(nxgep != NULL); 6771ef523517SMichael Speer 677244961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, "==> nxge_uninit_common_device")); 677344961713Sgirish if (nxgep->nxge_hw_p == NULL) { 677444961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 67754045d941Ssowmini "<== nxge_uninit_common_device (no common)")); 677644961713Sgirish return; 677744961713Sgirish } 677844961713Sgirish 677944961713Sgirish MUTEX_ENTER(&nxge_common_lock); 678044961713Sgirish h_hw_p = nxge_hw_list; 678144961713Sgirish for (hw_p = nxge_hw_list; hw_p; hw_p = hw_p->next) { 678244961713Sgirish p_dip = hw_p->parent_devp; 678344961713Sgirish if (nxgep->nxge_hw_p == hw_p && 67844045d941Ssowmini p_dip == nxgep->p_dip && 67854045d941Ssowmini nxgep->nxge_hw_p->magic == NXGE_NEPTUNE_MAGIC && 67864045d941Ssowmini hw_p->magic == NXGE_NEPTUNE_MAGIC) { 678744961713Sgirish 678844961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 67894045d941Ssowmini "==> nxge_uninit_common_device:func # %d " 67904045d941Ssowmini "hw_p $%p parent dip $%p " 67914045d941Ssowmini "ndevs %d (found)", 67924045d941Ssowmini nxgep->function_num, 67934045d941Ssowmini hw_p, 67944045d941Ssowmini p_dip, 67954045d941Ssowmini hw_p->ndevs)); 679644961713Sgirish 67970b0beae0Sspeer /* 67980b0beae0Sspeer * Release the RDC table, a shared resoruce 67990b0beae0Sspeer * of the nxge hardware. The RDC table was 68000b0beae0Sspeer * assigned to this instance of nxge in 68010b0beae0Sspeer * nxge_use_cfg_dma_config(). 68020b0beae0Sspeer */ 68039d5b8bc5SMichael Speer if (!isLDOMguest(nxgep)) { 68049d5b8bc5SMichael Speer p_dma_cfgp = 68059d5b8bc5SMichael Speer (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 68069d5b8bc5SMichael Speer p_cfgp = 68079d5b8bc5SMichael Speer (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 68089d5b8bc5SMichael Speer (void) nxge_fzc_rdc_tbl_unbind(nxgep, 68099d5b8bc5SMichael Speer p_cfgp->def_mac_rxdma_grpid); 6810651ce697SMichael Speer 6811651ce697SMichael Speer /* Cleanup any outstanding groups. */ 6812651ce697SMichael Speer nxge_grp_cleanup(nxgep); 68139d5b8bc5SMichael Speer } 68140b0beae0Sspeer 681544961713Sgirish if (hw_p->ndevs) { 681644961713Sgirish hw_p->ndevs--; 681744961713Sgirish } 681844961713Sgirish hw_p->nxge_p[nxgep->function_num] = NULL; 681944961713Sgirish if (!hw_p->ndevs) { 68204df55fdeSJanie Lu KMEM_FREE(hw_p->tcam, 68214df55fdeSJanie Lu sizeof (tcam_flow_spec_t) * 68224df55fdeSJanie Lu hw_p->tcam_size); 682344961713Sgirish MUTEX_DESTROY(&hw_p->nxge_vlan_lock); 682444961713Sgirish MUTEX_DESTROY(&hw_p->nxge_tcam_lock); 682544961713Sgirish MUTEX_DESTROY(&hw_p->nxge_cfg_lock); 682644961713Sgirish MUTEX_DESTROY(&hw_p->nxge_mdio_lock); 682744961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 68284045d941Ssowmini "==> nxge_uninit_common_device: " 68294045d941Ssowmini "func # %d " 68304045d941Ssowmini "hw_p $%p parent dip $%p " 68314045d941Ssowmini "ndevs %d (last)", 68324045d941Ssowmini nxgep->function_num, 68334045d941Ssowmini hw_p, 68344045d941Ssowmini p_dip, 68354045d941Ssowmini hw_p->ndevs)); 683644961713Sgirish 6837678453a8Sspeer nxge_hio_uninit(nxgep); 6838678453a8Sspeer 683944961713Sgirish if (hw_p == nxge_hw_list) { 684044961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 68414045d941Ssowmini "==> nxge_uninit_common_device:" 68424045d941Ssowmini "remove head func # %d " 68434045d941Ssowmini "hw_p $%p parent dip $%p " 68444045d941Ssowmini "ndevs %d (head)", 68454045d941Ssowmini nxgep->function_num, 68464045d941Ssowmini hw_p, 68474045d941Ssowmini p_dip, 68484045d941Ssowmini hw_p->ndevs)); 684944961713Sgirish nxge_hw_list = hw_p->next; 685044961713Sgirish } else { 685144961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 68524045d941Ssowmini "==> nxge_uninit_common_device:" 68534045d941Ssowmini "remove middle func # %d " 68544045d941Ssowmini "hw_p $%p parent dip $%p " 68554045d941Ssowmini "ndevs %d (middle)", 68564045d941Ssowmini nxgep->function_num, 68574045d941Ssowmini hw_p, 68584045d941Ssowmini p_dip, 68594045d941Ssowmini hw_p->ndevs)); 686044961713Sgirish h_hw_p->next = hw_p->next; 686144961713Sgirish } 686244961713Sgirish 6863678453a8Sspeer nxgep->nxge_hw_p = NULL; 686444961713Sgirish KMEM_FREE(hw_p, sizeof (nxge_hw_list_t)); 686544961713Sgirish } 686644961713Sgirish break; 686744961713Sgirish } else { 686844961713Sgirish h_hw_p = hw_p; 686944961713Sgirish } 687044961713Sgirish } 687144961713Sgirish 687244961713Sgirish MUTEX_EXIT(&nxge_common_lock); 687344961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 68744045d941Ssowmini "==> nxge_uninit_common_device (nxge_hw_list) $%p", 68754045d941Ssowmini nxge_hw_list)); 687644961713Sgirish 687744961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, "<= nxge_uninit_common_device")); 687844961713Sgirish } 687959ac0c16Sdavemq 688059ac0c16Sdavemq /* 68812e59129aSraghus * Determines the number of ports from the niu_type or the platform type. 688259ac0c16Sdavemq * Returns the number of ports, or returns zero on failure. 688359ac0c16Sdavemq */ 688459ac0c16Sdavemq 688559ac0c16Sdavemq int 68862e59129aSraghus nxge_get_nports(p_nxge_t nxgep) 688759ac0c16Sdavemq { 688859ac0c16Sdavemq int nports = 0; 688959ac0c16Sdavemq 68902e59129aSraghus switch (nxgep->niu_type) { 689159ac0c16Sdavemq case N2_NIU: 689259ac0c16Sdavemq case NEPTUNE_2_10GF: 689359ac0c16Sdavemq nports = 2; 689459ac0c16Sdavemq break; 689559ac0c16Sdavemq case NEPTUNE_4_1GC: 689659ac0c16Sdavemq case NEPTUNE_2_10GF_2_1GC: 689759ac0c16Sdavemq case NEPTUNE_1_10GF_3_1GC: 689859ac0c16Sdavemq case NEPTUNE_1_1GC_1_10GF_2_1GC: 689959a835ddSjoycey case NEPTUNE_2_10GF_2_1GRF: 690059ac0c16Sdavemq nports = 4; 690159ac0c16Sdavemq break; 690259ac0c16Sdavemq default: 69032e59129aSraghus switch (nxgep->platform_type) { 69042e59129aSraghus case P_NEPTUNE_NIU: 69052e59129aSraghus case P_NEPTUNE_ATLAS_2PORT: 69062e59129aSraghus nports = 2; 69072e59129aSraghus break; 69082e59129aSraghus case P_NEPTUNE_ATLAS_4PORT: 69092e59129aSraghus case P_NEPTUNE_MARAMBA_P0: 69102e59129aSraghus case P_NEPTUNE_MARAMBA_P1: 691123b952a3SSantwona Behera case P_NEPTUNE_ROCK: 6912d81011f0Ssbehera case P_NEPTUNE_ALONSO: 69132e59129aSraghus nports = 4; 69142e59129aSraghus break; 69152e59129aSraghus default: 69162e59129aSraghus break; 69172e59129aSraghus } 691859ac0c16Sdavemq break; 691959ac0c16Sdavemq } 692059ac0c16Sdavemq 692159ac0c16Sdavemq return (nports); 692259ac0c16Sdavemq } 6923ec090658Sml 6924ec090658Sml /* 6925ec090658Sml * The following two functions are to support 6926ec090658Sml * PSARC/2007/453 MSI-X interrupt limit override. 6927ec090658Sml */ 6928ec090658Sml static int 6929ec090658Sml nxge_create_msi_property(p_nxge_t nxgep) 6930ec090658Sml { 6931ec090658Sml int nmsi; 6932ec090658Sml extern int ncpus; 6933ec090658Sml 6934ec090658Sml NXGE_DEBUG_MSG((nxgep, MOD_CTL, "==>nxge_create_msi_property")); 6935ec090658Sml 6936ec090658Sml switch (nxgep->mac.portmode) { 6937ec090658Sml case PORT_10G_COPPER: 6938ec090658Sml case PORT_10G_FIBER: 693900161856Syc case PORT_10G_TN1010: 6940ec090658Sml (void) ddi_prop_create(DDI_DEV_T_NONE, nxgep->dip, 6941ec090658Sml DDI_PROP_CANSLEEP, "#msix-request", NULL, 0); 6942ec090658Sml /* 6943ec090658Sml * The maximum MSI-X requested will be 8. 6944ef755e7aStc * If the # of CPUs is less than 8, we will request 6945ef755e7aStc * # MSI-X based on the # of CPUs (default). 6946ec090658Sml */ 6947ef755e7aStc NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6948ef755e7aStc "==>nxge_create_msi_property (10G): nxge_msix_10g_intrs %d", 6949ef755e7aStc nxge_msix_10g_intrs)); 6950ef755e7aStc if ((nxge_msix_10g_intrs == 0) || 6951ef755e7aStc (nxge_msix_10g_intrs > NXGE_MSIX_MAX_ALLOWED)) { 6952ec090658Sml nmsi = NXGE_MSIX_REQUEST_10G; 6953ef755e7aStc NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6954ef755e7aStc "==>nxge_create_msi_property (10G): reset to 8")); 6955ec090658Sml } else { 6956ef755e7aStc nmsi = nxge_msix_10g_intrs; 6957ef755e7aStc } 6958ef755e7aStc 6959ef755e7aStc /* 6960ef755e7aStc * If # of interrupts requested is 8 (default), 6961ef755e7aStc * the checking of the number of cpus will be 6962ef755e7aStc * be maintained. 6963ef755e7aStc */ 6964ef755e7aStc if ((nmsi == NXGE_MSIX_REQUEST_10G) && 6965ef755e7aStc (ncpus < nmsi)) { 6966ef755e7aStc NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6967ef755e7aStc "==>nxge_create_msi_property (10G): reset to 8")); 6968ec090658Sml nmsi = ncpus; 6969ec090658Sml } 6970ec090658Sml NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6971ec090658Sml "==>nxge_create_msi_property(10G): exists 0x%x (nmsi %d)", 6972ec090658Sml ddi_prop_exists(DDI_DEV_T_NONE, nxgep->dip, 6973ec090658Sml DDI_PROP_CANSLEEP, "#msix-request"), nmsi)); 6974ec090658Sml break; 6975ec090658Sml 6976ec090658Sml default: 6977ef755e7aStc (void) ddi_prop_create(DDI_DEV_T_NONE, nxgep->dip, 6978ef755e7aStc DDI_PROP_CANSLEEP, "#msix-request", NULL, 0); 6979ef755e7aStc NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6980ef755e7aStc "==>nxge_create_msi_property (1G): nxge_msix_1g_intrs %d", 6981ef755e7aStc nxge_msix_1g_intrs)); 6982ef755e7aStc if ((nxge_msix_1g_intrs == 0) || 6983ef755e7aStc (nxge_msix_1g_intrs > NXGE_MSIX_MAX_ALLOWED)) { 6984ef755e7aStc nmsi = NXGE_MSIX_REQUEST_1G; 6985ef755e7aStc NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6986ef755e7aStc "==>nxge_create_msi_property (1G): reset to 2")); 6987ef755e7aStc } else { 6988ef755e7aStc nmsi = nxge_msix_1g_intrs; 6989ef755e7aStc } 6990ec090658Sml NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6991ec090658Sml "==>nxge_create_msi_property(1G): exists 0x%x (nmsi %d)", 6992ec090658Sml ddi_prop_exists(DDI_DEV_T_NONE, nxgep->dip, 6993ec090658Sml DDI_PROP_CANSLEEP, "#msix-request"), nmsi)); 6994ec090658Sml break; 6995ec090658Sml } 6996ec090658Sml 6997ec090658Sml NXGE_DEBUG_MSG((nxgep, MOD_CTL, "<==nxge_create_msi_property")); 6998ec090658Sml return (nmsi); 6999ec090658Sml } 70004045d941Ssowmini 70016f157acbSml /* 70026f157acbSml * The following is a software around for the Neptune hardware's 70036f157acbSml * interrupt bugs; The Neptune hardware may generate spurious interrupts when 70046f157acbSml * an interrupr handler is removed. 70056f157acbSml */ 70066f157acbSml #define NXGE_PCI_PORT_LOGIC_OFFSET 0x98 70076f157acbSml #define NXGE_PIM_RESET (1ULL << 29) 70086f157acbSml #define NXGE_GLU_RESET (1ULL << 30) 70096f157acbSml #define NXGE_NIU_RESET (1ULL << 31) 70106f157acbSml #define NXGE_PCI_RESET_ALL (NXGE_PIM_RESET | \ 70116f157acbSml NXGE_GLU_RESET | \ 70126f157acbSml NXGE_NIU_RESET) 70136f157acbSml 70146f157acbSml #define NXGE_WAIT_QUITE_TIME 200000 70156f157acbSml #define NXGE_WAIT_QUITE_RETRY 40 70166f157acbSml #define NXGE_PCI_RESET_WAIT 1000000 /* one second */ 70176f157acbSml 70186f157acbSml static void 70196f157acbSml nxge_niu_peu_reset(p_nxge_t nxgep) 70206f157acbSml { 70216f157acbSml uint32_t rvalue; 70226f157acbSml p_nxge_hw_list_t hw_p; 70236f157acbSml p_nxge_t fnxgep; 70246f157acbSml int i, j; 70256f157acbSml 70266f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, "==> nxge_niu_peu_reset")); 70276f157acbSml if ((hw_p = nxgep->nxge_hw_p) == NULL) { 70286f157acbSml NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 70296f157acbSml "==> nxge_niu_peu_reset: NULL hardware pointer")); 70306f157acbSml return; 70316f157acbSml } 70326f157acbSml 70336f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 70346f157acbSml "==> nxge_niu_peu_reset: flags 0x%x link timer id %d timer id %d", 70356f157acbSml hw_p->flags, nxgep->nxge_link_poll_timerid, 70366f157acbSml nxgep->nxge_timerid)); 70376f157acbSml 70386f157acbSml MUTEX_ENTER(&hw_p->nxge_cfg_lock); 70396f157acbSml /* 70406f157acbSml * Make sure other instances from the same hardware 70416f157acbSml * stop sending PIO and in quiescent state. 70426f157acbSml */ 70436f157acbSml for (i = 0; i < NXGE_MAX_PORTS; i++) { 70446f157acbSml fnxgep = hw_p->nxge_p[i]; 70456f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 70466f157acbSml "==> nxge_niu_peu_reset: checking entry %d " 70476f157acbSml "nxgep $%p", i, fnxgep)); 70486f157acbSml #ifdef NXGE_DEBUG 70496f157acbSml if (fnxgep) { 70506f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 70516f157acbSml "==> nxge_niu_peu_reset: entry %d (function %d) " 70526f157acbSml "link timer id %d hw timer id %d", 70536f157acbSml i, fnxgep->function_num, 70546f157acbSml fnxgep->nxge_link_poll_timerid, 70556f157acbSml fnxgep->nxge_timerid)); 70566f157acbSml } 70576f157acbSml #endif 70586f157acbSml if (fnxgep && fnxgep != nxgep && 70596f157acbSml (fnxgep->nxge_timerid || fnxgep->nxge_link_poll_timerid)) { 70606f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 70616f157acbSml "==> nxge_niu_peu_reset: checking $%p " 70626f157acbSml "(function %d) timer ids", 70636f157acbSml fnxgep, fnxgep->function_num)); 70646f157acbSml for (j = 0; j < NXGE_WAIT_QUITE_RETRY; j++) { 70656f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 70666f157acbSml "==> nxge_niu_peu_reset: waiting")); 70676f157acbSml NXGE_DELAY(NXGE_WAIT_QUITE_TIME); 70686f157acbSml if (!fnxgep->nxge_timerid && 70696f157acbSml !fnxgep->nxge_link_poll_timerid) { 70706f157acbSml break; 70716f157acbSml } 70726f157acbSml } 70736f157acbSml NXGE_DELAY(NXGE_WAIT_QUITE_TIME); 70746f157acbSml if (fnxgep->nxge_timerid || 70756f157acbSml fnxgep->nxge_link_poll_timerid) { 70766f157acbSml MUTEX_EXIT(&hw_p->nxge_cfg_lock); 70776f157acbSml NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 70786f157acbSml "<== nxge_niu_peu_reset: cannot reset " 70796f157acbSml "hardware (devices are still in use)")); 70806f157acbSml return; 70816f157acbSml } 70826f157acbSml } 70836f157acbSml } 70846f157acbSml 70856f157acbSml if ((hw_p->flags & COMMON_RESET_NIU_PCI) != COMMON_RESET_NIU_PCI) { 70866f157acbSml hw_p->flags |= COMMON_RESET_NIU_PCI; 70876f157acbSml rvalue = pci_config_get32(nxgep->dev_regs->nxge_pciregh, 70886f157acbSml NXGE_PCI_PORT_LOGIC_OFFSET); 70896f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 70906f157acbSml "nxge_niu_peu_reset: read offset 0x%x (%d) " 70916f157acbSml "(data 0x%x)", 70926f157acbSml NXGE_PCI_PORT_LOGIC_OFFSET, 70936f157acbSml NXGE_PCI_PORT_LOGIC_OFFSET, 70946f157acbSml rvalue)); 70956f157acbSml 70966f157acbSml rvalue |= NXGE_PCI_RESET_ALL; 70976f157acbSml pci_config_put32(nxgep->dev_regs->nxge_pciregh, 70986f157acbSml NXGE_PCI_PORT_LOGIC_OFFSET, rvalue); 70996f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 71006f157acbSml "nxge_niu_peu_reset: RESETTING NIU: write NIU reset 0x%x", 71016f157acbSml rvalue)); 71026f157acbSml 71036f157acbSml NXGE_DELAY(NXGE_PCI_RESET_WAIT); 71046f157acbSml } 71056f157acbSml 71066f157acbSml MUTEX_EXIT(&hw_p->nxge_cfg_lock); 71076f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_niu_peu_reset")); 71086f157acbSml } 7109d6d3405fSml 7110d6d3405fSml static void 7111d6d3405fSml nxge_set_pci_replay_timeout(p_nxge_t nxgep) 7112d6d3405fSml { 7113da14cebeSEric Cheng p_dev_regs_t dev_regs; 7114d6d3405fSml uint32_t value; 7115d6d3405fSml 7116d6d3405fSml NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_set_pci_replay_timeout")); 7117d6d3405fSml 7118d6d3405fSml if (!nxge_set_replay_timer) { 7119d6d3405fSml NXGE_DEBUG_MSG((nxgep, DDI_CTL, 7120d6d3405fSml "==> nxge_set_pci_replay_timeout: will not change " 7121d6d3405fSml "the timeout")); 7122d6d3405fSml return; 7123d6d3405fSml } 7124d6d3405fSml 7125d6d3405fSml dev_regs = nxgep->dev_regs; 7126d6d3405fSml NXGE_DEBUG_MSG((nxgep, DDI_CTL, 7127d6d3405fSml "==> nxge_set_pci_replay_timeout: dev_regs 0x%p pcireg 0x%p", 7128d6d3405fSml dev_regs, dev_regs->nxge_pciregh)); 7129d6d3405fSml 7130d6d3405fSml if (dev_regs == NULL || (dev_regs->nxge_pciregh == NULL)) { 7131f720bc57Syc NXGE_DEBUG_MSG((nxgep, DDI_CTL, 7132d6d3405fSml "==> nxge_set_pci_replay_timeout: NULL dev_regs $%p or " 7133d6d3405fSml "no PCI handle", 7134d6d3405fSml dev_regs)); 7135d6d3405fSml return; 7136d6d3405fSml } 7137d6d3405fSml value = (pci_config_get32(dev_regs->nxge_pciregh, 7138d6d3405fSml PCI_REPLAY_TIMEOUT_CFG_OFFSET) | 7139d6d3405fSml (nxge_replay_timeout << PCI_REPLAY_TIMEOUT_SHIFT)); 7140d6d3405fSml 7141d6d3405fSml NXGE_DEBUG_MSG((nxgep, DDI_CTL, 7142d6d3405fSml "nxge_set_pci_replay_timeout: replay timeout value before set 0x%x " 7143d6d3405fSml "(timeout value to set 0x%x at offset 0x%x) value 0x%x", 7144d6d3405fSml pci_config_get32(dev_regs->nxge_pciregh, 7145d6d3405fSml PCI_REPLAY_TIMEOUT_CFG_OFFSET), nxge_replay_timeout, 7146d6d3405fSml PCI_REPLAY_TIMEOUT_CFG_OFFSET, value)); 7147d6d3405fSml 7148d6d3405fSml pci_config_put32(dev_regs->nxge_pciregh, PCI_REPLAY_TIMEOUT_CFG_OFFSET, 7149d6d3405fSml value); 7150d6d3405fSml 7151d6d3405fSml NXGE_DEBUG_MSG((nxgep, DDI_CTL, 7152d6d3405fSml "nxge_set_pci_replay_timeout: replay timeout value after set 0x%x", 7153d6d3405fSml pci_config_get32(dev_regs->nxge_pciregh, 7154d6d3405fSml PCI_REPLAY_TIMEOUT_CFG_OFFSET))); 7155d6d3405fSml 7156d6d3405fSml NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_set_pci_replay_timeout")); 7157d6d3405fSml } 715819397407SSherry Moore 715919397407SSherry Moore /* 716019397407SSherry Moore * quiesce(9E) entry point. 716119397407SSherry Moore * 716219397407SSherry Moore * This function is called when the system is single-threaded at high 716319397407SSherry Moore * PIL with preemption disabled. Therefore, this function must not be 716419397407SSherry Moore * blocked. 716519397407SSherry Moore * 716619397407SSherry Moore * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 716719397407SSherry Moore * DDI_FAILURE indicates an error condition and should almost never happen. 716819397407SSherry Moore */ 716919397407SSherry Moore static int 717019397407SSherry Moore nxge_quiesce(dev_info_t *dip) 717119397407SSherry Moore { 717219397407SSherry Moore int instance = ddi_get_instance(dip); 717319397407SSherry Moore p_nxge_t nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance); 717419397407SSherry Moore 717519397407SSherry Moore if (nxgep == NULL) 717619397407SSherry Moore return (DDI_FAILURE); 717719397407SSherry Moore 717819397407SSherry Moore /* Turn off debugging */ 717919397407SSherry Moore nxge_debug_level = NO_DEBUG; 718019397407SSherry Moore nxgep->nxge_debug_level = NO_DEBUG; 718119397407SSherry Moore npi_debug_level = NO_DEBUG; 718219397407SSherry Moore 718319397407SSherry Moore /* 718419397407SSherry Moore * Stop link monitor only when linkchkmod is interrupt based 718519397407SSherry Moore */ 718619397407SSherry Moore if (nxgep->mac.linkchkmode == LINKCHK_INTR) { 718719397407SSherry Moore (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 718819397407SSherry Moore } 718919397407SSherry Moore 719019397407SSherry Moore (void) nxge_intr_hw_disable(nxgep); 719119397407SSherry Moore 719219397407SSherry Moore /* 719319397407SSherry Moore * Reset the receive MAC side. 719419397407SSherry Moore */ 719519397407SSherry Moore (void) nxge_rx_mac_disable(nxgep); 719619397407SSherry Moore 719719397407SSherry Moore /* Disable and soft reset the IPP */ 719819397407SSherry Moore if (!isLDOMguest(nxgep)) 719919397407SSherry Moore (void) nxge_ipp_disable(nxgep); 720019397407SSherry Moore 720119397407SSherry Moore /* 720219397407SSherry Moore * Reset the transmit/receive DMA side. 720319397407SSherry Moore */ 720419397407SSherry Moore (void) nxge_txdma_hw_mode(nxgep, NXGE_DMA_STOP); 720519397407SSherry Moore (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_STOP); 720619397407SSherry Moore 720719397407SSherry Moore /* 720819397407SSherry Moore * Reset the transmit MAC side. 720919397407SSherry Moore */ 721019397407SSherry Moore (void) nxge_tx_mac_disable(nxgep); 721119397407SSherry Moore 721219397407SSherry Moore return (DDI_SUCCESS); 721319397407SSherry Moore } 7214