xref: /illumos-gate/usr/src/uts/common/io/nxge/nxge_main.c (revision 86ef0a63)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved.
23  * Copyright 2016 OmniTI Computer Consulting, Inc. All rights reserved.
24  */
25 
26 /*
27  * SunOs MT STREAMS NIU/Neptune 10Gb Ethernet Device Driver.
28  */
29 #include	<sys/nxge/nxge_impl.h>
30 #include	<sys/nxge/nxge_hio.h>
31 #include	<sys/nxge/nxge_rxdma.h>
32 #include	<sys/pcie.h>
33 
34 uint32_t	nxge_use_partition = 0;		/* debug partition flag */
35 uint32_t	nxge_dma_obp_props_only = 1;	/* use obp published props */
36 uint32_t	nxge_use_rdc_intr = 1;		/* debug to assign rdc intr */
37 /*
38  * PSARC/2007/453 MSI-X interrupt limit override
39  */
40 uint32_t	nxge_msi_enable = 2;
41 
42 /*
43  * Software workaround for a Neptune (PCI-E)
44  * hardware interrupt bug which the hardware
45  * may generate spurious interrupts after the
46  * device interrupt handler was removed. If this flag
47  * is enabled, the driver will reset the
48  * hardware when devices are being detached.
49  */
50 uint32_t	nxge_peu_reset_enable = 0;
51 
52 /*
53  * Software workaround for the hardware
54  * checksum bugs that affect packet transmission
55  * and receive:
56  *
57  * Usage of nxge_cksum_offload:
58  *
59  *  (1) nxge_cksum_offload = 0 (default):
60  *	- transmits packets:
61  *	  TCP: uses the hardware checksum feature.
62  *	  UDP: driver will compute the software checksum
63  *	       based on the partial checksum computed
64  *	       by the IP layer.
65  *	- receives packets
66  *	  TCP: marks packets checksum flags based on hardware result.
67  *	  UDP: will not mark checksum flags.
68  *
69  *  (2) nxge_cksum_offload = 1:
70  *	- transmit packets:
71  *	  TCP/UDP: uses the hardware checksum feature.
72  *	- receives packets
73  *	  TCP/UDP: marks packet checksum flags based on hardware result.
74  *
75  *  (3) nxge_cksum_offload = 2:
76  *	- The driver will not register its checksum capability.
77  *	  Checksum for both TCP and UDP will be computed
78  *	  by the stack.
79  *	- The software LSO is not allowed in this case.
80  *
81  *  (4) nxge_cksum_offload > 2:
82  *	- Will be treated as it is set to 2
83  *	  (stack will compute the checksum).
84  *
85  *  (5) If the hardware bug is fixed, this workaround
86  *	needs to be updated accordingly to reflect
87  *	the new hardware revision.
88  */
89 uint32_t	nxge_cksum_offload = 0;
90 
91 /*
92  * Globals: tunable parameters (/etc/system or adb)
93  *
94  */
95 uint32_t	nxge_rbr_size = NXGE_RBR_RBB_DEFAULT;
96 uint32_t	nxge_rbr_spare_size = 0;
97 uint32_t	nxge_rcr_size = NXGE_RCR_DEFAULT;
98 uint16_t	nxge_rdc_buf_offset = SW_OFFSET_NO_OFFSET;
99 uint32_t	nxge_tx_ring_size = NXGE_TX_RING_DEFAULT;
100 boolean_t	nxge_no_msg = B_TRUE;		/* control message display */
101 uint32_t	nxge_no_link_notify = 0;	/* control DL_NOTIFY */
102 uint32_t	nxge_bcopy_thresh = TX_BCOPY_MAX;
103 uint32_t	nxge_dvma_thresh = TX_FASTDVMA_MIN;
104 uint32_t	nxge_dma_stream_thresh = TX_STREAM_MIN;
105 uint32_t	nxge_jumbo_mtu	= TX_JUMBO_MTU;
106 nxge_tx_mode_t	nxge_tx_scheme = NXGE_USE_SERIAL;
107 
108 /* MAX LSO size */
109 #define		NXGE_LSO_MAXLEN	65535
110 uint32_t	nxge_lso_max = NXGE_LSO_MAXLEN;
111 
112 
113 /*
114  * Add tunable to reduce the amount of time spent in the
115  * ISR doing Rx Processing.
116  */
117 uint32_t nxge_max_rx_pkts = 1024;
118 
119 /*
120  * Tunables to manage the receive buffer blocks.
121  *
122  * nxge_rx_threshold_hi: copy all buffers.
123  * nxge_rx_bcopy_size_type: receive buffer block size type.
124  * nxge_rx_threshold_lo: copy only up to tunable block size type.
125  */
126 nxge_rxbuf_threshold_t nxge_rx_threshold_hi = NXGE_RX_COPY_6;
127 nxge_rxbuf_type_t nxge_rx_buf_size_type = RCR_PKTBUFSZ_0;
128 nxge_rxbuf_threshold_t nxge_rx_threshold_lo = NXGE_RX_COPY_3;
129 
130 uint32_t	nxge_use_kmem_alloc = 1;
131 
132 rtrace_t npi_rtracebuf;
133 
134 /*
135  * The hardware sometimes fails to allow enough time for the link partner
136  * to send an acknowledgement for packets that the hardware sent to it. The
137  * hardware resends the packets earlier than it should be in those instances.
138  * This behavior caused some switches to acknowledge the wrong packets
139  * and it triggered the fatal error.
140  * This software workaround is to set the replay timer to a value
141  * suggested by the hardware team.
142  *
143  * PCI config space replay timer register:
144  *     The following replay timeout value is 0xc
145  *     for bit 14:18.
146  */
147 #define	PCI_REPLAY_TIMEOUT_CFG_OFFSET	0xb8
148 #define	PCI_REPLAY_TIMEOUT_SHIFT	14
149 
150 uint32_t	nxge_set_replay_timer = 1;
151 uint32_t	nxge_replay_timeout = 0xc;
152 
153 /*
154  * The transmit serialization sometimes causes
155  * longer sleep before calling the driver transmit
156  * function as it sleeps longer than it should.
157  * The performace group suggests that a time wait tunable
158  * can be used to set the maximum wait time when needed
159  * and the default is set to 1 tick.
160  */
161 uint32_t	nxge_tx_serial_maxsleep = 1;
162 
163 #if	defined(sun4v)
164 /*
165  * Hypervisor N2/NIU services information.
166  */
167 /*
168  * The following is the default API supported:
169  * major 1 and minor 1.
170  *
171  * Please update the MAX_NIU_MAJORS,
172  * MAX_NIU_MINORS, and minor number supported
173  * when the newer Hypervior API interfaces
174  * are added. Also, please update nxge_hsvc_register()
175  * if needed.
176  */
177 static hsvc_info_t niu_hsvc = {
178 	HSVC_REV_1, NULL, HSVC_GROUP_NIU, NIU_MAJOR_VER,
179 	NIU_MINOR_VER, "nxge"
180 };
181 
182 static int nxge_hsvc_register(p_nxge_t);
183 #endif
184 
185 /*
186  * Function Prototypes
187  */
188 static int nxge_attach(dev_info_t *, ddi_attach_cmd_t);
189 static int nxge_detach(dev_info_t *, ddi_detach_cmd_t);
190 static void nxge_unattach(p_nxge_t);
191 static int nxge_quiesce(dev_info_t *);
192 
193 #if NXGE_PROPERTY
194 static void nxge_remove_hard_properties(p_nxge_t);
195 #endif
196 
197 /*
198  * These two functions are required by nxge_hio.c
199  */
200 extern int nxge_m_mmac_remove(void *arg, int slot);
201 extern void nxge_grp_cleanup(p_nxge_t nxge);
202 
203 static nxge_status_t nxge_setup_system_dma_pages(p_nxge_t);
204 
205 static nxge_status_t nxge_setup_mutexes(p_nxge_t);
206 static void nxge_destroy_mutexes(p_nxge_t);
207 
208 static nxge_status_t nxge_map_regs(p_nxge_t nxgep);
209 static void nxge_unmap_regs(p_nxge_t nxgep);
210 #ifdef	NXGE_DEBUG
211 static void nxge_test_map_regs(p_nxge_t nxgep);
212 #endif
213 
214 static nxge_status_t nxge_add_intrs(p_nxge_t nxgep);
215 static void nxge_remove_intrs(p_nxge_t nxgep);
216 
217 static nxge_status_t nxge_add_intrs_adv(p_nxge_t nxgep);
218 static nxge_status_t nxge_add_intrs_adv_type(p_nxge_t, uint32_t);
219 static nxge_status_t nxge_add_intrs_adv_type_fix(p_nxge_t, uint32_t);
220 static void nxge_intrs_enable(p_nxge_t nxgep);
221 static void nxge_intrs_disable(p_nxge_t nxgep);
222 
223 static void nxge_suspend(p_nxge_t);
224 static nxge_status_t nxge_resume(p_nxge_t);
225 
226 static nxge_status_t nxge_setup_dev(p_nxge_t);
227 static void nxge_destroy_dev(p_nxge_t);
228 
229 static nxge_status_t nxge_alloc_mem_pool(p_nxge_t);
230 static void nxge_free_mem_pool(p_nxge_t);
231 
232 nxge_status_t nxge_alloc_rx_mem_pool(p_nxge_t);
233 static void nxge_free_rx_mem_pool(p_nxge_t);
234 
235 nxge_status_t nxge_alloc_tx_mem_pool(p_nxge_t);
236 static void nxge_free_tx_mem_pool(p_nxge_t);
237 
238 static nxge_status_t nxge_dma_mem_alloc(p_nxge_t, dma_method_t,
239 	struct ddi_dma_attr *,
240 	size_t, ddi_device_acc_attr_t *, uint_t,
241 	p_nxge_dma_common_t);
242 
243 static void nxge_dma_mem_free(p_nxge_dma_common_t);
244 static void nxge_dma_free_rx_data_buf(p_nxge_dma_common_t);
245 
246 static nxge_status_t nxge_alloc_rx_buf_dma(p_nxge_t, uint16_t,
247 	p_nxge_dma_common_t *, size_t, size_t, uint32_t *);
248 static void nxge_free_rx_buf_dma(p_nxge_t, p_nxge_dma_common_t, uint32_t);
249 
250 static nxge_status_t nxge_alloc_rx_cntl_dma(p_nxge_t, uint16_t,
251 	p_nxge_dma_common_t *, size_t);
252 static void nxge_free_rx_cntl_dma(p_nxge_t, p_nxge_dma_common_t);
253 
254 extern nxge_status_t nxge_alloc_tx_buf_dma(p_nxge_t, uint16_t,
255 	p_nxge_dma_common_t *, size_t, size_t, uint32_t *);
256 static void nxge_free_tx_buf_dma(p_nxge_t, p_nxge_dma_common_t, uint32_t);
257 
258 extern nxge_status_t nxge_alloc_tx_cntl_dma(p_nxge_t, uint16_t,
259 	p_nxge_dma_common_t *,
260 	size_t);
261 static void nxge_free_tx_cntl_dma(p_nxge_t, p_nxge_dma_common_t);
262 
263 static int nxge_init_common_dev(p_nxge_t);
264 static void nxge_uninit_common_dev(p_nxge_t);
265 extern int nxge_param_set_mac(p_nxge_t, queue_t *, mblk_t *,
266     char *, caddr_t);
267 #if defined(sun4v)
268 extern nxge_status_t nxge_hio_rdc_enable(p_nxge_t nxgep);
269 extern nxge_status_t nxge_hio_rdc_intr_arm(p_nxge_t nxge, boolean_t arm);
270 #endif
271 
272 /*
273  * The next declarations are for the GLDv3 interface.
274  */
275 static int nxge_m_start(void *);
276 static void nxge_m_stop(void *);
277 static int nxge_m_multicst(void *, boolean_t, const uint8_t *);
278 static int nxge_m_promisc(void *, boolean_t);
279 static void nxge_m_ioctl(void *, queue_t *, mblk_t *);
280 nxge_status_t nxge_mac_register(p_nxge_t);
281 static int nxge_altmac_set(p_nxge_t nxgep, uint8_t *mac_addr,
282 	int slot, int rdctbl, boolean_t usetbl);
283 void nxge_mmac_kstat_update(p_nxge_t nxgep, int slot,
284 	boolean_t factory);
285 
286 static void nxge_m_getfactaddr(void *, uint_t, uint8_t *);
287 static	boolean_t nxge_m_getcapab(void *, mac_capab_t, void *);
288 static int nxge_m_setprop(void *, const char *, mac_prop_id_t,
289     uint_t, const void *);
290 static int nxge_m_getprop(void *, const char *, mac_prop_id_t,
291     uint_t, void *);
292 static void nxge_m_propinfo(void *, const char *, mac_prop_id_t,
293     mac_prop_info_handle_t);
294 static void nxge_priv_propinfo(const char *, mac_prop_info_handle_t);
295 static int nxge_set_priv_prop(nxge_t *, const char *, uint_t,
296     const void *);
297 static int nxge_get_priv_prop(nxge_t *, const char *, uint_t, void *);
298 static void nxge_fill_ring(void *, mac_ring_type_t, const int, const int,
299     mac_ring_info_t *, mac_ring_handle_t);
300 static void nxge_group_add_ring(mac_group_driver_t, mac_ring_driver_t,
301     mac_ring_type_t);
302 static void nxge_group_rem_ring(mac_group_driver_t, mac_ring_driver_t,
303     mac_ring_type_t);
304 
305 static void nxge_niu_peu_reset(p_nxge_t nxgep);
306 static void nxge_set_pci_replay_timeout(nxge_t *);
307 
308 char *nxge_priv_props[] = {
309 	"_adv_10gfdx_cap",
310 	"_adv_pause_cap",
311 	"_function_number",
312 	"_fw_version",
313 	"_port_mode",
314 	"_hot_swap_phy",
315 	"_rxdma_intr_time",
316 	"_rxdma_intr_pkts",
317 	"_class_opt_ipv4_tcp",
318 	"_class_opt_ipv4_udp",
319 	"_class_opt_ipv4_ah",
320 	"_class_opt_ipv4_sctp",
321 	"_class_opt_ipv6_tcp",
322 	"_class_opt_ipv6_udp",
323 	"_class_opt_ipv6_ah",
324 	"_class_opt_ipv6_sctp",
325 	"_soft_lso_enable",
326 	NULL
327 };
328 
329 #define	NXGE_NEPTUNE_MAGIC	0x4E584745UL
330 #define	MAX_DUMP_SZ 256
331 
332 #define	NXGE_M_CALLBACK_FLAGS	\
333 	(MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP | MC_PROPINFO)
334 
335 mac_callbacks_t nxge_m_callbacks = {
336 	NXGE_M_CALLBACK_FLAGS,
337 	nxge_m_stat,
338 	nxge_m_start,
339 	nxge_m_stop,
340 	nxge_m_promisc,
341 	nxge_m_multicst,
342 	NULL,
343 	NULL,
344 	NULL,
345 	nxge_m_ioctl,
346 	nxge_m_getcapab,
347 	NULL,
348 	NULL,
349 	nxge_m_setprop,
350 	nxge_m_getprop,
351 	nxge_m_propinfo
352 };
353 
354 void
355 nxge_err_inject(p_nxge_t, queue_t *, mblk_t *);
356 
357 /* PSARC/2007/453 MSI-X interrupt limit override. */
358 #define	NXGE_MSIX_REQUEST_10G	8
359 #define	NXGE_MSIX_REQUEST_1G	2
360 static int nxge_create_msi_property(p_nxge_t);
361 /*
362  * For applications that care about the
363  * latency, it was requested by PAE and the
364  * customers that the driver has tunables that
365  * allow the user to tune it to a higher number
366  * interrupts to spread the interrupts among
367  * multiple channels. The DDI framework limits
368  * the maximum number of MSI-X resources to allocate
369  * to 8 (ddi_msix_alloc_limit). If more than 8
370  * is set, ddi_msix_alloc_limit must be set accordingly.
371  * The default number of MSI interrupts are set to
372  * 8 for 10G and 2 for 1G link.
373  */
374 #define	NXGE_MSIX_MAX_ALLOWED	32
375 uint32_t nxge_msix_10g_intrs = NXGE_MSIX_REQUEST_10G;
376 uint32_t nxge_msix_1g_intrs = NXGE_MSIX_REQUEST_1G;
377 
378 /*
379  * These global variables control the message
380  * output.
381  */
382 out_dbgmsg_t nxge_dbgmsg_out = DBG_CONSOLE | STR_LOG;
383 uint64_t nxge_debug_level;
384 
385 /*
386  * This list contains the instance structures for the Neptune
387  * devices present in the system. The lock exists to guarantee
388  * mutually exclusive access to the list.
389  */
390 void			*nxge_list = NULL;
391 void			*nxge_hw_list = NULL;
392 nxge_os_mutex_t		nxge_common_lock;
393 nxge_os_mutex_t		nxgedebuglock;
394 
395 extern uint64_t		npi_debug_level;
396 
397 extern nxge_status_t	nxge_ldgv_init(p_nxge_t, int *, int *);
398 extern nxge_status_t	nxge_ldgv_init_n2(p_nxge_t, int *, int *);
399 extern nxge_status_t	nxge_ldgv_uninit(p_nxge_t);
400 extern nxge_status_t	nxge_intr_ldgv_init(p_nxge_t);
401 extern void		nxge_fm_init(p_nxge_t,
402 					ddi_device_acc_attr_t *,
403 					ddi_dma_attr_t *);
404 extern void		nxge_fm_fini(p_nxge_t);
405 extern npi_status_t	npi_mac_altaddr_disable(npi_handle_t, uint8_t, uint8_t);
406 
407 /*
408  * Count used to maintain the number of buffers being used
409  * by Neptune instances and loaned up to the upper layers.
410  */
411 uint32_t nxge_mblks_pending = 0;
412 
413 /*
414  * Device register access attributes for PIO.
415  */
416 static ddi_device_acc_attr_t nxge_dev_reg_acc_attr = {
417 	DDI_DEVICE_ATTR_V1,
418 	DDI_STRUCTURE_LE_ACC,
419 	DDI_STRICTORDER_ACC,
420 	DDI_DEFAULT_ACC
421 };
422 
423 /*
424  * Device descriptor access attributes for DMA.
425  */
426 static ddi_device_acc_attr_t nxge_dev_desc_dma_acc_attr = {
427 	DDI_DEVICE_ATTR_V0,
428 	DDI_STRUCTURE_LE_ACC,
429 	DDI_STRICTORDER_ACC
430 };
431 
432 /*
433  * Device buffer access attributes for DMA.
434  */
435 static ddi_device_acc_attr_t nxge_dev_buf_dma_acc_attr = {
436 	DDI_DEVICE_ATTR_V0,
437 	DDI_STRUCTURE_BE_ACC,
438 	DDI_STRICTORDER_ACC
439 };
440 
441 ddi_dma_attr_t nxge_desc_dma_attr = {
442 	DMA_ATTR_V0,		/* version number. */
443 	0,			/* low address */
444 	0xffffffffffffffff,	/* high address */
445 	0xffffffffffffffff,	/* address counter max */
446 #ifndef NIU_PA_WORKAROUND
447 	0x100000,		/* alignment */
448 #else
449 	0x2000,
450 #endif
451 	0xfc00fc,		/* dlim_burstsizes */
452 	0x1,			/* minimum transfer size */
453 	0xffffffffffffffff,	/* maximum transfer size */
454 	0xffffffffffffffff,	/* maximum segment size */
455 	1,			/* scatter/gather list length */
456 	(unsigned int) 1,	/* granularity */
457 	0			/* attribute flags */
458 };
459 
460 ddi_dma_attr_t nxge_tx_dma_attr = {
461 	DMA_ATTR_V0,		/* version number. */
462 	0,			/* low address */
463 	0xffffffffffffffff,	/* high address */
464 	0xffffffffffffffff,	/* address counter max */
465 #if defined(_BIG_ENDIAN)
466 	0x2000,			/* alignment */
467 #else
468 	0x1000,			/* alignment */
469 #endif
470 	0xfc00fc,		/* dlim_burstsizes */
471 	0x1,			/* minimum transfer size */
472 	0xffffffffffffffff,	/* maximum transfer size */
473 	0xffffffffffffffff,	/* maximum segment size */
474 	5,			/* scatter/gather list length */
475 	(unsigned int) 1,	/* granularity */
476 	0			/* attribute flags */
477 };
478 
479 ddi_dma_attr_t nxge_rx_dma_attr = {
480 	DMA_ATTR_V0,		/* version number. */
481 	0,			/* low address */
482 	0xffffffffffffffff,	/* high address */
483 	0xffffffffffffffff,	/* address counter max */
484 	0x2000,			/* alignment */
485 	0xfc00fc,		/* dlim_burstsizes */
486 	0x1,			/* minimum transfer size */
487 	0xffffffffffffffff,	/* maximum transfer size */
488 	0xffffffffffffffff,	/* maximum segment size */
489 	1,			/* scatter/gather list length */
490 	(unsigned int) 1,	/* granularity */
491 	DDI_DMA_RELAXED_ORDERING /* attribute flags */
492 };
493 
494 ddi_dma_lim_t nxge_dma_limits = {
495 	(uint_t)0,		/* dlim_addr_lo */
496 	(uint_t)0xffffffff,	/* dlim_addr_hi */
497 	(uint_t)0xffffffff,	/* dlim_cntr_max */
498 	(uint_t)0xfc00fc,	/* dlim_burstsizes for 32 and 64 bit xfers */
499 	0x1,			/* dlim_minxfer */
500 	1024			/* dlim_speed */
501 };
502 
503 dma_method_t nxge_force_dma = DVMA;
504 
505 /*
506  * dma chunk sizes.
507  *
508  * Try to allocate the largest possible size
509  * so that fewer number of dma chunks would be managed
510  */
511 #ifdef NIU_PA_WORKAROUND
512 size_t alloc_sizes [] = {0x2000};
513 #else
514 size_t alloc_sizes [] = {0x1000, 0x2000, 0x4000, 0x8000,
515 		0x10000, 0x20000, 0x40000, 0x80000,
516 		0x100000, 0x200000, 0x400000, 0x800000,
517 		0x1000000, 0x2000000, 0x4000000};
518 #endif
519 
520 /*
521  * Translate "dev_t" to a pointer to the associated "dev_info_t".
522  */
523 
524 extern void nxge_get_environs(nxge_t *);
525 
526 static int
nxge_attach(dev_info_t * dip,ddi_attach_cmd_t cmd)527 nxge_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
528 {
529 	p_nxge_t	nxgep = NULL;
530 	int		instance;
531 	int		status = DDI_SUCCESS;
532 	uint8_t		portn;
533 	nxge_mmac_t	*mmac_info;
534 
535 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_attach"));
536 
537 	/*
538 	 * Get the device instance since we'll need to setup
539 	 * or retrieve a soft state for this instance.
540 	 */
541 	instance = ddi_get_instance(dip);
542 
543 	switch (cmd) {
544 	case DDI_ATTACH:
545 		NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_ATTACH"));
546 		break;
547 
548 	case DDI_RESUME:
549 		NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_RESUME"));
550 		nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance);
551 		if (nxgep == NULL) {
552 			status = DDI_FAILURE;
553 			break;
554 		}
555 		if (nxgep->dip != dip) {
556 			status = DDI_FAILURE;
557 			break;
558 		}
559 		if (nxgep->suspended == DDI_PM_SUSPEND) {
560 			status = ddi_dev_is_needed(nxgep->dip, 0, 1);
561 		} else {
562 			status = nxge_resume(nxgep);
563 		}
564 		goto nxge_attach_exit;
565 
566 	case DDI_PM_RESUME:
567 		NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_PM_RESUME"));
568 		nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance);
569 		if (nxgep == NULL) {
570 			status = DDI_FAILURE;
571 			break;
572 		}
573 		if (nxgep->dip != dip) {
574 			status = DDI_FAILURE;
575 			break;
576 		}
577 		status = nxge_resume(nxgep);
578 		goto nxge_attach_exit;
579 
580 	default:
581 		NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing unknown"));
582 		status = DDI_FAILURE;
583 		goto nxge_attach_exit;
584 	}
585 
586 
587 	if (ddi_soft_state_zalloc(nxge_list, instance) == DDI_FAILURE) {
588 		status = DDI_FAILURE;
589 		goto nxge_attach_exit;
590 	}
591 
592 	nxgep = ddi_get_soft_state(nxge_list, instance);
593 	if (nxgep == NULL) {
594 		status = NXGE_ERROR;
595 		goto nxge_attach_fail2;
596 	}
597 
598 	nxgep->nxge_magic = NXGE_MAGIC;
599 
600 	nxgep->drv_state = 0;
601 	nxgep->dip = dip;
602 	nxgep->instance = instance;
603 	nxgep->p_dip = ddi_get_parent(dip);
604 	nxgep->nxge_debug_level = nxge_debug_level;
605 	npi_debug_level = nxge_debug_level;
606 
607 	/* Are we a guest running in a Hybrid I/O environment? */
608 	nxge_get_environs(nxgep);
609 
610 	status = nxge_map_regs(nxgep);
611 
612 	if (status != NXGE_OK) {
613 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_map_regs failed"));
614 		goto nxge_attach_fail3;
615 	}
616 
617 	nxge_fm_init(nxgep, &nxge_dev_reg_acc_attr, &nxge_rx_dma_attr);
618 
619 	/* Create & initialize the per-Neptune data structure */
620 	/* (even if we're a guest). */
621 	status = nxge_init_common_dev(nxgep);
622 	if (status != NXGE_OK) {
623 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
624 		    "nxge_init_common_dev failed"));
625 		goto nxge_attach_fail4;
626 	}
627 
628 	/*
629 	 * Software workaround: set the replay timer.
630 	 */
631 	if (nxgep->niu_type != N2_NIU) {
632 		nxge_set_pci_replay_timeout(nxgep);
633 	}
634 
635 #if defined(sun4v)
636 	/* This is required by nxge_hio_init(), which follows. */
637 	if ((status = nxge_hsvc_register(nxgep)) != DDI_SUCCESS)
638 		goto nxge_attach_fail4;
639 #endif
640 
641 	if ((status = nxge_hio_init(nxgep)) != NXGE_OK) {
642 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
643 		    "nxge_hio_init failed"));
644 		goto nxge_attach_fail4;
645 	}
646 
647 	if (nxgep->niu_type == NEPTUNE_2_10GF) {
648 		if (nxgep->function_num > 1) {
649 			NXGE_DEBUG_MSG((nxgep, DDI_CTL, "Unsupported"
650 			    " function %d. Only functions 0 and 1 are "
651 			    "supported for this card.", nxgep->function_num));
652 			status = NXGE_ERROR;
653 			goto nxge_attach_fail4;
654 		}
655 	}
656 
657 	if (isLDOMguest(nxgep)) {
658 		/*
659 		 * Use the function number here.
660 		 */
661 		nxgep->mac.portnum = nxgep->function_num;
662 		nxgep->mac.porttype = PORT_TYPE_LOGICAL;
663 
664 		/* XXX We'll set the MAC address counts to 1 for now. */
665 		mmac_info = &nxgep->nxge_mmac_info;
666 		mmac_info->num_mmac = 1;
667 		mmac_info->naddrfree = 1;
668 	} else {
669 		portn = NXGE_GET_PORT_NUM(nxgep->function_num);
670 		nxgep->mac.portnum = portn;
671 		if ((portn == 0) || (portn == 1))
672 			nxgep->mac.porttype = PORT_TYPE_XMAC;
673 		else
674 			nxgep->mac.porttype = PORT_TYPE_BMAC;
675 		/*
676 		 * Neptune has 4 ports, the first 2 ports use XMAC (10G MAC)
677 		 * internally, the rest 2 ports use BMAC (1G "Big" MAC).
678 		 * The two types of MACs have different characterizations.
679 		 */
680 		mmac_info = &nxgep->nxge_mmac_info;
681 		if (nxgep->function_num < 2) {
682 			mmac_info->num_mmac = XMAC_MAX_ALT_ADDR_ENTRY;
683 			mmac_info->naddrfree = XMAC_MAX_ALT_ADDR_ENTRY;
684 		} else {
685 			mmac_info->num_mmac = BMAC_MAX_ALT_ADDR_ENTRY;
686 			mmac_info->naddrfree = BMAC_MAX_ALT_ADDR_ENTRY;
687 		}
688 	}
689 	/*
690 	 * Setup the Ndd parameters for the this instance.
691 	 */
692 	nxge_init_param(nxgep);
693 
694 	/*
695 	 * Setup Register Tracing Buffer.
696 	 */
697 	npi_rtrace_buf_init((rtrace_t *)&npi_rtracebuf);
698 
699 	/* init stats ptr */
700 	nxge_init_statsp(nxgep);
701 
702 	/*
703 	 * Copy the vpd info from eeprom to a local data
704 	 * structure, and then check its validity.
705 	 */
706 	if (!isLDOMguest(nxgep)) {
707 		int *regp;
708 		uint_t reglen;
709 		int rv;
710 
711 		nxge_vpd_info_get(nxgep);
712 
713 		/* Find the NIU config handle. */
714 		rv = ddi_prop_lookup_int_array(DDI_DEV_T_ANY,
715 		    ddi_get_parent(nxgep->dip), DDI_PROP_DONTPASS,
716 		    "reg", &regp, &reglen);
717 
718 		if (rv != DDI_PROP_SUCCESS) {
719 			goto nxge_attach_fail5;
720 		}
721 		/*
722 		 * The address_hi, that is the first int, in the reg
723 		 * property consists of config handle, but need to remove
724 		 * the bits 28-31 which are OBP specific info.
725 		 */
726 		nxgep->niu_cfg_hdl = (*regp) & 0xFFFFFFF;
727 		ddi_prop_free(regp);
728 	}
729 
730 	/*
731 	 * Set the defaults for the MTU size.
732 	 */
733 	nxge_hw_id_init(nxgep);
734 
735 	if (isLDOMguest(nxgep)) {
736 		uchar_t *prop_val;
737 		uint_t prop_len;
738 		uint32_t max_frame_size;
739 
740 		extern void nxge_get_logical_props(p_nxge_t);
741 
742 		nxgep->statsp->mac_stats.xcvr_inuse = LOGICAL_XCVR;
743 		nxgep->mac.portmode = PORT_LOGICAL;
744 		(void) ddi_prop_update_string(DDI_DEV_T_NONE, nxgep->dip,
745 		    "phy-type", "virtual transceiver");
746 
747 		nxgep->nports = 1;
748 		nxgep->board_ver = 0;	/* XXX What? */
749 
750 		/*
751 		 * local-mac-address property gives us info on which
752 		 * specific MAC address the Hybrid resource is associated
753 		 * with.
754 		 */
755 		if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
756 		    "local-mac-address", &prop_val,
757 		    &prop_len) != DDI_PROP_SUCCESS) {
758 			goto nxge_attach_fail5;
759 		}
760 		if (prop_len !=	 ETHERADDRL) {
761 			ddi_prop_free(prop_val);
762 			goto nxge_attach_fail5;
763 		}
764 		ether_copy(prop_val, nxgep->hio_mac_addr);
765 		ddi_prop_free(prop_val);
766 		nxge_get_logical_props(nxgep);
767 
768 		/*
769 		 * Enable Jumbo property based on the "max-frame-size"
770 		 * property value.
771 		 */
772 		max_frame_size = ddi_prop_get_int(DDI_DEV_T_ANY,
773 		    nxgep->dip, DDI_PROP_DONTPASS | DDI_PROP_NOTPROM,
774 		    "max-frame-size", NXGE_MTU_DEFAULT_MAX);
775 		if ((max_frame_size > NXGE_MTU_DEFAULT_MAX) &&
776 		    (max_frame_size <= TX_JUMBO_MTU)) {
777 			nxgep->mac.is_jumbo = B_TRUE;
778 			nxgep->mac.maxframesize = (uint16_t)max_frame_size;
779 			nxgep->mac.default_mtu = nxgep->mac.maxframesize -
780 			    NXGE_EHEADER_VLAN_CRC;
781 		}
782 	} else {
783 		status = nxge_xcvr_find(nxgep);
784 
785 		if (status != NXGE_OK) {
786 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_attach: "
787 			    " Couldn't determine card type"
788 			    " .... exit "));
789 			goto nxge_attach_fail5;
790 		}
791 
792 		status = nxge_get_config_properties(nxgep);
793 
794 		if (status != NXGE_OK) {
795 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
796 			    "get_hw create failed"));
797 			goto nxge_attach_fail;
798 		}
799 	}
800 
801 	/*
802 	 * Setup the Kstats for the driver.
803 	 */
804 	nxge_setup_kstats(nxgep);
805 
806 	if (!isLDOMguest(nxgep))
807 		nxge_setup_param(nxgep);
808 
809 	status = nxge_setup_system_dma_pages(nxgep);
810 	if (status != NXGE_OK) {
811 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "set dma page failed"));
812 		goto nxge_attach_fail;
813 	}
814 
815 
816 	if (!isLDOMguest(nxgep))
817 		nxge_hw_init_niu_common(nxgep);
818 
819 	status = nxge_setup_mutexes(nxgep);
820 	if (status != NXGE_OK) {
821 		NXGE_DEBUG_MSG((nxgep, DDI_CTL, "set mutex failed"));
822 		goto nxge_attach_fail;
823 	}
824 
825 #if defined(sun4v)
826 	if (isLDOMguest(nxgep)) {
827 		/* Find our VR & channel sets. */
828 		status = nxge_hio_vr_add(nxgep);
829 		if (status != DDI_SUCCESS) {
830 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
831 			    "nxge_hio_vr_add failed"));
832 			(void) hsvc_unregister(&nxgep->niu_hsvc);
833 			nxgep->niu_hsvc_available = B_FALSE;
834 			goto nxge_attach_fail;
835 		}
836 		goto nxge_attach_exit;
837 	}
838 #endif
839 
840 	status = nxge_setup_dev(nxgep);
841 	if (status != DDI_SUCCESS) {
842 		NXGE_DEBUG_MSG((nxgep, DDI_CTL, "set dev failed"));
843 		goto nxge_attach_fail;
844 	}
845 
846 	status = nxge_add_intrs(nxgep);
847 	if (status != DDI_SUCCESS) {
848 		NXGE_DEBUG_MSG((nxgep, DDI_CTL, "add_intr failed"));
849 		goto nxge_attach_fail;
850 	}
851 
852 	/* If a guest, register with vio_net instead. */
853 	if ((status = nxge_mac_register(nxgep)) != NXGE_OK) {
854 		NXGE_DEBUG_MSG((nxgep, DDI_CTL,
855 		    "unable to register to mac layer (%d)", status));
856 		goto nxge_attach_fail;
857 	}
858 
859 	mac_link_update(nxgep->mach, LINK_STATE_UNKNOWN);
860 
861 	NXGE_DEBUG_MSG((nxgep, DDI_CTL,
862 	    "registered to mac (instance %d)", instance));
863 
864 	/* nxge_link_monitor calls xcvr.check_link recursively */
865 	(void) nxge_link_monitor(nxgep, LINK_MONITOR_START);
866 
867 	goto nxge_attach_exit;
868 
869 nxge_attach_fail:
870 	nxge_unattach(nxgep);
871 	goto nxge_attach_fail1;
872 
873 nxge_attach_fail5:
874 	/*
875 	 * Tear down the ndd parameters setup.
876 	 */
877 	nxge_destroy_param(nxgep);
878 
879 	/*
880 	 * Tear down the kstat setup.
881 	 */
882 	nxge_destroy_kstats(nxgep);
883 
884 nxge_attach_fail4:
885 	if (nxgep->nxge_hw_p) {
886 		nxge_uninit_common_dev(nxgep);
887 		nxgep->nxge_hw_p = NULL;
888 	}
889 
890 nxge_attach_fail3:
891 	/*
892 	 * Unmap the register setup.
893 	 */
894 	nxge_unmap_regs(nxgep);
895 
896 	nxge_fm_fini(nxgep);
897 
898 nxge_attach_fail2:
899 	ddi_soft_state_free(nxge_list, nxgep->instance);
900 
901 nxge_attach_fail1:
902 	if (status != NXGE_OK)
903 		status = (NXGE_ERROR | NXGE_DDI_FAILED);
904 	nxgep = NULL;
905 
906 nxge_attach_exit:
907 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_attach status = 0x%08x",
908 	    status));
909 
910 	return (status);
911 }
912 
913 static int
nxge_detach(dev_info_t * dip,ddi_detach_cmd_t cmd)914 nxge_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
915 {
916 	int		status = DDI_SUCCESS;
917 	int		instance;
918 	p_nxge_t	nxgep = NULL;
919 
920 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_detach"));
921 	instance = ddi_get_instance(dip);
922 	nxgep = ddi_get_soft_state(nxge_list, instance);
923 	if (nxgep == NULL) {
924 		status = DDI_FAILURE;
925 		goto nxge_detach_exit;
926 	}
927 
928 	switch (cmd) {
929 	case DDI_DETACH:
930 		NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_DETACH"));
931 		break;
932 
933 	case DDI_PM_SUSPEND:
934 		NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_PM_SUSPEND"));
935 		nxgep->suspended = DDI_PM_SUSPEND;
936 		nxge_suspend(nxgep);
937 		break;
938 
939 	case DDI_SUSPEND:
940 		NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_SUSPEND"));
941 		if (nxgep->suspended != DDI_PM_SUSPEND) {
942 			nxgep->suspended = DDI_SUSPEND;
943 			nxge_suspend(nxgep);
944 		}
945 		break;
946 
947 	default:
948 		status = DDI_FAILURE;
949 	}
950 
951 	if (cmd != DDI_DETACH)
952 		goto nxge_detach_exit;
953 
954 	/*
955 	 * Stop the xcvr polling.
956 	 */
957 	nxgep->suspended = cmd;
958 
959 	(void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP);
960 
961 	if (nxgep->mach && (status = mac_unregister(nxgep->mach)) != 0) {
962 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
963 		    "<== nxge_detach status = 0x%08X", status));
964 		return (DDI_FAILURE);
965 	}
966 
967 	NXGE_DEBUG_MSG((nxgep, DDI_CTL,
968 	    "<== nxge_detach (mac_unregister) status = 0x%08X", status));
969 
970 	nxge_unattach(nxgep);
971 	nxgep = NULL;
972 
973 nxge_detach_exit:
974 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_detach status = 0x%08X",
975 	    status));
976 
977 	return (status);
978 }
979 
980 static void
nxge_unattach(p_nxge_t nxgep)981 nxge_unattach(p_nxge_t nxgep)
982 {
983 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_unattach"));
984 
985 	if (nxgep == NULL || nxgep->dev_regs == NULL) {
986 		return;
987 	}
988 
989 	nxgep->nxge_magic = 0;
990 
991 	if (nxgep->nxge_timerid) {
992 		nxge_stop_timer(nxgep, nxgep->nxge_timerid);
993 		nxgep->nxge_timerid = 0;
994 	}
995 
996 	/*
997 	 * If this flag is set, it will affect the Neptune
998 	 * only.
999 	 */
1000 	if ((nxgep->niu_type != N2_NIU) && nxge_peu_reset_enable) {
1001 		nxge_niu_peu_reset(nxgep);
1002 	}
1003 
1004 #if	defined(sun4v)
1005 	if (isLDOMguest(nxgep)) {
1006 		(void) nxge_hio_vr_release(nxgep);
1007 	}
1008 #endif
1009 
1010 	if (nxgep->nxge_hw_p) {
1011 		nxge_uninit_common_dev(nxgep);
1012 		nxgep->nxge_hw_p = NULL;
1013 	}
1014 
1015 #if	defined(sun4v)
1016 	if (nxgep->niu_type == N2_NIU && nxgep->niu_hsvc_available == B_TRUE) {
1017 		(void) hsvc_unregister(&nxgep->niu_hsvc);
1018 		nxgep->niu_hsvc_available = B_FALSE;
1019 	}
1020 #endif
1021 	/*
1022 	 * Stop any further interrupts.
1023 	 */
1024 	nxge_remove_intrs(nxgep);
1025 
1026 	/*
1027 	 * Stop the device and free resources.
1028 	 */
1029 	if (!isLDOMguest(nxgep)) {
1030 		nxge_destroy_dev(nxgep);
1031 	}
1032 
1033 	/*
1034 	 * Tear down the ndd parameters setup.
1035 	 */
1036 	nxge_destroy_param(nxgep);
1037 
1038 	/*
1039 	 * Tear down the kstat setup.
1040 	 */
1041 	nxge_destroy_kstats(nxgep);
1042 
1043 	/*
1044 	 * Free any memory allocated for PHY properties
1045 	 */
1046 	if (nxgep->phy_prop.cnt > 0) {
1047 		KMEM_FREE(nxgep->phy_prop.arr,
1048 		    sizeof (nxge_phy_mdio_val_t) * nxgep->phy_prop.cnt);
1049 		nxgep->phy_prop.cnt = 0;
1050 	}
1051 
1052 	/*
1053 	 * Destroy all mutexes.
1054 	 */
1055 	nxge_destroy_mutexes(nxgep);
1056 
1057 	/*
1058 	 * Remove the list of ndd parameters which
1059 	 * were setup during attach.
1060 	 */
1061 	if (nxgep->dip) {
1062 		NXGE_DEBUG_MSG((nxgep, OBP_CTL,
1063 		    " nxge_unattach: remove all properties"));
1064 
1065 		(void) ddi_prop_remove_all(nxgep->dip);
1066 	}
1067 
1068 #if NXGE_PROPERTY
1069 	nxge_remove_hard_properties(nxgep);
1070 #endif
1071 
1072 	/*
1073 	 * Unmap the register setup.
1074 	 */
1075 	nxge_unmap_regs(nxgep);
1076 
1077 	nxge_fm_fini(nxgep);
1078 
1079 	ddi_soft_state_free(nxge_list, nxgep->instance);
1080 
1081 	NXGE_DEBUG_MSG((NULL, DDI_CTL, "<== nxge_unattach"));
1082 }
1083 
1084 #if defined(sun4v)
1085 int
nxge_hsvc_register(nxge_t * nxgep)1086 nxge_hsvc_register(nxge_t *nxgep)
1087 {
1088 	nxge_status_t status;
1089 	int i, j;
1090 
1091 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hsvc_register"));
1092 	if (nxgep->niu_type != N2_NIU) {
1093 		NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hsvc_register"));
1094 		return (DDI_SUCCESS);
1095 	}
1096 
1097 	/*
1098 	 * Currently, the NIU Hypervisor API supports two major versions:
1099 	 * version 1 and 2.
1100 	 * If Hypervisor introduces a higher major or minor version,
1101 	 * please update NIU_MAJOR_HI and NIU_MINOR_HI accordingly.
1102 	 */
1103 	nxgep->niu_hsvc_available = B_FALSE;
1104 	bcopy(&niu_hsvc, &nxgep->niu_hsvc,
1105 	    sizeof (hsvc_info_t));
1106 
1107 	for (i = NIU_MAJOR_HI; i > 0; i--) {
1108 		nxgep->niu_hsvc.hsvc_major = i;
1109 		for (j = NIU_MINOR_HI; j >= 0; j--) {
1110 			nxgep->niu_hsvc.hsvc_minor = j;
1111 			NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1112 			    "nxge_hsvc_register: %s: negotiating "
1113 			    "hypervisor services revision %d "
1114 			    "group: 0x%lx major: 0x%lx "
1115 			    "minor: 0x%lx",
1116 			    nxgep->niu_hsvc.hsvc_modname,
1117 			    nxgep->niu_hsvc.hsvc_rev,
1118 			    nxgep->niu_hsvc.hsvc_group,
1119 			    nxgep->niu_hsvc.hsvc_major,
1120 			    nxgep->niu_hsvc.hsvc_minor,
1121 			    nxgep->niu_min_ver));
1122 
1123 			if ((status = hsvc_register(&nxgep->niu_hsvc,
1124 			    &nxgep->niu_min_ver)) == 0) {
1125 				/* Use the supported minor */
1126 				nxgep->niu_hsvc.hsvc_minor = nxgep->niu_min_ver;
1127 				NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1128 				    "nxge_hsvc_register: %s: negotiated "
1129 				    "hypervisor services revision %d "
1130 				    "group: 0x%lx major: 0x%lx "
1131 				    "minor: 0x%lx (niu_min_ver 0x%lx)",
1132 				    nxgep->niu_hsvc.hsvc_modname,
1133 				    nxgep->niu_hsvc.hsvc_rev,
1134 				    nxgep->niu_hsvc.hsvc_group,
1135 				    nxgep->niu_hsvc.hsvc_major,
1136 				    nxgep->niu_hsvc.hsvc_minor,
1137 				    nxgep->niu_min_ver));
1138 
1139 				nxgep->niu_hsvc_available = B_TRUE;
1140 				NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1141 				    "<== nxge_hsvc_register: "
1142 				    "NIU Hypervisor service enabled"));
1143 				return (DDI_SUCCESS);
1144 			}
1145 
1146 			NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1147 			    "nxge_hsvc_register: %s: negotiated failed - "
1148 			    "try lower major number "
1149 			    "hypervisor services revision %d "
1150 			    "group: 0x%lx major: 0x%lx minor: 0x%lx "
1151 			    "errno: %d",
1152 			    nxgep->niu_hsvc.hsvc_modname,
1153 			    nxgep->niu_hsvc.hsvc_rev,
1154 			    nxgep->niu_hsvc.hsvc_group,
1155 			    nxgep->niu_hsvc.hsvc_major,
1156 			    nxgep->niu_hsvc.hsvc_minor, status));
1157 		}
1158 	}
1159 
1160 	NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1161 	    "nxge_hsvc_register: %s: cannot negotiate "
1162 	    "hypervisor services revision %d group: 0x%lx "
1163 	    "major: 0x%lx minor: 0x%lx errno: %d",
1164 	    niu_hsvc.hsvc_modname, niu_hsvc.hsvc_rev,
1165 	    niu_hsvc.hsvc_group, niu_hsvc.hsvc_major,
1166 	    niu_hsvc.hsvc_minor, status));
1167 
1168 	NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1169 	    "<== nxge_hsvc_register: Register to NIU Hypervisor failed"));
1170 
1171 	return (DDI_FAILURE);
1172 }
1173 #endif
1174 
1175 static char n2_siu_name[] = "niu";
1176 
1177 static nxge_status_t
nxge_map_regs(p_nxge_t nxgep)1178 nxge_map_regs(p_nxge_t nxgep)
1179 {
1180 	int		ddi_status = DDI_SUCCESS;
1181 	p_dev_regs_t	dev_regs;
1182 	char		buf[MAXPATHLEN + 1];
1183 	char		*devname;
1184 #ifdef	NXGE_DEBUG
1185 	char		*sysname;
1186 #endif
1187 	off_t		regsize;
1188 	nxge_status_t	status = NXGE_OK;
1189 #if !defined(_BIG_ENDIAN)
1190 	off_t pci_offset;
1191 	uint16_t pcie_devctl;
1192 #endif
1193 
1194 	if (isLDOMguest(nxgep)) {
1195 		return (nxge_guest_regs_map(nxgep));
1196 	}
1197 
1198 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_map_regs"));
1199 	nxgep->dev_regs = NULL;
1200 	dev_regs = KMEM_ZALLOC(sizeof (dev_regs_t), KM_SLEEP);
1201 	dev_regs->nxge_regh = NULL;
1202 	dev_regs->nxge_pciregh = NULL;
1203 	dev_regs->nxge_msix_regh = NULL;
1204 	dev_regs->nxge_vir_regh = NULL;
1205 	dev_regs->nxge_vir2_regh = NULL;
1206 	nxgep->niu_type = NIU_TYPE_NONE;
1207 
1208 	devname = ddi_pathname(nxgep->dip, buf);
1209 	ASSERT(strlen(devname) > 0);
1210 	NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1211 	    "nxge_map_regs: pathname devname %s", devname));
1212 
1213 	/*
1214 	 * The driver is running on a N2-NIU system if devname is something
1215 	 * like "/niu@80/network@0"
1216 	 */
1217 	if (strstr(devname, n2_siu_name)) {
1218 		/* N2/NIU */
1219 		nxgep->niu_type = N2_NIU;
1220 		NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1221 		    "nxge_map_regs: N2/NIU devname %s", devname));
1222 		/*
1223 		 * Get function number:
1224 		 *  - N2/NIU: "/niu@80/network@0" and "/niu@80/network@1"
1225 		 */
1226 		nxgep->function_num =
1227 		    (devname[strlen(devname) -1] == '1' ? 1 : 0);
1228 		NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1229 		    "nxge_map_regs: N2/NIU function number %d",
1230 		    nxgep->function_num));
1231 	} else {
1232 		int		*prop_val;
1233 		uint_t		prop_len;
1234 		uint8_t		func_num;
1235 
1236 		if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip,
1237 		    0, "reg",
1238 		    &prop_val, &prop_len) != DDI_PROP_SUCCESS) {
1239 			NXGE_DEBUG_MSG((nxgep, VPD_CTL,
1240 			    "Reg property not found"));
1241 			ddi_status = DDI_FAILURE;
1242 			goto nxge_map_regs_fail0;
1243 
1244 		} else {
1245 			func_num = (prop_val[0] >> 8) & 0x7;
1246 			NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1247 			    "Reg property found: fun # %d",
1248 			    func_num));
1249 			nxgep->function_num = func_num;
1250 			if (isLDOMguest(nxgep)) {
1251 				nxgep->function_num /= 2;
1252 				return (NXGE_OK);
1253 			}
1254 			ddi_prop_free(prop_val);
1255 		}
1256 	}
1257 
1258 	switch (nxgep->niu_type) {
1259 	default:
1260 		(void) ddi_dev_regsize(nxgep->dip, 0, &regsize);
1261 		NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1262 		    "nxge_map_regs: pci config size 0x%x", regsize));
1263 
1264 		ddi_status = ddi_regs_map_setup(nxgep->dip, 0,
1265 		    (caddr_t *)&(dev_regs->nxge_pciregp), 0, 0,
1266 		    &nxge_dev_reg_acc_attr, &dev_regs->nxge_pciregh);
1267 		if (ddi_status != DDI_SUCCESS) {
1268 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1269 			    "ddi_map_regs, nxge bus config regs failed"));
1270 			goto nxge_map_regs_fail0;
1271 		}
1272 		NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1273 		    "nxge_map_reg: PCI config addr 0x%0llx "
1274 		    " handle 0x%0llx", dev_regs->nxge_pciregp,
1275 		    dev_regs->nxge_pciregh));
1276 			/*
1277 			 * IMP IMP
1278 			 * workaround  for bit swapping bug in HW
1279 			 * which ends up in no-snoop = yes
1280 			 * resulting, in DMA not synched properly
1281 			 */
1282 #if !defined(_BIG_ENDIAN)
1283 		/* workarounds for x86 systems */
1284 		pci_offset = 0x80 + PCIE_DEVCTL;
1285 		pcie_devctl = pci_config_get16(dev_regs->nxge_pciregh,
1286 		    pci_offset);
1287 		pcie_devctl &= ~PCIE_DEVCTL_ENABLE_NO_SNOOP;
1288 		pcie_devctl |= PCIE_DEVCTL_RO_EN;
1289 		pci_config_put16(dev_regs->nxge_pciregh, pci_offset,
1290 		    pcie_devctl);
1291 #endif
1292 
1293 		(void) ddi_dev_regsize(nxgep->dip, 1, &regsize);
1294 		NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1295 		    "nxge_map_regs: pio size 0x%x", regsize));
1296 		/* set up the device mapped register */
1297 		ddi_status = ddi_regs_map_setup(nxgep->dip, 1,
1298 		    (caddr_t *)&(dev_regs->nxge_regp), 0, 0,
1299 		    &nxge_dev_reg_acc_attr, &dev_regs->nxge_regh);
1300 		if (ddi_status != DDI_SUCCESS) {
1301 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1302 			    "ddi_map_regs for Neptune global reg failed"));
1303 			goto nxge_map_regs_fail1;
1304 		}
1305 
1306 		/* set up the msi/msi-x mapped register */
1307 		(void) ddi_dev_regsize(nxgep->dip, 2, &regsize);
1308 		NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1309 		    "nxge_map_regs: msix size 0x%x", regsize));
1310 		ddi_status = ddi_regs_map_setup(nxgep->dip, 2,
1311 		    (caddr_t *)&(dev_regs->nxge_msix_regp), 0, 0,
1312 		    &nxge_dev_reg_acc_attr, &dev_regs->nxge_msix_regh);
1313 		if (ddi_status != DDI_SUCCESS) {
1314 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1315 			    "ddi_map_regs for msi reg failed"));
1316 			goto nxge_map_regs_fail2;
1317 		}
1318 
1319 		/* set up the vio region mapped register */
1320 		(void) ddi_dev_regsize(nxgep->dip, 3, &regsize);
1321 		NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1322 		    "nxge_map_regs: vio size 0x%x", regsize));
1323 		ddi_status = ddi_regs_map_setup(nxgep->dip, 3,
1324 		    (caddr_t *)&(dev_regs->nxge_vir_regp), 0, 0,
1325 		    &nxge_dev_reg_acc_attr, &dev_regs->nxge_vir_regh);
1326 
1327 		if (ddi_status != DDI_SUCCESS) {
1328 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1329 			    "ddi_map_regs for nxge vio reg failed"));
1330 			goto nxge_map_regs_fail3;
1331 		}
1332 		nxgep->dev_regs = dev_regs;
1333 
1334 		NPI_PCI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_pciregh);
1335 		NPI_PCI_ADD_HANDLE_SET(nxgep,
1336 		    (npi_reg_ptr_t)dev_regs->nxge_pciregp);
1337 		NPI_MSI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_msix_regh);
1338 		NPI_MSI_ADD_HANDLE_SET(nxgep,
1339 		    (npi_reg_ptr_t)dev_regs->nxge_msix_regp);
1340 
1341 		NPI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh);
1342 		NPI_ADD_HANDLE_SET(nxgep, (npi_reg_ptr_t)dev_regs->nxge_regp);
1343 
1344 		NPI_REG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh);
1345 		NPI_REG_ADD_HANDLE_SET(nxgep,
1346 		    (npi_reg_ptr_t)dev_regs->nxge_regp);
1347 
1348 		NPI_VREG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_vir_regh);
1349 		NPI_VREG_ADD_HANDLE_SET(nxgep,
1350 		    (npi_reg_ptr_t)dev_regs->nxge_vir_regp);
1351 
1352 		break;
1353 
1354 	case N2_NIU:
1355 		NXGE_DEBUG_MSG((nxgep, DDI_CTL, "ddi_map_regs, NIU"));
1356 		/*
1357 		 * Set up the device mapped register (FWARC 2006/556)
1358 		 * (changed back to 1: reg starts at 1!)
1359 		 */
1360 		(void) ddi_dev_regsize(nxgep->dip, 1, &regsize);
1361 		NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1362 		    "nxge_map_regs: dev size 0x%x", regsize));
1363 		ddi_status = ddi_regs_map_setup(nxgep->dip, 1,
1364 		    (caddr_t *)&(dev_regs->nxge_regp), 0, 0,
1365 		    &nxge_dev_reg_acc_attr, &dev_regs->nxge_regh);
1366 
1367 		if (ddi_status != DDI_SUCCESS) {
1368 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1369 			    "ddi_map_regs for N2/NIU, global reg failed "));
1370 			goto nxge_map_regs_fail1;
1371 		}
1372 
1373 		/* set up the first vio region mapped register */
1374 		(void) ddi_dev_regsize(nxgep->dip, 2, &regsize);
1375 		NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1376 		    "nxge_map_regs: vio (1) size 0x%x", regsize));
1377 		ddi_status = ddi_regs_map_setup(nxgep->dip, 2,
1378 		    (caddr_t *)&(dev_regs->nxge_vir_regp), 0, 0,
1379 		    &nxge_dev_reg_acc_attr, &dev_regs->nxge_vir_regh);
1380 
1381 		if (ddi_status != DDI_SUCCESS) {
1382 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1383 			    "ddi_map_regs for nxge vio reg failed"));
1384 			goto nxge_map_regs_fail2;
1385 		}
1386 		/* set up the second vio region mapped register */
1387 		(void) ddi_dev_regsize(nxgep->dip, 3, &regsize);
1388 		NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1389 		    "nxge_map_regs: vio (3) size 0x%x", regsize));
1390 		ddi_status = ddi_regs_map_setup(nxgep->dip, 3,
1391 		    (caddr_t *)&(dev_regs->nxge_vir2_regp), 0, 0,
1392 		    &nxge_dev_reg_acc_attr, &dev_regs->nxge_vir2_regh);
1393 
1394 		if (ddi_status != DDI_SUCCESS) {
1395 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1396 			    "ddi_map_regs for nxge vio2 reg failed"));
1397 			goto nxge_map_regs_fail3;
1398 		}
1399 		nxgep->dev_regs = dev_regs;
1400 
1401 		NPI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh);
1402 		NPI_ADD_HANDLE_SET(nxgep, (npi_reg_ptr_t)dev_regs->nxge_regp);
1403 
1404 		NPI_REG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh);
1405 		NPI_REG_ADD_HANDLE_SET(nxgep,
1406 		    (npi_reg_ptr_t)dev_regs->nxge_regp);
1407 
1408 		NPI_VREG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_vir_regh);
1409 		NPI_VREG_ADD_HANDLE_SET(nxgep,
1410 		    (npi_reg_ptr_t)dev_regs->nxge_vir_regp);
1411 
1412 		NPI_V2REG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_vir2_regh);
1413 		NPI_V2REG_ADD_HANDLE_SET(nxgep,
1414 		    (npi_reg_ptr_t)dev_regs->nxge_vir2_regp);
1415 
1416 		break;
1417 	}
1418 
1419 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "nxge_map_reg: hardware addr 0x%0llx "
1420 	    " handle 0x%0llx", dev_regs->nxge_regp, dev_regs->nxge_regh));
1421 
1422 	goto nxge_map_regs_exit;
1423 nxge_map_regs_fail3:
1424 	if (dev_regs->nxge_msix_regh) {
1425 		ddi_regs_map_free(&dev_regs->nxge_msix_regh);
1426 	}
1427 	if (dev_regs->nxge_vir_regh) {
1428 		ddi_regs_map_free(&dev_regs->nxge_regh);
1429 	}
1430 nxge_map_regs_fail2:
1431 	if (dev_regs->nxge_regh) {
1432 		ddi_regs_map_free(&dev_regs->nxge_regh);
1433 	}
1434 nxge_map_regs_fail1:
1435 	if (dev_regs->nxge_pciregh) {
1436 		ddi_regs_map_free(&dev_regs->nxge_pciregh);
1437 	}
1438 nxge_map_regs_fail0:
1439 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "Freeing register set memory"));
1440 	kmem_free(dev_regs, sizeof (dev_regs_t));
1441 
1442 nxge_map_regs_exit:
1443 	if (ddi_status != DDI_SUCCESS)
1444 		status |= (NXGE_ERROR | NXGE_DDI_FAILED);
1445 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_map_regs"));
1446 	return (status);
1447 }
1448 
1449 static void
nxge_unmap_regs(p_nxge_t nxgep)1450 nxge_unmap_regs(p_nxge_t nxgep)
1451 {
1452 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_unmap_regs"));
1453 
1454 	if (isLDOMguest(nxgep)) {
1455 		nxge_guest_regs_map_free(nxgep);
1456 		return;
1457 	}
1458 
1459 	if (nxgep->dev_regs) {
1460 		if (nxgep->dev_regs->nxge_pciregh) {
1461 			NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1462 			    "==> nxge_unmap_regs: bus"));
1463 			ddi_regs_map_free(&nxgep->dev_regs->nxge_pciregh);
1464 			nxgep->dev_regs->nxge_pciregh = NULL;
1465 		}
1466 		if (nxgep->dev_regs->nxge_regh) {
1467 			NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1468 			    "==> nxge_unmap_regs: device registers"));
1469 			ddi_regs_map_free(&nxgep->dev_regs->nxge_regh);
1470 			nxgep->dev_regs->nxge_regh = NULL;
1471 		}
1472 		if (nxgep->dev_regs->nxge_msix_regh) {
1473 			NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1474 			    "==> nxge_unmap_regs: device interrupts"));
1475 			ddi_regs_map_free(&nxgep->dev_regs->nxge_msix_regh);
1476 			nxgep->dev_regs->nxge_msix_regh = NULL;
1477 		}
1478 		if (nxgep->dev_regs->nxge_vir_regh) {
1479 			NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1480 			    "==> nxge_unmap_regs: vio region"));
1481 			ddi_regs_map_free(&nxgep->dev_regs->nxge_vir_regh);
1482 			nxgep->dev_regs->nxge_vir_regh = NULL;
1483 		}
1484 		if (nxgep->dev_regs->nxge_vir2_regh) {
1485 			NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1486 			    "==> nxge_unmap_regs: vio2 region"));
1487 			ddi_regs_map_free(&nxgep->dev_regs->nxge_vir2_regh);
1488 			nxgep->dev_regs->nxge_vir2_regh = NULL;
1489 		}
1490 
1491 		kmem_free(nxgep->dev_regs, sizeof (dev_regs_t));
1492 		nxgep->dev_regs = NULL;
1493 	}
1494 
1495 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_unmap_regs"));
1496 }
1497 
1498 static nxge_status_t
nxge_setup_mutexes(p_nxge_t nxgep)1499 nxge_setup_mutexes(p_nxge_t nxgep)
1500 {
1501 	int ddi_status = DDI_SUCCESS;
1502 	nxge_status_t status = NXGE_OK;
1503 	nxge_classify_t *classify_ptr;
1504 	int partition;
1505 
1506 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_setup_mutexes"));
1507 
1508 	/*
1509 	 * Get the interrupt cookie so the mutexes can be
1510 	 * Initialized.
1511 	 */
1512 	if (isLDOMguest(nxgep)) {
1513 		nxgep->interrupt_cookie = 0;
1514 	} else {
1515 		ddi_status = ddi_get_iblock_cookie(nxgep->dip, 0,
1516 		    &nxgep->interrupt_cookie);
1517 
1518 		if (ddi_status != DDI_SUCCESS) {
1519 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1520 			    "<== nxge_setup_mutexes: failed 0x%x",
1521 			    ddi_status));
1522 			goto nxge_setup_mutexes_exit;
1523 		}
1524 	}
1525 
1526 	cv_init(&nxgep->poll_cv, NULL, CV_DRIVER, NULL);
1527 	MUTEX_INIT(&nxgep->poll_lock, NULL,
1528 	    MUTEX_DRIVER, (void *)nxgep->interrupt_cookie);
1529 
1530 	/*
1531 	 * Initialize mutexes for this device.
1532 	 */
1533 	MUTEX_INIT(nxgep->genlock, NULL,
1534 	    MUTEX_DRIVER, (void *)nxgep->interrupt_cookie);
1535 	MUTEX_INIT(&nxgep->ouraddr_lock, NULL,
1536 	    MUTEX_DRIVER, (void *)nxgep->interrupt_cookie);
1537 	MUTEX_INIT(&nxgep->mif_lock, NULL,
1538 	    MUTEX_DRIVER, (void *)nxgep->interrupt_cookie);
1539 	MUTEX_INIT(&nxgep->group_lock, NULL,
1540 	    MUTEX_DRIVER, (void *)nxgep->interrupt_cookie);
1541 	RW_INIT(&nxgep->filter_lock, NULL,
1542 	    RW_DRIVER, (void *)nxgep->interrupt_cookie);
1543 
1544 	classify_ptr = &nxgep->classifier;
1545 		/*
1546 		 * FFLP Mutexes are never used in interrupt context
1547 		 * as fflp operation can take very long time to
1548 		 * complete and hence not suitable to invoke from interrupt
1549 		 * handlers.
1550 		 */
1551 	MUTEX_INIT(&classify_ptr->tcam_lock, NULL,
1552 	    NXGE_MUTEX_DRIVER, (void *)nxgep->interrupt_cookie);
1553 	if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) {
1554 		MUTEX_INIT(&classify_ptr->fcram_lock, NULL,
1555 		    NXGE_MUTEX_DRIVER, (void *)nxgep->interrupt_cookie);
1556 		for (partition = 0; partition < MAX_PARTITION; partition++) {
1557 			MUTEX_INIT(&classify_ptr->hash_lock[partition], NULL,
1558 			    NXGE_MUTEX_DRIVER, (void *)nxgep->interrupt_cookie);
1559 		}
1560 	}
1561 
1562 nxge_setup_mutexes_exit:
1563 	NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1564 	    "<== nxge_setup_mutexes status = %x", status));
1565 
1566 	if (ddi_status != DDI_SUCCESS)
1567 		status |= (NXGE_ERROR | NXGE_DDI_FAILED);
1568 
1569 	return (status);
1570 }
1571 
1572 static void
nxge_destroy_mutexes(p_nxge_t nxgep)1573 nxge_destroy_mutexes(p_nxge_t nxgep)
1574 {
1575 	int partition;
1576 	nxge_classify_t *classify_ptr;
1577 
1578 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_mutexes"));
1579 	RW_DESTROY(&nxgep->filter_lock);
1580 	MUTEX_DESTROY(&nxgep->group_lock);
1581 	MUTEX_DESTROY(&nxgep->mif_lock);
1582 	MUTEX_DESTROY(&nxgep->ouraddr_lock);
1583 	MUTEX_DESTROY(nxgep->genlock);
1584 
1585 	classify_ptr = &nxgep->classifier;
1586 	MUTEX_DESTROY(&classify_ptr->tcam_lock);
1587 
1588 	/* Destroy all polling resources. */
1589 	MUTEX_DESTROY(&nxgep->poll_lock);
1590 	cv_destroy(&nxgep->poll_cv);
1591 
1592 	/* free data structures, based on HW type */
1593 	if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) {
1594 		MUTEX_DESTROY(&classify_ptr->fcram_lock);
1595 		for (partition = 0; partition < MAX_PARTITION; partition++) {
1596 			MUTEX_DESTROY(&classify_ptr->hash_lock[partition]);
1597 		}
1598 	}
1599 
1600 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_mutexes"));
1601 }
1602 
1603 nxge_status_t
nxge_init(p_nxge_t nxgep)1604 nxge_init(p_nxge_t nxgep)
1605 {
1606 	nxge_status_t status = NXGE_OK;
1607 
1608 	NXGE_DEBUG_MSG((nxgep, STR_CTL, "==> nxge_init"));
1609 
1610 	if (nxgep->drv_state & STATE_HW_INITIALIZED) {
1611 		return (status);
1612 	}
1613 
1614 	/*
1615 	 * Allocate system memory for the receive/transmit buffer blocks
1616 	 * and receive/transmit descriptor rings.
1617 	 */
1618 	status = nxge_alloc_mem_pool(nxgep);
1619 	if (status != NXGE_OK) {
1620 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "alloc mem failed\n"));
1621 		goto nxge_init_fail1;
1622 	}
1623 
1624 	if (!isLDOMguest(nxgep)) {
1625 		/*
1626 		 * Initialize and enable the TXC registers.
1627 		 * (Globally enable the Tx controller,
1628 		 *  enable the port, configure the dma channel bitmap,
1629 		 *  configure the max burst size).
1630 		 */
1631 		status = nxge_txc_init(nxgep);
1632 		if (status != NXGE_OK) {
1633 			NXGE_ERROR_MSG((nxgep,
1634 			    NXGE_ERR_CTL, "init txc failed\n"));
1635 			goto nxge_init_fail2;
1636 		}
1637 	}
1638 
1639 	/*
1640 	 * Initialize and enable TXDMA channels.
1641 	 */
1642 	status = nxge_init_txdma_channels(nxgep);
1643 	if (status != NXGE_OK) {
1644 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init txdma failed\n"));
1645 		goto nxge_init_fail3;
1646 	}
1647 
1648 	/*
1649 	 * Initialize and enable RXDMA channels.
1650 	 */
1651 	status = nxge_init_rxdma_channels(nxgep);
1652 	if (status != NXGE_OK) {
1653 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init rxdma failed\n"));
1654 		goto nxge_init_fail4;
1655 	}
1656 
1657 	/*
1658 	 * The guest domain is now done.
1659 	 */
1660 	if (isLDOMguest(nxgep)) {
1661 		nxgep->drv_state |= STATE_HW_INITIALIZED;
1662 		goto nxge_init_exit;
1663 	}
1664 
1665 	/*
1666 	 * Initialize TCAM and FCRAM (Neptune).
1667 	 */
1668 	status = nxge_classify_init(nxgep);
1669 	if (status != NXGE_OK) {
1670 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init classify failed\n"));
1671 		goto nxge_init_fail5;
1672 	}
1673 
1674 	/*
1675 	 * Initialize ZCP
1676 	 */
1677 	status = nxge_zcp_init(nxgep);
1678 	if (status != NXGE_OK) {
1679 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init ZCP failed\n"));
1680 		goto nxge_init_fail5;
1681 	}
1682 
1683 	/*
1684 	 * Initialize IPP.
1685 	 */
1686 	status = nxge_ipp_init(nxgep);
1687 	if (status != NXGE_OK) {
1688 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init IPP failed\n"));
1689 		goto nxge_init_fail5;
1690 	}
1691 
1692 	/*
1693 	 * Initialize the MAC block.
1694 	 */
1695 	status = nxge_mac_init(nxgep);
1696 	if (status != NXGE_OK) {
1697 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init MAC failed\n"));
1698 		goto nxge_init_fail5;
1699 	}
1700 
1701 	/*
1702 	 * Enable the interrrupts for DDI.
1703 	 */
1704 	nxge_intrs_enable(nxgep);
1705 
1706 	nxgep->drv_state |= STATE_HW_INITIALIZED;
1707 
1708 	goto nxge_init_exit;
1709 
1710 nxge_init_fail5:
1711 	nxge_uninit_rxdma_channels(nxgep);
1712 nxge_init_fail4:
1713 	nxge_uninit_txdma_channels(nxgep);
1714 nxge_init_fail3:
1715 	if (!isLDOMguest(nxgep)) {
1716 		(void) nxge_txc_uninit(nxgep);
1717 	}
1718 nxge_init_fail2:
1719 	nxge_free_mem_pool(nxgep);
1720 nxge_init_fail1:
1721 	NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1722 	    "<== nxge_init status (failed) = 0x%08x", status));
1723 	return (status);
1724 
1725 nxge_init_exit:
1726 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_init status = 0x%08x",
1727 	    status));
1728 	return (status);
1729 }
1730 
1731 
1732 timeout_id_t
nxge_start_timer(p_nxge_t nxgep,fptrv_t func,int msec)1733 nxge_start_timer(p_nxge_t nxgep, fptrv_t func, int msec)
1734 {
1735 	if ((nxgep->suspended == 0) || (nxgep->suspended == DDI_RESUME)) {
1736 		return (timeout(func, (caddr_t)nxgep,
1737 		    drv_usectohz(1000 * msec)));
1738 	}
1739 	return (NULL);
1740 }
1741 
1742 /*ARGSUSED*/
1743 void
nxge_stop_timer(p_nxge_t nxgep,timeout_id_t timerid)1744 nxge_stop_timer(p_nxge_t nxgep, timeout_id_t timerid)
1745 {
1746 	if (timerid) {
1747 		(void) untimeout(timerid);
1748 	}
1749 }
1750 
1751 void
nxge_uninit(p_nxge_t nxgep)1752 nxge_uninit(p_nxge_t nxgep)
1753 {
1754 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_uninit"));
1755 
1756 	if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) {
1757 		NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1758 		    "==> nxge_uninit: not initialized"));
1759 		NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1760 		    "<== nxge_uninit"));
1761 		return;
1762 	}
1763 
1764 	if (!isLDOMguest(nxgep)) {
1765 		/*
1766 		 * Reset the receive MAC side.
1767 		 */
1768 		(void) nxge_rx_mac_disable(nxgep);
1769 
1770 		/*
1771 		 * Drain the IPP.
1772 		 */
1773 		(void) nxge_ipp_drain(nxgep);
1774 	}
1775 
1776 	/* stop timer */
1777 	if (nxgep->nxge_timerid) {
1778 		nxge_stop_timer(nxgep, nxgep->nxge_timerid);
1779 		nxgep->nxge_timerid = 0;
1780 	}
1781 
1782 	(void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP);
1783 	(void) nxge_intr_hw_disable(nxgep);
1784 
1785 
1786 	/* Disable and soft reset the IPP */
1787 	if (!isLDOMguest(nxgep))
1788 		(void) nxge_ipp_disable(nxgep);
1789 
1790 	/* Free classification resources */
1791 	(void) nxge_classify_uninit(nxgep);
1792 
1793 	/*
1794 	 * Reset the transmit/receive DMA side.
1795 	 */
1796 	(void) nxge_txdma_hw_mode(nxgep, NXGE_DMA_STOP);
1797 	(void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_STOP);
1798 
1799 	nxge_uninit_txdma_channels(nxgep);
1800 	nxge_uninit_rxdma_channels(nxgep);
1801 
1802 	/*
1803 	 * Reset the transmit MAC side.
1804 	 */
1805 	(void) nxge_tx_mac_disable(nxgep);
1806 
1807 	nxge_free_mem_pool(nxgep);
1808 
1809 	/*
1810 	 * Start the timer if the reset flag is not set.
1811 	 * If this reset flag is set, the link monitor
1812 	 * will not be started in order to stop furthur bus
1813 	 * activities coming from this interface.
1814 	 * The driver will start the monitor function
1815 	 * if the interface was initialized again later.
1816 	 */
1817 	if (!nxge_peu_reset_enable) {
1818 		(void) nxge_link_monitor(nxgep, LINK_MONITOR_START);
1819 	}
1820 
1821 	nxgep->drv_state &= ~STATE_HW_INITIALIZED;
1822 
1823 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_uninit: "
1824 	    "nxge_mblks_pending %d", nxge_mblks_pending));
1825 }
1826 
1827 void
nxge_get64(p_nxge_t nxgep,p_mblk_t mp)1828 nxge_get64(p_nxge_t nxgep, p_mblk_t mp)
1829 {
1830 	uint64_t	reg;
1831 	uint64_t	regdata;
1832 	int		i, retry;
1833 
1834 	bcopy((char *)mp->b_rptr, (char *)&reg, sizeof (uint64_t));
1835 	regdata = 0;
1836 	retry = 1;
1837 
1838 	for (i = 0; i < retry; i++) {
1839 		NXGE_REG_RD64(nxgep->npi_handle, reg, &regdata);
1840 	}
1841 	bcopy((char *)&regdata, (char *)mp->b_rptr, sizeof (uint64_t));
1842 }
1843 
1844 void
nxge_put64(p_nxge_t nxgep,p_mblk_t mp)1845 nxge_put64(p_nxge_t nxgep, p_mblk_t mp)
1846 {
1847 	uint64_t	reg;
1848 	uint64_t	buf[2];
1849 
1850 	bcopy((char *)mp->b_rptr, (char *)&buf[0], 2 * sizeof (uint64_t));
1851 	reg = buf[0];
1852 
1853 	NXGE_NPI_PIO_WRITE64(nxgep->npi_handle, reg, buf[1]);
1854 }
1855 
1856 /*ARGSUSED*/
1857 /*VARARGS*/
1858 void
nxge_debug_msg(p_nxge_t nxgep,uint64_t level,char * fmt,...)1859 nxge_debug_msg(p_nxge_t nxgep, uint64_t level, char *fmt, ...)
1860 {
1861 	char msg_buffer[1048];
1862 	char prefix_buffer[32];
1863 	int instance;
1864 	uint64_t debug_level;
1865 	int cmn_level = CE_CONT;
1866 	va_list ap;
1867 
1868 	if (nxgep && nxgep->nxge_debug_level != nxge_debug_level) {
1869 		/* In case a developer has changed nxge_debug_level. */
1870 		if (nxgep->nxge_debug_level != nxge_debug_level)
1871 			nxgep->nxge_debug_level = nxge_debug_level;
1872 	}
1873 
1874 	debug_level = (nxgep == NULL) ? nxge_debug_level :
1875 	    nxgep->nxge_debug_level;
1876 
1877 	if ((level & debug_level) ||
1878 	    (level == NXGE_NOTE) ||
1879 	    (level == NXGE_ERR_CTL)) {
1880 		/* do the msg processing */
1881 		MUTEX_ENTER(&nxgedebuglock);
1882 
1883 		if ((level & NXGE_NOTE)) {
1884 			cmn_level = CE_NOTE;
1885 		}
1886 
1887 		if (level & NXGE_ERR_CTL) {
1888 			cmn_level = CE_WARN;
1889 		}
1890 
1891 		va_start(ap, fmt);
1892 		(void) vsprintf(msg_buffer, fmt, ap);
1893 		va_end(ap);
1894 		if (nxgep == NULL) {
1895 			instance = -1;
1896 			(void) sprintf(prefix_buffer, "%s :", "nxge");
1897 		} else {
1898 			instance = nxgep->instance;
1899 			(void) sprintf(prefix_buffer,
1900 			    "%s%d :", "nxge", instance);
1901 		}
1902 
1903 		MUTEX_EXIT(&nxgedebuglock);
1904 		cmn_err(cmn_level, "!%s %s\n",
1905 		    prefix_buffer, msg_buffer);
1906 
1907 	}
1908 }
1909 
1910 char *
nxge_dump_packet(char * addr,int size)1911 nxge_dump_packet(char *addr, int size)
1912 {
1913 	uchar_t *ap = (uchar_t *)addr;
1914 	int i;
1915 	static char etherbuf[1024];
1916 	char *cp = etherbuf;
1917 	char digits[] = "0123456789abcdef";
1918 
1919 	if (!size)
1920 		size = 60;
1921 
1922 	if (size > MAX_DUMP_SZ) {
1923 		/* Dump the leading bytes */
1924 		for (i = 0; i < MAX_DUMP_SZ/2; i++) {
1925 			if (*ap > 0x0f)
1926 				*cp++ = digits[*ap >> 4];
1927 			*cp++ = digits[*ap++ & 0xf];
1928 			*cp++ = ':';
1929 		}
1930 		for (i = 0; i < 20; i++)
1931 			*cp++ = '.';
1932 		/* Dump the last MAX_DUMP_SZ/2 bytes */
1933 		ap = (uchar_t *)(addr + (size - MAX_DUMP_SZ/2));
1934 		for (i = 0; i < MAX_DUMP_SZ/2; i++) {
1935 			if (*ap > 0x0f)
1936 				*cp++ = digits[*ap >> 4];
1937 			*cp++ = digits[*ap++ & 0xf];
1938 			*cp++ = ':';
1939 		}
1940 	} else {
1941 		for (i = 0; i < size; i++) {
1942 			if (*ap > 0x0f)
1943 				*cp++ = digits[*ap >> 4];
1944 			*cp++ = digits[*ap++ & 0xf];
1945 			*cp++ = ':';
1946 		}
1947 	}
1948 	*--cp = 0;
1949 	return (etherbuf);
1950 }
1951 
1952 #ifdef	NXGE_DEBUG
1953 static void
nxge_test_map_regs(p_nxge_t nxgep)1954 nxge_test_map_regs(p_nxge_t nxgep)
1955 {
1956 	ddi_acc_handle_t cfg_handle;
1957 	p_pci_cfg_t	cfg_ptr;
1958 	ddi_acc_handle_t dev_handle;
1959 	char		*dev_ptr;
1960 	ddi_acc_handle_t pci_config_handle;
1961 	uint32_t	regval;
1962 	int		i;
1963 
1964 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_test_map_regs"));
1965 
1966 	dev_handle = nxgep->dev_regs->nxge_regh;
1967 	dev_ptr = (char *)nxgep->dev_regs->nxge_regp;
1968 
1969 	if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) {
1970 		cfg_handle = nxgep->dev_regs->nxge_pciregh;
1971 		cfg_ptr = (void *)nxgep->dev_regs->nxge_pciregp;
1972 
1973 		NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1974 		    "Neptune PCI regp cfg_ptr 0x%llx", (char *)cfg_ptr));
1975 		NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1976 		    "Neptune PCI cfg_ptr vendor id ptr 0x%llx",
1977 		    &cfg_ptr->vendorid));
1978 		NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1979 		    "\tvendorid 0x%x devid 0x%x",
1980 		    NXGE_PIO_READ16(cfg_handle, &cfg_ptr->vendorid, 0),
1981 		    NXGE_PIO_READ16(cfg_handle, &cfg_ptr->devid,    0)));
1982 		NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1983 		    "PCI BAR: base 0x%x base14 0x%x base 18 0x%x "
1984 		    "bar1c 0x%x",
1985 		    NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base,	  0),
1986 		    NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base14, 0),
1987 		    NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base18, 0),
1988 		    NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base1c, 0)));
1989 		NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1990 		    "\nNeptune PCI BAR: base20 0x%x base24 0x%x "
1991 		    "base 28 0x%x bar2c 0x%x\n",
1992 		    NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base20, 0),
1993 		    NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base24, 0),
1994 		    NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base28, 0),
1995 		    NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base2c, 0)));
1996 		NXGE_DEBUG_MSG((nxgep, DDI_CTL,
1997 		    "\nNeptune PCI BAR: base30 0x%x\n",
1998 		    NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base30, 0)));
1999 
2000 		cfg_handle = nxgep->dev_regs->nxge_pciregh;
2001 		cfg_ptr = (void *)nxgep->dev_regs->nxge_pciregp;
2002 		NXGE_DEBUG_MSG((nxgep, DDI_CTL,
2003 		    "first  0x%llx second 0x%llx third 0x%llx "
2004 		    "last 0x%llx ",
2005 		    NXGE_PIO_READ64(dev_handle,
2006 		    (uint64_t *)(dev_ptr + 0),	0),
2007 		    NXGE_PIO_READ64(dev_handle,
2008 		    (uint64_t *)(dev_ptr + 8),	0),
2009 		    NXGE_PIO_READ64(dev_handle,
2010 		    (uint64_t *)(dev_ptr + 16), 0),
2011 		    NXGE_PIO_READ64(cfg_handle,
2012 		    (uint64_t *)(dev_ptr + 24), 0)));
2013 	}
2014 }
2015 
2016 #endif
2017 
2018 static void
nxge_suspend(p_nxge_t nxgep)2019 nxge_suspend(p_nxge_t nxgep)
2020 {
2021 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_suspend"));
2022 
2023 	nxge_intrs_disable(nxgep);
2024 	nxge_destroy_dev(nxgep);
2025 
2026 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_suspend"));
2027 }
2028 
2029 static nxge_status_t
nxge_resume(p_nxge_t nxgep)2030 nxge_resume(p_nxge_t nxgep)
2031 {
2032 	nxge_status_t status = NXGE_OK;
2033 
2034 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_resume"));
2035 
2036 	nxgep->suspended = DDI_RESUME;
2037 	(void) nxge_link_monitor(nxgep, LINK_MONITOR_START);
2038 	(void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_START);
2039 	(void) nxge_txdma_hw_mode(nxgep, NXGE_DMA_START);
2040 	(void) nxge_rx_mac_enable(nxgep);
2041 	(void) nxge_tx_mac_enable(nxgep);
2042 	nxge_intrs_enable(nxgep);
2043 	nxgep->suspended = 0;
2044 
2045 	NXGE_DEBUG_MSG((nxgep, DDI_CTL,
2046 	    "<== nxge_resume status = 0x%x", status));
2047 	return (status);
2048 }
2049 
2050 static nxge_status_t
nxge_setup_dev(p_nxge_t nxgep)2051 nxge_setup_dev(p_nxge_t nxgep)
2052 {
2053 	nxge_status_t	status = NXGE_OK;
2054 
2055 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_setup_dev port %d",
2056 	    nxgep->mac.portnum));
2057 
2058 	status = nxge_link_init(nxgep);
2059 
2060 	if (fm_check_acc_handle(nxgep->dev_regs->nxge_regh) != DDI_FM_OK) {
2061 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2062 		    "port%d Bad register acc handle", nxgep->mac.portnum));
2063 		status = NXGE_ERROR;
2064 	}
2065 
2066 	if (status != NXGE_OK) {
2067 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2068 		    " nxge_setup_dev status "
2069 		    "(xcvr init 0x%08x)", status));
2070 		goto nxge_setup_dev_exit;
2071 	}
2072 
2073 nxge_setup_dev_exit:
2074 	NXGE_DEBUG_MSG((nxgep, DDI_CTL,
2075 	    "<== nxge_setup_dev port %d status = 0x%08x",
2076 	    nxgep->mac.portnum, status));
2077 
2078 	return (status);
2079 }
2080 
2081 static void
nxge_destroy_dev(p_nxge_t nxgep)2082 nxge_destroy_dev(p_nxge_t nxgep)
2083 {
2084 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_dev"));
2085 
2086 	(void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP);
2087 
2088 	(void) nxge_hw_stop(nxgep);
2089 
2090 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_dev"));
2091 }
2092 
2093 static nxge_status_t
nxge_setup_system_dma_pages(p_nxge_t nxgep)2094 nxge_setup_system_dma_pages(p_nxge_t nxgep)
2095 {
2096 	int			ddi_status = DDI_SUCCESS;
2097 	uint_t			count;
2098 	ddi_dma_cookie_t	cookie;
2099 	uint_t			iommu_pagesize;
2100 	nxge_status_t		status = NXGE_OK;
2101 
2102 	NXGE_ERROR_MSG((nxgep, DDI_CTL, "==> nxge_setup_system_dma_pages"));
2103 	nxgep->sys_page_sz = ddi_ptob(nxgep->dip, (ulong_t)1);
2104 	if (nxgep->niu_type != N2_NIU) {
2105 		iommu_pagesize = dvma_pagesize(nxgep->dip);
2106 		NXGE_DEBUG_MSG((nxgep, DDI_CTL,
2107 		    " nxge_setup_system_dma_pages: page %d (ddi_ptob %d) "
2108 		    " default_block_size %d iommu_pagesize %d",
2109 		    nxgep->sys_page_sz,
2110 		    ddi_ptob(nxgep->dip, (ulong_t)1),
2111 		    nxgep->rx_default_block_size,
2112 		    iommu_pagesize));
2113 
2114 		if (iommu_pagesize != 0) {
2115 			if (nxgep->sys_page_sz == iommu_pagesize) {
2116 				if (iommu_pagesize > 0x4000)
2117 					nxgep->sys_page_sz = 0x4000;
2118 			} else {
2119 				if (nxgep->sys_page_sz > iommu_pagesize)
2120 					nxgep->sys_page_sz = iommu_pagesize;
2121 			}
2122 		}
2123 	}
2124 	nxgep->sys_page_mask = ~(nxgep->sys_page_sz - 1);
2125 	NXGE_DEBUG_MSG((nxgep, DDI_CTL,
2126 	    "==> nxge_setup_system_dma_pages: page %d (ddi_ptob %d) "
2127 	    "default_block_size %d page mask %d",
2128 	    nxgep->sys_page_sz,
2129 	    ddi_ptob(nxgep->dip, (ulong_t)1),
2130 	    nxgep->rx_default_block_size,
2131 	    nxgep->sys_page_mask));
2132 
2133 
2134 	switch (nxgep->sys_page_sz) {
2135 	default:
2136 		nxgep->sys_page_sz = 0x1000;
2137 		nxgep->sys_page_mask = ~(nxgep->sys_page_sz - 1);
2138 		nxgep->rx_default_block_size = 0x1000;
2139 		nxgep->rx_bksize_code = RBR_BKSIZE_4K;
2140 		break;
2141 	case 0x1000:
2142 		nxgep->rx_default_block_size = 0x1000;
2143 		nxgep->rx_bksize_code = RBR_BKSIZE_4K;
2144 		break;
2145 	case 0x2000:
2146 		nxgep->rx_default_block_size = 0x2000;
2147 		nxgep->rx_bksize_code = RBR_BKSIZE_8K;
2148 		break;
2149 	case 0x4000:
2150 		nxgep->rx_default_block_size = 0x4000;
2151 		nxgep->rx_bksize_code = RBR_BKSIZE_16K;
2152 		break;
2153 	case 0x8000:
2154 		nxgep->rx_default_block_size = 0x8000;
2155 		nxgep->rx_bksize_code = RBR_BKSIZE_32K;
2156 		break;
2157 	}
2158 
2159 #ifndef USE_RX_BIG_BUF
2160 	nxge_rx_dma_attr.dma_attr_align = nxgep->sys_page_sz;
2161 #else
2162 		nxgep->rx_default_block_size = 0x2000;
2163 		nxgep->rx_bksize_code = RBR_BKSIZE_8K;
2164 #endif
2165 	/*
2166 	 * Get the system DMA burst size.
2167 	 */
2168 	ddi_status = ddi_dma_alloc_handle(nxgep->dip, &nxge_tx_dma_attr,
2169 	    DDI_DMA_DONTWAIT, 0,
2170 	    &nxgep->dmasparehandle);
2171 	if (ddi_status != DDI_SUCCESS) {
2172 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2173 		    "ddi_dma_alloc_handle: failed "
2174 		    " status 0x%x", ddi_status));
2175 		goto nxge_get_soft_properties_exit;
2176 	}
2177 
2178 	ddi_status = ddi_dma_addr_bind_handle(nxgep->dmasparehandle, NULL,
2179 	    (caddr_t)nxgep->dmasparehandle,
2180 	    sizeof (nxgep->dmasparehandle),
2181 	    DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
2182 	    DDI_DMA_DONTWAIT, 0,
2183 	    &cookie, &count);
2184 	if (ddi_status != DDI_DMA_MAPPED) {
2185 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2186 		    "Binding spare handle to find system"
2187 		    " burstsize failed."));
2188 		ddi_status = DDI_FAILURE;
2189 		goto nxge_get_soft_properties_fail1;
2190 	}
2191 
2192 	nxgep->sys_burst_sz = ddi_dma_burstsizes(nxgep->dmasparehandle);
2193 	(void) ddi_dma_unbind_handle(nxgep->dmasparehandle);
2194 
2195 nxge_get_soft_properties_fail1:
2196 	ddi_dma_free_handle(&nxgep->dmasparehandle);
2197 
2198 nxge_get_soft_properties_exit:
2199 
2200 	if (ddi_status != DDI_SUCCESS)
2201 		status |= (NXGE_ERROR | NXGE_DDI_FAILED);
2202 
2203 	NXGE_DEBUG_MSG((nxgep, DDI_CTL,
2204 	    "<== nxge_setup_system_dma_pages status = 0x%08x", status));
2205 	return (status);
2206 }
2207 
2208 static nxge_status_t
nxge_alloc_mem_pool(p_nxge_t nxgep)2209 nxge_alloc_mem_pool(p_nxge_t nxgep)
2210 {
2211 	nxge_status_t	status = NXGE_OK;
2212 
2213 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_alloc_mem_pool"));
2214 
2215 	status = nxge_alloc_rx_mem_pool(nxgep);
2216 	if (status != NXGE_OK) {
2217 		return (NXGE_ERROR);
2218 	}
2219 
2220 	status = nxge_alloc_tx_mem_pool(nxgep);
2221 	if (status != NXGE_OK) {
2222 		nxge_free_rx_mem_pool(nxgep);
2223 		return (NXGE_ERROR);
2224 	}
2225 
2226 	NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_alloc_mem_pool"));
2227 	return (NXGE_OK);
2228 }
2229 
2230 static void
nxge_free_mem_pool(p_nxge_t nxgep)2231 nxge_free_mem_pool(p_nxge_t nxgep)
2232 {
2233 	NXGE_DEBUG_MSG((nxgep, MEM_CTL, "==> nxge_free_mem_pool"));
2234 
2235 	nxge_free_rx_mem_pool(nxgep);
2236 	nxge_free_tx_mem_pool(nxgep);
2237 
2238 	NXGE_DEBUG_MSG((nxgep, MEM_CTL, "<== nxge_free_mem_pool"));
2239 }
2240 
2241 nxge_status_t
nxge_alloc_rx_mem_pool(p_nxge_t nxgep)2242 nxge_alloc_rx_mem_pool(p_nxge_t nxgep)
2243 {
2244 	uint32_t		rdc_max;
2245 	p_nxge_dma_pt_cfg_t	p_all_cfgp;
2246 	p_nxge_hw_pt_cfg_t	p_cfgp;
2247 	p_nxge_dma_pool_t	dma_poolp;
2248 	p_nxge_dma_common_t	*dma_buf_p;
2249 	p_nxge_dma_pool_t	dma_cntl_poolp;
2250 	p_nxge_dma_common_t	*dma_cntl_p;
2251 	uint32_t		*num_chunks; /* per dma */
2252 	nxge_status_t		status = NXGE_OK;
2253 
2254 	uint32_t		nxge_port_rbr_size;
2255 	uint32_t		nxge_port_rbr_spare_size;
2256 	uint32_t		nxge_port_rcr_size;
2257 	uint32_t		rx_cntl_alloc_size;
2258 
2259 	NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rx_mem_pool"));
2260 
2261 	p_all_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2262 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_all_cfgp->hw_config;
2263 	rdc_max = NXGE_MAX_RDCS;
2264 
2265 	/*
2266 	 * Allocate memory for the common DMA data structures.
2267 	 */
2268 	dma_poolp = (p_nxge_dma_pool_t)KMEM_ZALLOC(sizeof (nxge_dma_pool_t),
2269 	    KM_SLEEP);
2270 	dma_buf_p = (p_nxge_dma_common_t *)KMEM_ZALLOC(
2271 	    sizeof (p_nxge_dma_common_t) * rdc_max, KM_SLEEP);
2272 
2273 	dma_cntl_poolp = (p_nxge_dma_pool_t)
2274 	    KMEM_ZALLOC(sizeof (nxge_dma_pool_t), KM_SLEEP);
2275 	dma_cntl_p = (p_nxge_dma_common_t *)KMEM_ZALLOC(
2276 	    sizeof (p_nxge_dma_common_t) * rdc_max, KM_SLEEP);
2277 
2278 	num_chunks = (uint32_t *)KMEM_ZALLOC(
2279 	    sizeof (uint32_t) * rdc_max, KM_SLEEP);
2280 
2281 	/*
2282 	 * Assume that each DMA channel will be configured with
2283 	 * the default block size.
2284 	 * rbr block counts are modulo the batch count (16).
2285 	 */
2286 	nxge_port_rbr_size = p_all_cfgp->rbr_size;
2287 	nxge_port_rcr_size = p_all_cfgp->rcr_size;
2288 
2289 	if (!nxge_port_rbr_size) {
2290 		nxge_port_rbr_size = NXGE_RBR_RBB_DEFAULT;
2291 	}
2292 	if (nxge_port_rbr_size % NXGE_RXDMA_POST_BATCH) {
2293 		nxge_port_rbr_size = (NXGE_RXDMA_POST_BATCH *
2294 		    (nxge_port_rbr_size / NXGE_RXDMA_POST_BATCH + 1));
2295 	}
2296 
2297 	p_all_cfgp->rbr_size = nxge_port_rbr_size;
2298 	nxge_port_rbr_spare_size = nxge_rbr_spare_size;
2299 
2300 	if (nxge_port_rbr_spare_size % NXGE_RXDMA_POST_BATCH) {
2301 		nxge_port_rbr_spare_size = (NXGE_RXDMA_POST_BATCH *
2302 		    (nxge_port_rbr_spare_size / NXGE_RXDMA_POST_BATCH + 1));
2303 	}
2304 	if (nxge_port_rbr_size > RBR_DEFAULT_MAX_BLKS) {
2305 		NXGE_DEBUG_MSG((nxgep, MEM_CTL,
2306 		    "nxge_alloc_rx_mem_pool: RBR size too high %d, "
2307 		    "set to default %d",
2308 		    nxge_port_rbr_size, RBR_DEFAULT_MAX_BLKS));
2309 		nxge_port_rbr_size = RBR_DEFAULT_MAX_BLKS;
2310 	}
2311 	if (nxge_port_rcr_size > RCR_DEFAULT_MAX) {
2312 		NXGE_DEBUG_MSG((nxgep, MEM_CTL,
2313 		    "nxge_alloc_rx_mem_pool: RCR too high %d, "
2314 		    "set to default %d",
2315 		    nxge_port_rcr_size, RCR_DEFAULT_MAX));
2316 		nxge_port_rcr_size = RCR_DEFAULT_MAX;
2317 	}
2318 
2319 	/*
2320 	 * N2/NIU has limitation on the descriptor sizes (contiguous
2321 	 * memory allocation on data buffers to 4M (contig_mem_alloc)
2322 	 * and little endian for control buffers (must use the ddi/dki mem alloc
2323 	 * function).
2324 	 */
2325 #if	defined(sun4v) && defined(NIU_LP_WORKAROUND)
2326 	if (nxgep->niu_type == N2_NIU) {
2327 		nxge_port_rbr_spare_size = 0;
2328 		if ((nxge_port_rbr_size > NXGE_NIU_CONTIG_RBR_MAX) ||
2329 		    (!ISP2(nxge_port_rbr_size))) {
2330 			nxge_port_rbr_size = NXGE_NIU_CONTIG_RBR_MAX;
2331 		}
2332 		if ((nxge_port_rcr_size > NXGE_NIU_CONTIG_RCR_MAX) ||
2333 		    (!ISP2(nxge_port_rcr_size))) {
2334 			nxge_port_rcr_size = NXGE_NIU_CONTIG_RCR_MAX;
2335 		}
2336 	}
2337 #endif
2338 
2339 	/*
2340 	 * Addresses of receive block ring, receive completion ring and the
2341 	 * mailbox must be all cache-aligned (64 bytes).
2342 	 */
2343 	rx_cntl_alloc_size = nxge_port_rbr_size + nxge_port_rbr_spare_size;
2344 	rx_cntl_alloc_size *= (sizeof (rx_desc_t));
2345 	rx_cntl_alloc_size += (sizeof (rcr_entry_t) * nxge_port_rcr_size);
2346 	rx_cntl_alloc_size += sizeof (rxdma_mailbox_t);
2347 
2348 	NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_alloc_rx_mem_pool: "
2349 	    "nxge_port_rbr_size = %d nxge_port_rbr_spare_size = %d "
2350 	    "nxge_port_rcr_size = %d "
2351 	    "rx_cntl_alloc_size = %d",
2352 	    nxge_port_rbr_size, nxge_port_rbr_spare_size,
2353 	    nxge_port_rcr_size,
2354 	    rx_cntl_alloc_size));
2355 
2356 #if	defined(sun4v) && defined(NIU_LP_WORKAROUND)
2357 	if (nxgep->niu_type == N2_NIU) {
2358 		uint32_t rx_buf_alloc_size = (nxgep->rx_default_block_size *
2359 		    (nxge_port_rbr_size + nxge_port_rbr_spare_size));
2360 
2361 		if (!ISP2(rx_buf_alloc_size)) {
2362 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2363 			    "==> nxge_alloc_rx_mem_pool: "
2364 			    " must be power of 2"));
2365 			status |= (NXGE_ERROR | NXGE_DDI_FAILED);
2366 			goto nxge_alloc_rx_mem_pool_exit;
2367 		}
2368 
2369 		if (rx_buf_alloc_size > (1 << 22)) {
2370 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2371 			    "==> nxge_alloc_rx_mem_pool: "
2372 			    " limit size to 4M"));
2373 			status |= (NXGE_ERROR | NXGE_DDI_FAILED);
2374 			goto nxge_alloc_rx_mem_pool_exit;
2375 		}
2376 
2377 		if (rx_cntl_alloc_size < 0x2000) {
2378 			rx_cntl_alloc_size = 0x2000;
2379 		}
2380 	}
2381 #endif
2382 	nxgep->nxge_port_rbr_size = nxge_port_rbr_size;
2383 	nxgep->nxge_port_rcr_size = nxge_port_rcr_size;
2384 	nxgep->nxge_port_rbr_spare_size = nxge_port_rbr_spare_size;
2385 	nxgep->nxge_port_rx_cntl_alloc_size = rx_cntl_alloc_size;
2386 
2387 	dma_poolp->ndmas = p_cfgp->max_rdcs;
2388 	dma_poolp->num_chunks = num_chunks;
2389 	dma_poolp->buf_allocated = B_TRUE;
2390 	nxgep->rx_buf_pool_p = dma_poolp;
2391 	dma_poolp->dma_buf_pool_p = dma_buf_p;
2392 
2393 	dma_cntl_poolp->ndmas = p_cfgp->max_rdcs;
2394 	dma_cntl_poolp->buf_allocated = B_TRUE;
2395 	nxgep->rx_cntl_pool_p = dma_cntl_poolp;
2396 	dma_cntl_poolp->dma_buf_pool_p = dma_cntl_p;
2397 
2398 	/* Allocate the receive rings, too. */
2399 	nxgep->rx_rbr_rings =
2400 	    KMEM_ZALLOC(sizeof (rx_rbr_rings_t), KM_SLEEP);
2401 	nxgep->rx_rbr_rings->rbr_rings =
2402 	    KMEM_ZALLOC(sizeof (p_rx_rbr_ring_t) * rdc_max, KM_SLEEP);
2403 	nxgep->rx_rcr_rings =
2404 	    KMEM_ZALLOC(sizeof (rx_rcr_rings_t), KM_SLEEP);
2405 	nxgep->rx_rcr_rings->rcr_rings =
2406 	    KMEM_ZALLOC(sizeof (p_rx_rcr_ring_t) * rdc_max, KM_SLEEP);
2407 	nxgep->rx_mbox_areas_p =
2408 	    KMEM_ZALLOC(sizeof (rx_mbox_areas_t), KM_SLEEP);
2409 	nxgep->rx_mbox_areas_p->rxmbox_areas =
2410 	    KMEM_ZALLOC(sizeof (p_rx_mbox_t) * rdc_max, KM_SLEEP);
2411 
2412 	nxgep->rx_rbr_rings->ndmas = nxgep->rx_rcr_rings->ndmas =
2413 	    p_cfgp->max_rdcs;
2414 
2415 	NXGE_DEBUG_MSG((nxgep, DMA_CTL,
2416 	    "<== nxge_alloc_rx_mem_pool:status 0x%08x", status));
2417 
2418 nxge_alloc_rx_mem_pool_exit:
2419 	return (status);
2420 }
2421 
2422 /*
2423  * nxge_alloc_rxb
2424  *
2425  *	Allocate buffers for an RDC.
2426  *
2427  * Arguments:
2428  *	nxgep
2429  *	channel	The channel to map into our kernel space.
2430  *
2431  * Notes:
2432  *
2433  * NPI function calls:
2434  *
2435  * NXGE function calls:
2436  *
2437  * Registers accessed:
2438  *
2439  * Context:
2440  *
2441  * Taking apart:
2442  *
2443  * Open questions:
2444  *
2445  */
2446 nxge_status_t
nxge_alloc_rxb(p_nxge_t nxgep,int channel)2447 nxge_alloc_rxb(
2448 	p_nxge_t nxgep,
2449 	int channel)
2450 {
2451 	size_t			rx_buf_alloc_size;
2452 	nxge_status_t		status = NXGE_OK;
2453 
2454 	nxge_dma_common_t	**data;
2455 	nxge_dma_common_t	**control;
2456 	uint32_t		*num_chunks;
2457 
2458 	NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rbb"));
2459 
2460 	/*
2461 	 * Allocate memory for the receive buffers and descriptor rings.
2462 	 * Replace these allocation functions with the interface functions
2463 	 * provided by the partition manager if/when they are available.
2464 	 */
2465 
2466 	/*
2467 	 * Allocate memory for the receive buffer blocks.
2468 	 */
2469 	rx_buf_alloc_size = (nxgep->rx_default_block_size *
2470 	    (nxgep->nxge_port_rbr_size + nxgep->nxge_port_rbr_spare_size));
2471 
2472 	data = &nxgep->rx_buf_pool_p->dma_buf_pool_p[channel];
2473 	num_chunks = &nxgep->rx_buf_pool_p->num_chunks[channel];
2474 
2475 	if ((status = nxge_alloc_rx_buf_dma(
2476 	    nxgep, channel, data, rx_buf_alloc_size,
2477 	    nxgep->rx_default_block_size, num_chunks)) != NXGE_OK) {
2478 		return (status);
2479 	}
2480 
2481 	NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_alloc_rxb(): "
2482 	    "dma %d dma_buf_p %llx &dma_buf_p %llx", channel, *data, data));
2483 
2484 	/*
2485 	 * Allocate memory for descriptor rings and mailbox.
2486 	 */
2487 	control = &nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel];
2488 
2489 	if ((status = nxge_alloc_rx_cntl_dma(
2490 	    nxgep, channel, control, nxgep->nxge_port_rx_cntl_alloc_size))
2491 	    != NXGE_OK) {
2492 		nxge_free_rx_cntl_dma(nxgep, *control);
2493 		(*data)->buf_alloc_state |= BUF_ALLOCATED_WAIT_FREE;
2494 		nxge_free_rx_buf_dma(nxgep, *data, *num_chunks);
2495 		return (status);
2496 	}
2497 
2498 	NXGE_DEBUG_MSG((nxgep, DMA_CTL,
2499 	    "<== nxge_alloc_rx_mem_pool:status 0x%08x", status));
2500 
2501 	return (status);
2502 }
2503 
2504 void
nxge_free_rxb(p_nxge_t nxgep,int channel)2505 nxge_free_rxb(
2506 	p_nxge_t nxgep,
2507 	int channel)
2508 {
2509 	nxge_dma_common_t	*data;
2510 	nxge_dma_common_t	*control;
2511 	uint32_t		num_chunks;
2512 
2513 	NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rbb"));
2514 
2515 	data = nxgep->rx_buf_pool_p->dma_buf_pool_p[channel];
2516 	num_chunks = nxgep->rx_buf_pool_p->num_chunks[channel];
2517 	nxge_free_rx_buf_dma(nxgep, data, num_chunks);
2518 
2519 	nxgep->rx_buf_pool_p->dma_buf_pool_p[channel] = 0;
2520 	nxgep->rx_buf_pool_p->num_chunks[channel] = 0;
2521 
2522 	control = nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel];
2523 	nxge_free_rx_cntl_dma(nxgep, control);
2524 
2525 	nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel] = 0;
2526 
2527 	KMEM_FREE(data, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK);
2528 	KMEM_FREE(control, sizeof (nxge_dma_common_t));
2529 
2530 	NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_alloc_rbb"));
2531 }
2532 
2533 static void
nxge_free_rx_mem_pool(p_nxge_t nxgep)2534 nxge_free_rx_mem_pool(p_nxge_t nxgep)
2535 {
2536 	int rdc_max = NXGE_MAX_RDCS;
2537 
2538 	NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_free_rx_mem_pool"));
2539 
2540 	if (!nxgep->rx_buf_pool_p || !nxgep->rx_buf_pool_p->buf_allocated) {
2541 		NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
2542 		    "<== nxge_free_rx_mem_pool "
2543 		    "(null rx buf pool or buf not allocated"));
2544 		return;
2545 	}
2546 	if (!nxgep->rx_cntl_pool_p || !nxgep->rx_cntl_pool_p->buf_allocated) {
2547 		NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
2548 		    "<== nxge_free_rx_mem_pool "
2549 		    "(null rx cntl buf pool or cntl buf not allocated"));
2550 		return;
2551 	}
2552 
2553 	KMEM_FREE(nxgep->rx_cntl_pool_p->dma_buf_pool_p,
2554 	    sizeof (p_nxge_dma_common_t) * rdc_max);
2555 	KMEM_FREE(nxgep->rx_cntl_pool_p, sizeof (nxge_dma_pool_t));
2556 
2557 	KMEM_FREE(nxgep->rx_buf_pool_p->num_chunks,
2558 	    sizeof (uint32_t) * rdc_max);
2559 	KMEM_FREE(nxgep->rx_buf_pool_p->dma_buf_pool_p,
2560 	    sizeof (p_nxge_dma_common_t) * rdc_max);
2561 	KMEM_FREE(nxgep->rx_buf_pool_p, sizeof (nxge_dma_pool_t));
2562 
2563 	nxgep->rx_buf_pool_p = 0;
2564 	nxgep->rx_cntl_pool_p = 0;
2565 
2566 	KMEM_FREE(nxgep->rx_rbr_rings->rbr_rings,
2567 	    sizeof (p_rx_rbr_ring_t) * rdc_max);
2568 	KMEM_FREE(nxgep->rx_rbr_rings, sizeof (rx_rbr_rings_t));
2569 	KMEM_FREE(nxgep->rx_rcr_rings->rcr_rings,
2570 	    sizeof (p_rx_rcr_ring_t) * rdc_max);
2571 	KMEM_FREE(nxgep->rx_rcr_rings, sizeof (rx_rcr_rings_t));
2572 	KMEM_FREE(nxgep->rx_mbox_areas_p->rxmbox_areas,
2573 	    sizeof (p_rx_mbox_t) * rdc_max);
2574 	KMEM_FREE(nxgep->rx_mbox_areas_p, sizeof (rx_mbox_areas_t));
2575 
2576 	nxgep->rx_rbr_rings = 0;
2577 	nxgep->rx_rcr_rings = 0;
2578 	nxgep->rx_mbox_areas_p = 0;
2579 
2580 	NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_free_rx_mem_pool"));
2581 }
2582 
2583 
2584 static nxge_status_t
nxge_alloc_rx_buf_dma(p_nxge_t nxgep,uint16_t dma_channel,p_nxge_dma_common_t * dmap,size_t alloc_size,size_t block_size,uint32_t * num_chunks)2585 nxge_alloc_rx_buf_dma(p_nxge_t nxgep, uint16_t dma_channel,
2586     p_nxge_dma_common_t *dmap,
2587     size_t alloc_size, size_t block_size, uint32_t *num_chunks)
2588 {
2589 	p_nxge_dma_common_t	rx_dmap;
2590 	nxge_status_t		status = NXGE_OK;
2591 	size_t			total_alloc_size;
2592 	size_t			allocated = 0;
2593 	int			i, size_index, array_size;
2594 	boolean_t		use_kmem_alloc = B_FALSE;
2595 
2596 	NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rx_buf_dma"));
2597 
2598 	rx_dmap = (p_nxge_dma_common_t)
2599 	    KMEM_ZALLOC(sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK,
2600 	    KM_SLEEP);
2601 
2602 	NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
2603 	    " alloc_rx_buf_dma rdc %d asize %x bsize %x bbuf %llx ",
2604 	    dma_channel, alloc_size, block_size, dmap));
2605 
2606 	total_alloc_size = alloc_size;
2607 
2608 #if defined(RX_USE_RECLAIM_POST)
2609 	total_alloc_size = alloc_size + alloc_size/4;
2610 #endif
2611 
2612 	i = 0;
2613 	size_index = 0;
2614 	array_size =  sizeof (alloc_sizes)/sizeof (size_t);
2615 	while ((size_index < array_size) &&
2616 	    (alloc_sizes[size_index] < alloc_size))
2617 		size_index++;
2618 	if (size_index >= array_size) {
2619 		size_index = array_size - 1;
2620 	}
2621 
2622 	/* For Neptune, use kmem_alloc if the kmem flag is set. */
2623 	if (nxgep->niu_type != N2_NIU && nxge_use_kmem_alloc) {
2624 		use_kmem_alloc = B_TRUE;
2625 #if defined(__x86)
2626 		size_index = 0;
2627 #endif
2628 		NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
2629 		    "==> nxge_alloc_rx_buf_dma: "
2630 		    "Neptune use kmem_alloc() - size_index %d",
2631 		    size_index));
2632 	}
2633 
2634 	while ((allocated < total_alloc_size) &&
2635 	    (size_index >= 0) && (i < NXGE_DMA_BLOCK)) {
2636 		rx_dmap[i].dma_chunk_index = i;
2637 		rx_dmap[i].block_size = block_size;
2638 		rx_dmap[i].alength = alloc_sizes[size_index];
2639 		rx_dmap[i].orig_alength = rx_dmap[i].alength;
2640 		rx_dmap[i].nblocks = alloc_sizes[size_index] / block_size;
2641 		rx_dmap[i].dma_channel = dma_channel;
2642 		rx_dmap[i].contig_alloc_type = B_FALSE;
2643 		rx_dmap[i].kmem_alloc_type = B_FALSE;
2644 		rx_dmap[i].buf_alloc_type = DDI_MEM_ALLOC;
2645 
2646 		/*
2647 		 * N2/NIU: data buffers must be contiguous as the driver
2648 		 *	   needs to call Hypervisor api to set up
2649 		 *	   logical pages.
2650 		 */
2651 		if ((nxgep->niu_type == N2_NIU) && (NXGE_DMA_BLOCK == 1)) {
2652 			rx_dmap[i].contig_alloc_type = B_TRUE;
2653 			rx_dmap[i].buf_alloc_type = CONTIG_MEM_ALLOC;
2654 		} else if (use_kmem_alloc) {
2655 			/* For Neptune, use kmem_alloc */
2656 			NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
2657 			    "==> nxge_alloc_rx_buf_dma: "
2658 			    "Neptune use kmem_alloc()"));
2659 			rx_dmap[i].kmem_alloc_type = B_TRUE;
2660 			rx_dmap[i].buf_alloc_type = KMEM_ALLOC;
2661 		}
2662 
2663 		NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
2664 		    "alloc_rx_buf_dma rdc %d chunk %d bufp %llx size %x "
2665 		    "i %d nblocks %d alength %d",
2666 		    dma_channel, i, &rx_dmap[i], block_size,
2667 		    i, rx_dmap[i].nblocks,
2668 		    rx_dmap[i].alength));
2669 		status = nxge_dma_mem_alloc(nxgep, nxge_force_dma,
2670 		    &nxge_rx_dma_attr,
2671 		    rx_dmap[i].alength,
2672 		    &nxge_dev_buf_dma_acc_attr,
2673 		    DDI_DMA_READ | DDI_DMA_STREAMING,
2674 		    (p_nxge_dma_common_t)(&rx_dmap[i]));
2675 		if (status != NXGE_OK) {
2676 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2677 			    "nxge_alloc_rx_buf_dma: Alloc Failed: "
2678 			    "dma %d size_index %d size requested %d",
2679 			    dma_channel,
2680 			    size_index,
2681 			    rx_dmap[i].alength));
2682 			size_index--;
2683 		} else {
2684 			rx_dmap[i].buf_alloc_state = BUF_ALLOCATED;
2685 			NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
2686 			    " nxge_alloc_rx_buf_dma DONE  alloc mem: "
2687 			    "dma %d dma_buf_p $%p kaddrp $%p alength %d "
2688 			    "buf_alloc_state %d alloc_type %d",
2689 			    dma_channel,
2690 			    &rx_dmap[i],
2691 			    rx_dmap[i].kaddrp,
2692 			    rx_dmap[i].alength,
2693 			    rx_dmap[i].buf_alloc_state,
2694 			    rx_dmap[i].buf_alloc_type));
2695 			NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
2696 			    " alloc_rx_buf_dma allocated rdc %d "
2697 			    "chunk %d size %x dvma %x bufp %llx kaddrp $%p",
2698 			    dma_channel, i, rx_dmap[i].alength,
2699 			    rx_dmap[i].ioaddr_pp, &rx_dmap[i],
2700 			    rx_dmap[i].kaddrp));
2701 			i++;
2702 			allocated += alloc_sizes[size_index];
2703 		}
2704 	}
2705 
2706 	if (allocated < total_alloc_size) {
2707 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2708 		    "==> nxge_alloc_rx_buf_dma: not enough for channel %d "
2709 		    "allocated 0x%x requested 0x%x",
2710 		    dma_channel,
2711 		    allocated, total_alloc_size));
2712 		status = NXGE_ERROR;
2713 		goto nxge_alloc_rx_mem_fail1;
2714 	}
2715 
2716 	NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
2717 	    "==> nxge_alloc_rx_buf_dma: Allocated for channel %d "
2718 	    "allocated 0x%x requested 0x%x",
2719 	    dma_channel,
2720 	    allocated, total_alloc_size));
2721 
2722 	NXGE_DEBUG_MSG((nxgep, DMA_CTL,
2723 	    " alloc_rx_buf_dma rdc %d allocated %d chunks",
2724 	    dma_channel, i));
2725 	*num_chunks = i;
2726 	*dmap = rx_dmap;
2727 
2728 	goto nxge_alloc_rx_mem_exit;
2729 
2730 nxge_alloc_rx_mem_fail1:
2731 	KMEM_FREE(rx_dmap, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK);
2732 
2733 nxge_alloc_rx_mem_exit:
2734 	NXGE_DEBUG_MSG((nxgep, DMA_CTL,
2735 	    "<== nxge_alloc_rx_buf_dma status 0x%08x", status));
2736 
2737 	return (status);
2738 }
2739 
2740 /*ARGSUSED*/
2741 static void
nxge_free_rx_buf_dma(p_nxge_t nxgep,p_nxge_dma_common_t dmap,uint32_t num_chunks)2742 nxge_free_rx_buf_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap,
2743     uint32_t num_chunks)
2744 {
2745 	int		i;
2746 
2747 	NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
2748 	    "==> nxge_free_rx_buf_dma: # of chunks %d", num_chunks));
2749 
2750 	if (dmap == 0)
2751 		return;
2752 
2753 	for (i = 0; i < num_chunks; i++) {
2754 		NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
2755 		    "==> nxge_free_rx_buf_dma: chunk %d dmap 0x%llx",
2756 		    i, dmap));
2757 		nxge_dma_free_rx_data_buf(dmap++);
2758 	}
2759 
2760 	NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_free_rx_buf_dma"));
2761 }
2762 
2763 /*ARGSUSED*/
2764 static nxge_status_t
nxge_alloc_rx_cntl_dma(p_nxge_t nxgep,uint16_t dma_channel,p_nxge_dma_common_t * dmap,size_t size)2765 nxge_alloc_rx_cntl_dma(p_nxge_t nxgep, uint16_t dma_channel,
2766     p_nxge_dma_common_t *dmap, size_t size)
2767 {
2768 	p_nxge_dma_common_t	rx_dmap;
2769 	nxge_status_t		status = NXGE_OK;
2770 
2771 	NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rx_cntl_dma"));
2772 
2773 	rx_dmap = (p_nxge_dma_common_t)
2774 	    KMEM_ZALLOC(sizeof (nxge_dma_common_t), KM_SLEEP);
2775 
2776 	rx_dmap->contig_alloc_type = B_FALSE;
2777 	rx_dmap->kmem_alloc_type = B_FALSE;
2778 
2779 	status = nxge_dma_mem_alloc(nxgep, nxge_force_dma,
2780 	    &nxge_desc_dma_attr,
2781 	    size,
2782 	    &nxge_dev_desc_dma_acc_attr,
2783 	    DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
2784 	    rx_dmap);
2785 	if (status != NXGE_OK) {
2786 		goto nxge_alloc_rx_cntl_dma_fail1;
2787 	}
2788 
2789 	*dmap = rx_dmap;
2790 	goto nxge_alloc_rx_cntl_dma_exit;
2791 
2792 nxge_alloc_rx_cntl_dma_fail1:
2793 	KMEM_FREE(rx_dmap, sizeof (nxge_dma_common_t));
2794 
2795 nxge_alloc_rx_cntl_dma_exit:
2796 	NXGE_DEBUG_MSG((nxgep, DMA_CTL,
2797 	    "<== nxge_alloc_rx_cntl_dma status 0x%08x", status));
2798 
2799 	return (status);
2800 }
2801 
2802 /*ARGSUSED*/
2803 static void
nxge_free_rx_cntl_dma(p_nxge_t nxgep,p_nxge_dma_common_t dmap)2804 nxge_free_rx_cntl_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap)
2805 {
2806 	NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_free_rx_cntl_dma"));
2807 
2808 	if (dmap == 0)
2809 		return;
2810 
2811 	nxge_dma_mem_free(dmap);
2812 
2813 	NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_free_rx_cntl_dma"));
2814 }
2815 
2816 typedef struct {
2817 	size_t	tx_size;
2818 	size_t	cr_size;
2819 	size_t	threshhold;
2820 } nxge_tdc_sizes_t;
2821 
2822 static
2823 nxge_status_t
nxge_tdc_sizes(nxge_t * nxgep,nxge_tdc_sizes_t * sizes)2824 nxge_tdc_sizes(
2825 	nxge_t *nxgep,
2826 	nxge_tdc_sizes_t *sizes)
2827 {
2828 	uint32_t threshhold;	/* The bcopy() threshhold */
2829 	size_t tx_size;		/* Transmit buffer size */
2830 	size_t cr_size;		/* Completion ring size */
2831 
2832 	/*
2833 	 * Assume that each DMA channel will be configured with the
2834 	 * default transmit buffer size for copying transmit data.
2835 	 * (If a packet is bigger than this, it will not be copied.)
2836 	 */
2837 	if (nxgep->niu_type == N2_NIU) {
2838 		threshhold = TX_BCOPY_SIZE;
2839 	} else {
2840 		threshhold = nxge_bcopy_thresh;
2841 	}
2842 	tx_size = nxge_tx_ring_size * threshhold;
2843 
2844 	cr_size = nxge_tx_ring_size * sizeof (tx_desc_t);
2845 	cr_size += sizeof (txdma_mailbox_t);
2846 
2847 #if	defined(sun4v) && defined(NIU_LP_WORKAROUND)
2848 	if (nxgep->niu_type == N2_NIU) {
2849 		if (!ISP2(tx_size)) {
2850 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2851 			    "==> nxge_tdc_sizes: Tx size"
2852 			    " must be power of 2"));
2853 			return (NXGE_ERROR);
2854 		}
2855 
2856 		if (tx_size > (1 << 22)) {
2857 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2858 			    "==> nxge_tdc_sizes: Tx size"
2859 			    " limited to 4M"));
2860 			return (NXGE_ERROR);
2861 		}
2862 
2863 		if (cr_size < 0x2000)
2864 			cr_size = 0x2000;
2865 	}
2866 #endif
2867 
2868 	sizes->threshhold = threshhold;
2869 	sizes->tx_size = tx_size;
2870 	sizes->cr_size = cr_size;
2871 
2872 	return (NXGE_OK);
2873 }
2874 /*
2875  * nxge_alloc_txb
2876  *
2877  *	Allocate buffers for an TDC.
2878  *
2879  * Arguments:
2880  *	nxgep
2881  *	channel	The channel to map into our kernel space.
2882  *
2883  * Notes:
2884  *
2885  * NPI function calls:
2886  *
2887  * NXGE function calls:
2888  *
2889  * Registers accessed:
2890  *
2891  * Context:
2892  *
2893  * Taking apart:
2894  *
2895  * Open questions:
2896  *
2897  */
2898 nxge_status_t
nxge_alloc_txb(p_nxge_t nxgep,int channel)2899 nxge_alloc_txb(
2900 	p_nxge_t nxgep,
2901 	int channel)
2902 {
2903 	nxge_dma_common_t	**dma_buf_p;
2904 	nxge_dma_common_t	**dma_cntl_p;
2905 	uint32_t		*num_chunks;
2906 	nxge_status_t		status = NXGE_OK;
2907 
2908 	nxge_tdc_sizes_t	sizes;
2909 
2910 	NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_tbb"));
2911 
2912 	if (nxge_tdc_sizes(nxgep, &sizes) != NXGE_OK)
2913 		return (NXGE_ERROR);
2914 
2915 	/*
2916 	 * Allocate memory for transmit buffers and descriptor rings.
2917 	 * Replace these allocation functions with the interface functions
2918 	 * provided by the partition manager Real Soon Now.
2919 	 */
2920 	dma_buf_p = &nxgep->tx_buf_pool_p->dma_buf_pool_p[channel];
2921 	num_chunks = &nxgep->tx_buf_pool_p->num_chunks[channel];
2922 
2923 	dma_cntl_p = &nxgep->tx_cntl_pool_p->dma_buf_pool_p[channel];
2924 
2925 	/*
2926 	 * Allocate memory for transmit buffers and descriptor rings.
2927 	 * Replace allocation functions with interface functions provided
2928 	 * by the partition manager when it is available.
2929 	 *
2930 	 * Allocate memory for the transmit buffer pool.
2931 	 */
2932 	NXGE_DEBUG_MSG((nxgep, DMA_CTL,
2933 	    "sizes: tx: %ld, cr:%ld, th:%ld",
2934 	    sizes.tx_size, sizes.cr_size, sizes.threshhold));
2935 
2936 	*num_chunks = 0;
2937 	status = nxge_alloc_tx_buf_dma(nxgep, channel, dma_buf_p,
2938 	    sizes.tx_size, sizes.threshhold, num_chunks);
2939 	if (status != NXGE_OK) {
2940 		cmn_err(CE_NOTE, "nxge_alloc_tx_buf_dma failed!");
2941 		return (status);
2942 	}
2943 
2944 	/*
2945 	 * Allocate memory for descriptor rings and mailbox.
2946 	 */
2947 	status = nxge_alloc_tx_cntl_dma(nxgep, channel, dma_cntl_p,
2948 	    sizes.cr_size);
2949 	if (status != NXGE_OK) {
2950 		nxge_free_tx_buf_dma(nxgep, *dma_buf_p, *num_chunks);
2951 		cmn_err(CE_NOTE, "nxge_alloc_tx_cntl_dma failed!");
2952 		return (status);
2953 	}
2954 
2955 	return (NXGE_OK);
2956 }
2957 
2958 void
nxge_free_txb(p_nxge_t nxgep,int channel)2959 nxge_free_txb(
2960 	p_nxge_t nxgep,
2961 	int channel)
2962 {
2963 	nxge_dma_common_t	*data;
2964 	nxge_dma_common_t	*control;
2965 	uint32_t		num_chunks;
2966 
2967 	NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_free_txb"));
2968 
2969 	data = nxgep->tx_buf_pool_p->dma_buf_pool_p[channel];
2970 	num_chunks = nxgep->tx_buf_pool_p->num_chunks[channel];
2971 	nxge_free_tx_buf_dma(nxgep, data, num_chunks);
2972 
2973 	nxgep->tx_buf_pool_p->dma_buf_pool_p[channel] = 0;
2974 	nxgep->tx_buf_pool_p->num_chunks[channel] = 0;
2975 
2976 	control = nxgep->tx_cntl_pool_p->dma_buf_pool_p[channel];
2977 	nxge_free_tx_cntl_dma(nxgep, control);
2978 
2979 	nxgep->tx_cntl_pool_p->dma_buf_pool_p[channel] = 0;
2980 
2981 	KMEM_FREE(data, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK);
2982 	KMEM_FREE(control, sizeof (nxge_dma_common_t));
2983 
2984 	NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_free_txb"));
2985 }
2986 
2987 /*
2988  * nxge_alloc_tx_mem_pool
2989  *
2990  *	This function allocates all of the per-port TDC control data structures.
2991  *	The per-channel (TDC) data structures are allocated when needed.
2992  *
2993  * Arguments:
2994  *	nxgep
2995  *
2996  * Notes:
2997  *
2998  * Context:
2999  *	Any domain
3000  */
3001 nxge_status_t
nxge_alloc_tx_mem_pool(p_nxge_t nxgep)3002 nxge_alloc_tx_mem_pool(p_nxge_t nxgep)
3003 {
3004 	nxge_hw_pt_cfg_t	*p_cfgp;
3005 	nxge_dma_pool_t		*dma_poolp;
3006 	nxge_dma_common_t	**dma_buf_p;
3007 	nxge_dma_pool_t		*dma_cntl_poolp;
3008 	nxge_dma_common_t	**dma_cntl_p;
3009 	uint32_t		*num_chunks; /* per dma */
3010 	int			tdc_max;
3011 
3012 	NXGE_DEBUG_MSG((nxgep, MEM_CTL, "==> nxge_alloc_tx_mem_pool"));
3013 
3014 	p_cfgp = &nxgep->pt_config.hw_config;
3015 	tdc_max = NXGE_MAX_TDCS;
3016 
3017 	/*
3018 	 * Allocate memory for each transmit DMA channel.
3019 	 */
3020 	dma_poolp = (p_nxge_dma_pool_t)KMEM_ZALLOC(sizeof (nxge_dma_pool_t),
3021 	    KM_SLEEP);
3022 	dma_buf_p = (p_nxge_dma_common_t *)KMEM_ZALLOC(
3023 	    sizeof (p_nxge_dma_common_t) * tdc_max, KM_SLEEP);
3024 
3025 	dma_cntl_poolp = (p_nxge_dma_pool_t)
3026 	    KMEM_ZALLOC(sizeof (nxge_dma_pool_t), KM_SLEEP);
3027 	dma_cntl_p = (p_nxge_dma_common_t *)KMEM_ZALLOC(
3028 	    sizeof (p_nxge_dma_common_t) * tdc_max, KM_SLEEP);
3029 
3030 	if (nxge_tx_ring_size > TDC_DEFAULT_MAX) {
3031 		NXGE_DEBUG_MSG((nxgep, MEM_CTL,
3032 		    "nxge_alloc_tx_mem_pool: TDC too high %d, "
3033 		    "set to default %d",
3034 		    nxge_tx_ring_size, TDC_DEFAULT_MAX));
3035 		nxge_tx_ring_size = TDC_DEFAULT_MAX;
3036 	}
3037 
3038 #if	defined(sun4v) && defined(NIU_LP_WORKAROUND)
3039 	/*
3040 	 * N2/NIU has limitation on the descriptor sizes (contiguous
3041 	 * memory allocation on data buffers to 4M (contig_mem_alloc)
3042 	 * and little endian for control buffers (must use the ddi/dki mem alloc
3043 	 * function). The transmit ring is limited to 8K (includes the
3044 	 * mailbox).
3045 	 */
3046 	if (nxgep->niu_type == N2_NIU) {
3047 		if ((nxge_tx_ring_size > NXGE_NIU_CONTIG_TX_MAX) ||
3048 		    (!ISP2(nxge_tx_ring_size))) {
3049 			nxge_tx_ring_size = NXGE_NIU_CONTIG_TX_MAX;
3050 		}
3051 	}
3052 #endif
3053 
3054 	nxgep->nxge_port_tx_ring_size = nxge_tx_ring_size;
3055 
3056 	num_chunks = (uint32_t *)KMEM_ZALLOC(
3057 	    sizeof (uint32_t) * tdc_max, KM_SLEEP);
3058 
3059 	dma_poolp->ndmas = p_cfgp->tdc.owned;
3060 	dma_poolp->num_chunks = num_chunks;
3061 	dma_poolp->dma_buf_pool_p = dma_buf_p;
3062 	nxgep->tx_buf_pool_p = dma_poolp;
3063 
3064 	dma_poolp->buf_allocated = B_TRUE;
3065 
3066 	dma_cntl_poolp->ndmas = p_cfgp->tdc.owned;
3067 	dma_cntl_poolp->dma_buf_pool_p = dma_cntl_p;
3068 	nxgep->tx_cntl_pool_p = dma_cntl_poolp;
3069 
3070 	dma_cntl_poolp->buf_allocated = B_TRUE;
3071 
3072 	nxgep->tx_rings =
3073 	    KMEM_ZALLOC(sizeof (tx_rings_t), KM_SLEEP);
3074 	nxgep->tx_rings->rings =
3075 	    KMEM_ZALLOC(sizeof (p_tx_ring_t) * tdc_max, KM_SLEEP);
3076 	nxgep->tx_mbox_areas_p =
3077 	    KMEM_ZALLOC(sizeof (tx_mbox_areas_t), KM_SLEEP);
3078 	nxgep->tx_mbox_areas_p->txmbox_areas_p =
3079 	    KMEM_ZALLOC(sizeof (p_tx_mbox_t) * tdc_max, KM_SLEEP);
3080 
3081 	nxgep->tx_rings->ndmas = p_cfgp->tdc.owned;
3082 
3083 	NXGE_DEBUG_MSG((nxgep, MEM_CTL,
3084 	    "==> nxge_alloc_tx_mem_pool: ndmas %d poolp->ndmas %d",
3085 	    tdc_max, dma_poolp->ndmas));
3086 
3087 	return (NXGE_OK);
3088 }
3089 
3090 nxge_status_t
nxge_alloc_tx_buf_dma(p_nxge_t nxgep,uint16_t dma_channel,p_nxge_dma_common_t * dmap,size_t alloc_size,size_t block_size,uint32_t * num_chunks)3091 nxge_alloc_tx_buf_dma(p_nxge_t nxgep, uint16_t dma_channel,
3092     p_nxge_dma_common_t *dmap, size_t alloc_size,
3093     size_t block_size, uint32_t *num_chunks)
3094 {
3095 	p_nxge_dma_common_t	tx_dmap;
3096 	nxge_status_t		status = NXGE_OK;
3097 	size_t			total_alloc_size;
3098 	size_t			allocated = 0;
3099 	int			i, size_index, array_size;
3100 
3101 	NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_tx_buf_dma"));
3102 
3103 	tx_dmap = (p_nxge_dma_common_t)
3104 	    KMEM_ZALLOC(sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK,
3105 	    KM_SLEEP);
3106 
3107 	total_alloc_size = alloc_size;
3108 	i = 0;
3109 	size_index = 0;
3110 	array_size =  sizeof (alloc_sizes) /  sizeof (size_t);
3111 	while ((size_index < array_size) &&
3112 	    (alloc_sizes[size_index] < alloc_size))
3113 		size_index++;
3114 	if (size_index >= array_size) {
3115 		size_index = array_size - 1;
3116 	}
3117 
3118 	while ((allocated < total_alloc_size) &&
3119 	    (size_index >= 0) && (i < NXGE_DMA_BLOCK)) {
3120 
3121 		tx_dmap[i].dma_chunk_index = i;
3122 		tx_dmap[i].block_size = block_size;
3123 		tx_dmap[i].alength = alloc_sizes[size_index];
3124 		tx_dmap[i].orig_alength = tx_dmap[i].alength;
3125 		tx_dmap[i].nblocks = alloc_sizes[size_index] / block_size;
3126 		tx_dmap[i].dma_channel = dma_channel;
3127 		tx_dmap[i].contig_alloc_type = B_FALSE;
3128 		tx_dmap[i].kmem_alloc_type = B_FALSE;
3129 
3130 		/*
3131 		 * N2/NIU: data buffers must be contiguous as the driver
3132 		 *	   needs to call Hypervisor api to set up
3133 		 *	   logical pages.
3134 		 */
3135 		if ((nxgep->niu_type == N2_NIU) && (NXGE_DMA_BLOCK == 1)) {
3136 			tx_dmap[i].contig_alloc_type = B_TRUE;
3137 		}
3138 
3139 		status = nxge_dma_mem_alloc(nxgep, nxge_force_dma,
3140 		    &nxge_tx_dma_attr,
3141 		    tx_dmap[i].alength,
3142 		    &nxge_dev_buf_dma_acc_attr,
3143 		    DDI_DMA_WRITE | DDI_DMA_STREAMING,
3144 		    (p_nxge_dma_common_t)(&tx_dmap[i]));
3145 		if (status != NXGE_OK) {
3146 			size_index--;
3147 		} else {
3148 			i++;
3149 			allocated += alloc_sizes[size_index];
3150 		}
3151 	}
3152 
3153 	if (allocated < total_alloc_size) {
3154 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3155 		    "==> nxge_alloc_tx_buf_dma: not enough channel %d: "
3156 		    "allocated 0x%x requested 0x%x",
3157 		    dma_channel,
3158 		    allocated, total_alloc_size));
3159 		status = NXGE_ERROR;
3160 		goto nxge_alloc_tx_mem_fail1;
3161 	}
3162 
3163 	NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
3164 	    "==> nxge_alloc_tx_buf_dma: Allocated for channel %d: "
3165 	    "allocated 0x%x requested 0x%x",
3166 	    dma_channel,
3167 	    allocated, total_alloc_size));
3168 
3169 	*num_chunks = i;
3170 	*dmap = tx_dmap;
3171 	NXGE_DEBUG_MSG((nxgep, DMA_CTL,
3172 	    "==> nxge_alloc_tx_buf_dma dmap 0x%016llx num chunks %d",
3173 	    *dmap, i));
3174 	goto nxge_alloc_tx_mem_exit;
3175 
3176 nxge_alloc_tx_mem_fail1:
3177 	KMEM_FREE(tx_dmap, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK);
3178 
3179 nxge_alloc_tx_mem_exit:
3180 	NXGE_DEBUG_MSG((nxgep, DMA_CTL,
3181 	    "<== nxge_alloc_tx_buf_dma status 0x%08x", status));
3182 
3183 	return (status);
3184 }
3185 
3186 /*ARGSUSED*/
3187 static void
nxge_free_tx_buf_dma(p_nxge_t nxgep,p_nxge_dma_common_t dmap,uint32_t num_chunks)3188 nxge_free_tx_buf_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap,
3189     uint32_t num_chunks)
3190 {
3191 	int		i;
3192 
3193 	NXGE_DEBUG_MSG((nxgep, MEM_CTL, "==> nxge_free_tx_buf_dma"));
3194 
3195 	if (dmap == 0)
3196 		return;
3197 
3198 	for (i = 0; i < num_chunks; i++) {
3199 		nxge_dma_mem_free(dmap++);
3200 	}
3201 
3202 	NXGE_DEBUG_MSG((nxgep, MEM_CTL, "<== nxge_free_tx_buf_dma"));
3203 }
3204 
3205 /*ARGSUSED*/
3206 nxge_status_t
nxge_alloc_tx_cntl_dma(p_nxge_t nxgep,uint16_t dma_channel,p_nxge_dma_common_t * dmap,size_t size)3207 nxge_alloc_tx_cntl_dma(p_nxge_t nxgep, uint16_t dma_channel,
3208     p_nxge_dma_common_t *dmap, size_t size)
3209 {
3210 	p_nxge_dma_common_t	tx_dmap;
3211 	nxge_status_t		status = NXGE_OK;
3212 
3213 	NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_tx_cntl_dma"));
3214 	tx_dmap = (p_nxge_dma_common_t)
3215 	    KMEM_ZALLOC(sizeof (nxge_dma_common_t), KM_SLEEP);
3216 
3217 	tx_dmap->contig_alloc_type = B_FALSE;
3218 	tx_dmap->kmem_alloc_type = B_FALSE;
3219 
3220 	status = nxge_dma_mem_alloc(nxgep, nxge_force_dma,
3221 	    &nxge_desc_dma_attr,
3222 	    size,
3223 	    &nxge_dev_desc_dma_acc_attr,
3224 	    DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
3225 	    tx_dmap);
3226 	if (status != NXGE_OK) {
3227 		goto nxge_alloc_tx_cntl_dma_fail1;
3228 	}
3229 
3230 	*dmap = tx_dmap;
3231 	goto nxge_alloc_tx_cntl_dma_exit;
3232 
3233 nxge_alloc_tx_cntl_dma_fail1:
3234 	KMEM_FREE(tx_dmap, sizeof (nxge_dma_common_t));
3235 
3236 nxge_alloc_tx_cntl_dma_exit:
3237 	NXGE_DEBUG_MSG((nxgep, DMA_CTL,
3238 	    "<== nxge_alloc_tx_cntl_dma status 0x%08x", status));
3239 
3240 	return (status);
3241 }
3242 
3243 /*ARGSUSED*/
3244 static void
nxge_free_tx_cntl_dma(p_nxge_t nxgep,p_nxge_dma_common_t dmap)3245 nxge_free_tx_cntl_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap)
3246 {
3247 	NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_free_tx_cntl_dma"));
3248 
3249 	if (dmap == 0)
3250 		return;
3251 
3252 	nxge_dma_mem_free(dmap);
3253 
3254 	NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_free_tx_cntl_dma"));
3255 }
3256 
3257 /*
3258  * nxge_free_tx_mem_pool
3259  *
3260  *	This function frees all of the per-port TDC control data structures.
3261  *	The per-channel (TDC) data structures are freed when the channel
3262  *	is stopped.
3263  *
3264  * Arguments:
3265  *	nxgep
3266  *
3267  * Notes:
3268  *
3269  * Context:
3270  *	Any domain
3271  */
3272 static void
nxge_free_tx_mem_pool(p_nxge_t nxgep)3273 nxge_free_tx_mem_pool(p_nxge_t nxgep)
3274 {
3275 	int tdc_max = NXGE_MAX_TDCS;
3276 
3277 	NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_free_tx_mem_pool"));
3278 
3279 	if (!nxgep->tx_buf_pool_p || !nxgep->tx_buf_pool_p->buf_allocated) {
3280 		NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
3281 		    "<== nxge_free_tx_mem_pool "
3282 		    "(null tx buf pool or buf not allocated"));
3283 		return;
3284 	}
3285 	if (!nxgep->tx_cntl_pool_p || !nxgep->tx_cntl_pool_p->buf_allocated) {
3286 		NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
3287 		    "<== nxge_free_tx_mem_pool "
3288 		    "(null tx cntl buf pool or cntl buf not allocated"));
3289 		return;
3290 	}
3291 
3292 	/* 1. Free the mailboxes. */
3293 	KMEM_FREE(nxgep->tx_mbox_areas_p->txmbox_areas_p,
3294 	    sizeof (p_tx_mbox_t) * tdc_max);
3295 	KMEM_FREE(nxgep->tx_mbox_areas_p, sizeof (tx_mbox_areas_t));
3296 
3297 	nxgep->tx_mbox_areas_p = 0;
3298 
3299 	/* 2. Free the transmit ring arrays. */
3300 	KMEM_FREE(nxgep->tx_rings->rings,
3301 	    sizeof (p_tx_ring_t) * tdc_max);
3302 	KMEM_FREE(nxgep->tx_rings, sizeof (tx_rings_t));
3303 
3304 	nxgep->tx_rings = 0;
3305 
3306 	/* 3. Free the completion ring data structures. */
3307 	KMEM_FREE(nxgep->tx_cntl_pool_p->dma_buf_pool_p,
3308 	    sizeof (p_nxge_dma_common_t) * tdc_max);
3309 	KMEM_FREE(nxgep->tx_cntl_pool_p, sizeof (nxge_dma_pool_t));
3310 
3311 	nxgep->tx_cntl_pool_p = 0;
3312 
3313 	/* 4. Free the data ring data structures. */
3314 	KMEM_FREE(nxgep->tx_buf_pool_p->num_chunks,
3315 	    sizeof (uint32_t) * tdc_max);
3316 	KMEM_FREE(nxgep->tx_buf_pool_p->dma_buf_pool_p,
3317 	    sizeof (p_nxge_dma_common_t) * tdc_max);
3318 	KMEM_FREE(nxgep->tx_buf_pool_p, sizeof (nxge_dma_pool_t));
3319 
3320 	nxgep->tx_buf_pool_p = 0;
3321 
3322 	NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_free_tx_mem_pool"));
3323 }
3324 
3325 /*ARGSUSED*/
3326 static nxge_status_t
nxge_dma_mem_alloc(p_nxge_t nxgep,dma_method_t method,struct ddi_dma_attr * dma_attrp,size_t length,ddi_device_acc_attr_t * acc_attr_p,uint_t xfer_flags,p_nxge_dma_common_t dma_p)3327 nxge_dma_mem_alloc(p_nxge_t nxgep, dma_method_t method,
3328     struct ddi_dma_attr *dma_attrp,
3329     size_t length, ddi_device_acc_attr_t *acc_attr_p, uint_t xfer_flags,
3330     p_nxge_dma_common_t dma_p)
3331 {
3332 	caddr_t			kaddrp;
3333 	int			ddi_status = DDI_SUCCESS;
3334 	boolean_t		contig_alloc_type;
3335 	boolean_t		kmem_alloc_type;
3336 
3337 	contig_alloc_type = dma_p->contig_alloc_type;
3338 
3339 	if (contig_alloc_type && (nxgep->niu_type != N2_NIU)) {
3340 		/*
3341 		 * contig_alloc_type for contiguous memory only allowed
3342 		 * for N2/NIU.
3343 		 */
3344 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3345 		    "nxge_dma_mem_alloc: alloc type not allowed (%d)",
3346 		    dma_p->contig_alloc_type));
3347 		return (NXGE_ERROR | NXGE_DDI_FAILED);
3348 	}
3349 
3350 	dma_p->dma_handle = NULL;
3351 	dma_p->acc_handle = NULL;
3352 	dma_p->kaddrp = dma_p->last_kaddrp = NULL;
3353 	dma_p->first_ioaddr_pp = dma_p->last_ioaddr_pp = NULL;
3354 	ddi_status = ddi_dma_alloc_handle(nxgep->dip, dma_attrp,
3355 	    DDI_DMA_DONTWAIT, NULL, &dma_p->dma_handle);
3356 	if (ddi_status != DDI_SUCCESS) {
3357 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3358 		    "nxge_dma_mem_alloc:ddi_dma_alloc_handle failed."));
3359 		return (NXGE_ERROR | NXGE_DDI_FAILED);
3360 	}
3361 
3362 	kmem_alloc_type = dma_p->kmem_alloc_type;
3363 
3364 	switch (contig_alloc_type) {
3365 	case B_FALSE:
3366 		switch (kmem_alloc_type) {
3367 		case B_FALSE:
3368 			ddi_status = ddi_dma_mem_alloc(dma_p->dma_handle,
3369 			    length,
3370 			    acc_attr_p,
3371 			    xfer_flags,
3372 			    DDI_DMA_DONTWAIT, 0, &kaddrp, &dma_p->alength,
3373 			    &dma_p->acc_handle);
3374 			if (ddi_status != DDI_SUCCESS) {
3375 				NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3376 				    "nxge_dma_mem_alloc: "
3377 				    "ddi_dma_mem_alloc failed"));
3378 				ddi_dma_free_handle(&dma_p->dma_handle);
3379 				dma_p->dma_handle = NULL;
3380 				return (NXGE_ERROR | NXGE_DDI_FAILED);
3381 			}
3382 			if (dma_p->alength < length) {
3383 				NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3384 				    "nxge_dma_mem_alloc:di_dma_mem_alloc "
3385 				    "< length."));
3386 				ddi_dma_mem_free(&dma_p->acc_handle);
3387 				ddi_dma_free_handle(&dma_p->dma_handle);
3388 				dma_p->acc_handle = NULL;
3389 				dma_p->dma_handle = NULL;
3390 				return (NXGE_ERROR);
3391 			}
3392 
3393 			ddi_status = ddi_dma_addr_bind_handle(dma_p->dma_handle,
3394 			    NULL,
3395 			    kaddrp, dma_p->alength, xfer_flags,
3396 			    DDI_DMA_DONTWAIT,
3397 			    0, &dma_p->dma_cookie, &dma_p->ncookies);
3398 			if (ddi_status != DDI_DMA_MAPPED) {
3399 				NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3400 				    "nxge_dma_mem_alloc: ddi_dma_addr_bind "
3401 				    "failed "
3402 				    "(staus 0x%x ncookies %d.)", ddi_status,
3403 				    dma_p->ncookies));
3404 				if (dma_p->acc_handle) {
3405 					ddi_dma_mem_free(&dma_p->acc_handle);
3406 					dma_p->acc_handle = NULL;
3407 				}
3408 				ddi_dma_free_handle(&dma_p->dma_handle);
3409 				dma_p->dma_handle = NULL;
3410 				return (NXGE_ERROR | NXGE_DDI_FAILED);
3411 			}
3412 
3413 			if (dma_p->ncookies != 1) {
3414 				NXGE_DEBUG_MSG((nxgep, DMA_CTL,
3415 				    "nxge_dma_mem_alloc:ddi_dma_addr_bind "
3416 				    "> 1 cookie"
3417 				    "(staus 0x%x ncookies %d.)", ddi_status,
3418 				    dma_p->ncookies));
3419 				(void) ddi_dma_unbind_handle(dma_p->dma_handle);
3420 				if (dma_p->acc_handle) {
3421 					ddi_dma_mem_free(&dma_p->acc_handle);
3422 					dma_p->acc_handle = NULL;
3423 				}
3424 				ddi_dma_free_handle(&dma_p->dma_handle);
3425 				dma_p->dma_handle = NULL;
3426 				dma_p->acc_handle = NULL;
3427 				return (NXGE_ERROR);
3428 			}
3429 			break;
3430 
3431 		case B_TRUE:
3432