144961713Sgirish /* 244961713Sgirish * CDDL HEADER START 344961713Sgirish * 444961713Sgirish * The contents of this file are subject to the terms of the 544961713Sgirish * Common Development and Distribution License (the "License"). 644961713Sgirish * You may not use this file except in compliance with the License. 744961713Sgirish * 844961713Sgirish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 944961713Sgirish * or http://www.opensolaris.org/os/licensing. 1044961713Sgirish * See the License for the specific language governing permissions 1144961713Sgirish * and limitations under the License. 1244961713Sgirish * 1344961713Sgirish * When distributing Covered Code, include this CDDL HEADER in each 1444961713Sgirish * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1544961713Sgirish * If applicable, add the following below this CDDL HEADER, with the 1644961713Sgirish * fields enclosed by brackets "[]" replaced with your own identifying 1744961713Sgirish * information: Portions Copyright [yyyy] [name of copyright owner] 1844961713Sgirish * 1944961713Sgirish * CDDL HEADER END 2044961713Sgirish */ 2144961713Sgirish /* 2230ac2e7bSml * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 2344961713Sgirish * Use is subject to license terms. 2444961713Sgirish */ 2544961713Sgirish 2644961713Sgirish /* 2744961713Sgirish * SunOs MT STREAMS NIU/Neptune 10Gb Ethernet Device Driver. 2844961713Sgirish */ 2944961713Sgirish #include <sys/nxge/nxge_impl.h> 30678453a8Sspeer #include <sys/nxge/nxge_hio.h> 31678453a8Sspeer #include <sys/nxge/nxge_rxdma.h> 3214ea4bb7Ssd #include <sys/pcie.h> 3344961713Sgirish 3444961713Sgirish uint32_t nxge_use_partition = 0; /* debug partition flag */ 3544961713Sgirish uint32_t nxge_dma_obp_props_only = 1; /* use obp published props */ 3644961713Sgirish uint32_t nxge_use_rdc_intr = 1; /* debug to assign rdc intr */ 3744961713Sgirish /* 38ec090658Sml * PSARC/2007/453 MSI-X interrupt limit override 39ec090658Sml * (This PSARC case is limited to MSI-X vectors 40ec090658Sml * and SPARC platforms only). 4144961713Sgirish */ 42ec090658Sml #if defined(_BIG_ENDIAN) 43ec090658Sml uint32_t nxge_msi_enable = 2; 44ec090658Sml #else 45ec090658Sml uint32_t nxge_msi_enable = 1; 46ec090658Sml #endif 4744961713Sgirish 486f157acbSml /* 496f157acbSml * Software workaround for a Neptune (PCI-E) 506f157acbSml * hardware interrupt bug which the hardware 516f157acbSml * may generate spurious interrupts after the 526f157acbSml * device interrupt handler was removed. If this flag 536f157acbSml * is enabled, the driver will reset the 546f157acbSml * hardware when devices are being detached. 556f157acbSml */ 566f157acbSml uint32_t nxge_peu_reset_enable = 0; 576f157acbSml 58b4d05839Sml /* 59b4d05839Sml * Software workaround for the hardware 60b4d05839Sml * checksum bugs that affect packet transmission 61b4d05839Sml * and receive: 62b4d05839Sml * 63b4d05839Sml * Usage of nxge_cksum_offload: 64b4d05839Sml * 65b4d05839Sml * (1) nxge_cksum_offload = 0 (default): 66b4d05839Sml * - transmits packets: 67b4d05839Sml * TCP: uses the hardware checksum feature. 68b4d05839Sml * UDP: driver will compute the software checksum 69b4d05839Sml * based on the partial checksum computed 70b4d05839Sml * by the IP layer. 71b4d05839Sml * - receives packets 72b4d05839Sml * TCP: marks packets checksum flags based on hardware result. 73b4d05839Sml * UDP: will not mark checksum flags. 74b4d05839Sml * 75b4d05839Sml * (2) nxge_cksum_offload = 1: 76b4d05839Sml * - transmit packets: 77b4d05839Sml * TCP/UDP: uses the hardware checksum feature. 78b4d05839Sml * - receives packets 79b4d05839Sml * TCP/UDP: marks packet checksum flags based on hardware result. 80b4d05839Sml * 81b4d05839Sml * (3) nxge_cksum_offload = 2: 82b4d05839Sml * - The driver will not register its checksum capability. 83b4d05839Sml * Checksum for both TCP and UDP will be computed 84b4d05839Sml * by the stack. 85b4d05839Sml * - The software LSO is not allowed in this case. 86b4d05839Sml * 87b4d05839Sml * (4) nxge_cksum_offload > 2: 88b4d05839Sml * - Will be treated as it is set to 2 89b4d05839Sml * (stack will compute the checksum). 90b4d05839Sml * 91b4d05839Sml * (5) If the hardware bug is fixed, this workaround 92b4d05839Sml * needs to be updated accordingly to reflect 93b4d05839Sml * the new hardware revision. 94b4d05839Sml */ 95b4d05839Sml uint32_t nxge_cksum_offload = 0; 96678453a8Sspeer 9744961713Sgirish /* 9844961713Sgirish * Globals: tunable parameters (/etc/system or adb) 9944961713Sgirish * 10044961713Sgirish */ 10144961713Sgirish uint32_t nxge_rbr_size = NXGE_RBR_RBB_DEFAULT; 10244961713Sgirish uint32_t nxge_rbr_spare_size = 0; 10344961713Sgirish uint32_t nxge_rcr_size = NXGE_RCR_DEFAULT; 10444961713Sgirish uint32_t nxge_tx_ring_size = NXGE_TX_RING_DEFAULT; 105b3a0105bSspeer boolean_t nxge_no_msg = B_TRUE; /* control message display */ 10644961713Sgirish uint32_t nxge_no_link_notify = 0; /* control DL_NOTIFY */ 10744961713Sgirish uint32_t nxge_bcopy_thresh = TX_BCOPY_MAX; 10844961713Sgirish uint32_t nxge_dvma_thresh = TX_FASTDVMA_MIN; 10944961713Sgirish uint32_t nxge_dma_stream_thresh = TX_STREAM_MIN; 11044961713Sgirish uint32_t nxge_jumbo_mtu = TX_JUMBO_MTU; 11144961713Sgirish boolean_t nxge_jumbo_enable = B_FALSE; 11244961713Sgirish uint16_t nxge_rcr_timeout = NXGE_RDC_RCR_TIMEOUT; 11344961713Sgirish uint16_t nxge_rcr_threshold = NXGE_RDC_RCR_THRESHOLD; 1141f8914d5Sml nxge_tx_mode_t nxge_tx_scheme = NXGE_USE_SERIAL; 11544961713Sgirish 11630ac2e7bSml /* MAX LSO size */ 11730ac2e7bSml #define NXGE_LSO_MAXLEN 65535 11830ac2e7bSml uint32_t nxge_lso_max = NXGE_LSO_MAXLEN; 11930ac2e7bSml 12044961713Sgirish 12144961713Sgirish /* 12244961713Sgirish * Add tunable to reduce the amount of time spent in the 12344961713Sgirish * ISR doing Rx Processing. 12444961713Sgirish */ 12544961713Sgirish uint32_t nxge_max_rx_pkts = 1024; 12644961713Sgirish 12744961713Sgirish /* 12844961713Sgirish * Tunables to manage the receive buffer blocks. 12944961713Sgirish * 13044961713Sgirish * nxge_rx_threshold_hi: copy all buffers. 13144961713Sgirish * nxge_rx_bcopy_size_type: receive buffer block size type. 13244961713Sgirish * nxge_rx_threshold_lo: copy only up to tunable block size type. 13344961713Sgirish */ 13444961713Sgirish nxge_rxbuf_threshold_t nxge_rx_threshold_hi = NXGE_RX_COPY_6; 13544961713Sgirish nxge_rxbuf_type_t nxge_rx_buf_size_type = RCR_PKTBUFSZ_0; 13644961713Sgirish nxge_rxbuf_threshold_t nxge_rx_threshold_lo = NXGE_RX_COPY_3; 13744961713Sgirish 138678453a8Sspeer /* Use kmem_alloc() to allocate data buffers. */ 139b1000363Sml #if defined(_BIG_ENDIAN) 140d00f30bbSspeer uint32_t nxge_use_kmem_alloc = 1; 141678453a8Sspeer #else 142d00f30bbSspeer uint32_t nxge_use_kmem_alloc = 0; 143678453a8Sspeer #endif 144678453a8Sspeer 14544961713Sgirish rtrace_t npi_rtracebuf; 14644961713Sgirish 147d6d3405fSml /* 148d6d3405fSml * The hardware sometimes fails to allow enough time for the link partner 149d6d3405fSml * to send an acknowledgement for packets that the hardware sent to it. The 150d6d3405fSml * hardware resends the packets earlier than it should be in those instances. 151d6d3405fSml * This behavior caused some switches to acknowledge the wrong packets 152d6d3405fSml * and it triggered the fatal error. 153d6d3405fSml * This software workaround is to set the replay timer to a value 154d6d3405fSml * suggested by the hardware team. 155d6d3405fSml * 156d6d3405fSml * PCI config space replay timer register: 157d6d3405fSml * The following replay timeout value is 0xc 158d6d3405fSml * for bit 14:18. 159d6d3405fSml */ 160d6d3405fSml #define PCI_REPLAY_TIMEOUT_CFG_OFFSET 0xb8 161d6d3405fSml #define PCI_REPLAY_TIMEOUT_SHIFT 14 162d6d3405fSml 163d6d3405fSml uint32_t nxge_set_replay_timer = 1; 164d6d3405fSml uint32_t nxge_replay_timeout = 0xc; 165d6d3405fSml 166cf020df9Sml /* 167cf020df9Sml * The transmit serialization sometimes causes 168cf020df9Sml * longer sleep before calling the driver transmit 169cf020df9Sml * function as it sleeps longer than it should. 170cf020df9Sml * The performace group suggests that a time wait tunable 171cf020df9Sml * can be used to set the maximum wait time when needed 172cf020df9Sml * and the default is set to 1 tick. 173cf020df9Sml */ 174cf020df9Sml uint32_t nxge_tx_serial_maxsleep = 1; 175cf020df9Sml 17644961713Sgirish #if defined(sun4v) 17744961713Sgirish /* 17844961713Sgirish * Hypervisor N2/NIU services information. 17944961713Sgirish */ 18044961713Sgirish static hsvc_info_t niu_hsvc = { 18144961713Sgirish HSVC_REV_1, NULL, HSVC_GROUP_NIU, NIU_MAJOR_VER, 18244961713Sgirish NIU_MINOR_VER, "nxge" 18344961713Sgirish }; 184678453a8Sspeer 185678453a8Sspeer static int nxge_hsvc_register(p_nxge_t); 18644961713Sgirish #endif 18744961713Sgirish 18844961713Sgirish /* 18944961713Sgirish * Function Prototypes 19044961713Sgirish */ 19144961713Sgirish static int nxge_attach(dev_info_t *, ddi_attach_cmd_t); 19244961713Sgirish static int nxge_detach(dev_info_t *, ddi_detach_cmd_t); 19344961713Sgirish static void nxge_unattach(p_nxge_t); 19419397407SSherry Moore static int nxge_quiesce(dev_info_t *); 19544961713Sgirish 19644961713Sgirish #if NXGE_PROPERTY 19744961713Sgirish static void nxge_remove_hard_properties(p_nxge_t); 19844961713Sgirish #endif 19944961713Sgirish 200678453a8Sspeer /* 201678453a8Sspeer * These two functions are required by nxge_hio.c 202678453a8Sspeer */ 203da14cebeSEric Cheng extern int nxge_m_mmac_remove(void *arg, int slot); 204651ce697SMichael Speer extern void nxge_grp_cleanup(p_nxge_t nxge); 205678453a8Sspeer 20644961713Sgirish static nxge_status_t nxge_setup_system_dma_pages(p_nxge_t); 20744961713Sgirish 20844961713Sgirish static nxge_status_t nxge_setup_mutexes(p_nxge_t); 20944961713Sgirish static void nxge_destroy_mutexes(p_nxge_t); 21044961713Sgirish 21144961713Sgirish static nxge_status_t nxge_map_regs(p_nxge_t nxgep); 21244961713Sgirish static void nxge_unmap_regs(p_nxge_t nxgep); 21344961713Sgirish #ifdef NXGE_DEBUG 21444961713Sgirish static void nxge_test_map_regs(p_nxge_t nxgep); 21544961713Sgirish #endif 21644961713Sgirish 21744961713Sgirish static nxge_status_t nxge_add_intrs(p_nxge_t nxgep); 21844961713Sgirish static void nxge_remove_intrs(p_nxge_t nxgep); 21944961713Sgirish 22044961713Sgirish static nxge_status_t nxge_add_intrs_adv(p_nxge_t nxgep); 22144961713Sgirish static nxge_status_t nxge_add_intrs_adv_type(p_nxge_t, uint32_t); 22244961713Sgirish static nxge_status_t nxge_add_intrs_adv_type_fix(p_nxge_t, uint32_t); 22344961713Sgirish static void nxge_intrs_enable(p_nxge_t nxgep); 22444961713Sgirish static void nxge_intrs_disable(p_nxge_t nxgep); 22544961713Sgirish 22644961713Sgirish static void nxge_suspend(p_nxge_t); 22744961713Sgirish static nxge_status_t nxge_resume(p_nxge_t); 22844961713Sgirish 22944961713Sgirish static nxge_status_t nxge_setup_dev(p_nxge_t); 23044961713Sgirish static void nxge_destroy_dev(p_nxge_t); 23144961713Sgirish 23244961713Sgirish static nxge_status_t nxge_alloc_mem_pool(p_nxge_t); 23344961713Sgirish static void nxge_free_mem_pool(p_nxge_t); 23444961713Sgirish 235678453a8Sspeer nxge_status_t nxge_alloc_rx_mem_pool(p_nxge_t); 23644961713Sgirish static void nxge_free_rx_mem_pool(p_nxge_t); 23744961713Sgirish 238678453a8Sspeer nxge_status_t nxge_alloc_tx_mem_pool(p_nxge_t); 23944961713Sgirish static void nxge_free_tx_mem_pool(p_nxge_t); 24044961713Sgirish 24144961713Sgirish static nxge_status_t nxge_dma_mem_alloc(p_nxge_t, dma_method_t, 24244961713Sgirish struct ddi_dma_attr *, 24344961713Sgirish size_t, ddi_device_acc_attr_t *, uint_t, 24444961713Sgirish p_nxge_dma_common_t); 24544961713Sgirish 24644961713Sgirish static void nxge_dma_mem_free(p_nxge_dma_common_t); 247678453a8Sspeer static void nxge_dma_free_rx_data_buf(p_nxge_dma_common_t); 24844961713Sgirish 24944961713Sgirish static nxge_status_t nxge_alloc_rx_buf_dma(p_nxge_t, uint16_t, 25044961713Sgirish p_nxge_dma_common_t *, size_t, size_t, uint32_t *); 25144961713Sgirish static void nxge_free_rx_buf_dma(p_nxge_t, p_nxge_dma_common_t, uint32_t); 25244961713Sgirish 25344961713Sgirish static nxge_status_t nxge_alloc_rx_cntl_dma(p_nxge_t, uint16_t, 25444961713Sgirish p_nxge_dma_common_t *, size_t); 25544961713Sgirish static void nxge_free_rx_cntl_dma(p_nxge_t, p_nxge_dma_common_t); 25644961713Sgirish 257678453a8Sspeer extern nxge_status_t nxge_alloc_tx_buf_dma(p_nxge_t, uint16_t, 25844961713Sgirish p_nxge_dma_common_t *, size_t, size_t, uint32_t *); 25944961713Sgirish static void nxge_free_tx_buf_dma(p_nxge_t, p_nxge_dma_common_t, uint32_t); 26044961713Sgirish 261678453a8Sspeer extern nxge_status_t nxge_alloc_tx_cntl_dma(p_nxge_t, uint16_t, 26244961713Sgirish p_nxge_dma_common_t *, 26344961713Sgirish size_t); 26444961713Sgirish static void nxge_free_tx_cntl_dma(p_nxge_t, p_nxge_dma_common_t); 26544961713Sgirish 26644961713Sgirish static int nxge_init_common_dev(p_nxge_t); 26744961713Sgirish static void nxge_uninit_common_dev(p_nxge_t); 2684045d941Ssowmini extern int nxge_param_set_mac(p_nxge_t, queue_t *, mblk_t *, 2694045d941Ssowmini char *, caddr_t); 27044961713Sgirish 27144961713Sgirish /* 27244961713Sgirish * The next declarations are for the GLDv3 interface. 27344961713Sgirish */ 27444961713Sgirish static int nxge_m_start(void *); 27544961713Sgirish static void nxge_m_stop(void *); 27644961713Sgirish static int nxge_m_multicst(void *, boolean_t, const uint8_t *); 27744961713Sgirish static int nxge_m_promisc(void *, boolean_t); 27844961713Sgirish static void nxge_m_ioctl(void *, queue_t *, mblk_t *); 27944961713Sgirish static nxge_status_t nxge_mac_register(p_nxge_t); 280da14cebeSEric Cheng static int nxge_altmac_set(p_nxge_t nxgep, uint8_t *mac_addr, 281da14cebeSEric Cheng int slot, int rdctbl, boolean_t usetbl); 282da14cebeSEric Cheng void nxge_mmac_kstat_update(p_nxge_t nxgep, int slot, 28358324dfcSspeer boolean_t factory); 284da14cebeSEric Cheng #if defined(sun4v) 285da14cebeSEric Cheng extern mblk_t *nxge_m_tx(void *arg, mblk_t *mp); 286da14cebeSEric Cheng #endif 287da14cebeSEric Cheng 288da14cebeSEric Cheng static void nxge_m_getfactaddr(void *, uint_t, uint8_t *); 2891bd6825cSml static boolean_t nxge_m_getcapab(void *, mac_capab_t, void *); 2901bd6825cSml static int nxge_m_setprop(void *, const char *, mac_prop_id_t, 2911bd6825cSml uint_t, const void *); 2921bd6825cSml static int nxge_m_getprop(void *, const char *, mac_prop_id_t, 293afdda45fSVasumathi Sundaram - Sun Microsystems uint_t, uint_t, void *, uint_t *); 2941bd6825cSml static int nxge_set_priv_prop(nxge_t *, const char *, uint_t, 2951bd6825cSml const void *); 2964045d941Ssowmini static int nxge_get_priv_prop(nxge_t *, const char *, uint_t, uint_t, 297afdda45fSVasumathi Sundaram - Sun Microsystems void *, uint_t *); 2984045d941Ssowmini static int nxge_get_def_val(nxge_t *, mac_prop_id_t, uint_t, void *); 299da14cebeSEric Cheng static void nxge_fill_ring(void *, mac_ring_type_t, const int, const int, 300da14cebeSEric Cheng mac_ring_info_t *, mac_ring_handle_t); 301da14cebeSEric Cheng static void nxge_group_add_ring(mac_group_driver_t, mac_ring_driver_t, 302da14cebeSEric Cheng mac_ring_type_t); 303da14cebeSEric Cheng static void nxge_group_rem_ring(mac_group_driver_t, mac_ring_driver_t, 304da14cebeSEric Cheng mac_ring_type_t); 3054045d941Ssowmini 3066f157acbSml static void nxge_niu_peu_reset(p_nxge_t nxgep); 307d6d3405fSml static void nxge_set_pci_replay_timeout(nxge_t *); 3084045d941Ssowmini 3094045d941Ssowmini mac_priv_prop_t nxge_priv_props[] = { 3104045d941Ssowmini {"_adv_10gfdx_cap", MAC_PROP_PERM_RW}, 3114045d941Ssowmini {"_adv_pause_cap", MAC_PROP_PERM_RW}, 3124045d941Ssowmini {"_function_number", MAC_PROP_PERM_READ}, 3134045d941Ssowmini {"_fw_version", MAC_PROP_PERM_READ}, 3144045d941Ssowmini {"_port_mode", MAC_PROP_PERM_READ}, 3154045d941Ssowmini {"_hot_swap_phy", MAC_PROP_PERM_READ}, 3164045d941Ssowmini {"_accept_jumbo", MAC_PROP_PERM_RW}, 3174045d941Ssowmini {"_rxdma_intr_time", MAC_PROP_PERM_RW}, 3184045d941Ssowmini {"_rxdma_intr_pkts", MAC_PROP_PERM_RW}, 3194045d941Ssowmini {"_class_opt_ipv4_tcp", MAC_PROP_PERM_RW}, 3204045d941Ssowmini {"_class_opt_ipv4_udp", MAC_PROP_PERM_RW}, 3214045d941Ssowmini {"_class_opt_ipv4_ah", MAC_PROP_PERM_RW}, 3224045d941Ssowmini {"_class_opt_ipv4_sctp", MAC_PROP_PERM_RW}, 3234045d941Ssowmini {"_class_opt_ipv6_tcp", MAC_PROP_PERM_RW}, 3244045d941Ssowmini {"_class_opt_ipv6_udp", MAC_PROP_PERM_RW}, 3254045d941Ssowmini {"_class_opt_ipv6_ah", MAC_PROP_PERM_RW}, 3264045d941Ssowmini {"_class_opt_ipv6_sctp", MAC_PROP_PERM_RW}, 3274045d941Ssowmini {"_soft_lso_enable", MAC_PROP_PERM_RW} 3284045d941Ssowmini }; 3294045d941Ssowmini 3304045d941Ssowmini #define NXGE_MAX_PRIV_PROPS \ 3314045d941Ssowmini (sizeof (nxge_priv_props)/sizeof (mac_priv_prop_t)) 3321bd6825cSml 33344961713Sgirish #define NXGE_NEPTUNE_MAGIC 0x4E584745UL 33444961713Sgirish #define MAX_DUMP_SZ 256 33544961713Sgirish 3361bd6825cSml #define NXGE_M_CALLBACK_FLAGS \ 337da14cebeSEric Cheng (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP) 33844961713Sgirish 339678453a8Sspeer mac_callbacks_t nxge_m_callbacks = { 34044961713Sgirish NXGE_M_CALLBACK_FLAGS, 34144961713Sgirish nxge_m_stat, 34244961713Sgirish nxge_m_start, 34344961713Sgirish nxge_m_stop, 34444961713Sgirish nxge_m_promisc, 34544961713Sgirish nxge_m_multicst, 346da14cebeSEric Cheng NULL, 347da14cebeSEric Cheng NULL, 34844961713Sgirish nxge_m_ioctl, 3491bd6825cSml nxge_m_getcapab, 3501bd6825cSml NULL, 3511bd6825cSml NULL, 3521bd6825cSml nxge_m_setprop, 3531bd6825cSml nxge_m_getprop 35444961713Sgirish }; 35544961713Sgirish 35644961713Sgirish void 35744961713Sgirish nxge_err_inject(p_nxge_t, queue_t *, mblk_t *); 35844961713Sgirish 359ec090658Sml /* PSARC/2007/453 MSI-X interrupt limit override. */ 360ec090658Sml #define NXGE_MSIX_REQUEST_10G 8 361ec090658Sml #define NXGE_MSIX_REQUEST_1G 2 362ec090658Sml static int nxge_create_msi_property(p_nxge_t); 363*ef755e7aStc /* 364*ef755e7aStc * For applications that care about the 365*ef755e7aStc * latency, it was requested by PAE and the 366*ef755e7aStc * customers that the driver has tunables that 367*ef755e7aStc * allow the user to tune it to a higher number 368*ef755e7aStc * interrupts to spread the interrupts among 369*ef755e7aStc * multiple channels. The DDI framework limits 370*ef755e7aStc * the maximum number of MSI-X resources to allocate 371*ef755e7aStc * to 8 (ddi_msix_alloc_limit). If more than 8 372*ef755e7aStc * is set, ddi_msix_alloc_limit must be set accordingly. 373*ef755e7aStc * The default number of MSI interrupts are set to 374*ef755e7aStc * 8 for 10G and 2 for 1G link. 375*ef755e7aStc */ 376*ef755e7aStc #define NXGE_MSIX_MAX_ALLOWED 32 377*ef755e7aStc uint32_t nxge_msix_10g_intrs = NXGE_MSIX_REQUEST_10G; 378*ef755e7aStc uint32_t nxge_msix_1g_intrs = NXGE_MSIX_REQUEST_1G; 379ec090658Sml 38044961713Sgirish /* 38144961713Sgirish * These global variables control the message 38244961713Sgirish * output. 38344961713Sgirish */ 38444961713Sgirish out_dbgmsg_t nxge_dbgmsg_out = DBG_CONSOLE | STR_LOG; 385678453a8Sspeer uint64_t nxge_debug_level; 38644961713Sgirish 38744961713Sgirish /* 38844961713Sgirish * This list contains the instance structures for the Neptune 38944961713Sgirish * devices present in the system. The lock exists to guarantee 39044961713Sgirish * mutually exclusive access to the list. 39144961713Sgirish */ 39244961713Sgirish void *nxge_list = NULL; 39344961713Sgirish 39444961713Sgirish void *nxge_hw_list = NULL; 39544961713Sgirish nxge_os_mutex_t nxge_common_lock; 39644961713Sgirish 39744961713Sgirish extern uint64_t npi_debug_level; 39844961713Sgirish 39944961713Sgirish extern nxge_status_t nxge_ldgv_init(p_nxge_t, int *, int *); 40044961713Sgirish extern nxge_status_t nxge_ldgv_init_n2(p_nxge_t, int *, int *); 40144961713Sgirish extern nxge_status_t nxge_ldgv_uninit(p_nxge_t); 40244961713Sgirish extern nxge_status_t nxge_intr_ldgv_init(p_nxge_t); 40344961713Sgirish extern void nxge_fm_init(p_nxge_t, 40444961713Sgirish ddi_device_acc_attr_t *, 40544961713Sgirish ddi_device_acc_attr_t *, 40644961713Sgirish ddi_dma_attr_t *); 40744961713Sgirish extern void nxge_fm_fini(p_nxge_t); 40858324dfcSspeer extern npi_status_t npi_mac_altaddr_disable(npi_handle_t, uint8_t, uint8_t); 40944961713Sgirish 41044961713Sgirish /* 41144961713Sgirish * Count used to maintain the number of buffers being used 41244961713Sgirish * by Neptune instances and loaned up to the upper layers. 41344961713Sgirish */ 41444961713Sgirish uint32_t nxge_mblks_pending = 0; 41544961713Sgirish 41644961713Sgirish /* 41744961713Sgirish * Device register access attributes for PIO. 41844961713Sgirish */ 41944961713Sgirish static ddi_device_acc_attr_t nxge_dev_reg_acc_attr = { 42044961713Sgirish DDI_DEVICE_ATTR_V0, 42144961713Sgirish DDI_STRUCTURE_LE_ACC, 42244961713Sgirish DDI_STRICTORDER_ACC, 42344961713Sgirish }; 42444961713Sgirish 42544961713Sgirish /* 42644961713Sgirish * Device descriptor access attributes for DMA. 42744961713Sgirish */ 42844961713Sgirish static ddi_device_acc_attr_t nxge_dev_desc_dma_acc_attr = { 42944961713Sgirish DDI_DEVICE_ATTR_V0, 43044961713Sgirish DDI_STRUCTURE_LE_ACC, 43144961713Sgirish DDI_STRICTORDER_ACC 43244961713Sgirish }; 43344961713Sgirish 43444961713Sgirish /* 43544961713Sgirish * Device buffer access attributes for DMA. 43644961713Sgirish */ 43744961713Sgirish static ddi_device_acc_attr_t nxge_dev_buf_dma_acc_attr = { 43844961713Sgirish DDI_DEVICE_ATTR_V0, 43944961713Sgirish DDI_STRUCTURE_BE_ACC, 44044961713Sgirish DDI_STRICTORDER_ACC 44144961713Sgirish }; 44244961713Sgirish 44344961713Sgirish ddi_dma_attr_t nxge_desc_dma_attr = { 44444961713Sgirish DMA_ATTR_V0, /* version number. */ 44544961713Sgirish 0, /* low address */ 44644961713Sgirish 0xffffffffffffffff, /* high address */ 44744961713Sgirish 0xffffffffffffffff, /* address counter max */ 44844961713Sgirish #ifndef NIU_PA_WORKAROUND 44944961713Sgirish 0x100000, /* alignment */ 45044961713Sgirish #else 45144961713Sgirish 0x2000, 45244961713Sgirish #endif 45344961713Sgirish 0xfc00fc, /* dlim_burstsizes */ 45444961713Sgirish 0x1, /* minimum transfer size */ 45544961713Sgirish 0xffffffffffffffff, /* maximum transfer size */ 45644961713Sgirish 0xffffffffffffffff, /* maximum segment size */ 45744961713Sgirish 1, /* scatter/gather list length */ 45844961713Sgirish (unsigned int) 1, /* granularity */ 45944961713Sgirish 0 /* attribute flags */ 46044961713Sgirish }; 46144961713Sgirish 46244961713Sgirish ddi_dma_attr_t nxge_tx_dma_attr = { 46344961713Sgirish DMA_ATTR_V0, /* version number. */ 46444961713Sgirish 0, /* low address */ 46544961713Sgirish 0xffffffffffffffff, /* high address */ 46644961713Sgirish 0xffffffffffffffff, /* address counter max */ 46744961713Sgirish #if defined(_BIG_ENDIAN) 46844961713Sgirish 0x2000, /* alignment */ 46944961713Sgirish #else 47044961713Sgirish 0x1000, /* alignment */ 47144961713Sgirish #endif 47244961713Sgirish 0xfc00fc, /* dlim_burstsizes */ 47344961713Sgirish 0x1, /* minimum transfer size */ 47444961713Sgirish 0xffffffffffffffff, /* maximum transfer size */ 47544961713Sgirish 0xffffffffffffffff, /* maximum segment size */ 47644961713Sgirish 5, /* scatter/gather list length */ 47744961713Sgirish (unsigned int) 1, /* granularity */ 47844961713Sgirish 0 /* attribute flags */ 47944961713Sgirish }; 48044961713Sgirish 48144961713Sgirish ddi_dma_attr_t nxge_rx_dma_attr = { 48244961713Sgirish DMA_ATTR_V0, /* version number. */ 48344961713Sgirish 0, /* low address */ 48444961713Sgirish 0xffffffffffffffff, /* high address */ 48544961713Sgirish 0xffffffffffffffff, /* address counter max */ 48644961713Sgirish 0x2000, /* alignment */ 48744961713Sgirish 0xfc00fc, /* dlim_burstsizes */ 48844961713Sgirish 0x1, /* minimum transfer size */ 48944961713Sgirish 0xffffffffffffffff, /* maximum transfer size */ 49044961713Sgirish 0xffffffffffffffff, /* maximum segment size */ 49144961713Sgirish 1, /* scatter/gather list length */ 49244961713Sgirish (unsigned int) 1, /* granularity */ 4930e2bd521Ssbehera DDI_DMA_RELAXED_ORDERING /* attribute flags */ 49444961713Sgirish }; 49544961713Sgirish 49644961713Sgirish ddi_dma_lim_t nxge_dma_limits = { 49744961713Sgirish (uint_t)0, /* dlim_addr_lo */ 49844961713Sgirish (uint_t)0xffffffff, /* dlim_addr_hi */ 49944961713Sgirish (uint_t)0xffffffff, /* dlim_cntr_max */ 50044961713Sgirish (uint_t)0xfc00fc, /* dlim_burstsizes for 32 and 64 bit xfers */ 50144961713Sgirish 0x1, /* dlim_minxfer */ 50244961713Sgirish 1024 /* dlim_speed */ 50344961713Sgirish }; 50444961713Sgirish 50544961713Sgirish dma_method_t nxge_force_dma = DVMA; 50644961713Sgirish 50744961713Sgirish /* 50844961713Sgirish * dma chunk sizes. 50944961713Sgirish * 51044961713Sgirish * Try to allocate the largest possible size 51144961713Sgirish * so that fewer number of dma chunks would be managed 51244961713Sgirish */ 51344961713Sgirish #ifdef NIU_PA_WORKAROUND 51444961713Sgirish size_t alloc_sizes [] = {0x2000}; 51544961713Sgirish #else 51644961713Sgirish size_t alloc_sizes [] = {0x1000, 0x2000, 0x4000, 0x8000, 51744961713Sgirish 0x10000, 0x20000, 0x40000, 0x80000, 51830ac2e7bSml 0x100000, 0x200000, 0x400000, 0x800000, 51930ac2e7bSml 0x1000000, 0x2000000, 0x4000000}; 52044961713Sgirish #endif 52144961713Sgirish 52244961713Sgirish /* 52344961713Sgirish * Translate "dev_t" to a pointer to the associated "dev_info_t". 52444961713Sgirish */ 52544961713Sgirish 526678453a8Sspeer extern void nxge_get_environs(nxge_t *); 527678453a8Sspeer 52844961713Sgirish static int 52944961713Sgirish nxge_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 53044961713Sgirish { 53144961713Sgirish p_nxge_t nxgep = NULL; 53244961713Sgirish int instance; 53344961713Sgirish int status = DDI_SUCCESS; 53444961713Sgirish uint8_t portn; 53558324dfcSspeer nxge_mmac_t *mmac_info; 5367b1f684aSSriharsha Basavapatna p_nxge_param_t param_arr; 53744961713Sgirish 53844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_attach")); 53944961713Sgirish 54044961713Sgirish /* 54144961713Sgirish * Get the device instance since we'll need to setup 54244961713Sgirish * or retrieve a soft state for this instance. 54344961713Sgirish */ 54444961713Sgirish instance = ddi_get_instance(dip); 54544961713Sgirish 54644961713Sgirish switch (cmd) { 54744961713Sgirish case DDI_ATTACH: 54844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_ATTACH")); 54944961713Sgirish break; 55044961713Sgirish 55144961713Sgirish case DDI_RESUME: 55244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_RESUME")); 55344961713Sgirish nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance); 55444961713Sgirish if (nxgep == NULL) { 55544961713Sgirish status = DDI_FAILURE; 55644961713Sgirish break; 55744961713Sgirish } 55844961713Sgirish if (nxgep->dip != dip) { 55944961713Sgirish status = DDI_FAILURE; 56044961713Sgirish break; 56144961713Sgirish } 56244961713Sgirish if (nxgep->suspended == DDI_PM_SUSPEND) { 56344961713Sgirish status = ddi_dev_is_needed(nxgep->dip, 0, 1); 56444961713Sgirish } else { 56556d930aeSspeer status = nxge_resume(nxgep); 56644961713Sgirish } 56744961713Sgirish goto nxge_attach_exit; 56844961713Sgirish 56944961713Sgirish case DDI_PM_RESUME: 57044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_PM_RESUME")); 57144961713Sgirish nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance); 57244961713Sgirish if (nxgep == NULL) { 57344961713Sgirish status = DDI_FAILURE; 57444961713Sgirish break; 57544961713Sgirish } 57644961713Sgirish if (nxgep->dip != dip) { 57744961713Sgirish status = DDI_FAILURE; 57844961713Sgirish break; 57944961713Sgirish } 58056d930aeSspeer status = nxge_resume(nxgep); 58144961713Sgirish goto nxge_attach_exit; 58244961713Sgirish 58344961713Sgirish default: 58444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing unknown")); 58544961713Sgirish status = DDI_FAILURE; 58644961713Sgirish goto nxge_attach_exit; 58744961713Sgirish } 58844961713Sgirish 58944961713Sgirish 59044961713Sgirish if (ddi_soft_state_zalloc(nxge_list, instance) == DDI_FAILURE) { 59144961713Sgirish status = DDI_FAILURE; 59244961713Sgirish goto nxge_attach_exit; 59344961713Sgirish } 59444961713Sgirish 59544961713Sgirish nxgep = ddi_get_soft_state(nxge_list, instance); 59644961713Sgirish if (nxgep == NULL) { 5972e59129aSraghus status = NXGE_ERROR; 5982e59129aSraghus goto nxge_attach_fail2; 59944961713Sgirish } 60044961713Sgirish 60198ecde52Stm nxgep->nxge_magic = NXGE_MAGIC; 60298ecde52Stm 60344961713Sgirish nxgep->drv_state = 0; 60444961713Sgirish nxgep->dip = dip; 60544961713Sgirish nxgep->instance = instance; 60644961713Sgirish nxgep->p_dip = ddi_get_parent(dip); 60744961713Sgirish nxgep->nxge_debug_level = nxge_debug_level; 60844961713Sgirish npi_debug_level = nxge_debug_level; 60944961713Sgirish 610678453a8Sspeer /* Are we a guest running in a Hybrid I/O environment? */ 611678453a8Sspeer nxge_get_environs(nxgep); 61244961713Sgirish 61344961713Sgirish status = nxge_map_regs(nxgep); 614678453a8Sspeer 61544961713Sgirish if (status != NXGE_OK) { 61644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_map_regs failed")); 6172e59129aSraghus goto nxge_attach_fail3; 61844961713Sgirish } 61944961713Sgirish 620678453a8Sspeer nxge_fm_init(nxgep, &nxge_dev_reg_acc_attr, 621678453a8Sspeer &nxge_dev_desc_dma_acc_attr, 622678453a8Sspeer &nxge_rx_dma_attr); 623678453a8Sspeer 624678453a8Sspeer /* Create & initialize the per-Neptune data structure */ 625678453a8Sspeer /* (even if we're a guest). */ 62644961713Sgirish status = nxge_init_common_dev(nxgep); 62744961713Sgirish if (status != NXGE_OK) { 62844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6294045d941Ssowmini "nxge_init_common_dev failed")); 6302e59129aSraghus goto nxge_attach_fail4; 63144961713Sgirish } 63244961713Sgirish 633d6d3405fSml /* 634d6d3405fSml * Software workaround: set the replay timer. 635d6d3405fSml */ 636d6d3405fSml if (nxgep->niu_type != N2_NIU) { 637d6d3405fSml nxge_set_pci_replay_timeout(nxgep); 638d6d3405fSml } 639da14cebeSEric Cheng #if defined(sun4v) 640da14cebeSEric Cheng if (isLDOMguest(nxgep)) { 641da14cebeSEric Cheng nxge_m_callbacks.mc_tx = nxge_m_tx; 642da14cebeSEric Cheng } 643da14cebeSEric Cheng #endif 644d6d3405fSml 645678453a8Sspeer #if defined(sun4v) 646678453a8Sspeer /* This is required by nxge_hio_init(), which follows. */ 647678453a8Sspeer if ((status = nxge_hsvc_register(nxgep)) != DDI_SUCCESS) 6489d5b8bc5SMichael Speer goto nxge_attach_fail4; 649678453a8Sspeer #endif 650678453a8Sspeer 651678453a8Sspeer if ((status = nxge_hio_init(nxgep)) != NXGE_OK) { 652678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6534045d941Ssowmini "nxge_hio_init failed")); 654678453a8Sspeer goto nxge_attach_fail4; 655678453a8Sspeer } 656678453a8Sspeer 65759ac0c16Sdavemq if (nxgep->niu_type == NEPTUNE_2_10GF) { 65859ac0c16Sdavemq if (nxgep->function_num > 1) { 6594202ea4bSsbehera NXGE_DEBUG_MSG((nxgep, DDI_CTL, "Unsupported" 66059ac0c16Sdavemq " function %d. Only functions 0 and 1 are " 66159ac0c16Sdavemq "supported for this card.", nxgep->function_num)); 66259ac0c16Sdavemq status = NXGE_ERROR; 6632e59129aSraghus goto nxge_attach_fail4; 66459ac0c16Sdavemq } 66559ac0c16Sdavemq } 66659ac0c16Sdavemq 667678453a8Sspeer if (isLDOMguest(nxgep)) { 668678453a8Sspeer /* 669678453a8Sspeer * Use the function number here. 670678453a8Sspeer */ 671678453a8Sspeer nxgep->mac.portnum = nxgep->function_num; 672678453a8Sspeer nxgep->mac.porttype = PORT_TYPE_LOGICAL; 673678453a8Sspeer 674678453a8Sspeer /* XXX We'll set the MAC address counts to 1 for now. */ 675678453a8Sspeer mmac_info = &nxgep->nxge_mmac_info; 676678453a8Sspeer mmac_info->num_mmac = 1; 677678453a8Sspeer mmac_info->naddrfree = 1; 67858324dfcSspeer } else { 679678453a8Sspeer portn = NXGE_GET_PORT_NUM(nxgep->function_num); 680678453a8Sspeer nxgep->mac.portnum = portn; 681678453a8Sspeer if ((portn == 0) || (portn == 1)) 682678453a8Sspeer nxgep->mac.porttype = PORT_TYPE_XMAC; 683678453a8Sspeer else 684678453a8Sspeer nxgep->mac.porttype = PORT_TYPE_BMAC; 685678453a8Sspeer /* 686678453a8Sspeer * Neptune has 4 ports, the first 2 ports use XMAC (10G MAC) 687678453a8Sspeer * internally, the rest 2 ports use BMAC (1G "Big" MAC). 688678453a8Sspeer * The two types of MACs have different characterizations. 689678453a8Sspeer */ 690678453a8Sspeer mmac_info = &nxgep->nxge_mmac_info; 691678453a8Sspeer if (nxgep->function_num < 2) { 692678453a8Sspeer mmac_info->num_mmac = XMAC_MAX_ALT_ADDR_ENTRY; 693678453a8Sspeer mmac_info->naddrfree = XMAC_MAX_ALT_ADDR_ENTRY; 694678453a8Sspeer } else { 695678453a8Sspeer mmac_info->num_mmac = BMAC_MAX_ALT_ADDR_ENTRY; 696678453a8Sspeer mmac_info->naddrfree = BMAC_MAX_ALT_ADDR_ENTRY; 697678453a8Sspeer } 69858324dfcSspeer } 69944961713Sgirish /* 70044961713Sgirish * Setup the Ndd parameters for the this instance. 70144961713Sgirish */ 70244961713Sgirish nxge_init_param(nxgep); 70344961713Sgirish 70444961713Sgirish /* 70544961713Sgirish * Setup Register Tracing Buffer. 70644961713Sgirish */ 70744961713Sgirish npi_rtrace_buf_init((rtrace_t *)&npi_rtracebuf); 70844961713Sgirish 70944961713Sgirish /* init stats ptr */ 71044961713Sgirish nxge_init_statsp(nxgep); 71156d930aeSspeer 7122e59129aSraghus /* 713678453a8Sspeer * Copy the vpd info from eeprom to a local data 714678453a8Sspeer * structure, and then check its validity. 7152e59129aSraghus */ 716678453a8Sspeer if (!isLDOMguest(nxgep)) { 717678453a8Sspeer int *regp; 718678453a8Sspeer uint_t reglen; 719678453a8Sspeer int rv; 72056d930aeSspeer 721678453a8Sspeer nxge_vpd_info_get(nxgep); 72244961713Sgirish 723678453a8Sspeer /* Find the NIU config handle. */ 724678453a8Sspeer rv = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, 725678453a8Sspeer ddi_get_parent(nxgep->dip), DDI_PROP_DONTPASS, 726678453a8Sspeer "reg", ®p, ®len); 727678453a8Sspeer 728678453a8Sspeer if (rv != DDI_PROP_SUCCESS) { 729678453a8Sspeer goto nxge_attach_fail5; 730678453a8Sspeer } 731678453a8Sspeer /* 732678453a8Sspeer * The address_hi, that is the first int, in the reg 733678453a8Sspeer * property consists of config handle, but need to remove 734678453a8Sspeer * the bits 28-31 which are OBP specific info. 735678453a8Sspeer */ 736678453a8Sspeer nxgep->niu_cfg_hdl = (*regp) & 0xFFFFFFF; 737678453a8Sspeer ddi_prop_free(regp); 73844961713Sgirish } 73944961713Sgirish 740678453a8Sspeer if (isLDOMguest(nxgep)) { 741678453a8Sspeer uchar_t *prop_val; 742678453a8Sspeer uint_t prop_len; 7437b1f684aSSriharsha Basavapatna uint32_t max_frame_size; 74444961713Sgirish 745678453a8Sspeer extern void nxge_get_logical_props(p_nxge_t); 746678453a8Sspeer 747678453a8Sspeer nxgep->statsp->mac_stats.xcvr_inuse = LOGICAL_XCVR; 748678453a8Sspeer nxgep->mac.portmode = PORT_LOGICAL; 749678453a8Sspeer (void) ddi_prop_update_string(DDI_DEV_T_NONE, nxgep->dip, 750678453a8Sspeer "phy-type", "virtual transceiver"); 751678453a8Sspeer 752678453a8Sspeer nxgep->nports = 1; 753678453a8Sspeer nxgep->board_ver = 0; /* XXX What? */ 754678453a8Sspeer 755678453a8Sspeer /* 756678453a8Sspeer * local-mac-address property gives us info on which 757678453a8Sspeer * specific MAC address the Hybrid resource is associated 758678453a8Sspeer * with. 759678453a8Sspeer */ 760678453a8Sspeer if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0, 761678453a8Sspeer "local-mac-address", &prop_val, 762678453a8Sspeer &prop_len) != DDI_PROP_SUCCESS) { 763678453a8Sspeer goto nxge_attach_fail5; 764678453a8Sspeer } 765678453a8Sspeer if (prop_len != ETHERADDRL) { 766678453a8Sspeer ddi_prop_free(prop_val); 767678453a8Sspeer goto nxge_attach_fail5; 768678453a8Sspeer } 769678453a8Sspeer ether_copy(prop_val, nxgep->hio_mac_addr); 770678453a8Sspeer ddi_prop_free(prop_val); 771678453a8Sspeer nxge_get_logical_props(nxgep); 772678453a8Sspeer 7737b1f684aSSriharsha Basavapatna /* 7747b1f684aSSriharsha Basavapatna * Enable Jumbo property based on the "max-frame-size" 7757b1f684aSSriharsha Basavapatna * property value. 7767b1f684aSSriharsha Basavapatna */ 7777b1f684aSSriharsha Basavapatna max_frame_size = ddi_prop_get_int(DDI_DEV_T_ANY, 7787b1f684aSSriharsha Basavapatna nxgep->dip, DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, 7797b1f684aSSriharsha Basavapatna "max-frame-size", NXGE_MTU_DEFAULT_MAX); 7807b1f684aSSriharsha Basavapatna if ((max_frame_size > NXGE_MTU_DEFAULT_MAX) && 7817b1f684aSSriharsha Basavapatna (max_frame_size <= TX_JUMBO_MTU)) { 7827b1f684aSSriharsha Basavapatna param_arr = nxgep->param_arr; 7837b1f684aSSriharsha Basavapatna 7847b1f684aSSriharsha Basavapatna param_arr[param_accept_jumbo].value = 1; 7857b1f684aSSriharsha Basavapatna nxgep->mac.is_jumbo = B_TRUE; 7867b1f684aSSriharsha Basavapatna nxgep->mac.maxframesize = (uint16_t)max_frame_size; 7877b1f684aSSriharsha Basavapatna nxgep->mac.default_mtu = nxgep->mac.maxframesize - 7887b1f684aSSriharsha Basavapatna NXGE_EHEADER_VLAN_CRC; 7897b1f684aSSriharsha Basavapatna } 790678453a8Sspeer } else { 791678453a8Sspeer status = nxge_xcvr_find(nxgep); 792678453a8Sspeer 793678453a8Sspeer if (status != NXGE_OK) { 794678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_attach: " 7954045d941Ssowmini " Couldn't determine card type" 7964045d941Ssowmini " .... exit ")); 797678453a8Sspeer goto nxge_attach_fail5; 798678453a8Sspeer } 799678453a8Sspeer 800678453a8Sspeer status = nxge_get_config_properties(nxgep); 801678453a8Sspeer 802678453a8Sspeer if (status != NXGE_OK) { 803678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 8044045d941Ssowmini "get_hw create failed")); 805678453a8Sspeer goto nxge_attach_fail; 806678453a8Sspeer } 80744961713Sgirish } 80844961713Sgirish 80944961713Sgirish /* 81044961713Sgirish * Setup the Kstats for the driver. 81144961713Sgirish */ 81244961713Sgirish nxge_setup_kstats(nxgep); 81344961713Sgirish 814678453a8Sspeer if (!isLDOMguest(nxgep)) 815678453a8Sspeer nxge_setup_param(nxgep); 81644961713Sgirish 81744961713Sgirish status = nxge_setup_system_dma_pages(nxgep); 81844961713Sgirish if (status != NXGE_OK) { 81944961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "set dma page failed")); 82044961713Sgirish goto nxge_attach_fail; 82144961713Sgirish } 82244961713Sgirish 82344961713Sgirish nxge_hw_id_init(nxgep); 824678453a8Sspeer 825678453a8Sspeer if (!isLDOMguest(nxgep)) 826678453a8Sspeer nxge_hw_init_niu_common(nxgep); 82744961713Sgirish 82844961713Sgirish status = nxge_setup_mutexes(nxgep); 82944961713Sgirish if (status != NXGE_OK) { 83044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "set mutex failed")); 83144961713Sgirish goto nxge_attach_fail; 83244961713Sgirish } 83344961713Sgirish 834678453a8Sspeer #if defined(sun4v) 835678453a8Sspeer if (isLDOMguest(nxgep)) { 836678453a8Sspeer /* Find our VR & channel sets. */ 837678453a8Sspeer status = nxge_hio_vr_add(nxgep); 838330cd344SMichael Speer if (status != NXGE_OK) { 839330cd344SMichael Speer NXGE_DEBUG_MSG((nxgep, DDI_CTL, 840330cd344SMichael Speer "nxge_hio_vr_add failed")); 841330cd344SMichael Speer (void) hsvc_unregister(&nxgep->niu_hsvc); 842330cd344SMichael Speer nxgep->niu_hsvc_available = B_FALSE; 843330cd344SMichael Speer } 844678453a8Sspeer goto nxge_attach_exit; 845678453a8Sspeer } 846678453a8Sspeer #endif 847678453a8Sspeer 84844961713Sgirish status = nxge_setup_dev(nxgep); 84944961713Sgirish if (status != DDI_SUCCESS) { 85044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "set dev failed")); 85144961713Sgirish goto nxge_attach_fail; 85244961713Sgirish } 85344961713Sgirish 85444961713Sgirish status = nxge_add_intrs(nxgep); 85544961713Sgirish if (status != DDI_SUCCESS) { 85644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "add_intr failed")); 85744961713Sgirish goto nxge_attach_fail; 85844961713Sgirish } 859330cd344SMichael Speer 86000161856Syc /* If a guest, register with vio_net instead. */ 8612e59129aSraghus if ((status = nxge_mac_register(nxgep)) != NXGE_OK) { 86244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 863678453a8Sspeer "unable to register to mac layer (%d)", status)); 86444961713Sgirish goto nxge_attach_fail; 86544961713Sgirish } 86644961713Sgirish 86744961713Sgirish mac_link_update(nxgep->mach, LINK_STATE_UNKNOWN); 86844961713Sgirish 869678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DDI_CTL, 870678453a8Sspeer "registered to mac (instance %d)", instance)); 87144961713Sgirish 87200161856Syc /* nxge_link_monitor calls xcvr.check_link recursively */ 87344961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 87444961713Sgirish 87544961713Sgirish goto nxge_attach_exit; 87644961713Sgirish 87744961713Sgirish nxge_attach_fail: 87844961713Sgirish nxge_unattach(nxgep); 8792e59129aSraghus goto nxge_attach_fail1; 8802e59129aSraghus 8812e59129aSraghus nxge_attach_fail5: 8822e59129aSraghus /* 8832e59129aSraghus * Tear down the ndd parameters setup. 8842e59129aSraghus */ 8852e59129aSraghus nxge_destroy_param(nxgep); 8862e59129aSraghus 8872e59129aSraghus /* 8882e59129aSraghus * Tear down the kstat setup. 8892e59129aSraghus */ 8902e59129aSraghus nxge_destroy_kstats(nxgep); 8912e59129aSraghus 8922e59129aSraghus nxge_attach_fail4: 8932e59129aSraghus if (nxgep->nxge_hw_p) { 8942e59129aSraghus nxge_uninit_common_dev(nxgep); 8952e59129aSraghus nxgep->nxge_hw_p = NULL; 8962e59129aSraghus } 8972e59129aSraghus 8982e59129aSraghus nxge_attach_fail3: 8992e59129aSraghus /* 9002e59129aSraghus * Unmap the register setup. 9012e59129aSraghus */ 9022e59129aSraghus nxge_unmap_regs(nxgep); 9032e59129aSraghus 9042e59129aSraghus nxge_fm_fini(nxgep); 9052e59129aSraghus 9062e59129aSraghus nxge_attach_fail2: 9072e59129aSraghus ddi_soft_state_free(nxge_list, nxgep->instance); 9082e59129aSraghus 9092e59129aSraghus nxge_attach_fail1: 91056d930aeSspeer if (status != NXGE_OK) 91156d930aeSspeer status = (NXGE_ERROR | NXGE_DDI_FAILED); 91244961713Sgirish nxgep = NULL; 91344961713Sgirish 91444961713Sgirish nxge_attach_exit: 91544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_attach status = 0x%08x", 9164045d941Ssowmini status)); 91744961713Sgirish 91844961713Sgirish return (status); 91944961713Sgirish } 92044961713Sgirish 92144961713Sgirish static int 92244961713Sgirish nxge_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 92344961713Sgirish { 92444961713Sgirish int status = DDI_SUCCESS; 92544961713Sgirish int instance; 92644961713Sgirish p_nxge_t nxgep = NULL; 92744961713Sgirish 92844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_detach")); 92944961713Sgirish instance = ddi_get_instance(dip); 93044961713Sgirish nxgep = ddi_get_soft_state(nxge_list, instance); 93144961713Sgirish if (nxgep == NULL) { 93244961713Sgirish status = DDI_FAILURE; 93344961713Sgirish goto nxge_detach_exit; 93444961713Sgirish } 93544961713Sgirish 93644961713Sgirish switch (cmd) { 93744961713Sgirish case DDI_DETACH: 93844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_DETACH")); 93944961713Sgirish break; 94044961713Sgirish 94144961713Sgirish case DDI_PM_SUSPEND: 94244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_PM_SUSPEND")); 94344961713Sgirish nxgep->suspended = DDI_PM_SUSPEND; 94444961713Sgirish nxge_suspend(nxgep); 94544961713Sgirish break; 94644961713Sgirish 94744961713Sgirish case DDI_SUSPEND: 94844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_SUSPEND")); 94944961713Sgirish if (nxgep->suspended != DDI_PM_SUSPEND) { 95044961713Sgirish nxgep->suspended = DDI_SUSPEND; 95144961713Sgirish nxge_suspend(nxgep); 95244961713Sgirish } 95344961713Sgirish break; 95444961713Sgirish 95544961713Sgirish default: 95644961713Sgirish status = DDI_FAILURE; 95744961713Sgirish } 95844961713Sgirish 95944961713Sgirish if (cmd != DDI_DETACH) 96044961713Sgirish goto nxge_detach_exit; 96144961713Sgirish 96244961713Sgirish /* 96344961713Sgirish * Stop the xcvr polling. 96444961713Sgirish */ 96544961713Sgirish nxgep->suspended = cmd; 96644961713Sgirish 96744961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 96844961713Sgirish 969678453a8Sspeer if (isLDOMguest(nxgep)) { 970d7cf53fcSmisaki Miyashita if (nxgep->nxge_mac_state == NXGE_MAC_STARTED) 971d7cf53fcSmisaki Miyashita nxge_m_stop((void *)nxgep); 972678453a8Sspeer nxge_hio_unregister(nxgep); 973678453a8Sspeer } else if (nxgep->mach && (status = mac_unregister(nxgep->mach)) != 0) { 97444961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 9754045d941Ssowmini "<== nxge_detach status = 0x%08X", status)); 97644961713Sgirish return (DDI_FAILURE); 97744961713Sgirish } 97844961713Sgirish 97944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 9804045d941Ssowmini "<== nxge_detach (mac_unregister) status = 0x%08X", status)); 98144961713Sgirish 98244961713Sgirish nxge_unattach(nxgep); 98344961713Sgirish nxgep = NULL; 98444961713Sgirish 98544961713Sgirish nxge_detach_exit: 98644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_detach status = 0x%08X", 9874045d941Ssowmini status)); 98844961713Sgirish 98944961713Sgirish return (status); 99044961713Sgirish } 99144961713Sgirish 99244961713Sgirish static void 99344961713Sgirish nxge_unattach(p_nxge_t nxgep) 99444961713Sgirish { 99544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_unattach")); 99644961713Sgirish 99744961713Sgirish if (nxgep == NULL || nxgep->dev_regs == NULL) { 99844961713Sgirish return; 99944961713Sgirish } 100044961713Sgirish 100198ecde52Stm nxgep->nxge_magic = 0; 100298ecde52Stm 100344961713Sgirish if (nxgep->nxge_timerid) { 100444961713Sgirish nxge_stop_timer(nxgep, nxgep->nxge_timerid); 100544961713Sgirish nxgep->nxge_timerid = 0; 100644961713Sgirish } 100744961713Sgirish 10086f157acbSml /* 10096f157acbSml * If this flag is set, it will affect the Neptune 10106f157acbSml * only. 10116f157acbSml */ 10126f157acbSml if ((nxgep->niu_type != N2_NIU) && nxge_peu_reset_enable) { 10136f157acbSml nxge_niu_peu_reset(nxgep); 10146f157acbSml } 10156f157acbSml 1016678453a8Sspeer #if defined(sun4v) 1017678453a8Sspeer if (isLDOMguest(nxgep)) { 1018d00f30bbSspeer (void) nxge_hio_vr_release(nxgep); 1019678453a8Sspeer } 1020678453a8Sspeer #endif 1021678453a8Sspeer 102253560810Ssbehera if (nxgep->nxge_hw_p) { 102353560810Ssbehera nxge_uninit_common_dev(nxgep); 102453560810Ssbehera nxgep->nxge_hw_p = NULL; 102553560810Ssbehera } 102653560810Ssbehera 102744961713Sgirish #if defined(sun4v) 102844961713Sgirish if (nxgep->niu_type == N2_NIU && nxgep->niu_hsvc_available == B_TRUE) { 102944961713Sgirish (void) hsvc_unregister(&nxgep->niu_hsvc); 103044961713Sgirish nxgep->niu_hsvc_available = B_FALSE; 103144961713Sgirish } 103244961713Sgirish #endif 103344961713Sgirish /* 103444961713Sgirish * Stop any further interrupts. 103544961713Sgirish */ 103644961713Sgirish nxge_remove_intrs(nxgep); 103744961713Sgirish 103844961713Sgirish /* 103944961713Sgirish * Stop the device and free resources. 104044961713Sgirish */ 1041678453a8Sspeer if (!isLDOMguest(nxgep)) { 1042678453a8Sspeer nxge_destroy_dev(nxgep); 1043678453a8Sspeer } 104444961713Sgirish 104544961713Sgirish /* 104644961713Sgirish * Tear down the ndd parameters setup. 104744961713Sgirish */ 104844961713Sgirish nxge_destroy_param(nxgep); 104944961713Sgirish 105044961713Sgirish /* 105144961713Sgirish * Tear down the kstat setup. 105244961713Sgirish */ 105344961713Sgirish nxge_destroy_kstats(nxgep); 105444961713Sgirish 105544961713Sgirish /* 105644961713Sgirish * Destroy all mutexes. 105744961713Sgirish */ 105844961713Sgirish nxge_destroy_mutexes(nxgep); 105944961713Sgirish 106044961713Sgirish /* 106144961713Sgirish * Remove the list of ndd parameters which 106244961713Sgirish * were setup during attach. 106344961713Sgirish */ 106444961713Sgirish if (nxgep->dip) { 106544961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL, 10664045d941Ssowmini " nxge_unattach: remove all properties")); 106744961713Sgirish 106844961713Sgirish (void) ddi_prop_remove_all(nxgep->dip); 106944961713Sgirish } 107044961713Sgirish 107144961713Sgirish #if NXGE_PROPERTY 107244961713Sgirish nxge_remove_hard_properties(nxgep); 107344961713Sgirish #endif 107444961713Sgirish 107544961713Sgirish /* 107644961713Sgirish * Unmap the register setup. 107744961713Sgirish */ 107844961713Sgirish nxge_unmap_regs(nxgep); 107944961713Sgirish 108044961713Sgirish nxge_fm_fini(nxgep); 108144961713Sgirish 108244961713Sgirish ddi_soft_state_free(nxge_list, nxgep->instance); 108344961713Sgirish 108444961713Sgirish NXGE_DEBUG_MSG((NULL, DDI_CTL, "<== nxge_unattach")); 108544961713Sgirish } 108644961713Sgirish 1087678453a8Sspeer #if defined(sun4v) 1088678453a8Sspeer int 10899d5b8bc5SMichael Speer nxge_hsvc_register(nxge_t *nxgep) 1090678453a8Sspeer { 1091678453a8Sspeer nxge_status_t status; 1092678453a8Sspeer 1093678453a8Sspeer if (nxgep->niu_type == N2_NIU) { 1094678453a8Sspeer nxgep->niu_hsvc_available = B_FALSE; 1095678453a8Sspeer bcopy(&niu_hsvc, &nxgep->niu_hsvc, sizeof (hsvc_info_t)); 1096678453a8Sspeer if ((status = hsvc_register(&nxgep->niu_hsvc, 1097678453a8Sspeer &nxgep->niu_min_ver)) != 0) { 1098678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1099678453a8Sspeer "nxge_attach: %s: cannot negotiate " 1100678453a8Sspeer "hypervisor services revision %d group: 0x%lx " 1101678453a8Sspeer "major: 0x%lx minor: 0x%lx errno: %d", 1102678453a8Sspeer niu_hsvc.hsvc_modname, niu_hsvc.hsvc_rev, 1103678453a8Sspeer niu_hsvc.hsvc_group, niu_hsvc.hsvc_major, 1104678453a8Sspeer niu_hsvc.hsvc_minor, status)); 1105678453a8Sspeer return (DDI_FAILURE); 1106678453a8Sspeer } 1107678453a8Sspeer nxgep->niu_hsvc_available = B_TRUE; 1108678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DDI_CTL, 11094045d941Ssowmini "NIU Hypervisor service enabled")); 1110678453a8Sspeer } 1111678453a8Sspeer 1112678453a8Sspeer return (DDI_SUCCESS); 1113678453a8Sspeer } 1114678453a8Sspeer #endif 1115678453a8Sspeer 111644961713Sgirish static char n2_siu_name[] = "niu"; 111744961713Sgirish 111844961713Sgirish static nxge_status_t 111944961713Sgirish nxge_map_regs(p_nxge_t nxgep) 112044961713Sgirish { 112144961713Sgirish int ddi_status = DDI_SUCCESS; 112244961713Sgirish p_dev_regs_t dev_regs; 112344961713Sgirish char buf[MAXPATHLEN + 1]; 112444961713Sgirish char *devname; 112544961713Sgirish #ifdef NXGE_DEBUG 112644961713Sgirish char *sysname; 112744961713Sgirish #endif 112844961713Sgirish off_t regsize; 112944961713Sgirish nxge_status_t status = NXGE_OK; 113014ea4bb7Ssd #if !defined(_BIG_ENDIAN) 113114ea4bb7Ssd off_t pci_offset; 113214ea4bb7Ssd uint16_t pcie_devctl; 113314ea4bb7Ssd #endif 113444961713Sgirish 1135678453a8Sspeer if (isLDOMguest(nxgep)) { 1136678453a8Sspeer return (nxge_guest_regs_map(nxgep)); 1137678453a8Sspeer } 1138678453a8Sspeer 113944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_map_regs")); 114044961713Sgirish nxgep->dev_regs = NULL; 114144961713Sgirish dev_regs = KMEM_ZALLOC(sizeof (dev_regs_t), KM_SLEEP); 114244961713Sgirish dev_regs->nxge_regh = NULL; 114344961713Sgirish dev_regs->nxge_pciregh = NULL; 114444961713Sgirish dev_regs->nxge_msix_regh = NULL; 114544961713Sgirish dev_regs->nxge_vir_regh = NULL; 114644961713Sgirish dev_regs->nxge_vir2_regh = NULL; 114759ac0c16Sdavemq nxgep->niu_type = NIU_TYPE_NONE; 114844961713Sgirish 114944961713Sgirish devname = ddi_pathname(nxgep->dip, buf); 115044961713Sgirish ASSERT(strlen(devname) > 0); 115144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 11524045d941Ssowmini "nxge_map_regs: pathname devname %s", devname)); 115344961713Sgirish 115400161856Syc /* 115500161856Syc * The driver is running on a N2-NIU system if devname is something 115600161856Syc * like "/niu@80/network@0" 115700161856Syc */ 115844961713Sgirish if (strstr(devname, n2_siu_name)) { 115944961713Sgirish /* N2/NIU */ 116044961713Sgirish nxgep->niu_type = N2_NIU; 116144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 11624045d941Ssowmini "nxge_map_regs: N2/NIU devname %s", devname)); 116344961713Sgirish /* get function number */ 116444961713Sgirish nxgep->function_num = 11654045d941Ssowmini (devname[strlen(devname) -1] == '1' ? 1 : 0); 116644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 11674045d941Ssowmini "nxge_map_regs: N2/NIU function number %d", 11684045d941Ssowmini nxgep->function_num)); 116944961713Sgirish } else { 117044961713Sgirish int *prop_val; 117144961713Sgirish uint_t prop_len; 117244961713Sgirish uint8_t func_num; 117344961713Sgirish 117444961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 11754045d941Ssowmini 0, "reg", 11764045d941Ssowmini &prop_val, &prop_len) != DDI_PROP_SUCCESS) { 117744961713Sgirish NXGE_DEBUG_MSG((nxgep, VPD_CTL, 11784045d941Ssowmini "Reg property not found")); 117944961713Sgirish ddi_status = DDI_FAILURE; 118044961713Sgirish goto nxge_map_regs_fail0; 118144961713Sgirish 118244961713Sgirish } else { 118344961713Sgirish func_num = (prop_val[0] >> 8) & 0x7; 118444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 11854045d941Ssowmini "Reg property found: fun # %d", 11864045d941Ssowmini func_num)); 118744961713Sgirish nxgep->function_num = func_num; 1188678453a8Sspeer if (isLDOMguest(nxgep)) { 1189678453a8Sspeer nxgep->function_num /= 2; 1190678453a8Sspeer return (NXGE_OK); 1191678453a8Sspeer } 119244961713Sgirish ddi_prop_free(prop_val); 119344961713Sgirish } 119444961713Sgirish } 119544961713Sgirish 119644961713Sgirish switch (nxgep->niu_type) { 119744961713Sgirish default: 119844961713Sgirish (void) ddi_dev_regsize(nxgep->dip, 0, ®size); 119944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 12004045d941Ssowmini "nxge_map_regs: pci config size 0x%x", regsize)); 120144961713Sgirish 120244961713Sgirish ddi_status = ddi_regs_map_setup(nxgep->dip, 0, 12034045d941Ssowmini (caddr_t *)&(dev_regs->nxge_pciregp), 0, 0, 12044045d941Ssowmini &nxge_dev_reg_acc_attr, &dev_regs->nxge_pciregh); 120544961713Sgirish if (ddi_status != DDI_SUCCESS) { 120644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 12074045d941Ssowmini "ddi_map_regs, nxge bus config regs failed")); 120844961713Sgirish goto nxge_map_regs_fail0; 120944961713Sgirish } 121044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 12114045d941Ssowmini "nxge_map_reg: PCI config addr 0x%0llx " 12124045d941Ssowmini " handle 0x%0llx", dev_regs->nxge_pciregp, 12134045d941Ssowmini dev_regs->nxge_pciregh)); 121444961713Sgirish /* 121544961713Sgirish * IMP IMP 121644961713Sgirish * workaround for bit swapping bug in HW 121744961713Sgirish * which ends up in no-snoop = yes 121844961713Sgirish * resulting, in DMA not synched properly 121944961713Sgirish */ 122044961713Sgirish #if !defined(_BIG_ENDIAN) 122114ea4bb7Ssd /* workarounds for x86 systems */ 122214ea4bb7Ssd pci_offset = 0x80 + PCIE_DEVCTL; 122314ea4bb7Ssd pcie_devctl = 0x0; 122414ea4bb7Ssd pcie_devctl &= PCIE_DEVCTL_ENABLE_NO_SNOOP; 122514ea4bb7Ssd pcie_devctl |= PCIE_DEVCTL_RO_EN; 122614ea4bb7Ssd pci_config_put16(dev_regs->nxge_pciregh, pci_offset, 12274045d941Ssowmini pcie_devctl); 122844961713Sgirish #endif 122914ea4bb7Ssd 123044961713Sgirish (void) ddi_dev_regsize(nxgep->dip, 1, ®size); 123144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 12324045d941Ssowmini "nxge_map_regs: pio size 0x%x", regsize)); 123344961713Sgirish /* set up the device mapped register */ 123444961713Sgirish ddi_status = ddi_regs_map_setup(nxgep->dip, 1, 12354045d941Ssowmini (caddr_t *)&(dev_regs->nxge_regp), 0, 0, 12364045d941Ssowmini &nxge_dev_reg_acc_attr, &dev_regs->nxge_regh); 123744961713Sgirish if (ddi_status != DDI_SUCCESS) { 123844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 12394045d941Ssowmini "ddi_map_regs for Neptune global reg failed")); 124044961713Sgirish goto nxge_map_regs_fail1; 124144961713Sgirish } 124244961713Sgirish 124344961713Sgirish /* set up the msi/msi-x mapped register */ 124444961713Sgirish (void) ddi_dev_regsize(nxgep->dip, 2, ®size); 124544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 12464045d941Ssowmini "nxge_map_regs: msix size 0x%x", regsize)); 124744961713Sgirish ddi_status = ddi_regs_map_setup(nxgep->dip, 2, 12484045d941Ssowmini (caddr_t *)&(dev_regs->nxge_msix_regp), 0, 0, 12494045d941Ssowmini &nxge_dev_reg_acc_attr, &dev_regs->nxge_msix_regh); 125044961713Sgirish if (ddi_status != DDI_SUCCESS) { 125144961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 12524045d941Ssowmini "ddi_map_regs for msi reg failed")); 125344961713Sgirish goto nxge_map_regs_fail2; 125444961713Sgirish } 125544961713Sgirish 125644961713Sgirish /* set up the vio region mapped register */ 125744961713Sgirish (void) ddi_dev_regsize(nxgep->dip, 3, ®size); 125844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 12594045d941Ssowmini "nxge_map_regs: vio size 0x%x", regsize)); 126044961713Sgirish ddi_status = ddi_regs_map_setup(nxgep->dip, 3, 12614045d941Ssowmini (caddr_t *)&(dev_regs->nxge_vir_regp), 0, 0, 12624045d941Ssowmini &nxge_dev_reg_acc_attr, &dev_regs->nxge_vir_regh); 126344961713Sgirish 126444961713Sgirish if (ddi_status != DDI_SUCCESS) { 126544961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 12664045d941Ssowmini "ddi_map_regs for nxge vio reg failed")); 126744961713Sgirish goto nxge_map_regs_fail3; 126844961713Sgirish } 126944961713Sgirish nxgep->dev_regs = dev_regs; 127044961713Sgirish 127144961713Sgirish NPI_PCI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_pciregh); 127244961713Sgirish NPI_PCI_ADD_HANDLE_SET(nxgep, 12734045d941Ssowmini (npi_reg_ptr_t)dev_regs->nxge_pciregp); 127444961713Sgirish NPI_MSI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_msix_regh); 127544961713Sgirish NPI_MSI_ADD_HANDLE_SET(nxgep, 12764045d941Ssowmini (npi_reg_ptr_t)dev_regs->nxge_msix_regp); 127744961713Sgirish 127844961713Sgirish NPI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh); 127944961713Sgirish NPI_ADD_HANDLE_SET(nxgep, (npi_reg_ptr_t)dev_regs->nxge_regp); 128044961713Sgirish 128144961713Sgirish NPI_REG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh); 128244961713Sgirish NPI_REG_ADD_HANDLE_SET(nxgep, 12834045d941Ssowmini (npi_reg_ptr_t)dev_regs->nxge_regp); 128444961713Sgirish 128544961713Sgirish NPI_VREG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_vir_regh); 128644961713Sgirish NPI_VREG_ADD_HANDLE_SET(nxgep, 12874045d941Ssowmini (npi_reg_ptr_t)dev_regs->nxge_vir_regp); 128844961713Sgirish 128944961713Sgirish break; 129044961713Sgirish 129144961713Sgirish case N2_NIU: 129244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "ddi_map_regs, NIU")); 129344961713Sgirish /* 129444961713Sgirish * Set up the device mapped register (FWARC 2006/556) 129544961713Sgirish * (changed back to 1: reg starts at 1!) 129644961713Sgirish */ 129744961713Sgirish (void) ddi_dev_regsize(nxgep->dip, 1, ®size); 129844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 12994045d941Ssowmini "nxge_map_regs: dev size 0x%x", regsize)); 130044961713Sgirish ddi_status = ddi_regs_map_setup(nxgep->dip, 1, 13014045d941Ssowmini (caddr_t *)&(dev_regs->nxge_regp), 0, 0, 13024045d941Ssowmini &nxge_dev_reg_acc_attr, &dev_regs->nxge_regh); 130344961713Sgirish 130444961713Sgirish if (ddi_status != DDI_SUCCESS) { 130544961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 13064045d941Ssowmini "ddi_map_regs for N2/NIU, global reg failed ")); 130744961713Sgirish goto nxge_map_regs_fail1; 130844961713Sgirish } 130944961713Sgirish 1310678453a8Sspeer /* set up the first vio region mapped register */ 131144961713Sgirish (void) ddi_dev_regsize(nxgep->dip, 2, ®size); 131244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 13134045d941Ssowmini "nxge_map_regs: vio (1) size 0x%x", regsize)); 131444961713Sgirish ddi_status = ddi_regs_map_setup(nxgep->dip, 2, 13154045d941Ssowmini (caddr_t *)&(dev_regs->nxge_vir_regp), 0, 0, 13164045d941Ssowmini &nxge_dev_reg_acc_attr, &dev_regs->nxge_vir_regh); 131744961713Sgirish 131844961713Sgirish if (ddi_status != DDI_SUCCESS) { 131944961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 13204045d941Ssowmini "ddi_map_regs for nxge vio reg failed")); 132144961713Sgirish goto nxge_map_regs_fail2; 132244961713Sgirish } 1323678453a8Sspeer /* set up the second vio region mapped register */ 132444961713Sgirish (void) ddi_dev_regsize(nxgep->dip, 3, ®size); 132544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 13264045d941Ssowmini "nxge_map_regs: vio (3) size 0x%x", regsize)); 132744961713Sgirish ddi_status = ddi_regs_map_setup(nxgep->dip, 3, 13284045d941Ssowmini (caddr_t *)&(dev_regs->nxge_vir2_regp), 0, 0, 13294045d941Ssowmini &nxge_dev_reg_acc_attr, &dev_regs->nxge_vir2_regh); 133044961713Sgirish 133144961713Sgirish if (ddi_status != DDI_SUCCESS) { 133244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 13334045d941Ssowmini "ddi_map_regs for nxge vio2 reg failed")); 133444961713Sgirish goto nxge_map_regs_fail3; 133544961713Sgirish } 133644961713Sgirish nxgep->dev_regs = dev_regs; 133744961713Sgirish 133844961713Sgirish NPI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh); 133944961713Sgirish NPI_ADD_HANDLE_SET(nxgep, (npi_reg_ptr_t)dev_regs->nxge_regp); 134044961713Sgirish 134144961713Sgirish NPI_REG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh); 134244961713Sgirish NPI_REG_ADD_HANDLE_SET(nxgep, 13434045d941Ssowmini (npi_reg_ptr_t)dev_regs->nxge_regp); 134444961713Sgirish 134544961713Sgirish NPI_VREG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_vir_regh); 134644961713Sgirish NPI_VREG_ADD_HANDLE_SET(nxgep, 13474045d941Ssowmini (npi_reg_ptr_t)dev_regs->nxge_vir_regp); 134844961713Sgirish 134944961713Sgirish NPI_V2REG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_vir2_regh); 135044961713Sgirish NPI_V2REG_ADD_HANDLE_SET(nxgep, 13514045d941Ssowmini (npi_reg_ptr_t)dev_regs->nxge_vir2_regp); 135244961713Sgirish 135344961713Sgirish break; 135444961713Sgirish } 135544961713Sgirish 135644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "nxge_map_reg: hardware addr 0x%0llx " 13574045d941Ssowmini " handle 0x%0llx", dev_regs->nxge_regp, dev_regs->nxge_regh)); 135844961713Sgirish 135944961713Sgirish goto nxge_map_regs_exit; 136044961713Sgirish nxge_map_regs_fail3: 136144961713Sgirish if (dev_regs->nxge_msix_regh) { 136244961713Sgirish ddi_regs_map_free(&dev_regs->nxge_msix_regh); 136344961713Sgirish } 136444961713Sgirish if (dev_regs->nxge_vir_regh) { 136544961713Sgirish ddi_regs_map_free(&dev_regs->nxge_regh); 136644961713Sgirish } 136744961713Sgirish nxge_map_regs_fail2: 136844961713Sgirish if (dev_regs->nxge_regh) { 136944961713Sgirish ddi_regs_map_free(&dev_regs->nxge_regh); 137044961713Sgirish } 137144961713Sgirish nxge_map_regs_fail1: 137244961713Sgirish if (dev_regs->nxge_pciregh) { 137344961713Sgirish ddi_regs_map_free(&dev_regs->nxge_pciregh); 137444961713Sgirish } 137544961713Sgirish nxge_map_regs_fail0: 137644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "Freeing register set memory")); 137744961713Sgirish kmem_free(dev_regs, sizeof (dev_regs_t)); 137844961713Sgirish 137944961713Sgirish nxge_map_regs_exit: 138044961713Sgirish if (ddi_status != DDI_SUCCESS) 138144961713Sgirish status |= (NXGE_ERROR | NXGE_DDI_FAILED); 138244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_map_regs")); 138344961713Sgirish return (status); 138444961713Sgirish } 138544961713Sgirish 138644961713Sgirish static void 138744961713Sgirish nxge_unmap_regs(p_nxge_t nxgep) 138844961713Sgirish { 138944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_unmap_regs")); 1390678453a8Sspeer 1391678453a8Sspeer if (isLDOMguest(nxgep)) { 1392678453a8Sspeer nxge_guest_regs_map_free(nxgep); 1393678453a8Sspeer return; 1394678453a8Sspeer } 1395678453a8Sspeer 139644961713Sgirish if (nxgep->dev_regs) { 139744961713Sgirish if (nxgep->dev_regs->nxge_pciregh) { 139844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 13994045d941Ssowmini "==> nxge_unmap_regs: bus")); 140044961713Sgirish ddi_regs_map_free(&nxgep->dev_regs->nxge_pciregh); 140144961713Sgirish nxgep->dev_regs->nxge_pciregh = NULL; 140244961713Sgirish } 140344961713Sgirish if (nxgep->dev_regs->nxge_regh) { 140444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 14054045d941Ssowmini "==> nxge_unmap_regs: device registers")); 140644961713Sgirish ddi_regs_map_free(&nxgep->dev_regs->nxge_regh); 140744961713Sgirish nxgep->dev_regs->nxge_regh = NULL; 140844961713Sgirish } 140944961713Sgirish if (nxgep->dev_regs->nxge_msix_regh) { 141044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 14114045d941Ssowmini "==> nxge_unmap_regs: device interrupts")); 141244961713Sgirish ddi_regs_map_free(&nxgep->dev_regs->nxge_msix_regh); 141344961713Sgirish nxgep->dev_regs->nxge_msix_regh = NULL; 141444961713Sgirish } 141544961713Sgirish if (nxgep->dev_regs->nxge_vir_regh) { 141644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 14174045d941Ssowmini "==> nxge_unmap_regs: vio region")); 141844961713Sgirish ddi_regs_map_free(&nxgep->dev_regs->nxge_vir_regh); 141944961713Sgirish nxgep->dev_regs->nxge_vir_regh = NULL; 142044961713Sgirish } 142144961713Sgirish if (nxgep->dev_regs->nxge_vir2_regh) { 142244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 14234045d941Ssowmini "==> nxge_unmap_regs: vio2 region")); 142444961713Sgirish ddi_regs_map_free(&nxgep->dev_regs->nxge_vir2_regh); 142544961713Sgirish nxgep->dev_regs->nxge_vir2_regh = NULL; 142644961713Sgirish } 142744961713Sgirish 142844961713Sgirish kmem_free(nxgep->dev_regs, sizeof (dev_regs_t)); 142944961713Sgirish nxgep->dev_regs = NULL; 143044961713Sgirish } 143144961713Sgirish 143244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_unmap_regs")); 143344961713Sgirish } 143444961713Sgirish 143544961713Sgirish static nxge_status_t 143644961713Sgirish nxge_setup_mutexes(p_nxge_t nxgep) 143744961713Sgirish { 143844961713Sgirish int ddi_status = DDI_SUCCESS; 143944961713Sgirish nxge_status_t status = NXGE_OK; 144044961713Sgirish nxge_classify_t *classify_ptr; 144144961713Sgirish int partition; 144244961713Sgirish 144344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_setup_mutexes")); 144444961713Sgirish 144544961713Sgirish /* 144644961713Sgirish * Get the interrupt cookie so the mutexes can be 144758324dfcSspeer * Initialized. 144844961713Sgirish */ 1449678453a8Sspeer if (isLDOMguest(nxgep)) { 1450678453a8Sspeer nxgep->interrupt_cookie = 0; 1451678453a8Sspeer } else { 1452678453a8Sspeer ddi_status = ddi_get_iblock_cookie(nxgep->dip, 0, 1453678453a8Sspeer &nxgep->interrupt_cookie); 1454678453a8Sspeer 1455678453a8Sspeer if (ddi_status != DDI_SUCCESS) { 1456678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1457678453a8Sspeer "<== nxge_setup_mutexes: failed 0x%x", 1458678453a8Sspeer ddi_status)); 1459678453a8Sspeer goto nxge_setup_mutexes_exit; 1460678453a8Sspeer } 146144961713Sgirish } 146244961713Sgirish 146398ecde52Stm cv_init(&nxgep->poll_cv, NULL, CV_DRIVER, NULL); 146498ecde52Stm MUTEX_INIT(&nxgep->poll_lock, NULL, 146598ecde52Stm MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 146698ecde52Stm 146744961713Sgirish /* 146898ecde52Stm * Initialize mutexes for this device. 146944961713Sgirish */ 147044961713Sgirish MUTEX_INIT(nxgep->genlock, NULL, 14714045d941Ssowmini MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 147244961713Sgirish MUTEX_INIT(&nxgep->ouraddr_lock, NULL, 14734045d941Ssowmini MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 147444961713Sgirish MUTEX_INIT(&nxgep->mif_lock, NULL, 14754045d941Ssowmini MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1476678453a8Sspeer MUTEX_INIT(&nxgep->group_lock, NULL, 1477678453a8Sspeer MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 147844961713Sgirish RW_INIT(&nxgep->filter_lock, NULL, 14794045d941Ssowmini RW_DRIVER, (void *)nxgep->interrupt_cookie); 148044961713Sgirish 148144961713Sgirish classify_ptr = &nxgep->classifier; 148244961713Sgirish /* 148344961713Sgirish * FFLP Mutexes are never used in interrupt context 148444961713Sgirish * as fflp operation can take very long time to 148544961713Sgirish * complete and hence not suitable to invoke from interrupt 148644961713Sgirish * handlers. 148744961713Sgirish */ 148844961713Sgirish MUTEX_INIT(&classify_ptr->tcam_lock, NULL, 148959ac0c16Sdavemq NXGE_MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 14902e59129aSraghus if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) { 149144961713Sgirish MUTEX_INIT(&classify_ptr->fcram_lock, NULL, 149259ac0c16Sdavemq NXGE_MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 149344961713Sgirish for (partition = 0; partition < MAX_PARTITION; partition++) { 149444961713Sgirish MUTEX_INIT(&classify_ptr->hash_lock[partition], NULL, 149544961713Sgirish NXGE_MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 149644961713Sgirish } 149744961713Sgirish } 149844961713Sgirish 149944961713Sgirish nxge_setup_mutexes_exit: 150044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 150159ac0c16Sdavemq "<== nxge_setup_mutexes status = %x", status)); 150244961713Sgirish 150344961713Sgirish if (ddi_status != DDI_SUCCESS) 150444961713Sgirish status |= (NXGE_ERROR | NXGE_DDI_FAILED); 150544961713Sgirish 150644961713Sgirish return (status); 150744961713Sgirish } 150844961713Sgirish 150944961713Sgirish static void 151044961713Sgirish nxge_destroy_mutexes(p_nxge_t nxgep) 151144961713Sgirish { 151244961713Sgirish int partition; 151344961713Sgirish nxge_classify_t *classify_ptr; 151444961713Sgirish 151544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_mutexes")); 151644961713Sgirish RW_DESTROY(&nxgep->filter_lock); 1517678453a8Sspeer MUTEX_DESTROY(&nxgep->group_lock); 151844961713Sgirish MUTEX_DESTROY(&nxgep->mif_lock); 151944961713Sgirish MUTEX_DESTROY(&nxgep->ouraddr_lock); 152044961713Sgirish MUTEX_DESTROY(nxgep->genlock); 152144961713Sgirish 152244961713Sgirish classify_ptr = &nxgep->classifier; 152344961713Sgirish MUTEX_DESTROY(&classify_ptr->tcam_lock); 152444961713Sgirish 152598ecde52Stm /* Destroy all polling resources. */ 152698ecde52Stm MUTEX_DESTROY(&nxgep->poll_lock); 152798ecde52Stm cv_destroy(&nxgep->poll_cv); 152898ecde52Stm 152998ecde52Stm /* free data structures, based on HW type */ 15302e59129aSraghus if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) { 153144961713Sgirish MUTEX_DESTROY(&classify_ptr->fcram_lock); 153244961713Sgirish for (partition = 0; partition < MAX_PARTITION; partition++) { 153344961713Sgirish MUTEX_DESTROY(&classify_ptr->hash_lock[partition]); 153444961713Sgirish } 153544961713Sgirish } 153644961713Sgirish 153744961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_mutexes")); 153844961713Sgirish } 153944961713Sgirish 154044961713Sgirish nxge_status_t 154144961713Sgirish nxge_init(p_nxge_t nxgep) 154244961713Sgirish { 1543678453a8Sspeer nxge_status_t status = NXGE_OK; 154444961713Sgirish 154544961713Sgirish NXGE_DEBUG_MSG((nxgep, STR_CTL, "==> nxge_init")); 154644961713Sgirish 154714ea4bb7Ssd if (nxgep->drv_state & STATE_HW_INITIALIZED) { 154814ea4bb7Ssd return (status); 154914ea4bb7Ssd } 155014ea4bb7Ssd 155144961713Sgirish /* 155244961713Sgirish * Allocate system memory for the receive/transmit buffer blocks 155344961713Sgirish * and receive/transmit descriptor rings. 155444961713Sgirish */ 155544961713Sgirish status = nxge_alloc_mem_pool(nxgep); 155644961713Sgirish if (status != NXGE_OK) { 155744961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "alloc mem failed\n")); 155844961713Sgirish goto nxge_init_fail1; 155944961713Sgirish } 156044961713Sgirish 1561678453a8Sspeer if (!isLDOMguest(nxgep)) { 1562678453a8Sspeer /* 1563678453a8Sspeer * Initialize and enable the TXC registers. 1564678453a8Sspeer * (Globally enable the Tx controller, 1565678453a8Sspeer * enable the port, configure the dma channel bitmap, 1566678453a8Sspeer * configure the max burst size). 1567678453a8Sspeer */ 1568678453a8Sspeer status = nxge_txc_init(nxgep); 1569678453a8Sspeer if (status != NXGE_OK) { 1570678453a8Sspeer NXGE_ERROR_MSG((nxgep, 1571678453a8Sspeer NXGE_ERR_CTL, "init txc failed\n")); 1572678453a8Sspeer goto nxge_init_fail2; 1573678453a8Sspeer } 157444961713Sgirish } 157544961713Sgirish 157644961713Sgirish /* 157744961713Sgirish * Initialize and enable TXDMA channels. 157844961713Sgirish */ 157944961713Sgirish status = nxge_init_txdma_channels(nxgep); 158044961713Sgirish if (status != NXGE_OK) { 158144961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init txdma failed\n")); 158244961713Sgirish goto nxge_init_fail3; 158344961713Sgirish } 158444961713Sgirish 158544961713Sgirish /* 158644961713Sgirish * Initialize and enable RXDMA channels. 158744961713Sgirish */ 158844961713Sgirish status = nxge_init_rxdma_channels(nxgep); 158944961713Sgirish if (status != NXGE_OK) { 159044961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init rxdma failed\n")); 159144961713Sgirish goto nxge_init_fail4; 159244961713Sgirish } 159344961713Sgirish 1594678453a8Sspeer /* 1595678453a8Sspeer * The guest domain is now done. 1596678453a8Sspeer */ 1597678453a8Sspeer if (isLDOMguest(nxgep)) { 1598678453a8Sspeer nxgep->drv_state |= STATE_HW_INITIALIZED; 1599678453a8Sspeer goto nxge_init_exit; 1600678453a8Sspeer } 1601678453a8Sspeer 160244961713Sgirish /* 160344961713Sgirish * Initialize TCAM and FCRAM (Neptune). 160444961713Sgirish */ 160544961713Sgirish status = nxge_classify_init(nxgep); 160644961713Sgirish if (status != NXGE_OK) { 160744961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init classify failed\n")); 160844961713Sgirish goto nxge_init_fail5; 160944961713Sgirish } 161044961713Sgirish 161144961713Sgirish /* 161244961713Sgirish * Initialize ZCP 161344961713Sgirish */ 161444961713Sgirish status = nxge_zcp_init(nxgep); 161544961713Sgirish if (status != NXGE_OK) { 161644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init ZCP failed\n")); 161744961713Sgirish goto nxge_init_fail5; 161844961713Sgirish } 161944961713Sgirish 162044961713Sgirish /* 162144961713Sgirish * Initialize IPP. 162244961713Sgirish */ 162344961713Sgirish status = nxge_ipp_init(nxgep); 162444961713Sgirish if (status != NXGE_OK) { 162544961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init IPP failed\n")); 162644961713Sgirish goto nxge_init_fail5; 162744961713Sgirish } 162844961713Sgirish 162944961713Sgirish /* 163044961713Sgirish * Initialize the MAC block. 163144961713Sgirish */ 163244961713Sgirish status = nxge_mac_init(nxgep); 163344961713Sgirish if (status != NXGE_OK) { 163444961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init MAC failed\n")); 163544961713Sgirish goto nxge_init_fail5; 163644961713Sgirish } 163744961713Sgirish 1638678453a8Sspeer nxge_intrs_enable(nxgep); /* XXX What changes do I need to make here? */ 163944961713Sgirish 164044961713Sgirish /* 164144961713Sgirish * Enable hardware interrupts. 164244961713Sgirish */ 164344961713Sgirish nxge_intr_hw_enable(nxgep); 164444961713Sgirish nxgep->drv_state |= STATE_HW_INITIALIZED; 164544961713Sgirish 164644961713Sgirish goto nxge_init_exit; 164744961713Sgirish 164844961713Sgirish nxge_init_fail5: 164944961713Sgirish nxge_uninit_rxdma_channels(nxgep); 165044961713Sgirish nxge_init_fail4: 165144961713Sgirish nxge_uninit_txdma_channels(nxgep); 165244961713Sgirish nxge_init_fail3: 1653678453a8Sspeer if (!isLDOMguest(nxgep)) { 1654678453a8Sspeer (void) nxge_txc_uninit(nxgep); 1655678453a8Sspeer } 165644961713Sgirish nxge_init_fail2: 165744961713Sgirish nxge_free_mem_pool(nxgep); 165844961713Sgirish nxge_init_fail1: 165944961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 16604045d941Ssowmini "<== nxge_init status (failed) = 0x%08x", status)); 166144961713Sgirish return (status); 166244961713Sgirish 166344961713Sgirish nxge_init_exit: 166444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_init status = 0x%08x", 16654045d941Ssowmini status)); 166644961713Sgirish return (status); 166744961713Sgirish } 166844961713Sgirish 166944961713Sgirish 167044961713Sgirish timeout_id_t 167144961713Sgirish nxge_start_timer(p_nxge_t nxgep, fptrv_t func, int msec) 167244961713Sgirish { 16734045d941Ssowmini if ((nxgep->suspended == 0) || (nxgep->suspended == DDI_RESUME)) { 167444961713Sgirish return (timeout(func, (caddr_t)nxgep, 16754045d941Ssowmini drv_usectohz(1000 * msec))); 167644961713Sgirish } 167744961713Sgirish return (NULL); 167844961713Sgirish } 167944961713Sgirish 168044961713Sgirish /*ARGSUSED*/ 168144961713Sgirish void 168244961713Sgirish nxge_stop_timer(p_nxge_t nxgep, timeout_id_t timerid) 168344961713Sgirish { 168444961713Sgirish if (timerid) { 168544961713Sgirish (void) untimeout(timerid); 168644961713Sgirish } 168744961713Sgirish } 168844961713Sgirish 168944961713Sgirish void 169044961713Sgirish nxge_uninit(p_nxge_t nxgep) 169144961713Sgirish { 169244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_uninit")); 169344961713Sgirish 169444961713Sgirish if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 169544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 16964045d941Ssowmini "==> nxge_uninit: not initialized")); 169744961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 16984045d941Ssowmini "<== nxge_uninit")); 169944961713Sgirish return; 170044961713Sgirish } 170144961713Sgirish 170244961713Sgirish /* stop timer */ 170344961713Sgirish if (nxgep->nxge_timerid) { 170444961713Sgirish nxge_stop_timer(nxgep, nxgep->nxge_timerid); 170544961713Sgirish nxgep->nxge_timerid = 0; 170644961713Sgirish } 170744961713Sgirish 170844961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 170944961713Sgirish (void) nxge_intr_hw_disable(nxgep); 171044961713Sgirish 171144961713Sgirish /* 171244961713Sgirish * Reset the receive MAC side. 171344961713Sgirish */ 171444961713Sgirish (void) nxge_rx_mac_disable(nxgep); 171544961713Sgirish 171644961713Sgirish /* Disable and soft reset the IPP */ 1717678453a8Sspeer if (!isLDOMguest(nxgep)) 1718678453a8Sspeer (void) nxge_ipp_disable(nxgep); 171944961713Sgirish 1720a3c5bd6dSspeer /* Free classification resources */ 1721a3c5bd6dSspeer (void) nxge_classify_uninit(nxgep); 1722a3c5bd6dSspeer 172344961713Sgirish /* 172444961713Sgirish * Reset the transmit/receive DMA side. 172544961713Sgirish */ 172644961713Sgirish (void) nxge_txdma_hw_mode(nxgep, NXGE_DMA_STOP); 172744961713Sgirish (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_STOP); 172844961713Sgirish 172944961713Sgirish nxge_uninit_txdma_channels(nxgep); 173044961713Sgirish nxge_uninit_rxdma_channels(nxgep); 173144961713Sgirish 173244961713Sgirish /* 173344961713Sgirish * Reset the transmit MAC side. 173444961713Sgirish */ 173544961713Sgirish (void) nxge_tx_mac_disable(nxgep); 173644961713Sgirish 173744961713Sgirish nxge_free_mem_pool(nxgep); 173844961713Sgirish 17396f157acbSml /* 17406f157acbSml * Start the timer if the reset flag is not set. 17416f157acbSml * If this reset flag is set, the link monitor 17426f157acbSml * will not be started in order to stop furthur bus 17436f157acbSml * activities coming from this interface. 17446f157acbSml * The driver will start the monitor function 17456f157acbSml * if the interface was initialized again later. 17466f157acbSml */ 17476f157acbSml if (!nxge_peu_reset_enable) { 17486f157acbSml (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 17496f157acbSml } 175044961713Sgirish 175144961713Sgirish nxgep->drv_state &= ~STATE_HW_INITIALIZED; 175244961713Sgirish 175344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_uninit: " 17544045d941Ssowmini "nxge_mblks_pending %d", nxge_mblks_pending)); 175544961713Sgirish } 175644961713Sgirish 175744961713Sgirish void 175844961713Sgirish nxge_get64(p_nxge_t nxgep, p_mblk_t mp) 175944961713Sgirish { 1760adfcba55Sjoycey #if defined(__i386) 1761adfcba55Sjoycey size_t reg; 1762adfcba55Sjoycey #else 176344961713Sgirish uint64_t reg; 1764adfcba55Sjoycey #endif 176544961713Sgirish uint64_t regdata; 176644961713Sgirish int i, retry; 176744961713Sgirish 176844961713Sgirish bcopy((char *)mp->b_rptr, (char *)®, sizeof (uint64_t)); 176944961713Sgirish regdata = 0; 177044961713Sgirish retry = 1; 177144961713Sgirish 177244961713Sgirish for (i = 0; i < retry; i++) { 177344961713Sgirish NXGE_REG_RD64(nxgep->npi_handle, reg, ®data); 177444961713Sgirish } 177544961713Sgirish bcopy((char *)®data, (char *)mp->b_rptr, sizeof (uint64_t)); 177644961713Sgirish } 177744961713Sgirish 177844961713Sgirish void 177944961713Sgirish nxge_put64(p_nxge_t nxgep, p_mblk_t mp) 178044961713Sgirish { 1781adfcba55Sjoycey #if defined(__i386) 1782adfcba55Sjoycey size_t reg; 1783adfcba55Sjoycey #else 178444961713Sgirish uint64_t reg; 1785adfcba55Sjoycey #endif 178644961713Sgirish uint64_t buf[2]; 178744961713Sgirish 178844961713Sgirish bcopy((char *)mp->b_rptr, (char *)&buf[0], 2 * sizeof (uint64_t)); 17897a8b1321Sjoycey #if defined(__i386) 17907a8b1321Sjoycey reg = (size_t)buf[0]; 17917a8b1321Sjoycey #else 179244961713Sgirish reg = buf[0]; 17937a8b1321Sjoycey #endif 179444961713Sgirish 179544961713Sgirish NXGE_NPI_PIO_WRITE64(nxgep->npi_handle, reg, buf[1]); 179644961713Sgirish } 179744961713Sgirish 179844961713Sgirish 179944961713Sgirish nxge_os_mutex_t nxgedebuglock; 180044961713Sgirish int nxge_debug_init = 0; 180144961713Sgirish 180244961713Sgirish /*ARGSUSED*/ 180344961713Sgirish /*VARARGS*/ 180444961713Sgirish void 180544961713Sgirish nxge_debug_msg(p_nxge_t nxgep, uint64_t level, char *fmt, ...) 180644961713Sgirish { 180744961713Sgirish char msg_buffer[1048]; 180844961713Sgirish char prefix_buffer[32]; 180944961713Sgirish int instance; 181044961713Sgirish uint64_t debug_level; 181144961713Sgirish int cmn_level = CE_CONT; 181244961713Sgirish va_list ap; 181344961713Sgirish 1814678453a8Sspeer if (nxgep && nxgep->nxge_debug_level != nxge_debug_level) { 1815678453a8Sspeer /* In case a developer has changed nxge_debug_level. */ 1816678453a8Sspeer if (nxgep->nxge_debug_level != nxge_debug_level) 1817678453a8Sspeer nxgep->nxge_debug_level = nxge_debug_level; 1818678453a8Sspeer } 1819678453a8Sspeer 182044961713Sgirish debug_level = (nxgep == NULL) ? nxge_debug_level : 18214045d941Ssowmini nxgep->nxge_debug_level; 182244961713Sgirish 182344961713Sgirish if ((level & debug_level) || 18244045d941Ssowmini (level == NXGE_NOTE) || 18254045d941Ssowmini (level == NXGE_ERR_CTL)) { 182644961713Sgirish /* do the msg processing */ 182744961713Sgirish if (nxge_debug_init == 0) { 182844961713Sgirish MUTEX_INIT(&nxgedebuglock, NULL, MUTEX_DRIVER, NULL); 182944961713Sgirish nxge_debug_init = 1; 183044961713Sgirish } 183144961713Sgirish 183244961713Sgirish MUTEX_ENTER(&nxgedebuglock); 183344961713Sgirish 183444961713Sgirish if ((level & NXGE_NOTE)) { 183544961713Sgirish cmn_level = CE_NOTE; 183644961713Sgirish } 183744961713Sgirish 183844961713Sgirish if (level & NXGE_ERR_CTL) { 183944961713Sgirish cmn_level = CE_WARN; 184044961713Sgirish } 184144961713Sgirish 184244961713Sgirish va_start(ap, fmt); 184344961713Sgirish (void) vsprintf(msg_buffer, fmt, ap); 184444961713Sgirish va_end(ap); 184544961713Sgirish if (nxgep == NULL) { 184644961713Sgirish instance = -1; 184744961713Sgirish (void) sprintf(prefix_buffer, "%s :", "nxge"); 184844961713Sgirish } else { 184944961713Sgirish instance = nxgep->instance; 185044961713Sgirish (void) sprintf(prefix_buffer, 18514045d941Ssowmini "%s%d :", "nxge", instance); 185244961713Sgirish } 185344961713Sgirish 185444961713Sgirish MUTEX_EXIT(&nxgedebuglock); 185544961713Sgirish cmn_err(cmn_level, "!%s %s\n", 18564045d941Ssowmini prefix_buffer, msg_buffer); 185744961713Sgirish 185844961713Sgirish } 185944961713Sgirish } 186044961713Sgirish 186144961713Sgirish char * 186244961713Sgirish nxge_dump_packet(char *addr, int size) 186344961713Sgirish { 186444961713Sgirish uchar_t *ap = (uchar_t *)addr; 186544961713Sgirish int i; 186644961713Sgirish static char etherbuf[1024]; 186744961713Sgirish char *cp = etherbuf; 186844961713Sgirish char digits[] = "0123456789abcdef"; 186944961713Sgirish 187044961713Sgirish if (!size) 187144961713Sgirish size = 60; 187244961713Sgirish 187344961713Sgirish if (size > MAX_DUMP_SZ) { 187444961713Sgirish /* Dump the leading bytes */ 187544961713Sgirish for (i = 0; i < MAX_DUMP_SZ/2; i++) { 187644961713Sgirish if (*ap > 0x0f) 187744961713Sgirish *cp++ = digits[*ap >> 4]; 187844961713Sgirish *cp++ = digits[*ap++ & 0xf]; 187944961713Sgirish *cp++ = ':'; 188044961713Sgirish } 188144961713Sgirish for (i = 0; i < 20; i++) 188244961713Sgirish *cp++ = '.'; 188344961713Sgirish /* Dump the last MAX_DUMP_SZ/2 bytes */ 188444961713Sgirish ap = (uchar_t *)(addr + (size - MAX_DUMP_SZ/2)); 188544961713Sgirish for (i = 0; i < MAX_DUMP_SZ/2; i++) { 188644961713Sgirish if (*ap > 0x0f) 188744961713Sgirish *cp++ = digits[*ap >> 4]; 188844961713Sgirish *cp++ = digits[*ap++ & 0xf]; 188944961713Sgirish *cp++ = ':'; 189044961713Sgirish } 189144961713Sgirish } else { 189244961713Sgirish for (i = 0; i < size; i++) { 189344961713Sgirish if (*ap > 0x0f) 189444961713Sgirish *cp++ = digits[*ap >> 4]; 189544961713Sgirish *cp++ = digits[*ap++ & 0xf]; 189644961713Sgirish *cp++ = ':'; 189744961713Sgirish } 189844961713Sgirish } 189944961713Sgirish *--cp = 0; 190044961713Sgirish return (etherbuf); 190144961713Sgirish } 190244961713Sgirish 190344961713Sgirish #ifdef NXGE_DEBUG 190444961713Sgirish static void 190544961713Sgirish nxge_test_map_regs(p_nxge_t nxgep) 190644961713Sgirish { 190744961713Sgirish ddi_acc_handle_t cfg_handle; 190844961713Sgirish p_pci_cfg_t cfg_ptr; 190944961713Sgirish ddi_acc_handle_t dev_handle; 191044961713Sgirish char *dev_ptr; 191144961713Sgirish ddi_acc_handle_t pci_config_handle; 191244961713Sgirish uint32_t regval; 191344961713Sgirish int i; 191444961713Sgirish 191544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_test_map_regs")); 191644961713Sgirish 191744961713Sgirish dev_handle = nxgep->dev_regs->nxge_regh; 191844961713Sgirish dev_ptr = (char *)nxgep->dev_regs->nxge_regp; 191944961713Sgirish 19202e59129aSraghus if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) { 192144961713Sgirish cfg_handle = nxgep->dev_regs->nxge_pciregh; 192244961713Sgirish cfg_ptr = (void *)nxgep->dev_regs->nxge_pciregp; 192344961713Sgirish 192444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 192559ac0c16Sdavemq "Neptune PCI regp cfg_ptr 0x%llx", (char *)cfg_ptr)); 192644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 192759ac0c16Sdavemq "Neptune PCI cfg_ptr vendor id ptr 0x%llx", 192859ac0c16Sdavemq &cfg_ptr->vendorid)); 192944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 193059ac0c16Sdavemq "\tvendorid 0x%x devid 0x%x", 193159ac0c16Sdavemq NXGE_PIO_READ16(cfg_handle, &cfg_ptr->vendorid, 0), 193259ac0c16Sdavemq NXGE_PIO_READ16(cfg_handle, &cfg_ptr->devid, 0))); 193344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 193459ac0c16Sdavemq "PCI BAR: base 0x%x base14 0x%x base 18 0x%x " 193559ac0c16Sdavemq "bar1c 0x%x", 193659ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base, 0), 193759ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base14, 0), 193859ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base18, 0), 193959ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base1c, 0))); 194044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 194159ac0c16Sdavemq "\nNeptune PCI BAR: base20 0x%x base24 0x%x " 194259ac0c16Sdavemq "base 28 0x%x bar2c 0x%x\n", 194359ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base20, 0), 194459ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base24, 0), 194559ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base28, 0), 194659ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base2c, 0))); 194744961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 194859ac0c16Sdavemq "\nNeptune PCI BAR: base30 0x%x\n", 194959ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base30, 0))); 195044961713Sgirish 195144961713Sgirish cfg_handle = nxgep->dev_regs->nxge_pciregh; 195244961713Sgirish cfg_ptr = (void *)nxgep->dev_regs->nxge_pciregp; 195344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 195459ac0c16Sdavemq "first 0x%llx second 0x%llx third 0x%llx " 195559ac0c16Sdavemq "last 0x%llx ", 195659ac0c16Sdavemq NXGE_PIO_READ64(dev_handle, 195759ac0c16Sdavemq (uint64_t *)(dev_ptr + 0), 0), 195859ac0c16Sdavemq NXGE_PIO_READ64(dev_handle, 195959ac0c16Sdavemq (uint64_t *)(dev_ptr + 8), 0), 196059ac0c16Sdavemq NXGE_PIO_READ64(dev_handle, 196159ac0c16Sdavemq (uint64_t *)(dev_ptr + 16), 0), 196259ac0c16Sdavemq NXGE_PIO_READ64(cfg_handle, 196359ac0c16Sdavemq (uint64_t *)(dev_ptr + 24), 0))); 196444961713Sgirish } 196544961713Sgirish } 196644961713Sgirish 196744961713Sgirish #endif 196844961713Sgirish 196944961713Sgirish static void 197044961713Sgirish nxge_suspend(p_nxge_t nxgep) 197144961713Sgirish { 197244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_suspend")); 197344961713Sgirish 197444961713Sgirish nxge_intrs_disable(nxgep); 197544961713Sgirish nxge_destroy_dev(nxgep); 197644961713Sgirish 197744961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_suspend")); 197844961713Sgirish } 197944961713Sgirish 198044961713Sgirish static nxge_status_t 198144961713Sgirish nxge_resume(p_nxge_t nxgep) 198244961713Sgirish { 198344961713Sgirish nxge_status_t status = NXGE_OK; 198444961713Sgirish 198544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_resume")); 198644961713Sgirish 198791c98b31Sjoycey nxgep->suspended = DDI_RESUME; 198891c98b31Sjoycey (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 198991c98b31Sjoycey (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_START); 199091c98b31Sjoycey (void) nxge_txdma_hw_mode(nxgep, NXGE_DMA_START); 199191c98b31Sjoycey (void) nxge_rx_mac_enable(nxgep); 199291c98b31Sjoycey (void) nxge_tx_mac_enable(nxgep); 199391c98b31Sjoycey nxge_intrs_enable(nxgep); 199444961713Sgirish nxgep->suspended = 0; 199544961713Sgirish 199644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 19974045d941Ssowmini "<== nxge_resume status = 0x%x", status)); 199844961713Sgirish return (status); 199944961713Sgirish } 200044961713Sgirish 200144961713Sgirish static nxge_status_t 200244961713Sgirish nxge_setup_dev(p_nxge_t nxgep) 200344961713Sgirish { 200444961713Sgirish nxge_status_t status = NXGE_OK; 200544961713Sgirish 200644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_setup_dev port %d", 200759ac0c16Sdavemq nxgep->mac.portnum)); 200844961713Sgirish 200944961713Sgirish status = nxge_link_init(nxgep); 201014ea4bb7Ssd 201114ea4bb7Ssd if (fm_check_acc_handle(nxgep->dev_regs->nxge_regh) != DDI_FM_OK) { 201214ea4bb7Ssd NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 20134045d941Ssowmini "port%d Bad register acc handle", nxgep->mac.portnum)); 201414ea4bb7Ssd status = NXGE_ERROR; 201514ea4bb7Ssd } 201614ea4bb7Ssd 201744961713Sgirish if (status != NXGE_OK) { 201844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 20194045d941Ssowmini " nxge_setup_dev status " 20204045d941Ssowmini "(xcvr init 0x%08x)", status)); 202144961713Sgirish goto nxge_setup_dev_exit; 202244961713Sgirish } 202344961713Sgirish 202444961713Sgirish nxge_setup_dev_exit: 202544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 20264045d941Ssowmini "<== nxge_setup_dev port %d status = 0x%08x", 20274045d941Ssowmini nxgep->mac.portnum, status)); 202844961713Sgirish 202944961713Sgirish return (status); 203044961713Sgirish } 203144961713Sgirish 203244961713Sgirish static void 203344961713Sgirish nxge_destroy_dev(p_nxge_t nxgep) 203444961713Sgirish { 203544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_dev")); 203644961713Sgirish 203744961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 203844961713Sgirish 203944961713Sgirish (void) nxge_hw_stop(nxgep); 204044961713Sgirish 204144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_dev")); 204244961713Sgirish } 204344961713Sgirish 204444961713Sgirish static nxge_status_t 204544961713Sgirish nxge_setup_system_dma_pages(p_nxge_t nxgep) 204644961713Sgirish { 204744961713Sgirish int ddi_status = DDI_SUCCESS; 204844961713Sgirish uint_t count; 204944961713Sgirish ddi_dma_cookie_t cookie; 205044961713Sgirish uint_t iommu_pagesize; 205144961713Sgirish nxge_status_t status = NXGE_OK; 205244961713Sgirish 2053678453a8Sspeer NXGE_ERROR_MSG((nxgep, DDI_CTL, "==> nxge_setup_system_dma_pages")); 205444961713Sgirish nxgep->sys_page_sz = ddi_ptob(nxgep->dip, (ulong_t)1); 205544961713Sgirish if (nxgep->niu_type != N2_NIU) { 205644961713Sgirish iommu_pagesize = dvma_pagesize(nxgep->dip); 205744961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 20584045d941Ssowmini " nxge_setup_system_dma_pages: page %d (ddi_ptob %d) " 20594045d941Ssowmini " default_block_size %d iommu_pagesize %d", 20604045d941Ssowmini nxgep->sys_page_sz, 20614045d941Ssowmini ddi_ptob(nxgep->dip, (ulong_t)1), 20624045d941Ssowmini nxgep->rx_default_block_size, 20634045d941Ssowmini iommu_pagesize)); 206444961713Sgirish 206544961713Sgirish if (iommu_pagesize != 0) { 206644961713Sgirish if (nxgep->sys_page_sz == iommu_pagesize) { 206744961713Sgirish if (iommu_pagesize > 0x4000) 206844961713Sgirish nxgep->sys_page_sz = 0x4000; 206944961713Sgirish } else { 207044961713Sgirish if (nxgep->sys_page_sz > iommu_pagesize) 207144961713Sgirish nxgep->sys_page_sz = iommu_pagesize; 207244961713Sgirish } 207344961713Sgirish } 207444961713Sgirish } 207544961713Sgirish nxgep->sys_page_mask = ~(nxgep->sys_page_sz - 1); 207644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 20774045d941Ssowmini "==> nxge_setup_system_dma_pages: page %d (ddi_ptob %d) " 20784045d941Ssowmini "default_block_size %d page mask %d", 20794045d941Ssowmini nxgep->sys_page_sz, 20804045d941Ssowmini ddi_ptob(nxgep->dip, (ulong_t)1), 20814045d941Ssowmini nxgep->rx_default_block_size, 20824045d941Ssowmini nxgep->sys_page_mask)); 208344961713Sgirish 208444961713Sgirish 208544961713Sgirish switch (nxgep->sys_page_sz) { 208644961713Sgirish default: 208744961713Sgirish nxgep->sys_page_sz = 0x1000; 208844961713Sgirish nxgep->sys_page_mask = ~(nxgep->sys_page_sz - 1); 208944961713Sgirish nxgep->rx_default_block_size = 0x1000; 209044961713Sgirish nxgep->rx_bksize_code = RBR_BKSIZE_4K; 209144961713Sgirish break; 209244961713Sgirish case 0x1000: 209344961713Sgirish nxgep->rx_default_block_size = 0x1000; 209444961713Sgirish nxgep->rx_bksize_code = RBR_BKSIZE_4K; 209544961713Sgirish break; 209644961713Sgirish case 0x2000: 209744961713Sgirish nxgep->rx_default_block_size = 0x2000; 209844961713Sgirish nxgep->rx_bksize_code = RBR_BKSIZE_8K; 209944961713Sgirish break; 210044961713Sgirish case 0x4000: 210144961713Sgirish nxgep->rx_default_block_size = 0x4000; 210244961713Sgirish nxgep->rx_bksize_code = RBR_BKSIZE_16K; 210344961713Sgirish break; 210444961713Sgirish case 0x8000: 210544961713Sgirish nxgep->rx_default_block_size = 0x8000; 210644961713Sgirish nxgep->rx_bksize_code = RBR_BKSIZE_32K; 210744961713Sgirish break; 210844961713Sgirish } 210944961713Sgirish 211044961713Sgirish #ifndef USE_RX_BIG_BUF 211144961713Sgirish nxge_rx_dma_attr.dma_attr_align = nxgep->sys_page_sz; 211244961713Sgirish #else 211344961713Sgirish nxgep->rx_default_block_size = 0x2000; 211444961713Sgirish nxgep->rx_bksize_code = RBR_BKSIZE_8K; 211544961713Sgirish #endif 211644961713Sgirish /* 211744961713Sgirish * Get the system DMA burst size. 211844961713Sgirish */ 211944961713Sgirish ddi_status = ddi_dma_alloc_handle(nxgep->dip, &nxge_tx_dma_attr, 21204045d941Ssowmini DDI_DMA_DONTWAIT, 0, 21214045d941Ssowmini &nxgep->dmasparehandle); 212244961713Sgirish if (ddi_status != DDI_SUCCESS) { 212344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 21244045d941Ssowmini "ddi_dma_alloc_handle: failed " 21254045d941Ssowmini " status 0x%x", ddi_status)); 212644961713Sgirish goto nxge_get_soft_properties_exit; 212744961713Sgirish } 212844961713Sgirish 212944961713Sgirish ddi_status = ddi_dma_addr_bind_handle(nxgep->dmasparehandle, NULL, 21304045d941Ssowmini (caddr_t)nxgep->dmasparehandle, 21314045d941Ssowmini sizeof (nxgep->dmasparehandle), 21324045d941Ssowmini DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 21334045d941Ssowmini DDI_DMA_DONTWAIT, 0, 21344045d941Ssowmini &cookie, &count); 213544961713Sgirish if (ddi_status != DDI_DMA_MAPPED) { 213644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 21374045d941Ssowmini "Binding spare handle to find system" 21384045d941Ssowmini " burstsize failed.")); 213944961713Sgirish ddi_status = DDI_FAILURE; 214044961713Sgirish goto nxge_get_soft_properties_fail1; 214144961713Sgirish } 214244961713Sgirish 214344961713Sgirish nxgep->sys_burst_sz = ddi_dma_burstsizes(nxgep->dmasparehandle); 214444961713Sgirish (void) ddi_dma_unbind_handle(nxgep->dmasparehandle); 214544961713Sgirish 214644961713Sgirish nxge_get_soft_properties_fail1: 214744961713Sgirish ddi_dma_free_handle(&nxgep->dmasparehandle); 214844961713Sgirish 214944961713Sgirish nxge_get_soft_properties_exit: 215044961713Sgirish 215144961713Sgirish if (ddi_status != DDI_SUCCESS) 215244961713Sgirish status |= (NXGE_ERROR | NXGE_DDI_FAILED); 215344961713Sgirish 215444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 21554045d941Ssowmini "<== nxge_setup_system_dma_pages status = 0x%08x", status)); 215644961713Sgirish return (status); 215744961713Sgirish } 215844961713Sgirish 215944961713Sgirish static nxge_status_t 216044961713Sgirish nxge_alloc_mem_pool(p_nxge_t nxgep) 216144961713Sgirish { 216244961713Sgirish nxge_status_t status = NXGE_OK; 216344961713Sgirish 216444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_alloc_mem_pool")); 216544961713Sgirish 216644961713Sgirish status = nxge_alloc_rx_mem_pool(nxgep); 216744961713Sgirish if (status != NXGE_OK) { 216844961713Sgirish return (NXGE_ERROR); 216944961713Sgirish } 217044961713Sgirish 217144961713Sgirish status = nxge_alloc_tx_mem_pool(nxgep); 217244961713Sgirish if (status != NXGE_OK) { 217344961713Sgirish nxge_free_rx_mem_pool(nxgep); 217444961713Sgirish return (NXGE_ERROR); 217544961713Sgirish } 217644961713Sgirish 217744961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_alloc_mem_pool")); 217844961713Sgirish return (NXGE_OK); 217944961713Sgirish } 218044961713Sgirish 218144961713Sgirish static void 218244961713Sgirish nxge_free_mem_pool(p_nxge_t nxgep) 218344961713Sgirish { 218444961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM_CTL, "==> nxge_free_mem_pool")); 218544961713Sgirish 218644961713Sgirish nxge_free_rx_mem_pool(nxgep); 218744961713Sgirish nxge_free_tx_mem_pool(nxgep); 218844961713Sgirish 218944961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM_CTL, "<== nxge_free_mem_pool")); 219044961713Sgirish } 219144961713Sgirish 2192678453a8Sspeer nxge_status_t 219344961713Sgirish nxge_alloc_rx_mem_pool(p_nxge_t nxgep) 219444961713Sgirish { 2195678453a8Sspeer uint32_t rdc_max; 219644961713Sgirish p_nxge_dma_pt_cfg_t p_all_cfgp; 219744961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 219844961713Sgirish p_nxge_dma_pool_t dma_poolp; 219944961713Sgirish p_nxge_dma_common_t *dma_buf_p; 220044961713Sgirish p_nxge_dma_pool_t dma_cntl_poolp; 220144961713Sgirish p_nxge_dma_common_t *dma_cntl_p; 220244961713Sgirish uint32_t *num_chunks; /* per dma */ 220344961713Sgirish nxge_status_t status = NXGE_OK; 220444961713Sgirish 220544961713Sgirish uint32_t nxge_port_rbr_size; 220644961713Sgirish uint32_t nxge_port_rbr_spare_size; 220744961713Sgirish uint32_t nxge_port_rcr_size; 2208678453a8Sspeer uint32_t rx_cntl_alloc_size; 220944961713Sgirish 221044961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rx_mem_pool")); 221144961713Sgirish 221244961713Sgirish p_all_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 221344961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_all_cfgp->hw_config; 2214678453a8Sspeer rdc_max = NXGE_MAX_RDCS; 221544961713Sgirish 221644961713Sgirish /* 2217678453a8Sspeer * Allocate memory for the common DMA data structures. 221844961713Sgirish */ 221944961713Sgirish dma_poolp = (p_nxge_dma_pool_t)KMEM_ZALLOC(sizeof (nxge_dma_pool_t), 22204045d941Ssowmini KM_SLEEP); 222144961713Sgirish dma_buf_p = (p_nxge_dma_common_t *)KMEM_ZALLOC( 22224045d941Ssowmini sizeof (p_nxge_dma_common_t) * rdc_max, KM_SLEEP); 222344961713Sgirish 222444961713Sgirish dma_cntl_poolp = (p_nxge_dma_pool_t) 22254045d941Ssowmini KMEM_ZALLOC(sizeof (nxge_dma_pool_t), KM_SLEEP); 222644961713Sgirish dma_cntl_p = (p_nxge_dma_common_t *)KMEM_ZALLOC( 22274045d941Ssowmini sizeof (p_nxge_dma_common_t) * rdc_max, KM_SLEEP); 222844961713Sgirish 222944961713Sgirish num_chunks = (uint32_t *)KMEM_ZALLOC( 22304045d941Ssowmini sizeof (uint32_t) * rdc_max, KM_SLEEP); 223144961713Sgirish 223244961713Sgirish /* 2233678453a8Sspeer * Assume that each DMA channel will be configured with 2234678453a8Sspeer * the default block size. 2235678453a8Sspeer * rbr block counts are modulo the batch count (16). 223644961713Sgirish */ 223744961713Sgirish nxge_port_rbr_size = p_all_cfgp->rbr_size; 223844961713Sgirish nxge_port_rcr_size = p_all_cfgp->rcr_size; 223944961713Sgirish 224044961713Sgirish if (!nxge_port_rbr_size) { 224144961713Sgirish nxge_port_rbr_size = NXGE_RBR_RBB_DEFAULT; 224244961713Sgirish } 224344961713Sgirish if (nxge_port_rbr_size % NXGE_RXDMA_POST_BATCH) { 224444961713Sgirish nxge_port_rbr_size = (NXGE_RXDMA_POST_BATCH * 22454045d941Ssowmini (nxge_port_rbr_size / NXGE_RXDMA_POST_BATCH + 1)); 224644961713Sgirish } 224744961713Sgirish 224844961713Sgirish p_all_cfgp->rbr_size = nxge_port_rbr_size; 224944961713Sgirish nxge_port_rbr_spare_size = nxge_rbr_spare_size; 225044961713Sgirish 225144961713Sgirish if (nxge_port_rbr_spare_size % NXGE_RXDMA_POST_BATCH) { 225244961713Sgirish nxge_port_rbr_spare_size = (NXGE_RXDMA_POST_BATCH * 22534045d941Ssowmini (nxge_port_rbr_spare_size / NXGE_RXDMA_POST_BATCH + 1)); 225444961713Sgirish } 225530ac2e7bSml if (nxge_port_rbr_size > RBR_DEFAULT_MAX_BLKS) { 225630ac2e7bSml NXGE_DEBUG_MSG((nxgep, MEM_CTL, 225730ac2e7bSml "nxge_alloc_rx_mem_pool: RBR size too high %d, " 225830ac2e7bSml "set to default %d", 225930ac2e7bSml nxge_port_rbr_size, RBR_DEFAULT_MAX_BLKS)); 226030ac2e7bSml nxge_port_rbr_size = RBR_DEFAULT_MAX_BLKS; 226130ac2e7bSml } 226230ac2e7bSml if (nxge_port_rcr_size > RCR_DEFAULT_MAX) { 226330ac2e7bSml NXGE_DEBUG_MSG((nxgep, MEM_CTL, 226430ac2e7bSml "nxge_alloc_rx_mem_pool: RCR too high %d, " 226530ac2e7bSml "set to default %d", 226630ac2e7bSml nxge_port_rcr_size, RCR_DEFAULT_MAX)); 226730ac2e7bSml nxge_port_rcr_size = RCR_DEFAULT_MAX; 226830ac2e7bSml } 226944961713Sgirish 227044961713Sgirish /* 227144961713Sgirish * N2/NIU has limitation on the descriptor sizes (contiguous 227244961713Sgirish * memory allocation on data buffers to 4M (contig_mem_alloc) 227344961713Sgirish * and little endian for control buffers (must use the ddi/dki mem alloc 227444961713Sgirish * function). 227544961713Sgirish */ 227644961713Sgirish #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 227744961713Sgirish if (nxgep->niu_type == N2_NIU) { 227844961713Sgirish nxge_port_rbr_spare_size = 0; 227944961713Sgirish if ((nxge_port_rbr_size > NXGE_NIU_CONTIG_RBR_MAX) || 22804045d941Ssowmini (!ISP2(nxge_port_rbr_size))) { 228144961713Sgirish nxge_port_rbr_size = NXGE_NIU_CONTIG_RBR_MAX; 228244961713Sgirish } 228344961713Sgirish if ((nxge_port_rcr_size > NXGE_NIU_CONTIG_RCR_MAX) || 22844045d941Ssowmini (!ISP2(nxge_port_rcr_size))) { 228544961713Sgirish nxge_port_rcr_size = NXGE_NIU_CONTIG_RCR_MAX; 228644961713Sgirish } 228744961713Sgirish } 228844961713Sgirish #endif 228944961713Sgirish 229044961713Sgirish /* 229144961713Sgirish * Addresses of receive block ring, receive completion ring and the 229244961713Sgirish * mailbox must be all cache-aligned (64 bytes). 229344961713Sgirish */ 229444961713Sgirish rx_cntl_alloc_size = nxge_port_rbr_size + nxge_port_rbr_spare_size; 229544961713Sgirish rx_cntl_alloc_size *= (sizeof (rx_desc_t)); 229644961713Sgirish rx_cntl_alloc_size += (sizeof (rcr_entry_t) * nxge_port_rcr_size); 229744961713Sgirish rx_cntl_alloc_size += sizeof (rxdma_mailbox_t); 229844961713Sgirish 229944961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_alloc_rx_mem_pool: " 23004045d941Ssowmini "nxge_port_rbr_size = %d nxge_port_rbr_spare_size = %d " 23014045d941Ssowmini "nxge_port_rcr_size = %d " 23024045d941Ssowmini "rx_cntl_alloc_size = %d", 23034045d941Ssowmini nxge_port_rbr_size, nxge_port_rbr_spare_size, 23044045d941Ssowmini nxge_port_rcr_size, 23054045d941Ssowmini rx_cntl_alloc_size)); 230644961713Sgirish 230744961713Sgirish #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 230844961713Sgirish if (nxgep->niu_type == N2_NIU) { 2309678453a8Sspeer uint32_t rx_buf_alloc_size = (nxgep->rx_default_block_size * 2310678453a8Sspeer (nxge_port_rbr_size + nxge_port_rbr_spare_size)); 2311678453a8Sspeer 231244961713Sgirish if (!ISP2(rx_buf_alloc_size)) { 231344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 23144045d941Ssowmini "==> nxge_alloc_rx_mem_pool: " 23154045d941Ssowmini " must be power of 2")); 231644961713Sgirish status |= (NXGE_ERROR | NXGE_DDI_FAILED); 231744961713Sgirish goto nxge_alloc_rx_mem_pool_exit; 231844961713Sgirish } 231944961713Sgirish 232044961713Sgirish if (rx_buf_alloc_size > (1 << 22)) { 232144961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 23224045d941Ssowmini "==> nxge_alloc_rx_mem_pool: " 23234045d941Ssowmini " limit size to 4M")); 232444961713Sgirish status |= (NXGE_ERROR | NXGE_DDI_FAILED); 232544961713Sgirish goto nxge_alloc_rx_mem_pool_exit; 232644961713Sgirish } 232744961713Sgirish 232844961713Sgirish if (rx_cntl_alloc_size < 0x2000) { 232944961713Sgirish rx_cntl_alloc_size = 0x2000; 233044961713Sgirish } 233144961713Sgirish } 233244961713Sgirish #endif 233344961713Sgirish nxgep->nxge_port_rbr_size = nxge_port_rbr_size; 233444961713Sgirish nxgep->nxge_port_rcr_size = nxge_port_rcr_size; 2335678453a8Sspeer nxgep->nxge_port_rbr_spare_size = nxge_port_rbr_spare_size; 2336678453a8Sspeer nxgep->nxge_port_rx_cntl_alloc_size = rx_cntl_alloc_size; 233744961713Sgirish 2338678453a8Sspeer dma_poolp->ndmas = p_cfgp->max_rdcs; 233944961713Sgirish dma_poolp->num_chunks = num_chunks; 234044961713Sgirish dma_poolp->buf_allocated = B_TRUE; 234144961713Sgirish nxgep->rx_buf_pool_p = dma_poolp; 234244961713Sgirish dma_poolp->dma_buf_pool_p = dma_buf_p; 234344961713Sgirish 2344678453a8Sspeer dma_cntl_poolp->ndmas = p_cfgp->max_rdcs; 234544961713Sgirish dma_cntl_poolp->buf_allocated = B_TRUE; 234644961713Sgirish nxgep->rx_cntl_pool_p = dma_cntl_poolp; 234744961713Sgirish dma_cntl_poolp->dma_buf_pool_p = dma_cntl_p; 234844961713Sgirish 2349678453a8Sspeer /* Allocate the receive rings, too. */ 2350678453a8Sspeer nxgep->rx_rbr_rings = 23514045d941Ssowmini KMEM_ZALLOC(sizeof (rx_rbr_rings_t), KM_SLEEP); 2352678453a8Sspeer nxgep->rx_rbr_rings->rbr_rings = 23534045d941Ssowmini KMEM_ZALLOC(sizeof (p_rx_rbr_ring_t) * rdc_max, KM_SLEEP); 2354678453a8Sspeer nxgep->rx_rcr_rings = 23554045d941Ssowmini KMEM_ZALLOC(sizeof (rx_rcr_rings_t), KM_SLEEP); 2356678453a8Sspeer nxgep->rx_rcr_rings->rcr_rings = 23574045d941Ssowmini KMEM_ZALLOC(sizeof (p_rx_rcr_ring_t) * rdc_max, KM_SLEEP); 2358678453a8Sspeer nxgep->rx_mbox_areas_p = 23594045d941Ssowmini KMEM_ZALLOC(sizeof (rx_mbox_areas_t), KM_SLEEP); 2360678453a8Sspeer nxgep->rx_mbox_areas_p->rxmbox_areas = 23614045d941Ssowmini KMEM_ZALLOC(sizeof (p_rx_mbox_t) * rdc_max, KM_SLEEP); 2362678453a8Sspeer 2363678453a8Sspeer nxgep->rx_rbr_rings->ndmas = nxgep->rx_rcr_rings->ndmas = 2364678453a8Sspeer p_cfgp->max_rdcs; 236544961713Sgirish 236644961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 23674045d941Ssowmini "<== nxge_alloc_rx_mem_pool:status 0x%08x", status)); 236844961713Sgirish 2369678453a8Sspeer nxge_alloc_rx_mem_pool_exit: 2370678453a8Sspeer return (status); 2371678453a8Sspeer } 2372678453a8Sspeer 2373678453a8Sspeer /* 2374678453a8Sspeer * nxge_alloc_rxb 2375678453a8Sspeer * 2376678453a8Sspeer * Allocate buffers for an RDC. 2377678453a8Sspeer * 2378678453a8Sspeer * Arguments: 2379678453a8Sspeer * nxgep 2380678453a8Sspeer * channel The channel to map into our kernel space. 2381678453a8Sspeer * 2382678453a8Sspeer * Notes: 2383678453a8Sspeer * 2384678453a8Sspeer * NPI function calls: 2385678453a8Sspeer * 2386678453a8Sspeer * NXGE function calls: 2387678453a8Sspeer * 2388678453a8Sspeer * Registers accessed: 2389678453a8Sspeer * 2390678453a8Sspeer * Context: 2391678453a8Sspeer * 2392678453a8Sspeer * Taking apart: 2393678453a8Sspeer * 2394678453a8Sspeer * Open questions: 2395678453a8Sspeer * 2396678453a8Sspeer */ 2397678453a8Sspeer nxge_status_t 2398678453a8Sspeer nxge_alloc_rxb( 2399678453a8Sspeer p_nxge_t nxgep, 2400678453a8Sspeer int channel) 2401678453a8Sspeer { 2402678453a8Sspeer size_t rx_buf_alloc_size; 2403678453a8Sspeer nxge_status_t status = NXGE_OK; 2404678453a8Sspeer 2405678453a8Sspeer nxge_dma_common_t **data; 2406678453a8Sspeer nxge_dma_common_t **control; 2407678453a8Sspeer uint32_t *num_chunks; 2408678453a8Sspeer 2409678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rbb")); 2410678453a8Sspeer 2411678453a8Sspeer /* 2412678453a8Sspeer * Allocate memory for the receive buffers and descriptor rings. 2413678453a8Sspeer * Replace these allocation functions with the interface functions 2414678453a8Sspeer * provided by the partition manager if/when they are available. 2415678453a8Sspeer */ 2416678453a8Sspeer 2417678453a8Sspeer /* 2418678453a8Sspeer * Allocate memory for the receive buffer blocks. 2419678453a8Sspeer */ 2420678453a8Sspeer rx_buf_alloc_size = (nxgep->rx_default_block_size * 24214045d941Ssowmini (nxgep->nxge_port_rbr_size + nxgep->nxge_port_rbr_spare_size)); 2422678453a8Sspeer 2423678453a8Sspeer data = &nxgep->rx_buf_pool_p->dma_buf_pool_p[channel]; 2424678453a8Sspeer num_chunks = &nxgep->rx_buf_pool_p->num_chunks[channel]; 2425678453a8Sspeer 2426678453a8Sspeer if ((status = nxge_alloc_rx_buf_dma( 2427678453a8Sspeer nxgep, channel, data, rx_buf_alloc_size, 2428678453a8Sspeer nxgep->rx_default_block_size, num_chunks)) != NXGE_OK) { 2429678453a8Sspeer return (status); 243044961713Sgirish } 243144961713Sgirish 2432678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_alloc_rxb(): " 2433678453a8Sspeer "dma %d dma_buf_p %llx &dma_buf_p %llx", channel, *data, data)); 2434678453a8Sspeer 2435678453a8Sspeer /* 2436678453a8Sspeer * Allocate memory for descriptor rings and mailbox. 2437678453a8Sspeer */ 2438678453a8Sspeer control = &nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel]; 2439678453a8Sspeer 2440678453a8Sspeer if ((status = nxge_alloc_rx_cntl_dma( 2441678453a8Sspeer nxgep, channel, control, nxgep->nxge_port_rx_cntl_alloc_size)) 2442678453a8Sspeer != NXGE_OK) { 2443678453a8Sspeer nxge_free_rx_cntl_dma(nxgep, *control); 2444678453a8Sspeer (*data)->buf_alloc_state |= BUF_ALLOCATED_WAIT_FREE; 2445678453a8Sspeer nxge_free_rx_buf_dma(nxgep, *data, *num_chunks); 2446678453a8Sspeer return (status); 2447678453a8Sspeer } 244844961713Sgirish 244944961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 2450678453a8Sspeer "<== nxge_alloc_rx_mem_pool:status 0x%08x", status)); 245144961713Sgirish 245244961713Sgirish return (status); 245344961713Sgirish } 245444961713Sgirish 2455678453a8Sspeer void 2456678453a8Sspeer nxge_free_rxb( 2457678453a8Sspeer p_nxge_t nxgep, 2458678453a8Sspeer int channel) 2459678453a8Sspeer { 2460678453a8Sspeer nxge_dma_common_t *data; 2461678453a8Sspeer nxge_dma_common_t *control; 2462678453a8Sspeer uint32_t num_chunks; 2463678453a8Sspeer 2464678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rbb")); 2465678453a8Sspeer 2466678453a8Sspeer data = nxgep->rx_buf_pool_p->dma_buf_pool_p[channel]; 2467678453a8Sspeer num_chunks = nxgep->rx_buf_pool_p->num_chunks[channel]; 2468678453a8Sspeer nxge_free_rx_buf_dma(nxgep, data, num_chunks); 2469678453a8Sspeer 2470678453a8Sspeer nxgep->rx_buf_pool_p->dma_buf_pool_p[channel] = 0; 2471678453a8Sspeer nxgep->rx_buf_pool_p->num_chunks[channel] = 0; 2472678453a8Sspeer 2473678453a8Sspeer control = nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel]; 2474678453a8Sspeer nxge_free_rx_cntl_dma(nxgep, control); 2475678453a8Sspeer 2476678453a8Sspeer nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel] = 0; 2477678453a8Sspeer 2478678453a8Sspeer KMEM_FREE(data, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK); 2479678453a8Sspeer KMEM_FREE(control, sizeof (nxge_dma_common_t)); 2480678453a8Sspeer 2481678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_alloc_rbb")); 2482678453a8Sspeer } 2483678453a8Sspeer 248444961713Sgirish static void 248544961713Sgirish nxge_free_rx_mem_pool(p_nxge_t nxgep) 248644961713Sgirish { 2487678453a8Sspeer int rdc_max = NXGE_MAX_RDCS; 248844961713Sgirish 248944961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_free_rx_mem_pool")); 249044961713Sgirish 2491678453a8Sspeer if (!nxgep->rx_buf_pool_p || !nxgep->rx_buf_pool_p->buf_allocated) { 249244961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 24934045d941Ssowmini "<== nxge_free_rx_mem_pool " 24944045d941Ssowmini "(null rx buf pool or buf not allocated")); 249544961713Sgirish return; 249644961713Sgirish } 2497678453a8Sspeer if (!nxgep->rx_cntl_pool_p || !nxgep->rx_cntl_pool_p->buf_allocated) { 249844961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 24994045d941Ssowmini "<== nxge_free_rx_mem_pool " 25004045d941Ssowmini "(null rx cntl buf pool or cntl buf not allocated")); 250144961713Sgirish return; 250244961713Sgirish } 250344961713Sgirish 2504678453a8Sspeer KMEM_FREE(nxgep->rx_cntl_pool_p->dma_buf_pool_p, 2505678453a8Sspeer sizeof (p_nxge_dma_common_t) * rdc_max); 2506678453a8Sspeer KMEM_FREE(nxgep->rx_cntl_pool_p, sizeof (nxge_dma_pool_t)); 250744961713Sgirish 2508678453a8Sspeer KMEM_FREE(nxgep->rx_buf_pool_p->num_chunks, 2509678453a8Sspeer sizeof (uint32_t) * rdc_max); 2510678453a8Sspeer KMEM_FREE(nxgep->rx_buf_pool_p->dma_buf_pool_p, 2511678453a8Sspeer sizeof (p_nxge_dma_common_t) * rdc_max); 2512678453a8Sspeer KMEM_FREE(nxgep->rx_buf_pool_p, sizeof (nxge_dma_pool_t)); 251344961713Sgirish 2514678453a8Sspeer nxgep->rx_buf_pool_p = 0; 2515678453a8Sspeer nxgep->rx_cntl_pool_p = 0; 251644961713Sgirish 2517678453a8Sspeer KMEM_FREE(nxgep->rx_rbr_rings->rbr_rings, 2518678453a8Sspeer sizeof (p_rx_rbr_ring_t) * rdc_max); 2519678453a8Sspeer KMEM_FREE(nxgep->rx_rbr_rings, sizeof (rx_rbr_rings_t)); 2520678453a8Sspeer KMEM_FREE(nxgep->rx_rcr_rings->rcr_rings, 2521678453a8Sspeer sizeof (p_rx_rcr_ring_t) * rdc_max); 2522678453a8Sspeer KMEM_FREE(nxgep->rx_rcr_rings, sizeof (rx_rcr_rings_t)); 2523678453a8Sspeer KMEM_FREE(nxgep->rx_mbox_areas_p->rxmbox_areas, 2524678453a8Sspeer sizeof (p_rx_mbox_t) * rdc_max); 2525678453a8Sspeer KMEM_FREE(nxgep->rx_mbox_areas_p, sizeof (rx_mbox_areas_t)); 252644961713Sgirish 2527678453a8Sspeer nxgep->rx_rbr_rings = 0; 2528678453a8Sspeer nxgep->rx_rcr_rings = 0; 2529678453a8Sspeer nxgep->rx_mbox_areas_p = 0; 253044961713Sgirish 253144961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_free_rx_mem_pool")); 253244961713Sgirish } 253344961713Sgirish 253444961713Sgirish 253544961713Sgirish static nxge_status_t 253644961713Sgirish nxge_alloc_rx_buf_dma(p_nxge_t nxgep, uint16_t dma_channel, 253744961713Sgirish p_nxge_dma_common_t *dmap, 253844961713Sgirish size_t alloc_size, size_t block_size, uint32_t *num_chunks) 253944961713Sgirish { 254044961713Sgirish p_nxge_dma_common_t rx_dmap; 254144961713Sgirish nxge_status_t status = NXGE_OK; 254244961713Sgirish size_t total_alloc_size; 254344961713Sgirish size_t allocated = 0; 254444961713Sgirish int i, size_index, array_size; 2545678453a8Sspeer boolean_t use_kmem_alloc = B_FALSE; 254644961713Sgirish 254744961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rx_buf_dma")); 254844961713Sgirish 254944961713Sgirish rx_dmap = (p_nxge_dma_common_t) 25504045d941Ssowmini KMEM_ZALLOC(sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK, 25514045d941Ssowmini KM_SLEEP); 255244961713Sgirish 255344961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 25544045d941Ssowmini " alloc_rx_buf_dma rdc %d asize %x bsize %x bbuf %llx ", 25554045d941Ssowmini dma_channel, alloc_size, block_size, dmap)); 255644961713Sgirish 255744961713Sgirish total_alloc_size = alloc_size; 255844961713Sgirish 255944961713Sgirish #if defined(RX_USE_RECLAIM_POST) 256044961713Sgirish total_alloc_size = alloc_size + alloc_size/4; 256144961713Sgirish #endif 256244961713Sgirish 256344961713Sgirish i = 0; 256444961713Sgirish size_index = 0; 256544961713Sgirish array_size = sizeof (alloc_sizes)/sizeof (size_t); 256644961713Sgirish while ((alloc_sizes[size_index] < alloc_size) && 25674045d941Ssowmini (size_index < array_size)) 25684045d941Ssowmini size_index++; 256944961713Sgirish if (size_index >= array_size) { 257044961713Sgirish size_index = array_size - 1; 257144961713Sgirish } 257244961713Sgirish 2573678453a8Sspeer /* For Neptune, use kmem_alloc if the kmem flag is set. */ 2574678453a8Sspeer if (nxgep->niu_type != N2_NIU && nxge_use_kmem_alloc) { 2575678453a8Sspeer use_kmem_alloc = B_TRUE; 2576678453a8Sspeer #if defined(__i386) || defined(__amd64) 2577678453a8Sspeer size_index = 0; 2578678453a8Sspeer #endif 2579678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2580678453a8Sspeer "==> nxge_alloc_rx_buf_dma: " 2581678453a8Sspeer "Neptune use kmem_alloc() - size_index %d", 2582678453a8Sspeer size_index)); 2583678453a8Sspeer } 2584678453a8Sspeer 258544961713Sgirish while ((allocated < total_alloc_size) && 25864045d941Ssowmini (size_index >= 0) && (i < NXGE_DMA_BLOCK)) { 258744961713Sgirish rx_dmap[i].dma_chunk_index = i; 258844961713Sgirish rx_dmap[i].block_size = block_size; 258944961713Sgirish rx_dmap[i].alength = alloc_sizes[size_index]; 259044961713Sgirish rx_dmap[i].orig_alength = rx_dmap[i].alength; 259144961713Sgirish rx_dmap[i].nblocks = alloc_sizes[size_index] / block_size; 259244961713Sgirish rx_dmap[i].dma_channel = dma_channel; 259344961713Sgirish rx_dmap[i].contig_alloc_type = B_FALSE; 2594678453a8Sspeer rx_dmap[i].kmem_alloc_type = B_FALSE; 2595678453a8Sspeer rx_dmap[i].buf_alloc_type = DDI_MEM_ALLOC; 259644961713Sgirish 259744961713Sgirish /* 259844961713Sgirish * N2/NIU: data buffers must be contiguous as the driver 259944961713Sgirish * needs to call Hypervisor api to set up 260044961713Sgirish * logical pages. 260144961713Sgirish */ 260244961713Sgirish if ((nxgep->niu_type == N2_NIU) && (NXGE_DMA_BLOCK == 1)) { 260344961713Sgirish rx_dmap[i].contig_alloc_type = B_TRUE; 2604678453a8Sspeer rx_dmap[i].buf_alloc_type = CONTIG_MEM_ALLOC; 2605678453a8Sspeer } else if (use_kmem_alloc) { 2606678453a8Sspeer /* For Neptune, use kmem_alloc */ 2607678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2608678453a8Sspeer "==> nxge_alloc_rx_buf_dma: " 2609678453a8Sspeer "Neptune use kmem_alloc()")); 2610678453a8Sspeer rx_dmap[i].kmem_alloc_type = B_TRUE; 2611678453a8Sspeer rx_dmap[i].buf_alloc_type = KMEM_ALLOC; 261244961713Sgirish } 261344961713Sgirish 261444961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 26154045d941Ssowmini "alloc_rx_buf_dma rdc %d chunk %d bufp %llx size %x " 26164045d941Ssowmini "i %d nblocks %d alength %d", 26174045d941Ssowmini dma_channel, i, &rx_dmap[i], block_size, 26184045d941Ssowmini i, rx_dmap[i].nblocks, 26194045d941Ssowmini rx_dmap[i].alength)); 262044961713Sgirish status = nxge_dma_mem_alloc(nxgep, nxge_force_dma, 26214045d941Ssowmini &nxge_rx_dma_attr, 26224045d941Ssowmini rx_dmap[i].alength, 26234045d941Ssowmini &nxge_dev_buf_dma_acc_attr, 26244045d941Ssowmini DDI_DMA_READ | DDI_DMA_STREAMING, 26254045d941Ssowmini (p_nxge_dma_common_t)(&rx_dmap[i])); 262644961713Sgirish if (status != NXGE_OK) { 262744961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2628678453a8Sspeer "nxge_alloc_rx_buf_dma: Alloc Failed: " 2629678453a8Sspeer "dma %d size_index %d size requested %d", 2630678453a8Sspeer dma_channel, 2631678453a8Sspeer size_index, 2632678453a8Sspeer rx_dmap[i].alength)); 263344961713Sgirish size_index--; 263444961713Sgirish } else { 2635678453a8Sspeer rx_dmap[i].buf_alloc_state = BUF_ALLOCATED; 2636678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2637678453a8Sspeer " nxge_alloc_rx_buf_dma DONE alloc mem: " 2638678453a8Sspeer "dma %d dma_buf_p $%p kaddrp $%p alength %d " 2639678453a8Sspeer "buf_alloc_state %d alloc_type %d", 2640678453a8Sspeer dma_channel, 2641678453a8Sspeer &rx_dmap[i], 2642678453a8Sspeer rx_dmap[i].kaddrp, 2643678453a8Sspeer rx_dmap[i].alength, 2644678453a8Sspeer rx_dmap[i].buf_alloc_state, 2645678453a8Sspeer rx_dmap[i].buf_alloc_type)); 2646678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2647678453a8Sspeer " alloc_rx_buf_dma allocated rdc %d " 2648678453a8Sspeer "chunk %d size %x dvma %x bufp %llx kaddrp $%p", 2649678453a8Sspeer dma_channel, i, rx_dmap[i].alength, 2650678453a8Sspeer rx_dmap[i].ioaddr_pp, &rx_dmap[i], 2651678453a8Sspeer rx_dmap[i].kaddrp)); 265244961713Sgirish i++; 265344961713Sgirish allocated += alloc_sizes[size_index]; 265444961713Sgirish } 265544961713Sgirish } 265644961713Sgirish 265744961713Sgirish if (allocated < total_alloc_size) { 265830ac2e7bSml NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2659678453a8Sspeer "==> nxge_alloc_rx_buf_dma: not enough for channel %d " 266030ac2e7bSml "allocated 0x%x requested 0x%x", 266130ac2e7bSml dma_channel, 266230ac2e7bSml allocated, total_alloc_size)); 266330ac2e7bSml status = NXGE_ERROR; 266444961713Sgirish goto nxge_alloc_rx_mem_fail1; 266544961713Sgirish } 266644961713Sgirish 266730ac2e7bSml NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2668678453a8Sspeer "==> nxge_alloc_rx_buf_dma: Allocated for channel %d " 266930ac2e7bSml "allocated 0x%x requested 0x%x", 267030ac2e7bSml dma_channel, 267130ac2e7bSml allocated, total_alloc_size)); 267230ac2e7bSml 267344961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 26744045d941Ssowmini " alloc_rx_buf_dma rdc %d allocated %d chunks", 26754045d941Ssowmini dma_channel, i)); 267644961713Sgirish *num_chunks = i; 267744961713Sgirish *dmap = rx_dmap; 267844961713Sgirish 267944961713Sgirish goto nxge_alloc_rx_mem_exit; 268044961713Sgirish 268144961713Sgirish nxge_alloc_rx_mem_fail1: 268244961713Sgirish KMEM_FREE(rx_dmap, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK); 268344961713Sgirish 268444961713Sgirish nxge_alloc_rx_mem_exit: 268544961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 26864045d941Ssowmini "<== nxge_alloc_rx_buf_dma status 0x%08x", status)); 268744961713Sgirish 268844961713Sgirish return (status); 268944961713Sgirish } 269044961713Sgirish 269144961713Sgirish /*ARGSUSED*/ 269244961713Sgirish static void 269344961713Sgirish nxge_free_rx_buf_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap, 269444961713Sgirish uint32_t num_chunks) 269544961713Sgirish { 269644961713Sgirish int i; 269744961713Sgirish 269844961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 26994045d941Ssowmini "==> nxge_free_rx_buf_dma: # of chunks %d", num_chunks)); 270044961713Sgirish 2701678453a8Sspeer if (dmap == 0) 2702678453a8Sspeer return; 2703678453a8Sspeer 270444961713Sgirish for (i = 0; i < num_chunks; i++) { 270544961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 27064045d941Ssowmini "==> nxge_free_rx_buf_dma: chunk %d dmap 0x%llx", 27074045d941Ssowmini i, dmap)); 2708678453a8Sspeer nxge_dma_free_rx_data_buf(dmap++); 270944961713Sgirish } 271044961713Sgirish 271144961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_free_rx_buf_dma")); 271244961713Sgirish } 271344961713Sgirish 271444961713Sgirish /*ARGSUSED*/ 271544961713Sgirish static nxge_status_t 271644961713Sgirish nxge_alloc_rx_cntl_dma(p_nxge_t nxgep, uint16_t dma_channel, 271744961713Sgirish p_nxge_dma_common_t *dmap, size_t size) 271844961713Sgirish { 271944961713Sgirish p_nxge_dma_common_t rx_dmap; 272044961713Sgirish nxge_status_t status = NXGE_OK; 272144961713Sgirish 272244961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rx_cntl_dma")); 272344961713Sgirish 272444961713Sgirish rx_dmap = (p_nxge_dma_common_t) 27254045d941Ssowmini KMEM_ZALLOC(sizeof (nxge_dma_common_t), KM_SLEEP); 272644961713Sgirish 272744961713Sgirish rx_dmap->contig_alloc_type = B_FALSE; 2728678453a8Sspeer rx_dmap->kmem_alloc_type = B_FALSE; 272944961713Sgirish 273044961713Sgirish status = nxge_dma_mem_alloc(nxgep, nxge_force_dma, 27314045d941Ssowmini &nxge_desc_dma_attr, 27324045d941Ssowmini size, 27334045d941Ssowmini &nxge_dev_desc_dma_acc_attr, 27344045d941Ssowmini DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 27354045d941Ssowmini rx_dmap); 273644961713Sgirish if (status != NXGE_OK) { 273744961713Sgirish goto nxge_alloc_rx_cntl_dma_fail1; 273844961713Sgirish } 273944961713Sgirish 274044961713Sgirish *dmap = rx_dmap; 274144961713Sgirish goto nxge_alloc_rx_cntl_dma_exit; 274244961713Sgirish 274344961713Sgirish nxge_alloc_rx_cntl_dma_fail1: 274444961713Sgirish KMEM_FREE(rx_dmap, sizeof (nxge_dma_common_t)); 274544961713Sgirish 274644961713Sgirish nxge_alloc_rx_cntl_dma_exit: 274744961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 27484045d941Ssowmini "<== nxge_alloc_rx_cntl_dma status 0x%08x", status)); 274944961713Sgirish 2750678453a8Sspeer return (status); 2751678453a8Sspeer } 2752678453a8Sspeer 2753678453a8Sspeer /*ARGSUSED*/ 2754678453a8Sspeer static void 2755678453a8Sspeer nxge_free_rx_cntl_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap) 2756678453a8Sspeer { 2757678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_free_rx_cntl_dma")); 2758678453a8Sspeer 2759678453a8Sspeer if (dmap == 0) 2760678453a8Sspeer return; 2761678453a8Sspeer 2762678453a8Sspeer nxge_dma_mem_free(dmap); 2763678453a8Sspeer 2764678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_free_rx_cntl_dma")); 2765678453a8Sspeer } 2766678453a8Sspeer 2767678453a8Sspeer typedef struct { 2768678453a8Sspeer size_t tx_size; 2769678453a8Sspeer size_t cr_size; 2770678453a8Sspeer size_t threshhold; 2771678453a8Sspeer } nxge_tdc_sizes_t; 2772678453a8Sspeer 2773678453a8Sspeer static 2774678453a8Sspeer nxge_status_t 2775678453a8Sspeer nxge_tdc_sizes( 2776678453a8Sspeer nxge_t *nxgep, 2777678453a8Sspeer nxge_tdc_sizes_t *sizes) 2778678453a8Sspeer { 2779678453a8Sspeer uint32_t threshhold; /* The bcopy() threshhold */ 2780678453a8Sspeer size_t tx_size; /* Transmit buffer size */ 2781678453a8Sspeer size_t cr_size; /* Completion ring size */ 2782678453a8Sspeer 2783678453a8Sspeer /* 2784678453a8Sspeer * Assume that each DMA channel will be configured with the 2785678453a8Sspeer * default transmit buffer size for copying transmit data. 2786678453a8Sspeer * (If a packet is bigger than this, it will not be copied.) 2787678453a8Sspeer */ 2788678453a8Sspeer if (nxgep->niu_type == N2_NIU) { 2789678453a8Sspeer threshhold = TX_BCOPY_SIZE; 2790678453a8Sspeer } else { 2791678453a8Sspeer threshhold = nxge_bcopy_thresh; 2792678453a8Sspeer } 2793678453a8Sspeer tx_size = nxge_tx_ring_size * threshhold; 2794678453a8Sspeer 2795678453a8Sspeer cr_size = nxge_tx_ring_size * sizeof (tx_desc_t); 2796678453a8Sspeer cr_size += sizeof (txdma_mailbox_t); 2797678453a8Sspeer 2798678453a8Sspeer #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 2799678453a8Sspeer if (nxgep->niu_type == N2_NIU) { 2800678453a8Sspeer if (!ISP2(tx_size)) { 2801678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 28024045d941Ssowmini "==> nxge_tdc_sizes: Tx size" 28034045d941Ssowmini " must be power of 2")); 2804678453a8Sspeer return (NXGE_ERROR); 2805678453a8Sspeer } 2806678453a8Sspeer 2807678453a8Sspeer if (tx_size > (1 << 22)) { 2808678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 28094045d941Ssowmini "==> nxge_tdc_sizes: Tx size" 28104045d941Ssowmini " limited to 4M")); 2811678453a8Sspeer return (NXGE_ERROR); 2812678453a8Sspeer } 2813678453a8Sspeer 2814678453a8Sspeer if (cr_size < 0x2000) 2815678453a8Sspeer cr_size = 0x2000; 2816678453a8Sspeer } 2817678453a8Sspeer #endif 2818678453a8Sspeer 2819678453a8Sspeer sizes->threshhold = threshhold; 2820678453a8Sspeer sizes->tx_size = tx_size; 2821678453a8Sspeer sizes->cr_size = cr_size; 2822678453a8Sspeer 2823678453a8Sspeer return (NXGE_OK); 2824678453a8Sspeer } 2825678453a8Sspeer /* 2826678453a8Sspeer * nxge_alloc_txb 2827678453a8Sspeer * 2828678453a8Sspeer * Allocate buffers for an TDC. 2829678453a8Sspeer * 2830678453a8Sspeer * Arguments: 2831678453a8Sspeer * nxgep 2832678453a8Sspeer * channel The channel to map into our kernel space. 2833678453a8Sspeer * 2834678453a8Sspeer * Notes: 2835678453a8Sspeer * 2836678453a8Sspeer * NPI function calls: 2837678453a8Sspeer * 2838678453a8Sspeer * NXGE function calls: 2839678453a8Sspeer * 2840678453a8Sspeer * Registers accessed: 2841678453a8Sspeer * 2842678453a8Sspeer * Context: 2843678453a8Sspeer * 2844678453a8Sspeer * Taking apart: 2845678453a8Sspeer * 2846678453a8Sspeer * Open questions: 2847678453a8Sspeer * 2848678453a8Sspeer */ 2849678453a8Sspeer nxge_status_t 2850678453a8Sspeer nxge_alloc_txb( 2851678453a8Sspeer p_nxge_t nxgep, 2852678453a8Sspeer int channel) 2853678453a8Sspeer { 2854678453a8Sspeer nxge_dma_common_t **dma_buf_p; 2855678453a8Sspeer nxge_dma_common_t **dma_cntl_p; 2856678453a8Sspeer uint32_t *num_chunks; 2857678453a8Sspeer nxge_status_t status = NXGE_OK; 2858678453a8Sspeer 2859678453a8Sspeer nxge_tdc_sizes_t sizes; 2860678453a8Sspeer 2861678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_tbb")); 2862678453a8Sspeer 2863678453a8Sspeer if (nxge_tdc_sizes(nxgep, &sizes) != NXGE_OK) 2864678453a8Sspeer return (NXGE_ERROR); 2865678453a8Sspeer 2866678453a8Sspeer /* 2867678453a8Sspeer * Allocate memory for transmit buffers and descriptor rings. 2868678453a8Sspeer * Replace these allocation functions with the interface functions 2869678453a8Sspeer * provided by the partition manager Real Soon Now. 2870678453a8Sspeer */ 2871678453a8Sspeer dma_buf_p = &nxgep->tx_buf_pool_p->dma_buf_pool_p[channel]; 2872678453a8Sspeer num_chunks = &nxgep->tx_buf_pool_p->num_chunks[channel]; 2873678453a8Sspeer 2874678453a8Sspeer dma_cntl_p = &nxgep->tx_cntl_pool_p->dma_buf_pool_p[channel]; 2875678453a8Sspeer 2876678453a8Sspeer /* 2877678453a8Sspeer * Allocate memory for transmit buffers and descriptor rings. 2878678453a8Sspeer * Replace allocation functions with interface functions provided 2879678453a8Sspeer * by the partition manager when it is available. 2880678453a8Sspeer * 2881678453a8Sspeer * Allocate memory for the transmit buffer pool. 2882678453a8Sspeer */ 2883678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, 28844045d941Ssowmini "sizes: tx: %ld, cr:%ld, th:%ld", 28854045d941Ssowmini sizes.tx_size, sizes.cr_size, sizes.threshhold)); 2886678453a8Sspeer 2887678453a8Sspeer *num_chunks = 0; 2888678453a8Sspeer status = nxge_alloc_tx_buf_dma(nxgep, channel, dma_buf_p, 2889678453a8Sspeer sizes.tx_size, sizes.threshhold, num_chunks); 2890678453a8Sspeer if (status != NXGE_OK) { 2891678453a8Sspeer cmn_err(CE_NOTE, "nxge_alloc_tx_buf_dma failed!"); 2892678453a8Sspeer return (status); 2893678453a8Sspeer } 2894678453a8Sspeer 2895678453a8Sspeer /* 2896678453a8Sspeer * Allocate memory for descriptor rings and mailbox. 2897678453a8Sspeer */ 2898678453a8Sspeer status = nxge_alloc_tx_cntl_dma(nxgep, channel, dma_cntl_p, 2899678453a8Sspeer sizes.cr_size); 2900678453a8Sspeer if (status != NXGE_OK) { 2901678453a8Sspeer nxge_free_tx_buf_dma(nxgep, *dma_buf_p, *num_chunks); 2902678453a8Sspeer cmn_err(CE_NOTE, "nxge_alloc_tx_cntl_dma failed!"); 2903678453a8Sspeer return (status); 2904678453a8Sspeer } 2905678453a8Sspeer 2906678453a8Sspeer return (NXGE_OK); 2907678453a8Sspeer } 2908678453a8Sspeer 2909678453a8Sspeer void 2910678453a8Sspeer nxge_free_txb( 2911678453a8Sspeer p_nxge_t nxgep, 2912678453a8Sspeer int channel) 2913678453a8Sspeer { 2914678453a8Sspeer nxge_dma_common_t *data; 2915678453a8Sspeer nxge_dma_common_t *control; 2916678453a8Sspeer uint32_t num_chunks; 2917678453a8Sspeer 2918678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_free_txb")); 2919678453a8Sspeer 2920678453a8Sspeer data = nxgep->tx_buf_pool_p->dma_buf_pool_p[channel]; 2921678453a8Sspeer num_chunks = nxgep->tx_buf_pool_p->num_chunks[channel]; 2922678453a8Sspeer nxge_free_tx_buf_dma(nxgep, data, num_chunks); 2923678453a8Sspeer 2924678453a8Sspeer nxgep->tx_buf_pool_p->dma_buf_pool_p[channel] = 0; 2925678453a8Sspeer nxgep->tx_buf_pool_p->num_chunks[channel] = 0; 2926678453a8Sspeer 2927678453a8Sspeer control = nxgep->tx_cntl_pool_p->dma_buf_pool_p[channel]; 2928678453a8Sspeer nxge_free_tx_cntl_dma(nxgep, control); 292944961713Sgirish 2930678453a8Sspeer nxgep->tx_cntl_pool_p->dma_buf_pool_p[channel] = 0; 293144961713Sgirish 2932678453a8Sspeer KMEM_FREE(data, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK); 2933678453a8Sspeer KMEM_FREE(control, sizeof (nxge_dma_common_t)); 293444961713Sgirish 2935678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_free_txb")); 293644961713Sgirish } 293744961713Sgirish 2938678453a8Sspeer /* 2939678453a8Sspeer * nxge_alloc_tx_mem_pool 2940678453a8Sspeer * 2941678453a8Sspeer * This function allocates all of the per-port TDC control data structures. 2942678453a8Sspeer * The per-channel (TDC) data structures are allocated when needed. 2943678453a8Sspeer * 2944678453a8Sspeer * Arguments: 2945678453a8Sspeer * nxgep 2946678453a8Sspeer * 2947678453a8Sspeer * Notes: 2948678453a8Sspeer * 2949678453a8Sspeer * Context: 2950678453a8Sspeer * Any domain 2951678453a8Sspeer */ 2952678453a8Sspeer nxge_status_t 295344961713Sgirish nxge_alloc_tx_mem_pool(p_nxge_t nxgep) 295444961713Sgirish { 2955678453a8Sspeer nxge_hw_pt_cfg_t *p_cfgp; 2956678453a8Sspeer nxge_dma_pool_t *dma_poolp; 2957678453a8Sspeer nxge_dma_common_t **dma_buf_p; 2958678453a8Sspeer nxge_dma_pool_t *dma_cntl_poolp; 2959678453a8Sspeer nxge_dma_common_t **dma_cntl_p; 296044961713Sgirish uint32_t *num_chunks; /* per dma */ 2961678453a8Sspeer int tdc_max; 296244961713Sgirish 296344961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM_CTL, "==> nxge_alloc_tx_mem_pool")); 296444961713Sgirish 2965678453a8Sspeer p_cfgp = &nxgep->pt_config.hw_config; 2966678453a8Sspeer tdc_max = NXGE_MAX_TDCS; 296744961713Sgirish 296844961713Sgirish /* 296944961713Sgirish * Allocate memory for each transmit DMA channel. 297044961713Sgirish */ 297144961713Sgirish dma_poolp = (p_nxge_dma_pool_t)KMEM_ZALLOC(sizeof (nxge_dma_pool_t), 29724045d941Ssowmini KM_SLEEP); 297344961713Sgirish dma_buf_p = (p_nxge_dma_common_t *)KMEM_ZALLOC( 29744045d941Ssowmini sizeof (p_nxge_dma_common_t) * tdc_max, KM_SLEEP); 297544961713Sgirish 297644961713Sgirish dma_cntl_poolp = (p_nxge_dma_pool_t) 29774045d941Ssowmini KMEM_ZALLOC(sizeof (nxge_dma_pool_t), KM_SLEEP); 297844961713Sgirish dma_cntl_p = (p_nxge_dma_common_t *)KMEM_ZALLOC( 29794045d941Ssowmini sizeof (p_nxge_dma_common_t) * tdc_max, KM_SLEEP); 298044961713Sgirish 298130ac2e7bSml if (nxge_tx_ring_size > TDC_DEFAULT_MAX) { 298230ac2e7bSml NXGE_DEBUG_MSG((nxgep, MEM_CTL, 298330ac2e7bSml "nxge_alloc_tx_mem_pool: TDC too high %d, " 298430ac2e7bSml "set to default %d", 298530ac2e7bSml nxge_tx_ring_size, TDC_DEFAULT_MAX)); 298630ac2e7bSml nxge_tx_ring_size = TDC_DEFAULT_MAX; 298730ac2e7bSml } 298830ac2e7bSml 298944961713Sgirish #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 299044961713Sgirish /* 299144961713Sgirish * N2/NIU has limitation on the descriptor sizes (contiguous 299244961713Sgirish * memory allocation on data buffers to 4M (contig_mem_alloc) 299344961713Sgirish * and little endian for control buffers (must use the ddi/dki mem alloc 299444961713Sgirish * function). The transmit ring is limited to 8K (includes the 299544961713Sgirish * mailbox). 299644961713Sgirish */ 299744961713Sgirish if (nxgep->niu_type == N2_NIU) { 299844961713Sgirish if ((nxge_tx_ring_size > NXGE_NIU_CONTIG_TX_MAX) || 29994045d941Ssowmini (!ISP2(nxge_tx_ring_size))) { 300044961713Sgirish nxge_tx_ring_size = NXGE_NIU_CONTIG_TX_MAX; 300144961713Sgirish } 300244961713Sgirish } 300344961713Sgirish #endif 300444961713Sgirish 300544961713Sgirish nxgep->nxge_port_tx_ring_size = nxge_tx_ring_size; 300644961713Sgirish 300744961713Sgirish num_chunks = (uint32_t *)KMEM_ZALLOC( 30084045d941Ssowmini sizeof (uint32_t) * tdc_max, KM_SLEEP); 300944961713Sgirish 3010678453a8Sspeer dma_poolp->ndmas = p_cfgp->tdc.owned; 301144961713Sgirish dma_poolp->num_chunks = num_chunks; 301244961713Sgirish dma_poolp->dma_buf_pool_p = dma_buf_p; 301344961713Sgirish nxgep->tx_buf_pool_p = dma_poolp; 301444961713Sgirish 3015678453a8Sspeer dma_poolp->buf_allocated = B_TRUE; 3016678453a8Sspeer 3017678453a8Sspeer dma_cntl_poolp->ndmas = p_cfgp->tdc.owned; 301844961713Sgirish dma_cntl_poolp->dma_buf_pool_p = dma_cntl_p; 301944961713Sgirish nxgep->tx_cntl_pool_p = dma_cntl_poolp; 302044961713Sgirish 3021678453a8Sspeer dma_cntl_poolp->buf_allocated = B_TRUE; 302244961713Sgirish 3023678453a8Sspeer nxgep->tx_rings = 3024678453a8Sspeer KMEM_ZALLOC(sizeof (tx_rings_t), KM_SLEEP); 3025678453a8Sspeer nxgep->tx_rings->rings = 3026678453a8Sspeer KMEM_ZALLOC(sizeof (p_tx_ring_t) * tdc_max, KM_SLEEP); 3027678453a8Sspeer nxgep->tx_mbox_areas_p = 3028678453a8Sspeer KMEM_ZALLOC(sizeof (tx_mbox_areas_t), KM_SLEEP); 3029678453a8Sspeer nxgep->tx_mbox_areas_p->txmbox_areas_p = 3030678453a8Sspeer KMEM_ZALLOC(sizeof (p_tx_mbox_t) * tdc_max, KM_SLEEP); 303144961713Sgirish 3032678453a8Sspeer nxgep->tx_rings->ndmas = p_cfgp->tdc.owned; 303344961713Sgirish 303444961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM_CTL, 30354045d941Ssowmini "==> nxge_alloc_tx_mem_pool: ndmas %d poolp->ndmas %d", 30364045d941Ssowmini tdc_max, dma_poolp->ndmas)); 303744961713Sgirish 3038678453a8Sspeer return (NXGE_OK); 303944961713Sgirish } 304044961713Sgirish 3041678453a8Sspeer nxge_status_t 304244961713Sgirish nxge_alloc_tx_buf_dma(p_nxge_t nxgep, uint16_t dma_channel, 304344961713Sgirish p_nxge_dma_common_t *dmap, size_t alloc_size, 304444961713Sgirish size_t block_size, uint32_t *num_chunks) 304544961713Sgirish { 304644961713Sgirish p_nxge_dma_common_t tx_dmap; 304744961713Sgirish nxge_status_t status = NXGE_OK; 304844961713Sgirish size_t total_alloc_size; 304944961713Sgirish size_t allocated = 0; 305044961713Sgirish int i, size_index, array_size; 305144961713Sgirish 305244961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_tx_buf_dma")); 305344961713Sgirish 305444961713Sgirish tx_dmap = (p_nxge_dma_common_t) 30554045d941Ssowmini KMEM_ZALLOC(sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK, 30564045d941Ssowmini KM_SLEEP); 305744961713Sgirish 305844961713Sgirish total_alloc_size = alloc_size; 305944961713Sgirish i = 0; 306044961713Sgirish size_index = 0; 306144961713Sgirish array_size = sizeof (alloc_sizes) / sizeof (size_t); 306244961713Sgirish while ((alloc_sizes[size_index] < alloc_size) && 30634045d941Ssowmini (size_index < array_size)) 306444961713Sgirish size_index++; 306544961713Sgirish if (size_index >= array_size) { 306644961713Sgirish size_index = array_size - 1; 306744961713Sgirish } 306844961713Sgirish 306944961713Sgirish while ((allocated < total_alloc_size) && 30704045d941Ssowmini (size_index >= 0) && (i < NXGE_DMA_BLOCK)) { 307144961713Sgirish 307244961713Sgirish tx_dmap[i].dma_chunk_index = i; 307344961713Sgirish tx_dmap[i].block_size = block_size; 307444961713Sgirish tx_dmap[i].alength = alloc_sizes[size_index]; 307544961713Sgirish tx_dmap[i].orig_alength = tx_dmap[i].alength; 307644961713Sgirish tx_dmap[i].nblocks = alloc_sizes[size_index] / block_size; 307744961713Sgirish tx_dmap[i].dma_channel = dma_channel; 307844961713Sgirish tx_dmap[i].contig_alloc_type = B_FALSE; 3079678453a8Sspeer tx_dmap[i].kmem_alloc_type = B_FALSE; 308044961713Sgirish 308144961713Sgirish /* 308244961713Sgirish * N2/NIU: data buffers must be contiguous as the driver 308344961713Sgirish * needs to call Hypervisor api to set up 308444961713Sgirish * logical pages. 308544961713Sgirish */ 308644961713Sgirish if ((nxgep->niu_type == N2_NIU) && (NXGE_DMA_BLOCK == 1)) { 308744961713Sgirish tx_dmap[i].contig_alloc_type = B_TRUE; 308844961713Sgirish } 308944961713Sgirish 309044961713Sgirish status = nxge_dma_mem_alloc(nxgep, nxge_force_dma, 30914045d941Ssowmini &nxge_tx_dma_attr, 30924045d941Ssowmini tx_dmap[i].alength, 30934045d941Ssowmini &nxge_dev_buf_dma_acc_attr, 30944045d941Ssowmini DDI_DMA_WRITE | DDI_DMA_STREAMING, 30954045d941Ssowmini (p_nxge_dma_common_t)(&tx_dmap[i])); 309644961713Sgirish if (status != NXGE_OK) { 309744961713Sgirish size_index--; 309844961713Sgirish } else { 309944961713Sgirish i++; 310044961713Sgirish allocated += alloc_sizes[size_index]; 310144961713Sgirish } 310244961713Sgirish } 310344961713Sgirish 310444961713Sgirish if (allocated < total_alloc_size) { 310530ac2e7bSml NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 310630ac2e7bSml "==> nxge_alloc_tx_buf_dma: not enough channel %d: " 310730ac2e7bSml "allocated 0x%x requested 0x%x", 310830ac2e7bSml dma_channel, 310930ac2e7bSml allocated, total_alloc_size)); 311030ac2e7bSml status = NXGE_ERROR; 311144961713Sgirish goto nxge_alloc_tx_mem_fail1; 311244961713Sgirish } 311344961713Sgirish 311430ac2e7bSml NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 311530ac2e7bSml "==> nxge_alloc_tx_buf_dma: Allocated for channel %d: " 311630ac2e7bSml "allocated 0x%x requested 0x%x", 311730ac2e7bSml dma_channel, 311830ac2e7bSml allocated, total_alloc_size)); 311930ac2e7bSml 312044961713Sgirish *num_chunks = i; 312144961713Sgirish *dmap = tx_dmap; 312244961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 31234045d941Ssowmini "==> nxge_alloc_tx_buf_dma dmap 0x%016llx num chunks %d", 31244045d941Ssowmini *dmap, i)); 312544961713Sgirish goto nxge_alloc_tx_mem_exit; 312644961713Sgirish 312744961713Sgirish nxge_alloc_tx_mem_fail1: 312844961713Sgirish KMEM_FREE(tx_dmap, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK); 312944961713Sgirish 313044961713Sgirish nxge_alloc_tx_mem_exit: 313144961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 31324045d941Ssowmini "<== nxge_alloc_tx_buf_dma status 0x%08x", status)); 313344961713Sgirish 313444961713Sgirish return (status); 313544961713Sgirish } 313644961713Sgirish 313744961713Sgirish /*ARGSUSED*/ 313844961713Sgirish static void 313944961713Sgirish nxge_free_tx_buf_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap, 314044961713Sgirish uint32_t num_chunks) 314144961713Sgirish { 314244961713Sgirish int i; 314344961713Sgirish 314444961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM_CTL, "==> nxge_free_tx_buf_dma")); 314544961713Sgirish 3146678453a8Sspeer if (dmap == 0) 3147678453a8Sspeer return; 3148678453a8Sspeer 314944961713Sgirish for (i = 0; i < num_chunks; i++) { 315044961713Sgirish nxge_dma_mem_free(dmap++); 315144961713Sgirish } 315244961713Sgirish 315344961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM_CTL, "<== nxge_free_tx_buf_dma")); 315444961713Sgirish } 315544961713Sgirish 315644961713Sgirish /*ARGSUSED*/ 3157678453a8Sspeer nxge_status_t 315844961713Sgirish nxge_alloc_tx_cntl_dma(p_nxge_t nxgep, uint16_t dma_channel, 315944961713Sgirish p_nxge_dma_common_t *dmap, size_t size) 316044961713Sgirish { 316144961713Sgirish p_nxge_dma_common_t tx_dmap; 316244961713Sgirish nxge_status_t status = NXGE_OK; 316344961713Sgirish 316444961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_tx_cntl_dma")); 316544961713Sgirish tx_dmap = (p_nxge_dma_common_t) 31664045d941Ssowmini KMEM_ZALLOC(sizeof (nxge_dma_common_t), KM_SLEEP); 316744961713Sgirish 316844961713Sgirish tx_dmap->contig_alloc_type = B_FALSE; 3169678453a8Sspeer tx_dmap->kmem_alloc_type = B_FALSE; 317044961713Sgirish 317144961713Sgirish status = nxge_dma_mem_alloc(nxgep, nxge_force_dma, 31724045d941Ssowmini &nxge_desc_dma_attr, 31734045d941Ssowmini size, 31744045d941Ssowmini &nxge_dev_desc_dma_acc_attr, 31754045d941Ssowmini DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 31764045d941Ssowmini tx_dmap); 317744961713Sgirish if (status != NXGE_OK) { 317844961713Sgirish goto nxge_alloc_tx_cntl_dma_fail1; 317944961713Sgirish } 318044961713Sgirish 318144961713Sgirish *dmap = tx_dmap; 318244961713Sgirish goto nxge_alloc_tx_cntl_dma_exit; 318344961713Sgirish 318444961713Sgirish nxge_alloc_tx_cntl_dma_fail1: 318544961713Sgirish KMEM_FREE(tx_dmap, sizeof (nxge_dma_common_t)); 318644961713Sgirish 318744961713Sgirish nxge_alloc_tx_cntl_dma_exit: 318844961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 31894045d941Ssowmini "<== nxge_alloc_tx_cntl_dma status 0x%08x", status)); 319044961713Sgirish 319144961713Sgirish return (status); 319244961713Sgirish } 319344961713Sgirish 319444961713Sgirish /*ARGSUSED*/ 319544961713Sgirish static void 319644961713Sgirish nxge_free_tx_cntl_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap) 319744961713Sgirish { 319844961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_free_tx_cntl_dma")); 319944961713Sgirish 3200678453a8Sspeer if (dmap == 0) 3201678453a8Sspeer return; 3202678453a8Sspeer 320344961713Sgirish nxge_dma_mem_free(dmap); 320444961713Sgirish 320544961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_free_tx_cntl_dma")); 320644961713Sgirish } 320744961713Sgirish 3208678453a8Sspeer /* 3209678453a8Sspeer * nxge_free_tx_mem_pool 3210678453a8Sspeer * 3211678453a8Sspeer * This function frees all of the per-port TDC control data structures. 3212678453a8Sspeer * The per-channel (TDC) data structures are freed when the channel 3213678453a8Sspeer * is stopped. 3214678453a8Sspeer * 3215678453a8Sspeer * Arguments: 3216678453a8Sspeer * nxgep 3217678453a8Sspeer * 3218678453a8Sspeer * Notes: 3219678453a8Sspeer * 3220678453a8Sspeer * Context: 3221678453a8Sspeer * Any domain 3222678453a8Sspeer */ 322344961713Sgirish static void 322444961713Sgirish nxge_free_tx_mem_pool(p_nxge_t nxgep) 322544961713Sgirish { 3226678453a8Sspeer int tdc_max = NXGE_MAX_TDCS; 322744961713Sgirish 3228678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_free_tx_mem_pool")); 322944961713Sgirish 3230678453a8Sspeer if (!nxgep->tx_buf_pool_p || !nxgep->tx_buf_pool_p->buf_allocated) { 3231678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 32324045d941Ssowmini "<== nxge_free_tx_mem_pool " 32334045d941Ssowmini "(null tx buf pool or buf not allocated")); 323444961713Sgirish return; 323544961713Sgirish } 3236678453a8Sspeer if (!nxgep->tx_cntl_pool_p || !nxgep->tx_cntl_pool_p->buf_allocated) { 3237678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 32384045d941Ssowmini "<== nxge_free_tx_mem_pool " 32394045d941Ssowmini "(null tx cntl buf pool or cntl buf not allocated")); 324044961713Sgirish return; 324144961713Sgirish } 324244961713Sgirish 3243678453a8Sspeer /* 1. Free the mailboxes. */ 3244678453a8Sspeer KMEM_FREE(nxgep->tx_mbox_areas_p->txmbox_areas_p, 3245678453a8Sspeer sizeof (p_tx_mbox_t) * tdc_max); 3246678453a8Sspeer KMEM_FREE(nxgep->tx_mbox_areas_p, sizeof (tx_mbox_areas_t)); 324744961713Sgirish 3248678453a8Sspeer nxgep->tx_mbox_areas_p = 0; 324944961713Sgirish 3250678453a8Sspeer /* 2. Free the transmit ring arrays. */ 3251678453a8Sspeer KMEM_FREE(nxgep->tx_rings->rings, 3252678453a8Sspeer sizeof (p_tx_ring_t) * tdc_max); 3253678453a8Sspeer KMEM_FREE(nxgep->tx_rings, sizeof (tx_rings_t)); 325444961713Sgirish 3255678453a8Sspeer nxgep->tx_rings = 0; 325644961713Sgirish 3257678453a8Sspeer /* 3. Free the completion ring data structures. */ 3258678453a8Sspeer KMEM_FREE(nxgep->tx_cntl_pool_p->dma_buf_pool_p, 3259678453a8Sspeer sizeof (p_nxge_dma_common_t) * tdc_max); 3260678453a8Sspeer KMEM_FREE(nxgep->tx_cntl_pool_p, sizeof (nxge_dma_pool_t)); 326144961713Sgirish 3262678453a8Sspeer nxgep->tx_cntl_pool_p = 0; 326344961713Sgirish 3264678453a8Sspeer /* 4. Free the data ring data structures. */ 3265678453a8Sspeer KMEM_FREE(nxgep->tx_buf_pool_p->num_chunks, 3266678453a8Sspeer sizeof (uint32_t) * tdc_max); 3267678453a8Sspeer KMEM_FREE(nxgep->tx_buf_pool_p->dma_buf_pool_p, 3268678453a8Sspeer sizeof (p_nxge_dma_common_t) * tdc_max); 3269678453a8Sspeer KMEM_FREE(nxgep->tx_buf_pool_p, sizeof (nxge_dma_pool_t)); 327044961713Sgirish 3271678453a8Sspeer nxgep->tx_buf_pool_p = 0; 3272678453a8Sspeer 3273678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_free_tx_mem_pool")); 327444961713Sgirish } 327544961713Sgirish 327644961713Sgirish /*ARGSUSED*/ 327744961713Sgirish static nxge_status_t 327844961713Sgirish nxge_dma_mem_alloc(p_nxge_t nxgep, dma_method_t method, 327944961713Sgirish struct ddi_dma_attr *dma_attrp, 328044961713Sgirish size_t length, ddi_device_acc_attr_t *acc_attr_p, uint_t xfer_flags, 328144961713Sgirish p_nxge_dma_common_t dma_p) 328244961713Sgirish { 328344961713Sgirish caddr_t kaddrp; 328444961713Sgirish int ddi_status = DDI_SUCCESS; 328544961713Sgirish boolean_t contig_alloc_type; 3286678453a8Sspeer boolean_t kmem_alloc_type; 328744961713Sgirish 328844961713Sgirish contig_alloc_type = dma_p->contig_alloc_type; 328944961713Sgirish 329044961713Sgirish if (contig_alloc_type && (nxgep->niu_type != N2_NIU)) { 329144961713Sgirish /* 329244961713Sgirish * contig_alloc_type for contiguous memory only allowed 329344961713Sgirish * for N2/NIU. 329444961713Sgirish */ 329544961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 32964045d941Ssowmini "nxge_dma_mem_alloc: alloc type not allowed (%d)", 32974045d941Ssowmini dma_p->contig_alloc_type)); 329844961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 329944961713Sgirish } 330044961713Sgirish 330144961713Sgirish dma_p->dma_handle = NULL; 330244961713Sgirish dma_p->acc_handle = NULL; 330344961713Sgirish dma_p->kaddrp = dma_p->last_kaddrp = NULL; 330444961713Sgirish dma_p->first_ioaddr_pp = dma_p->last_ioaddr_pp = NULL; 330544961713Sgirish ddi_status = ddi_dma_alloc_handle(nxgep->dip, dma_attrp, 33064045d941Ssowmini DDI_DMA_DONTWAIT, NULL, &dma_p->dma_handle); 330744961713Sgirish if (ddi_status != DDI_SUCCESS) { 330844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 33094045d941Ssowmini "nxge_dma_mem_alloc:ddi_dma_alloc_handle failed.")); 331044961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 331144961713Sgirish } 331244961713Sgirish 3313678453a8Sspeer kmem_alloc_type = dma_p->kmem_alloc_type; 3314678453a8Sspeer 331544961713Sgirish switch (contig_alloc_type) { 331644961713Sgirish case B_FALSE: 3317678453a8Sspeer switch (kmem_alloc_type) { 3318678453a8Sspeer case B_FALSE: 3319678453a8Sspeer ddi_status = ddi_dma_mem_alloc(dma_p->dma_handle, 33204045d941Ssowmini length, 33214045d941Ssowmini acc_attr_p, 33224045d941Ssowmini xfer_flags, 33234045d941Ssowmini DDI_DMA_DONTWAIT, 0, &kaddrp, &dma_p->alength, 33244045d941Ssowmini &dma_p->acc_handle); 3325678453a8Sspeer if (ddi_status != DDI_SUCCESS) { 3326678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3327678453a8Sspeer "nxge_dma_mem_alloc: " 3328678453a8Sspeer "ddi_dma_mem_alloc failed")); 3329678453a8Sspeer ddi_dma_free_handle(&dma_p->dma_handle); 3330678453a8Sspeer dma_p->dma_handle = NULL; 3331678453a8Sspeer return (NXGE_ERROR | NXGE_DDI_FAILED); 3332678453a8Sspeer } 3333678453a8Sspeer if (dma_p->alength < length) { 3334678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3335678453a8Sspeer "nxge_dma_mem_alloc:di_dma_mem_alloc " 3336678453a8Sspeer "< length.")); 333744961713Sgirish ddi_dma_mem_free(&dma_p->acc_handle); 3338678453a8Sspeer ddi_dma_free_handle(&dma_p->dma_handle); 333944961713Sgirish dma_p->acc_handle = NULL; 3340678453a8Sspeer dma_p->dma_handle = NULL; 3341678453a8Sspeer return (NXGE_ERROR); 334244961713Sgirish } 334344961713Sgirish 3344678453a8Sspeer ddi_status = ddi_dma_addr_bind_handle(dma_p->dma_handle, 3345678453a8Sspeer NULL, 3346678453a8Sspeer kaddrp, dma_p->alength, xfer_flags, 3347678453a8Sspeer DDI_DMA_DONTWAIT, 3348678453a8Sspeer 0, &dma_p->dma_cookie, &dma_p->ncookies); 3349678453a8Sspeer if (ddi_status != DDI_DMA_MAPPED) { 3350678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3351678453a8Sspeer "nxge_dma_mem_alloc: ddi_dma_addr_bind " 3352678453a8Sspeer "failed " 3353678453a8Sspeer "(staus 0x%x ncookies %d.)", ddi_status, 3354678453a8Sspeer dma_p->ncookies)); 3355678453a8Sspeer if (dma_p->acc_handle) { 3356678453a8Sspeer ddi_dma_mem_free(&dma_p->acc_handle); 3357678453a8Sspeer dma_p->acc_handle = NULL; 3358678453a8Sspeer } 3359678453a8Sspeer ddi_dma_free_handle(&dma_p->dma_handle); 3360678453a8Sspeer dma_p->dma_handle = NULL; 3361678453a8Sspeer return (NXGE_ERROR | NXGE_DDI_FAILED); 3362678453a8Sspeer } 3363678453a8Sspeer 3364678453a8Sspeer if (dma_p->ncookies != 1) { 3365678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, 3366678453a8Sspeer "nxge_dma_mem_alloc:ddi_dma_addr_bind " 3367678453a8Sspeer "> 1 cookie" 3368678453a8Sspeer "(staus 0x%x ncookies %d.)", ddi_status, 3369678453a8Sspeer dma_p->ncookies)); 3370330cd344SMichael Speer (void) ddi_dma_unbind_handle(dma_p->dma_handle); 3371678453a8Sspeer if (dma_p->acc_handle) { 3372678453a8Sspeer ddi_dma_mem_free(&dma_p->acc_handle); 3373678453a8Sspeer dma_p->acc_handle = NULL; 3374678453a8Sspeer } 3375678453a8Sspeer ddi_dma_free_handle(&dma_p->dma_handle); 3376678453a8Sspeer dma_p->dma_handle = NULL; 3377330cd344SMichael Speer dma_p->acc_handle = NULL; 3378678453a8Sspeer return (NXGE_ERROR); 3379678453a8Sspeer } 3380678453a8Sspeer break; 3381678453a8Sspeer 3382678453a8Sspeer case B_TRUE: 3383678453a8Sspeer kaddrp = KMEM_ALLOC(length, KM_NOSLEEP); 3384678453a8Sspeer if (kaddrp == NULL) { 3385678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3386678453a8Sspeer "nxge_dma_mem_alloc:ddi_dma_mem_alloc " 3387678453a8Sspeer "kmem alloc failed")); 3388678453a8Sspeer return (NXGE_ERROR); 3389678453a8Sspeer } 3390678453a8Sspeer 3391678453a8Sspeer dma_p->alength = length; 3392678453a8Sspeer ddi_status = ddi_dma_addr_bind_handle(dma_p->dma_handle, 3393678453a8Sspeer NULL, kaddrp, dma_p->alength, xfer_flags, 3394678453a8Sspeer DDI_DMA_DONTWAIT, 0, 3395678453a8Sspeer &dma_p->dma_cookie, &dma_p->ncookies); 3396678453a8Sspeer if (ddi_status != DDI_DMA_MAPPED) { 3397678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3398678453a8Sspeer "nxge_dma_mem_alloc:ddi_dma_addr_bind: " 3399678453a8Sspeer "(kmem_alloc) failed kaddrp $%p length %d " 3400678453a8Sspeer "(staus 0x%x (%d) ncookies %d.)", 3401678453a8Sspeer kaddrp, length, 3402678453a8Sspeer ddi_status, ddi_status, dma_p->ncookies)); 3403678453a8Sspeer KMEM_FREE(kaddrp, length); 3404678453a8Sspeer dma_p->acc_handle = NULL; 3405678453a8Sspeer ddi_dma_free_handle(&dma_p->dma_handle); 3406678453a8Sspeer dma_p->dma_handle = NULL; 3407678453a8Sspeer dma_p->kaddrp = NULL; 3408678453a8Sspeer return (NXGE_ERROR | NXGE_DDI_FAILED); 3409678453a8Sspeer } 3410678453a8Sspeer 3411678453a8Sspeer if (dma_p->ncookies != 1) { 3412678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, 3413678453a8Sspeer "nxge_dma_mem_alloc:ddi_dma_addr_bind " 3414678453a8Sspeer "(kmem_alloc) > 1 cookie" 3415678453a8Sspeer "(staus 0x%x ncookies %d.)", ddi_status, 34164045d941Ssowmini dma_p->ncookies)); 3417678453a8Sspeer (void) ddi_dma_unbind_handle(dma_p->dma_handle); 3418330cd344SMichael Speer KMEM_FREE(kaddrp, length); 3419678453a8Sspeer ddi_dma_free_handle(&dma_p->dma_handle); 3420678453a8Sspeer dma_p->dma_handle = NULL; 3421330cd344SMichael Speer dma_p->acc_handle = NULL; 3422678453a8Sspeer dma_p->kaddrp = NULL; 3423678453a8Sspeer return (NXGE_ERROR); 342444961713Sgirish } 3425678453a8Sspeer 3426678453a8Sspeer dma_p->kaddrp = kaddrp; 3427678453a8Sspeer 3428678453a8Sspeer NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 34294045d941Ssowmini "nxge_dma_mem_alloc: kmem_alloc dmap $%p " 34304045d941Ssowmini "kaddr $%p alength %d", 34314045d941Ssowmini dma_p, 34324045d941Ssowmini kaddrp, 34334045d941Ssowmini dma_p->alength)); 3434678453a8Sspeer break; 343544961713Sgirish } 343644961713Sgirish break; 343744961713Sgirish 343844961713Sgirish #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 343944961713Sgirish case B_TRUE: 344044961713Sgirish kaddrp = (caddr_t)contig_mem_alloc(length); 344144961713Sgirish if (kaddrp == NULL) { 344244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 34434045d941Ssowmini "nxge_dma_mem_alloc:contig_mem_alloc failed.")); 344444961713Sgirish ddi_dma_free_handle(&dma_p->dma_handle); 344544961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 344644961713Sgirish } 344744961713Sgirish 344844961713Sgirish dma_p->alength = length; 344944961713Sgirish ddi_status = ddi_dma_addr_bind_handle(dma_p->dma_handle, NULL, 34504045d941Ssowmini kaddrp, dma_p->alength, xfer_flags, DDI_DMA_DONTWAIT, 0, 34514045d941Ssowmini &dma_p->dma_cookie, &dma_p->ncookies); 345244961713Sgirish if (ddi_status != DDI_DMA_MAPPED) { 345344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 34544045d941Ssowmini "nxge_dma_mem_alloc:di_dma_addr_bind failed " 34554045d941Ssowmini "(status 0x%x ncookies %d.)", ddi_status, 34564045d941Ssowmini dma_p->ncookies)); 345744961713Sgirish 345844961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 34594045d941Ssowmini "==> nxge_dma_mem_alloc: (not mapped)" 34604045d941Ssowmini "length %lu (0x%x) " 34614045d941Ssowmini "free contig kaddrp $%p " 34624045d941Ssowmini "va_to_pa $%p", 34634045d941Ssowmini length, length, 34644045d941Ssowmini kaddrp, 34654045d941Ssowmini va_to_pa(kaddrp))); 346644961713Sgirish 346744961713Sgirish 346844961713Sgirish contig_mem_free((void *)kaddrp, length); 346944961713Sgirish ddi_dma_free_handle(&dma_p->dma_handle); 347044961713Sgirish 347144961713Sgirish dma_p->dma_handle = NULL; 347244961713Sgirish dma_p->acc_handle = NULL; 347344961713Sgirish dma_p->alength = NULL; 347444961713Sgirish dma_p->kaddrp = NULL; 347544961713Sgirish 347644961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 347744961713Sgirish } 347844961713Sgirish 347944961713Sgirish if (dma_p->ncookies != 1 || 34804045d941Ssowmini (dma_p->dma_cookie.dmac_laddress == NULL)) { 348144961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 34824045d941Ssowmini "nxge_dma_mem_alloc:di_dma_addr_bind > 1 " 34834045d941Ssowmini "cookie or " 34844045d941Ssowmini "dmac_laddress is NULL $%p size %d " 34854045d941Ssowmini " (status 0x%x ncookies %d.)", 34864045d941Ssowmini ddi_status, 34874045d941Ssowmini dma_p->dma_cookie.dmac_laddress, 34884045d941Ssowmini dma_p->dma_cookie.dmac_size, 34894045d941Ssowmini dma_p->ncookies)); 349044961713Sgirish 349144961713Sgirish contig_mem_free((void *)kaddrp, length); 349256d930aeSspeer (void) ddi_dma_unbind_handle(dma_p->dma_handle); 349344961713Sgirish ddi_dma_free_handle(&dma_p->dma_handle); 349444961713Sgirish 349544961713Sgirish dma_p->alength = 0; 349644961713Sgirish dma_p->dma_handle = NULL; 349744961713Sgirish dma_p->acc_handle = NULL; 349844961713Sgirish dma_p->kaddrp = NULL; 349944961713Sgirish 350044961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 350144961713Sgirish } 350244961713Sgirish break; 350344961713Sgirish 350444961713Sgirish #else 350544961713Sgirish case B_TRUE: 350644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 35074045d941Ssowmini "nxge_dma_mem_alloc: invalid alloc type for !sun4v")); 350844961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 350944961713Sgirish #endif 351044961713Sgirish } 351144961713Sgirish 351244961713Sgirish dma_p->kaddrp = kaddrp; 351344961713Sgirish dma_p->last_kaddrp = (unsigned char *)kaddrp + 35144045d941Ssowmini dma_p->alength - RXBUF_64B_ALIGNED; 3515adfcba55Sjoycey #if defined(__i386) 3516adfcba55Sjoycey dma_p->ioaddr_pp = 35174045d941Ssowmini (unsigned char *)(uint32_t)dma_p->dma_cookie.dmac_laddress; 3518adfcba55Sjoycey #else 351944961713Sgirish dma_p->ioaddr_pp = (unsigned char *)dma_p->dma_cookie.dmac_laddress; 3520adfcba55Sjoycey #endif 352144961713Sgirish dma_p->last_ioaddr_pp = 3522adfcba55Sjoycey #if defined(__i386) 35234045d941Ssowmini (unsigned char *)(uint32_t)dma_p->dma_cookie.dmac_laddress + 3524adfcba55Sjoycey #else 35254045d941Ssowmini (unsigned char *)dma_p->dma_cookie.dmac_laddress + 3526adfcba55Sjoycey #endif 35274045d941Ssowmini dma_p->alength - RXBUF_64B_ALIGNED; 352844961713Sgirish 352944961713Sgirish NPI_DMA_ACC_HANDLE_SET(dma_p, dma_p->acc_handle); 353044961713Sgirish 353144961713Sgirish #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 353244961713Sgirish dma_p->orig_ioaddr_pp = 35334045d941Ssowmini (unsigned char *)dma_p->dma_cookie.dmac_laddress; 353444961713Sgirish dma_p->orig_alength = length; 353544961713Sgirish dma_p->orig_kaddrp = kaddrp; 353644961713Sgirish dma_p->orig_vatopa = (uint64_t)va_to_pa(kaddrp); 353744961713Sgirish #endif 353844961713Sgirish 353944961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_dma_mem_alloc: " 35404045d941Ssowmini "dma buffer allocated: dma_p $%p " 35414045d941Ssowmini "return dmac_ladress from cookie $%p cookie dmac_size %d " 35424045d941Ssowmini "dma_p->ioaddr_p $%p " 35434045d941Ssowmini "dma_p->orig_ioaddr_p $%p " 35444045d941Ssowmini "orig_vatopa $%p " 35454045d941Ssowmini "alength %d (0x%x) " 35464045d941Ssowmini "kaddrp $%p " 35474045d941Ssowmini "length %d (0x%x)", 35484045d941Ssowmini dma_p, 35494045d941Ssowmini dma_p->dma_cookie.dmac_laddress, dma_p->dma_cookie.dmac_size, 35504045d941Ssowmini dma_p->ioaddr_pp, 35514045d941Ssowmini dma_p->orig_ioaddr_pp, 35524045d941Ssowmini dma_p->orig_vatopa, 35534045d941Ssowmini dma_p->alength, dma_p->alength, 35544045d941Ssowmini kaddrp, 35554045d941Ssowmini length, length)); 355644961713Sgirish 355744961713Sgirish return (NXGE_OK); 355844961713Sgirish } 355944961713Sgirish 356044961713Sgirish static void 356144961713Sgirish nxge_dma_mem_free(p_nxge_dma_common_t dma_p) 356244961713Sgirish { 356344961713Sgirish if (dma_p->dma_handle != NULL) { 356444961713Sgirish if (dma_p->ncookies) { 356544961713Sgirish (void) ddi_dma_unbind_handle(dma_p->dma_handle); 356644961713Sgirish dma_p->ncookies = 0; 356744961713Sgirish } 356844961713Sgirish ddi_dma_free_handle(&dma_p->dma_handle); 356944961713Sgirish dma_p->dma_handle = NULL; 357044961713Sgirish } 357144961713Sgirish 357244961713Sgirish if (dma_p->acc_handle != NULL) { 357344961713Sgirish ddi_dma_mem_free(&dma_p->acc_handle); 357444961713Sgirish dma_p->acc_handle = NULL; 357544961713Sgirish NPI_DMA_ACC_HANDLE_SET(dma_p, NULL); 357644961713Sgirish } 357744961713Sgirish 357844961713Sgirish #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 357944961713Sgirish if (dma_p->contig_alloc_type && 35804045d941Ssowmini dma_p->orig_kaddrp && dma_p->orig_alength) { 358144961713Sgirish NXGE_DEBUG_MSG((NULL, DMA_CTL, "nxge_dma_mem_free: " 35824045d941Ssowmini "kaddrp $%p (orig_kaddrp $%p)" 35834045d941Ssowmini "mem type %d ", 35844045d941Ssowmini "orig_alength %d " 35854045d941Ssowmini "alength 0x%x (%d)", 35864045d941Ssowmini dma_p->kaddrp, 35874045d941Ssowmini dma_p->orig_kaddrp, 35884045d941Ssowmini dma_p->contig_alloc_type, 35894045d941Ssowmini dma_p->orig_alength, 35904045d941Ssowmini dma_p->alength, dma_p->alength)); 359144961713Sgirish 359244961713Sgirish contig_mem_free(dma_p->orig_kaddrp, dma_p->orig_alength); 359344961713Sgirish dma_p->orig_alength = NULL; 359444961713Sgirish dma_p->orig_kaddrp = NULL; 359544961713Sgirish dma_p->contig_alloc_type = B_FALSE; 359644961713Sgirish } 359744961713Sgirish #endif 359844961713Sgirish dma_p->kaddrp = NULL; 359944961713Sgirish dma_p->alength = NULL; 360044961713Sgirish } 360144961713Sgirish 3602678453a8Sspeer static void 3603678453a8Sspeer nxge_dma_free_rx_data_buf(p_nxge_dma_common_t dma_p) 3604678453a8Sspeer { 3605678453a8Sspeer uint64_t kaddr; 3606678453a8Sspeer uint32_t buf_size; 3607678453a8Sspeer 3608678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, "==> nxge_dma_free_rx_data_buf")); 3609678453a8Sspeer 3610678453a8Sspeer if (dma_p->dma_handle != NULL) { 3611678453a8Sspeer if (dma_p->ncookies) { 3612678453a8Sspeer (void) ddi_dma_unbind_handle(dma_p->dma_handle); 3613678453a8Sspeer dma_p->ncookies = 0; 3614678453a8Sspeer } 3615678453a8Sspeer ddi_dma_free_handle(&dma_p->dma_handle); 3616678453a8Sspeer dma_p->dma_handle = NULL; 3617678453a8Sspeer } 3618678453a8Sspeer 3619678453a8Sspeer if (dma_p->acc_handle != NULL) { 3620678453a8Sspeer ddi_dma_mem_free(&dma_p->acc_handle); 3621678453a8Sspeer dma_p->acc_handle = NULL; 3622678453a8Sspeer NPI_DMA_ACC_HANDLE_SET(dma_p, NULL); 3623678453a8Sspeer } 3624678453a8Sspeer 3625678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, 3626678453a8Sspeer "==> nxge_dma_free_rx_data_buf: dmap $%p buf_alloc_state %d", 3627678453a8Sspeer dma_p, 3628678453a8Sspeer dma_p->buf_alloc_state)); 3629678453a8Sspeer 3630678453a8Sspeer if (!(dma_p->buf_alloc_state & BUF_ALLOCATED_WAIT_FREE)) { 3631678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, 3632678453a8Sspeer "<== nxge_dma_free_rx_data_buf: " 3633678453a8Sspeer "outstanding data buffers")); 3634678453a8Sspeer return; 3635678453a8Sspeer } 3636678453a8Sspeer 3637678453a8Sspeer #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 3638678453a8Sspeer if (dma_p->contig_alloc_type && 36394045d941Ssowmini dma_p->orig_kaddrp && dma_p->orig_alength) { 3640678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, "nxge_dma_free_rx_data_buf: " 3641678453a8Sspeer "kaddrp $%p (orig_kaddrp $%p)" 3642678453a8Sspeer "mem type %d ", 3643678453a8Sspeer "orig_alength %d " 3644678453a8Sspeer "alength 0x%x (%d)", 3645678453a8Sspeer dma_p->kaddrp, 3646678453a8Sspeer dma_p->orig_kaddrp, 3647678453a8Sspeer dma_p->contig_alloc_type, 3648678453a8Sspeer dma_p->orig_alength, 3649678453a8Sspeer dma_p->alength, dma_p->alength)); 3650678453a8Sspeer 3651678453a8Sspeer kaddr = (uint64_t)dma_p->orig_kaddrp; 3652678453a8Sspeer buf_size = dma_p->orig_alength; 3653678453a8Sspeer nxge_free_buf(CONTIG_MEM_ALLOC, kaddr, buf_size); 3654678453a8Sspeer dma_p->orig_alength = NULL; 3655678453a8Sspeer dma_p->orig_kaddrp = NULL; 3656678453a8Sspeer dma_p->contig_alloc_type = B_FALSE; 3657678453a8Sspeer dma_p->kaddrp = NULL; 3658678453a8Sspeer dma_p->alength = NULL; 3659678453a8Sspeer return; 3660678453a8Sspeer } 3661678453a8Sspeer #endif 3662678453a8Sspeer 3663678453a8Sspeer if (dma_p->kmem_alloc_type) { 3664678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, 3665678453a8Sspeer "nxge_dma_free_rx_data_buf: free kmem " 36664045d941Ssowmini "kaddrp $%p (orig_kaddrp $%p)" 36674045d941Ssowmini "alloc type %d " 36684045d941Ssowmini "orig_alength %d " 36694045d941Ssowmini "alength 0x%x (%d)", 36704045d941Ssowmini dma_p->kaddrp, 36714045d941Ssowmini dma_p->orig_kaddrp, 36724045d941Ssowmini dma_p->kmem_alloc_type, 36734045d941Ssowmini dma_p->orig_alength, 36744045d941Ssowmini dma_p->alength, dma_p->alength)); 3675678453a8Sspeer #if defined(__i386) 3676678453a8Sspeer kaddr = (uint64_t)(uint32_t)dma_p->kaddrp; 3677678453a8Sspeer #else 3678678453a8Sspeer kaddr = (uint64_t)dma_p->kaddrp; 3679678453a8Sspeer #endif 3680678453a8Sspeer buf_size = dma_p->orig_alength; 3681678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, 3682678453a8Sspeer "nxge_dma_free_rx_data_buf: free dmap $%p " 3683678453a8Sspeer "kaddr $%p buf_size %d", 3684678453a8Sspeer dma_p, 3685678453a8Sspeer kaddr, buf_size)); 3686678453a8Sspeer nxge_free_buf(KMEM_ALLOC, kaddr, buf_size); 3687678453a8Sspeer dma_p->alength = 0; 3688678453a8Sspeer dma_p->orig_alength = 0; 3689678453a8Sspeer dma_p->kaddrp = NULL; 3690678453a8Sspeer dma_p->kmem_alloc_type = B_FALSE; 3691678453a8Sspeer } 3692678453a8Sspeer 3693678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_dma_free_rx_data_buf")); 3694678453a8Sspeer } 3695678453a8Sspeer 369644961713Sgirish /* 369744961713Sgirish * nxge_m_start() -- start transmitting and receiving. 369844961713Sgirish * 369944961713Sgirish * This function is called by the MAC layer when the first 370044961713Sgirish * stream is open to prepare the hardware ready for sending 370144961713Sgirish * and transmitting packets. 370244961713Sgirish */ 370344961713Sgirish static int 370444961713Sgirish nxge_m_start(void *arg) 370544961713Sgirish { 370644961713Sgirish p_nxge_t nxgep = (p_nxge_t)arg; 370744961713Sgirish 370844961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_start")); 370944961713Sgirish 37106f157acbSml if (nxge_peu_reset_enable && !nxgep->nxge_link_poll_timerid) { 37116f157acbSml (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 37126f157acbSml } 37136f157acbSml 371444961713Sgirish MUTEX_ENTER(nxgep->genlock); 371514ea4bb7Ssd if (nxge_init(nxgep) != NXGE_OK) { 371644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 37174045d941Ssowmini "<== nxge_m_start: initialization failed")); 371844961713Sgirish MUTEX_EXIT(nxgep->genlock); 371944961713Sgirish return (EIO); 372044961713Sgirish } 372144961713Sgirish 372214ea4bb7Ssd if (nxgep->nxge_mac_state == NXGE_MAC_STARTED) 372314ea4bb7Ssd goto nxge_m_start_exit; 372444961713Sgirish /* 372544961713Sgirish * Start timer to check the system error and tx hangs 372644961713Sgirish */ 3727678453a8Sspeer if (!isLDOMguest(nxgep)) 3728678453a8Sspeer nxgep->nxge_timerid = nxge_start_timer(nxgep, 3729678453a8Sspeer nxge_check_hw_state, NXGE_CHECK_TIMER); 3730678453a8Sspeer #if defined(sun4v) 3731678453a8Sspeer else 3732678453a8Sspeer nxge_hio_start_timer(nxgep); 3733678453a8Sspeer #endif 373444961713Sgirish 3735a3c5bd6dSspeer nxgep->link_notify = B_TRUE; 3736a3c5bd6dSspeer 373744961713Sgirish nxgep->nxge_mac_state = NXGE_MAC_STARTED; 373844961713Sgirish 373914ea4bb7Ssd nxge_m_start_exit: 374044961713Sgirish MUTEX_EXIT(nxgep->genlock); 374144961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_start")); 374244961713Sgirish return (0); 374344961713Sgirish } 374444961713Sgirish 3745da14cebeSEric Cheng 3746da14cebeSEric Cheng static boolean_t 3747da14cebeSEric Cheng nxge_check_groups_stopped(p_nxge_t nxgep) 3748da14cebeSEric Cheng { 3749da14cebeSEric Cheng int i; 3750da14cebeSEric Cheng 3751da14cebeSEric Cheng for (i = 0; i < NXGE_MAX_RDC_GROUPS; i++) { 3752da14cebeSEric Cheng if (nxgep->rx_hio_groups[i].started) 3753da14cebeSEric Cheng return (B_FALSE); 3754da14cebeSEric Cheng } 3755da14cebeSEric Cheng 3756da14cebeSEric Cheng return (B_TRUE); 3757da14cebeSEric Cheng } 3758da14cebeSEric Cheng 375944961713Sgirish /* 376044961713Sgirish * nxge_m_stop(): stop transmitting and receiving. 376144961713Sgirish */ 376244961713Sgirish static void 376344961713Sgirish nxge_m_stop(void *arg) 376444961713Sgirish { 376544961713Sgirish p_nxge_t nxgep = (p_nxge_t)arg; 3766da14cebeSEric Cheng boolean_t groups_stopped; 376744961713Sgirish 376844961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_stop")); 376944961713Sgirish 3770da14cebeSEric Cheng groups_stopped = nxge_check_groups_stopped(nxgep); 3771da14cebeSEric Cheng #ifdef later 3772da14cebeSEric Cheng ASSERT(groups_stopped == B_FALSE); 3773da14cebeSEric Cheng #endif 3774da14cebeSEric Cheng 3775da14cebeSEric Cheng if (!groups_stopped) { 3776da14cebeSEric Cheng cmn_err(CE_WARN, "nxge(%d): groups are not stopped!\n", 3777da14cebeSEric Cheng nxgep->instance); 3778da14cebeSEric Cheng return; 3779da14cebeSEric Cheng } 3780da14cebeSEric Cheng 3781d7cf53fcSmisaki Miyashita MUTEX_ENTER(nxgep->genlock); 3782d7cf53fcSmisaki Miyashita nxgep->nxge_mac_state = NXGE_MAC_STOPPING; 3783d7cf53fcSmisaki Miyashita 378444961713Sgirish if (nxgep->nxge_timerid) { 378544961713Sgirish nxge_stop_timer(nxgep, nxgep->nxge_timerid); 378644961713Sgirish nxgep->nxge_timerid = 0; 378744961713Sgirish } 3788a3c5bd6dSspeer 378944961713Sgirish nxge_uninit(nxgep); 379044961713Sgirish 379144961713Sgirish nxgep->nxge_mac_state = NXGE_MAC_STOPPED; 379244961713Sgirish 379344961713Sgirish MUTEX_EXIT(nxgep->genlock); 379444961713Sgirish 379544961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_stop")); 379644961713Sgirish } 379744961713Sgirish 379844961713Sgirish static int 379944961713Sgirish nxge_m_multicst(void *arg, boolean_t add, const uint8_t *mca) 380044961713Sgirish { 380144961713Sgirish p_nxge_t nxgep = (p_nxge_t)arg; 380244961713Sgirish struct ether_addr addrp; 380344961713Sgirish 380444961713Sgirish NXGE_DEBUG_MSG((nxgep, MAC_CTL, 38054045d941Ssowmini "==> nxge_m_multicst: add %d", add)); 380644961713Sgirish 380744961713Sgirish bcopy(mca, (uint8_t *)&addrp, ETHERADDRL); 380844961713Sgirish if (add) { 380944961713Sgirish if (nxge_add_mcast_addr(nxgep, &addrp)) { 381044961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 38114045d941Ssowmini "<== nxge_m_multicst: add multicast failed")); 381244961713Sgirish return (EINVAL); 381344961713Sgirish } 381444961713Sgirish } else { 381544961713Sgirish if (nxge_del_mcast_addr(nxgep, &addrp)) { 381644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 38174045d941Ssowmini "<== nxge_m_multicst: del multicast failed")); 381844961713Sgirish return (EINVAL); 381944961713Sgirish } 382044961713Sgirish } 382144961713Sgirish 382244961713Sgirish NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_m_multicst")); 382344961713Sgirish 382444961713Sgirish return (0); 382544961713Sgirish } 382644961713Sgirish 382744961713Sgirish static int 382844961713Sgirish nxge_m_promisc(void *arg, boolean_t on) 382944961713Sgirish { 383044961713Sgirish p_nxge_t nxgep = (p_nxge_t)arg; 383144961713Sgirish 383244961713Sgirish NXGE_DEBUG_MSG((nxgep, MAC_CTL, 38334045d941Ssowmini "==> nxge_m_promisc: on %d", on)); 383444961713Sgirish 383544961713Sgirish if (nxge_set_promisc(nxgep, on)) { 383644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 38374045d941Ssowmini "<== nxge_m_promisc: set promisc failed")); 383844961713Sgirish return (EINVAL); 383944961713Sgirish } 384044961713Sgirish 384144961713Sgirish NXGE_DEBUG_MSG((nxgep, MAC_CTL, 38424045d941Ssowmini "<== nxge_m_promisc: on %d", on)); 384344961713Sgirish 384444961713Sgirish return (0); 384544961713Sgirish } 384644961713Sgirish 384744961713Sgirish static void 384844961713Sgirish nxge_m_ioctl(void *arg, queue_t *wq, mblk_t *mp) 384944961713Sgirish { 385044961713Sgirish p_nxge_t nxgep = (p_nxge_t)arg; 385156d930aeSspeer struct iocblk *iocp; 385244961713Sgirish boolean_t need_privilege; 385344961713Sgirish int err; 385444961713Sgirish int cmd; 385544961713Sgirish 385644961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_ioctl")); 385744961713Sgirish 385844961713Sgirish iocp = (struct iocblk *)mp->b_rptr; 385944961713Sgirish iocp->ioc_error = 0; 386044961713Sgirish need_privilege = B_TRUE; 386144961713Sgirish cmd = iocp->ioc_cmd; 386244961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_ioctl: cmd 0x%08x", cmd)); 386344961713Sgirish switch (cmd) { 386444961713Sgirish default: 386544961713Sgirish miocnak(wq, mp, 0, EINVAL); 386644961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_ioctl: invalid")); 386744961713Sgirish return; 386844961713Sgirish 386944961713Sgirish case LB_GET_INFO_SIZE: 387044961713Sgirish case LB_GET_INFO: 387144961713Sgirish case LB_GET_MODE: 387244961713Sgirish need_privilege = B_FALSE; 387344961713Sgirish break; 387444961713Sgirish case LB_SET_MODE: 387544961713Sgirish break; 387644961713Sgirish 387744961713Sgirish 387844961713Sgirish case NXGE_GET_MII: 387944961713Sgirish case NXGE_PUT_MII: 388044961713Sgirish case NXGE_GET64: 388144961713Sgirish case NXGE_PUT64: 388244961713Sgirish case NXGE_GET_TX_RING_SZ: 388344961713Sgirish case NXGE_GET_TX_DESC: 388444961713Sgirish case NXGE_TX_SIDE_RESET: 388544961713Sgirish case NXGE_RX_SIDE_RESET: 388644961713Sgirish case NXGE_GLOBAL_RESET: 388744961713Sgirish case NXGE_RESET_MAC: 388844961713Sgirish case NXGE_TX_REGS_DUMP: 388944961713Sgirish case NXGE_RX_REGS_DUMP: 389044961713Sgirish case NXGE_INT_REGS_DUMP: 389144961713Sgirish case NXGE_VIR_INT_REGS_DUMP: 389244961713Sgirish case NXGE_PUT_TCAM: 389344961713Sgirish case NXGE_GET_TCAM: 389444961713Sgirish case NXGE_RTRACE: 389544961713Sgirish case NXGE_RDUMP: 389644961713Sgirish 389744961713Sgirish need_privilege = B_FALSE; 389844961713Sgirish break; 389944961713Sgirish case NXGE_INJECT_ERR: 390044961713Sgirish cmn_err(CE_NOTE, "!nxge_m_ioctl: Inject error\n"); 390144961713Sgirish nxge_err_inject(nxgep, wq, mp); 390244961713Sgirish break; 390344961713Sgirish } 390444961713Sgirish 390544961713Sgirish if (need_privilege) { 390656d930aeSspeer err = secpolicy_net_config(iocp->ioc_cr, B_FALSE); 390744961713Sgirish if (err != 0) { 390844961713Sgirish miocnak(wq, mp, 0, err); 390944961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 39104045d941Ssowmini "<== nxge_m_ioctl: no priv")); 391144961713Sgirish return; 391244961713Sgirish } 391344961713Sgirish } 391444961713Sgirish 391544961713Sgirish switch (cmd) { 391644961713Sgirish 391744961713Sgirish case LB_GET_MODE: 391844961713Sgirish case LB_SET_MODE: 391944961713Sgirish case LB_GET_INFO_SIZE: 392044961713Sgirish case LB_GET_INFO: 392144961713Sgirish nxge_loopback_ioctl(nxgep, wq, mp, iocp); 392244961713Sgirish break; 392344961713Sgirish 392444961713Sgirish case NXGE_GET_MII: 392544961713Sgirish case NXGE_PUT_MII: 392644961713Sgirish case NXGE_PUT_TCAM: 392744961713Sgirish case NXGE_GET_TCAM: 392844961713Sgirish case NXGE_GET64: 392944961713Sgirish case NXGE_PUT64: 393044961713Sgirish case NXGE_GET_TX_RING_SZ: 393144961713Sgirish case NXGE_GET_TX_DESC: 393244961713Sgirish case NXGE_TX_SIDE_RESET: 393344961713Sgirish case NXGE_RX_SIDE_RESET: 393444961713Sgirish case NXGE_GLOBAL_RESET: 393544961713Sgirish case NXGE_RESET_MAC: 393644961713Sgirish case NXGE_TX_REGS_DUMP: 393744961713Sgirish case NXGE_RX_REGS_DUMP: 393844961713Sgirish case NXGE_INT_REGS_DUMP: 393944961713Sgirish case NXGE_VIR_INT_REGS_DUMP: 394044961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 39414045d941Ssowmini "==> nxge_m_ioctl: cmd 0x%x", cmd)); 394244961713Sgirish nxge_hw_ioctl(nxgep, wq, mp, iocp); 394344961713Sgirish break; 394444961713Sgirish } 394544961713Sgirish 394644961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_ioctl")); 394744961713Sgirish } 394844961713Sgirish 394944961713Sgirish extern void nxge_rx_hw_blank(void *arg, time_t ticks, uint_t count); 395044961713Sgirish 3951678453a8Sspeer void 3952da14cebeSEric Cheng nxge_mmac_kstat_update(p_nxge_t nxgep, int slot, boolean_t factory) 395358324dfcSspeer { 395458324dfcSspeer p_nxge_mmac_stats_t mmac_stats; 395558324dfcSspeer int i; 395658324dfcSspeer nxge_mmac_t *mmac_info; 395758324dfcSspeer 395858324dfcSspeer mmac_info = &nxgep->nxge_mmac_info; 395958324dfcSspeer 396058324dfcSspeer mmac_stats = &nxgep->statsp->mmac_stats; 396158324dfcSspeer mmac_stats->mmac_max_cnt = mmac_info->num_mmac; 396258324dfcSspeer mmac_stats->mmac_avail_cnt = mmac_info->naddrfree; 396358324dfcSspeer 396458324dfcSspeer for (i = 0; i < ETHERADDRL; i++) { 396558324dfcSspeer if (factory) { 396658324dfcSspeer mmac_stats->mmac_avail_pool[slot-1].ether_addr_octet[i] 39674045d941Ssowmini = mmac_info->factory_mac_pool[slot][ 39684045d941Ssowmini (ETHERADDRL-1) - i]; 396958324dfcSspeer } else { 397058324dfcSspeer mmac_stats->mmac_avail_pool[slot-1].ether_addr_octet[i] 39714045d941Ssowmini = mmac_info->mac_pool[slot].addr[ 39724045d941Ssowmini (ETHERADDRL - 1) - i]; 397358324dfcSspeer } 397458324dfcSspeer } 397558324dfcSspeer } 397658324dfcSspeer 397758324dfcSspeer /* 397858324dfcSspeer * nxge_altmac_set() -- Set an alternate MAC address 397958324dfcSspeer */ 3980da14cebeSEric Cheng static int 3981da14cebeSEric Cheng nxge_altmac_set(p_nxge_t nxgep, uint8_t *maddr, int slot, 3982da14cebeSEric Cheng int rdctbl, boolean_t usetbl) 398358324dfcSspeer { 398458324dfcSspeer uint8_t addrn; 398558324dfcSspeer uint8_t portn; 398658324dfcSspeer npi_mac_addr_t altmac; 39877b9fa28bSspeer hostinfo_t mac_rdc; 39887b9fa28bSspeer p_nxge_class_pt_cfg_t clscfgp; 398958324dfcSspeer 3990da14cebeSEric Cheng 399158324dfcSspeer altmac.w2 = ((uint16_t)maddr[0] << 8) | ((uint16_t)maddr[1] & 0x0ff); 399258324dfcSspeer altmac.w1 = ((uint16_t)maddr[2] << 8) | ((uint16_t)maddr[3] & 0x0ff); 399358324dfcSspeer altmac.w0 = ((uint16_t)maddr[4] << 8) | ((uint16_t)maddr[5] & 0x0ff); 399458324dfcSspeer 399558324dfcSspeer portn = nxgep->mac.portnum; 399658324dfcSspeer addrn = (uint8_t)slot - 1; 399758324dfcSspeer 3998da14cebeSEric Cheng if (npi_mac_altaddr_entry(nxgep->npi_handle, OP_SET, 3999da14cebeSEric Cheng nxgep->function_num, addrn, &altmac) != NPI_SUCCESS) 400058324dfcSspeer return (EIO); 40017b9fa28bSspeer 40027b9fa28bSspeer /* 40037b9fa28bSspeer * Set the rdc table number for the host info entry 40047b9fa28bSspeer * for this mac address slot. 40057b9fa28bSspeer */ 40067b9fa28bSspeer clscfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 40077b9fa28bSspeer mac_rdc.value = 0; 4008da14cebeSEric Cheng if (usetbl) 4009da14cebeSEric Cheng mac_rdc.bits.w0.rdc_tbl_num = rdctbl; 4010da14cebeSEric Cheng else 4011da14cebeSEric Cheng mac_rdc.bits.w0.rdc_tbl_num = 4012da14cebeSEric Cheng clscfgp->mac_host_info[addrn].rdctbl; 40137b9fa28bSspeer mac_rdc.bits.w0.mac_pref = clscfgp->mac_host_info[addrn].mpr_npr; 40147b9fa28bSspeer 40157b9fa28bSspeer if (npi_mac_hostinfo_entry(nxgep->npi_handle, OP_SET, 40167b9fa28bSspeer nxgep->function_num, addrn, &mac_rdc) != NPI_SUCCESS) { 40177b9fa28bSspeer return (EIO); 40187b9fa28bSspeer } 40197b9fa28bSspeer 402058324dfcSspeer /* 402158324dfcSspeer * Enable comparison with the alternate MAC address. 402258324dfcSspeer * While the first alternate addr is enabled by bit 1 of register 402358324dfcSspeer * BMAC_ALTAD_CMPEN, it is enabled by bit 0 of register 402458324dfcSspeer * XMAC_ADDR_CMPEN, so slot needs to be converted to addrn 402558324dfcSspeer * accordingly before calling npi_mac_altaddr_entry. 402658324dfcSspeer */ 402758324dfcSspeer if (portn == XMAC_PORT_0 || portn == XMAC_PORT_1) 402858324dfcSspeer addrn = (uint8_t)slot - 1; 402958324dfcSspeer else 403058324dfcSspeer addrn = (uint8_t)slot; 403158324dfcSspeer 4032da14cebeSEric Cheng if (npi_mac_altaddr_enable(nxgep->npi_handle, 4033da14cebeSEric Cheng nxgep->function_num, addrn) != NPI_SUCCESS) { 403458324dfcSspeer return (EIO); 4035da14cebeSEric Cheng } 4036da14cebeSEric Cheng 403758324dfcSspeer return (0); 403858324dfcSspeer } 403958324dfcSspeer 404058324dfcSspeer /* 4041da14cebeSEric Cheng * nxeg_m_mmac_add_g() - find an unused address slot, set the address 404258324dfcSspeer * value to the one specified, enable the port to start filtering on 404358324dfcSspeer * the new MAC address. Returns 0 on success. 404458324dfcSspeer */ 4045678453a8Sspeer int 4046da14cebeSEric Cheng nxge_m_mmac_add_g(void *arg, const uint8_t *maddr, int rdctbl, 4047da14cebeSEric Cheng boolean_t usetbl) 404858324dfcSspeer { 404958324dfcSspeer p_nxge_t nxgep = arg; 4050da14cebeSEric Cheng int slot; 405158324dfcSspeer nxge_mmac_t *mmac_info; 405258324dfcSspeer int err; 405358324dfcSspeer nxge_status_t status; 405458324dfcSspeer 405558324dfcSspeer mutex_enter(nxgep->genlock); 405658324dfcSspeer 405758324dfcSspeer /* 405858324dfcSspeer * Make sure that nxge is initialized, if _start() has 405958324dfcSspeer * not been called. 406058324dfcSspeer */ 406158324dfcSspeer if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 406258324dfcSspeer status = nxge_init(nxgep); 406358324dfcSspeer if (status != NXGE_OK) { 406458324dfcSspeer mutex_exit(nxgep->genlock); 406558324dfcSspeer return (ENXIO); 406658324dfcSspeer } 406758324dfcSspeer } 406858324dfcSspeer 406958324dfcSspeer mmac_info = &nxgep->nxge_mmac_info; 407058324dfcSspeer if (mmac_info->naddrfree == 0) { 407158324dfcSspeer mutex_exit(nxgep->genlock); 407258324dfcSspeer return (ENOSPC); 407358324dfcSspeer } 4074da14cebeSEric Cheng 407558324dfcSspeer /* 407658324dfcSspeer * Search for the first available slot. Because naddrfree 407758324dfcSspeer * is not zero, we are guaranteed to find one. 407858324dfcSspeer * Each of the first two ports of Neptune has 16 alternate 4079678453a8Sspeer * MAC slots but only the first 7 (of 15) slots have assigned factory 408058324dfcSspeer * MAC addresses. We first search among the slots without bundled 408158324dfcSspeer * factory MACs. If we fail to find one in that range, then we 408258324dfcSspeer * search the slots with bundled factory MACs. A factory MAC 408358324dfcSspeer * will be wasted while the slot is used with a user MAC address. 408458324dfcSspeer * But the slot could be used by factory MAC again after calling 408558324dfcSspeer * nxge_m_mmac_remove and nxge_m_mmac_reserve. 408658324dfcSspeer */ 4087da14cebeSEric Cheng for (slot = 0; slot <= mmac_info->num_mmac; slot++) { 4088da14cebeSEric Cheng if (!(mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED)) 4089da14cebeSEric Cheng break; 409058324dfcSspeer } 4091da14cebeSEric Cheng 409258324dfcSspeer ASSERT(slot <= mmac_info->num_mmac); 4093e857d0f3SMichael Speer 4094da14cebeSEric Cheng if ((err = nxge_altmac_set(nxgep, (uint8_t *)maddr, slot, rdctbl, 4095da14cebeSEric Cheng usetbl)) != 0) { 409658324dfcSspeer mutex_exit(nxgep->genlock); 409758324dfcSspeer return (err); 409858324dfcSspeer } 4099e857d0f3SMichael Speer 4100da14cebeSEric Cheng bcopy(maddr, mmac_info->mac_pool[slot].addr, ETHERADDRL); 410158324dfcSspeer mmac_info->mac_pool[slot].flags |= MMAC_SLOT_USED; 410258324dfcSspeer mmac_info->mac_pool[slot].flags &= ~MMAC_VENDOR_ADDR; 410358324dfcSspeer mmac_info->naddrfree--; 410458324dfcSspeer nxge_mmac_kstat_update(nxgep, slot, B_FALSE); 410558324dfcSspeer 410658324dfcSspeer mutex_exit(nxgep->genlock); 410758324dfcSspeer return (0); 410858324dfcSspeer } 410958324dfcSspeer 411058324dfcSspeer /* 411158324dfcSspeer * Remove the specified mac address and update the HW not to filter 411258324dfcSspeer * the mac address anymore. 411358324dfcSspeer */ 4114678453a8Sspeer int 4115da14cebeSEric Cheng nxge_m_mmac_remove(void *arg, int slot) 411658324dfcSspeer { 411758324dfcSspeer p_nxge_t nxgep = arg; 411858324dfcSspeer nxge_mmac_t *mmac_info; 411958324dfcSspeer uint8_t addrn; 412058324dfcSspeer uint8_t portn; 412158324dfcSspeer int err = 0; 412258324dfcSspeer nxge_status_t status; 412358324dfcSspeer 412458324dfcSspeer mutex_enter(nxgep->genlock); 412558324dfcSspeer 412658324dfcSspeer /* 412758324dfcSspeer * Make sure that nxge is initialized, if _start() has 412858324dfcSspeer * not been called. 412958324dfcSspeer */ 413058324dfcSspeer if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 413158324dfcSspeer status = nxge_init(nxgep); 413258324dfcSspeer if (status != NXGE_OK) { 413358324dfcSspeer mutex_exit(nxgep->genlock); 413458324dfcSspeer return (ENXIO); 413558324dfcSspeer } 413658324dfcSspeer } 413758324dfcSspeer 413858324dfcSspeer mmac_info = &nxgep->nxge_mmac_info; 413958324dfcSspeer if (slot < 1 || slot > mmac_info->num_mmac) { 414058324dfcSspeer mutex_exit(nxgep->genlock); 414158324dfcSspeer return (EINVAL); 414258324dfcSspeer } 414358324dfcSspeer 414458324dfcSspeer portn = nxgep->mac.portnum; 414558324dfcSspeer if (portn == XMAC_PORT_0 || portn == XMAC_PORT_1) 414658324dfcSspeer addrn = (uint8_t)slot - 1; 414758324dfcSspeer else 414858324dfcSspeer addrn = (uint8_t)slot; 414958324dfcSspeer 415058324dfcSspeer if (mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED) { 415158324dfcSspeer if (npi_mac_altaddr_disable(nxgep->npi_handle, portn, addrn) 41524045d941Ssowmini == NPI_SUCCESS) { 415358324dfcSspeer mmac_info->naddrfree++; 415458324dfcSspeer mmac_info->mac_pool[slot].flags &= ~MMAC_SLOT_USED; 415558324dfcSspeer /* 415658324dfcSspeer * Regardless if the MAC we just stopped filtering 415758324dfcSspeer * is a user addr or a facory addr, we must set 415858324dfcSspeer * the MMAC_VENDOR_ADDR flag if this slot has an 415958324dfcSspeer * associated factory MAC to indicate that a factory 416058324dfcSspeer * MAC is available. 416158324dfcSspeer */ 416258324dfcSspeer if (slot <= mmac_info->num_factory_mmac) { 416358324dfcSspeer mmac_info->mac_pool[slot].flags 41644045d941Ssowmini |= MMAC_VENDOR_ADDR; 416558324dfcSspeer } 416658324dfcSspeer /* 416758324dfcSspeer * Clear mac_pool[slot].addr so that kstat shows 0 416858324dfcSspeer * alternate MAC address if the slot is not used. 416958324dfcSspeer * (But nxge_m_mmac_get returns the factory MAC even 417058324dfcSspeer * when the slot is not used!) 417158324dfcSspeer */ 417258324dfcSspeer bzero(mmac_info->mac_pool[slot].addr, ETHERADDRL); 417358324dfcSspeer nxge_mmac_kstat_update(nxgep, slot, B_FALSE); 417458324dfcSspeer } else { 417558324dfcSspeer err = EIO; 417658324dfcSspeer } 417758324dfcSspeer } else { 417858324dfcSspeer err = EINVAL; 417958324dfcSspeer } 418058324dfcSspeer 418158324dfcSspeer mutex_exit(nxgep->genlock); 418258324dfcSspeer return (err); 418358324dfcSspeer } 418458324dfcSspeer 418558324dfcSspeer /* 4186da14cebeSEric Cheng * The callback to query all the factory addresses. naddr must be the same as 4187da14cebeSEric Cheng * the number of factory addresses (returned by MAC_CAPAB_MULTIFACTADDR), and 4188da14cebeSEric Cheng * mcm_addr is the space allocated for keep all the addresses, whose size is 4189da14cebeSEric Cheng * naddr * MAXMACADDRLEN. 419058324dfcSspeer */ 4191da14cebeSEric Cheng static void 4192da14cebeSEric Cheng nxge_m_getfactaddr(void *arg, uint_t naddr, uint8_t *addr) 419358324dfcSspeer { 4194da14cebeSEric Cheng nxge_t *nxgep = arg; 4195da14cebeSEric Cheng nxge_mmac_t *mmac_info; 4196da14cebeSEric Cheng int i; 419758324dfcSspeer 419858324dfcSspeer mutex_enter(nxgep->genlock); 419958324dfcSspeer 420058324dfcSspeer mmac_info = &nxgep->nxge_mmac_info; 4201da14cebeSEric Cheng ASSERT(naddr == mmac_info->num_factory_mmac); 420258324dfcSspeer 4203da14cebeSEric Cheng for (i = 0; i < naddr; i++) { 4204da14cebeSEric Cheng bcopy(mmac_info->factory_mac_pool[i + 1], 4205da14cebeSEric Cheng addr + i * MAXMACADDRLEN, ETHERADDRL); 420658324dfcSspeer } 420758324dfcSspeer 420858324dfcSspeer mutex_exit(nxgep->genlock); 420958324dfcSspeer } 421058324dfcSspeer 4211da14cebeSEric Cheng 421244961713Sgirish static boolean_t 421344961713Sgirish nxge_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 421444961713Sgirish { 421558324dfcSspeer nxge_t *nxgep = arg; 421658324dfcSspeer uint32_t *txflags = cap_data; 421744961713Sgirish 421858324dfcSspeer switch (cap) { 421958324dfcSspeer case MAC_CAPAB_HCKSUM: 4220678453a8Sspeer NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4221b4d05839Sml "==> nxge_m_getcapab: checksum %d", nxge_cksum_offload)); 4222b4d05839Sml if (nxge_cksum_offload <= 1) { 4223678453a8Sspeer *txflags = HCKSUM_INET_PARTIAL; 4224678453a8Sspeer } 422544961713Sgirish break; 4226678453a8Sspeer 4227da14cebeSEric Cheng case MAC_CAPAB_MULTIFACTADDR: { 4228da14cebeSEric Cheng mac_capab_multifactaddr_t *mfacp = cap_data; 422944961713Sgirish 423058324dfcSspeer mutex_enter(nxgep->genlock); 4231da14cebeSEric Cheng mfacp->mcm_naddr = nxgep->nxge_mmac_info.num_factory_mmac; 4232da14cebeSEric Cheng mfacp->mcm_getaddr = nxge_m_getfactaddr; 423358324dfcSspeer mutex_exit(nxgep->genlock); 423458324dfcSspeer break; 4235da14cebeSEric Cheng } 4236678453a8Sspeer 423730ac2e7bSml case MAC_CAPAB_LSO: { 423830ac2e7bSml mac_capab_lso_t *cap_lso = cap_data; 423930ac2e7bSml 42403d16f8e7Sml if (nxgep->soft_lso_enable) { 4241b4d05839Sml if (nxge_cksum_offload <= 1) { 4242b4d05839Sml cap_lso->lso_flags = LSO_TX_BASIC_TCP_IPV4; 4243b4d05839Sml if (nxge_lso_max > NXGE_LSO_MAXLEN) { 4244b4d05839Sml nxge_lso_max = NXGE_LSO_MAXLEN; 4245b4d05839Sml } 4246b4d05839Sml cap_lso->lso_basic_tcp_ipv4.lso_max = 4247b4d05839Sml nxge_lso_max; 424830ac2e7bSml } 424930ac2e7bSml break; 425030ac2e7bSml } else { 425130ac2e7bSml return (B_FALSE); 425230ac2e7bSml } 425330ac2e7bSml } 425430ac2e7bSml 4255678453a8Sspeer case MAC_CAPAB_RINGS: { 4256da14cebeSEric Cheng mac_capab_rings_t *cap_rings = cap_data; 4257da14cebeSEric Cheng p_nxge_hw_pt_cfg_t p_cfgp = &nxgep->pt_config.hw_config; 4258678453a8Sspeer 4259da14cebeSEric Cheng mutex_enter(nxgep->genlock); 4260da14cebeSEric Cheng if (cap_rings->mr_type == MAC_RING_TYPE_RX) { 4261da14cebeSEric Cheng cap_rings->mr_group_type = MAC_GROUP_TYPE_DYNAMIC; 4262da14cebeSEric Cheng cap_rings->mr_rnum = p_cfgp->max_rdcs; 4263da14cebeSEric Cheng cap_rings->mr_rget = nxge_fill_ring; 4264da14cebeSEric Cheng cap_rings->mr_gnum = p_cfgp->max_rdc_grpids; 4265da14cebeSEric Cheng cap_rings->mr_gget = nxge_hio_group_get; 4266da14cebeSEric Cheng cap_rings->mr_gaddring = nxge_group_add_ring; 4267da14cebeSEric Cheng cap_rings->mr_gremring = nxge_group_rem_ring; 4268da14cebeSEric Cheng 4269da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, RX_CTL, 4270da14cebeSEric Cheng "==> nxge_m_getcapab: rx nrings[%d] ngroups[%d]", 4271da14cebeSEric Cheng p_cfgp->max_rdcs, p_cfgp->max_rdc_grpids)); 4272da14cebeSEric Cheng } else { 4273da14cebeSEric Cheng cap_rings->mr_group_type = MAC_GROUP_TYPE_DYNAMIC; 4274da14cebeSEric Cheng cap_rings->mr_rnum = p_cfgp->tdc.count; 4275da14cebeSEric Cheng cap_rings->mr_rget = nxge_fill_ring; 4276da14cebeSEric Cheng if (isLDOMservice(nxgep)) { 4277da14cebeSEric Cheng /* share capable */ 4278da14cebeSEric Cheng /* Do not report the default ring: hence -1 */ 4279da14cebeSEric Cheng cap_rings->mr_gnum = 4280da14cebeSEric Cheng NXGE_MAX_TDC_GROUPS / nxgep->nports - 1; 4281678453a8Sspeer } else { 4282da14cebeSEric Cheng cap_rings->mr_gnum = 0; 4283678453a8Sspeer } 4284da14cebeSEric Cheng 4285da14cebeSEric Cheng cap_rings->mr_gget = nxge_hio_group_get; 4286da14cebeSEric Cheng cap_rings->mr_gaddring = nxge_group_add_ring; 4287da14cebeSEric Cheng cap_rings->mr_gremring = nxge_group_rem_ring; 4288da14cebeSEric Cheng 4289da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, TX_CTL, 4290da14cebeSEric Cheng "==> nxge_m_getcapab: tx rings # of rings %d", 4291da14cebeSEric Cheng p_cfgp->tdc.count)); 4292da14cebeSEric Cheng } 4293da14cebeSEric Cheng mutex_exit(nxgep->genlock); 4294678453a8Sspeer break; 4295678453a8Sspeer } 4296678453a8Sspeer 4297da14cebeSEric Cheng #if defined(sun4v) 4298678453a8Sspeer case MAC_CAPAB_SHARES: { 4299678453a8Sspeer mac_capab_share_t *mshares = (mac_capab_share_t *)cap_data; 4300678453a8Sspeer 4301678453a8Sspeer /* 4302678453a8Sspeer * Only the service domain driver responds to 4303678453a8Sspeer * this capability request. 4304678453a8Sspeer */ 4305da14cebeSEric Cheng mutex_enter(nxgep->genlock); 4306678453a8Sspeer if (isLDOMservice(nxgep)) { 4307678453a8Sspeer mshares->ms_snum = 3; 4308678453a8Sspeer mshares->ms_handle = (void *)nxgep; 4309678453a8Sspeer mshares->ms_salloc = nxge_hio_share_alloc; 4310678453a8Sspeer mshares->ms_sfree = nxge_hio_share_free; 4311da14cebeSEric Cheng mshares->ms_sadd = nxge_hio_share_add_group; 4312da14cebeSEric Cheng mshares->ms_sremove = nxge_hio_share_rem_group; 4313678453a8Sspeer mshares->ms_squery = nxge_hio_share_query; 4314da14cebeSEric Cheng mshares->ms_sbind = nxge_hio_share_bind; 4315da14cebeSEric Cheng mshares->ms_sunbind = nxge_hio_share_unbind; 4316da14cebeSEric Cheng mutex_exit(nxgep->genlock); 4317da14cebeSEric Cheng } else { 4318da14cebeSEric Cheng mutex_exit(nxgep->genlock); 4319678453a8Sspeer return (B_FALSE); 4320da14cebeSEric Cheng } 4321678453a8Sspeer break; 4322678453a8Sspeer } 4323678453a8Sspeer #endif 432444961713Sgirish default: 432544961713Sgirish return (B_FALSE); 432644961713Sgirish } 432744961713Sgirish return (B_TRUE); 432844961713Sgirish } 432944961713Sgirish 43301bd6825cSml static boolean_t 43311bd6825cSml nxge_param_locked(mac_prop_id_t pr_num) 43321bd6825cSml { 43331bd6825cSml /* 43341bd6825cSml * All adv_* parameters are locked (read-only) while 43351bd6825cSml * the device is in any sort of loopback mode ... 43361bd6825cSml */ 43371bd6825cSml switch (pr_num) { 43383fd94f8cSam case MAC_PROP_ADV_1000FDX_CAP: 43393fd94f8cSam case MAC_PROP_EN_1000FDX_CAP: 43403fd94f8cSam case MAC_PROP_ADV_1000HDX_CAP: 43413fd94f8cSam case MAC_PROP_EN_1000HDX_CAP: 43423fd94f8cSam case MAC_PROP_ADV_100FDX_CAP: 43433fd94f8cSam case MAC_PROP_EN_100FDX_CAP: 43443fd94f8cSam case MAC_PROP_ADV_100HDX_CAP: 43453fd94f8cSam case MAC_PROP_EN_100HDX_CAP: 43463fd94f8cSam case MAC_PROP_ADV_10FDX_CAP: 43473fd94f8cSam case MAC_PROP_EN_10FDX_CAP: 43483fd94f8cSam case MAC_PROP_ADV_10HDX_CAP: 43493fd94f8cSam case MAC_PROP_EN_10HDX_CAP: 43503fd94f8cSam case MAC_PROP_AUTONEG: 43513fd94f8cSam case MAC_PROP_FLOWCTRL: 43521bd6825cSml return (B_TRUE); 43531bd6825cSml } 43541bd6825cSml return (B_FALSE); 43551bd6825cSml } 43561bd6825cSml 43571bd6825cSml /* 43581bd6825cSml * callback functions for set/get of properties 43591bd6825cSml */ 43601bd6825cSml static int 43611bd6825cSml nxge_m_setprop(void *barg, const char *pr_name, mac_prop_id_t pr_num, 43621bd6825cSml uint_t pr_valsize, const void *pr_val) 43631bd6825cSml { 43641bd6825cSml nxge_t *nxgep = barg; 43651bd6825cSml p_nxge_param_t param_arr; 43661bd6825cSml p_nxge_stats_t statsp; 43671bd6825cSml int err = 0; 43681bd6825cSml uint8_t val; 43691bd6825cSml uint32_t cur_mtu, new_mtu, old_framesize; 43701bd6825cSml link_flowctrl_t fl; 43711bd6825cSml 43721bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_setprop")); 43731bd6825cSml param_arr = nxgep->param_arr; 43741bd6825cSml statsp = nxgep->statsp; 43751bd6825cSml mutex_enter(nxgep->genlock); 43761bd6825cSml if (statsp->port_stats.lb_mode != nxge_lb_normal && 43771bd6825cSml nxge_param_locked(pr_num)) { 43781bd6825cSml /* 43791bd6825cSml * All adv_* parameters are locked (read-only) 43801bd6825cSml * while the device is in any sort of loopback mode. 43811bd6825cSml */ 43821bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 43831bd6825cSml "==> nxge_m_setprop: loopback mode: read only")); 43841bd6825cSml mutex_exit(nxgep->genlock); 43851bd6825cSml return (EBUSY); 43861bd6825cSml } 43871bd6825cSml 43881bd6825cSml val = *(uint8_t *)pr_val; 43891bd6825cSml switch (pr_num) { 43903fd94f8cSam case MAC_PROP_EN_1000FDX_CAP: 43911bd6825cSml nxgep->param_en_1000fdx = val; 43921bd6825cSml param_arr[param_anar_1000fdx].value = val; 43931bd6825cSml 43941bd6825cSml goto reprogram; 43951bd6825cSml 43963fd94f8cSam case MAC_PROP_EN_100FDX_CAP: 43971bd6825cSml nxgep->param_en_100fdx = val; 43981bd6825cSml param_arr[param_anar_100fdx].value = val; 43991bd6825cSml 44001bd6825cSml goto reprogram; 44011bd6825cSml 44023fd94f8cSam case MAC_PROP_EN_10FDX_CAP: 44031bd6825cSml nxgep->param_en_10fdx = val; 44041bd6825cSml param_arr[param_anar_10fdx].value = val; 44051bd6825cSml 44061bd6825cSml goto reprogram; 44071bd6825cSml 44083fd94f8cSam case MAC_PROP_EN_1000HDX_CAP: 44093fd94f8cSam case MAC_PROP_EN_100HDX_CAP: 44103fd94f8cSam case MAC_PROP_EN_10HDX_CAP: 44113fd94f8cSam case MAC_PROP_ADV_1000FDX_CAP: 44123fd94f8cSam case MAC_PROP_ADV_1000HDX_CAP: 44133fd94f8cSam case MAC_PROP_ADV_100FDX_CAP: 44143fd94f8cSam case MAC_PROP_ADV_100HDX_CAP: 44153fd94f8cSam case MAC_PROP_ADV_10FDX_CAP: 44163fd94f8cSam case MAC_PROP_ADV_10HDX_CAP: 44173fd94f8cSam case MAC_PROP_STATUS: 44183fd94f8cSam case MAC_PROP_SPEED: 44193fd94f8cSam case MAC_PROP_DUPLEX: 44201bd6825cSml err = EINVAL; /* cannot set read-only properties */ 44211bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 44221bd6825cSml "==> nxge_m_setprop: read only property %d", 44231bd6825cSml pr_num)); 44241bd6825cSml break; 44251bd6825cSml 44263fd94f8cSam case MAC_PROP_AUTONEG: 44271bd6825cSml param_arr[param_autoneg].value = val; 44281bd6825cSml 44291bd6825cSml goto reprogram; 44301bd6825cSml 44313fd94f8cSam case MAC_PROP_MTU: 44321bd6825cSml cur_mtu = nxgep->mac.default_mtu; 44331bd6825cSml bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 44341bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 44351bd6825cSml "==> nxge_m_setprop: set MTU: %d is_jumbo %d", 44361bd6825cSml new_mtu, nxgep->mac.is_jumbo)); 44371bd6825cSml 44381bd6825cSml if (new_mtu == cur_mtu) { 44391bd6825cSml err = 0; 44401bd6825cSml break; 44411bd6825cSml } 4442afdda45fSVasumathi Sundaram - Sun Microsystems if (nxgep->nxge_mac_state == NXGE_MAC_STARTED) { 4443afdda45fSVasumathi Sundaram - Sun Microsystems err = EBUSY; 4444afdda45fSVasumathi Sundaram - Sun Microsystems break; 4445afdda45fSVasumathi Sundaram - Sun Microsystems } 44461bd6825cSml if (new_mtu < NXGE_DEFAULT_MTU || 44471bd6825cSml new_mtu > NXGE_MAXIMUM_MTU) { 44481bd6825cSml err = EINVAL; 44491bd6825cSml break; 44501bd6825cSml } 44511bd6825cSml 44521bd6825cSml if ((new_mtu > NXGE_DEFAULT_MTU) && 44531bd6825cSml !nxgep->mac.is_jumbo) { 44541bd6825cSml err = EINVAL; 44551bd6825cSml break; 44561bd6825cSml } 44571bd6825cSml 44581bd6825cSml old_framesize = (uint32_t)nxgep->mac.maxframesize; 44591bd6825cSml nxgep->mac.maxframesize = (uint16_t) 44601bd6825cSml (new_mtu + NXGE_EHEADER_VLAN_CRC); 44611bd6825cSml if (nxge_mac_set_framesize(nxgep)) { 4462c2d37b8bSml nxgep->mac.maxframesize = 4463c2d37b8bSml (uint16_t)old_framesize; 44641bd6825cSml err = EINVAL; 44651bd6825cSml break; 44661bd6825cSml } 44671bd6825cSml 44681bd6825cSml err = mac_maxsdu_update(nxgep->mach, new_mtu); 44691bd6825cSml if (err) { 4470c2d37b8bSml nxgep->mac.maxframesize = 4471c2d37b8bSml (uint16_t)old_framesize; 44721bd6825cSml err = EINVAL; 44731bd6825cSml break; 44741bd6825cSml } 44751bd6825cSml 44761bd6825cSml nxgep->mac.default_mtu = new_mtu; 44771bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 44781bd6825cSml "==> nxge_m_setprop: set MTU: %d maxframe %d", 44791bd6825cSml new_mtu, nxgep->mac.maxframesize)); 44801bd6825cSml break; 44811bd6825cSml 44823fd94f8cSam case MAC_PROP_FLOWCTRL: 44831bd6825cSml bcopy(pr_val, &fl, sizeof (fl)); 44841bd6825cSml switch (fl) { 44851bd6825cSml default: 44861bd6825cSml err = EINVAL; 44871bd6825cSml break; 44881bd6825cSml 44891bd6825cSml case LINK_FLOWCTRL_NONE: 44901bd6825cSml param_arr[param_anar_pause].value = 0; 44911bd6825cSml break; 44921bd6825cSml 44931bd6825cSml case LINK_FLOWCTRL_RX: 44941bd6825cSml param_arr[param_anar_pause].value = 1; 44951bd6825cSml break; 44961bd6825cSml 44971bd6825cSml case LINK_FLOWCTRL_TX: 44981bd6825cSml case LINK_FLOWCTRL_BI: 44991bd6825cSml err = EINVAL; 45001bd6825cSml break; 45011bd6825cSml } 45021bd6825cSml 45031bd6825cSml reprogram: 45041bd6825cSml if (err == 0) { 45051bd6825cSml if (!nxge_param_link_update(nxgep)) { 45061bd6825cSml err = EINVAL; 45071bd6825cSml } 45081bd6825cSml } 45091bd6825cSml break; 45103fd94f8cSam case MAC_PROP_PRIVATE: 45111bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 45121bd6825cSml "==> nxge_m_setprop: private property")); 45131bd6825cSml err = nxge_set_priv_prop(nxgep, pr_name, pr_valsize, 45141bd6825cSml pr_val); 45151bd6825cSml break; 45164045d941Ssowmini 45174045d941Ssowmini default: 45184045d941Ssowmini err = ENOTSUP; 45194045d941Ssowmini break; 45201bd6825cSml } 45211bd6825cSml 45221bd6825cSml mutex_exit(nxgep->genlock); 45231bd6825cSml 45241bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 45251bd6825cSml "<== nxge_m_setprop (return %d)", err)); 45261bd6825cSml return (err); 45271bd6825cSml } 45281bd6825cSml 45291bd6825cSml static int 45301bd6825cSml nxge_m_getprop(void *barg, const char *pr_name, mac_prop_id_t pr_num, 4531afdda45fSVasumathi Sundaram - Sun Microsystems uint_t pr_flags, uint_t pr_valsize, void *pr_val, uint_t *perm) 45321bd6825cSml { 45331bd6825cSml nxge_t *nxgep = barg; 45341bd6825cSml p_nxge_param_t param_arr = nxgep->param_arr; 45351bd6825cSml p_nxge_stats_t statsp = nxgep->statsp; 45361bd6825cSml int err = 0; 45371bd6825cSml link_flowctrl_t fl; 45381bd6825cSml uint64_t tmp = 0; 45394045d941Ssowmini link_state_t ls; 45403fd94f8cSam boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 45411bd6825cSml 45421bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 45431bd6825cSml "==> nxge_m_getprop: pr_num %d", pr_num)); 45444045d941Ssowmini 45454045d941Ssowmini if (pr_valsize == 0) 45464045d941Ssowmini return (EINVAL); 45474045d941Ssowmini 4548afdda45fSVasumathi Sundaram - Sun Microsystems *perm = MAC_PROP_PERM_RW; 4549afdda45fSVasumathi Sundaram - Sun Microsystems 45503fd94f8cSam if ((is_default) && (pr_num != MAC_PROP_PRIVATE)) { 45514045d941Ssowmini err = nxge_get_def_val(nxgep, pr_num, pr_valsize, pr_val); 45524045d941Ssowmini return (err); 45534045d941Ssowmini } 45544045d941Ssowmini 45551bd6825cSml bzero(pr_val, pr_valsize); 45561bd6825cSml switch (pr_num) { 45573fd94f8cSam case MAC_PROP_DUPLEX: 4558afdda45fSVasumathi Sundaram - Sun Microsystems *perm = MAC_PROP_PERM_READ; 45591bd6825cSml *(uint8_t *)pr_val = statsp->mac_stats.link_duplex; 45601bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 45611bd6825cSml "==> nxge_m_getprop: duplex mode %d", 45621bd6825cSml *(uint8_t *)pr_val)); 45631bd6825cSml break; 45641bd6825cSml 45653fd94f8cSam case MAC_PROP_SPEED: 45661bd6825cSml if (pr_valsize < sizeof (uint64_t)) 45671bd6825cSml return (EINVAL); 4568afdda45fSVasumathi Sundaram - Sun Microsystems *perm = MAC_PROP_PERM_READ; 45691bd6825cSml tmp = statsp->mac_stats.link_speed * 1000000ull; 45701bd6825cSml bcopy(&tmp, pr_val, sizeof (tmp)); 45711bd6825cSml break; 45721bd6825cSml 45733fd94f8cSam case MAC_PROP_STATUS: 45744045d941Ssowmini if (pr_valsize < sizeof (link_state_t)) 45751bd6825cSml return (EINVAL); 4576afdda45fSVasumathi Sundaram - Sun Microsystems *perm = MAC_PROP_PERM_READ; 45774045d941Ssowmini if (!statsp->mac_stats.link_up) 45784045d941Ssowmini ls = LINK_STATE_DOWN; 45794045d941Ssowmini else 45804045d941Ssowmini ls = LINK_STATE_UP; 45814045d941Ssowmini bcopy(&ls, pr_val, sizeof (ls)); 45821bd6825cSml break; 45831bd6825cSml 45843fd94f8cSam case MAC_PROP_AUTONEG: 45851bd6825cSml *(uint8_t *)pr_val = 45861bd6825cSml param_arr[param_autoneg].value; 45871bd6825cSml break; 45881bd6825cSml 45893fd94f8cSam case MAC_PROP_FLOWCTRL: 45901bd6825cSml if (pr_valsize < sizeof (link_flowctrl_t)) 45911bd6825cSml return (EINVAL); 45921bd6825cSml 45931bd6825cSml fl = LINK_FLOWCTRL_NONE; 45941bd6825cSml if (param_arr[param_anar_pause].value) { 45951bd6825cSml fl = LINK_FLOWCTRL_RX; 45961bd6825cSml } 45971bd6825cSml bcopy(&fl, pr_val, sizeof (fl)); 45981bd6825cSml break; 45991bd6825cSml 46003fd94f8cSam case MAC_PROP_ADV_1000FDX_CAP: 4601afdda45fSVasumathi Sundaram - Sun Microsystems *perm = MAC_PROP_PERM_READ; 46021bd6825cSml *(uint8_t *)pr_val = 46031bd6825cSml param_arr[param_anar_1000fdx].value; 46041bd6825cSml break; 46051bd6825cSml 46063fd94f8cSam case MAC_PROP_EN_1000FDX_CAP: 46071bd6825cSml *(uint8_t *)pr_val = nxgep->param_en_1000fdx; 46081bd6825cSml break; 46091bd6825cSml 46103fd94f8cSam case MAC_PROP_ADV_100FDX_CAP: 4611afdda45fSVasumathi Sundaram - Sun Microsystems *perm = MAC_PROP_PERM_READ; 46121bd6825cSml *(uint8_t *)pr_val = 46131bd6825cSml param_arr[param_anar_100fdx].value; 46141bd6825cSml break; 46151bd6825cSml 46163fd94f8cSam case MAC_PROP_EN_100FDX_CAP: 46171bd6825cSml *(uint8_t *)pr_val = nxgep->param_en_100fdx; 46181bd6825cSml break; 46191bd6825cSml 46203fd94f8cSam case MAC_PROP_ADV_10FDX_CAP: 4621afdda45fSVasumathi Sundaram - Sun Microsystems *perm = MAC_PROP_PERM_READ; 46221bd6825cSml *(uint8_t *)pr_val = 46231bd6825cSml param_arr[param_anar_10fdx].value; 46241bd6825cSml break; 46251bd6825cSml 46263fd94f8cSam case MAC_PROP_EN_10FDX_CAP: 46271bd6825cSml *(uint8_t *)pr_val = nxgep->param_en_10fdx; 46281bd6825cSml break; 46291bd6825cSml 46303fd94f8cSam case MAC_PROP_EN_1000HDX_CAP: 46313fd94f8cSam case MAC_PROP_EN_100HDX_CAP: 46323fd94f8cSam case MAC_PROP_EN_10HDX_CAP: 46333fd94f8cSam case MAC_PROP_ADV_1000HDX_CAP: 46343fd94f8cSam case MAC_PROP_ADV_100HDX_CAP: 46353fd94f8cSam case MAC_PROP_ADV_10HDX_CAP: 46364045d941Ssowmini err = ENOTSUP; 46371bd6825cSml break; 46381bd6825cSml 46393fd94f8cSam case MAC_PROP_PRIVATE: 46404045d941Ssowmini err = nxge_get_priv_prop(nxgep, pr_name, pr_flags, 4641afdda45fSVasumathi Sundaram - Sun Microsystems pr_valsize, pr_val, perm); 46424045d941Ssowmini break; 46431bd6825cSml default: 46444045d941Ssowmini err = EINVAL; 46454045d941Ssowmini break; 46461bd6825cSml } 46471bd6825cSml 46481bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_getprop")); 46491bd6825cSml 46501bd6825cSml return (err); 46511bd6825cSml } 46521bd6825cSml 46531bd6825cSml /* ARGSUSED */ 46541bd6825cSml static int 46551bd6825cSml nxge_set_priv_prop(p_nxge_t nxgep, const char *pr_name, uint_t pr_valsize, 46561bd6825cSml const void *pr_val) 46571bd6825cSml { 46581bd6825cSml p_nxge_param_t param_arr = nxgep->param_arr; 46591bd6825cSml int err = 0; 46601bd6825cSml long result; 46611bd6825cSml 46621bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 46631bd6825cSml "==> nxge_set_priv_prop: name %s", pr_name)); 46641bd6825cSml 46651bd6825cSml if (strcmp(pr_name, "_accept_jumbo") == 0) { 46661bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 46671bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 46681bd6825cSml "<== nxge_set_priv_prop: name %s " 46691bd6825cSml "pr_val %s result %d " 46701bd6825cSml "param %d is_jumbo %d", 46711bd6825cSml pr_name, pr_val, result, 46721bd6825cSml param_arr[param_accept_jumbo].value, 46731bd6825cSml nxgep->mac.is_jumbo)); 46741bd6825cSml 46751bd6825cSml if (result > 1 || result < 0) { 46761bd6825cSml err = EINVAL; 46771bd6825cSml } else { 46781bd6825cSml if (nxgep->mac.is_jumbo == 46791bd6825cSml (uint32_t)result) { 46801bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 46811bd6825cSml "no change (%d %d)", 46821bd6825cSml nxgep->mac.is_jumbo, 46831bd6825cSml result)); 46841bd6825cSml return (0); 46851bd6825cSml } 46861bd6825cSml } 46871bd6825cSml 46881bd6825cSml param_arr[param_accept_jumbo].value = result; 46891bd6825cSml nxgep->mac.is_jumbo = B_FALSE; 46901bd6825cSml if (result) { 46911bd6825cSml nxgep->mac.is_jumbo = B_TRUE; 46921bd6825cSml } 46931bd6825cSml 46941bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 46951bd6825cSml "<== nxge_set_priv_prop: name %s (value %d) is_jumbo %d", 46961bd6825cSml pr_name, result, nxgep->mac.is_jumbo)); 46971bd6825cSml 46981bd6825cSml return (err); 46991bd6825cSml } 47001bd6825cSml 47011bd6825cSml /* Blanking */ 47021bd6825cSml if (strcmp(pr_name, "_rxdma_intr_time") == 0) { 47031bd6825cSml err = nxge_param_rx_intr_time(nxgep, NULL, NULL, 47041bd6825cSml (char *)pr_val, 47051bd6825cSml (caddr_t)¶m_arr[param_rxdma_intr_time]); 47061bd6825cSml if (err) { 47071bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 47081bd6825cSml "<== nxge_set_priv_prop: " 47091bd6825cSml "unable to set (%s)", pr_name)); 47101bd6825cSml err = EINVAL; 47111bd6825cSml } else { 47121bd6825cSml err = 0; 47131bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 47141bd6825cSml "<== nxge_set_priv_prop: " 47151bd6825cSml "set (%s)", pr_name)); 47161bd6825cSml } 47171bd6825cSml 47181bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 47191bd6825cSml "<== nxge_set_priv_prop: name %s (value %d)", 47201bd6825cSml pr_name, result)); 47211bd6825cSml 47221bd6825cSml return (err); 47231bd6825cSml } 47241bd6825cSml 47251bd6825cSml if (strcmp(pr_name, "_rxdma_intr_pkts") == 0) { 47261bd6825cSml err = nxge_param_rx_intr_pkts(nxgep, NULL, NULL, 47271bd6825cSml (char *)pr_val, 47281bd6825cSml (caddr_t)¶m_arr[param_rxdma_intr_pkts]); 47291bd6825cSml if (err) { 47301bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 47311bd6825cSml "<== nxge_set_priv_prop: " 47321bd6825cSml "unable to set (%s)", pr_name)); 47331bd6825cSml err = EINVAL; 47341bd6825cSml } else { 47351bd6825cSml err = 0; 47361bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 47371bd6825cSml "<== nxge_set_priv_prop: " 47381bd6825cSml "set (%s)", pr_name)); 47391bd6825cSml } 47401bd6825cSml 47411bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 47421bd6825cSml "<== nxge_set_priv_prop: name %s (value %d)", 47431bd6825cSml pr_name, result)); 47441bd6825cSml 47451bd6825cSml return (err); 47461bd6825cSml } 47471bd6825cSml 47481bd6825cSml /* Classification */ 47491bd6825cSml if (strcmp(pr_name, "_class_opt_ipv4_tcp") == 0) { 47501bd6825cSml if (pr_val == NULL) { 47511bd6825cSml err = EINVAL; 47521bd6825cSml return (err); 47531bd6825cSml } 47541bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 47551bd6825cSml 47561bd6825cSml err = nxge_param_set_ip_opt(nxgep, NULL, 47571bd6825cSml NULL, (char *)pr_val, 47581bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv4_tcp]); 47591bd6825cSml 47601bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 47611bd6825cSml "<== nxge_set_priv_prop: name %s (value 0x%x)", 47621bd6825cSml pr_name, result)); 47631bd6825cSml 47641bd6825cSml return (err); 47651bd6825cSml } 47661bd6825cSml 47671bd6825cSml if (strcmp(pr_name, "_class_opt_ipv4_udp") == 0) { 47681bd6825cSml if (pr_val == NULL) { 47691bd6825cSml err = EINVAL; 47701bd6825cSml return (err); 47711bd6825cSml } 47721bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 47731bd6825cSml 47741bd6825cSml err = nxge_param_set_ip_opt(nxgep, NULL, 47751bd6825cSml NULL, (char *)pr_val, 47761bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv4_udp]); 47771bd6825cSml 47781bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 47791bd6825cSml "<== nxge_set_priv_prop: name %s (value 0x%x)", 47801bd6825cSml pr_name, result)); 47811bd6825cSml 47821bd6825cSml return (err); 47831bd6825cSml } 47841bd6825cSml if (strcmp(pr_name, "_class_opt_ipv4_ah") == 0) { 47851bd6825cSml if (pr_val == NULL) { 47861bd6825cSml err = EINVAL; 47871bd6825cSml return (err); 47881bd6825cSml } 47891bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 47901bd6825cSml 47911bd6825cSml err = nxge_param_set_ip_opt(nxgep, NULL, 47921bd6825cSml NULL, (char *)pr_val, 47931bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv4_ah]); 47941bd6825cSml 47951bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 47961bd6825cSml "<== nxge_set_priv_prop: name %s (value 0x%x)", 47971bd6825cSml pr_name, result)); 47981bd6825cSml 47991bd6825cSml return (err); 48001bd6825cSml } 48011bd6825cSml if (strcmp(pr_name, "_class_opt_ipv4_sctp") == 0) { 48021bd6825cSml if (pr_val == NULL) { 48031bd6825cSml err = EINVAL; 48041bd6825cSml return (err); 48051bd6825cSml } 48061bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 48071bd6825cSml 48081bd6825cSml err = nxge_param_set_ip_opt(nxgep, NULL, 48091bd6825cSml NULL, (char *)pr_val, 48101bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv4_sctp]); 48111bd6825cSml 48121bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 48131bd6825cSml "<== nxge_set_priv_prop: name %s (value 0x%x)", 48141bd6825cSml pr_name, result)); 48151bd6825cSml 48161bd6825cSml return (err); 48171bd6825cSml } 48181bd6825cSml 48191bd6825cSml if (strcmp(pr_name, "_class_opt_ipv6_tcp") == 0) { 48201bd6825cSml if (pr_val == NULL) { 48211bd6825cSml err = EINVAL; 48221bd6825cSml return (err); 48231bd6825cSml } 48241bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 48251bd6825cSml 48261bd6825cSml err = nxge_param_set_ip_opt(nxgep, NULL, 48271bd6825cSml NULL, (char *)pr_val, 48281bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv6_tcp]); 48291bd6825cSml 48301bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 48311bd6825cSml "<== nxge_set_priv_prop: name %s (value 0x%x)", 48321bd6825cSml pr_name, result)); 48331bd6825cSml 48341bd6825cSml return (err); 48351bd6825cSml } 48361bd6825cSml 48371bd6825cSml if (strcmp(pr_name, "_class_opt_ipv6_udp") == 0) { 48381bd6825cSml if (pr_val == NULL) { 48391bd6825cSml err = EINVAL; 48401bd6825cSml return (err); 48411bd6825cSml } 48421bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 48431bd6825cSml 48441bd6825cSml err = nxge_param_set_ip_opt(nxgep, NULL, 48451bd6825cSml NULL, (char *)pr_val, 48461bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv6_udp]); 48471bd6825cSml 48481bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 48491bd6825cSml "<== nxge_set_priv_prop: name %s (value 0x%x)", 48501bd6825cSml pr_name, result)); 48511bd6825cSml 48521bd6825cSml return (err); 48531bd6825cSml } 48541bd6825cSml if (strcmp(pr_name, "_class_opt_ipv6_ah") == 0) { 48551bd6825cSml if (pr_val == NULL) { 48561bd6825cSml err = EINVAL; 48571bd6825cSml return (err); 48581bd6825cSml } 48591bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 48601bd6825cSml 48611bd6825cSml err = nxge_param_set_ip_opt(nxgep, NULL, 48621bd6825cSml NULL, (char *)pr_val, 48631bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv6_ah]); 48641bd6825cSml 48651bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 48661bd6825cSml "<== nxge_set_priv_prop: name %s (value 0x%x)", 48671bd6825cSml pr_name, result)); 48681bd6825cSml 48691bd6825cSml return (err); 48701bd6825cSml } 48711bd6825cSml if (strcmp(pr_name, "_class_opt_ipv6_sctp") == 0) { 48721bd6825cSml if (pr_val == NULL) { 48731bd6825cSml err = EINVAL; 48741bd6825cSml return (err); 48751bd6825cSml } 48761bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 48771bd6825cSml 48781bd6825cSml err = nxge_param_set_ip_opt(nxgep, NULL, 48791bd6825cSml NULL, (char *)pr_val, 48801bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv6_sctp]); 48811bd6825cSml 48821bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 48831bd6825cSml "<== nxge_set_priv_prop: name %s (value 0x%x)", 48841bd6825cSml pr_name, result)); 48851bd6825cSml 48861bd6825cSml return (err); 48871bd6825cSml } 48881bd6825cSml 48891bd6825cSml if (strcmp(pr_name, "_soft_lso_enable") == 0) { 48901bd6825cSml if (pr_val == NULL) { 48911bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 48921bd6825cSml "==> nxge_set_priv_prop: name %s (null)", pr_name)); 48931bd6825cSml err = EINVAL; 48941bd6825cSml return (err); 48951bd6825cSml } 48961bd6825cSml 48971bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 48981bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 48991bd6825cSml "<== nxge_set_priv_prop: name %s " 49001bd6825cSml "(lso %d pr_val %s value %d)", 49011bd6825cSml pr_name, nxgep->soft_lso_enable, pr_val, result)); 49021bd6825cSml 49031bd6825cSml if (result > 1 || result < 0) { 49041bd6825cSml err = EINVAL; 49051bd6825cSml } else { 49061bd6825cSml if (nxgep->soft_lso_enable == (uint32_t)result) { 49071bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 49081bd6825cSml "no change (%d %d)", 49091bd6825cSml nxgep->soft_lso_enable, result)); 49101bd6825cSml return (0); 49111bd6825cSml } 49121bd6825cSml } 49131bd6825cSml 49141bd6825cSml nxgep->soft_lso_enable = (int)result; 49151bd6825cSml 49161bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 49171bd6825cSml "<== nxge_set_priv_prop: name %s (value %d)", 49181bd6825cSml pr_name, result)); 49191bd6825cSml 49201bd6825cSml return (err); 49211bd6825cSml } 492200161856Syc /* 492300161856Syc * Commands like "ndd -set /dev/nxge0 adv_10gfdx_cap 1" cause the 492400161856Syc * following code to be executed. 492500161856Syc */ 49264045d941Ssowmini if (strcmp(pr_name, "_adv_10gfdx_cap") == 0) { 49274045d941Ssowmini err = nxge_param_set_mac(nxgep, NULL, NULL, (char *)pr_val, 49284045d941Ssowmini (caddr_t)¶m_arr[param_anar_10gfdx]); 49294045d941Ssowmini return (err); 49304045d941Ssowmini } 49314045d941Ssowmini if (strcmp(pr_name, "_adv_pause_cap") == 0) { 49324045d941Ssowmini err = nxge_param_set_mac(nxgep, NULL, NULL, (char *)pr_val, 49334045d941Ssowmini (caddr_t)¶m_arr[param_anar_pause]); 49344045d941Ssowmini return (err); 49354045d941Ssowmini } 49361bd6825cSml 49371bd6825cSml return (EINVAL); 49381bd6825cSml } 49391bd6825cSml 49401bd6825cSml static int 49414045d941Ssowmini nxge_get_priv_prop(p_nxge_t nxgep, const char *pr_name, uint_t pr_flags, 4942afdda45fSVasumathi Sundaram - Sun Microsystems uint_t pr_valsize, void *pr_val, uint_t *perm) 49431bd6825cSml { 49441bd6825cSml p_nxge_param_t param_arr = nxgep->param_arr; 49451bd6825cSml char valstr[MAXNAMELEN]; 49461bd6825cSml int err = EINVAL; 49471bd6825cSml uint_t strsize; 49483fd94f8cSam boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 49491bd6825cSml 49501bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 49511bd6825cSml "==> nxge_get_priv_prop: property %s", pr_name)); 49521bd6825cSml 49531bd6825cSml /* function number */ 49541bd6825cSml if (strcmp(pr_name, "_function_number") == 0) { 49554045d941Ssowmini if (is_default) 49564045d941Ssowmini return (ENOTSUP); 4957afdda45fSVasumathi Sundaram - Sun Microsystems *perm = MAC_PROP_PERM_READ; 49584045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%d", 49594045d941Ssowmini nxgep->function_num); 49601bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 49611bd6825cSml "==> nxge_get_priv_prop: name %s " 49621bd6825cSml "(value %d valstr %s)", 49631bd6825cSml pr_name, nxgep->function_num, valstr)); 49641bd6825cSml 49651bd6825cSml err = 0; 49661bd6825cSml goto done; 49671bd6825cSml } 49681bd6825cSml 49691bd6825cSml /* Neptune firmware version */ 49701bd6825cSml if (strcmp(pr_name, "_fw_version") == 0) { 49714045d941Ssowmini if (is_default) 49724045d941Ssowmini return (ENOTSUP); 4973afdda45fSVasumathi Sundaram - Sun Microsystems *perm = MAC_PROP_PERM_READ; 49744045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%s", 49754045d941Ssowmini nxgep->vpd_info.ver); 49761bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 49771bd6825cSml "==> nxge_get_priv_prop: name %s " 49781bd6825cSml "(value %d valstr %s)", 49791bd6825cSml pr_name, nxgep->vpd_info.ver, valstr)); 49801bd6825cSml 49811bd6825cSml err = 0; 49821bd6825cSml goto done; 49831bd6825cSml } 49841bd6825cSml 49851bd6825cSml /* port PHY mode */ 49861bd6825cSml if (strcmp(pr_name, "_port_mode") == 0) { 49874045d941Ssowmini if (is_default) 49884045d941Ssowmini return (ENOTSUP); 4989afdda45fSVasumathi Sundaram - Sun Microsystems *perm = MAC_PROP_PERM_READ; 49901bd6825cSml switch (nxgep->mac.portmode) { 49911bd6825cSml case PORT_1G_COPPER: 49924045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "1G copper %s", 49931bd6825cSml nxgep->hot_swappable_phy ? 49941bd6825cSml "[Hot Swappable]" : ""); 49951bd6825cSml break; 49961bd6825cSml case PORT_1G_FIBER: 49974045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "1G fiber %s", 49981bd6825cSml nxgep->hot_swappable_phy ? 49991bd6825cSml "[hot swappable]" : ""); 50001bd6825cSml break; 50011bd6825cSml case PORT_10G_COPPER: 50024045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), 50034045d941Ssowmini "10G copper %s", 50041bd6825cSml nxgep->hot_swappable_phy ? 50051bd6825cSml "[hot swappable]" : ""); 50061bd6825cSml break; 50071bd6825cSml case PORT_10G_FIBER: 50084045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "10G fiber %s", 50091bd6825cSml nxgep->hot_swappable_phy ? 50101bd6825cSml "[hot swappable]" : ""); 50111bd6825cSml break; 50121bd6825cSml case PORT_10G_SERDES: 50134045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), 50144045d941Ssowmini "10G serdes %s", nxgep->hot_swappable_phy ? 50151bd6825cSml "[hot swappable]" : ""); 50161bd6825cSml break; 50171bd6825cSml case PORT_1G_SERDES: 50184045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "1G serdes %s", 50191bd6825cSml nxgep->hot_swappable_phy ? 50201bd6825cSml "[hot swappable]" : ""); 50211bd6825cSml break; 502200161856Syc case PORT_1G_TN1010: 502300161856Syc (void) snprintf(valstr, sizeof (valstr), 502400161856Syc "1G TN1010 copper %s", nxgep->hot_swappable_phy ? 502500161856Syc "[hot swappable]" : ""); 502600161856Syc break; 502700161856Syc case PORT_10G_TN1010: 502800161856Syc (void) snprintf(valstr, sizeof (valstr), 502900161856Syc "10G TN1010 copper %s", nxgep->hot_swappable_phy ? 503000161856Syc "[hot swappable]" : ""); 503100161856Syc break; 50321bd6825cSml case PORT_1G_RGMII_FIBER: 50334045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), 50344045d941Ssowmini "1G rgmii fiber %s", nxgep->hot_swappable_phy ? 50351bd6825cSml "[hot swappable]" : ""); 50361bd6825cSml break; 50371bd6825cSml case PORT_HSP_MODE: 50384045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), 5039c2d37b8bSml "phy not present[hot swappable]"); 50401bd6825cSml break; 50411bd6825cSml default: 50424045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "unknown %s", 50431bd6825cSml nxgep->hot_swappable_phy ? 50441bd6825cSml "[hot swappable]" : ""); 50451bd6825cSml break; 50461bd6825cSml } 50471bd6825cSml 50481bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 50491bd6825cSml "==> nxge_get_priv_prop: name %s (value %s)", 50501bd6825cSml pr_name, valstr)); 50511bd6825cSml 50521bd6825cSml err = 0; 50531bd6825cSml goto done; 50541bd6825cSml } 50551bd6825cSml 50561bd6825cSml /* Hot swappable PHY */ 50571bd6825cSml if (strcmp(pr_name, "_hot_swap_phy") == 0) { 50584045d941Ssowmini if (is_default) 50594045d941Ssowmini return (ENOTSUP); 5060afdda45fSVasumathi Sundaram - Sun Microsystems *perm = MAC_PROP_PERM_READ; 50614045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%s", 50621bd6825cSml nxgep->hot_swappable_phy ? 50631bd6825cSml "yes" : "no"); 50641bd6825cSml 50651bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 50661bd6825cSml "==> nxge_get_priv_prop: name %s " 50671bd6825cSml "(value %d valstr %s)", 50681bd6825cSml pr_name, nxgep->hot_swappable_phy, valstr)); 50691bd6825cSml 50701bd6825cSml err = 0; 50711bd6825cSml goto done; 50721bd6825cSml } 50731bd6825cSml 50741bd6825cSml 50751bd6825cSml /* accept jumbo */ 50761bd6825cSml if (strcmp(pr_name, "_accept_jumbo") == 0) { 50774045d941Ssowmini if (is_default) 50784045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%d", 0); 50794045d941Ssowmini else 50804045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), 50814045d941Ssowmini "%d", nxgep->mac.is_jumbo); 50821bd6825cSml err = 0; 50831bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 50841bd6825cSml "==> nxge_get_priv_prop: name %s (value %d (%d, %d))", 50851bd6825cSml pr_name, 50861bd6825cSml (uint32_t)param_arr[param_accept_jumbo].value, 50871bd6825cSml nxgep->mac.is_jumbo, 50881bd6825cSml nxge_jumbo_enable)); 50891bd6825cSml 50901bd6825cSml goto done; 50911bd6825cSml } 50921bd6825cSml 50931bd6825cSml /* Receive Interrupt Blanking Parameters */ 50941bd6825cSml if (strcmp(pr_name, "_rxdma_intr_time") == 0) { 50954045d941Ssowmini err = 0; 50964045d941Ssowmini if (is_default) { 50974045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), 50984045d941Ssowmini "%d", RXDMA_RCR_TO_DEFAULT); 50994045d941Ssowmini goto done; 51004045d941Ssowmini } 51014045d941Ssowmini 51024045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%d", 51034045d941Ssowmini nxgep->intr_timeout); 51041bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 51051bd6825cSml "==> nxge_get_priv_prop: name %s (value %d)", 51061bd6825cSml pr_name, 51071bd6825cSml (uint32_t)nxgep->intr_timeout)); 51081bd6825cSml goto done; 51091bd6825cSml } 51101bd6825cSml 51111bd6825cSml if (strcmp(pr_name, "_rxdma_intr_pkts") == 0) { 51124045d941Ssowmini err = 0; 51134045d941Ssowmini if (is_default) { 51144045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), 51154045d941Ssowmini "%d", RXDMA_RCR_PTHRES_DEFAULT); 51164045d941Ssowmini goto done; 51174045d941Ssowmini } 51184045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%d", 51194045d941Ssowmini nxgep->intr_threshold); 51201bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 51211bd6825cSml "==> nxge_get_priv_prop: name %s (value %d)", 51221bd6825cSml pr_name, (uint32_t)nxgep->intr_threshold)); 51231bd6825cSml 51241bd6825cSml goto done; 51251bd6825cSml } 51261bd6825cSml 51271bd6825cSml /* Classification and Load Distribution Configuration */ 51281bd6825cSml if (strcmp(pr_name, "_class_opt_ipv4_tcp") == 0) { 51294045d941Ssowmini if (is_default) { 51304045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 51314045d941Ssowmini NXGE_CLASS_FLOW_GEN_SERVER); 51324045d941Ssowmini err = 0; 51334045d941Ssowmini goto done; 51344045d941Ssowmini } 51351bd6825cSml err = nxge_dld_get_ip_opt(nxgep, 51361bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv4_tcp]); 51371bd6825cSml 51384045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 51391bd6825cSml (int)param_arr[param_class_opt_ipv4_tcp].value); 51401bd6825cSml 51411bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 51421bd6825cSml "==> nxge_get_priv_prop: %s", valstr)); 51431bd6825cSml goto done; 51441bd6825cSml } 51451bd6825cSml 51461bd6825cSml if (strcmp(pr_name, "_class_opt_ipv4_udp") == 0) { 51474045d941Ssowmini if (is_default) { 51484045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 51494045d941Ssowmini NXGE_CLASS_FLOW_GEN_SERVER); 51504045d941Ssowmini err = 0; 51514045d941Ssowmini goto done; 51524045d941Ssowmini } 51531bd6825cSml err = nxge_dld_get_ip_opt(nxgep, 51541bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv4_udp]); 51551bd6825cSml 51564045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 51571bd6825cSml (int)param_arr[param_class_opt_ipv4_udp].value); 51581bd6825cSml 51591bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 51601bd6825cSml "==> nxge_get_priv_prop: %s", valstr)); 51611bd6825cSml goto done; 51621bd6825cSml } 51631bd6825cSml if (strcmp(pr_name, "_class_opt_ipv4_ah") == 0) { 51644045d941Ssowmini if (is_default) { 51654045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 51664045d941Ssowmini NXGE_CLASS_FLOW_GEN_SERVER); 51674045d941Ssowmini err = 0; 51684045d941Ssowmini goto done; 51694045d941Ssowmini } 51701bd6825cSml err = nxge_dld_get_ip_opt(nxgep, 51711bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv4_ah]); 51721bd6825cSml 51734045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 51741bd6825cSml (int)param_arr[param_class_opt_ipv4_ah].value); 51751bd6825cSml 51761bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 51771bd6825cSml "==> nxge_get_priv_prop: %s", valstr)); 51781bd6825cSml goto done; 51791bd6825cSml } 51801bd6825cSml 51811bd6825cSml if (strcmp(pr_name, "_class_opt_ipv4_sctp") == 0) { 51824045d941Ssowmini if (is_default) { 51834045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 51844045d941Ssowmini NXGE_CLASS_FLOW_GEN_SERVER); 51854045d941Ssowmini err = 0; 51864045d941Ssowmini goto done; 51874045d941Ssowmini } 51881bd6825cSml err = nxge_dld_get_ip_opt(nxgep, 51891bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv4_sctp]); 51901bd6825cSml 51914045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 51921bd6825cSml (int)param_arr[param_class_opt_ipv4_sctp].value); 51931bd6825cSml 51941bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 51951bd6825cSml "==> nxge_get_priv_prop: %s", valstr)); 51961bd6825cSml goto done; 51971bd6825cSml } 51981bd6825cSml 51991bd6825cSml if (strcmp(pr_name, "_class_opt_ipv6_tcp") == 0) { 52004045d941Ssowmini if (is_default) { 52014045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 52024045d941Ssowmini NXGE_CLASS_FLOW_GEN_SERVER); 52034045d941Ssowmini err = 0; 52044045d941Ssowmini goto done; 52054045d941Ssowmini } 52061bd6825cSml err = nxge_dld_get_ip_opt(nxgep, 52071bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv6_tcp]); 52081bd6825cSml 52094045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 52101bd6825cSml (int)param_arr[param_class_opt_ipv6_tcp].value); 52111bd6825cSml 52121bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 52131bd6825cSml "==> nxge_get_priv_prop: %s", valstr)); 52141bd6825cSml goto done; 52151bd6825cSml } 52161bd6825cSml 52171bd6825cSml if (strcmp(pr_name, "_class_opt_ipv6_udp") == 0) { 52184045d941Ssowmini if (is_default) { 52194045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 52204045d941Ssowmini NXGE_CLASS_FLOW_GEN_SERVER); 52214045d941Ssowmini err = 0; 52224045d941Ssowmini goto done; 52234045d941Ssowmini } 52241bd6825cSml err = nxge_dld_get_ip_opt(nxgep, 52251bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv6_udp]); 52261bd6825cSml 52274045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 52281bd6825cSml (int)param_arr[param_class_opt_ipv6_udp].value); 52291bd6825cSml 52301bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 52311bd6825cSml "==> nxge_get_priv_prop: %s", valstr)); 52321bd6825cSml goto done; 52331bd6825cSml } 52341bd6825cSml 52351bd6825cSml if (strcmp(pr_name, "_class_opt_ipv6_ah") == 0) { 52364045d941Ssowmini if (is_default) { 52374045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 52384045d941Ssowmini NXGE_CLASS_FLOW_GEN_SERVER); 52394045d941Ssowmini err = 0; 52404045d941Ssowmini goto done; 52414045d941Ssowmini } 52421bd6825cSml err = nxge_dld_get_ip_opt(nxgep, 52431bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv6_ah]); 52441bd6825cSml 52454045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 52461bd6825cSml (int)param_arr[param_class_opt_ipv6_ah].value); 52471bd6825cSml 52481bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 52491bd6825cSml "==> nxge_get_priv_prop: %s", valstr)); 52501bd6825cSml goto done; 52511bd6825cSml } 52521bd6825cSml 52531bd6825cSml if (strcmp(pr_name, "_class_opt_ipv6_sctp") == 0) { 52544045d941Ssowmini if (is_default) { 52554045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 52564045d941Ssowmini NXGE_CLASS_FLOW_GEN_SERVER); 52574045d941Ssowmini err = 0; 52584045d941Ssowmini goto done; 52594045d941Ssowmini } 52601bd6825cSml err = nxge_dld_get_ip_opt(nxgep, 52611bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv6_sctp]); 52621bd6825cSml 52634045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 52641bd6825cSml (int)param_arr[param_class_opt_ipv6_sctp].value); 52651bd6825cSml 52661bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 52671bd6825cSml "==> nxge_get_priv_prop: %s", valstr)); 52681bd6825cSml goto done; 52691bd6825cSml } 52701bd6825cSml 52711bd6825cSml /* Software LSO */ 52721bd6825cSml if (strcmp(pr_name, "_soft_lso_enable") == 0) { 52734045d941Ssowmini if (is_default) { 52744045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%d", 0); 52754045d941Ssowmini err = 0; 52764045d941Ssowmini goto done; 52774045d941Ssowmini } 52784045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), 52794045d941Ssowmini "%d", nxgep->soft_lso_enable); 52801bd6825cSml err = 0; 52811bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 52821bd6825cSml "==> nxge_get_priv_prop: name %s (value %d)", 52831bd6825cSml pr_name, nxgep->soft_lso_enable)); 52841bd6825cSml 52851bd6825cSml goto done; 52861bd6825cSml } 52874045d941Ssowmini if (strcmp(pr_name, "_adv_10gfdx_cap") == 0) { 52884045d941Ssowmini err = 0; 52894045d941Ssowmini if (is_default || 52904045d941Ssowmini nxgep->param_arr[param_anar_10gfdx].value != 0) { 52914045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%d", 1); 52924045d941Ssowmini goto done; 52934045d941Ssowmini } else { 52944045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%d", 0); 52954045d941Ssowmini goto done; 52964045d941Ssowmini } 52974045d941Ssowmini } 52984045d941Ssowmini if (strcmp(pr_name, "_adv_pause_cap") == 0) { 52994045d941Ssowmini err = 0; 53004045d941Ssowmini if (is_default || 53014045d941Ssowmini nxgep->param_arr[param_anar_pause].value != 0) { 53024045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%d", 1); 53034045d941Ssowmini goto done; 53044045d941Ssowmini } else { 53054045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%d", 0); 53064045d941Ssowmini goto done; 53074045d941Ssowmini } 53084045d941Ssowmini } 53091bd6825cSml 53101bd6825cSml done: 53111bd6825cSml if (err == 0) { 53121bd6825cSml strsize = (uint_t)strlen(valstr); 53131bd6825cSml if (pr_valsize < strsize) { 53141bd6825cSml err = ENOBUFS; 53151bd6825cSml } else { 53161bd6825cSml (void) strlcpy(pr_val, valstr, pr_valsize); 53171bd6825cSml } 53181bd6825cSml } 53191bd6825cSml 53201bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 53211bd6825cSml "<== nxge_get_priv_prop: return %d", err)); 53221bd6825cSml return (err); 53231bd6825cSml } 53241bd6825cSml 532544961713Sgirish /* 532644961713Sgirish * Module loading and removing entry points. 532744961713Sgirish */ 532844961713Sgirish 53296f157acbSml DDI_DEFINE_STREAM_OPS(nxge_dev_ops, nulldev, nulldev, nxge_attach, nxge_detach, 533019397407SSherry Moore nodev, NULL, D_MP, NULL, nxge_quiesce); 533144961713Sgirish 53322e59129aSraghus #define NXGE_DESC_VER "Sun NIU 10Gb Ethernet" 533344961713Sgirish 533444961713Sgirish /* 533544961713Sgirish * Module linkage information for the kernel. 533644961713Sgirish */ 533744961713Sgirish static struct modldrv nxge_modldrv = { 533844961713Sgirish &mod_driverops, 533944961713Sgirish NXGE_DESC_VER, 534044961713Sgirish &nxge_dev_ops 534144961713Sgirish }; 534244961713Sgirish 534344961713Sgirish static struct modlinkage modlinkage = { 534444961713Sgirish MODREV_1, (void *) &nxge_modldrv, NULL 534544961713Sgirish }; 534644961713Sgirish 534744961713Sgirish int 534844961713Sgirish _init(void) 534944961713Sgirish { 535044961713Sgirish int status; 535144961713Sgirish 535244961713Sgirish NXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _init")); 535344961713Sgirish mac_init_ops(&nxge_dev_ops, "nxge"); 535444961713Sgirish status = ddi_soft_state_init(&nxge_list, sizeof (nxge_t), 0); 535544961713Sgirish if (status != 0) { 535644961713Sgirish NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 53574045d941Ssowmini "failed to init device soft state")); 535844961713Sgirish goto _init_exit; 535944961713Sgirish } 536044961713Sgirish status = mod_install(&modlinkage); 536144961713Sgirish if (status != 0) { 536244961713Sgirish ddi_soft_state_fini(&nxge_list); 536344961713Sgirish NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, "Mod install failed")); 536444961713Sgirish goto _init_exit; 536544961713Sgirish } 536644961713Sgirish 536744961713Sgirish MUTEX_INIT(&nxge_common_lock, NULL, MUTEX_DRIVER, NULL); 536844961713Sgirish 536944961713Sgirish _init_exit: 537044961713Sgirish NXGE_DEBUG_MSG((NULL, MOD_CTL, "_init status = 0x%X", status)); 537144961713Sgirish 537244961713Sgirish return (status); 537344961713Sgirish } 537444961713Sgirish 537544961713Sgirish int 537644961713Sgirish _fini(void) 537744961713Sgirish { 537844961713Sgirish int status; 537944961713Sgirish 538044961713Sgirish NXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _fini")); 538144961713Sgirish 538244961713Sgirish NXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _fini: mod_remove")); 5383a3c5bd6dSspeer 5384a3c5bd6dSspeer if (nxge_mblks_pending) 5385a3c5bd6dSspeer return (EBUSY); 5386a3c5bd6dSspeer 538744961713Sgirish status = mod_remove(&modlinkage); 538844961713Sgirish if (status != DDI_SUCCESS) { 538944961713Sgirish NXGE_DEBUG_MSG((NULL, MOD_CTL, 53904045d941Ssowmini "Module removal failed 0x%08x", 53914045d941Ssowmini status)); 539244961713Sgirish goto _fini_exit; 539344961713Sgirish } 539444961713Sgirish 539544961713Sgirish mac_fini_ops(&nxge_dev_ops); 539644961713Sgirish 539744961713Sgirish ddi_soft_state_fini(&nxge_list); 539844961713Sgirish 539944961713Sgirish MUTEX_DESTROY(&nxge_common_lock); 540044961713Sgirish _fini_exit: 540144961713Sgirish NXGE_DEBUG_MSG((NULL, MOD_CTL, "_fini status = 0x%08x", status)); 540244961713Sgirish 540344961713Sgirish return (status); 540444961713Sgirish } 540544961713Sgirish 540644961713Sgirish int 540744961713Sgirish _info(struct modinfo *modinfop) 540844961713Sgirish { 540944961713Sgirish int status; 541044961713Sgirish 541144961713Sgirish NXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _info")); 541244961713Sgirish status = mod_info(&modlinkage, modinfop); 541344961713Sgirish NXGE_DEBUG_MSG((NULL, MOD_CTL, " _info status = 0x%X", status)); 541444961713Sgirish 541544961713Sgirish return (status); 541644961713Sgirish } 541744961713Sgirish 5418da14cebeSEric Cheng /*ARGSUSED*/ 5419da14cebeSEric Cheng static int 5420da14cebeSEric Cheng nxge_tx_ring_start(mac_ring_driver_t rdriver, uint64_t mr_gen_num) 5421da14cebeSEric Cheng { 5422da14cebeSEric Cheng p_nxge_ring_handle_t rhp = (p_nxge_ring_handle_t)rdriver; 5423da14cebeSEric Cheng p_nxge_t nxgep = rhp->nxgep; 5424da14cebeSEric Cheng uint32_t channel; 5425da14cebeSEric Cheng p_tx_ring_t ring; 5426da14cebeSEric Cheng 5427da14cebeSEric Cheng channel = nxgep->pt_config.hw_config.tdc.start + rhp->index; 5428da14cebeSEric Cheng ring = nxgep->tx_rings->rings[channel]; 5429da14cebeSEric Cheng 5430da14cebeSEric Cheng MUTEX_ENTER(&ring->lock); 5431da14cebeSEric Cheng ring->tx_ring_handle = rhp->ring_handle; 5432da14cebeSEric Cheng MUTEX_EXIT(&ring->lock); 5433da14cebeSEric Cheng 5434da14cebeSEric Cheng return (0); 5435da14cebeSEric Cheng } 5436da14cebeSEric Cheng 5437da14cebeSEric Cheng static void 5438da14cebeSEric Cheng nxge_tx_ring_stop(mac_ring_driver_t rdriver) 5439da14cebeSEric Cheng { 5440da14cebeSEric Cheng p_nxge_ring_handle_t rhp = (p_nxge_ring_handle_t)rdriver; 5441da14cebeSEric Cheng p_nxge_t nxgep = rhp->nxgep; 5442da14cebeSEric Cheng uint32_t channel; 5443da14cebeSEric Cheng p_tx_ring_t ring; 5444da14cebeSEric Cheng 5445da14cebeSEric Cheng channel = nxgep->pt_config.hw_config.tdc.start + rhp->index; 5446da14cebeSEric Cheng ring = nxgep->tx_rings->rings[channel]; 5447da14cebeSEric Cheng 5448da14cebeSEric Cheng MUTEX_ENTER(&ring->lock); 5449da14cebeSEric Cheng ring->tx_ring_handle = (mac_ring_handle_t)NULL; 5450da14cebeSEric Cheng MUTEX_EXIT(&ring->lock); 5451da14cebeSEric Cheng } 5452da14cebeSEric Cheng 5453da14cebeSEric Cheng static int 5454da14cebeSEric Cheng nxge_rx_ring_start(mac_ring_driver_t rdriver, uint64_t mr_gen_num) 5455da14cebeSEric Cheng { 5456da14cebeSEric Cheng p_nxge_ring_handle_t rhp = (p_nxge_ring_handle_t)rdriver; 5457da14cebeSEric Cheng p_nxge_t nxgep = rhp->nxgep; 5458da14cebeSEric Cheng uint32_t channel; 5459da14cebeSEric Cheng p_rx_rcr_ring_t ring; 5460da14cebeSEric Cheng int i; 5461da14cebeSEric Cheng 5462da14cebeSEric Cheng channel = nxgep->pt_config.hw_config.start_rdc + rhp->index; 5463da14cebeSEric Cheng ring = nxgep->rx_rcr_rings->rcr_rings[channel]; 5464da14cebeSEric Cheng 5465da14cebeSEric Cheng MUTEX_ENTER(&ring->lock); 5466da14cebeSEric Cheng 5467da14cebeSEric Cheng if (nxgep->rx_channel_started[channel] == B_TRUE) { 5468da14cebeSEric Cheng MUTEX_EXIT(&ring->lock); 5469da14cebeSEric Cheng return (0); 5470da14cebeSEric Cheng } 5471da14cebeSEric Cheng 5472da14cebeSEric Cheng /* set rcr_ring */ 5473da14cebeSEric Cheng for (i = 0; i < nxgep->ldgvp->maxldvs; i++) { 5474da14cebeSEric Cheng if ((nxgep->ldgvp->ldvp[i].is_rxdma == 1) && 5475da14cebeSEric Cheng (nxgep->ldgvp->ldvp[i].channel == channel)) { 5476da14cebeSEric Cheng ring->ldvp = &nxgep->ldgvp->ldvp[i]; 5477da14cebeSEric Cheng ring->ldgp = nxgep->ldgvp->ldvp[i].ldgp; 5478da14cebeSEric Cheng } 5479da14cebeSEric Cheng } 5480da14cebeSEric Cheng 5481da14cebeSEric Cheng nxgep->rx_channel_started[channel] = B_TRUE; 5482da14cebeSEric Cheng ring->rcr_mac_handle = rhp->ring_handle; 5483da14cebeSEric Cheng ring->rcr_gen_num = mr_gen_num; 5484da14cebeSEric Cheng MUTEX_EXIT(&ring->lock); 5485da14cebeSEric Cheng 5486da14cebeSEric Cheng return (0); 5487da14cebeSEric Cheng } 5488da14cebeSEric Cheng 5489da14cebeSEric Cheng static void 5490da14cebeSEric Cheng nxge_rx_ring_stop(mac_ring_driver_t rdriver) 5491da14cebeSEric Cheng { 5492da14cebeSEric Cheng p_nxge_ring_handle_t rhp = (p_nxge_ring_handle_t)rdriver; 5493da14cebeSEric Cheng p_nxge_t nxgep = rhp->nxgep; 5494da14cebeSEric Cheng uint32_t channel; 5495da14cebeSEric Cheng p_rx_rcr_ring_t ring; 5496da14cebeSEric Cheng 5497da14cebeSEric Cheng channel = nxgep->pt_config.hw_config.start_rdc + rhp->index; 5498da14cebeSEric Cheng ring = nxgep->rx_rcr_rings->rcr_rings[channel]; 5499da14cebeSEric Cheng 5500da14cebeSEric Cheng MUTEX_ENTER(&ring->lock); 5501da14cebeSEric Cheng nxgep->rx_channel_started[channel] = B_FALSE; 5502da14cebeSEric Cheng ring->rcr_mac_handle = NULL; 5503da14cebeSEric Cheng MUTEX_EXIT(&ring->lock); 5504da14cebeSEric Cheng } 5505da14cebeSEric Cheng 5506da14cebeSEric Cheng /* 5507da14cebeSEric Cheng * Callback funtion for MAC layer to register all rings. 5508da14cebeSEric Cheng */ 5509da14cebeSEric Cheng static void 5510da14cebeSEric Cheng nxge_fill_ring(void *arg, mac_ring_type_t rtype, const int rg_index, 5511da14cebeSEric Cheng const int index, mac_ring_info_t *infop, mac_ring_handle_t rh) 5512da14cebeSEric Cheng { 5513da14cebeSEric Cheng p_nxge_t nxgep = (p_nxge_t)arg; 5514da14cebeSEric Cheng p_nxge_hw_pt_cfg_t p_cfgp = &nxgep->pt_config.hw_config; 5515da14cebeSEric Cheng 5516da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, TX_CTL, 5517da14cebeSEric Cheng "==> nxge_fill_ring 0x%x index %d", rtype, index)); 5518da14cebeSEric Cheng 5519da14cebeSEric Cheng switch (rtype) { 5520da14cebeSEric Cheng case MAC_RING_TYPE_TX: { 5521da14cebeSEric Cheng p_nxge_ring_handle_t rhandlep; 5522da14cebeSEric Cheng 5523da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, TX_CTL, 5524da14cebeSEric Cheng "==> nxge_fill_ring (TX) 0x%x index %d ntdcs %d", 5525da14cebeSEric Cheng rtype, index, p_cfgp->tdc.count)); 5526da14cebeSEric Cheng 5527da14cebeSEric Cheng ASSERT((index >= 0) && (index < p_cfgp->tdc.count)); 5528da14cebeSEric Cheng rhandlep = &nxgep->tx_ring_handles[index]; 5529da14cebeSEric Cheng rhandlep->nxgep = nxgep; 5530da14cebeSEric Cheng rhandlep->index = index; 5531da14cebeSEric Cheng rhandlep->ring_handle = rh; 5532da14cebeSEric Cheng 5533da14cebeSEric Cheng infop->mri_driver = (mac_ring_driver_t)rhandlep; 5534da14cebeSEric Cheng infop->mri_start = nxge_tx_ring_start; 5535da14cebeSEric Cheng infop->mri_stop = nxge_tx_ring_stop; 5536da14cebeSEric Cheng infop->mri_tx = nxge_tx_ring_send; 5537da14cebeSEric Cheng 5538da14cebeSEric Cheng break; 5539da14cebeSEric Cheng } 5540da14cebeSEric Cheng case MAC_RING_TYPE_RX: { 5541da14cebeSEric Cheng p_nxge_ring_handle_t rhandlep; 5542da14cebeSEric Cheng int nxge_rindex; 5543da14cebeSEric Cheng mac_intr_t nxge_mac_intr; 5544da14cebeSEric Cheng 5545da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, RX_CTL, 5546da14cebeSEric Cheng "==> nxge_fill_ring (RX) 0x%x index %d nrdcs %d", 5547da14cebeSEric Cheng rtype, index, p_cfgp->max_rdcs)); 5548da14cebeSEric Cheng 5549da14cebeSEric Cheng /* 5550da14cebeSEric Cheng * 'index' is the ring index within the group. 5551da14cebeSEric Cheng * Find the ring index in the nxge instance. 5552da14cebeSEric Cheng */ 5553da14cebeSEric Cheng nxge_rindex = nxge_get_rxring_index(nxgep, rg_index, index); 5554da14cebeSEric Cheng 5555da14cebeSEric Cheng ASSERT((nxge_rindex >= 0) && (nxge_rindex < p_cfgp->max_rdcs)); 5556da14cebeSEric Cheng rhandlep = &nxgep->rx_ring_handles[nxge_rindex]; 5557da14cebeSEric Cheng rhandlep->nxgep = nxgep; 5558da14cebeSEric Cheng rhandlep->index = nxge_rindex; 5559da14cebeSEric Cheng rhandlep->ring_handle = rh; 5560da14cebeSEric Cheng 5561da14cebeSEric Cheng /* 5562da14cebeSEric Cheng * Entrypoint to enable interrupt (disable poll) and 5563da14cebeSEric Cheng * disable interrupt (enable poll). 5564da14cebeSEric Cheng */ 5565da14cebeSEric Cheng nxge_mac_intr.mi_handle = (mac_intr_handle_t)rhandlep; 5566da14cebeSEric Cheng nxge_mac_intr.mi_enable = (mac_intr_enable_t)nxge_disable_poll; 5567da14cebeSEric Cheng nxge_mac_intr.mi_disable = (mac_intr_disable_t)nxge_enable_poll; 5568da14cebeSEric Cheng infop->mri_driver = (mac_ring_driver_t)rhandlep; 5569da14cebeSEric Cheng infop->mri_start = nxge_rx_ring_start; 5570da14cebeSEric Cheng infop->mri_stop = nxge_rx_ring_stop; 5571da14cebeSEric Cheng infop->mri_intr = nxge_mac_intr; /* ??? */ 5572da14cebeSEric Cheng infop->mri_poll = nxge_rx_poll; 5573da14cebeSEric Cheng 5574da14cebeSEric Cheng break; 5575da14cebeSEric Cheng } 5576da14cebeSEric Cheng default: 5577da14cebeSEric Cheng break; 5578da14cebeSEric Cheng } 5579da14cebeSEric Cheng 5580da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_fill_ring 0x%x", 5581da14cebeSEric Cheng rtype)); 5582da14cebeSEric Cheng } 5583da14cebeSEric Cheng 5584da14cebeSEric Cheng static void 5585da14cebeSEric Cheng nxge_group_add_ring(mac_group_driver_t gh, mac_ring_driver_t rh, 5586da14cebeSEric Cheng mac_ring_type_t type) 5587da14cebeSEric Cheng { 5588da14cebeSEric Cheng nxge_ring_group_t *rgroup = (nxge_ring_group_t *)gh; 5589da14cebeSEric Cheng nxge_ring_handle_t *rhandle = (nxge_ring_handle_t *)rh; 5590da14cebeSEric Cheng nxge_t *nxge; 5591da14cebeSEric Cheng nxge_grp_t *grp; 5592da14cebeSEric Cheng nxge_rdc_grp_t *rdc_grp; 5593da14cebeSEric Cheng uint16_t channel; /* device-wise ring id */ 5594da14cebeSEric Cheng int dev_gindex; 5595da14cebeSEric Cheng int rv; 5596da14cebeSEric Cheng 5597da14cebeSEric Cheng nxge = rgroup->nxgep; 5598da14cebeSEric Cheng 5599da14cebeSEric Cheng switch (type) { 5600da14cebeSEric Cheng case MAC_RING_TYPE_TX: 5601da14cebeSEric Cheng /* 5602da14cebeSEric Cheng * nxge_grp_dc_add takes a channel number which is a 5603da14cebeSEric Cheng * "devise" ring ID. 5604da14cebeSEric Cheng */ 5605da14cebeSEric Cheng channel = nxge->pt_config.hw_config.tdc.start + rhandle->index; 5606da14cebeSEric Cheng 5607da14cebeSEric Cheng /* 5608da14cebeSEric Cheng * Remove the ring from the default group 5609da14cebeSEric Cheng */ 5610da14cebeSEric Cheng if (rgroup->gindex != 0) { 5611da14cebeSEric Cheng (void) nxge_grp_dc_remove(nxge, VP_BOUND_TX, channel); 5612da14cebeSEric Cheng } 5613da14cebeSEric Cheng 5614da14cebeSEric Cheng /* 5615da14cebeSEric Cheng * nxge->tx_set.group[] is an array of groups indexed by 5616da14cebeSEric Cheng * a "port" group ID. 5617da14cebeSEric Cheng */ 5618da14cebeSEric Cheng grp = nxge->tx_set.group[rgroup->gindex]; 5619da14cebeSEric Cheng rv = nxge_grp_dc_add(nxge, grp, VP_BOUND_TX, channel); 5620da14cebeSEric Cheng if (rv != 0) { 5621da14cebeSEric Cheng NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, 5622da14cebeSEric Cheng "nxge_group_add_ring: nxge_grp_dc_add failed")); 5623da14cebeSEric Cheng } 5624da14cebeSEric Cheng break; 5625da14cebeSEric Cheng 5626da14cebeSEric Cheng case MAC_RING_TYPE_RX: 5627da14cebeSEric Cheng /* 5628da14cebeSEric Cheng * nxge->rx_set.group[] is an array of groups indexed by 5629da14cebeSEric Cheng * a "port" group ID. 5630da14cebeSEric Cheng */ 5631da14cebeSEric Cheng grp = nxge->rx_set.group[rgroup->gindex]; 5632da14cebeSEric Cheng 5633da14cebeSEric Cheng dev_gindex = nxge->pt_config.hw_config.def_mac_rxdma_grpid + 5634da14cebeSEric Cheng rgroup->gindex; 5635da14cebeSEric Cheng rdc_grp = &nxge->pt_config.rdc_grps[dev_gindex]; 5636da14cebeSEric Cheng 5637da14cebeSEric Cheng /* 5638da14cebeSEric Cheng * nxge_grp_dc_add takes a channel number which is a 5639da14cebeSEric Cheng * "devise" ring ID. 5640da14cebeSEric Cheng */ 5641da14cebeSEric Cheng channel = nxge->pt_config.hw_config.start_rdc + rhandle->index; 5642da14cebeSEric Cheng rv = nxge_grp_dc_add(nxge, grp, VP_BOUND_RX, channel); 5643da14cebeSEric Cheng if (rv != 0) { 5644da14cebeSEric Cheng NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, 5645da14cebeSEric Cheng "nxge_group_add_ring: nxge_grp_dc_add failed")); 5646da14cebeSEric Cheng } 5647da14cebeSEric Cheng 5648da14cebeSEric Cheng rdc_grp->map |= (1 << channel); 5649da14cebeSEric Cheng rdc_grp->max_rdcs++; 5650da14cebeSEric Cheng 5651da14cebeSEric Cheng (void) nxge_init_fzc_rdc_tbl(nxge, rgroup->rdctbl); 5652da14cebeSEric Cheng break; 5653da14cebeSEric Cheng } 5654da14cebeSEric Cheng } 5655da14cebeSEric Cheng 5656da14cebeSEric Cheng static void 5657da14cebeSEric Cheng nxge_group_rem_ring(mac_group_driver_t gh, mac_ring_driver_t rh, 5658da14cebeSEric Cheng mac_ring_type_t type) 5659da14cebeSEric Cheng { 5660da14cebeSEric Cheng nxge_ring_group_t *rgroup = (nxge_ring_group_t *)gh; 5661da14cebeSEric Cheng nxge_ring_handle_t *rhandle = (nxge_ring_handle_t *)rh; 5662da14cebeSEric Cheng nxge_t *nxge; 5663da14cebeSEric Cheng uint16_t channel; /* device-wise ring id */ 5664da14cebeSEric Cheng nxge_rdc_grp_t *rdc_grp; 5665da14cebeSEric Cheng int dev_gindex; 5666da14cebeSEric Cheng 5667da14cebeSEric Cheng nxge = rgroup->nxgep; 5668da14cebeSEric Cheng 5669da14cebeSEric Cheng switch (type) { 5670da14cebeSEric Cheng case MAC_RING_TYPE_TX: 5671da14cebeSEric Cheng dev_gindex = nxge->pt_config.hw_config.def_mac_txdma_grpid + 5672da14cebeSEric Cheng rgroup->gindex; 5673da14cebeSEric Cheng channel = nxge->pt_config.hw_config.tdc.start + rhandle->index; 5674da14cebeSEric Cheng nxge_grp_dc_remove(nxge, VP_BOUND_TX, channel); 5675da14cebeSEric Cheng 5676da14cebeSEric Cheng /* 5677da14cebeSEric Cheng * Add the ring back to the default group 5678da14cebeSEric Cheng */ 5679da14cebeSEric Cheng if (rgroup->gindex != 0) { 5680da14cebeSEric Cheng nxge_grp_t *grp; 5681da14cebeSEric Cheng grp = nxge->tx_set.group[0]; 5682da14cebeSEric Cheng (void) nxge_grp_dc_add(nxge, grp, VP_BOUND_TX, channel); 5683da14cebeSEric Cheng } 5684da14cebeSEric Cheng break; 5685da14cebeSEric Cheng 5686da14cebeSEric Cheng case MAC_RING_TYPE_RX: 5687da14cebeSEric Cheng dev_gindex = nxge->pt_config.hw_config.def_mac_rxdma_grpid + 5688da14cebeSEric Cheng rgroup->gindex; 5689da14cebeSEric Cheng rdc_grp = &nxge->pt_config.rdc_grps[dev_gindex]; 5690da14cebeSEric Cheng channel = rdc_grp->start_rdc + rhandle->index; 5691da14cebeSEric Cheng nxge_grp_dc_remove(nxge, VP_BOUND_RX, channel); 5692da14cebeSEric Cheng 5693da14cebeSEric Cheng rdc_grp->map &= ~(1 << channel); 5694da14cebeSEric Cheng rdc_grp->max_rdcs--; 5695da14cebeSEric Cheng 5696da14cebeSEric Cheng (void) nxge_init_fzc_rdc_tbl(nxge, rgroup->rdctbl); 5697da14cebeSEric Cheng break; 5698da14cebeSEric Cheng } 5699da14cebeSEric Cheng } 5700da14cebeSEric Cheng 5701da14cebeSEric Cheng 570244961713Sgirish /*ARGSUSED*/ 570344961713Sgirish static nxge_status_t 570444961713Sgirish nxge_add_intrs(p_nxge_t nxgep) 570544961713Sgirish { 570644961713Sgirish 570744961713Sgirish int intr_types; 570844961713Sgirish int type = 0; 570944961713Sgirish int ddi_status = DDI_SUCCESS; 571044961713Sgirish nxge_status_t status = NXGE_OK; 571144961713Sgirish 571244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs")); 571344961713Sgirish 571444961713Sgirish nxgep->nxge_intr_type.intr_registered = B_FALSE; 571544961713Sgirish nxgep->nxge_intr_type.intr_enabled = B_FALSE; 571644961713Sgirish nxgep->nxge_intr_type.msi_intx_cnt = 0; 571744961713Sgirish nxgep->nxge_intr_type.intr_added = 0; 571844961713Sgirish nxgep->nxge_intr_type.niu_msi_enable = B_FALSE; 571944961713Sgirish nxgep->nxge_intr_type.intr_type = 0; 572044961713Sgirish 572144961713Sgirish if (nxgep->niu_type == N2_NIU) { 572244961713Sgirish nxgep->nxge_intr_type.niu_msi_enable = B_TRUE; 572344961713Sgirish } else if (nxge_msi_enable) { 572444961713Sgirish nxgep->nxge_intr_type.niu_msi_enable = B_TRUE; 572544961713Sgirish } 572644961713Sgirish 572744961713Sgirish /* Get the supported interrupt types */ 572844961713Sgirish if ((ddi_status = ddi_intr_get_supported_types(nxgep->dip, &intr_types)) 57294045d941Ssowmini != DDI_SUCCESS) { 573044961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_add_intrs: " 57314045d941Ssowmini "ddi_intr_get_supported_types failed: status 0x%08x", 57324045d941Ssowmini ddi_status)); 573344961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 573444961713Sgirish } 573544961713Sgirish nxgep->nxge_intr_type.intr_types = intr_types; 573644961713Sgirish 573744961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 57384045d941Ssowmini "ddi_intr_get_supported_types: 0x%08x", intr_types)); 573944961713Sgirish 574044961713Sgirish /* 574144961713Sgirish * Solaris MSIX is not supported yet. use MSI for now. 574244961713Sgirish * nxge_msi_enable (1): 574344961713Sgirish * 1 - MSI 2 - MSI-X others - FIXED 574444961713Sgirish */ 574544961713Sgirish switch (nxge_msi_enable) { 574644961713Sgirish default: 574744961713Sgirish type = DDI_INTR_TYPE_FIXED; 574844961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: " 57494045d941Ssowmini "use fixed (intx emulation) type %08x", 57504045d941Ssowmini type)); 575144961713Sgirish break; 575244961713Sgirish 575344961713Sgirish case 2: 575444961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: " 57554045d941Ssowmini "ddi_intr_get_supported_types: 0x%08x", intr_types)); 575644961713Sgirish if (intr_types & DDI_INTR_TYPE_MSIX) { 575744961713Sgirish type = DDI_INTR_TYPE_MSIX; 575844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 57594045d941Ssowmini "ddi_intr_get_supported_types: MSIX 0x%08x", 57604045d941Ssowmini type)); 576144961713Sgirish } else if (intr_types & DDI_INTR_TYPE_MSI) { 576244961713Sgirish type = DDI_INTR_TYPE_MSI; 576344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 57644045d941Ssowmini "ddi_intr_get_supported_types: MSI 0x%08x", 57654045d941Ssowmini type)); 576644961713Sgirish } else if (intr_types & DDI_INTR_TYPE_FIXED) { 576744961713Sgirish type = DDI_INTR_TYPE_FIXED; 576844961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: " 57694045d941Ssowmini "ddi_intr_get_supported_types: MSXED0x%08x", 57704045d941Ssowmini type)); 577144961713Sgirish } 577244961713Sgirish break; 577344961713Sgirish 577444961713Sgirish case 1: 577544961713Sgirish if (intr_types & DDI_INTR_TYPE_MSI) { 577644961713Sgirish type = DDI_INTR_TYPE_MSI; 577744961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: " 57784045d941Ssowmini "ddi_intr_get_supported_types: MSI 0x%08x", 57794045d941Ssowmini type)); 578044961713Sgirish } else if (intr_types & DDI_INTR_TYPE_MSIX) { 578144961713Sgirish type = DDI_INTR_TYPE_MSIX; 578244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 57834045d941Ssowmini "ddi_intr_get_supported_types: MSIX 0x%08x", 57844045d941Ssowmini type)); 578544961713Sgirish } else if (intr_types & DDI_INTR_TYPE_FIXED) { 578644961713Sgirish type = DDI_INTR_TYPE_FIXED; 578744961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 57884045d941Ssowmini "ddi_intr_get_supported_types: MSXED0x%08x", 57894045d941Ssowmini type)); 579044961713Sgirish } 579144961713Sgirish } 579244961713Sgirish 579344961713Sgirish nxgep->nxge_intr_type.intr_type = type; 579444961713Sgirish if ((type == DDI_INTR_TYPE_MSIX || type == DDI_INTR_TYPE_MSI || 57954045d941Ssowmini type == DDI_INTR_TYPE_FIXED) && 57964045d941Ssowmini nxgep->nxge_intr_type.niu_msi_enable) { 579744961713Sgirish if ((status = nxge_add_intrs_adv(nxgep)) != DDI_SUCCESS) { 579844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 57994045d941Ssowmini " nxge_add_intrs: " 58004045d941Ssowmini " nxge_add_intrs_adv failed: status 0x%08x", 58014045d941Ssowmini status)); 580244961713Sgirish return (status); 580344961713Sgirish } else { 580444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 58054045d941Ssowmini "interrupts registered : type %d", type)); 580644961713Sgirish nxgep->nxge_intr_type.intr_registered = B_TRUE; 580744961713Sgirish 580844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 58094045d941Ssowmini "\nAdded advanced nxge add_intr_adv " 58104045d941Ssowmini "intr type 0x%x\n", type)); 581144961713Sgirish 581244961713Sgirish return (status); 581344961713Sgirish } 581444961713Sgirish } 581544961713Sgirish 581644961713Sgirish if (!nxgep->nxge_intr_type.intr_registered) { 581744961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "==> nxge_add_intrs: " 58184045d941Ssowmini "failed to register interrupts")); 581944961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 582044961713Sgirish } 582144961713Sgirish 582244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_add_intrs")); 582344961713Sgirish return (status); 582444961713Sgirish } 582544961713Sgirish 582644961713Sgirish static nxge_status_t 582744961713Sgirish nxge_add_intrs_adv(p_nxge_t nxgep) 582844961713Sgirish { 582944961713Sgirish int intr_type; 583044961713Sgirish p_nxge_intr_t intrp; 583144961713Sgirish 583244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs_adv")); 583344961713Sgirish 583444961713Sgirish intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 583544961713Sgirish intr_type = intrp->intr_type; 583644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs_adv: type 0x%x", 58374045d941Ssowmini intr_type)); 583844961713Sgirish 583944961713Sgirish switch (intr_type) { 584044961713Sgirish case DDI_INTR_TYPE_MSI: /* 0x2 */ 584144961713Sgirish case DDI_INTR_TYPE_MSIX: /* 0x4 */ 584244961713Sgirish return (nxge_add_intrs_adv_type(nxgep, intr_type)); 584344961713Sgirish 584444961713Sgirish case DDI_INTR_TYPE_FIXED: /* 0x1 */ 584544961713Sgirish return (nxge_add_intrs_adv_type_fix(nxgep, intr_type)); 584644961713Sgirish 584744961713Sgirish default: 584844961713Sgirish return (NXGE_ERROR); 584944961713Sgirish } 585044961713Sgirish } 585144961713Sgirish 585244961713Sgirish 585344961713Sgirish /*ARGSUSED*/ 585444961713Sgirish static nxge_status_t 585544961713Sgirish nxge_add_intrs_adv_type(p_nxge_t nxgep, uint32_t int_type) 585644961713Sgirish { 585744961713Sgirish dev_info_t *dip = nxgep->dip; 585844961713Sgirish p_nxge_ldg_t ldgp; 585944961713Sgirish p_nxge_intr_t intrp; 586044961713Sgirish uint_t *inthandler; 586144961713Sgirish void *arg1, *arg2; 586244961713Sgirish int behavior; 5863ec090658Sml int nintrs, navail, nrequest; 586444961713Sgirish int nactual, nrequired; 586544961713Sgirish int inum = 0; 586644961713Sgirish int x, y; 586744961713Sgirish int ddi_status = DDI_SUCCESS; 586844961713Sgirish nxge_status_t status = NXGE_OK; 586944961713Sgirish 587044961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs_adv_type")); 587144961713Sgirish intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 587244961713Sgirish intrp->start_inum = 0; 587344961713Sgirish 587444961713Sgirish ddi_status = ddi_intr_get_nintrs(dip, int_type, &nintrs); 587544961713Sgirish if ((ddi_status != DDI_SUCCESS) || (nintrs == 0)) { 587644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 58774045d941Ssowmini "ddi_intr_get_nintrs() failed, status: 0x%x%, " 58784045d941Ssowmini "nintrs: %d", ddi_status, nintrs)); 587944961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 588044961713Sgirish } 588144961713Sgirish 588244961713Sgirish ddi_status = ddi_intr_get_navail(dip, int_type, &navail); 588344961713Sgirish if ((ddi_status != DDI_SUCCESS) || (navail == 0)) { 588444961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 58854045d941Ssowmini "ddi_intr_get_navail() failed, status: 0x%x%, " 58864045d941Ssowmini "nintrs: %d", ddi_status, navail)); 588744961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 588844961713Sgirish } 588944961713Sgirish 589044961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 58914045d941Ssowmini "ddi_intr_get_navail() returned: nintrs %d, navail %d", 58924045d941Ssowmini nintrs, navail)); 589344961713Sgirish 5894ec090658Sml /* PSARC/2007/453 MSI-X interrupt limit override */ 5895ec090658Sml if (int_type == DDI_INTR_TYPE_MSIX) { 5896ec090658Sml nrequest = nxge_create_msi_property(nxgep); 5897ec090658Sml if (nrequest < navail) { 5898ec090658Sml navail = nrequest; 5899ec090658Sml NXGE_DEBUG_MSG((nxgep, INT_CTL, 5900ec090658Sml "nxge_add_intrs_adv_type: nintrs %d " 5901ec090658Sml "navail %d (nrequest %d)", 5902ec090658Sml nintrs, navail, nrequest)); 5903ec090658Sml } 5904ec090658Sml } 5905ec090658Sml 590644961713Sgirish if (int_type == DDI_INTR_TYPE_MSI && !ISP2(navail)) { 590744961713Sgirish /* MSI must be power of 2 */ 590844961713Sgirish if ((navail & 16) == 16) { 590944961713Sgirish navail = 16; 591044961713Sgirish } else if ((navail & 8) == 8) { 591144961713Sgirish navail = 8; 591244961713Sgirish } else if ((navail & 4) == 4) { 591344961713Sgirish navail = 4; 591444961713Sgirish } else if ((navail & 2) == 2) { 591544961713Sgirish navail = 2; 591644961713Sgirish } else { 591744961713Sgirish navail = 1; 591844961713Sgirish } 591944961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 59204045d941Ssowmini "ddi_intr_get_navail(): (msi power of 2) nintrs %d, " 59214045d941Ssowmini "navail %d", nintrs, navail)); 592244961713Sgirish } 592344961713Sgirish 592444961713Sgirish behavior = ((int_type == DDI_INTR_TYPE_FIXED) ? DDI_INTR_ALLOC_STRICT : 59254045d941Ssowmini DDI_INTR_ALLOC_NORMAL); 592644961713Sgirish intrp->intr_size = navail * sizeof (ddi_intr_handle_t); 592744961713Sgirish intrp->htable = kmem_alloc(intrp->intr_size, KM_SLEEP); 592844961713Sgirish ddi_status = ddi_intr_alloc(dip, intrp->htable, int_type, inum, 59294045d941Ssowmini navail, &nactual, behavior); 593044961713Sgirish if (ddi_status != DDI_SUCCESS || nactual == 0) { 593144961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 59324045d941Ssowmini " ddi_intr_alloc() failed: %d", 59334045d941Ssowmini ddi_status)); 593444961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 593544961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 593644961713Sgirish } 593744961713Sgirish 593844961713Sgirish if ((ddi_status = ddi_intr_get_pri(intrp->htable[0], 59394045d941Ssowmini (uint_t *)&intrp->pri)) != DDI_SUCCESS) { 594044961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 59414045d941Ssowmini " ddi_intr_get_pri() failed: %d", 59424045d941Ssowmini ddi_status)); 594344961713Sgirish /* Free already allocated interrupts */ 594444961713Sgirish for (y = 0; y < nactual; y++) { 594544961713Sgirish (void) ddi_intr_free(intrp->htable[y]); 594644961713Sgirish } 594744961713Sgirish 594844961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 594944961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 595044961713Sgirish } 595144961713Sgirish 595244961713Sgirish nrequired = 0; 595344961713Sgirish switch (nxgep->niu_type) { 595444961713Sgirish default: 595544961713Sgirish status = nxge_ldgv_init(nxgep, &nactual, &nrequired); 595644961713Sgirish break; 595744961713Sgirish 595844961713Sgirish case N2_NIU: 595944961713Sgirish status = nxge_ldgv_init_n2(nxgep, &nactual, &nrequired); 596044961713Sgirish break; 596144961713Sgirish } 596244961713Sgirish 596344961713Sgirish if (status != NXGE_OK) { 596444961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 59654045d941Ssowmini "nxge_add_intrs_adv_typ:nxge_ldgv_init " 59664045d941Ssowmini "failed: 0x%x", status)); 596744961713Sgirish /* Free already allocated interrupts */ 596844961713Sgirish for (y = 0; y < nactual; y++) { 596944961713Sgirish (void) ddi_intr_free(intrp->htable[y]); 597044961713Sgirish } 597144961713Sgirish 597244961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 597344961713Sgirish return (status); 597444961713Sgirish } 597544961713Sgirish 597644961713Sgirish ldgp = nxgep->ldgvp->ldgp; 597744961713Sgirish for (x = 0; x < nrequired; x++, ldgp++) { 597844961713Sgirish ldgp->vector = (uint8_t)x; 597944961713Sgirish ldgp->intdata = SID_DATA(ldgp->func, x); 598044961713Sgirish arg1 = ldgp->ldvp; 598144961713Sgirish arg2 = nxgep; 598244961713Sgirish if (ldgp->nldvs == 1) { 598344961713Sgirish inthandler = (uint_t *)ldgp->ldvp->ldv_intr_handler; 598444961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 59854045d941Ssowmini "nxge_add_intrs_adv_type: " 59864045d941Ssowmini "arg1 0x%x arg2 0x%x: " 59874045d941Ssowmini "1-1 int handler (entry %d intdata 0x%x)\n", 59884045d941Ssowmini arg1, arg2, 59894045d941Ssowmini x, ldgp->intdata)); 599044961713Sgirish } else if (ldgp->nldvs > 1) { 599144961713Sgirish inthandler = (uint_t *)ldgp->sys_intr_handler; 599244961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 59934045d941Ssowmini "nxge_add_intrs_adv_type: " 59944045d941Ssowmini "arg1 0x%x arg2 0x%x: " 59954045d941Ssowmini "nldevs %d int handler " 59964045d941Ssowmini "(entry %d intdata 0x%x)\n", 59974045d941Ssowmini arg1, arg2, 59984045d941Ssowmini ldgp->nldvs, x, ldgp->intdata)); 599944961713Sgirish } 600044961713Sgirish 600144961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 60024045d941Ssowmini "==> nxge_add_intrs_adv_type: ddi_add_intr(inum) #%d " 60034045d941Ssowmini "htable 0x%llx", x, intrp->htable[x])); 600444961713Sgirish 600544961713Sgirish if ((ddi_status = ddi_intr_add_handler(intrp->htable[x], 60064045d941Ssowmini (ddi_intr_handler_t *)inthandler, arg1, arg2)) 60074045d941Ssowmini != DDI_SUCCESS) { 600844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 60094045d941Ssowmini "==> nxge_add_intrs_adv_type: failed #%d " 60104045d941Ssowmini "status 0x%x", x, ddi_status)); 601144961713Sgirish for (y = 0; y < intrp->intr_added; y++) { 601244961713Sgirish (void) ddi_intr_remove_handler( 60134045d941Ssowmini intrp->htable[y]); 601444961713Sgirish } 601544961713Sgirish /* Free already allocated intr */ 601644961713Sgirish for (y = 0; y < nactual; y++) { 601744961713Sgirish (void) ddi_intr_free(intrp->htable[y]); 601844961713Sgirish } 601944961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 602044961713Sgirish 602144961713Sgirish (void) nxge_ldgv_uninit(nxgep); 602244961713Sgirish 602344961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 602444961713Sgirish } 602544961713Sgirish intrp->intr_added++; 602644961713Sgirish } 602744961713Sgirish 602844961713Sgirish intrp->msi_intx_cnt = nactual; 602944961713Sgirish 603044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 60314045d941Ssowmini "Requested: %d, Allowed: %d msi_intx_cnt %d intr_added %d", 60324045d941Ssowmini navail, nactual, 60334045d941Ssowmini intrp->msi_intx_cnt, 60344045d941Ssowmini intrp->intr_added)); 603544961713Sgirish 603644961713Sgirish (void) ddi_intr_get_cap(intrp->htable[0], &intrp->intr_cap); 603744961713Sgirish 603844961713Sgirish (void) nxge_intr_ldgv_init(nxgep); 603944961713Sgirish 604044961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_add_intrs_adv_type")); 604144961713Sgirish 604244961713Sgirish return (status); 604344961713Sgirish } 604444961713Sgirish 604544961713Sgirish /*ARGSUSED*/ 604644961713Sgirish static nxge_status_t 604744961713Sgirish nxge_add_intrs_adv_type_fix(p_nxge_t nxgep, uint32_t int_type) 604844961713Sgirish { 604944961713Sgirish dev_info_t *dip = nxgep->dip; 605044961713Sgirish p_nxge_ldg_t ldgp; 605144961713Sgirish p_nxge_intr_t intrp; 605244961713Sgirish uint_t *inthandler; 605344961713Sgirish void *arg1, *arg2; 605444961713Sgirish int behavior; 605544961713Sgirish int nintrs, navail; 605644961713Sgirish int nactual, nrequired; 605744961713Sgirish int inum = 0; 605844961713Sgirish int x, y; 605944961713Sgirish int ddi_status = DDI_SUCCESS; 606044961713Sgirish nxge_status_t status = NXGE_OK; 606144961713Sgirish 606244961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs_adv_type_fix")); 606344961713Sgirish intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 606444961713Sgirish intrp->start_inum = 0; 606544961713Sgirish 606644961713Sgirish ddi_status = ddi_intr_get_nintrs(dip, int_type, &nintrs); 606744961713Sgirish if ((ddi_status != DDI_SUCCESS) || (nintrs == 0)) { 606844961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 60694045d941Ssowmini "ddi_intr_get_nintrs() failed, status: 0x%x%, " 60704045d941Ssowmini "nintrs: %d", status, nintrs)); 607144961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 607244961713Sgirish } 607344961713Sgirish 607444961713Sgirish ddi_status = ddi_intr_get_navail(dip, int_type, &navail); 607544961713Sgirish if ((ddi_status != DDI_SUCCESS) || (navail == 0)) { 607644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 60774045d941Ssowmini "ddi_intr_get_navail() failed, status: 0x%x%, " 60784045d941Ssowmini "nintrs: %d", ddi_status, navail)); 607944961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 608044961713Sgirish } 608144961713Sgirish 608244961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 60834045d941Ssowmini "ddi_intr_get_navail() returned: nintrs %d, naavail %d", 60844045d941Ssowmini nintrs, navail)); 608544961713Sgirish 608644961713Sgirish behavior = ((int_type == DDI_INTR_TYPE_FIXED) ? DDI_INTR_ALLOC_STRICT : 60874045d941Ssowmini DDI_INTR_ALLOC_NORMAL); 608844961713Sgirish intrp->intr_size = navail * sizeof (ddi_intr_handle_t); 608944961713Sgirish intrp->htable = kmem_alloc(intrp->intr_size, KM_SLEEP); 609044961713Sgirish ddi_status = ddi_intr_alloc(dip, intrp->htable, int_type, inum, 60914045d941Ssowmini navail, &nactual, behavior); 609244961713Sgirish if (ddi_status != DDI_SUCCESS || nactual == 0) { 609344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 60944045d941Ssowmini " ddi_intr_alloc() failed: %d", 60954045d941Ssowmini ddi_status)); 609644961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 609744961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 609844961713Sgirish } 609944961713Sgirish 610044961713Sgirish if ((ddi_status = ddi_intr_get_pri(intrp->htable[0], 61014045d941Ssowmini (uint_t *)&intrp->pri)) != DDI_SUCCESS) { 610244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 61034045d941Ssowmini " ddi_intr_get_pri() failed: %d", 61044045d941Ssowmini ddi_status)); 610544961713Sgirish /* Free already allocated interrupts */ 610644961713Sgirish for (y = 0; y < nactual; y++) { 610744961713Sgirish (void) ddi_intr_free(intrp->htable[y]); 610844961713Sgirish } 610944961713Sgirish 611044961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 611144961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 611244961713Sgirish } 611344961713Sgirish 611444961713Sgirish nrequired = 0; 611544961713Sgirish switch (nxgep->niu_type) { 611644961713Sgirish default: 611744961713Sgirish status = nxge_ldgv_init(nxgep, &nactual, &nrequired); 611844961713Sgirish break; 611944961713Sgirish 612044961713Sgirish case N2_NIU: 612144961713Sgirish status = nxge_ldgv_init_n2(nxgep, &nactual, &nrequired); 612244961713Sgirish break; 612344961713Sgirish } 612444961713Sgirish 612544961713Sgirish if (status != NXGE_OK) { 612644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 61274045d941Ssowmini "nxge_add_intrs_adv_type_fix:nxge_ldgv_init " 61284045d941Ssowmini "failed: 0x%x", status)); 612944961713Sgirish /* Free already allocated interrupts */ 613044961713Sgirish for (y = 0; y < nactual; y++) { 613144961713Sgirish (void) ddi_intr_free(intrp->htable[y]); 613244961713Sgirish } 613344961713Sgirish 613444961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 613544961713Sgirish return (status); 613644961713Sgirish } 613744961713Sgirish 613844961713Sgirish ldgp = nxgep->ldgvp->ldgp; 613944961713Sgirish for (x = 0; x < nrequired; x++, ldgp++) { 614044961713Sgirish ldgp->vector = (uint8_t)x; 614144961713Sgirish if (nxgep->niu_type != N2_NIU) { 614244961713Sgirish ldgp->intdata = SID_DATA(ldgp->func, x); 614344961713Sgirish } 614444961713Sgirish 614544961713Sgirish arg1 = ldgp->ldvp; 614644961713Sgirish arg2 = nxgep; 614744961713Sgirish if (ldgp->nldvs == 1) { 614844961713Sgirish inthandler = (uint_t *)ldgp->ldvp->ldv_intr_handler; 614944961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 61504045d941Ssowmini "nxge_add_intrs_adv_type_fix: " 61514045d941Ssowmini "1-1 int handler(%d) ldg %d ldv %d " 61524045d941Ssowmini "arg1 $%p arg2 $%p\n", 61534045d941Ssowmini x, ldgp->ldg, ldgp->ldvp->ldv, 61544045d941Ssowmini arg1, arg2)); 615544961713Sgirish } else if (ldgp->nldvs > 1) { 615644961713Sgirish inthandler = (uint_t *)ldgp->sys_intr_handler; 615744961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 61584045d941Ssowmini "nxge_add_intrs_adv_type_fix: " 61594045d941Ssowmini "shared ldv %d int handler(%d) ldv %d ldg %d" 61604045d941Ssowmini "arg1 0x%016llx arg2 0x%016llx\n", 61614045d941Ssowmini x, ldgp->nldvs, ldgp->ldg, ldgp->ldvp->ldv, 61624045d941Ssowmini arg1, arg2)); 616344961713Sgirish } 616444961713Sgirish 616544961713Sgirish if ((ddi_status = ddi_intr_add_handler(intrp->htable[x], 61664045d941Ssowmini (ddi_intr_handler_t *)inthandler, arg1, arg2)) 61674045d941Ssowmini != DDI_SUCCESS) { 616844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 61694045d941Ssowmini "==> nxge_add_intrs_adv_type_fix: failed #%d " 61704045d941Ssowmini "status 0x%x", x, ddi_status)); 617144961713Sgirish for (y = 0; y < intrp->intr_added; y++) { 617244961713Sgirish (void) ddi_intr_remove_handler( 61734045d941Ssowmini intrp->htable[y]); 617444961713Sgirish } 617544961713Sgirish for (y = 0; y < nactual; y++) { 617644961713Sgirish (void) ddi_intr_free(intrp->htable[y]); 617744961713Sgirish } 617844961713Sgirish /* Free already allocated intr */ 617944961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 618044961713Sgirish 618144961713Sgirish (void) nxge_ldgv_uninit(nxgep); 618244961713Sgirish 618344961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 618444961713Sgirish } 618544961713Sgirish intrp->intr_added++; 618644961713Sgirish } 618744961713Sgirish 618844961713Sgirish intrp->msi_intx_cnt = nactual; 618944961713Sgirish 619044961713Sgirish (void) ddi_intr_get_cap(intrp->htable[0], &intrp->intr_cap); 619144961713Sgirish 619244961713Sgirish status = nxge_intr_ldgv_init(nxgep); 619344961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_add_intrs_adv_type_fix")); 619444961713Sgirish 619544961713Sgirish return (status); 619644961713Sgirish } 619744961713Sgirish 619844961713Sgirish static void 619944961713Sgirish nxge_remove_intrs(p_nxge_t nxgep) 620044961713Sgirish { 620144961713Sgirish int i, inum; 620244961713Sgirish p_nxge_intr_t intrp; 620344961713Sgirish 620444961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_remove_intrs")); 620544961713Sgirish intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 620644961713Sgirish if (!intrp->intr_registered) { 620744961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 62084045d941Ssowmini "<== nxge_remove_intrs: interrupts not registered")); 620944961713Sgirish return; 621044961713Sgirish } 621144961713Sgirish 621244961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_remove_intrs:advanced")); 621344961713Sgirish 621444961713Sgirish if (intrp->intr_cap & DDI_INTR_FLAG_BLOCK) { 621544961713Sgirish (void) ddi_intr_block_disable(intrp->htable, 62164045d941Ssowmini intrp->intr_added); 621744961713Sgirish } else { 621844961713Sgirish for (i = 0; i < intrp->intr_added; i++) { 621944961713Sgirish (void) ddi_intr_disable(intrp->htable[i]); 622044961713Sgirish } 622144961713Sgirish } 622244961713Sgirish 622344961713Sgirish for (inum = 0; inum < intrp->intr_added; inum++) { 622444961713Sgirish if (intrp->htable[inum]) { 622544961713Sgirish (void) ddi_intr_remove_handler(intrp->htable[inum]); 622644961713Sgirish } 622744961713Sgirish } 622844961713Sgirish 622944961713Sgirish for (inum = 0; inum < intrp->msi_intx_cnt; inum++) { 623044961713Sgirish if (intrp->htable[inum]) { 623144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 62324045d941Ssowmini "nxge_remove_intrs: ddi_intr_free inum %d " 62334045d941Ssowmini "msi_intx_cnt %d intr_added %d", 62344045d941Ssowmini inum, 62354045d941Ssowmini intrp->msi_intx_cnt, 62364045d941Ssowmini intrp->intr_added)); 623744961713Sgirish 623844961713Sgirish (void) ddi_intr_free(intrp->htable[inum]); 623944961713Sgirish } 624044961713Sgirish } 624144961713Sgirish 624244961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 624344961713Sgirish intrp->intr_registered = B_FALSE; 624444961713Sgirish intrp->intr_enabled = B_FALSE; 624544961713Sgirish intrp->msi_intx_cnt = 0; 624644961713Sgirish intrp->intr_added = 0; 624744961713Sgirish 6248a3c5bd6dSspeer (void) nxge_ldgv_uninit(nxgep); 6249a3c5bd6dSspeer 6250ec090658Sml (void) ddi_prop_remove(DDI_DEV_T_NONE, nxgep->dip, 6251ec090658Sml "#msix-request"); 6252ec090658Sml 625344961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_remove_intrs")); 625444961713Sgirish } 625544961713Sgirish 625644961713Sgirish /*ARGSUSED*/ 625744961713Sgirish static void 625844961713Sgirish nxge_intrs_enable(p_nxge_t nxgep) 625944961713Sgirish { 626044961713Sgirish p_nxge_intr_t intrp; 626144961713Sgirish int i; 626244961713Sgirish int status; 626344961713Sgirish 626444961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_enable")); 626544961713Sgirish 626644961713Sgirish intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 626744961713Sgirish 626844961713Sgirish if (!intrp->intr_registered) { 626944961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_intrs_enable: " 62704045d941Ssowmini "interrupts are not registered")); 627144961713Sgirish return; 627244961713Sgirish } 627344961713Sgirish 627444961713Sgirish if (intrp->intr_enabled) { 627544961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 62764045d941Ssowmini "<== nxge_intrs_enable: already enabled")); 627744961713Sgirish return; 627844961713Sgirish } 627944961713Sgirish 628044961713Sgirish if (intrp->intr_cap & DDI_INTR_FLAG_BLOCK) { 628144961713Sgirish status = ddi_intr_block_enable(intrp->htable, 62824045d941Ssowmini intrp->intr_added); 628344961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_enable " 62844045d941Ssowmini "block enable - status 0x%x total inums #%d\n", 62854045d941Ssowmini status, intrp->intr_added)); 628644961713Sgirish } else { 628744961713Sgirish for (i = 0; i < intrp->intr_added; i++) { 628844961713Sgirish status = ddi_intr_enable(intrp->htable[i]); 628944961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_enable " 62904045d941Ssowmini "ddi_intr_enable:enable - status 0x%x " 62914045d941Ssowmini "total inums %d enable inum #%d\n", 62924045d941Ssowmini status, intrp->intr_added, i)); 629344961713Sgirish if (status == DDI_SUCCESS) { 629444961713Sgirish intrp->intr_enabled = B_TRUE; 629544961713Sgirish } 629644961713Sgirish } 629744961713Sgirish } 629844961713Sgirish 629944961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intrs_enable")); 630044961713Sgirish } 630144961713Sgirish 630244961713Sgirish /*ARGSUSED*/ 630344961713Sgirish static void 630444961713Sgirish nxge_intrs_disable(p_nxge_t nxgep) 630544961713Sgirish { 630644961713Sgirish p_nxge_intr_t intrp; 630744961713Sgirish int i; 630844961713Sgirish 630944961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_disable")); 631044961713Sgirish 631144961713Sgirish intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 631244961713Sgirish 631344961713Sgirish if (!intrp->intr_registered) { 631444961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intrs_disable: " 63154045d941Ssowmini "interrupts are not registered")); 631644961713Sgirish return; 631744961713Sgirish } 631844961713Sgirish 631944961713Sgirish if (intrp->intr_cap & DDI_INTR_FLAG_BLOCK) { 632044961713Sgirish (void) ddi_intr_block_disable(intrp->htable, 63214045d941Ssowmini intrp->intr_added); 632244961713Sgirish } else { 632344961713Sgirish for (i = 0; i < intrp->intr_added; i++) { 632444961713Sgirish (void) ddi_intr_disable(intrp->htable[i]); 632544961713Sgirish } 632644961713Sgirish } 632744961713Sgirish 632844961713Sgirish intrp->intr_enabled = B_FALSE; 632944961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intrs_disable")); 633044961713Sgirish } 633144961713Sgirish 633244961713Sgirish static nxge_status_t 633344961713Sgirish nxge_mac_register(p_nxge_t nxgep) 633444961713Sgirish { 633544961713Sgirish mac_register_t *macp; 633644961713Sgirish int status; 633744961713Sgirish 633844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_mac_register")); 633944961713Sgirish 634044961713Sgirish if ((macp = mac_alloc(MAC_VERSION)) == NULL) 634144961713Sgirish return (NXGE_ERROR); 634244961713Sgirish 634344961713Sgirish macp->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 634444961713Sgirish macp->m_driver = nxgep; 634544961713Sgirish macp->m_dip = nxgep->dip; 634644961713Sgirish macp->m_src_addr = nxgep->ouraddr.ether_addr_octet; 634744961713Sgirish macp->m_callbacks = &nxge_m_callbacks; 634844961713Sgirish macp->m_min_sdu = 0; 63491bd6825cSml nxgep->mac.default_mtu = nxgep->mac.maxframesize - 63501bd6825cSml NXGE_EHEADER_VLAN_CRC; 63511bd6825cSml macp->m_max_sdu = nxgep->mac.default_mtu; 6352d62bc4baSyz macp->m_margin = VLAN_TAGSZ; 63534045d941Ssowmini macp->m_priv_props = nxge_priv_props; 63544045d941Ssowmini macp->m_priv_prop_count = NXGE_MAX_PRIV_PROPS; 6355da14cebeSEric Cheng macp->m_v12n = MAC_VIRT_HIO | MAC_VIRT_LEVEL1 | MAC_VIRT_SERIALIZE; 635644961713Sgirish 63571bd6825cSml NXGE_DEBUG_MSG((nxgep, MAC_CTL, 63581bd6825cSml "==> nxge_mac_register: instance %d " 63591bd6825cSml "max_sdu %d margin %d maxframe %d (header %d)", 63601bd6825cSml nxgep->instance, 63611bd6825cSml macp->m_max_sdu, macp->m_margin, 63621bd6825cSml nxgep->mac.maxframesize, 63631bd6825cSml NXGE_EHEADER_VLAN_CRC)); 63641bd6825cSml 636544961713Sgirish status = mac_register(macp, &nxgep->mach); 636644961713Sgirish mac_free(macp); 636744961713Sgirish 636844961713Sgirish if (status != 0) { 636944961713Sgirish cmn_err(CE_WARN, 63704045d941Ssowmini "!nxge_mac_register failed (status %d instance %d)", 63714045d941Ssowmini status, nxgep->instance); 637244961713Sgirish return (NXGE_ERROR); 637344961713Sgirish } 637444961713Sgirish 637544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_mac_register success " 63764045d941Ssowmini "(instance %d)", nxgep->instance)); 637744961713Sgirish 637844961713Sgirish return (NXGE_OK); 637944961713Sgirish } 638044961713Sgirish 638144961713Sgirish void 638244961713Sgirish nxge_err_inject(p_nxge_t nxgep, queue_t *wq, mblk_t *mp) 638344961713Sgirish { 638444961713Sgirish ssize_t size; 638544961713Sgirish mblk_t *nmp; 638644961713Sgirish uint8_t blk_id; 638744961713Sgirish uint8_t chan; 638844961713Sgirish uint32_t err_id; 638944961713Sgirish err_inject_t *eip; 639044961713Sgirish 639144961713Sgirish NXGE_DEBUG_MSG((nxgep, STR_CTL, "==> nxge_err_inject")); 639244961713Sgirish 639344961713Sgirish size = 1024; 639444961713Sgirish nmp = mp->b_cont; 639544961713Sgirish eip = (err_inject_t *)nmp->b_rptr; 639644961713Sgirish blk_id = eip->blk_id; 639744961713Sgirish err_id = eip->err_id; 639844961713Sgirish chan = eip->chan; 639944961713Sgirish cmn_err(CE_NOTE, "!blk_id = 0x%x\n", blk_id); 640044961713Sgirish cmn_err(CE_NOTE, "!err_id = 0x%x\n", err_id); 640144961713Sgirish cmn_err(CE_NOTE, "!chan = 0x%x\n", chan); 640244961713Sgirish switch (blk_id) { 640344961713Sgirish case MAC_BLK_ID: 640444961713Sgirish break; 640544961713Sgirish case TXMAC_BLK_ID: 640644961713Sgirish break; 640744961713Sgirish case RXMAC_BLK_ID: 640844961713Sgirish break; 640944961713Sgirish case MIF_BLK_ID: 641044961713Sgirish break; 641144961713Sgirish case IPP_BLK_ID: 641244961713Sgirish nxge_ipp_inject_err(nxgep, err_id); 641344961713Sgirish break; 641444961713Sgirish case TXC_BLK_ID: 641544961713Sgirish nxge_txc_inject_err(nxgep, err_id); 641644961713Sgirish break; 641744961713Sgirish case TXDMA_BLK_ID: 641844961713Sgirish nxge_txdma_inject_err(nxgep, err_id, chan); 641944961713Sgirish break; 642044961713Sgirish case RXDMA_BLK_ID: 642144961713Sgirish nxge_rxdma_inject_err(nxgep, err_id, chan); 642244961713Sgirish break; 642344961713Sgirish case ZCP_BLK_ID: 642444961713Sgirish nxge_zcp_inject_err(nxgep, err_id); 642544961713Sgirish break; 642644961713Sgirish case ESPC_BLK_ID: 642744961713Sgirish break; 642844961713Sgirish case FFLP_BLK_ID: 642944961713Sgirish break; 643044961713Sgirish case PHY_BLK_ID: 643144961713Sgirish break; 643244961713Sgirish case ETHER_SERDES_BLK_ID: 643344961713Sgirish break; 643444961713Sgirish case PCIE_SERDES_BLK_ID: 643544961713Sgirish break; 643644961713Sgirish case VIR_BLK_ID: 643744961713Sgirish break; 643844961713Sgirish } 643944961713Sgirish 644044961713Sgirish nmp->b_wptr = nmp->b_rptr + size; 644144961713Sgirish NXGE_DEBUG_MSG((nxgep, STR_CTL, "<== nxge_err_inject")); 644244961713Sgirish 644344961713Sgirish miocack(wq, mp, (int)size, 0); 644444961713Sgirish } 644544961713Sgirish 644644961713Sgirish static int 644744961713Sgirish nxge_init_common_dev(p_nxge_t nxgep) 644844961713Sgirish { 644944961713Sgirish p_nxge_hw_list_t hw_p; 645044961713Sgirish dev_info_t *p_dip; 645144961713Sgirish 645244961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, "==> nxge_init_common_device")); 645344961713Sgirish 645444961713Sgirish p_dip = nxgep->p_dip; 645544961713Sgirish MUTEX_ENTER(&nxge_common_lock); 645644961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 64574045d941Ssowmini "==> nxge_init_common_dev:func # %d", 64584045d941Ssowmini nxgep->function_num)); 645944961713Sgirish /* 646044961713Sgirish * Loop through existing per neptune hardware list. 646144961713Sgirish */ 646244961713Sgirish for (hw_p = nxge_hw_list; hw_p; hw_p = hw_p->next) { 646344961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 64644045d941Ssowmini "==> nxge_init_common_device:func # %d " 64654045d941Ssowmini "hw_p $%p parent dip $%p", 64664045d941Ssowmini nxgep->function_num, 64674045d941Ssowmini hw_p, 64684045d941Ssowmini p_dip)); 646944961713Sgirish if (hw_p->parent_devp == p_dip) { 647044961713Sgirish nxgep->nxge_hw_p = hw_p; 647144961713Sgirish hw_p->ndevs++; 647244961713Sgirish hw_p->nxge_p[nxgep->function_num] = nxgep; 647344961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 64744045d941Ssowmini "==> nxge_init_common_device:func # %d " 64754045d941Ssowmini "hw_p $%p parent dip $%p " 64764045d941Ssowmini "ndevs %d (found)", 64774045d941Ssowmini nxgep->function_num, 64784045d941Ssowmini hw_p, 64794045d941Ssowmini p_dip, 64804045d941Ssowmini hw_p->ndevs)); 648144961713Sgirish break; 648244961713Sgirish } 648344961713Sgirish } 648444961713Sgirish 648544961713Sgirish if (hw_p == NULL) { 648623b952a3SSantwona Behera 648723b952a3SSantwona Behera char **prop_val; 648823b952a3SSantwona Behera uint_t prop_len; 648923b952a3SSantwona Behera int i; 649023b952a3SSantwona Behera 649144961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 64924045d941Ssowmini "==> nxge_init_common_device:func # %d " 64934045d941Ssowmini "parent dip $%p (new)", 64944045d941Ssowmini nxgep->function_num, 64954045d941Ssowmini p_dip)); 649644961713Sgirish hw_p = kmem_zalloc(sizeof (nxge_hw_list_t), KM_SLEEP); 649744961713Sgirish hw_p->parent_devp = p_dip; 649844961713Sgirish hw_p->magic = NXGE_NEPTUNE_MAGIC; 649944961713Sgirish nxgep->nxge_hw_p = hw_p; 650044961713Sgirish hw_p->ndevs++; 650144961713Sgirish hw_p->nxge_p[nxgep->function_num] = nxgep; 650244961713Sgirish hw_p->next = nxge_hw_list; 650359ac0c16Sdavemq if (nxgep->niu_type == N2_NIU) { 650459ac0c16Sdavemq hw_p->niu_type = N2_NIU; 650559ac0c16Sdavemq hw_p->platform_type = P_NEPTUNE_NIU; 650659ac0c16Sdavemq } else { 650759ac0c16Sdavemq hw_p->niu_type = NIU_TYPE_NONE; 65082e59129aSraghus hw_p->platform_type = P_NEPTUNE_NONE; 650959ac0c16Sdavemq } 651044961713Sgirish 651144961713Sgirish MUTEX_INIT(&hw_p->nxge_cfg_lock, NULL, MUTEX_DRIVER, NULL); 651244961713Sgirish MUTEX_INIT(&hw_p->nxge_tcam_lock, NULL, MUTEX_DRIVER, NULL); 651344961713Sgirish MUTEX_INIT(&hw_p->nxge_vlan_lock, NULL, MUTEX_DRIVER, NULL); 651444961713Sgirish MUTEX_INIT(&hw_p->nxge_mdio_lock, NULL, MUTEX_DRIVER, NULL); 651544961713Sgirish 651644961713Sgirish nxge_hw_list = hw_p; 651759ac0c16Sdavemq 651823b952a3SSantwona Behera if (ddi_prop_lookup_string_array(DDI_DEV_T_ANY, nxgep->dip, 0, 651923b952a3SSantwona Behera "compatible", &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 652023b952a3SSantwona Behera for (i = 0; i < prop_len; i++) { 652123b952a3SSantwona Behera if ((strcmp((caddr_t)prop_val[i], 652223b952a3SSantwona Behera NXGE_ROCK_COMPATIBLE) == 0)) { 652323b952a3SSantwona Behera hw_p->platform_type = P_NEPTUNE_ROCK; 652423b952a3SSantwona Behera NXGE_DEBUG_MSG((nxgep, MOD_CTL, 652523b952a3SSantwona Behera "ROCK hw_p->platform_type %d", 652623b952a3SSantwona Behera hw_p->platform_type)); 652723b952a3SSantwona Behera break; 652823b952a3SSantwona Behera } 652923b952a3SSantwona Behera NXGE_DEBUG_MSG((nxgep, MOD_CTL, 653023b952a3SSantwona Behera "nxge_init_common_dev: read compatible" 653123b952a3SSantwona Behera " property[%d] val[%s]", 653223b952a3SSantwona Behera i, (caddr_t)prop_val[i])); 653323b952a3SSantwona Behera } 653423b952a3SSantwona Behera } 653523b952a3SSantwona Behera 653623b952a3SSantwona Behera ddi_prop_free(prop_val); 653723b952a3SSantwona Behera 653859ac0c16Sdavemq (void) nxge_scan_ports_phy(nxgep, nxge_hw_list); 653944961713Sgirish } 654044961713Sgirish 654144961713Sgirish MUTEX_EXIT(&nxge_common_lock); 654259ac0c16Sdavemq 65432e59129aSraghus nxgep->platform_type = hw_p->platform_type; 654423b952a3SSantwona Behera NXGE_DEBUG_MSG((nxgep, MOD_CTL, "nxgep->platform_type %d", 654523b952a3SSantwona Behera nxgep->platform_type)); 654659ac0c16Sdavemq if (nxgep->niu_type != N2_NIU) { 654759ac0c16Sdavemq nxgep->niu_type = hw_p->niu_type; 654859ac0c16Sdavemq } 654959ac0c16Sdavemq 655044961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 65514045d941Ssowmini "==> nxge_init_common_device (nxge_hw_list) $%p", 65524045d941Ssowmini nxge_hw_list)); 655344961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, "<== nxge_init_common_device")); 655444961713Sgirish 655544961713Sgirish return (NXGE_OK); 655644961713Sgirish } 655744961713Sgirish 655844961713Sgirish static void 655944961713Sgirish nxge_uninit_common_dev(p_nxge_t nxgep) 656044961713Sgirish { 656144961713Sgirish p_nxge_hw_list_t hw_p, h_hw_p; 65620b0beae0Sspeer p_nxge_dma_pt_cfg_t p_dma_cfgp; 65630b0beae0Sspeer p_nxge_hw_pt_cfg_t p_cfgp; 656444961713Sgirish dev_info_t *p_dip; 656544961713Sgirish 656644961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, "==> nxge_uninit_common_device")); 656744961713Sgirish if (nxgep->nxge_hw_p == NULL) { 656844961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 65694045d941Ssowmini "<== nxge_uninit_common_device (no common)")); 657044961713Sgirish return; 657144961713Sgirish } 657244961713Sgirish 657344961713Sgirish MUTEX_ENTER(&nxge_common_lock); 657444961713Sgirish h_hw_p = nxge_hw_list; 657544961713Sgirish for (hw_p = nxge_hw_list; hw_p; hw_p = hw_p->next) { 657644961713Sgirish p_dip = hw_p->parent_devp; 657744961713Sgirish if (nxgep->nxge_hw_p == hw_p && 65784045d941Ssowmini p_dip == nxgep->p_dip && 65794045d941Ssowmini nxgep->nxge_hw_p->magic == NXGE_NEPTUNE_MAGIC && 65804045d941Ssowmini hw_p->magic == NXGE_NEPTUNE_MAGIC) { 658144961713Sgirish 658244961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 65834045d941Ssowmini "==> nxge_uninit_common_device:func # %d " 65844045d941Ssowmini "hw_p $%p parent dip $%p " 65854045d941Ssowmini "ndevs %d (found)", 65864045d941Ssowmini nxgep->function_num, 65874045d941Ssowmini hw_p, 65884045d941Ssowmini p_dip, 65894045d941Ssowmini hw_p->ndevs)); 659044961713Sgirish 65910b0beae0Sspeer /* 65920b0beae0Sspeer * Release the RDC table, a shared resoruce 65930b0beae0Sspeer * of the nxge hardware. The RDC table was 65940b0beae0Sspeer * assigned to this instance of nxge in 65950b0beae0Sspeer * nxge_use_cfg_dma_config(). 65960b0beae0Sspeer */ 65979d5b8bc5SMichael Speer if (!isLDOMguest(nxgep)) { 65989d5b8bc5SMichael Speer p_dma_cfgp = 65999d5b8bc5SMichael Speer (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 66009d5b8bc5SMichael Speer p_cfgp = 66019d5b8bc5SMichael Speer (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 66029d5b8bc5SMichael Speer (void) nxge_fzc_rdc_tbl_unbind(nxgep, 66039d5b8bc5SMichael Speer p_cfgp->def_mac_rxdma_grpid); 6604651ce697SMichael Speer 6605651ce697SMichael Speer /* Cleanup any outstanding groups. */ 6606651ce697SMichael Speer nxge_grp_cleanup(nxgep); 66079d5b8bc5SMichael Speer } 66080b0beae0Sspeer 660944961713Sgirish if (hw_p->ndevs) { 661044961713Sgirish hw_p->ndevs--; 661144961713Sgirish } 661244961713Sgirish hw_p->nxge_p[nxgep->function_num] = NULL; 661344961713Sgirish if (!hw_p->ndevs) { 661444961713Sgirish MUTEX_DESTROY(&hw_p->nxge_vlan_lock); 661544961713Sgirish MUTEX_DESTROY(&hw_p->nxge_tcam_lock); 661644961713Sgirish MUTEX_DESTROY(&hw_p->nxge_cfg_lock); 661744961713Sgirish MUTEX_DESTROY(&hw_p->nxge_mdio_lock); 661844961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 66194045d941Ssowmini "==> nxge_uninit_common_device: " 66204045d941Ssowmini "func # %d " 66214045d941Ssowmini "hw_p $%p parent dip $%p " 66224045d941Ssowmini "ndevs %d (last)", 66234045d941Ssowmini nxgep->function_num, 66244045d941Ssowmini hw_p, 66254045d941Ssowmini p_dip, 66264045d941Ssowmini hw_p->ndevs)); 662744961713Sgirish 6628678453a8Sspeer nxge_hio_uninit(nxgep); 6629678453a8Sspeer 663044961713Sgirish if (hw_p == nxge_hw_list) { 663144961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 66324045d941Ssowmini "==> nxge_uninit_common_device:" 66334045d941Ssowmini "remove head func # %d " 66344045d941Ssowmini "hw_p $%p parent dip $%p " 66354045d941Ssowmini "ndevs %d (head)", 66364045d941Ssowmini nxgep->function_num, 66374045d941Ssowmini hw_p, 66384045d941Ssowmini p_dip, 66394045d941Ssowmini hw_p->ndevs)); 664044961713Sgirish nxge_hw_list = hw_p->next; 664144961713Sgirish } else { 664244961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 66434045d941Ssowmini "==> nxge_uninit_common_device:" 66444045d941Ssowmini "remove middle func # %d " 66454045d941Ssowmini "hw_p $%p parent dip $%p " 66464045d941Ssowmini "ndevs %d (middle)", 66474045d941Ssowmini nxgep->function_num, 66484045d941Ssowmini hw_p, 66494045d941Ssowmini p_dip, 66504045d941Ssowmini hw_p->ndevs)); 665144961713Sgirish h_hw_p->next = hw_p->next; 665244961713Sgirish } 665344961713Sgirish 6654678453a8Sspeer nxgep->nxge_hw_p = NULL; 665544961713Sgirish KMEM_FREE(hw_p, sizeof (nxge_hw_list_t)); 665644961713Sgirish } 665744961713Sgirish break; 665844961713Sgirish } else { 665944961713Sgirish h_hw_p = hw_p; 666044961713Sgirish } 666144961713Sgirish } 666244961713Sgirish 666344961713Sgirish MUTEX_EXIT(&nxge_common_lock); 666444961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 66654045d941Ssowmini "==> nxge_uninit_common_device (nxge_hw_list) $%p", 66664045d941Ssowmini nxge_hw_list)); 666744961713Sgirish 666844961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, "<= nxge_uninit_common_device")); 666944961713Sgirish } 667059ac0c16Sdavemq 667159ac0c16Sdavemq /* 66722e59129aSraghus * Determines the number of ports from the niu_type or the platform type. 667359ac0c16Sdavemq * Returns the number of ports, or returns zero on failure. 667459ac0c16Sdavemq */ 667559ac0c16Sdavemq 667659ac0c16Sdavemq int 66772e59129aSraghus nxge_get_nports(p_nxge_t nxgep) 667859ac0c16Sdavemq { 667959ac0c16Sdavemq int nports = 0; 668059ac0c16Sdavemq 66812e59129aSraghus switch (nxgep->niu_type) { 668259ac0c16Sdavemq case N2_NIU: 668359ac0c16Sdavemq case NEPTUNE_2_10GF: 668459ac0c16Sdavemq nports = 2; 668559ac0c16Sdavemq break; 668659ac0c16Sdavemq case NEPTUNE_4_1GC: 668759ac0c16Sdavemq case NEPTUNE_2_10GF_2_1GC: 668859ac0c16Sdavemq case NEPTUNE_1_10GF_3_1GC: 668959ac0c16Sdavemq case NEPTUNE_1_1GC_1_10GF_2_1GC: 669059a835ddSjoycey case NEPTUNE_2_10GF_2_1GRF: 669159ac0c16Sdavemq nports = 4; 669259ac0c16Sdavemq break; 669359ac0c16Sdavemq default: 66942e59129aSraghus switch (nxgep->platform_type) { 66952e59129aSraghus case P_NEPTUNE_NIU: 66962e59129aSraghus case P_NEPTUNE_ATLAS_2PORT: 66972e59129aSraghus nports = 2; 66982e59129aSraghus break; 66992e59129aSraghus case P_NEPTUNE_ATLAS_4PORT: 67002e59129aSraghus case P_NEPTUNE_MARAMBA_P0: 67012e59129aSraghus case P_NEPTUNE_MARAMBA_P1: 670223b952a3SSantwona Behera case P_NEPTUNE_ROCK: 6703d81011f0Ssbehera case P_NEPTUNE_ALONSO: 67042e59129aSraghus nports = 4; 67052e59129aSraghus break; 67062e59129aSraghus default: 67072e59129aSraghus break; 67082e59129aSraghus } 670959ac0c16Sdavemq break; 671059ac0c16Sdavemq } 671159ac0c16Sdavemq 671259ac0c16Sdavemq return (nports); 671359ac0c16Sdavemq } 6714ec090658Sml 6715ec090658Sml /* 6716ec090658Sml * The following two functions are to support 6717ec090658Sml * PSARC/2007/453 MSI-X interrupt limit override. 6718ec090658Sml */ 6719ec090658Sml static int 6720ec090658Sml nxge_create_msi_property(p_nxge_t nxgep) 6721ec090658Sml { 6722ec090658Sml int nmsi; 6723ec090658Sml extern int ncpus; 6724ec090658Sml 6725ec090658Sml NXGE_DEBUG_MSG((nxgep, MOD_CTL, "==>nxge_create_msi_property")); 6726ec090658Sml 6727ec090658Sml switch (nxgep->mac.portmode) { 6728ec090658Sml case PORT_10G_COPPER: 6729ec090658Sml case PORT_10G_FIBER: 673000161856Syc case PORT_10G_TN1010: 6731ec090658Sml (void) ddi_prop_create(DDI_DEV_T_NONE, nxgep->dip, 6732ec090658Sml DDI_PROP_CANSLEEP, "#msix-request", NULL, 0); 6733ec090658Sml /* 6734ec090658Sml * The maximum MSI-X requested will be 8. 6735*ef755e7aStc * If the # of CPUs is less than 8, we will request 6736*ef755e7aStc * # MSI-X based on the # of CPUs (default). 6737ec090658Sml */ 6738*ef755e7aStc NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6739*ef755e7aStc "==>nxge_create_msi_property (10G): nxge_msix_10g_intrs %d", 6740*ef755e7aStc nxge_msix_10g_intrs)); 6741*ef755e7aStc if ((nxge_msix_10g_intrs == 0) || 6742*ef755e7aStc (nxge_msix_10g_intrs > NXGE_MSIX_MAX_ALLOWED)) { 6743ec090658Sml nmsi = NXGE_MSIX_REQUEST_10G; 6744*ef755e7aStc NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6745*ef755e7aStc "==>nxge_create_msi_property (10G): reset to 8")); 6746ec090658Sml } else { 6747*ef755e7aStc nmsi = nxge_msix_10g_intrs; 6748*ef755e7aStc } 6749*ef755e7aStc 6750*ef755e7aStc /* 6751*ef755e7aStc * If # of interrupts requested is 8 (default), 6752*ef755e7aStc * the checking of the number of cpus will be 6753*ef755e7aStc * be maintained. 6754*ef755e7aStc */ 6755*ef755e7aStc if ((nmsi == NXGE_MSIX_REQUEST_10G) && 6756*ef755e7aStc (ncpus < nmsi)) { 6757*ef755e7aStc NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6758*ef755e7aStc "==>nxge_create_msi_property (10G): reset to 8")); 6759ec090658Sml nmsi = ncpus; 6760ec090658Sml } 6761ec090658Sml NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6762ec090658Sml "==>nxge_create_msi_property(10G): exists 0x%x (nmsi %d)", 6763ec090658Sml ddi_prop_exists(DDI_DEV_T_NONE, nxgep->dip, 6764ec090658Sml DDI_PROP_CANSLEEP, "#msix-request"), nmsi)); 6765ec090658Sml break; 6766ec090658Sml 6767ec090658Sml default: 6768*ef755e7aStc (void) ddi_prop_create(DDI_DEV_T_NONE, nxgep->dip, 6769*ef755e7aStc DDI_PROP_CANSLEEP, "#msix-request", NULL, 0); 6770*ef755e7aStc NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6771*ef755e7aStc "==>nxge_create_msi_property (1G): nxge_msix_1g_intrs %d", 6772*ef755e7aStc nxge_msix_1g_intrs)); 6773*ef755e7aStc if ((nxge_msix_1g_intrs == 0) || 6774*ef755e7aStc (nxge_msix_1g_intrs > NXGE_MSIX_MAX_ALLOWED)) { 6775*ef755e7aStc nmsi = NXGE_MSIX_REQUEST_1G; 6776*ef755e7aStc NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6777*ef755e7aStc "==>nxge_create_msi_property (1G): reset to 2")); 6778*ef755e7aStc } else { 6779*ef755e7aStc nmsi = nxge_msix_1g_intrs; 6780*ef755e7aStc } 6781ec090658Sml NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6782ec090658Sml "==>nxge_create_msi_property(1G): exists 0x%x (nmsi %d)", 6783ec090658Sml ddi_prop_exists(DDI_DEV_T_NONE, nxgep->dip, 6784ec090658Sml DDI_PROP_CANSLEEP, "#msix-request"), nmsi)); 6785ec090658Sml break; 6786ec090658Sml } 6787ec090658Sml 6788ec090658Sml NXGE_DEBUG_MSG((nxgep, MOD_CTL, "<==nxge_create_msi_property")); 6789ec090658Sml return (nmsi); 6790ec090658Sml } 67914045d941Ssowmini 67924045d941Ssowmini /* ARGSUSED */ 67934045d941Ssowmini static int 67944045d941Ssowmini nxge_get_def_val(nxge_t *nxgep, mac_prop_id_t pr_num, uint_t pr_valsize, 67954045d941Ssowmini void *pr_val) 67964045d941Ssowmini { 67974045d941Ssowmini int err = 0; 67984045d941Ssowmini link_flowctrl_t fl; 67994045d941Ssowmini 68004045d941Ssowmini switch (pr_num) { 68013fd94f8cSam case MAC_PROP_AUTONEG: 68024045d941Ssowmini *(uint8_t *)pr_val = 1; 68034045d941Ssowmini break; 68043fd94f8cSam case MAC_PROP_FLOWCTRL: 68054045d941Ssowmini if (pr_valsize < sizeof (link_flowctrl_t)) 68064045d941Ssowmini return (EINVAL); 68074045d941Ssowmini fl = LINK_FLOWCTRL_RX; 68084045d941Ssowmini bcopy(&fl, pr_val, sizeof (fl)); 68094045d941Ssowmini break; 68103fd94f8cSam case MAC_PROP_ADV_1000FDX_CAP: 68113fd94f8cSam case MAC_PROP_EN_1000FDX_CAP: 68124045d941Ssowmini *(uint8_t *)pr_val = 1; 68134045d941Ssowmini break; 68143fd94f8cSam case MAC_PROP_ADV_100FDX_CAP: 68153fd94f8cSam case MAC_PROP_EN_100FDX_CAP: 68164045d941Ssowmini *(uint8_t *)pr_val = 1; 68174045d941Ssowmini break; 68184045d941Ssowmini default: 68194045d941Ssowmini err = ENOTSUP; 68204045d941Ssowmini break; 68214045d941Ssowmini } 68224045d941Ssowmini return (err); 68234045d941Ssowmini } 68246f157acbSml 68256f157acbSml 68266f157acbSml /* 68276f157acbSml * The following is a software around for the Neptune hardware's 68286f157acbSml * interrupt bugs; The Neptune hardware may generate spurious interrupts when 68296f157acbSml * an interrupr handler is removed. 68306f157acbSml */ 68316f157acbSml #define NXGE_PCI_PORT_LOGIC_OFFSET 0x98 68326f157acbSml #define NXGE_PIM_RESET (1ULL << 29) 68336f157acbSml #define NXGE_GLU_RESET (1ULL << 30) 68346f157acbSml #define NXGE_NIU_RESET (1ULL << 31) 68356f157acbSml #define NXGE_PCI_RESET_ALL (NXGE_PIM_RESET | \ 68366f157acbSml NXGE_GLU_RESET | \ 68376f157acbSml NXGE_NIU_RESET) 68386f157acbSml 68396f157acbSml #define NXGE_WAIT_QUITE_TIME 200000 68406f157acbSml #define NXGE_WAIT_QUITE_RETRY 40 68416f157acbSml #define NXGE_PCI_RESET_WAIT 1000000 /* one second */ 68426f157acbSml 68436f157acbSml static void 68446f157acbSml nxge_niu_peu_reset(p_nxge_t nxgep) 68456f157acbSml { 68466f157acbSml uint32_t rvalue; 68476f157acbSml p_nxge_hw_list_t hw_p; 68486f157acbSml p_nxge_t fnxgep; 68496f157acbSml int i, j; 68506f157acbSml 68516f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, "==> nxge_niu_peu_reset")); 68526f157acbSml if ((hw_p = nxgep->nxge_hw_p) == NULL) { 68536f157acbSml NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 68546f157acbSml "==> nxge_niu_peu_reset: NULL hardware pointer")); 68556f157acbSml return; 68566f157acbSml } 68576f157acbSml 68586f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 68596f157acbSml "==> nxge_niu_peu_reset: flags 0x%x link timer id %d timer id %d", 68606f157acbSml hw_p->flags, nxgep->nxge_link_poll_timerid, 68616f157acbSml nxgep->nxge_timerid)); 68626f157acbSml 68636f157acbSml MUTEX_ENTER(&hw_p->nxge_cfg_lock); 68646f157acbSml /* 68656f157acbSml * Make sure other instances from the same hardware 68666f157acbSml * stop sending PIO and in quiescent state. 68676f157acbSml */ 68686f157acbSml for (i = 0; i < NXGE_MAX_PORTS; i++) { 68696f157acbSml fnxgep = hw_p->nxge_p[i]; 68706f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 68716f157acbSml "==> nxge_niu_peu_reset: checking entry %d " 68726f157acbSml "nxgep $%p", i, fnxgep)); 68736f157acbSml #ifdef NXGE_DEBUG 68746f157acbSml if (fnxgep) { 68756f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 68766f157acbSml "==> nxge_niu_peu_reset: entry %d (function %d) " 68776f157acbSml "link timer id %d hw timer id %d", 68786f157acbSml i, fnxgep->function_num, 68796f157acbSml fnxgep->nxge_link_poll_timerid, 68806f157acbSml fnxgep->nxge_timerid)); 68816f157acbSml } 68826f157acbSml #endif 68836f157acbSml if (fnxgep && fnxgep != nxgep && 68846f157acbSml (fnxgep->nxge_timerid || fnxgep->nxge_link_poll_timerid)) { 68856f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 68866f157acbSml "==> nxge_niu_peu_reset: checking $%p " 68876f157acbSml "(function %d) timer ids", 68886f157acbSml fnxgep, fnxgep->function_num)); 68896f157acbSml for (j = 0; j < NXGE_WAIT_QUITE_RETRY; j++) { 68906f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 68916f157acbSml "==> nxge_niu_peu_reset: waiting")); 68926f157acbSml NXGE_DELAY(NXGE_WAIT_QUITE_TIME); 68936f157acbSml if (!fnxgep->nxge_timerid && 68946f157acbSml !fnxgep->nxge_link_poll_timerid) { 68956f157acbSml break; 68966f157acbSml } 68976f157acbSml } 68986f157acbSml NXGE_DELAY(NXGE_WAIT_QUITE_TIME); 68996f157acbSml if (fnxgep->nxge_timerid || 69006f157acbSml fnxgep->nxge_link_poll_timerid) { 69016f157acbSml MUTEX_EXIT(&hw_p->nxge_cfg_lock); 69026f157acbSml NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 69036f157acbSml "<== nxge_niu_peu_reset: cannot reset " 69046f157acbSml "hardware (devices are still in use)")); 69056f157acbSml return; 69066f157acbSml } 69076f157acbSml } 69086f157acbSml } 69096f157acbSml 69106f157acbSml if ((hw_p->flags & COMMON_RESET_NIU_PCI) != COMMON_RESET_NIU_PCI) { 69116f157acbSml hw_p->flags |= COMMON_RESET_NIU_PCI; 69126f157acbSml rvalue = pci_config_get32(nxgep->dev_regs->nxge_pciregh, 69136f157acbSml NXGE_PCI_PORT_LOGIC_OFFSET); 69146f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 69156f157acbSml "nxge_niu_peu_reset: read offset 0x%x (%d) " 69166f157acbSml "(data 0x%x)", 69176f157acbSml NXGE_PCI_PORT_LOGIC_OFFSET, 69186f157acbSml NXGE_PCI_PORT_LOGIC_OFFSET, 69196f157acbSml rvalue)); 69206f157acbSml 69216f157acbSml rvalue |= NXGE_PCI_RESET_ALL; 69226f157acbSml pci_config_put32(nxgep->dev_regs->nxge_pciregh, 69236f157acbSml NXGE_PCI_PORT_LOGIC_OFFSET, rvalue); 69246f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 69256f157acbSml "nxge_niu_peu_reset: RESETTING NIU: write NIU reset 0x%x", 69266f157acbSml rvalue)); 69276f157acbSml 69286f157acbSml NXGE_DELAY(NXGE_PCI_RESET_WAIT); 69296f157acbSml } 69306f157acbSml 69316f157acbSml MUTEX_EXIT(&hw_p->nxge_cfg_lock); 69326f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_niu_peu_reset")); 69336f157acbSml } 6934d6d3405fSml 6935d6d3405fSml static void 6936d6d3405fSml nxge_set_pci_replay_timeout(p_nxge_t nxgep) 6937d6d3405fSml { 6938da14cebeSEric Cheng p_dev_regs_t dev_regs; 6939d6d3405fSml uint32_t value; 6940d6d3405fSml 6941d6d3405fSml NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_set_pci_replay_timeout")); 6942d6d3405fSml 6943d6d3405fSml if (!nxge_set_replay_timer) { 6944d6d3405fSml NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6945d6d3405fSml "==> nxge_set_pci_replay_timeout: will not change " 6946d6d3405fSml "the timeout")); 6947d6d3405fSml return; 6948d6d3405fSml } 6949d6d3405fSml 6950d6d3405fSml dev_regs = nxgep->dev_regs; 6951d6d3405fSml NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6952d6d3405fSml "==> nxge_set_pci_replay_timeout: dev_regs 0x%p pcireg 0x%p", 6953d6d3405fSml dev_regs, dev_regs->nxge_pciregh)); 6954d6d3405fSml 6955d6d3405fSml if (dev_regs == NULL || (dev_regs->nxge_pciregh == NULL)) { 6956f720bc57Syc NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6957d6d3405fSml "==> nxge_set_pci_replay_timeout: NULL dev_regs $%p or " 6958d6d3405fSml "no PCI handle", 6959d6d3405fSml dev_regs)); 6960d6d3405fSml return; 6961d6d3405fSml } 6962d6d3405fSml value = (pci_config_get32(dev_regs->nxge_pciregh, 6963d6d3405fSml PCI_REPLAY_TIMEOUT_CFG_OFFSET) | 6964d6d3405fSml (nxge_replay_timeout << PCI_REPLAY_TIMEOUT_SHIFT)); 6965d6d3405fSml 6966d6d3405fSml NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6967d6d3405fSml "nxge_set_pci_replay_timeout: replay timeout value before set 0x%x " 6968d6d3405fSml "(timeout value to set 0x%x at offset 0x%x) value 0x%x", 6969d6d3405fSml pci_config_get32(dev_regs->nxge_pciregh, 6970d6d3405fSml PCI_REPLAY_TIMEOUT_CFG_OFFSET), nxge_replay_timeout, 6971d6d3405fSml PCI_REPLAY_TIMEOUT_CFG_OFFSET, value)); 6972d6d3405fSml 6973d6d3405fSml pci_config_put32(dev_regs->nxge_pciregh, PCI_REPLAY_TIMEOUT_CFG_OFFSET, 6974d6d3405fSml value); 6975d6d3405fSml 6976d6d3405fSml NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6977d6d3405fSml "nxge_set_pci_replay_timeout: replay timeout value after set 0x%x", 6978d6d3405fSml pci_config_get32(dev_regs->nxge_pciregh, 6979d6d3405fSml PCI_REPLAY_TIMEOUT_CFG_OFFSET))); 6980d6d3405fSml 6981d6d3405fSml NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_set_pci_replay_timeout")); 6982d6d3405fSml } 698319397407SSherry Moore 698419397407SSherry Moore /* 698519397407SSherry Moore * quiesce(9E) entry point. 698619397407SSherry Moore * 698719397407SSherry Moore * This function is called when the system is single-threaded at high 698819397407SSherry Moore * PIL with preemption disabled. Therefore, this function must not be 698919397407SSherry Moore * blocked. 699019397407SSherry Moore * 699119397407SSherry Moore * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 699219397407SSherry Moore * DDI_FAILURE indicates an error condition and should almost never happen. 699319397407SSherry Moore */ 699419397407SSherry Moore static int 699519397407SSherry Moore nxge_quiesce(dev_info_t *dip) 699619397407SSherry Moore { 699719397407SSherry Moore int instance = ddi_get_instance(dip); 699819397407SSherry Moore p_nxge_t nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance); 699919397407SSherry Moore 700019397407SSherry Moore if (nxgep == NULL) 700119397407SSherry Moore return (DDI_FAILURE); 700219397407SSherry Moore 700319397407SSherry Moore /* Turn off debugging */ 700419397407SSherry Moore nxge_debug_level = NO_DEBUG; 700519397407SSherry Moore nxgep->nxge_debug_level = NO_DEBUG; 700619397407SSherry Moore npi_debug_level = NO_DEBUG; 700719397407SSherry Moore 700819397407SSherry Moore /* 700919397407SSherry Moore * Stop link monitor only when linkchkmod is interrupt based 701019397407SSherry Moore */ 701119397407SSherry Moore if (nxgep->mac.linkchkmode == LINKCHK_INTR) { 701219397407SSherry Moore (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 701319397407SSherry Moore } 701419397407SSherry Moore 701519397407SSherry Moore (void) nxge_intr_hw_disable(nxgep); 701619397407SSherry Moore 701719397407SSherry Moore /* 701819397407SSherry Moore * Reset the receive MAC side. 701919397407SSherry Moore */ 702019397407SSherry Moore (void) nxge_rx_mac_disable(nxgep); 702119397407SSherry Moore 702219397407SSherry Moore /* Disable and soft reset the IPP */ 702319397407SSherry Moore if (!isLDOMguest(nxgep)) 702419397407SSherry Moore (void) nxge_ipp_disable(nxgep); 702519397407SSherry Moore 702619397407SSherry Moore /* 702719397407SSherry Moore * Reset the transmit/receive DMA side. 702819397407SSherry Moore */ 702919397407SSherry Moore (void) nxge_txdma_hw_mode(nxgep, NXGE_DMA_STOP); 703019397407SSherry Moore (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_STOP); 703119397407SSherry Moore 703219397407SSherry Moore /* 703319397407SSherry Moore * Reset the transmit MAC side. 703419397407SSherry Moore */ 703519397407SSherry Moore (void) nxge_tx_mac_disable(nxgep); 703619397407SSherry Moore 703719397407SSherry Moore return (DDI_SUCCESS); 703819397407SSherry Moore } 7039