144961713Sgirish /* 244961713Sgirish * CDDL HEADER START 344961713Sgirish * 444961713Sgirish * The contents of this file are subject to the terms of the 544961713Sgirish * Common Development and Distribution License (the "License"). 644961713Sgirish * You may not use this file except in compliance with the License. 744961713Sgirish * 844961713Sgirish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 944961713Sgirish * or http://www.opensolaris.org/os/licensing. 1044961713Sgirish * See the License for the specific language governing permissions 1144961713Sgirish * and limitations under the License. 1244961713Sgirish * 1344961713Sgirish * When distributing Covered Code, include this CDDL HEADER in each 1444961713Sgirish * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1544961713Sgirish * If applicable, add the following below this CDDL HEADER, with the 1644961713Sgirish * fields enclosed by brackets "[]" replaced with your own identifying 1744961713Sgirish * information: Portions Copyright [yyyy] [name of copyright owner] 1844961713Sgirish * 1944961713Sgirish * CDDL HEADER END 2044961713Sgirish */ 2144961713Sgirish /* 2230ac2e7bSml * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 2344961713Sgirish * Use is subject to license terms. 2444961713Sgirish */ 2544961713Sgirish 2644961713Sgirish #pragma ident "%Z%%M% %I% %E% SMI" 2744961713Sgirish 2844961713Sgirish /* 2944961713Sgirish * SunOs MT STREAMS NIU/Neptune 10Gb Ethernet Device Driver. 3044961713Sgirish */ 3144961713Sgirish #include <sys/nxge/nxge_impl.h> 32678453a8Sspeer #include <sys/nxge/nxge_hio.h> 33678453a8Sspeer #include <sys/nxge/nxge_rxdma.h> 3414ea4bb7Ssd #include <sys/pcie.h> 3544961713Sgirish 3644961713Sgirish uint32_t nxge_use_partition = 0; /* debug partition flag */ 3744961713Sgirish uint32_t nxge_dma_obp_props_only = 1; /* use obp published props */ 3844961713Sgirish uint32_t nxge_use_rdc_intr = 1; /* debug to assign rdc intr */ 3944961713Sgirish /* 40ec090658Sml * PSARC/2007/453 MSI-X interrupt limit override 41ec090658Sml * (This PSARC case is limited to MSI-X vectors 42ec090658Sml * and SPARC platforms only). 4344961713Sgirish */ 44ec090658Sml #if defined(_BIG_ENDIAN) 45ec090658Sml uint32_t nxge_msi_enable = 2; 46ec090658Sml #else 47ec090658Sml uint32_t nxge_msi_enable = 1; 48ec090658Sml #endif 4944961713Sgirish 506f157acbSml /* 516f157acbSml * Software workaround for a Neptune (PCI-E) 526f157acbSml * hardware interrupt bug which the hardware 536f157acbSml * may generate spurious interrupts after the 546f157acbSml * device interrupt handler was removed. If this flag 556f157acbSml * is enabled, the driver will reset the 566f157acbSml * hardware when devices are being detached. 576f157acbSml */ 586f157acbSml uint32_t nxge_peu_reset_enable = 0; 596f157acbSml 60b4d05839Sml /* 61b4d05839Sml * Software workaround for the hardware 62b4d05839Sml * checksum bugs that affect packet transmission 63b4d05839Sml * and receive: 64b4d05839Sml * 65b4d05839Sml * Usage of nxge_cksum_offload: 66b4d05839Sml * 67b4d05839Sml * (1) nxge_cksum_offload = 0 (default): 68b4d05839Sml * - transmits packets: 69b4d05839Sml * TCP: uses the hardware checksum feature. 70b4d05839Sml * UDP: driver will compute the software checksum 71b4d05839Sml * based on the partial checksum computed 72b4d05839Sml * by the IP layer. 73b4d05839Sml * - receives packets 74b4d05839Sml * TCP: marks packets checksum flags based on hardware result. 75b4d05839Sml * UDP: will not mark checksum flags. 76b4d05839Sml * 77b4d05839Sml * (2) nxge_cksum_offload = 1: 78b4d05839Sml * - transmit packets: 79b4d05839Sml * TCP/UDP: uses the hardware checksum feature. 80b4d05839Sml * - receives packets 81b4d05839Sml * TCP/UDP: marks packet checksum flags based on hardware result. 82b4d05839Sml * 83b4d05839Sml * (3) nxge_cksum_offload = 2: 84b4d05839Sml * - The driver will not register its checksum capability. 85b4d05839Sml * Checksum for both TCP and UDP will be computed 86b4d05839Sml * by the stack. 87b4d05839Sml * - The software LSO is not allowed in this case. 88b4d05839Sml * 89b4d05839Sml * (4) nxge_cksum_offload > 2: 90b4d05839Sml * - Will be treated as it is set to 2 91b4d05839Sml * (stack will compute the checksum). 92b4d05839Sml * 93b4d05839Sml * (5) If the hardware bug is fixed, this workaround 94b4d05839Sml * needs to be updated accordingly to reflect 95b4d05839Sml * the new hardware revision. 96b4d05839Sml */ 97b4d05839Sml uint32_t nxge_cksum_offload = 0; 98678453a8Sspeer 9944961713Sgirish /* 10044961713Sgirish * Globals: tunable parameters (/etc/system or adb) 10144961713Sgirish * 10244961713Sgirish */ 10344961713Sgirish uint32_t nxge_rbr_size = NXGE_RBR_RBB_DEFAULT; 10444961713Sgirish uint32_t nxge_rbr_spare_size = 0; 10544961713Sgirish uint32_t nxge_rcr_size = NXGE_RCR_DEFAULT; 10644961713Sgirish uint32_t nxge_tx_ring_size = NXGE_TX_RING_DEFAULT; 107b3a0105bSspeer boolean_t nxge_no_msg = B_TRUE; /* control message display */ 10844961713Sgirish uint32_t nxge_no_link_notify = 0; /* control DL_NOTIFY */ 10944961713Sgirish uint32_t nxge_bcopy_thresh = TX_BCOPY_MAX; 11044961713Sgirish uint32_t nxge_dvma_thresh = TX_FASTDVMA_MIN; 11144961713Sgirish uint32_t nxge_dma_stream_thresh = TX_STREAM_MIN; 11244961713Sgirish uint32_t nxge_jumbo_mtu = TX_JUMBO_MTU; 11344961713Sgirish boolean_t nxge_jumbo_enable = B_FALSE; 11444961713Sgirish uint16_t nxge_rcr_timeout = NXGE_RDC_RCR_TIMEOUT; 11544961713Sgirish uint16_t nxge_rcr_threshold = NXGE_RDC_RCR_THRESHOLD; 1161f8914d5Sml nxge_tx_mode_t nxge_tx_scheme = NXGE_USE_SERIAL; 11744961713Sgirish 11830ac2e7bSml /* MAX LSO size */ 11930ac2e7bSml #define NXGE_LSO_MAXLEN 65535 12030ac2e7bSml uint32_t nxge_lso_max = NXGE_LSO_MAXLEN; 12130ac2e7bSml 12244961713Sgirish /* 12344961713Sgirish * Debugging flags: 12444961713Sgirish * nxge_no_tx_lb : transmit load balancing 12544961713Sgirish * nxge_tx_lb_policy: 0 - TCP port (default) 12644961713Sgirish * 3 - DEST MAC 12744961713Sgirish */ 12844961713Sgirish uint32_t nxge_no_tx_lb = 0; 12944961713Sgirish uint32_t nxge_tx_lb_policy = NXGE_TX_LB_TCPUDP; 13044961713Sgirish 13144961713Sgirish /* 13244961713Sgirish * Add tunable to reduce the amount of time spent in the 13344961713Sgirish * ISR doing Rx Processing. 13444961713Sgirish */ 13544961713Sgirish uint32_t nxge_max_rx_pkts = 1024; 13644961713Sgirish 13744961713Sgirish /* 13844961713Sgirish * Tunables to manage the receive buffer blocks. 13944961713Sgirish * 14044961713Sgirish * nxge_rx_threshold_hi: copy all buffers. 14144961713Sgirish * nxge_rx_bcopy_size_type: receive buffer block size type. 14244961713Sgirish * nxge_rx_threshold_lo: copy only up to tunable block size type. 14344961713Sgirish */ 14444961713Sgirish nxge_rxbuf_threshold_t nxge_rx_threshold_hi = NXGE_RX_COPY_6; 14544961713Sgirish nxge_rxbuf_type_t nxge_rx_buf_size_type = RCR_PKTBUFSZ_0; 14644961713Sgirish nxge_rxbuf_threshold_t nxge_rx_threshold_lo = NXGE_RX_COPY_3; 14744961713Sgirish 148678453a8Sspeer /* Use kmem_alloc() to allocate data buffers. */ 149b1000363Sml #if defined(_BIG_ENDIAN) 150d00f30bbSspeer uint32_t nxge_use_kmem_alloc = 1; 151678453a8Sspeer #else 152d00f30bbSspeer uint32_t nxge_use_kmem_alloc = 0; 153678453a8Sspeer #endif 154678453a8Sspeer 15544961713Sgirish rtrace_t npi_rtracebuf; 15644961713Sgirish 157d6d3405fSml /* 158d6d3405fSml * The hardware sometimes fails to allow enough time for the link partner 159d6d3405fSml * to send an acknowledgement for packets that the hardware sent to it. The 160d6d3405fSml * hardware resends the packets earlier than it should be in those instances. 161d6d3405fSml * This behavior caused some switches to acknowledge the wrong packets 162d6d3405fSml * and it triggered the fatal error. 163d6d3405fSml * This software workaround is to set the replay timer to a value 164d6d3405fSml * suggested by the hardware team. 165d6d3405fSml * 166d6d3405fSml * PCI config space replay timer register: 167d6d3405fSml * The following replay timeout value is 0xc 168d6d3405fSml * for bit 14:18. 169d6d3405fSml */ 170d6d3405fSml #define PCI_REPLAY_TIMEOUT_CFG_OFFSET 0xb8 171d6d3405fSml #define PCI_REPLAY_TIMEOUT_SHIFT 14 172d6d3405fSml 173d6d3405fSml uint32_t nxge_set_replay_timer = 1; 174d6d3405fSml uint32_t nxge_replay_timeout = 0xc; 175d6d3405fSml 176*cf020df9Sml /* 177*cf020df9Sml * The transmit serialization sometimes causes 178*cf020df9Sml * longer sleep before calling the driver transmit 179*cf020df9Sml * function as it sleeps longer than it should. 180*cf020df9Sml * The performace group suggests that a time wait tunable 181*cf020df9Sml * can be used to set the maximum wait time when needed 182*cf020df9Sml * and the default is set to 1 tick. 183*cf020df9Sml */ 184*cf020df9Sml uint32_t nxge_tx_serial_maxsleep = 1; 185*cf020df9Sml 18644961713Sgirish #if defined(sun4v) 18744961713Sgirish /* 18844961713Sgirish * Hypervisor N2/NIU services information. 18944961713Sgirish */ 19044961713Sgirish static hsvc_info_t niu_hsvc = { 19144961713Sgirish HSVC_REV_1, NULL, HSVC_GROUP_NIU, NIU_MAJOR_VER, 19244961713Sgirish NIU_MINOR_VER, "nxge" 19344961713Sgirish }; 194678453a8Sspeer 195678453a8Sspeer static int nxge_hsvc_register(p_nxge_t); 19644961713Sgirish #endif 19744961713Sgirish 19844961713Sgirish /* 19944961713Sgirish * Function Prototypes 20044961713Sgirish */ 20144961713Sgirish static int nxge_attach(dev_info_t *, ddi_attach_cmd_t); 20244961713Sgirish static int nxge_detach(dev_info_t *, ddi_detach_cmd_t); 20344961713Sgirish static void nxge_unattach(p_nxge_t); 20444961713Sgirish 20544961713Sgirish #if NXGE_PROPERTY 20644961713Sgirish static void nxge_remove_hard_properties(p_nxge_t); 20744961713Sgirish #endif 20844961713Sgirish 209678453a8Sspeer /* 210678453a8Sspeer * These two functions are required by nxge_hio.c 211678453a8Sspeer */ 212678453a8Sspeer extern int nxge_m_mmac_add(void *arg, mac_multi_addr_t *maddr); 213678453a8Sspeer extern int nxge_m_mmac_remove(void *arg, mac_addr_slot_t slot); 214678453a8Sspeer 21544961713Sgirish static nxge_status_t nxge_setup_system_dma_pages(p_nxge_t); 21644961713Sgirish 21744961713Sgirish static nxge_status_t nxge_setup_mutexes(p_nxge_t); 21844961713Sgirish static void nxge_destroy_mutexes(p_nxge_t); 21944961713Sgirish 22044961713Sgirish static nxge_status_t nxge_map_regs(p_nxge_t nxgep); 22144961713Sgirish static void nxge_unmap_regs(p_nxge_t nxgep); 22244961713Sgirish #ifdef NXGE_DEBUG 22344961713Sgirish static void nxge_test_map_regs(p_nxge_t nxgep); 22444961713Sgirish #endif 22544961713Sgirish 22644961713Sgirish static nxge_status_t nxge_add_intrs(p_nxge_t nxgep); 22744961713Sgirish static nxge_status_t nxge_add_soft_intrs(p_nxge_t nxgep); 22844961713Sgirish static void nxge_remove_intrs(p_nxge_t nxgep); 22944961713Sgirish static void nxge_remove_soft_intrs(p_nxge_t nxgep); 23044961713Sgirish 23144961713Sgirish static nxge_status_t nxge_add_intrs_adv(p_nxge_t nxgep); 23244961713Sgirish static nxge_status_t nxge_add_intrs_adv_type(p_nxge_t, uint32_t); 23344961713Sgirish static nxge_status_t nxge_add_intrs_adv_type_fix(p_nxge_t, uint32_t); 23444961713Sgirish static void nxge_intrs_enable(p_nxge_t nxgep); 23544961713Sgirish static void nxge_intrs_disable(p_nxge_t nxgep); 23644961713Sgirish 23744961713Sgirish static void nxge_suspend(p_nxge_t); 23844961713Sgirish static nxge_status_t nxge_resume(p_nxge_t); 23944961713Sgirish 24044961713Sgirish static nxge_status_t nxge_setup_dev(p_nxge_t); 24144961713Sgirish static void nxge_destroy_dev(p_nxge_t); 24244961713Sgirish 24344961713Sgirish static nxge_status_t nxge_alloc_mem_pool(p_nxge_t); 24444961713Sgirish static void nxge_free_mem_pool(p_nxge_t); 24544961713Sgirish 246678453a8Sspeer nxge_status_t nxge_alloc_rx_mem_pool(p_nxge_t); 24744961713Sgirish static void nxge_free_rx_mem_pool(p_nxge_t); 24844961713Sgirish 249678453a8Sspeer nxge_status_t nxge_alloc_tx_mem_pool(p_nxge_t); 25044961713Sgirish static void nxge_free_tx_mem_pool(p_nxge_t); 25144961713Sgirish 25244961713Sgirish static nxge_status_t nxge_dma_mem_alloc(p_nxge_t, dma_method_t, 25344961713Sgirish struct ddi_dma_attr *, 25444961713Sgirish size_t, ddi_device_acc_attr_t *, uint_t, 25544961713Sgirish p_nxge_dma_common_t); 25644961713Sgirish 25744961713Sgirish static void nxge_dma_mem_free(p_nxge_dma_common_t); 258678453a8Sspeer static void nxge_dma_free_rx_data_buf(p_nxge_dma_common_t); 25944961713Sgirish 26044961713Sgirish static nxge_status_t nxge_alloc_rx_buf_dma(p_nxge_t, uint16_t, 26144961713Sgirish p_nxge_dma_common_t *, size_t, size_t, uint32_t *); 26244961713Sgirish static void nxge_free_rx_buf_dma(p_nxge_t, p_nxge_dma_common_t, uint32_t); 26344961713Sgirish 26444961713Sgirish static nxge_status_t nxge_alloc_rx_cntl_dma(p_nxge_t, uint16_t, 26544961713Sgirish p_nxge_dma_common_t *, size_t); 26644961713Sgirish static void nxge_free_rx_cntl_dma(p_nxge_t, p_nxge_dma_common_t); 26744961713Sgirish 268678453a8Sspeer extern nxge_status_t nxge_alloc_tx_buf_dma(p_nxge_t, uint16_t, 26944961713Sgirish p_nxge_dma_common_t *, size_t, size_t, uint32_t *); 27044961713Sgirish static void nxge_free_tx_buf_dma(p_nxge_t, p_nxge_dma_common_t, uint32_t); 27144961713Sgirish 272678453a8Sspeer extern nxge_status_t nxge_alloc_tx_cntl_dma(p_nxge_t, uint16_t, 27344961713Sgirish p_nxge_dma_common_t *, 27444961713Sgirish size_t); 27544961713Sgirish static void nxge_free_tx_cntl_dma(p_nxge_t, p_nxge_dma_common_t); 27644961713Sgirish 27744961713Sgirish static int nxge_init_common_dev(p_nxge_t); 27844961713Sgirish static void nxge_uninit_common_dev(p_nxge_t); 2794045d941Ssowmini extern int nxge_param_set_mac(p_nxge_t, queue_t *, mblk_t *, 2804045d941Ssowmini char *, caddr_t); 28144961713Sgirish 28244961713Sgirish /* 28344961713Sgirish * The next declarations are for the GLDv3 interface. 28444961713Sgirish */ 28544961713Sgirish static int nxge_m_start(void *); 28644961713Sgirish static void nxge_m_stop(void *); 28744961713Sgirish static int nxge_m_unicst(void *, const uint8_t *); 28844961713Sgirish static int nxge_m_multicst(void *, boolean_t, const uint8_t *); 28944961713Sgirish static int nxge_m_promisc(void *, boolean_t); 29044961713Sgirish static void nxge_m_ioctl(void *, queue_t *, mblk_t *); 29144961713Sgirish static void nxge_m_resources(void *); 29244961713Sgirish mblk_t *nxge_m_tx(void *arg, mblk_t *); 29344961713Sgirish static nxge_status_t nxge_mac_register(p_nxge_t); 29458324dfcSspeer static int nxge_altmac_set(p_nxge_t nxgep, uint8_t *mac_addr, 29558324dfcSspeer mac_addr_slot_t slot); 296678453a8Sspeer void nxge_mmac_kstat_update(p_nxge_t nxgep, mac_addr_slot_t slot, 29758324dfcSspeer boolean_t factory); 29858324dfcSspeer static int nxge_m_mmac_reserve(void *arg, mac_multi_addr_t *maddr); 29958324dfcSspeer static int nxge_m_mmac_modify(void *arg, mac_multi_addr_t *maddr); 30058324dfcSspeer static int nxge_m_mmac_get(void *arg, mac_multi_addr_t *maddr); 3011bd6825cSml static boolean_t nxge_m_getcapab(void *, mac_capab_t, void *); 3021bd6825cSml static int nxge_m_setprop(void *, const char *, mac_prop_id_t, 3031bd6825cSml uint_t, const void *); 3041bd6825cSml static int nxge_m_getprop(void *, const char *, mac_prop_id_t, 3054045d941Ssowmini uint_t, uint_t, void *); 3061bd6825cSml static int nxge_set_priv_prop(nxge_t *, const char *, uint_t, 3071bd6825cSml const void *); 3084045d941Ssowmini static int nxge_get_priv_prop(nxge_t *, const char *, uint_t, uint_t, 3091bd6825cSml void *); 3104045d941Ssowmini static int nxge_get_def_val(nxge_t *, mac_prop_id_t, uint_t, void *); 3114045d941Ssowmini 3126f157acbSml static void nxge_niu_peu_reset(p_nxge_t nxgep); 313d6d3405fSml static void nxge_set_pci_replay_timeout(nxge_t *); 3144045d941Ssowmini 3154045d941Ssowmini mac_priv_prop_t nxge_priv_props[] = { 3164045d941Ssowmini {"_adv_10gfdx_cap", MAC_PROP_PERM_RW}, 3174045d941Ssowmini {"_adv_pause_cap", MAC_PROP_PERM_RW}, 3184045d941Ssowmini {"_function_number", MAC_PROP_PERM_READ}, 3194045d941Ssowmini {"_fw_version", MAC_PROP_PERM_READ}, 3204045d941Ssowmini {"_port_mode", MAC_PROP_PERM_READ}, 3214045d941Ssowmini {"_hot_swap_phy", MAC_PROP_PERM_READ}, 3224045d941Ssowmini {"_accept_jumbo", MAC_PROP_PERM_RW}, 3234045d941Ssowmini {"_rxdma_intr_time", MAC_PROP_PERM_RW}, 3244045d941Ssowmini {"_rxdma_intr_pkts", MAC_PROP_PERM_RW}, 3254045d941Ssowmini {"_class_opt_ipv4_tcp", MAC_PROP_PERM_RW}, 3264045d941Ssowmini {"_class_opt_ipv4_udp", MAC_PROP_PERM_RW}, 3274045d941Ssowmini {"_class_opt_ipv4_ah", MAC_PROP_PERM_RW}, 3284045d941Ssowmini {"_class_opt_ipv4_sctp", MAC_PROP_PERM_RW}, 3294045d941Ssowmini {"_class_opt_ipv6_tcp", MAC_PROP_PERM_RW}, 3304045d941Ssowmini {"_class_opt_ipv6_udp", MAC_PROP_PERM_RW}, 3314045d941Ssowmini {"_class_opt_ipv6_ah", MAC_PROP_PERM_RW}, 3324045d941Ssowmini {"_class_opt_ipv6_sctp", MAC_PROP_PERM_RW}, 3334045d941Ssowmini {"_soft_lso_enable", MAC_PROP_PERM_RW} 3344045d941Ssowmini }; 3354045d941Ssowmini 3364045d941Ssowmini #define NXGE_MAX_PRIV_PROPS \ 3374045d941Ssowmini (sizeof (nxge_priv_props)/sizeof (mac_priv_prop_t)) 3381bd6825cSml 3391bd6825cSml #define NXGE_M_CALLBACK_FLAGS\ 3401bd6825cSml (MC_RESOURCES | MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP) 3411bd6825cSml 34244961713Sgirish 34344961713Sgirish #define NXGE_NEPTUNE_MAGIC 0x4E584745UL 34444961713Sgirish #define MAX_DUMP_SZ 256 34544961713Sgirish 3461bd6825cSml #define NXGE_M_CALLBACK_FLAGS \ 3471bd6825cSml (MC_RESOURCES | MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP) 34844961713Sgirish 349678453a8Sspeer mac_callbacks_t nxge_m_callbacks = { 35044961713Sgirish NXGE_M_CALLBACK_FLAGS, 35144961713Sgirish nxge_m_stat, 35244961713Sgirish nxge_m_start, 35344961713Sgirish nxge_m_stop, 35444961713Sgirish nxge_m_promisc, 35544961713Sgirish nxge_m_multicst, 35644961713Sgirish nxge_m_unicst, 35744961713Sgirish nxge_m_tx, 35844961713Sgirish nxge_m_resources, 35944961713Sgirish nxge_m_ioctl, 3601bd6825cSml nxge_m_getcapab, 3611bd6825cSml NULL, 3621bd6825cSml NULL, 3631bd6825cSml nxge_m_setprop, 3641bd6825cSml nxge_m_getprop 36544961713Sgirish }; 36644961713Sgirish 36744961713Sgirish void 36844961713Sgirish nxge_err_inject(p_nxge_t, queue_t *, mblk_t *); 36944961713Sgirish 370ec090658Sml /* PSARC/2007/453 MSI-X interrupt limit override. */ 371ec090658Sml #define NXGE_MSIX_REQUEST_10G 8 372ec090658Sml #define NXGE_MSIX_REQUEST_1G 2 373ec090658Sml static int nxge_create_msi_property(p_nxge_t); 374ec090658Sml 37544961713Sgirish /* 37644961713Sgirish * These global variables control the message 37744961713Sgirish * output. 37844961713Sgirish */ 37944961713Sgirish out_dbgmsg_t nxge_dbgmsg_out = DBG_CONSOLE | STR_LOG; 380678453a8Sspeer uint64_t nxge_debug_level; 38144961713Sgirish 38244961713Sgirish /* 38344961713Sgirish * This list contains the instance structures for the Neptune 38444961713Sgirish * devices present in the system. The lock exists to guarantee 38544961713Sgirish * mutually exclusive access to the list. 38644961713Sgirish */ 38744961713Sgirish void *nxge_list = NULL; 38844961713Sgirish 38944961713Sgirish void *nxge_hw_list = NULL; 39044961713Sgirish nxge_os_mutex_t nxge_common_lock; 39144961713Sgirish 39244961713Sgirish extern uint64_t npi_debug_level; 39344961713Sgirish 39444961713Sgirish extern nxge_status_t nxge_ldgv_init(p_nxge_t, int *, int *); 39544961713Sgirish extern nxge_status_t nxge_ldgv_init_n2(p_nxge_t, int *, int *); 39644961713Sgirish extern nxge_status_t nxge_ldgv_uninit(p_nxge_t); 39744961713Sgirish extern nxge_status_t nxge_intr_ldgv_init(p_nxge_t); 39844961713Sgirish extern void nxge_fm_init(p_nxge_t, 39944961713Sgirish ddi_device_acc_attr_t *, 40044961713Sgirish ddi_device_acc_attr_t *, 40144961713Sgirish ddi_dma_attr_t *); 40244961713Sgirish extern void nxge_fm_fini(p_nxge_t); 40358324dfcSspeer extern npi_status_t npi_mac_altaddr_disable(npi_handle_t, uint8_t, uint8_t); 40444961713Sgirish 40544961713Sgirish /* 40644961713Sgirish * Count used to maintain the number of buffers being used 40744961713Sgirish * by Neptune instances and loaned up to the upper layers. 40844961713Sgirish */ 40944961713Sgirish uint32_t nxge_mblks_pending = 0; 41044961713Sgirish 41144961713Sgirish /* 41244961713Sgirish * Device register access attributes for PIO. 41344961713Sgirish */ 41444961713Sgirish static ddi_device_acc_attr_t nxge_dev_reg_acc_attr = { 41544961713Sgirish DDI_DEVICE_ATTR_V0, 41644961713Sgirish DDI_STRUCTURE_LE_ACC, 41744961713Sgirish DDI_STRICTORDER_ACC, 41844961713Sgirish }; 41944961713Sgirish 42044961713Sgirish /* 42144961713Sgirish * Device descriptor access attributes for DMA. 42244961713Sgirish */ 42344961713Sgirish static ddi_device_acc_attr_t nxge_dev_desc_dma_acc_attr = { 42444961713Sgirish DDI_DEVICE_ATTR_V0, 42544961713Sgirish DDI_STRUCTURE_LE_ACC, 42644961713Sgirish DDI_STRICTORDER_ACC 42744961713Sgirish }; 42844961713Sgirish 42944961713Sgirish /* 43044961713Sgirish * Device buffer access attributes for DMA. 43144961713Sgirish */ 43244961713Sgirish static ddi_device_acc_attr_t nxge_dev_buf_dma_acc_attr = { 43344961713Sgirish DDI_DEVICE_ATTR_V0, 43444961713Sgirish DDI_STRUCTURE_BE_ACC, 43544961713Sgirish DDI_STRICTORDER_ACC 43644961713Sgirish }; 43744961713Sgirish 43844961713Sgirish ddi_dma_attr_t nxge_desc_dma_attr = { 43944961713Sgirish DMA_ATTR_V0, /* version number. */ 44044961713Sgirish 0, /* low address */ 44144961713Sgirish 0xffffffffffffffff, /* high address */ 44244961713Sgirish 0xffffffffffffffff, /* address counter max */ 44344961713Sgirish #ifndef NIU_PA_WORKAROUND 44444961713Sgirish 0x100000, /* alignment */ 44544961713Sgirish #else 44644961713Sgirish 0x2000, 44744961713Sgirish #endif 44844961713Sgirish 0xfc00fc, /* dlim_burstsizes */ 44944961713Sgirish 0x1, /* minimum transfer size */ 45044961713Sgirish 0xffffffffffffffff, /* maximum transfer size */ 45144961713Sgirish 0xffffffffffffffff, /* maximum segment size */ 45244961713Sgirish 1, /* scatter/gather list length */ 45344961713Sgirish (unsigned int) 1, /* granularity */ 45444961713Sgirish 0 /* attribute flags */ 45544961713Sgirish }; 45644961713Sgirish 45744961713Sgirish ddi_dma_attr_t nxge_tx_dma_attr = { 45844961713Sgirish DMA_ATTR_V0, /* version number. */ 45944961713Sgirish 0, /* low address */ 46044961713Sgirish 0xffffffffffffffff, /* high address */ 46144961713Sgirish 0xffffffffffffffff, /* address counter max */ 46244961713Sgirish #if defined(_BIG_ENDIAN) 46344961713Sgirish 0x2000, /* alignment */ 46444961713Sgirish #else 46544961713Sgirish 0x1000, /* alignment */ 46644961713Sgirish #endif 46744961713Sgirish 0xfc00fc, /* dlim_burstsizes */ 46844961713Sgirish 0x1, /* minimum transfer size */ 46944961713Sgirish 0xffffffffffffffff, /* maximum transfer size */ 47044961713Sgirish 0xffffffffffffffff, /* maximum segment size */ 47144961713Sgirish 5, /* scatter/gather list length */ 47244961713Sgirish (unsigned int) 1, /* granularity */ 47344961713Sgirish 0 /* attribute flags */ 47444961713Sgirish }; 47544961713Sgirish 47644961713Sgirish ddi_dma_attr_t nxge_rx_dma_attr = { 47744961713Sgirish DMA_ATTR_V0, /* version number. */ 47844961713Sgirish 0, /* low address */ 47944961713Sgirish 0xffffffffffffffff, /* high address */ 48044961713Sgirish 0xffffffffffffffff, /* address counter max */ 48144961713Sgirish 0x2000, /* alignment */ 48244961713Sgirish 0xfc00fc, /* dlim_burstsizes */ 48344961713Sgirish 0x1, /* minimum transfer size */ 48444961713Sgirish 0xffffffffffffffff, /* maximum transfer size */ 48544961713Sgirish 0xffffffffffffffff, /* maximum segment size */ 48644961713Sgirish 1, /* scatter/gather list length */ 48744961713Sgirish (unsigned int) 1, /* granularity */ 4880e2bd521Ssbehera DDI_DMA_RELAXED_ORDERING /* attribute flags */ 48944961713Sgirish }; 49044961713Sgirish 49144961713Sgirish ddi_dma_lim_t nxge_dma_limits = { 49244961713Sgirish (uint_t)0, /* dlim_addr_lo */ 49344961713Sgirish (uint_t)0xffffffff, /* dlim_addr_hi */ 49444961713Sgirish (uint_t)0xffffffff, /* dlim_cntr_max */ 49544961713Sgirish (uint_t)0xfc00fc, /* dlim_burstsizes for 32 and 64 bit xfers */ 49644961713Sgirish 0x1, /* dlim_minxfer */ 49744961713Sgirish 1024 /* dlim_speed */ 49844961713Sgirish }; 49944961713Sgirish 50044961713Sgirish dma_method_t nxge_force_dma = DVMA; 50144961713Sgirish 50244961713Sgirish /* 50344961713Sgirish * dma chunk sizes. 50444961713Sgirish * 50544961713Sgirish * Try to allocate the largest possible size 50644961713Sgirish * so that fewer number of dma chunks would be managed 50744961713Sgirish */ 50844961713Sgirish #ifdef NIU_PA_WORKAROUND 50944961713Sgirish size_t alloc_sizes [] = {0x2000}; 51044961713Sgirish #else 51144961713Sgirish size_t alloc_sizes [] = {0x1000, 0x2000, 0x4000, 0x8000, 51244961713Sgirish 0x10000, 0x20000, 0x40000, 0x80000, 51330ac2e7bSml 0x100000, 0x200000, 0x400000, 0x800000, 51430ac2e7bSml 0x1000000, 0x2000000, 0x4000000}; 51544961713Sgirish #endif 51644961713Sgirish 51744961713Sgirish /* 51844961713Sgirish * Translate "dev_t" to a pointer to the associated "dev_info_t". 51944961713Sgirish */ 52044961713Sgirish 521678453a8Sspeer extern void nxge_get_environs(nxge_t *); 522678453a8Sspeer 52344961713Sgirish static int 52444961713Sgirish nxge_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 52544961713Sgirish { 52644961713Sgirish p_nxge_t nxgep = NULL; 52744961713Sgirish int instance; 52844961713Sgirish int status = DDI_SUCCESS; 52944961713Sgirish uint8_t portn; 53058324dfcSspeer nxge_mmac_t *mmac_info; 53144961713Sgirish 53244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_attach")); 53344961713Sgirish 53444961713Sgirish /* 53544961713Sgirish * Get the device instance since we'll need to setup 53644961713Sgirish * or retrieve a soft state for this instance. 53744961713Sgirish */ 53844961713Sgirish instance = ddi_get_instance(dip); 53944961713Sgirish 54044961713Sgirish switch (cmd) { 54144961713Sgirish case DDI_ATTACH: 54244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_ATTACH")); 54344961713Sgirish break; 54444961713Sgirish 54544961713Sgirish case DDI_RESUME: 54644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_RESUME")); 54744961713Sgirish nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance); 54844961713Sgirish if (nxgep == NULL) { 54944961713Sgirish status = DDI_FAILURE; 55044961713Sgirish break; 55144961713Sgirish } 55244961713Sgirish if (nxgep->dip != dip) { 55344961713Sgirish status = DDI_FAILURE; 55444961713Sgirish break; 55544961713Sgirish } 55644961713Sgirish if (nxgep->suspended == DDI_PM_SUSPEND) { 55744961713Sgirish status = ddi_dev_is_needed(nxgep->dip, 0, 1); 55844961713Sgirish } else { 55956d930aeSspeer status = nxge_resume(nxgep); 56044961713Sgirish } 56144961713Sgirish goto nxge_attach_exit; 56244961713Sgirish 56344961713Sgirish case DDI_PM_RESUME: 56444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_PM_RESUME")); 56544961713Sgirish nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance); 56644961713Sgirish if (nxgep == NULL) { 56744961713Sgirish status = DDI_FAILURE; 56844961713Sgirish break; 56944961713Sgirish } 57044961713Sgirish if (nxgep->dip != dip) { 57144961713Sgirish status = DDI_FAILURE; 57244961713Sgirish break; 57344961713Sgirish } 57456d930aeSspeer status = nxge_resume(nxgep); 57544961713Sgirish goto nxge_attach_exit; 57644961713Sgirish 57744961713Sgirish default: 57844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing unknown")); 57944961713Sgirish status = DDI_FAILURE; 58044961713Sgirish goto nxge_attach_exit; 58144961713Sgirish } 58244961713Sgirish 58344961713Sgirish 58444961713Sgirish if (ddi_soft_state_zalloc(nxge_list, instance) == DDI_FAILURE) { 58544961713Sgirish status = DDI_FAILURE; 58644961713Sgirish goto nxge_attach_exit; 58744961713Sgirish } 58844961713Sgirish 58944961713Sgirish nxgep = ddi_get_soft_state(nxge_list, instance); 59044961713Sgirish if (nxgep == NULL) { 5912e59129aSraghus status = NXGE_ERROR; 5922e59129aSraghus goto nxge_attach_fail2; 59344961713Sgirish } 59444961713Sgirish 59598ecde52Stm nxgep->nxge_magic = NXGE_MAGIC; 59698ecde52Stm 59744961713Sgirish nxgep->drv_state = 0; 59844961713Sgirish nxgep->dip = dip; 59944961713Sgirish nxgep->instance = instance; 60044961713Sgirish nxgep->p_dip = ddi_get_parent(dip); 60144961713Sgirish nxgep->nxge_debug_level = nxge_debug_level; 60244961713Sgirish npi_debug_level = nxge_debug_level; 60344961713Sgirish 604678453a8Sspeer /* Are we a guest running in a Hybrid I/O environment? */ 605678453a8Sspeer nxge_get_environs(nxgep); 60644961713Sgirish 60744961713Sgirish status = nxge_map_regs(nxgep); 608678453a8Sspeer 60944961713Sgirish if (status != NXGE_OK) { 61044961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_map_regs failed")); 6112e59129aSraghus goto nxge_attach_fail3; 61244961713Sgirish } 61344961713Sgirish 614678453a8Sspeer nxge_fm_init(nxgep, &nxge_dev_reg_acc_attr, 615678453a8Sspeer &nxge_dev_desc_dma_acc_attr, 616678453a8Sspeer &nxge_rx_dma_attr); 617678453a8Sspeer 618678453a8Sspeer /* Create & initialize the per-Neptune data structure */ 619678453a8Sspeer /* (even if we're a guest). */ 62044961713Sgirish status = nxge_init_common_dev(nxgep); 62144961713Sgirish if (status != NXGE_OK) { 62244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6234045d941Ssowmini "nxge_init_common_dev failed")); 6242e59129aSraghus goto nxge_attach_fail4; 62544961713Sgirish } 62644961713Sgirish 627d6d3405fSml /* 628d6d3405fSml * Software workaround: set the replay timer. 629d6d3405fSml */ 630d6d3405fSml if (nxgep->niu_type != N2_NIU) { 631d6d3405fSml nxge_set_pci_replay_timeout(nxgep); 632d6d3405fSml } 633d6d3405fSml 634678453a8Sspeer #if defined(sun4v) 635678453a8Sspeer /* This is required by nxge_hio_init(), which follows. */ 636678453a8Sspeer if ((status = nxge_hsvc_register(nxgep)) != DDI_SUCCESS) 637678453a8Sspeer goto nxge_attach_fail; 638678453a8Sspeer #endif 639678453a8Sspeer 640678453a8Sspeer if ((status = nxge_hio_init(nxgep)) != NXGE_OK) { 641678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6424045d941Ssowmini "nxge_hio_init failed")); 643678453a8Sspeer goto nxge_attach_fail4; 644678453a8Sspeer } 645678453a8Sspeer 64659ac0c16Sdavemq if (nxgep->niu_type == NEPTUNE_2_10GF) { 64759ac0c16Sdavemq if (nxgep->function_num > 1) { 6484202ea4bSsbehera NXGE_DEBUG_MSG((nxgep, DDI_CTL, "Unsupported" 64959ac0c16Sdavemq " function %d. Only functions 0 and 1 are " 65059ac0c16Sdavemq "supported for this card.", nxgep->function_num)); 65159ac0c16Sdavemq status = NXGE_ERROR; 6522e59129aSraghus goto nxge_attach_fail4; 65359ac0c16Sdavemq } 65459ac0c16Sdavemq } 65559ac0c16Sdavemq 656678453a8Sspeer if (isLDOMguest(nxgep)) { 657678453a8Sspeer /* 658678453a8Sspeer * Use the function number here. 659678453a8Sspeer */ 660678453a8Sspeer nxgep->mac.portnum = nxgep->function_num; 661678453a8Sspeer nxgep->mac.porttype = PORT_TYPE_LOGICAL; 662678453a8Sspeer 663678453a8Sspeer /* XXX We'll set the MAC address counts to 1 for now. */ 664678453a8Sspeer mmac_info = &nxgep->nxge_mmac_info; 665678453a8Sspeer mmac_info->num_mmac = 1; 666678453a8Sspeer mmac_info->naddrfree = 1; 66758324dfcSspeer } else { 668678453a8Sspeer portn = NXGE_GET_PORT_NUM(nxgep->function_num); 669678453a8Sspeer nxgep->mac.portnum = portn; 670678453a8Sspeer if ((portn == 0) || (portn == 1)) 671678453a8Sspeer nxgep->mac.porttype = PORT_TYPE_XMAC; 672678453a8Sspeer else 673678453a8Sspeer nxgep->mac.porttype = PORT_TYPE_BMAC; 674678453a8Sspeer /* 675678453a8Sspeer * Neptune has 4 ports, the first 2 ports use XMAC (10G MAC) 676678453a8Sspeer * internally, the rest 2 ports use BMAC (1G "Big" MAC). 677678453a8Sspeer * The two types of MACs have different characterizations. 678678453a8Sspeer */ 679678453a8Sspeer mmac_info = &nxgep->nxge_mmac_info; 680678453a8Sspeer if (nxgep->function_num < 2) { 681678453a8Sspeer mmac_info->num_mmac = XMAC_MAX_ALT_ADDR_ENTRY; 682678453a8Sspeer mmac_info->naddrfree = XMAC_MAX_ALT_ADDR_ENTRY; 683678453a8Sspeer } else { 684678453a8Sspeer mmac_info->num_mmac = BMAC_MAX_ALT_ADDR_ENTRY; 685678453a8Sspeer mmac_info->naddrfree = BMAC_MAX_ALT_ADDR_ENTRY; 686678453a8Sspeer } 68758324dfcSspeer } 68844961713Sgirish /* 68944961713Sgirish * Setup the Ndd parameters for the this instance. 69044961713Sgirish */ 69144961713Sgirish nxge_init_param(nxgep); 69244961713Sgirish 69344961713Sgirish /* 69444961713Sgirish * Setup Register Tracing Buffer. 69544961713Sgirish */ 69644961713Sgirish npi_rtrace_buf_init((rtrace_t *)&npi_rtracebuf); 69744961713Sgirish 69844961713Sgirish /* init stats ptr */ 69944961713Sgirish nxge_init_statsp(nxgep); 70056d930aeSspeer 7012e59129aSraghus /* 702678453a8Sspeer * Copy the vpd info from eeprom to a local data 703678453a8Sspeer * structure, and then check its validity. 7042e59129aSraghus */ 705678453a8Sspeer if (!isLDOMguest(nxgep)) { 706678453a8Sspeer int *regp; 707678453a8Sspeer uint_t reglen; 708678453a8Sspeer int rv; 70956d930aeSspeer 710678453a8Sspeer nxge_vpd_info_get(nxgep); 71144961713Sgirish 712678453a8Sspeer /* Find the NIU config handle. */ 713678453a8Sspeer rv = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, 714678453a8Sspeer ddi_get_parent(nxgep->dip), DDI_PROP_DONTPASS, 715678453a8Sspeer "reg", ®p, ®len); 716678453a8Sspeer 717678453a8Sspeer if (rv != DDI_PROP_SUCCESS) { 718678453a8Sspeer goto nxge_attach_fail5; 719678453a8Sspeer } 720678453a8Sspeer /* 721678453a8Sspeer * The address_hi, that is the first int, in the reg 722678453a8Sspeer * property consists of config handle, but need to remove 723678453a8Sspeer * the bits 28-31 which are OBP specific info. 724678453a8Sspeer */ 725678453a8Sspeer nxgep->niu_cfg_hdl = (*regp) & 0xFFFFFFF; 726678453a8Sspeer ddi_prop_free(regp); 72744961713Sgirish } 72844961713Sgirish 729678453a8Sspeer if (isLDOMguest(nxgep)) { 730678453a8Sspeer uchar_t *prop_val; 731678453a8Sspeer uint_t prop_len; 73244961713Sgirish 733678453a8Sspeer extern void nxge_get_logical_props(p_nxge_t); 734678453a8Sspeer 735678453a8Sspeer nxgep->statsp->mac_stats.xcvr_inuse = LOGICAL_XCVR; 736678453a8Sspeer nxgep->mac.portmode = PORT_LOGICAL; 737678453a8Sspeer (void) ddi_prop_update_string(DDI_DEV_T_NONE, nxgep->dip, 738678453a8Sspeer "phy-type", "virtual transceiver"); 739678453a8Sspeer 740678453a8Sspeer nxgep->nports = 1; 741678453a8Sspeer nxgep->board_ver = 0; /* XXX What? */ 742678453a8Sspeer 743678453a8Sspeer /* 744678453a8Sspeer * local-mac-address property gives us info on which 745678453a8Sspeer * specific MAC address the Hybrid resource is associated 746678453a8Sspeer * with. 747678453a8Sspeer */ 748678453a8Sspeer if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0, 749678453a8Sspeer "local-mac-address", &prop_val, 750678453a8Sspeer &prop_len) != DDI_PROP_SUCCESS) { 751678453a8Sspeer goto nxge_attach_fail5; 752678453a8Sspeer } 753678453a8Sspeer if (prop_len != ETHERADDRL) { 754678453a8Sspeer ddi_prop_free(prop_val); 755678453a8Sspeer goto nxge_attach_fail5; 756678453a8Sspeer } 757678453a8Sspeer ether_copy(prop_val, nxgep->hio_mac_addr); 758678453a8Sspeer ddi_prop_free(prop_val); 759678453a8Sspeer nxge_get_logical_props(nxgep); 760678453a8Sspeer 761678453a8Sspeer } else { 762678453a8Sspeer status = nxge_xcvr_find(nxgep); 763678453a8Sspeer 764678453a8Sspeer if (status != NXGE_OK) { 765678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_attach: " 7664045d941Ssowmini " Couldn't determine card type" 7674045d941Ssowmini " .... exit ")); 768678453a8Sspeer goto nxge_attach_fail5; 769678453a8Sspeer } 770678453a8Sspeer 771678453a8Sspeer status = nxge_get_config_properties(nxgep); 772678453a8Sspeer 773678453a8Sspeer if (status != NXGE_OK) { 774678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 7754045d941Ssowmini "get_hw create failed")); 776678453a8Sspeer goto nxge_attach_fail; 777678453a8Sspeer } 77844961713Sgirish } 77944961713Sgirish 78044961713Sgirish /* 78144961713Sgirish * Setup the Kstats for the driver. 78244961713Sgirish */ 78344961713Sgirish nxge_setup_kstats(nxgep); 78444961713Sgirish 785678453a8Sspeer if (!isLDOMguest(nxgep)) 786678453a8Sspeer nxge_setup_param(nxgep); 78744961713Sgirish 78844961713Sgirish status = nxge_setup_system_dma_pages(nxgep); 78944961713Sgirish if (status != NXGE_OK) { 79044961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "set dma page failed")); 79144961713Sgirish goto nxge_attach_fail; 79244961713Sgirish } 79344961713Sgirish 79444961713Sgirish nxge_hw_id_init(nxgep); 795678453a8Sspeer 796678453a8Sspeer if (!isLDOMguest(nxgep)) 797678453a8Sspeer nxge_hw_init_niu_common(nxgep); 79844961713Sgirish 79944961713Sgirish status = nxge_setup_mutexes(nxgep); 80044961713Sgirish if (status != NXGE_OK) { 80144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "set mutex failed")); 80244961713Sgirish goto nxge_attach_fail; 80344961713Sgirish } 80444961713Sgirish 805678453a8Sspeer #if defined(sun4v) 806678453a8Sspeer if (isLDOMguest(nxgep)) { 807678453a8Sspeer /* Find our VR & channel sets. */ 808678453a8Sspeer status = nxge_hio_vr_add(nxgep); 809678453a8Sspeer goto nxge_attach_exit; 810678453a8Sspeer } 811678453a8Sspeer #endif 812678453a8Sspeer 81344961713Sgirish status = nxge_setup_dev(nxgep); 81444961713Sgirish if (status != DDI_SUCCESS) { 81544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "set dev failed")); 81644961713Sgirish goto nxge_attach_fail; 81744961713Sgirish } 81844961713Sgirish 81944961713Sgirish status = nxge_add_intrs(nxgep); 82044961713Sgirish if (status != DDI_SUCCESS) { 82144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "add_intr failed")); 82244961713Sgirish goto nxge_attach_fail; 82344961713Sgirish } 82444961713Sgirish status = nxge_add_soft_intrs(nxgep); 82544961713Sgirish if (status != DDI_SUCCESS) { 826678453a8Sspeer NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 827678453a8Sspeer "add_soft_intr failed")); 82844961713Sgirish goto nxge_attach_fail; 82944961713Sgirish } 83044961713Sgirish 83144961713Sgirish /* 83244961713Sgirish * Enable interrupts. 83344961713Sgirish */ 83444961713Sgirish nxge_intrs_enable(nxgep); 83544961713Sgirish 83600161856Syc /* If a guest, register with vio_net instead. */ 8372e59129aSraghus if ((status = nxge_mac_register(nxgep)) != NXGE_OK) { 83844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 839678453a8Sspeer "unable to register to mac layer (%d)", status)); 84044961713Sgirish goto nxge_attach_fail; 84144961713Sgirish } 84244961713Sgirish 84344961713Sgirish mac_link_update(nxgep->mach, LINK_STATE_UNKNOWN); 84444961713Sgirish 845678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DDI_CTL, 846678453a8Sspeer "registered to mac (instance %d)", instance)); 84744961713Sgirish 84800161856Syc /* nxge_link_monitor calls xcvr.check_link recursively */ 84944961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 85044961713Sgirish 85144961713Sgirish goto nxge_attach_exit; 85244961713Sgirish 85344961713Sgirish nxge_attach_fail: 85444961713Sgirish nxge_unattach(nxgep); 8552e59129aSraghus goto nxge_attach_fail1; 8562e59129aSraghus 8572e59129aSraghus nxge_attach_fail5: 8582e59129aSraghus /* 8592e59129aSraghus * Tear down the ndd parameters setup. 8602e59129aSraghus */ 8612e59129aSraghus nxge_destroy_param(nxgep); 8622e59129aSraghus 8632e59129aSraghus /* 8642e59129aSraghus * Tear down the kstat setup. 8652e59129aSraghus */ 8662e59129aSraghus nxge_destroy_kstats(nxgep); 8672e59129aSraghus 8682e59129aSraghus nxge_attach_fail4: 8692e59129aSraghus if (nxgep->nxge_hw_p) { 8702e59129aSraghus nxge_uninit_common_dev(nxgep); 8712e59129aSraghus nxgep->nxge_hw_p = NULL; 8722e59129aSraghus } 8732e59129aSraghus 8742e59129aSraghus nxge_attach_fail3: 8752e59129aSraghus /* 8762e59129aSraghus * Unmap the register setup. 8772e59129aSraghus */ 8782e59129aSraghus nxge_unmap_regs(nxgep); 8792e59129aSraghus 8802e59129aSraghus nxge_fm_fini(nxgep); 8812e59129aSraghus 8822e59129aSraghus nxge_attach_fail2: 8832e59129aSraghus ddi_soft_state_free(nxge_list, nxgep->instance); 8842e59129aSraghus 8852e59129aSraghus nxge_attach_fail1: 88656d930aeSspeer if (status != NXGE_OK) 88756d930aeSspeer status = (NXGE_ERROR | NXGE_DDI_FAILED); 88844961713Sgirish nxgep = NULL; 88944961713Sgirish 89044961713Sgirish nxge_attach_exit: 89144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_attach status = 0x%08x", 8924045d941Ssowmini status)); 89344961713Sgirish 89444961713Sgirish return (status); 89544961713Sgirish } 89644961713Sgirish 89744961713Sgirish static int 89844961713Sgirish nxge_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 89944961713Sgirish { 90044961713Sgirish int status = DDI_SUCCESS; 90144961713Sgirish int instance; 90244961713Sgirish p_nxge_t nxgep = NULL; 90344961713Sgirish 90444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_detach")); 90544961713Sgirish instance = ddi_get_instance(dip); 90644961713Sgirish nxgep = ddi_get_soft_state(nxge_list, instance); 90744961713Sgirish if (nxgep == NULL) { 90844961713Sgirish status = DDI_FAILURE; 90944961713Sgirish goto nxge_detach_exit; 91044961713Sgirish } 91144961713Sgirish 91244961713Sgirish switch (cmd) { 91344961713Sgirish case DDI_DETACH: 91444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_DETACH")); 91544961713Sgirish break; 91644961713Sgirish 91744961713Sgirish case DDI_PM_SUSPEND: 91844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_PM_SUSPEND")); 91944961713Sgirish nxgep->suspended = DDI_PM_SUSPEND; 92044961713Sgirish nxge_suspend(nxgep); 92144961713Sgirish break; 92244961713Sgirish 92344961713Sgirish case DDI_SUSPEND: 92444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_SUSPEND")); 92544961713Sgirish if (nxgep->suspended != DDI_PM_SUSPEND) { 92644961713Sgirish nxgep->suspended = DDI_SUSPEND; 92744961713Sgirish nxge_suspend(nxgep); 92844961713Sgirish } 92944961713Sgirish break; 93044961713Sgirish 93144961713Sgirish default: 93244961713Sgirish status = DDI_FAILURE; 93344961713Sgirish } 93444961713Sgirish 93544961713Sgirish if (cmd != DDI_DETACH) 93644961713Sgirish goto nxge_detach_exit; 93744961713Sgirish 93844961713Sgirish /* 93944961713Sgirish * Stop the xcvr polling. 94044961713Sgirish */ 94144961713Sgirish nxgep->suspended = cmd; 94244961713Sgirish 94344961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 94444961713Sgirish 945678453a8Sspeer if (isLDOMguest(nxgep)) { 946678453a8Sspeer nxge_hio_unregister(nxgep); 947678453a8Sspeer } else if (nxgep->mach && (status = mac_unregister(nxgep->mach)) != 0) { 94844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 9494045d941Ssowmini "<== nxge_detach status = 0x%08X", status)); 95044961713Sgirish return (DDI_FAILURE); 95144961713Sgirish } 95244961713Sgirish 95344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 9544045d941Ssowmini "<== nxge_detach (mac_unregister) status = 0x%08X", status)); 95544961713Sgirish 95644961713Sgirish nxge_unattach(nxgep); 95744961713Sgirish nxgep = NULL; 95844961713Sgirish 95944961713Sgirish nxge_detach_exit: 96044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_detach status = 0x%08X", 9614045d941Ssowmini status)); 96244961713Sgirish 96344961713Sgirish return (status); 96444961713Sgirish } 96544961713Sgirish 96644961713Sgirish static void 96744961713Sgirish nxge_unattach(p_nxge_t nxgep) 96844961713Sgirish { 96944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_unattach")); 97044961713Sgirish 97144961713Sgirish if (nxgep == NULL || nxgep->dev_regs == NULL) { 97244961713Sgirish return; 97344961713Sgirish } 97444961713Sgirish 97598ecde52Stm nxgep->nxge_magic = 0; 97698ecde52Stm 97744961713Sgirish if (nxgep->nxge_timerid) { 97844961713Sgirish nxge_stop_timer(nxgep, nxgep->nxge_timerid); 97944961713Sgirish nxgep->nxge_timerid = 0; 98044961713Sgirish } 98144961713Sgirish 9826f157acbSml /* 9836f157acbSml * If this flag is set, it will affect the Neptune 9846f157acbSml * only. 9856f157acbSml */ 9866f157acbSml if ((nxgep->niu_type != N2_NIU) && nxge_peu_reset_enable) { 9876f157acbSml nxge_niu_peu_reset(nxgep); 9886f157acbSml } 9896f157acbSml 990678453a8Sspeer #if defined(sun4v) 991678453a8Sspeer if (isLDOMguest(nxgep)) { 992d00f30bbSspeer (void) nxge_hio_vr_release(nxgep); 993678453a8Sspeer } 994678453a8Sspeer #endif 995678453a8Sspeer 99653560810Ssbehera if (nxgep->nxge_hw_p) { 99753560810Ssbehera nxge_uninit_common_dev(nxgep); 99853560810Ssbehera nxgep->nxge_hw_p = NULL; 99953560810Ssbehera } 100053560810Ssbehera 100144961713Sgirish #if defined(sun4v) 100244961713Sgirish if (nxgep->niu_type == N2_NIU && nxgep->niu_hsvc_available == B_TRUE) { 100344961713Sgirish (void) hsvc_unregister(&nxgep->niu_hsvc); 100444961713Sgirish nxgep->niu_hsvc_available = B_FALSE; 100544961713Sgirish } 100644961713Sgirish #endif 100744961713Sgirish /* 100844961713Sgirish * Stop any further interrupts. 100944961713Sgirish */ 101044961713Sgirish nxge_remove_intrs(nxgep); 101144961713Sgirish 101244961713Sgirish /* remove soft interrups */ 101344961713Sgirish nxge_remove_soft_intrs(nxgep); 101444961713Sgirish 101544961713Sgirish /* 101644961713Sgirish * Stop the device and free resources. 101744961713Sgirish */ 1018678453a8Sspeer if (!isLDOMguest(nxgep)) { 1019678453a8Sspeer nxge_destroy_dev(nxgep); 1020678453a8Sspeer } 102144961713Sgirish 102244961713Sgirish /* 102344961713Sgirish * Tear down the ndd parameters setup. 102444961713Sgirish */ 102544961713Sgirish nxge_destroy_param(nxgep); 102644961713Sgirish 102744961713Sgirish /* 102844961713Sgirish * Tear down the kstat setup. 102944961713Sgirish */ 103044961713Sgirish nxge_destroy_kstats(nxgep); 103144961713Sgirish 103244961713Sgirish /* 103344961713Sgirish * Destroy all mutexes. 103444961713Sgirish */ 103544961713Sgirish nxge_destroy_mutexes(nxgep); 103644961713Sgirish 103744961713Sgirish /* 103844961713Sgirish * Remove the list of ndd parameters which 103944961713Sgirish * were setup during attach. 104044961713Sgirish */ 104144961713Sgirish if (nxgep->dip) { 104244961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL, 10434045d941Ssowmini " nxge_unattach: remove all properties")); 104444961713Sgirish 104544961713Sgirish (void) ddi_prop_remove_all(nxgep->dip); 104644961713Sgirish } 104744961713Sgirish 104844961713Sgirish #if NXGE_PROPERTY 104944961713Sgirish nxge_remove_hard_properties(nxgep); 105044961713Sgirish #endif 105144961713Sgirish 105244961713Sgirish /* 105344961713Sgirish * Unmap the register setup. 105444961713Sgirish */ 105544961713Sgirish nxge_unmap_regs(nxgep); 105644961713Sgirish 105744961713Sgirish nxge_fm_fini(nxgep); 105844961713Sgirish 105944961713Sgirish ddi_soft_state_free(nxge_list, nxgep->instance); 106044961713Sgirish 106144961713Sgirish NXGE_DEBUG_MSG((NULL, DDI_CTL, "<== nxge_unattach")); 106244961713Sgirish } 106344961713Sgirish 1064678453a8Sspeer #if defined(sun4v) 1065678453a8Sspeer int 1066678453a8Sspeer nxge_hsvc_register( 1067678453a8Sspeer nxge_t *nxgep) 1068678453a8Sspeer { 1069678453a8Sspeer nxge_status_t status; 1070678453a8Sspeer 1071678453a8Sspeer if (nxgep->niu_type == N2_NIU) { 1072678453a8Sspeer nxgep->niu_hsvc_available = B_FALSE; 1073678453a8Sspeer bcopy(&niu_hsvc, &nxgep->niu_hsvc, sizeof (hsvc_info_t)); 1074678453a8Sspeer if ((status = hsvc_register(&nxgep->niu_hsvc, 1075678453a8Sspeer &nxgep->niu_min_ver)) != 0) { 1076678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1077678453a8Sspeer "nxge_attach: %s: cannot negotiate " 1078678453a8Sspeer "hypervisor services revision %d group: 0x%lx " 1079678453a8Sspeer "major: 0x%lx minor: 0x%lx errno: %d", 1080678453a8Sspeer niu_hsvc.hsvc_modname, niu_hsvc.hsvc_rev, 1081678453a8Sspeer niu_hsvc.hsvc_group, niu_hsvc.hsvc_major, 1082678453a8Sspeer niu_hsvc.hsvc_minor, status)); 1083678453a8Sspeer return (DDI_FAILURE); 1084678453a8Sspeer } 1085678453a8Sspeer nxgep->niu_hsvc_available = B_TRUE; 1086678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DDI_CTL, 10874045d941Ssowmini "NIU Hypervisor service enabled")); 1088678453a8Sspeer } 1089678453a8Sspeer 1090678453a8Sspeer return (DDI_SUCCESS); 1091678453a8Sspeer } 1092678453a8Sspeer #endif 1093678453a8Sspeer 109444961713Sgirish static char n2_siu_name[] = "niu"; 109544961713Sgirish 109644961713Sgirish static nxge_status_t 109744961713Sgirish nxge_map_regs(p_nxge_t nxgep) 109844961713Sgirish { 109944961713Sgirish int ddi_status = DDI_SUCCESS; 110044961713Sgirish p_dev_regs_t dev_regs; 110144961713Sgirish char buf[MAXPATHLEN + 1]; 110244961713Sgirish char *devname; 110344961713Sgirish #ifdef NXGE_DEBUG 110444961713Sgirish char *sysname; 110544961713Sgirish #endif 110644961713Sgirish off_t regsize; 110744961713Sgirish nxge_status_t status = NXGE_OK; 110814ea4bb7Ssd #if !defined(_BIG_ENDIAN) 110914ea4bb7Ssd off_t pci_offset; 111014ea4bb7Ssd uint16_t pcie_devctl; 111114ea4bb7Ssd #endif 111244961713Sgirish 1113678453a8Sspeer if (isLDOMguest(nxgep)) { 1114678453a8Sspeer return (nxge_guest_regs_map(nxgep)); 1115678453a8Sspeer } 1116678453a8Sspeer 111744961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_map_regs")); 111844961713Sgirish nxgep->dev_regs = NULL; 111944961713Sgirish dev_regs = KMEM_ZALLOC(sizeof (dev_regs_t), KM_SLEEP); 112044961713Sgirish dev_regs->nxge_regh = NULL; 112144961713Sgirish dev_regs->nxge_pciregh = NULL; 112244961713Sgirish dev_regs->nxge_msix_regh = NULL; 112344961713Sgirish dev_regs->nxge_vir_regh = NULL; 112444961713Sgirish dev_regs->nxge_vir2_regh = NULL; 112559ac0c16Sdavemq nxgep->niu_type = NIU_TYPE_NONE; 112644961713Sgirish 112744961713Sgirish devname = ddi_pathname(nxgep->dip, buf); 112844961713Sgirish ASSERT(strlen(devname) > 0); 112944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 11304045d941Ssowmini "nxge_map_regs: pathname devname %s", devname)); 113144961713Sgirish 113200161856Syc /* 113300161856Syc * The driver is running on a N2-NIU system if devname is something 113400161856Syc * like "/niu@80/network@0" 113500161856Syc */ 113644961713Sgirish if (strstr(devname, n2_siu_name)) { 113744961713Sgirish /* N2/NIU */ 113844961713Sgirish nxgep->niu_type = N2_NIU; 113944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 11404045d941Ssowmini "nxge_map_regs: N2/NIU devname %s", devname)); 114144961713Sgirish /* get function number */ 114244961713Sgirish nxgep->function_num = 11434045d941Ssowmini (devname[strlen(devname) -1] == '1' ? 1 : 0); 114444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 11454045d941Ssowmini "nxge_map_regs: N2/NIU function number %d", 11464045d941Ssowmini nxgep->function_num)); 114744961713Sgirish } else { 114844961713Sgirish int *prop_val; 114944961713Sgirish uint_t prop_len; 115044961713Sgirish uint8_t func_num; 115144961713Sgirish 115244961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 11534045d941Ssowmini 0, "reg", 11544045d941Ssowmini &prop_val, &prop_len) != DDI_PROP_SUCCESS) { 115544961713Sgirish NXGE_DEBUG_MSG((nxgep, VPD_CTL, 11564045d941Ssowmini "Reg property not found")); 115744961713Sgirish ddi_status = DDI_FAILURE; 115844961713Sgirish goto nxge_map_regs_fail0; 115944961713Sgirish 116044961713Sgirish } else { 116144961713Sgirish func_num = (prop_val[0] >> 8) & 0x7; 116244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 11634045d941Ssowmini "Reg property found: fun # %d", 11644045d941Ssowmini func_num)); 116544961713Sgirish nxgep->function_num = func_num; 1166678453a8Sspeer if (isLDOMguest(nxgep)) { 1167678453a8Sspeer nxgep->function_num /= 2; 1168678453a8Sspeer return (NXGE_OK); 1169678453a8Sspeer } 117044961713Sgirish ddi_prop_free(prop_val); 117144961713Sgirish } 117244961713Sgirish } 117344961713Sgirish 117444961713Sgirish switch (nxgep->niu_type) { 117544961713Sgirish default: 117644961713Sgirish (void) ddi_dev_regsize(nxgep->dip, 0, ®size); 117744961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 11784045d941Ssowmini "nxge_map_regs: pci config size 0x%x", regsize)); 117944961713Sgirish 118044961713Sgirish ddi_status = ddi_regs_map_setup(nxgep->dip, 0, 11814045d941Ssowmini (caddr_t *)&(dev_regs->nxge_pciregp), 0, 0, 11824045d941Ssowmini &nxge_dev_reg_acc_attr, &dev_regs->nxge_pciregh); 118344961713Sgirish if (ddi_status != DDI_SUCCESS) { 118444961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 11854045d941Ssowmini "ddi_map_regs, nxge bus config regs failed")); 118644961713Sgirish goto nxge_map_regs_fail0; 118744961713Sgirish } 118844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 11894045d941Ssowmini "nxge_map_reg: PCI config addr 0x%0llx " 11904045d941Ssowmini " handle 0x%0llx", dev_regs->nxge_pciregp, 11914045d941Ssowmini dev_regs->nxge_pciregh)); 119244961713Sgirish /* 119344961713Sgirish * IMP IMP 119444961713Sgirish * workaround for bit swapping bug in HW 119544961713Sgirish * which ends up in no-snoop = yes 119644961713Sgirish * resulting, in DMA not synched properly 119744961713Sgirish */ 119844961713Sgirish #if !defined(_BIG_ENDIAN) 119914ea4bb7Ssd /* workarounds for x86 systems */ 120014ea4bb7Ssd pci_offset = 0x80 + PCIE_DEVCTL; 120114ea4bb7Ssd pcie_devctl = 0x0; 120214ea4bb7Ssd pcie_devctl &= PCIE_DEVCTL_ENABLE_NO_SNOOP; 120314ea4bb7Ssd pcie_devctl |= PCIE_DEVCTL_RO_EN; 120414ea4bb7Ssd pci_config_put16(dev_regs->nxge_pciregh, pci_offset, 12054045d941Ssowmini pcie_devctl); 120644961713Sgirish #endif 120714ea4bb7Ssd 120844961713Sgirish (void) ddi_dev_regsize(nxgep->dip, 1, ®size); 120944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 12104045d941Ssowmini "nxge_map_regs: pio size 0x%x", regsize)); 121144961713Sgirish /* set up the device mapped register */ 121244961713Sgirish ddi_status = ddi_regs_map_setup(nxgep->dip, 1, 12134045d941Ssowmini (caddr_t *)&(dev_regs->nxge_regp), 0, 0, 12144045d941Ssowmini &nxge_dev_reg_acc_attr, &dev_regs->nxge_regh); 121544961713Sgirish if (ddi_status != DDI_SUCCESS) { 121644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 12174045d941Ssowmini "ddi_map_regs for Neptune global reg failed")); 121844961713Sgirish goto nxge_map_regs_fail1; 121944961713Sgirish } 122044961713Sgirish 122144961713Sgirish /* set up the msi/msi-x mapped register */ 122244961713Sgirish (void) ddi_dev_regsize(nxgep->dip, 2, ®size); 122344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 12244045d941Ssowmini "nxge_map_regs: msix size 0x%x", regsize)); 122544961713Sgirish ddi_status = ddi_regs_map_setup(nxgep->dip, 2, 12264045d941Ssowmini (caddr_t *)&(dev_regs->nxge_msix_regp), 0, 0, 12274045d941Ssowmini &nxge_dev_reg_acc_attr, &dev_regs->nxge_msix_regh); 122844961713Sgirish if (ddi_status != DDI_SUCCESS) { 122944961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 12304045d941Ssowmini "ddi_map_regs for msi reg failed")); 123144961713Sgirish goto nxge_map_regs_fail2; 123244961713Sgirish } 123344961713Sgirish 123444961713Sgirish /* set up the vio region mapped register */ 123544961713Sgirish (void) ddi_dev_regsize(nxgep->dip, 3, ®size); 123644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 12374045d941Ssowmini "nxge_map_regs: vio size 0x%x", regsize)); 123844961713Sgirish ddi_status = ddi_regs_map_setup(nxgep->dip, 3, 12394045d941Ssowmini (caddr_t *)&(dev_regs->nxge_vir_regp), 0, 0, 12404045d941Ssowmini &nxge_dev_reg_acc_attr, &dev_regs->nxge_vir_regh); 124144961713Sgirish 124244961713Sgirish if (ddi_status != DDI_SUCCESS) { 124344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 12444045d941Ssowmini "ddi_map_regs for nxge vio reg failed")); 124544961713Sgirish goto nxge_map_regs_fail3; 124644961713Sgirish } 124744961713Sgirish nxgep->dev_regs = dev_regs; 124844961713Sgirish 124944961713Sgirish NPI_PCI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_pciregh); 125044961713Sgirish NPI_PCI_ADD_HANDLE_SET(nxgep, 12514045d941Ssowmini (npi_reg_ptr_t)dev_regs->nxge_pciregp); 125244961713Sgirish NPI_MSI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_msix_regh); 125344961713Sgirish NPI_MSI_ADD_HANDLE_SET(nxgep, 12544045d941Ssowmini (npi_reg_ptr_t)dev_regs->nxge_msix_regp); 125544961713Sgirish 125644961713Sgirish NPI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh); 125744961713Sgirish NPI_ADD_HANDLE_SET(nxgep, (npi_reg_ptr_t)dev_regs->nxge_regp); 125844961713Sgirish 125944961713Sgirish NPI_REG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh); 126044961713Sgirish NPI_REG_ADD_HANDLE_SET(nxgep, 12614045d941Ssowmini (npi_reg_ptr_t)dev_regs->nxge_regp); 126244961713Sgirish 126344961713Sgirish NPI_VREG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_vir_regh); 126444961713Sgirish NPI_VREG_ADD_HANDLE_SET(nxgep, 12654045d941Ssowmini (npi_reg_ptr_t)dev_regs->nxge_vir_regp); 126644961713Sgirish 126744961713Sgirish break; 126844961713Sgirish 126944961713Sgirish case N2_NIU: 127044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "ddi_map_regs, NIU")); 127144961713Sgirish /* 127244961713Sgirish * Set up the device mapped register (FWARC 2006/556) 127344961713Sgirish * (changed back to 1: reg starts at 1!) 127444961713Sgirish */ 127544961713Sgirish (void) ddi_dev_regsize(nxgep->dip, 1, ®size); 127644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 12774045d941Ssowmini "nxge_map_regs: dev size 0x%x", regsize)); 127844961713Sgirish ddi_status = ddi_regs_map_setup(nxgep->dip, 1, 12794045d941Ssowmini (caddr_t *)&(dev_regs->nxge_regp), 0, 0, 12804045d941Ssowmini &nxge_dev_reg_acc_attr, &dev_regs->nxge_regh); 128144961713Sgirish 128244961713Sgirish if (ddi_status != DDI_SUCCESS) { 128344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 12844045d941Ssowmini "ddi_map_regs for N2/NIU, global reg failed ")); 128544961713Sgirish goto nxge_map_regs_fail1; 128644961713Sgirish } 128744961713Sgirish 1288678453a8Sspeer /* set up the first vio region mapped register */ 128944961713Sgirish (void) ddi_dev_regsize(nxgep->dip, 2, ®size); 129044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 12914045d941Ssowmini "nxge_map_regs: vio (1) size 0x%x", regsize)); 129244961713Sgirish ddi_status = ddi_regs_map_setup(nxgep->dip, 2, 12934045d941Ssowmini (caddr_t *)&(dev_regs->nxge_vir_regp), 0, 0, 12944045d941Ssowmini &nxge_dev_reg_acc_attr, &dev_regs->nxge_vir_regh); 129544961713Sgirish 129644961713Sgirish if (ddi_status != DDI_SUCCESS) { 129744961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 12984045d941Ssowmini "ddi_map_regs for nxge vio reg failed")); 129944961713Sgirish goto nxge_map_regs_fail2; 130044961713Sgirish } 1301678453a8Sspeer /* set up the second vio region mapped register */ 130244961713Sgirish (void) ddi_dev_regsize(nxgep->dip, 3, ®size); 130344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 13044045d941Ssowmini "nxge_map_regs: vio (3) size 0x%x", regsize)); 130544961713Sgirish ddi_status = ddi_regs_map_setup(nxgep->dip, 3, 13064045d941Ssowmini (caddr_t *)&(dev_regs->nxge_vir2_regp), 0, 0, 13074045d941Ssowmini &nxge_dev_reg_acc_attr, &dev_regs->nxge_vir2_regh); 130844961713Sgirish 130944961713Sgirish if (ddi_status != DDI_SUCCESS) { 131044961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 13114045d941Ssowmini "ddi_map_regs for nxge vio2 reg failed")); 131244961713Sgirish goto nxge_map_regs_fail3; 131344961713Sgirish } 131444961713Sgirish nxgep->dev_regs = dev_regs; 131544961713Sgirish 131644961713Sgirish NPI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh); 131744961713Sgirish NPI_ADD_HANDLE_SET(nxgep, (npi_reg_ptr_t)dev_regs->nxge_regp); 131844961713Sgirish 131944961713Sgirish NPI_REG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh); 132044961713Sgirish NPI_REG_ADD_HANDLE_SET(nxgep, 13214045d941Ssowmini (npi_reg_ptr_t)dev_regs->nxge_regp); 132244961713Sgirish 132344961713Sgirish NPI_VREG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_vir_regh); 132444961713Sgirish NPI_VREG_ADD_HANDLE_SET(nxgep, 13254045d941Ssowmini (npi_reg_ptr_t)dev_regs->nxge_vir_regp); 132644961713Sgirish 132744961713Sgirish NPI_V2REG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_vir2_regh); 132844961713Sgirish NPI_V2REG_ADD_HANDLE_SET(nxgep, 13294045d941Ssowmini (npi_reg_ptr_t)dev_regs->nxge_vir2_regp); 133044961713Sgirish 133144961713Sgirish break; 133244961713Sgirish } 133344961713Sgirish 133444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "nxge_map_reg: hardware addr 0x%0llx " 13354045d941Ssowmini " handle 0x%0llx", dev_regs->nxge_regp, dev_regs->nxge_regh)); 133644961713Sgirish 133744961713Sgirish goto nxge_map_regs_exit; 133844961713Sgirish nxge_map_regs_fail3: 133944961713Sgirish if (dev_regs->nxge_msix_regh) { 134044961713Sgirish ddi_regs_map_free(&dev_regs->nxge_msix_regh); 134144961713Sgirish } 134244961713Sgirish if (dev_regs->nxge_vir_regh) { 134344961713Sgirish ddi_regs_map_free(&dev_regs->nxge_regh); 134444961713Sgirish } 134544961713Sgirish nxge_map_regs_fail2: 134644961713Sgirish if (dev_regs->nxge_regh) { 134744961713Sgirish ddi_regs_map_free(&dev_regs->nxge_regh); 134844961713Sgirish } 134944961713Sgirish nxge_map_regs_fail1: 135044961713Sgirish if (dev_regs->nxge_pciregh) { 135144961713Sgirish ddi_regs_map_free(&dev_regs->nxge_pciregh); 135244961713Sgirish } 135344961713Sgirish nxge_map_regs_fail0: 135444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "Freeing register set memory")); 135544961713Sgirish kmem_free(dev_regs, sizeof (dev_regs_t)); 135644961713Sgirish 135744961713Sgirish nxge_map_regs_exit: 135844961713Sgirish if (ddi_status != DDI_SUCCESS) 135944961713Sgirish status |= (NXGE_ERROR | NXGE_DDI_FAILED); 136044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_map_regs")); 136144961713Sgirish return (status); 136244961713Sgirish } 136344961713Sgirish 136444961713Sgirish static void 136544961713Sgirish nxge_unmap_regs(p_nxge_t nxgep) 136644961713Sgirish { 136744961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_unmap_regs")); 1368678453a8Sspeer 1369678453a8Sspeer if (isLDOMguest(nxgep)) { 1370678453a8Sspeer nxge_guest_regs_map_free(nxgep); 1371678453a8Sspeer return; 1372678453a8Sspeer } 1373678453a8Sspeer 137444961713Sgirish if (nxgep->dev_regs) { 137544961713Sgirish if (nxgep->dev_regs->nxge_pciregh) { 137644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 13774045d941Ssowmini "==> nxge_unmap_regs: bus")); 137844961713Sgirish ddi_regs_map_free(&nxgep->dev_regs->nxge_pciregh); 137944961713Sgirish nxgep->dev_regs->nxge_pciregh = NULL; 138044961713Sgirish } 138144961713Sgirish if (nxgep->dev_regs->nxge_regh) { 138244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 13834045d941Ssowmini "==> nxge_unmap_regs: device registers")); 138444961713Sgirish ddi_regs_map_free(&nxgep->dev_regs->nxge_regh); 138544961713Sgirish nxgep->dev_regs->nxge_regh = NULL; 138644961713Sgirish } 138744961713Sgirish if (nxgep->dev_regs->nxge_msix_regh) { 138844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 13894045d941Ssowmini "==> nxge_unmap_regs: device interrupts")); 139044961713Sgirish ddi_regs_map_free(&nxgep->dev_regs->nxge_msix_regh); 139144961713Sgirish nxgep->dev_regs->nxge_msix_regh = NULL; 139244961713Sgirish } 139344961713Sgirish if (nxgep->dev_regs->nxge_vir_regh) { 139444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 13954045d941Ssowmini "==> nxge_unmap_regs: vio region")); 139644961713Sgirish ddi_regs_map_free(&nxgep->dev_regs->nxge_vir_regh); 139744961713Sgirish nxgep->dev_regs->nxge_vir_regh = NULL; 139844961713Sgirish } 139944961713Sgirish if (nxgep->dev_regs->nxge_vir2_regh) { 140044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 14014045d941Ssowmini "==> nxge_unmap_regs: vio2 region")); 140244961713Sgirish ddi_regs_map_free(&nxgep->dev_regs->nxge_vir2_regh); 140344961713Sgirish nxgep->dev_regs->nxge_vir2_regh = NULL; 140444961713Sgirish } 140544961713Sgirish 140644961713Sgirish kmem_free(nxgep->dev_regs, sizeof (dev_regs_t)); 140744961713Sgirish nxgep->dev_regs = NULL; 140844961713Sgirish } 140944961713Sgirish 141044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_unmap_regs")); 141144961713Sgirish } 141244961713Sgirish 141344961713Sgirish static nxge_status_t 141444961713Sgirish nxge_setup_mutexes(p_nxge_t nxgep) 141544961713Sgirish { 141644961713Sgirish int ddi_status = DDI_SUCCESS; 141744961713Sgirish nxge_status_t status = NXGE_OK; 141844961713Sgirish nxge_classify_t *classify_ptr; 141944961713Sgirish int partition; 142044961713Sgirish 142144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_setup_mutexes")); 142244961713Sgirish 142344961713Sgirish /* 142444961713Sgirish * Get the interrupt cookie so the mutexes can be 142558324dfcSspeer * Initialized. 142644961713Sgirish */ 1427678453a8Sspeer if (isLDOMguest(nxgep)) { 1428678453a8Sspeer nxgep->interrupt_cookie = 0; 1429678453a8Sspeer } else { 1430678453a8Sspeer ddi_status = ddi_get_iblock_cookie(nxgep->dip, 0, 1431678453a8Sspeer &nxgep->interrupt_cookie); 1432678453a8Sspeer 1433678453a8Sspeer if (ddi_status != DDI_SUCCESS) { 1434678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1435678453a8Sspeer "<== nxge_setup_mutexes: failed 0x%x", 1436678453a8Sspeer ddi_status)); 1437678453a8Sspeer goto nxge_setup_mutexes_exit; 1438678453a8Sspeer } 143944961713Sgirish } 144044961713Sgirish 144198ecde52Stm cv_init(&nxgep->poll_cv, NULL, CV_DRIVER, NULL); 144298ecde52Stm MUTEX_INIT(&nxgep->poll_lock, NULL, 144398ecde52Stm MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 144498ecde52Stm 144544961713Sgirish /* 144698ecde52Stm * Initialize mutexes for this device. 144744961713Sgirish */ 144844961713Sgirish MUTEX_INIT(nxgep->genlock, NULL, 14494045d941Ssowmini MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 145044961713Sgirish MUTEX_INIT(&nxgep->ouraddr_lock, NULL, 14514045d941Ssowmini MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 145244961713Sgirish MUTEX_INIT(&nxgep->mif_lock, NULL, 14534045d941Ssowmini MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1454678453a8Sspeer MUTEX_INIT(&nxgep->group_lock, NULL, 1455678453a8Sspeer MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 145644961713Sgirish RW_INIT(&nxgep->filter_lock, NULL, 14574045d941Ssowmini RW_DRIVER, (void *)nxgep->interrupt_cookie); 145844961713Sgirish 145944961713Sgirish classify_ptr = &nxgep->classifier; 146044961713Sgirish /* 146144961713Sgirish * FFLP Mutexes are never used in interrupt context 146244961713Sgirish * as fflp operation can take very long time to 146344961713Sgirish * complete and hence not suitable to invoke from interrupt 146444961713Sgirish * handlers. 146544961713Sgirish */ 146644961713Sgirish MUTEX_INIT(&classify_ptr->tcam_lock, NULL, 146759ac0c16Sdavemq NXGE_MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 14682e59129aSraghus if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) { 146944961713Sgirish MUTEX_INIT(&classify_ptr->fcram_lock, NULL, 147059ac0c16Sdavemq NXGE_MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 147144961713Sgirish for (partition = 0; partition < MAX_PARTITION; partition++) { 147244961713Sgirish MUTEX_INIT(&classify_ptr->hash_lock[partition], NULL, 147344961713Sgirish NXGE_MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 147444961713Sgirish } 147544961713Sgirish } 147644961713Sgirish 147744961713Sgirish nxge_setup_mutexes_exit: 147844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 147959ac0c16Sdavemq "<== nxge_setup_mutexes status = %x", status)); 148044961713Sgirish 148144961713Sgirish if (ddi_status != DDI_SUCCESS) 148244961713Sgirish status |= (NXGE_ERROR | NXGE_DDI_FAILED); 148344961713Sgirish 148444961713Sgirish return (status); 148544961713Sgirish } 148644961713Sgirish 148744961713Sgirish static void 148844961713Sgirish nxge_destroy_mutexes(p_nxge_t nxgep) 148944961713Sgirish { 149044961713Sgirish int partition; 149144961713Sgirish nxge_classify_t *classify_ptr; 149244961713Sgirish 149344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_mutexes")); 149444961713Sgirish RW_DESTROY(&nxgep->filter_lock); 1495678453a8Sspeer MUTEX_DESTROY(&nxgep->group_lock); 149644961713Sgirish MUTEX_DESTROY(&nxgep->mif_lock); 149744961713Sgirish MUTEX_DESTROY(&nxgep->ouraddr_lock); 149844961713Sgirish MUTEX_DESTROY(nxgep->genlock); 149944961713Sgirish 150044961713Sgirish classify_ptr = &nxgep->classifier; 150144961713Sgirish MUTEX_DESTROY(&classify_ptr->tcam_lock); 150244961713Sgirish 150398ecde52Stm /* Destroy all polling resources. */ 150498ecde52Stm MUTEX_DESTROY(&nxgep->poll_lock); 150598ecde52Stm cv_destroy(&nxgep->poll_cv); 150698ecde52Stm 150798ecde52Stm /* free data structures, based on HW type */ 15082e59129aSraghus if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) { 150944961713Sgirish MUTEX_DESTROY(&classify_ptr->fcram_lock); 151044961713Sgirish for (partition = 0; partition < MAX_PARTITION; partition++) { 151144961713Sgirish MUTEX_DESTROY(&classify_ptr->hash_lock[partition]); 151244961713Sgirish } 151344961713Sgirish } 151444961713Sgirish 151544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_mutexes")); 151644961713Sgirish } 151744961713Sgirish 151844961713Sgirish nxge_status_t 151944961713Sgirish nxge_init(p_nxge_t nxgep) 152044961713Sgirish { 1521678453a8Sspeer nxge_status_t status = NXGE_OK; 152244961713Sgirish 152344961713Sgirish NXGE_DEBUG_MSG((nxgep, STR_CTL, "==> nxge_init")); 152444961713Sgirish 152514ea4bb7Ssd if (nxgep->drv_state & STATE_HW_INITIALIZED) { 152614ea4bb7Ssd return (status); 152714ea4bb7Ssd } 152814ea4bb7Ssd 152944961713Sgirish /* 153044961713Sgirish * Allocate system memory for the receive/transmit buffer blocks 153144961713Sgirish * and receive/transmit descriptor rings. 153244961713Sgirish */ 153344961713Sgirish status = nxge_alloc_mem_pool(nxgep); 153444961713Sgirish if (status != NXGE_OK) { 153544961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "alloc mem failed\n")); 153644961713Sgirish goto nxge_init_fail1; 153744961713Sgirish } 153844961713Sgirish 1539678453a8Sspeer if (!isLDOMguest(nxgep)) { 1540678453a8Sspeer /* 1541678453a8Sspeer * Initialize and enable the TXC registers. 1542678453a8Sspeer * (Globally enable the Tx controller, 1543678453a8Sspeer * enable the port, configure the dma channel bitmap, 1544678453a8Sspeer * configure the max burst size). 1545678453a8Sspeer */ 1546678453a8Sspeer status = nxge_txc_init(nxgep); 1547678453a8Sspeer if (status != NXGE_OK) { 1548678453a8Sspeer NXGE_ERROR_MSG((nxgep, 1549678453a8Sspeer NXGE_ERR_CTL, "init txc failed\n")); 1550678453a8Sspeer goto nxge_init_fail2; 1551678453a8Sspeer } 155244961713Sgirish } 155344961713Sgirish 155444961713Sgirish /* 155544961713Sgirish * Initialize and enable TXDMA channels. 155644961713Sgirish */ 155744961713Sgirish status = nxge_init_txdma_channels(nxgep); 155844961713Sgirish if (status != NXGE_OK) { 155944961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init txdma failed\n")); 156044961713Sgirish goto nxge_init_fail3; 156144961713Sgirish } 156244961713Sgirish 156344961713Sgirish /* 156444961713Sgirish * Initialize and enable RXDMA channels. 156544961713Sgirish */ 156644961713Sgirish status = nxge_init_rxdma_channels(nxgep); 156744961713Sgirish if (status != NXGE_OK) { 156844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init rxdma failed\n")); 156944961713Sgirish goto nxge_init_fail4; 157044961713Sgirish } 157144961713Sgirish 1572678453a8Sspeer /* 1573678453a8Sspeer * The guest domain is now done. 1574678453a8Sspeer */ 1575678453a8Sspeer if (isLDOMguest(nxgep)) { 1576678453a8Sspeer nxgep->drv_state |= STATE_HW_INITIALIZED; 1577678453a8Sspeer goto nxge_init_exit; 1578678453a8Sspeer } 1579678453a8Sspeer 158044961713Sgirish /* 158144961713Sgirish * Initialize TCAM and FCRAM (Neptune). 158244961713Sgirish */ 158344961713Sgirish status = nxge_classify_init(nxgep); 158444961713Sgirish if (status != NXGE_OK) { 158544961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init classify failed\n")); 158644961713Sgirish goto nxge_init_fail5; 158744961713Sgirish } 158844961713Sgirish 158944961713Sgirish /* 159044961713Sgirish * Initialize ZCP 159144961713Sgirish */ 159244961713Sgirish status = nxge_zcp_init(nxgep); 159344961713Sgirish if (status != NXGE_OK) { 159444961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init ZCP failed\n")); 159544961713Sgirish goto nxge_init_fail5; 159644961713Sgirish } 159744961713Sgirish 159844961713Sgirish /* 159944961713Sgirish * Initialize IPP. 160044961713Sgirish */ 160144961713Sgirish status = nxge_ipp_init(nxgep); 160244961713Sgirish if (status != NXGE_OK) { 160344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init IPP failed\n")); 160444961713Sgirish goto nxge_init_fail5; 160544961713Sgirish } 160644961713Sgirish 160744961713Sgirish /* 160844961713Sgirish * Initialize the MAC block. 160944961713Sgirish */ 161044961713Sgirish status = nxge_mac_init(nxgep); 161144961713Sgirish if (status != NXGE_OK) { 161244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init MAC failed\n")); 161344961713Sgirish goto nxge_init_fail5; 161444961713Sgirish } 161544961713Sgirish 1616678453a8Sspeer nxge_intrs_enable(nxgep); /* XXX What changes do I need to make here? */ 161744961713Sgirish 161844961713Sgirish /* 161944961713Sgirish * Enable hardware interrupts. 162044961713Sgirish */ 162144961713Sgirish nxge_intr_hw_enable(nxgep); 162244961713Sgirish nxgep->drv_state |= STATE_HW_INITIALIZED; 162344961713Sgirish 162444961713Sgirish goto nxge_init_exit; 162544961713Sgirish 162644961713Sgirish nxge_init_fail5: 162744961713Sgirish nxge_uninit_rxdma_channels(nxgep); 162844961713Sgirish nxge_init_fail4: 162944961713Sgirish nxge_uninit_txdma_channels(nxgep); 163044961713Sgirish nxge_init_fail3: 1631678453a8Sspeer if (!isLDOMguest(nxgep)) { 1632678453a8Sspeer (void) nxge_txc_uninit(nxgep); 1633678453a8Sspeer } 163444961713Sgirish nxge_init_fail2: 163544961713Sgirish nxge_free_mem_pool(nxgep); 163644961713Sgirish nxge_init_fail1: 163744961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 16384045d941Ssowmini "<== nxge_init status (failed) = 0x%08x", status)); 163944961713Sgirish return (status); 164044961713Sgirish 164144961713Sgirish nxge_init_exit: 164244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_init status = 0x%08x", 16434045d941Ssowmini status)); 164444961713Sgirish return (status); 164544961713Sgirish } 164644961713Sgirish 164744961713Sgirish 164844961713Sgirish timeout_id_t 164944961713Sgirish nxge_start_timer(p_nxge_t nxgep, fptrv_t func, int msec) 165044961713Sgirish { 16514045d941Ssowmini if ((nxgep->suspended == 0) || (nxgep->suspended == DDI_RESUME)) { 165244961713Sgirish return (timeout(func, (caddr_t)nxgep, 16534045d941Ssowmini drv_usectohz(1000 * msec))); 165444961713Sgirish } 165544961713Sgirish return (NULL); 165644961713Sgirish } 165744961713Sgirish 165844961713Sgirish /*ARGSUSED*/ 165944961713Sgirish void 166044961713Sgirish nxge_stop_timer(p_nxge_t nxgep, timeout_id_t timerid) 166144961713Sgirish { 166244961713Sgirish if (timerid) { 166344961713Sgirish (void) untimeout(timerid); 166444961713Sgirish } 166544961713Sgirish } 166644961713Sgirish 166744961713Sgirish void 166844961713Sgirish nxge_uninit(p_nxge_t nxgep) 166944961713Sgirish { 167044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_uninit")); 167144961713Sgirish 167244961713Sgirish if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 167344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 16744045d941Ssowmini "==> nxge_uninit: not initialized")); 167544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 16764045d941Ssowmini "<== nxge_uninit")); 167744961713Sgirish return; 167844961713Sgirish } 167944961713Sgirish 168044961713Sgirish /* stop timer */ 168144961713Sgirish if (nxgep->nxge_timerid) { 168244961713Sgirish nxge_stop_timer(nxgep, nxgep->nxge_timerid); 168344961713Sgirish nxgep->nxge_timerid = 0; 168444961713Sgirish } 168544961713Sgirish 168644961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 168744961713Sgirish (void) nxge_intr_hw_disable(nxgep); 168844961713Sgirish 168944961713Sgirish /* 169044961713Sgirish * Reset the receive MAC side. 169144961713Sgirish */ 169244961713Sgirish (void) nxge_rx_mac_disable(nxgep); 169344961713Sgirish 169444961713Sgirish /* Disable and soft reset the IPP */ 1695678453a8Sspeer if (!isLDOMguest(nxgep)) 1696678453a8Sspeer (void) nxge_ipp_disable(nxgep); 169744961713Sgirish 1698a3c5bd6dSspeer /* Free classification resources */ 1699a3c5bd6dSspeer (void) nxge_classify_uninit(nxgep); 1700a3c5bd6dSspeer 170144961713Sgirish /* 170244961713Sgirish * Reset the transmit/receive DMA side. 170344961713Sgirish */ 170444961713Sgirish (void) nxge_txdma_hw_mode(nxgep, NXGE_DMA_STOP); 170544961713Sgirish (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_STOP); 170644961713Sgirish 170744961713Sgirish nxge_uninit_txdma_channels(nxgep); 170844961713Sgirish nxge_uninit_rxdma_channels(nxgep); 170944961713Sgirish 171044961713Sgirish /* 171144961713Sgirish * Reset the transmit MAC side. 171244961713Sgirish */ 171344961713Sgirish (void) nxge_tx_mac_disable(nxgep); 171444961713Sgirish 171544961713Sgirish nxge_free_mem_pool(nxgep); 171644961713Sgirish 17176f157acbSml /* 17186f157acbSml * Start the timer if the reset flag is not set. 17196f157acbSml * If this reset flag is set, the link monitor 17206f157acbSml * will not be started in order to stop furthur bus 17216f157acbSml * activities coming from this interface. 17226f157acbSml * The driver will start the monitor function 17236f157acbSml * if the interface was initialized again later. 17246f157acbSml */ 17256f157acbSml if (!nxge_peu_reset_enable) { 17266f157acbSml (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 17276f157acbSml } 172844961713Sgirish 172944961713Sgirish nxgep->drv_state &= ~STATE_HW_INITIALIZED; 173044961713Sgirish 173144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_uninit: " 17324045d941Ssowmini "nxge_mblks_pending %d", nxge_mblks_pending)); 173344961713Sgirish } 173444961713Sgirish 173544961713Sgirish void 173644961713Sgirish nxge_get64(p_nxge_t nxgep, p_mblk_t mp) 173744961713Sgirish { 1738adfcba55Sjoycey #if defined(__i386) 1739adfcba55Sjoycey size_t reg; 1740adfcba55Sjoycey #else 174144961713Sgirish uint64_t reg; 1742adfcba55Sjoycey #endif 174344961713Sgirish uint64_t regdata; 174444961713Sgirish int i, retry; 174544961713Sgirish 174644961713Sgirish bcopy((char *)mp->b_rptr, (char *)®, sizeof (uint64_t)); 174744961713Sgirish regdata = 0; 174844961713Sgirish retry = 1; 174944961713Sgirish 175044961713Sgirish for (i = 0; i < retry; i++) { 175144961713Sgirish NXGE_REG_RD64(nxgep->npi_handle, reg, ®data); 175244961713Sgirish } 175344961713Sgirish bcopy((char *)®data, (char *)mp->b_rptr, sizeof (uint64_t)); 175444961713Sgirish } 175544961713Sgirish 175644961713Sgirish void 175744961713Sgirish nxge_put64(p_nxge_t nxgep, p_mblk_t mp) 175844961713Sgirish { 1759adfcba55Sjoycey #if defined(__i386) 1760adfcba55Sjoycey size_t reg; 1761adfcba55Sjoycey #else 176244961713Sgirish uint64_t reg; 1763adfcba55Sjoycey #endif 176444961713Sgirish uint64_t buf[2]; 176544961713Sgirish 176644961713Sgirish bcopy((char *)mp->b_rptr, (char *)&buf[0], 2 * sizeof (uint64_t)); 17677a8b1321Sjoycey #if defined(__i386) 17687a8b1321Sjoycey reg = (size_t)buf[0]; 17697a8b1321Sjoycey #else 177044961713Sgirish reg = buf[0]; 17717a8b1321Sjoycey #endif 177244961713Sgirish 177344961713Sgirish NXGE_NPI_PIO_WRITE64(nxgep->npi_handle, reg, buf[1]); 177444961713Sgirish } 177544961713Sgirish 177644961713Sgirish 177744961713Sgirish nxge_os_mutex_t nxgedebuglock; 177844961713Sgirish int nxge_debug_init = 0; 177944961713Sgirish 178044961713Sgirish /*ARGSUSED*/ 178144961713Sgirish /*VARARGS*/ 178244961713Sgirish void 178344961713Sgirish nxge_debug_msg(p_nxge_t nxgep, uint64_t level, char *fmt, ...) 178444961713Sgirish { 178544961713Sgirish char msg_buffer[1048]; 178644961713Sgirish char prefix_buffer[32]; 178744961713Sgirish int instance; 178844961713Sgirish uint64_t debug_level; 178944961713Sgirish int cmn_level = CE_CONT; 179044961713Sgirish va_list ap; 179144961713Sgirish 1792678453a8Sspeer if (nxgep && nxgep->nxge_debug_level != nxge_debug_level) { 1793678453a8Sspeer /* In case a developer has changed nxge_debug_level. */ 1794678453a8Sspeer if (nxgep->nxge_debug_level != nxge_debug_level) 1795678453a8Sspeer nxgep->nxge_debug_level = nxge_debug_level; 1796678453a8Sspeer } 1797678453a8Sspeer 179844961713Sgirish debug_level = (nxgep == NULL) ? nxge_debug_level : 17994045d941Ssowmini nxgep->nxge_debug_level; 180044961713Sgirish 180144961713Sgirish if ((level & debug_level) || 18024045d941Ssowmini (level == NXGE_NOTE) || 18034045d941Ssowmini (level == NXGE_ERR_CTL)) { 180444961713Sgirish /* do the msg processing */ 180544961713Sgirish if (nxge_debug_init == 0) { 180644961713Sgirish MUTEX_INIT(&nxgedebuglock, NULL, MUTEX_DRIVER, NULL); 180744961713Sgirish nxge_debug_init = 1; 180844961713Sgirish } 180944961713Sgirish 181044961713Sgirish MUTEX_ENTER(&nxgedebuglock); 181144961713Sgirish 181244961713Sgirish if ((level & NXGE_NOTE)) { 181344961713Sgirish cmn_level = CE_NOTE; 181444961713Sgirish } 181544961713Sgirish 181644961713Sgirish if (level & NXGE_ERR_CTL) { 181744961713Sgirish cmn_level = CE_WARN; 181844961713Sgirish } 181944961713Sgirish 182044961713Sgirish va_start(ap, fmt); 182144961713Sgirish (void) vsprintf(msg_buffer, fmt, ap); 182244961713Sgirish va_end(ap); 182344961713Sgirish if (nxgep == NULL) { 182444961713Sgirish instance = -1; 182544961713Sgirish (void) sprintf(prefix_buffer, "%s :", "nxge"); 182644961713Sgirish } else { 182744961713Sgirish instance = nxgep->instance; 182844961713Sgirish (void) sprintf(prefix_buffer, 18294045d941Ssowmini "%s%d :", "nxge", instance); 183044961713Sgirish } 183144961713Sgirish 183244961713Sgirish MUTEX_EXIT(&nxgedebuglock); 183344961713Sgirish cmn_err(cmn_level, "!%s %s\n", 18344045d941Ssowmini prefix_buffer, msg_buffer); 183544961713Sgirish 183644961713Sgirish } 183744961713Sgirish } 183844961713Sgirish 183944961713Sgirish char * 184044961713Sgirish nxge_dump_packet(char *addr, int size) 184144961713Sgirish { 184244961713Sgirish uchar_t *ap = (uchar_t *)addr; 184344961713Sgirish int i; 184444961713Sgirish static char etherbuf[1024]; 184544961713Sgirish char *cp = etherbuf; 184644961713Sgirish char digits[] = "0123456789abcdef"; 184744961713Sgirish 184844961713Sgirish if (!size) 184944961713Sgirish size = 60; 185044961713Sgirish 185144961713Sgirish if (size > MAX_DUMP_SZ) { 185244961713Sgirish /* Dump the leading bytes */ 185344961713Sgirish for (i = 0; i < MAX_DUMP_SZ/2; i++) { 185444961713Sgirish if (*ap > 0x0f) 185544961713Sgirish *cp++ = digits[*ap >> 4]; 185644961713Sgirish *cp++ = digits[*ap++ & 0xf]; 185744961713Sgirish *cp++ = ':'; 185844961713Sgirish } 185944961713Sgirish for (i = 0; i < 20; i++) 186044961713Sgirish *cp++ = '.'; 186144961713Sgirish /* Dump the last MAX_DUMP_SZ/2 bytes */ 186244961713Sgirish ap = (uchar_t *)(addr + (size - MAX_DUMP_SZ/2)); 186344961713Sgirish for (i = 0; i < MAX_DUMP_SZ/2; i++) { 186444961713Sgirish if (*ap > 0x0f) 186544961713Sgirish *cp++ = digits[*ap >> 4]; 186644961713Sgirish *cp++ = digits[*ap++ & 0xf]; 186744961713Sgirish *cp++ = ':'; 186844961713Sgirish } 186944961713Sgirish } else { 187044961713Sgirish for (i = 0; i < size; i++) { 187144961713Sgirish if (*ap > 0x0f) 187244961713Sgirish *cp++ = digits[*ap >> 4]; 187344961713Sgirish *cp++ = digits[*ap++ & 0xf]; 187444961713Sgirish *cp++ = ':'; 187544961713Sgirish } 187644961713Sgirish } 187744961713Sgirish *--cp = 0; 187844961713Sgirish return (etherbuf); 187944961713Sgirish } 188044961713Sgirish 188144961713Sgirish #ifdef NXGE_DEBUG 188244961713Sgirish static void 188344961713Sgirish nxge_test_map_regs(p_nxge_t nxgep) 188444961713Sgirish { 188544961713Sgirish ddi_acc_handle_t cfg_handle; 188644961713Sgirish p_pci_cfg_t cfg_ptr; 188744961713Sgirish ddi_acc_handle_t dev_handle; 188844961713Sgirish char *dev_ptr; 188944961713Sgirish ddi_acc_handle_t pci_config_handle; 189044961713Sgirish uint32_t regval; 189144961713Sgirish int i; 189244961713Sgirish 189344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_test_map_regs")); 189444961713Sgirish 189544961713Sgirish dev_handle = nxgep->dev_regs->nxge_regh; 189644961713Sgirish dev_ptr = (char *)nxgep->dev_regs->nxge_regp; 189744961713Sgirish 18982e59129aSraghus if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) { 189944961713Sgirish cfg_handle = nxgep->dev_regs->nxge_pciregh; 190044961713Sgirish cfg_ptr = (void *)nxgep->dev_regs->nxge_pciregp; 190144961713Sgirish 190244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 190359ac0c16Sdavemq "Neptune PCI regp cfg_ptr 0x%llx", (char *)cfg_ptr)); 190444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 190559ac0c16Sdavemq "Neptune PCI cfg_ptr vendor id ptr 0x%llx", 190659ac0c16Sdavemq &cfg_ptr->vendorid)); 190744961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 190859ac0c16Sdavemq "\tvendorid 0x%x devid 0x%x", 190959ac0c16Sdavemq NXGE_PIO_READ16(cfg_handle, &cfg_ptr->vendorid, 0), 191059ac0c16Sdavemq NXGE_PIO_READ16(cfg_handle, &cfg_ptr->devid, 0))); 191144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 191259ac0c16Sdavemq "PCI BAR: base 0x%x base14 0x%x base 18 0x%x " 191359ac0c16Sdavemq "bar1c 0x%x", 191459ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base, 0), 191559ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base14, 0), 191659ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base18, 0), 191759ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base1c, 0))); 191844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 191959ac0c16Sdavemq "\nNeptune PCI BAR: base20 0x%x base24 0x%x " 192059ac0c16Sdavemq "base 28 0x%x bar2c 0x%x\n", 192159ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base20, 0), 192259ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base24, 0), 192359ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base28, 0), 192459ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base2c, 0))); 192544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 192659ac0c16Sdavemq "\nNeptune PCI BAR: base30 0x%x\n", 192759ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base30, 0))); 192844961713Sgirish 192944961713Sgirish cfg_handle = nxgep->dev_regs->nxge_pciregh; 193044961713Sgirish cfg_ptr = (void *)nxgep->dev_regs->nxge_pciregp; 193144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 193259ac0c16Sdavemq "first 0x%llx second 0x%llx third 0x%llx " 193359ac0c16Sdavemq "last 0x%llx ", 193459ac0c16Sdavemq NXGE_PIO_READ64(dev_handle, 193559ac0c16Sdavemq (uint64_t *)(dev_ptr + 0), 0), 193659ac0c16Sdavemq NXGE_PIO_READ64(dev_handle, 193759ac0c16Sdavemq (uint64_t *)(dev_ptr + 8), 0), 193859ac0c16Sdavemq NXGE_PIO_READ64(dev_handle, 193959ac0c16Sdavemq (uint64_t *)(dev_ptr + 16), 0), 194059ac0c16Sdavemq NXGE_PIO_READ64(cfg_handle, 194159ac0c16Sdavemq (uint64_t *)(dev_ptr + 24), 0))); 194244961713Sgirish } 194344961713Sgirish } 194444961713Sgirish 194544961713Sgirish #endif 194644961713Sgirish 194744961713Sgirish static void 194844961713Sgirish nxge_suspend(p_nxge_t nxgep) 194944961713Sgirish { 195044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_suspend")); 195144961713Sgirish 195244961713Sgirish nxge_intrs_disable(nxgep); 195344961713Sgirish nxge_destroy_dev(nxgep); 195444961713Sgirish 195544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_suspend")); 195644961713Sgirish } 195744961713Sgirish 195844961713Sgirish static nxge_status_t 195944961713Sgirish nxge_resume(p_nxge_t nxgep) 196044961713Sgirish { 196144961713Sgirish nxge_status_t status = NXGE_OK; 196244961713Sgirish 196344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_resume")); 196444961713Sgirish 196591c98b31Sjoycey nxgep->suspended = DDI_RESUME; 196691c98b31Sjoycey (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 196791c98b31Sjoycey (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_START); 196891c98b31Sjoycey (void) nxge_txdma_hw_mode(nxgep, NXGE_DMA_START); 196991c98b31Sjoycey (void) nxge_rx_mac_enable(nxgep); 197091c98b31Sjoycey (void) nxge_tx_mac_enable(nxgep); 197191c98b31Sjoycey nxge_intrs_enable(nxgep); 197244961713Sgirish nxgep->suspended = 0; 197344961713Sgirish 197444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 19754045d941Ssowmini "<== nxge_resume status = 0x%x", status)); 197644961713Sgirish return (status); 197744961713Sgirish } 197844961713Sgirish 197944961713Sgirish static nxge_status_t 198044961713Sgirish nxge_setup_dev(p_nxge_t nxgep) 198144961713Sgirish { 198244961713Sgirish nxge_status_t status = NXGE_OK; 198344961713Sgirish 198444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_setup_dev port %d", 198559ac0c16Sdavemq nxgep->mac.portnum)); 198644961713Sgirish 198744961713Sgirish status = nxge_link_init(nxgep); 198814ea4bb7Ssd 198914ea4bb7Ssd if (fm_check_acc_handle(nxgep->dev_regs->nxge_regh) != DDI_FM_OK) { 199014ea4bb7Ssd NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 19914045d941Ssowmini "port%d Bad register acc handle", nxgep->mac.portnum)); 199214ea4bb7Ssd status = NXGE_ERROR; 199314ea4bb7Ssd } 199414ea4bb7Ssd 199544961713Sgirish if (status != NXGE_OK) { 199644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 19974045d941Ssowmini " nxge_setup_dev status " 19984045d941Ssowmini "(xcvr init 0x%08x)", status)); 199944961713Sgirish goto nxge_setup_dev_exit; 200044961713Sgirish } 200144961713Sgirish 200244961713Sgirish nxge_setup_dev_exit: 200344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 20044045d941Ssowmini "<== nxge_setup_dev port %d status = 0x%08x", 20054045d941Ssowmini nxgep->mac.portnum, status)); 200644961713Sgirish 200744961713Sgirish return (status); 200844961713Sgirish } 200944961713Sgirish 201044961713Sgirish static void 201144961713Sgirish nxge_destroy_dev(p_nxge_t nxgep) 201244961713Sgirish { 201344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_dev")); 201444961713Sgirish 201544961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 201644961713Sgirish 201744961713Sgirish (void) nxge_hw_stop(nxgep); 201844961713Sgirish 201944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_dev")); 202044961713Sgirish } 202144961713Sgirish 202244961713Sgirish static nxge_status_t 202344961713Sgirish nxge_setup_system_dma_pages(p_nxge_t nxgep) 202444961713Sgirish { 202544961713Sgirish int ddi_status = DDI_SUCCESS; 202644961713Sgirish uint_t count; 202744961713Sgirish ddi_dma_cookie_t cookie; 202844961713Sgirish uint_t iommu_pagesize; 202944961713Sgirish nxge_status_t status = NXGE_OK; 203044961713Sgirish 2031678453a8Sspeer NXGE_ERROR_MSG((nxgep, DDI_CTL, "==> nxge_setup_system_dma_pages")); 203244961713Sgirish nxgep->sys_page_sz = ddi_ptob(nxgep->dip, (ulong_t)1); 203344961713Sgirish if (nxgep->niu_type != N2_NIU) { 203444961713Sgirish iommu_pagesize = dvma_pagesize(nxgep->dip); 203544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 20364045d941Ssowmini " nxge_setup_system_dma_pages: page %d (ddi_ptob %d) " 20374045d941Ssowmini " default_block_size %d iommu_pagesize %d", 20384045d941Ssowmini nxgep->sys_page_sz, 20394045d941Ssowmini ddi_ptob(nxgep->dip, (ulong_t)1), 20404045d941Ssowmini nxgep->rx_default_block_size, 20414045d941Ssowmini iommu_pagesize)); 204244961713Sgirish 204344961713Sgirish if (iommu_pagesize != 0) { 204444961713Sgirish if (nxgep->sys_page_sz == iommu_pagesize) { 204544961713Sgirish if (iommu_pagesize > 0x4000) 204644961713Sgirish nxgep->sys_page_sz = 0x4000; 204744961713Sgirish } else { 204844961713Sgirish if (nxgep->sys_page_sz > iommu_pagesize) 204944961713Sgirish nxgep->sys_page_sz = iommu_pagesize; 205044961713Sgirish } 205144961713Sgirish } 205244961713Sgirish } 205344961713Sgirish nxgep->sys_page_mask = ~(nxgep->sys_page_sz - 1); 205444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 20554045d941Ssowmini "==> nxge_setup_system_dma_pages: page %d (ddi_ptob %d) " 20564045d941Ssowmini "default_block_size %d page mask %d", 20574045d941Ssowmini nxgep->sys_page_sz, 20584045d941Ssowmini ddi_ptob(nxgep->dip, (ulong_t)1), 20594045d941Ssowmini nxgep->rx_default_block_size, 20604045d941Ssowmini nxgep->sys_page_mask)); 206144961713Sgirish 206244961713Sgirish 206344961713Sgirish switch (nxgep->sys_page_sz) { 206444961713Sgirish default: 206544961713Sgirish nxgep->sys_page_sz = 0x1000; 206644961713Sgirish nxgep->sys_page_mask = ~(nxgep->sys_page_sz - 1); 206744961713Sgirish nxgep->rx_default_block_size = 0x1000; 206844961713Sgirish nxgep->rx_bksize_code = RBR_BKSIZE_4K; 206944961713Sgirish break; 207044961713Sgirish case 0x1000: 207144961713Sgirish nxgep->rx_default_block_size = 0x1000; 207244961713Sgirish nxgep->rx_bksize_code = RBR_BKSIZE_4K; 207344961713Sgirish break; 207444961713Sgirish case 0x2000: 207544961713Sgirish nxgep->rx_default_block_size = 0x2000; 207644961713Sgirish nxgep->rx_bksize_code = RBR_BKSIZE_8K; 207744961713Sgirish break; 207844961713Sgirish case 0x4000: 207944961713Sgirish nxgep->rx_default_block_size = 0x4000; 208044961713Sgirish nxgep->rx_bksize_code = RBR_BKSIZE_16K; 208144961713Sgirish break; 208244961713Sgirish case 0x8000: 208344961713Sgirish nxgep->rx_default_block_size = 0x8000; 208444961713Sgirish nxgep->rx_bksize_code = RBR_BKSIZE_32K; 208544961713Sgirish break; 208644961713Sgirish } 208744961713Sgirish 208844961713Sgirish #ifndef USE_RX_BIG_BUF 208944961713Sgirish nxge_rx_dma_attr.dma_attr_align = nxgep->sys_page_sz; 209044961713Sgirish #else 209144961713Sgirish nxgep->rx_default_block_size = 0x2000; 209244961713Sgirish nxgep->rx_bksize_code = RBR_BKSIZE_8K; 209344961713Sgirish #endif 209444961713Sgirish /* 209544961713Sgirish * Get the system DMA burst size. 209644961713Sgirish */ 209744961713Sgirish ddi_status = ddi_dma_alloc_handle(nxgep->dip, &nxge_tx_dma_attr, 20984045d941Ssowmini DDI_DMA_DONTWAIT, 0, 20994045d941Ssowmini &nxgep->dmasparehandle); 210044961713Sgirish if (ddi_status != DDI_SUCCESS) { 210144961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 21024045d941Ssowmini "ddi_dma_alloc_handle: failed " 21034045d941Ssowmini " status 0x%x", ddi_status)); 210444961713Sgirish goto nxge_get_soft_properties_exit; 210544961713Sgirish } 210644961713Sgirish 210744961713Sgirish ddi_status = ddi_dma_addr_bind_handle(nxgep->dmasparehandle, NULL, 21084045d941Ssowmini (caddr_t)nxgep->dmasparehandle, 21094045d941Ssowmini sizeof (nxgep->dmasparehandle), 21104045d941Ssowmini DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 21114045d941Ssowmini DDI_DMA_DONTWAIT, 0, 21124045d941Ssowmini &cookie, &count); 211344961713Sgirish if (ddi_status != DDI_DMA_MAPPED) { 211444961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 21154045d941Ssowmini "Binding spare handle to find system" 21164045d941Ssowmini " burstsize failed.")); 211744961713Sgirish ddi_status = DDI_FAILURE; 211844961713Sgirish goto nxge_get_soft_properties_fail1; 211944961713Sgirish } 212044961713Sgirish 212144961713Sgirish nxgep->sys_burst_sz = ddi_dma_burstsizes(nxgep->dmasparehandle); 212244961713Sgirish (void) ddi_dma_unbind_handle(nxgep->dmasparehandle); 212344961713Sgirish 212444961713Sgirish nxge_get_soft_properties_fail1: 212544961713Sgirish ddi_dma_free_handle(&nxgep->dmasparehandle); 212644961713Sgirish 212744961713Sgirish nxge_get_soft_properties_exit: 212844961713Sgirish 212944961713Sgirish if (ddi_status != DDI_SUCCESS) 213044961713Sgirish status |= (NXGE_ERROR | NXGE_DDI_FAILED); 213144961713Sgirish 213244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 21334045d941Ssowmini "<== nxge_setup_system_dma_pages status = 0x%08x", status)); 213444961713Sgirish return (status); 213544961713Sgirish } 213644961713Sgirish 213744961713Sgirish static nxge_status_t 213844961713Sgirish nxge_alloc_mem_pool(p_nxge_t nxgep) 213944961713Sgirish { 214044961713Sgirish nxge_status_t status = NXGE_OK; 214144961713Sgirish 214244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_alloc_mem_pool")); 214344961713Sgirish 214444961713Sgirish status = nxge_alloc_rx_mem_pool(nxgep); 214544961713Sgirish if (status != NXGE_OK) { 214644961713Sgirish return (NXGE_ERROR); 214744961713Sgirish } 214844961713Sgirish 214944961713Sgirish status = nxge_alloc_tx_mem_pool(nxgep); 215044961713Sgirish if (status != NXGE_OK) { 215144961713Sgirish nxge_free_rx_mem_pool(nxgep); 215244961713Sgirish return (NXGE_ERROR); 215344961713Sgirish } 215444961713Sgirish 215544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_alloc_mem_pool")); 215644961713Sgirish return (NXGE_OK); 215744961713Sgirish } 215844961713Sgirish 215944961713Sgirish static void 216044961713Sgirish nxge_free_mem_pool(p_nxge_t nxgep) 216144961713Sgirish { 216244961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM_CTL, "==> nxge_free_mem_pool")); 216344961713Sgirish 216444961713Sgirish nxge_free_rx_mem_pool(nxgep); 216544961713Sgirish nxge_free_tx_mem_pool(nxgep); 216644961713Sgirish 216744961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM_CTL, "<== nxge_free_mem_pool")); 216844961713Sgirish } 216944961713Sgirish 2170678453a8Sspeer nxge_status_t 217144961713Sgirish nxge_alloc_rx_mem_pool(p_nxge_t nxgep) 217244961713Sgirish { 2173678453a8Sspeer uint32_t rdc_max; 217444961713Sgirish p_nxge_dma_pt_cfg_t p_all_cfgp; 217544961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 217644961713Sgirish p_nxge_dma_pool_t dma_poolp; 217744961713Sgirish p_nxge_dma_common_t *dma_buf_p; 217844961713Sgirish p_nxge_dma_pool_t dma_cntl_poolp; 217944961713Sgirish p_nxge_dma_common_t *dma_cntl_p; 218044961713Sgirish uint32_t *num_chunks; /* per dma */ 218144961713Sgirish nxge_status_t status = NXGE_OK; 218244961713Sgirish 218344961713Sgirish uint32_t nxge_port_rbr_size; 218444961713Sgirish uint32_t nxge_port_rbr_spare_size; 218544961713Sgirish uint32_t nxge_port_rcr_size; 2186678453a8Sspeer uint32_t rx_cntl_alloc_size; 218744961713Sgirish 218844961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rx_mem_pool")); 218944961713Sgirish 219044961713Sgirish p_all_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 219144961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_all_cfgp->hw_config; 2192678453a8Sspeer rdc_max = NXGE_MAX_RDCS; 219344961713Sgirish 219444961713Sgirish /* 2195678453a8Sspeer * Allocate memory for the common DMA data structures. 219644961713Sgirish */ 219744961713Sgirish dma_poolp = (p_nxge_dma_pool_t)KMEM_ZALLOC(sizeof (nxge_dma_pool_t), 21984045d941Ssowmini KM_SLEEP); 219944961713Sgirish dma_buf_p = (p_nxge_dma_common_t *)KMEM_ZALLOC( 22004045d941Ssowmini sizeof (p_nxge_dma_common_t) * rdc_max, KM_SLEEP); 220144961713Sgirish 220244961713Sgirish dma_cntl_poolp = (p_nxge_dma_pool_t) 22034045d941Ssowmini KMEM_ZALLOC(sizeof (nxge_dma_pool_t), KM_SLEEP); 220444961713Sgirish dma_cntl_p = (p_nxge_dma_common_t *)KMEM_ZALLOC( 22054045d941Ssowmini sizeof (p_nxge_dma_common_t) * rdc_max, KM_SLEEP); 220644961713Sgirish 220744961713Sgirish num_chunks = (uint32_t *)KMEM_ZALLOC( 22084045d941Ssowmini sizeof (uint32_t) * rdc_max, KM_SLEEP); 220944961713Sgirish 221044961713Sgirish /* 2211678453a8Sspeer * Assume that each DMA channel will be configured with 2212678453a8Sspeer * the default block size. 2213678453a8Sspeer * rbr block counts are modulo the batch count (16). 221444961713Sgirish */ 221544961713Sgirish nxge_port_rbr_size = p_all_cfgp->rbr_size; 221644961713Sgirish nxge_port_rcr_size = p_all_cfgp->rcr_size; 221744961713Sgirish 221844961713Sgirish if (!nxge_port_rbr_size) { 221944961713Sgirish nxge_port_rbr_size = NXGE_RBR_RBB_DEFAULT; 222044961713Sgirish } 222144961713Sgirish if (nxge_port_rbr_size % NXGE_RXDMA_POST_BATCH) { 222244961713Sgirish nxge_port_rbr_size = (NXGE_RXDMA_POST_BATCH * 22234045d941Ssowmini (nxge_port_rbr_size / NXGE_RXDMA_POST_BATCH + 1)); 222444961713Sgirish } 222544961713Sgirish 222644961713Sgirish p_all_cfgp->rbr_size = nxge_port_rbr_size; 222744961713Sgirish nxge_port_rbr_spare_size = nxge_rbr_spare_size; 222844961713Sgirish 222944961713Sgirish if (nxge_port_rbr_spare_size % NXGE_RXDMA_POST_BATCH) { 223044961713Sgirish nxge_port_rbr_spare_size = (NXGE_RXDMA_POST_BATCH * 22314045d941Ssowmini (nxge_port_rbr_spare_size / NXGE_RXDMA_POST_BATCH + 1)); 223244961713Sgirish } 223330ac2e7bSml if (nxge_port_rbr_size > RBR_DEFAULT_MAX_BLKS) { 223430ac2e7bSml NXGE_DEBUG_MSG((nxgep, MEM_CTL, 223530ac2e7bSml "nxge_alloc_rx_mem_pool: RBR size too high %d, " 223630ac2e7bSml "set to default %d", 223730ac2e7bSml nxge_port_rbr_size, RBR_DEFAULT_MAX_BLKS)); 223830ac2e7bSml nxge_port_rbr_size = RBR_DEFAULT_MAX_BLKS; 223930ac2e7bSml } 224030ac2e7bSml if (nxge_port_rcr_size > RCR_DEFAULT_MAX) { 224130ac2e7bSml NXGE_DEBUG_MSG((nxgep, MEM_CTL, 224230ac2e7bSml "nxge_alloc_rx_mem_pool: RCR too high %d, " 224330ac2e7bSml "set to default %d", 224430ac2e7bSml nxge_port_rcr_size, RCR_DEFAULT_MAX)); 224530ac2e7bSml nxge_port_rcr_size = RCR_DEFAULT_MAX; 224630ac2e7bSml } 224744961713Sgirish 224844961713Sgirish /* 224944961713Sgirish * N2/NIU has limitation on the descriptor sizes (contiguous 225044961713Sgirish * memory allocation on data buffers to 4M (contig_mem_alloc) 225144961713Sgirish * and little endian for control buffers (must use the ddi/dki mem alloc 225244961713Sgirish * function). 225344961713Sgirish */ 225444961713Sgirish #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 225544961713Sgirish if (nxgep->niu_type == N2_NIU) { 225644961713Sgirish nxge_port_rbr_spare_size = 0; 225744961713Sgirish if ((nxge_port_rbr_size > NXGE_NIU_CONTIG_RBR_MAX) || 22584045d941Ssowmini (!ISP2(nxge_port_rbr_size))) { 225944961713Sgirish nxge_port_rbr_size = NXGE_NIU_CONTIG_RBR_MAX; 226044961713Sgirish } 226144961713Sgirish if ((nxge_port_rcr_size > NXGE_NIU_CONTIG_RCR_MAX) || 22624045d941Ssowmini (!ISP2(nxge_port_rcr_size))) { 226344961713Sgirish nxge_port_rcr_size = NXGE_NIU_CONTIG_RCR_MAX; 226444961713Sgirish } 226544961713Sgirish } 226644961713Sgirish #endif 226744961713Sgirish 226844961713Sgirish /* 226944961713Sgirish * Addresses of receive block ring, receive completion ring and the 227044961713Sgirish * mailbox must be all cache-aligned (64 bytes). 227144961713Sgirish */ 227244961713Sgirish rx_cntl_alloc_size = nxge_port_rbr_size + nxge_port_rbr_spare_size; 227344961713Sgirish rx_cntl_alloc_size *= (sizeof (rx_desc_t)); 227444961713Sgirish rx_cntl_alloc_size += (sizeof (rcr_entry_t) * nxge_port_rcr_size); 227544961713Sgirish rx_cntl_alloc_size += sizeof (rxdma_mailbox_t); 227644961713Sgirish 227744961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_alloc_rx_mem_pool: " 22784045d941Ssowmini "nxge_port_rbr_size = %d nxge_port_rbr_spare_size = %d " 22794045d941Ssowmini "nxge_port_rcr_size = %d " 22804045d941Ssowmini "rx_cntl_alloc_size = %d", 22814045d941Ssowmini nxge_port_rbr_size, nxge_port_rbr_spare_size, 22824045d941Ssowmini nxge_port_rcr_size, 22834045d941Ssowmini rx_cntl_alloc_size)); 228444961713Sgirish 228544961713Sgirish #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 228644961713Sgirish if (nxgep->niu_type == N2_NIU) { 2287678453a8Sspeer uint32_t rx_buf_alloc_size = (nxgep->rx_default_block_size * 2288678453a8Sspeer (nxge_port_rbr_size + nxge_port_rbr_spare_size)); 2289678453a8Sspeer 229044961713Sgirish if (!ISP2(rx_buf_alloc_size)) { 229144961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 22924045d941Ssowmini "==> nxge_alloc_rx_mem_pool: " 22934045d941Ssowmini " must be power of 2")); 229444961713Sgirish status |= (NXGE_ERROR | NXGE_DDI_FAILED); 229544961713Sgirish goto nxge_alloc_rx_mem_pool_exit; 229644961713Sgirish } 229744961713Sgirish 229844961713Sgirish if (rx_buf_alloc_size > (1 << 22)) { 229944961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 23004045d941Ssowmini "==> nxge_alloc_rx_mem_pool: " 23014045d941Ssowmini " limit size to 4M")); 230244961713Sgirish status |= (NXGE_ERROR | NXGE_DDI_FAILED); 230344961713Sgirish goto nxge_alloc_rx_mem_pool_exit; 230444961713Sgirish } 230544961713Sgirish 230644961713Sgirish if (rx_cntl_alloc_size < 0x2000) { 230744961713Sgirish rx_cntl_alloc_size = 0x2000; 230844961713Sgirish } 230944961713Sgirish } 231044961713Sgirish #endif 231144961713Sgirish nxgep->nxge_port_rbr_size = nxge_port_rbr_size; 231244961713Sgirish nxgep->nxge_port_rcr_size = nxge_port_rcr_size; 2313678453a8Sspeer nxgep->nxge_port_rbr_spare_size = nxge_port_rbr_spare_size; 2314678453a8Sspeer nxgep->nxge_port_rx_cntl_alloc_size = rx_cntl_alloc_size; 231544961713Sgirish 2316678453a8Sspeer dma_poolp->ndmas = p_cfgp->max_rdcs; 231744961713Sgirish dma_poolp->num_chunks = num_chunks; 231844961713Sgirish dma_poolp->buf_allocated = B_TRUE; 231944961713Sgirish nxgep->rx_buf_pool_p = dma_poolp; 232044961713Sgirish dma_poolp->dma_buf_pool_p = dma_buf_p; 232144961713Sgirish 2322678453a8Sspeer dma_cntl_poolp->ndmas = p_cfgp->max_rdcs; 232344961713Sgirish dma_cntl_poolp->buf_allocated = B_TRUE; 232444961713Sgirish nxgep->rx_cntl_pool_p = dma_cntl_poolp; 232544961713Sgirish dma_cntl_poolp->dma_buf_pool_p = dma_cntl_p; 232644961713Sgirish 2327678453a8Sspeer /* Allocate the receive rings, too. */ 2328678453a8Sspeer nxgep->rx_rbr_rings = 23294045d941Ssowmini KMEM_ZALLOC(sizeof (rx_rbr_rings_t), KM_SLEEP); 2330678453a8Sspeer nxgep->rx_rbr_rings->rbr_rings = 23314045d941Ssowmini KMEM_ZALLOC(sizeof (p_rx_rbr_ring_t) * rdc_max, KM_SLEEP); 2332678453a8Sspeer nxgep->rx_rcr_rings = 23334045d941Ssowmini KMEM_ZALLOC(sizeof (rx_rcr_rings_t), KM_SLEEP); 2334678453a8Sspeer nxgep->rx_rcr_rings->rcr_rings = 23354045d941Ssowmini KMEM_ZALLOC(sizeof (p_rx_rcr_ring_t) * rdc_max, KM_SLEEP); 2336678453a8Sspeer nxgep->rx_mbox_areas_p = 23374045d941Ssowmini KMEM_ZALLOC(sizeof (rx_mbox_areas_t), KM_SLEEP); 2338678453a8Sspeer nxgep->rx_mbox_areas_p->rxmbox_areas = 23394045d941Ssowmini KMEM_ZALLOC(sizeof (p_rx_mbox_t) * rdc_max, KM_SLEEP); 2340678453a8Sspeer 2341678453a8Sspeer nxgep->rx_rbr_rings->ndmas = nxgep->rx_rcr_rings->ndmas = 2342678453a8Sspeer p_cfgp->max_rdcs; 234344961713Sgirish 234444961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 23454045d941Ssowmini "<== nxge_alloc_rx_mem_pool:status 0x%08x", status)); 234644961713Sgirish 2347678453a8Sspeer nxge_alloc_rx_mem_pool_exit: 2348678453a8Sspeer return (status); 2349678453a8Sspeer } 2350678453a8Sspeer 2351678453a8Sspeer /* 2352678453a8Sspeer * nxge_alloc_rxb 2353678453a8Sspeer * 2354678453a8Sspeer * Allocate buffers for an RDC. 2355678453a8Sspeer * 2356678453a8Sspeer * Arguments: 2357678453a8Sspeer * nxgep 2358678453a8Sspeer * channel The channel to map into our kernel space. 2359678453a8Sspeer * 2360678453a8Sspeer * Notes: 2361678453a8Sspeer * 2362678453a8Sspeer * NPI function calls: 2363678453a8Sspeer * 2364678453a8Sspeer * NXGE function calls: 2365678453a8Sspeer * 2366678453a8Sspeer * Registers accessed: 2367678453a8Sspeer * 2368678453a8Sspeer * Context: 2369678453a8Sspeer * 2370678453a8Sspeer * Taking apart: 2371678453a8Sspeer * 2372678453a8Sspeer * Open questions: 2373678453a8Sspeer * 2374678453a8Sspeer */ 2375678453a8Sspeer nxge_status_t 2376678453a8Sspeer nxge_alloc_rxb( 2377678453a8Sspeer p_nxge_t nxgep, 2378678453a8Sspeer int channel) 2379678453a8Sspeer { 2380678453a8Sspeer size_t rx_buf_alloc_size; 2381678453a8Sspeer nxge_status_t status = NXGE_OK; 2382678453a8Sspeer 2383678453a8Sspeer nxge_dma_common_t **data; 2384678453a8Sspeer nxge_dma_common_t **control; 2385678453a8Sspeer uint32_t *num_chunks; 2386678453a8Sspeer 2387678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rbb")); 2388678453a8Sspeer 2389678453a8Sspeer /* 2390678453a8Sspeer * Allocate memory for the receive buffers and descriptor rings. 2391678453a8Sspeer * Replace these allocation functions with the interface functions 2392678453a8Sspeer * provided by the partition manager if/when they are available. 2393678453a8Sspeer */ 2394678453a8Sspeer 2395678453a8Sspeer /* 2396678453a8Sspeer * Allocate memory for the receive buffer blocks. 2397678453a8Sspeer */ 2398678453a8Sspeer rx_buf_alloc_size = (nxgep->rx_default_block_size * 23994045d941Ssowmini (nxgep->nxge_port_rbr_size + nxgep->nxge_port_rbr_spare_size)); 2400678453a8Sspeer 2401678453a8Sspeer data = &nxgep->rx_buf_pool_p->dma_buf_pool_p[channel]; 2402678453a8Sspeer num_chunks = &nxgep->rx_buf_pool_p->num_chunks[channel]; 2403678453a8Sspeer 2404678453a8Sspeer if ((status = nxge_alloc_rx_buf_dma( 2405678453a8Sspeer nxgep, channel, data, rx_buf_alloc_size, 2406678453a8Sspeer nxgep->rx_default_block_size, num_chunks)) != NXGE_OK) { 2407678453a8Sspeer return (status); 240844961713Sgirish } 240944961713Sgirish 2410678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_alloc_rxb(): " 2411678453a8Sspeer "dma %d dma_buf_p %llx &dma_buf_p %llx", channel, *data, data)); 2412678453a8Sspeer 2413678453a8Sspeer /* 2414678453a8Sspeer * Allocate memory for descriptor rings and mailbox. 2415678453a8Sspeer */ 2416678453a8Sspeer control = &nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel]; 2417678453a8Sspeer 2418678453a8Sspeer if ((status = nxge_alloc_rx_cntl_dma( 2419678453a8Sspeer nxgep, channel, control, nxgep->nxge_port_rx_cntl_alloc_size)) 2420678453a8Sspeer != NXGE_OK) { 2421678453a8Sspeer nxge_free_rx_cntl_dma(nxgep, *control); 2422678453a8Sspeer (*data)->buf_alloc_state |= BUF_ALLOCATED_WAIT_FREE; 2423678453a8Sspeer nxge_free_rx_buf_dma(nxgep, *data, *num_chunks); 2424678453a8Sspeer return (status); 2425678453a8Sspeer } 242644961713Sgirish 242744961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 2428678453a8Sspeer "<== nxge_alloc_rx_mem_pool:status 0x%08x", status)); 242944961713Sgirish 243044961713Sgirish return (status); 243144961713Sgirish } 243244961713Sgirish 2433678453a8Sspeer void 2434678453a8Sspeer nxge_free_rxb( 2435678453a8Sspeer p_nxge_t nxgep, 2436678453a8Sspeer int channel) 2437678453a8Sspeer { 2438678453a8Sspeer nxge_dma_common_t *data; 2439678453a8Sspeer nxge_dma_common_t *control; 2440678453a8Sspeer uint32_t num_chunks; 2441678453a8Sspeer 2442678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rbb")); 2443678453a8Sspeer 2444678453a8Sspeer data = nxgep->rx_buf_pool_p->dma_buf_pool_p[channel]; 2445678453a8Sspeer num_chunks = nxgep->rx_buf_pool_p->num_chunks[channel]; 2446678453a8Sspeer nxge_free_rx_buf_dma(nxgep, data, num_chunks); 2447678453a8Sspeer 2448678453a8Sspeer nxgep->rx_buf_pool_p->dma_buf_pool_p[channel] = 0; 2449678453a8Sspeer nxgep->rx_buf_pool_p->num_chunks[channel] = 0; 2450678453a8Sspeer 2451678453a8Sspeer control = nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel]; 2452678453a8Sspeer nxge_free_rx_cntl_dma(nxgep, control); 2453678453a8Sspeer 2454678453a8Sspeer nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel] = 0; 2455678453a8Sspeer 2456678453a8Sspeer KMEM_FREE(data, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK); 2457678453a8Sspeer KMEM_FREE(control, sizeof (nxge_dma_common_t)); 2458678453a8Sspeer 2459678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_alloc_rbb")); 2460678453a8Sspeer } 2461678453a8Sspeer 246244961713Sgirish static void 246344961713Sgirish nxge_free_rx_mem_pool(p_nxge_t nxgep) 246444961713Sgirish { 2465678453a8Sspeer int rdc_max = NXGE_MAX_RDCS; 246644961713Sgirish 246744961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_free_rx_mem_pool")); 246844961713Sgirish 2469678453a8Sspeer if (!nxgep->rx_buf_pool_p || !nxgep->rx_buf_pool_p->buf_allocated) { 247044961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 24714045d941Ssowmini "<== nxge_free_rx_mem_pool " 24724045d941Ssowmini "(null rx buf pool or buf not allocated")); 247344961713Sgirish return; 247444961713Sgirish } 2475678453a8Sspeer if (!nxgep->rx_cntl_pool_p || !nxgep->rx_cntl_pool_p->buf_allocated) { 247644961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 24774045d941Ssowmini "<== nxge_free_rx_mem_pool " 24784045d941Ssowmini "(null rx cntl buf pool or cntl buf not allocated")); 247944961713Sgirish return; 248044961713Sgirish } 248144961713Sgirish 2482678453a8Sspeer KMEM_FREE(nxgep->rx_cntl_pool_p->dma_buf_pool_p, 2483678453a8Sspeer sizeof (p_nxge_dma_common_t) * rdc_max); 2484678453a8Sspeer KMEM_FREE(nxgep->rx_cntl_pool_p, sizeof (nxge_dma_pool_t)); 248544961713Sgirish 2486678453a8Sspeer KMEM_FREE(nxgep->rx_buf_pool_p->num_chunks, 2487678453a8Sspeer sizeof (uint32_t) * rdc_max); 2488678453a8Sspeer KMEM_FREE(nxgep->rx_buf_pool_p->dma_buf_pool_p, 2489678453a8Sspeer sizeof (p_nxge_dma_common_t) * rdc_max); 2490678453a8Sspeer KMEM_FREE(nxgep->rx_buf_pool_p, sizeof (nxge_dma_pool_t)); 249144961713Sgirish 2492678453a8Sspeer nxgep->rx_buf_pool_p = 0; 2493678453a8Sspeer nxgep->rx_cntl_pool_p = 0; 249444961713Sgirish 2495678453a8Sspeer KMEM_FREE(nxgep->rx_rbr_rings->rbr_rings, 2496678453a8Sspeer sizeof (p_rx_rbr_ring_t) * rdc_max); 2497678453a8Sspeer KMEM_FREE(nxgep->rx_rbr_rings, sizeof (rx_rbr_rings_t)); 2498678453a8Sspeer KMEM_FREE(nxgep->rx_rcr_rings->rcr_rings, 2499678453a8Sspeer sizeof (p_rx_rcr_ring_t) * rdc_max); 2500678453a8Sspeer KMEM_FREE(nxgep->rx_rcr_rings, sizeof (rx_rcr_rings_t)); 2501678453a8Sspeer KMEM_FREE(nxgep->rx_mbox_areas_p->rxmbox_areas, 2502678453a8Sspeer sizeof (p_rx_mbox_t) * rdc_max); 2503678453a8Sspeer KMEM_FREE(nxgep->rx_mbox_areas_p, sizeof (rx_mbox_areas_t)); 250444961713Sgirish 2505678453a8Sspeer nxgep->rx_rbr_rings = 0; 2506678453a8Sspeer nxgep->rx_rcr_rings = 0; 2507678453a8Sspeer nxgep->rx_mbox_areas_p = 0; 250844961713Sgirish 250944961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_free_rx_mem_pool")); 251044961713Sgirish } 251144961713Sgirish 251244961713Sgirish 251344961713Sgirish static nxge_status_t 251444961713Sgirish nxge_alloc_rx_buf_dma(p_nxge_t nxgep, uint16_t dma_channel, 251544961713Sgirish p_nxge_dma_common_t *dmap, 251644961713Sgirish size_t alloc_size, size_t block_size, uint32_t *num_chunks) 251744961713Sgirish { 251844961713Sgirish p_nxge_dma_common_t rx_dmap; 251944961713Sgirish nxge_status_t status = NXGE_OK; 252044961713Sgirish size_t total_alloc_size; 252144961713Sgirish size_t allocated = 0; 252244961713Sgirish int i, size_index, array_size; 2523678453a8Sspeer boolean_t use_kmem_alloc = B_FALSE; 252444961713Sgirish 252544961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rx_buf_dma")); 252644961713Sgirish 252744961713Sgirish rx_dmap = (p_nxge_dma_common_t) 25284045d941Ssowmini KMEM_ZALLOC(sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK, 25294045d941Ssowmini KM_SLEEP); 253044961713Sgirish 253144961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 25324045d941Ssowmini " alloc_rx_buf_dma rdc %d asize %x bsize %x bbuf %llx ", 25334045d941Ssowmini dma_channel, alloc_size, block_size, dmap)); 253444961713Sgirish 253544961713Sgirish total_alloc_size = alloc_size; 253644961713Sgirish 253744961713Sgirish #if defined(RX_USE_RECLAIM_POST) 253844961713Sgirish total_alloc_size = alloc_size + alloc_size/4; 253944961713Sgirish #endif 254044961713Sgirish 254144961713Sgirish i = 0; 254244961713Sgirish size_index = 0; 254344961713Sgirish array_size = sizeof (alloc_sizes)/sizeof (size_t); 254444961713Sgirish while ((alloc_sizes[size_index] < alloc_size) && 25454045d941Ssowmini (size_index < array_size)) 25464045d941Ssowmini size_index++; 254744961713Sgirish if (size_index >= array_size) { 254844961713Sgirish size_index = array_size - 1; 254944961713Sgirish } 255044961713Sgirish 2551678453a8Sspeer /* For Neptune, use kmem_alloc if the kmem flag is set. */ 2552678453a8Sspeer if (nxgep->niu_type != N2_NIU && nxge_use_kmem_alloc) { 2553678453a8Sspeer use_kmem_alloc = B_TRUE; 2554678453a8Sspeer #if defined(__i386) || defined(__amd64) 2555678453a8Sspeer size_index = 0; 2556678453a8Sspeer #endif 2557678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2558678453a8Sspeer "==> nxge_alloc_rx_buf_dma: " 2559678453a8Sspeer "Neptune use kmem_alloc() - size_index %d", 2560678453a8Sspeer size_index)); 2561678453a8Sspeer } 2562678453a8Sspeer 256344961713Sgirish while ((allocated < total_alloc_size) && 25644045d941Ssowmini (size_index >= 0) && (i < NXGE_DMA_BLOCK)) { 256544961713Sgirish rx_dmap[i].dma_chunk_index = i; 256644961713Sgirish rx_dmap[i].block_size = block_size; 256744961713Sgirish rx_dmap[i].alength = alloc_sizes[size_index]; 256844961713Sgirish rx_dmap[i].orig_alength = rx_dmap[i].alength; 256944961713Sgirish rx_dmap[i].nblocks = alloc_sizes[size_index] / block_size; 257044961713Sgirish rx_dmap[i].dma_channel = dma_channel; 257144961713Sgirish rx_dmap[i].contig_alloc_type = B_FALSE; 2572678453a8Sspeer rx_dmap[i].kmem_alloc_type = B_FALSE; 2573678453a8Sspeer rx_dmap[i].buf_alloc_type = DDI_MEM_ALLOC; 257444961713Sgirish 257544961713Sgirish /* 257644961713Sgirish * N2/NIU: data buffers must be contiguous as the driver 257744961713Sgirish * needs to call Hypervisor api to set up 257844961713Sgirish * logical pages. 257944961713Sgirish */ 258044961713Sgirish if ((nxgep->niu_type == N2_NIU) && (NXGE_DMA_BLOCK == 1)) { 258144961713Sgirish rx_dmap[i].contig_alloc_type = B_TRUE; 2582678453a8Sspeer rx_dmap[i].buf_alloc_type = CONTIG_MEM_ALLOC; 2583678453a8Sspeer } else if (use_kmem_alloc) { 2584678453a8Sspeer /* For Neptune, use kmem_alloc */ 2585678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2586678453a8Sspeer "==> nxge_alloc_rx_buf_dma: " 2587678453a8Sspeer "Neptune use kmem_alloc()")); 2588678453a8Sspeer rx_dmap[i].kmem_alloc_type = B_TRUE; 2589678453a8Sspeer rx_dmap[i].buf_alloc_type = KMEM_ALLOC; 259044961713Sgirish } 259144961713Sgirish 259244961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 25934045d941Ssowmini "alloc_rx_buf_dma rdc %d chunk %d bufp %llx size %x " 25944045d941Ssowmini "i %d nblocks %d alength %d", 25954045d941Ssowmini dma_channel, i, &rx_dmap[i], block_size, 25964045d941Ssowmini i, rx_dmap[i].nblocks, 25974045d941Ssowmini rx_dmap[i].alength)); 259844961713Sgirish status = nxge_dma_mem_alloc(nxgep, nxge_force_dma, 25994045d941Ssowmini &nxge_rx_dma_attr, 26004045d941Ssowmini rx_dmap[i].alength, 26014045d941Ssowmini &nxge_dev_buf_dma_acc_attr, 26024045d941Ssowmini DDI_DMA_READ | DDI_DMA_STREAMING, 26034045d941Ssowmini (p_nxge_dma_common_t)(&rx_dmap[i])); 260444961713Sgirish if (status != NXGE_OK) { 260544961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2606678453a8Sspeer "nxge_alloc_rx_buf_dma: Alloc Failed: " 2607678453a8Sspeer "dma %d size_index %d size requested %d", 2608678453a8Sspeer dma_channel, 2609678453a8Sspeer size_index, 2610678453a8Sspeer rx_dmap[i].alength)); 261144961713Sgirish size_index--; 261244961713Sgirish } else { 2613678453a8Sspeer rx_dmap[i].buf_alloc_state = BUF_ALLOCATED; 2614678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2615678453a8Sspeer " nxge_alloc_rx_buf_dma DONE alloc mem: " 2616678453a8Sspeer "dma %d dma_buf_p $%p kaddrp $%p alength %d " 2617678453a8Sspeer "buf_alloc_state %d alloc_type %d", 2618678453a8Sspeer dma_channel, 2619678453a8Sspeer &rx_dmap[i], 2620678453a8Sspeer rx_dmap[i].kaddrp, 2621678453a8Sspeer rx_dmap[i].alength, 2622678453a8Sspeer rx_dmap[i].buf_alloc_state, 2623678453a8Sspeer rx_dmap[i].buf_alloc_type)); 2624678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2625678453a8Sspeer " alloc_rx_buf_dma allocated rdc %d " 2626678453a8Sspeer "chunk %d size %x dvma %x bufp %llx kaddrp $%p", 2627678453a8Sspeer dma_channel, i, rx_dmap[i].alength, 2628678453a8Sspeer rx_dmap[i].ioaddr_pp, &rx_dmap[i], 2629678453a8Sspeer rx_dmap[i].kaddrp)); 263044961713Sgirish i++; 263144961713Sgirish allocated += alloc_sizes[size_index]; 263244961713Sgirish } 263344961713Sgirish } 263444961713Sgirish 263544961713Sgirish if (allocated < total_alloc_size) { 263630ac2e7bSml NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2637678453a8Sspeer "==> nxge_alloc_rx_buf_dma: not enough for channel %d " 263830ac2e7bSml "allocated 0x%x requested 0x%x", 263930ac2e7bSml dma_channel, 264030ac2e7bSml allocated, total_alloc_size)); 264130ac2e7bSml status = NXGE_ERROR; 264244961713Sgirish goto nxge_alloc_rx_mem_fail1; 264344961713Sgirish } 264444961713Sgirish 264530ac2e7bSml NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2646678453a8Sspeer "==> nxge_alloc_rx_buf_dma: Allocated for channel %d " 264730ac2e7bSml "allocated 0x%x requested 0x%x", 264830ac2e7bSml dma_channel, 264930ac2e7bSml allocated, total_alloc_size)); 265030ac2e7bSml 265144961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 26524045d941Ssowmini " alloc_rx_buf_dma rdc %d allocated %d chunks", 26534045d941Ssowmini dma_channel, i)); 265444961713Sgirish *num_chunks = i; 265544961713Sgirish *dmap = rx_dmap; 265644961713Sgirish 265744961713Sgirish goto nxge_alloc_rx_mem_exit; 265844961713Sgirish 265944961713Sgirish nxge_alloc_rx_mem_fail1: 266044961713Sgirish KMEM_FREE(rx_dmap, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK); 266144961713Sgirish 266244961713Sgirish nxge_alloc_rx_mem_exit: 266344961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 26644045d941Ssowmini "<== nxge_alloc_rx_buf_dma status 0x%08x", status)); 266544961713Sgirish 266644961713Sgirish return (status); 266744961713Sgirish } 266844961713Sgirish 266944961713Sgirish /*ARGSUSED*/ 267044961713Sgirish static void 267144961713Sgirish nxge_free_rx_buf_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap, 267244961713Sgirish uint32_t num_chunks) 267344961713Sgirish { 267444961713Sgirish int i; 267544961713Sgirish 267644961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 26774045d941Ssowmini "==> nxge_free_rx_buf_dma: # of chunks %d", num_chunks)); 267844961713Sgirish 2679678453a8Sspeer if (dmap == 0) 2680678453a8Sspeer return; 2681678453a8Sspeer 268244961713Sgirish for (i = 0; i < num_chunks; i++) { 268344961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 26844045d941Ssowmini "==> nxge_free_rx_buf_dma: chunk %d dmap 0x%llx", 26854045d941Ssowmini i, dmap)); 2686678453a8Sspeer nxge_dma_free_rx_data_buf(dmap++); 268744961713Sgirish } 268844961713Sgirish 268944961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_free_rx_buf_dma")); 269044961713Sgirish } 269144961713Sgirish 269244961713Sgirish /*ARGSUSED*/ 269344961713Sgirish static nxge_status_t 269444961713Sgirish nxge_alloc_rx_cntl_dma(p_nxge_t nxgep, uint16_t dma_channel, 269544961713Sgirish p_nxge_dma_common_t *dmap, size_t size) 269644961713Sgirish { 269744961713Sgirish p_nxge_dma_common_t rx_dmap; 269844961713Sgirish nxge_status_t status = NXGE_OK; 269944961713Sgirish 270044961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rx_cntl_dma")); 270144961713Sgirish 270244961713Sgirish rx_dmap = (p_nxge_dma_common_t) 27034045d941Ssowmini KMEM_ZALLOC(sizeof (nxge_dma_common_t), KM_SLEEP); 270444961713Sgirish 270544961713Sgirish rx_dmap->contig_alloc_type = B_FALSE; 2706678453a8Sspeer rx_dmap->kmem_alloc_type = B_FALSE; 270744961713Sgirish 270844961713Sgirish status = nxge_dma_mem_alloc(nxgep, nxge_force_dma, 27094045d941Ssowmini &nxge_desc_dma_attr, 27104045d941Ssowmini size, 27114045d941Ssowmini &nxge_dev_desc_dma_acc_attr, 27124045d941Ssowmini DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 27134045d941Ssowmini rx_dmap); 271444961713Sgirish if (status != NXGE_OK) { 271544961713Sgirish goto nxge_alloc_rx_cntl_dma_fail1; 271644961713Sgirish } 271744961713Sgirish 271844961713Sgirish *dmap = rx_dmap; 271944961713Sgirish goto nxge_alloc_rx_cntl_dma_exit; 272044961713Sgirish 272144961713Sgirish nxge_alloc_rx_cntl_dma_fail1: 272244961713Sgirish KMEM_FREE(rx_dmap, sizeof (nxge_dma_common_t)); 272344961713Sgirish 272444961713Sgirish nxge_alloc_rx_cntl_dma_exit: 272544961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 27264045d941Ssowmini "<== nxge_alloc_rx_cntl_dma status 0x%08x", status)); 272744961713Sgirish 2728678453a8Sspeer return (status); 2729678453a8Sspeer } 2730678453a8Sspeer 2731678453a8Sspeer /*ARGSUSED*/ 2732678453a8Sspeer static void 2733678453a8Sspeer nxge_free_rx_cntl_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap) 2734678453a8Sspeer { 2735678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_free_rx_cntl_dma")); 2736678453a8Sspeer 2737678453a8Sspeer if (dmap == 0) 2738678453a8Sspeer return; 2739678453a8Sspeer 2740678453a8Sspeer nxge_dma_mem_free(dmap); 2741678453a8Sspeer 2742678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_free_rx_cntl_dma")); 2743678453a8Sspeer } 2744678453a8Sspeer 2745678453a8Sspeer typedef struct { 2746678453a8Sspeer size_t tx_size; 2747678453a8Sspeer size_t cr_size; 2748678453a8Sspeer size_t threshhold; 2749678453a8Sspeer } nxge_tdc_sizes_t; 2750678453a8Sspeer 2751678453a8Sspeer static 2752678453a8Sspeer nxge_status_t 2753678453a8Sspeer nxge_tdc_sizes( 2754678453a8Sspeer nxge_t *nxgep, 2755678453a8Sspeer nxge_tdc_sizes_t *sizes) 2756678453a8Sspeer { 2757678453a8Sspeer uint32_t threshhold; /* The bcopy() threshhold */ 2758678453a8Sspeer size_t tx_size; /* Transmit buffer size */ 2759678453a8Sspeer size_t cr_size; /* Completion ring size */ 2760678453a8Sspeer 2761678453a8Sspeer /* 2762678453a8Sspeer * Assume that each DMA channel will be configured with the 2763678453a8Sspeer * default transmit buffer size for copying transmit data. 2764678453a8Sspeer * (If a packet is bigger than this, it will not be copied.) 2765678453a8Sspeer */ 2766678453a8Sspeer if (nxgep->niu_type == N2_NIU) { 2767678453a8Sspeer threshhold = TX_BCOPY_SIZE; 2768678453a8Sspeer } else { 2769678453a8Sspeer threshhold = nxge_bcopy_thresh; 2770678453a8Sspeer } 2771678453a8Sspeer tx_size = nxge_tx_ring_size * threshhold; 2772678453a8Sspeer 2773678453a8Sspeer cr_size = nxge_tx_ring_size * sizeof (tx_desc_t); 2774678453a8Sspeer cr_size += sizeof (txdma_mailbox_t); 2775678453a8Sspeer 2776678453a8Sspeer #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 2777678453a8Sspeer if (nxgep->niu_type == N2_NIU) { 2778678453a8Sspeer if (!ISP2(tx_size)) { 2779678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 27804045d941Ssowmini "==> nxge_tdc_sizes: Tx size" 27814045d941Ssowmini " must be power of 2")); 2782678453a8Sspeer return (NXGE_ERROR); 2783678453a8Sspeer } 2784678453a8Sspeer 2785678453a8Sspeer if (tx_size > (1 << 22)) { 2786678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 27874045d941Ssowmini "==> nxge_tdc_sizes: Tx size" 27884045d941Ssowmini " limited to 4M")); 2789678453a8Sspeer return (NXGE_ERROR); 2790678453a8Sspeer } 2791678453a8Sspeer 2792678453a8Sspeer if (cr_size < 0x2000) 2793678453a8Sspeer cr_size = 0x2000; 2794678453a8Sspeer } 2795678453a8Sspeer #endif 2796678453a8Sspeer 2797678453a8Sspeer sizes->threshhold = threshhold; 2798678453a8Sspeer sizes->tx_size = tx_size; 2799678453a8Sspeer sizes->cr_size = cr_size; 2800678453a8Sspeer 2801678453a8Sspeer return (NXGE_OK); 2802678453a8Sspeer } 2803678453a8Sspeer /* 2804678453a8Sspeer * nxge_alloc_txb 2805678453a8Sspeer * 2806678453a8Sspeer * Allocate buffers for an TDC. 2807678453a8Sspeer * 2808678453a8Sspeer * Arguments: 2809678453a8Sspeer * nxgep 2810678453a8Sspeer * channel The channel to map into our kernel space. 2811678453a8Sspeer * 2812678453a8Sspeer * Notes: 2813678453a8Sspeer * 2814678453a8Sspeer * NPI function calls: 2815678453a8Sspeer * 2816678453a8Sspeer * NXGE function calls: 2817678453a8Sspeer * 2818678453a8Sspeer * Registers accessed: 2819678453a8Sspeer * 2820678453a8Sspeer * Context: 2821678453a8Sspeer * 2822678453a8Sspeer * Taking apart: 2823678453a8Sspeer * 2824678453a8Sspeer * Open questions: 2825678453a8Sspeer * 2826678453a8Sspeer */ 2827678453a8Sspeer nxge_status_t 2828678453a8Sspeer nxge_alloc_txb( 2829678453a8Sspeer p_nxge_t nxgep, 2830678453a8Sspeer int channel) 2831678453a8Sspeer { 2832678453a8Sspeer nxge_dma_common_t **dma_buf_p; 2833678453a8Sspeer nxge_dma_common_t **dma_cntl_p; 2834678453a8Sspeer uint32_t *num_chunks; 2835678453a8Sspeer nxge_status_t status = NXGE_OK; 2836678453a8Sspeer 2837678453a8Sspeer nxge_tdc_sizes_t sizes; 2838678453a8Sspeer 2839678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_tbb")); 2840678453a8Sspeer 2841678453a8Sspeer if (nxge_tdc_sizes(nxgep, &sizes) != NXGE_OK) 2842678453a8Sspeer return (NXGE_ERROR); 2843678453a8Sspeer 2844678453a8Sspeer /* 2845678453a8Sspeer * Allocate memory for transmit buffers and descriptor rings. 2846678453a8Sspeer * Replace these allocation functions with the interface functions 2847678453a8Sspeer * provided by the partition manager Real Soon Now. 2848678453a8Sspeer */ 2849678453a8Sspeer dma_buf_p = &nxgep->tx_buf_pool_p->dma_buf_pool_p[channel]; 2850678453a8Sspeer num_chunks = &nxgep->tx_buf_pool_p->num_chunks[channel]; 2851678453a8Sspeer 2852678453a8Sspeer dma_cntl_p = &nxgep->tx_cntl_pool_p->dma_buf_pool_p[channel]; 2853678453a8Sspeer 2854678453a8Sspeer /* 2855678453a8Sspeer * Allocate memory for transmit buffers and descriptor rings. 2856678453a8Sspeer * Replace allocation functions with interface functions provided 2857678453a8Sspeer * by the partition manager when it is available. 2858678453a8Sspeer * 2859678453a8Sspeer * Allocate memory for the transmit buffer pool. 2860678453a8Sspeer */ 2861678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, 28624045d941Ssowmini "sizes: tx: %ld, cr:%ld, th:%ld", 28634045d941Ssowmini sizes.tx_size, sizes.cr_size, sizes.threshhold)); 2864678453a8Sspeer 2865678453a8Sspeer *num_chunks = 0; 2866678453a8Sspeer status = nxge_alloc_tx_buf_dma(nxgep, channel, dma_buf_p, 2867678453a8Sspeer sizes.tx_size, sizes.threshhold, num_chunks); 2868678453a8Sspeer if (status != NXGE_OK) { 2869678453a8Sspeer cmn_err(CE_NOTE, "nxge_alloc_tx_buf_dma failed!"); 2870678453a8Sspeer return (status); 2871678453a8Sspeer } 2872678453a8Sspeer 2873678453a8Sspeer /* 2874678453a8Sspeer * Allocate memory for descriptor rings and mailbox. 2875678453a8Sspeer */ 2876678453a8Sspeer status = nxge_alloc_tx_cntl_dma(nxgep, channel, dma_cntl_p, 2877678453a8Sspeer sizes.cr_size); 2878678453a8Sspeer if (status != NXGE_OK) { 2879678453a8Sspeer nxge_free_tx_buf_dma(nxgep, *dma_buf_p, *num_chunks); 2880678453a8Sspeer cmn_err(CE_NOTE, "nxge_alloc_tx_cntl_dma failed!"); 2881678453a8Sspeer return (status); 2882678453a8Sspeer } 2883678453a8Sspeer 2884678453a8Sspeer return (NXGE_OK); 2885678453a8Sspeer } 2886678453a8Sspeer 2887678453a8Sspeer void 2888678453a8Sspeer nxge_free_txb( 2889678453a8Sspeer p_nxge_t nxgep, 2890678453a8Sspeer int channel) 2891678453a8Sspeer { 2892678453a8Sspeer nxge_dma_common_t *data; 2893678453a8Sspeer nxge_dma_common_t *control; 2894678453a8Sspeer uint32_t num_chunks; 2895678453a8Sspeer 2896678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_free_txb")); 2897678453a8Sspeer 2898678453a8Sspeer data = nxgep->tx_buf_pool_p->dma_buf_pool_p[channel]; 2899678453a8Sspeer num_chunks = nxgep->tx_buf_pool_p->num_chunks[channel]; 2900678453a8Sspeer nxge_free_tx_buf_dma(nxgep, data, num_chunks); 2901678453a8Sspeer 2902678453a8Sspeer nxgep->tx_buf_pool_p->dma_buf_pool_p[channel] = 0; 2903678453a8Sspeer nxgep->tx_buf_pool_p->num_chunks[channel] = 0; 2904678453a8Sspeer 2905678453a8Sspeer control = nxgep->tx_cntl_pool_p->dma_buf_pool_p[channel]; 2906678453a8Sspeer nxge_free_tx_cntl_dma(nxgep, control); 290744961713Sgirish 2908678453a8Sspeer nxgep->tx_cntl_pool_p->dma_buf_pool_p[channel] = 0; 290944961713Sgirish 2910678453a8Sspeer KMEM_FREE(data, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK); 2911678453a8Sspeer KMEM_FREE(control, sizeof (nxge_dma_common_t)); 291244961713Sgirish 2913678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_free_txb")); 291444961713Sgirish } 291544961713Sgirish 2916678453a8Sspeer /* 2917678453a8Sspeer * nxge_alloc_tx_mem_pool 2918678453a8Sspeer * 2919678453a8Sspeer * This function allocates all of the per-port TDC control data structures. 2920678453a8Sspeer * The per-channel (TDC) data structures are allocated when needed. 2921678453a8Sspeer * 2922678453a8Sspeer * Arguments: 2923678453a8Sspeer * nxgep 2924678453a8Sspeer * 2925678453a8Sspeer * Notes: 2926678453a8Sspeer * 2927678453a8Sspeer * Context: 2928678453a8Sspeer * Any domain 2929678453a8Sspeer */ 2930678453a8Sspeer nxge_status_t 293144961713Sgirish nxge_alloc_tx_mem_pool(p_nxge_t nxgep) 293244961713Sgirish { 2933678453a8Sspeer nxge_hw_pt_cfg_t *p_cfgp; 2934678453a8Sspeer nxge_dma_pool_t *dma_poolp; 2935678453a8Sspeer nxge_dma_common_t **dma_buf_p; 2936678453a8Sspeer nxge_dma_pool_t *dma_cntl_poolp; 2937678453a8Sspeer nxge_dma_common_t **dma_cntl_p; 293844961713Sgirish uint32_t *num_chunks; /* per dma */ 2939678453a8Sspeer int tdc_max; 294044961713Sgirish 294144961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM_CTL, "==> nxge_alloc_tx_mem_pool")); 294244961713Sgirish 2943678453a8Sspeer p_cfgp = &nxgep->pt_config.hw_config; 2944678453a8Sspeer tdc_max = NXGE_MAX_TDCS; 294544961713Sgirish 294644961713Sgirish /* 294744961713Sgirish * Allocate memory for each transmit DMA channel. 294844961713Sgirish */ 294944961713Sgirish dma_poolp = (p_nxge_dma_pool_t)KMEM_ZALLOC(sizeof (nxge_dma_pool_t), 29504045d941Ssowmini KM_SLEEP); 295144961713Sgirish dma_buf_p = (p_nxge_dma_common_t *)KMEM_ZALLOC( 29524045d941Ssowmini sizeof (p_nxge_dma_common_t) * tdc_max, KM_SLEEP); 295344961713Sgirish 295444961713Sgirish dma_cntl_poolp = (p_nxge_dma_pool_t) 29554045d941Ssowmini KMEM_ZALLOC(sizeof (nxge_dma_pool_t), KM_SLEEP); 295644961713Sgirish dma_cntl_p = (p_nxge_dma_common_t *)KMEM_ZALLOC( 29574045d941Ssowmini sizeof (p_nxge_dma_common_t) * tdc_max, KM_SLEEP); 295844961713Sgirish 295930ac2e7bSml if (nxge_tx_ring_size > TDC_DEFAULT_MAX) { 296030ac2e7bSml NXGE_DEBUG_MSG((nxgep, MEM_CTL, 296130ac2e7bSml "nxge_alloc_tx_mem_pool: TDC too high %d, " 296230ac2e7bSml "set to default %d", 296330ac2e7bSml nxge_tx_ring_size, TDC_DEFAULT_MAX)); 296430ac2e7bSml nxge_tx_ring_size = TDC_DEFAULT_MAX; 296530ac2e7bSml } 296630ac2e7bSml 296744961713Sgirish #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 296844961713Sgirish /* 296944961713Sgirish * N2/NIU has limitation on the descriptor sizes (contiguous 297044961713Sgirish * memory allocation on data buffers to 4M (contig_mem_alloc) 297144961713Sgirish * and little endian for control buffers (must use the ddi/dki mem alloc 297244961713Sgirish * function). The transmit ring is limited to 8K (includes the 297344961713Sgirish * mailbox). 297444961713Sgirish */ 297544961713Sgirish if (nxgep->niu_type == N2_NIU) { 297644961713Sgirish if ((nxge_tx_ring_size > NXGE_NIU_CONTIG_TX_MAX) || 29774045d941Ssowmini (!ISP2(nxge_tx_ring_size))) { 297844961713Sgirish nxge_tx_ring_size = NXGE_NIU_CONTIG_TX_MAX; 297944961713Sgirish } 298044961713Sgirish } 298144961713Sgirish #endif 298244961713Sgirish 298344961713Sgirish nxgep->nxge_port_tx_ring_size = nxge_tx_ring_size; 298444961713Sgirish 298544961713Sgirish num_chunks = (uint32_t *)KMEM_ZALLOC( 29864045d941Ssowmini sizeof (uint32_t) * tdc_max, KM_SLEEP); 298744961713Sgirish 2988678453a8Sspeer dma_poolp->ndmas = p_cfgp->tdc.owned; 298944961713Sgirish dma_poolp->num_chunks = num_chunks; 299044961713Sgirish dma_poolp->dma_buf_pool_p = dma_buf_p; 299144961713Sgirish nxgep->tx_buf_pool_p = dma_poolp; 299244961713Sgirish 2993678453a8Sspeer dma_poolp->buf_allocated = B_TRUE; 2994678453a8Sspeer 2995678453a8Sspeer dma_cntl_poolp->ndmas = p_cfgp->tdc.owned; 299644961713Sgirish dma_cntl_poolp->dma_buf_pool_p = dma_cntl_p; 299744961713Sgirish nxgep->tx_cntl_pool_p = dma_cntl_poolp; 299844961713Sgirish 2999678453a8Sspeer dma_cntl_poolp->buf_allocated = B_TRUE; 300044961713Sgirish 3001678453a8Sspeer nxgep->tx_rings = 3002678453a8Sspeer KMEM_ZALLOC(sizeof (tx_rings_t), KM_SLEEP); 3003678453a8Sspeer nxgep->tx_rings->rings = 3004678453a8Sspeer KMEM_ZALLOC(sizeof (p_tx_ring_t) * tdc_max, KM_SLEEP); 3005678453a8Sspeer nxgep->tx_mbox_areas_p = 3006678453a8Sspeer KMEM_ZALLOC(sizeof (tx_mbox_areas_t), KM_SLEEP); 3007678453a8Sspeer nxgep->tx_mbox_areas_p->txmbox_areas_p = 3008678453a8Sspeer KMEM_ZALLOC(sizeof (p_tx_mbox_t) * tdc_max, KM_SLEEP); 300944961713Sgirish 3010678453a8Sspeer nxgep->tx_rings->ndmas = p_cfgp->tdc.owned; 301144961713Sgirish 301244961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM_CTL, 30134045d941Ssowmini "==> nxge_alloc_tx_mem_pool: ndmas %d poolp->ndmas %d", 30144045d941Ssowmini tdc_max, dma_poolp->ndmas)); 301544961713Sgirish 3016678453a8Sspeer return (NXGE_OK); 301744961713Sgirish } 301844961713Sgirish 3019678453a8Sspeer nxge_status_t 302044961713Sgirish nxge_alloc_tx_buf_dma(p_nxge_t nxgep, uint16_t dma_channel, 302144961713Sgirish p_nxge_dma_common_t *dmap, size_t alloc_size, 302244961713Sgirish size_t block_size, uint32_t *num_chunks) 302344961713Sgirish { 302444961713Sgirish p_nxge_dma_common_t tx_dmap; 302544961713Sgirish nxge_status_t status = NXGE_OK; 302644961713Sgirish size_t total_alloc_size; 302744961713Sgirish size_t allocated = 0; 302844961713Sgirish int i, size_index, array_size; 302944961713Sgirish 303044961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_tx_buf_dma")); 303144961713Sgirish 303244961713Sgirish tx_dmap = (p_nxge_dma_common_t) 30334045d941Ssowmini KMEM_ZALLOC(sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK, 30344045d941Ssowmini KM_SLEEP); 303544961713Sgirish 303644961713Sgirish total_alloc_size = alloc_size; 303744961713Sgirish i = 0; 303844961713Sgirish size_index = 0; 303944961713Sgirish array_size = sizeof (alloc_sizes) / sizeof (size_t); 304044961713Sgirish while ((alloc_sizes[size_index] < alloc_size) && 30414045d941Ssowmini (size_index < array_size)) 304244961713Sgirish size_index++; 304344961713Sgirish if (size_index >= array_size) { 304444961713Sgirish size_index = array_size - 1; 304544961713Sgirish } 304644961713Sgirish 304744961713Sgirish while ((allocated < total_alloc_size) && 30484045d941Ssowmini (size_index >= 0) && (i < NXGE_DMA_BLOCK)) { 304944961713Sgirish 305044961713Sgirish tx_dmap[i].dma_chunk_index = i; 305144961713Sgirish tx_dmap[i].block_size = block_size; 305244961713Sgirish tx_dmap[i].alength = alloc_sizes[size_index]; 305344961713Sgirish tx_dmap[i].orig_alength = tx_dmap[i].alength; 305444961713Sgirish tx_dmap[i].nblocks = alloc_sizes[size_index] / block_size; 305544961713Sgirish tx_dmap[i].dma_channel = dma_channel; 305644961713Sgirish tx_dmap[i].contig_alloc_type = B_FALSE; 3057678453a8Sspeer tx_dmap[i].kmem_alloc_type = B_FALSE; 305844961713Sgirish 305944961713Sgirish /* 306044961713Sgirish * N2/NIU: data buffers must be contiguous as the driver 306144961713Sgirish * needs to call Hypervisor api to set up 306244961713Sgirish * logical pages. 306344961713Sgirish */ 306444961713Sgirish if ((nxgep->niu_type == N2_NIU) && (NXGE_DMA_BLOCK == 1)) { 306544961713Sgirish tx_dmap[i].contig_alloc_type = B_TRUE; 306644961713Sgirish } 306744961713Sgirish 306844961713Sgirish status = nxge_dma_mem_alloc(nxgep, nxge_force_dma, 30694045d941Ssowmini &nxge_tx_dma_attr, 30704045d941Ssowmini tx_dmap[i].alength, 30714045d941Ssowmini &nxge_dev_buf_dma_acc_attr, 30724045d941Ssowmini DDI_DMA_WRITE | DDI_DMA_STREAMING, 30734045d941Ssowmini (p_nxge_dma_common_t)(&tx_dmap[i])); 307444961713Sgirish if (status != NXGE_OK) { 307544961713Sgirish size_index--; 307644961713Sgirish } else { 307744961713Sgirish i++; 307844961713Sgirish allocated += alloc_sizes[size_index]; 307944961713Sgirish } 308044961713Sgirish } 308144961713Sgirish 308244961713Sgirish if (allocated < total_alloc_size) { 308330ac2e7bSml NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 308430ac2e7bSml "==> nxge_alloc_tx_buf_dma: not enough channel %d: " 308530ac2e7bSml "allocated 0x%x requested 0x%x", 308630ac2e7bSml dma_channel, 308730ac2e7bSml allocated, total_alloc_size)); 308830ac2e7bSml status = NXGE_ERROR; 308944961713Sgirish goto nxge_alloc_tx_mem_fail1; 309044961713Sgirish } 309144961713Sgirish 309230ac2e7bSml NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 309330ac2e7bSml "==> nxge_alloc_tx_buf_dma: Allocated for channel %d: " 309430ac2e7bSml "allocated 0x%x requested 0x%x", 309530ac2e7bSml dma_channel, 309630ac2e7bSml allocated, total_alloc_size)); 309730ac2e7bSml 309844961713Sgirish *num_chunks = i; 309944961713Sgirish *dmap = tx_dmap; 310044961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 31014045d941Ssowmini "==> nxge_alloc_tx_buf_dma dmap 0x%016llx num chunks %d", 31024045d941Ssowmini *dmap, i)); 310344961713Sgirish goto nxge_alloc_tx_mem_exit; 310444961713Sgirish 310544961713Sgirish nxge_alloc_tx_mem_fail1: 310644961713Sgirish KMEM_FREE(tx_dmap, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK); 310744961713Sgirish 310844961713Sgirish nxge_alloc_tx_mem_exit: 310944961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 31104045d941Ssowmini "<== nxge_alloc_tx_buf_dma status 0x%08x", status)); 311144961713Sgirish 311244961713Sgirish return (status); 311344961713Sgirish } 311444961713Sgirish 311544961713Sgirish /*ARGSUSED*/ 311644961713Sgirish static void 311744961713Sgirish nxge_free_tx_buf_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap, 311844961713Sgirish uint32_t num_chunks) 311944961713Sgirish { 312044961713Sgirish int i; 312144961713Sgirish 312244961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM_CTL, "==> nxge_free_tx_buf_dma")); 312344961713Sgirish 3124678453a8Sspeer if (dmap == 0) 3125678453a8Sspeer return; 3126678453a8Sspeer 312744961713Sgirish for (i = 0; i < num_chunks; i++) { 312844961713Sgirish nxge_dma_mem_free(dmap++); 312944961713Sgirish } 313044961713Sgirish 313144961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM_CTL, "<== nxge_free_tx_buf_dma")); 313244961713Sgirish } 313344961713Sgirish 313444961713Sgirish /*ARGSUSED*/ 3135678453a8Sspeer nxge_status_t 313644961713Sgirish nxge_alloc_tx_cntl_dma(p_nxge_t nxgep, uint16_t dma_channel, 313744961713Sgirish p_nxge_dma_common_t *dmap, size_t size) 313844961713Sgirish { 313944961713Sgirish p_nxge_dma_common_t tx_dmap; 314044961713Sgirish nxge_status_t status = NXGE_OK; 314144961713Sgirish 314244961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_tx_cntl_dma")); 314344961713Sgirish tx_dmap = (p_nxge_dma_common_t) 31444045d941Ssowmini KMEM_ZALLOC(sizeof (nxge_dma_common_t), KM_SLEEP); 314544961713Sgirish 314644961713Sgirish tx_dmap->contig_alloc_type = B_FALSE; 3147678453a8Sspeer tx_dmap->kmem_alloc_type = B_FALSE; 314844961713Sgirish 314944961713Sgirish status = nxge_dma_mem_alloc(nxgep, nxge_force_dma, 31504045d941Ssowmini &nxge_desc_dma_attr, 31514045d941Ssowmini size, 31524045d941Ssowmini &nxge_dev_desc_dma_acc_attr, 31534045d941Ssowmini DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 31544045d941Ssowmini tx_dmap); 315544961713Sgirish if (status != NXGE_OK) { 315644961713Sgirish goto nxge_alloc_tx_cntl_dma_fail1; 315744961713Sgirish } 315844961713Sgirish 315944961713Sgirish *dmap = tx_dmap; 316044961713Sgirish goto nxge_alloc_tx_cntl_dma_exit; 316144961713Sgirish 316244961713Sgirish nxge_alloc_tx_cntl_dma_fail1: 316344961713Sgirish KMEM_FREE(tx_dmap, sizeof (nxge_dma_common_t)); 316444961713Sgirish 316544961713Sgirish nxge_alloc_tx_cntl_dma_exit: 316644961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 31674045d941Ssowmini "<== nxge_alloc_tx_cntl_dma status 0x%08x", status)); 316844961713Sgirish 316944961713Sgirish return (status); 317044961713Sgirish } 317144961713Sgirish 317244961713Sgirish /*ARGSUSED*/ 317344961713Sgirish static void 317444961713Sgirish nxge_free_tx_cntl_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap) 317544961713Sgirish { 317644961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_free_tx_cntl_dma")); 317744961713Sgirish 3178678453a8Sspeer if (dmap == 0) 3179678453a8Sspeer return; 3180678453a8Sspeer 318144961713Sgirish nxge_dma_mem_free(dmap); 318244961713Sgirish 318344961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_free_tx_cntl_dma")); 318444961713Sgirish } 318544961713Sgirish 3186678453a8Sspeer /* 3187678453a8Sspeer * nxge_free_tx_mem_pool 3188678453a8Sspeer * 3189678453a8Sspeer * This function frees all of the per-port TDC control data structures. 3190678453a8Sspeer * The per-channel (TDC) data structures are freed when the channel 3191678453a8Sspeer * is stopped. 3192678453a8Sspeer * 3193678453a8Sspeer * Arguments: 3194678453a8Sspeer * nxgep 3195678453a8Sspeer * 3196678453a8Sspeer * Notes: 3197678453a8Sspeer * 3198678453a8Sspeer * Context: 3199678453a8Sspeer * Any domain 3200678453a8Sspeer */ 320144961713Sgirish static void 320244961713Sgirish nxge_free_tx_mem_pool(p_nxge_t nxgep) 320344961713Sgirish { 3204678453a8Sspeer int tdc_max = NXGE_MAX_TDCS; 320544961713Sgirish 3206678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_free_tx_mem_pool")); 320744961713Sgirish 3208678453a8Sspeer if (!nxgep->tx_buf_pool_p || !nxgep->tx_buf_pool_p->buf_allocated) { 3209678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 32104045d941Ssowmini "<== nxge_free_tx_mem_pool " 32114045d941Ssowmini "(null tx buf pool or buf not allocated")); 321244961713Sgirish return; 321344961713Sgirish } 3214678453a8Sspeer if (!nxgep->tx_cntl_pool_p || !nxgep->tx_cntl_pool_p->buf_allocated) { 3215678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 32164045d941Ssowmini "<== nxge_free_tx_mem_pool " 32174045d941Ssowmini "(null tx cntl buf pool or cntl buf not allocated")); 321844961713Sgirish return; 321944961713Sgirish } 322044961713Sgirish 3221678453a8Sspeer /* 1. Free the mailboxes. */ 3222678453a8Sspeer KMEM_FREE(nxgep->tx_mbox_areas_p->txmbox_areas_p, 3223678453a8Sspeer sizeof (p_tx_mbox_t) * tdc_max); 3224678453a8Sspeer KMEM_FREE(nxgep->tx_mbox_areas_p, sizeof (tx_mbox_areas_t)); 322544961713Sgirish 3226678453a8Sspeer nxgep->tx_mbox_areas_p = 0; 322744961713Sgirish 3228678453a8Sspeer /* 2. Free the transmit ring arrays. */ 3229678453a8Sspeer KMEM_FREE(nxgep->tx_rings->rings, 3230678453a8Sspeer sizeof (p_tx_ring_t) * tdc_max); 3231678453a8Sspeer KMEM_FREE(nxgep->tx_rings, sizeof (tx_rings_t)); 323244961713Sgirish 3233678453a8Sspeer nxgep->tx_rings = 0; 323444961713Sgirish 3235678453a8Sspeer /* 3. Free the completion ring data structures. */ 3236678453a8Sspeer KMEM_FREE(nxgep->tx_cntl_pool_p->dma_buf_pool_p, 3237678453a8Sspeer sizeof (p_nxge_dma_common_t) * tdc_max); 3238678453a8Sspeer KMEM_FREE(nxgep->tx_cntl_pool_p, sizeof (nxge_dma_pool_t)); 323944961713Sgirish 3240678453a8Sspeer nxgep->tx_cntl_pool_p = 0; 324144961713Sgirish 3242678453a8Sspeer /* 4. Free the data ring data structures. */ 3243678453a8Sspeer KMEM_FREE(nxgep->tx_buf_pool_p->num_chunks, 3244678453a8Sspeer sizeof (uint32_t) * tdc_max); 3245678453a8Sspeer KMEM_FREE(nxgep->tx_buf_pool_p->dma_buf_pool_p, 3246678453a8Sspeer sizeof (p_nxge_dma_common_t) * tdc_max); 3247678453a8Sspeer KMEM_FREE(nxgep->tx_buf_pool_p, sizeof (nxge_dma_pool_t)); 324844961713Sgirish 3249678453a8Sspeer nxgep->tx_buf_pool_p = 0; 3250678453a8Sspeer 3251678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_free_tx_mem_pool")); 325244961713Sgirish } 325344961713Sgirish 325444961713Sgirish /*ARGSUSED*/ 325544961713Sgirish static nxge_status_t 325644961713Sgirish nxge_dma_mem_alloc(p_nxge_t nxgep, dma_method_t method, 325744961713Sgirish struct ddi_dma_attr *dma_attrp, 325844961713Sgirish size_t length, ddi_device_acc_attr_t *acc_attr_p, uint_t xfer_flags, 325944961713Sgirish p_nxge_dma_common_t dma_p) 326044961713Sgirish { 326144961713Sgirish caddr_t kaddrp; 326244961713Sgirish int ddi_status = DDI_SUCCESS; 326344961713Sgirish boolean_t contig_alloc_type; 3264678453a8Sspeer boolean_t kmem_alloc_type; 326544961713Sgirish 326644961713Sgirish contig_alloc_type = dma_p->contig_alloc_type; 326744961713Sgirish 326844961713Sgirish if (contig_alloc_type && (nxgep->niu_type != N2_NIU)) { 326944961713Sgirish /* 327044961713Sgirish * contig_alloc_type for contiguous memory only allowed 327144961713Sgirish * for N2/NIU. 327244961713Sgirish */ 327344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 32744045d941Ssowmini "nxge_dma_mem_alloc: alloc type not allowed (%d)", 32754045d941Ssowmini dma_p->contig_alloc_type)); 327644961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 327744961713Sgirish } 327844961713Sgirish 327944961713Sgirish dma_p->dma_handle = NULL; 328044961713Sgirish dma_p->acc_handle = NULL; 328144961713Sgirish dma_p->kaddrp = dma_p->last_kaddrp = NULL; 328244961713Sgirish dma_p->first_ioaddr_pp = dma_p->last_ioaddr_pp = NULL; 328344961713Sgirish ddi_status = ddi_dma_alloc_handle(nxgep->dip, dma_attrp, 32844045d941Ssowmini DDI_DMA_DONTWAIT, NULL, &dma_p->dma_handle); 328544961713Sgirish if (ddi_status != DDI_SUCCESS) { 328644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 32874045d941Ssowmini "nxge_dma_mem_alloc:ddi_dma_alloc_handle failed.")); 328844961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 328944961713Sgirish } 329044961713Sgirish 3291678453a8Sspeer kmem_alloc_type = dma_p->kmem_alloc_type; 3292678453a8Sspeer 329344961713Sgirish switch (contig_alloc_type) { 329444961713Sgirish case B_FALSE: 3295678453a8Sspeer switch (kmem_alloc_type) { 3296678453a8Sspeer case B_FALSE: 3297678453a8Sspeer ddi_status = ddi_dma_mem_alloc(dma_p->dma_handle, 32984045d941Ssowmini length, 32994045d941Ssowmini acc_attr_p, 33004045d941Ssowmini xfer_flags, 33014045d941Ssowmini DDI_DMA_DONTWAIT, 0, &kaddrp, &dma_p->alength, 33024045d941Ssowmini &dma_p->acc_handle); 3303678453a8Sspeer if (ddi_status != DDI_SUCCESS) { 3304678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3305678453a8Sspeer "nxge_dma_mem_alloc: " 3306678453a8Sspeer "ddi_dma_mem_alloc failed")); 3307678453a8Sspeer ddi_dma_free_handle(&dma_p->dma_handle); 3308678453a8Sspeer dma_p->dma_handle = NULL; 3309678453a8Sspeer return (NXGE_ERROR | NXGE_DDI_FAILED); 3310678453a8Sspeer } 3311678453a8Sspeer if (dma_p->alength < length) { 3312678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3313678453a8Sspeer "nxge_dma_mem_alloc:di_dma_mem_alloc " 3314678453a8Sspeer "< length.")); 331544961713Sgirish ddi_dma_mem_free(&dma_p->acc_handle); 3316678453a8Sspeer ddi_dma_free_handle(&dma_p->dma_handle); 331744961713Sgirish dma_p->acc_handle = NULL; 3318678453a8Sspeer dma_p->dma_handle = NULL; 3319678453a8Sspeer return (NXGE_ERROR); 332044961713Sgirish } 332144961713Sgirish 3322678453a8Sspeer ddi_status = ddi_dma_addr_bind_handle(dma_p->dma_handle, 3323678453a8Sspeer NULL, 3324678453a8Sspeer kaddrp, dma_p->alength, xfer_flags, 3325678453a8Sspeer DDI_DMA_DONTWAIT, 3326678453a8Sspeer 0, &dma_p->dma_cookie, &dma_p->ncookies); 3327678453a8Sspeer if (ddi_status != DDI_DMA_MAPPED) { 3328678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3329678453a8Sspeer "nxge_dma_mem_alloc: ddi_dma_addr_bind " 3330678453a8Sspeer "failed " 3331678453a8Sspeer "(staus 0x%x ncookies %d.)", ddi_status, 3332678453a8Sspeer dma_p->ncookies)); 3333678453a8Sspeer if (dma_p->acc_handle) { 3334678453a8Sspeer ddi_dma_mem_free(&dma_p->acc_handle); 3335678453a8Sspeer dma_p->acc_handle = NULL; 3336678453a8Sspeer } 3337678453a8Sspeer ddi_dma_free_handle(&dma_p->dma_handle); 3338678453a8Sspeer dma_p->dma_handle = NULL; 3339678453a8Sspeer return (NXGE_ERROR | NXGE_DDI_FAILED); 3340678453a8Sspeer } 3341678453a8Sspeer 3342678453a8Sspeer if (dma_p->ncookies != 1) { 3343678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, 3344678453a8Sspeer "nxge_dma_mem_alloc:ddi_dma_addr_bind " 3345678453a8Sspeer "> 1 cookie" 3346678453a8Sspeer "(staus 0x%x ncookies %d.)", ddi_status, 3347678453a8Sspeer dma_p->ncookies)); 3348678453a8Sspeer if (dma_p->acc_handle) { 3349678453a8Sspeer ddi_dma_mem_free(&dma_p->acc_handle); 3350678453a8Sspeer dma_p->acc_handle = NULL; 3351678453a8Sspeer } 3352678453a8Sspeer (void) ddi_dma_unbind_handle(dma_p->dma_handle); 3353678453a8Sspeer ddi_dma_free_handle(&dma_p->dma_handle); 3354678453a8Sspeer dma_p->dma_handle = NULL; 3355678453a8Sspeer return (NXGE_ERROR); 3356678453a8Sspeer } 3357678453a8Sspeer break; 3358678453a8Sspeer 3359678453a8Sspeer case B_TRUE: 3360678453a8Sspeer kaddrp = KMEM_ALLOC(length, KM_NOSLEEP); 3361678453a8Sspeer if (kaddrp == NULL) { 3362678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3363678453a8Sspeer "nxge_dma_mem_alloc:ddi_dma_mem_alloc " 3364678453a8Sspeer "kmem alloc failed")); 3365678453a8Sspeer return (NXGE_ERROR); 3366678453a8Sspeer } 3367678453a8Sspeer 3368678453a8Sspeer dma_p->alength = length; 3369678453a8Sspeer ddi_status = ddi_dma_addr_bind_handle(dma_p->dma_handle, 3370678453a8Sspeer NULL, kaddrp, dma_p->alength, xfer_flags, 3371678453a8Sspeer DDI_DMA_DONTWAIT, 0, 3372678453a8Sspeer &dma_p->dma_cookie, &dma_p->ncookies); 3373678453a8Sspeer if (ddi_status != DDI_DMA_MAPPED) { 3374678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3375678453a8Sspeer "nxge_dma_mem_alloc:ddi_dma_addr_bind: " 3376678453a8Sspeer "(kmem_alloc) failed kaddrp $%p length %d " 3377678453a8Sspeer "(staus 0x%x (%d) ncookies %d.)", 3378678453a8Sspeer kaddrp, length, 3379678453a8Sspeer ddi_status, ddi_status, dma_p->ncookies)); 3380678453a8Sspeer KMEM_FREE(kaddrp, length); 3381678453a8Sspeer dma_p->acc_handle = NULL; 3382678453a8Sspeer ddi_dma_free_handle(&dma_p->dma_handle); 3383678453a8Sspeer dma_p->dma_handle = NULL; 3384678453a8Sspeer dma_p->kaddrp = NULL; 3385678453a8Sspeer return (NXGE_ERROR | NXGE_DDI_FAILED); 3386678453a8Sspeer } 3387678453a8Sspeer 3388678453a8Sspeer if (dma_p->ncookies != 1) { 3389678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, 3390678453a8Sspeer "nxge_dma_mem_alloc:ddi_dma_addr_bind " 3391678453a8Sspeer "(kmem_alloc) > 1 cookie" 3392678453a8Sspeer "(staus 0x%x ncookies %d.)", ddi_status, 33934045d941Ssowmini dma_p->ncookies)); 3394678453a8Sspeer KMEM_FREE(kaddrp, length); 339544961713Sgirish dma_p->acc_handle = NULL; 3396678453a8Sspeer (void) ddi_dma_unbind_handle(dma_p->dma_handle); 3397678453a8Sspeer ddi_dma_free_handle(&dma_p->dma_handle); 3398678453a8Sspeer dma_p->dma_handle = NULL; 3399678453a8Sspeer dma_p->kaddrp = NULL; 3400678453a8Sspeer return (NXGE_ERROR); 340144961713Sgirish } 3402678453a8Sspeer 3403678453a8Sspeer dma_p->kaddrp = kaddrp; 3404678453a8Sspeer 3405678453a8Sspeer NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 34064045d941Ssowmini "nxge_dma_mem_alloc: kmem_alloc dmap $%p " 34074045d941Ssowmini "kaddr $%p alength %d", 34084045d941Ssowmini dma_p, 34094045d941Ssowmini kaddrp, 34104045d941Ssowmini dma_p->alength)); 3411678453a8Sspeer break; 341244961713Sgirish } 341344961713Sgirish break; 341444961713Sgirish 341544961713Sgirish #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 341644961713Sgirish case B_TRUE: 341744961713Sgirish kaddrp = (caddr_t)contig_mem_alloc(length); 341844961713Sgirish if (kaddrp == NULL) { 341944961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 34204045d941Ssowmini "nxge_dma_mem_alloc:contig_mem_alloc failed.")); 342144961713Sgirish ddi_dma_free_handle(&dma_p->dma_handle); 342244961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 342344961713Sgirish } 342444961713Sgirish 342544961713Sgirish dma_p->alength = length; 342644961713Sgirish ddi_status = ddi_dma_addr_bind_handle(dma_p->dma_handle, NULL, 34274045d941Ssowmini kaddrp, dma_p->alength, xfer_flags, DDI_DMA_DONTWAIT, 0, 34284045d941Ssowmini &dma_p->dma_cookie, &dma_p->ncookies); 342944961713Sgirish if (ddi_status != DDI_DMA_MAPPED) { 343044961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 34314045d941Ssowmini "nxge_dma_mem_alloc:di_dma_addr_bind failed " 34324045d941Ssowmini "(status 0x%x ncookies %d.)", ddi_status, 34334045d941Ssowmini dma_p->ncookies)); 343444961713Sgirish 343544961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 34364045d941Ssowmini "==> nxge_dma_mem_alloc: (not mapped)" 34374045d941Ssowmini "length %lu (0x%x) " 34384045d941Ssowmini "free contig kaddrp $%p " 34394045d941Ssowmini "va_to_pa $%p", 34404045d941Ssowmini length, length, 34414045d941Ssowmini kaddrp, 34424045d941Ssowmini va_to_pa(kaddrp))); 344344961713Sgirish 344444961713Sgirish 344544961713Sgirish contig_mem_free((void *)kaddrp, length); 344644961713Sgirish ddi_dma_free_handle(&dma_p->dma_handle); 344744961713Sgirish 344844961713Sgirish dma_p->dma_handle = NULL; 344944961713Sgirish dma_p->acc_handle = NULL; 345044961713Sgirish dma_p->alength = NULL; 345144961713Sgirish dma_p->kaddrp = NULL; 345244961713Sgirish 345344961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 345444961713Sgirish } 345544961713Sgirish 345644961713Sgirish if (dma_p->ncookies != 1 || 34574045d941Ssowmini (dma_p->dma_cookie.dmac_laddress == NULL)) { 345844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 34594045d941Ssowmini "nxge_dma_mem_alloc:di_dma_addr_bind > 1 " 34604045d941Ssowmini "cookie or " 34614045d941Ssowmini "dmac_laddress is NULL $%p size %d " 34624045d941Ssowmini " (status 0x%x ncookies %d.)", 34634045d941Ssowmini ddi_status, 34644045d941Ssowmini dma_p->dma_cookie.dmac_laddress, 34654045d941Ssowmini dma_p->dma_cookie.dmac_size, 34664045d941Ssowmini dma_p->ncookies)); 346744961713Sgirish 346844961713Sgirish contig_mem_free((void *)kaddrp, length); 346956d930aeSspeer (void) ddi_dma_unbind_handle(dma_p->dma_handle); 347044961713Sgirish ddi_dma_free_handle(&dma_p->dma_handle); 347144961713Sgirish 347244961713Sgirish dma_p->alength = 0; 347344961713Sgirish dma_p->dma_handle = NULL; 347444961713Sgirish dma_p->acc_handle = NULL; 347544961713Sgirish dma_p->kaddrp = NULL; 347644961713Sgirish 347744961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 347844961713Sgirish } 347944961713Sgirish break; 348044961713Sgirish 348144961713Sgirish #else 348244961713Sgirish case B_TRUE: 348344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 34844045d941Ssowmini "nxge_dma_mem_alloc: invalid alloc type for !sun4v")); 348544961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 348644961713Sgirish #endif 348744961713Sgirish } 348844961713Sgirish 348944961713Sgirish dma_p->kaddrp = kaddrp; 349044961713Sgirish dma_p->last_kaddrp = (unsigned char *)kaddrp + 34914045d941Ssowmini dma_p->alength - RXBUF_64B_ALIGNED; 3492adfcba55Sjoycey #if defined(__i386) 3493adfcba55Sjoycey dma_p->ioaddr_pp = 34944045d941Ssowmini (unsigned char *)(uint32_t)dma_p->dma_cookie.dmac_laddress; 3495adfcba55Sjoycey #else 349644961713Sgirish dma_p->ioaddr_pp = (unsigned char *)dma_p->dma_cookie.dmac_laddress; 3497adfcba55Sjoycey #endif 349844961713Sgirish dma_p->last_ioaddr_pp = 3499adfcba55Sjoycey #if defined(__i386) 35004045d941Ssowmini (unsigned char *)(uint32_t)dma_p->dma_cookie.dmac_laddress + 3501adfcba55Sjoycey #else 35024045d941Ssowmini (unsigned char *)dma_p->dma_cookie.dmac_laddress + 3503adfcba55Sjoycey #endif 35044045d941Ssowmini dma_p->alength - RXBUF_64B_ALIGNED; 350544961713Sgirish 350644961713Sgirish NPI_DMA_ACC_HANDLE_SET(dma_p, dma_p->acc_handle); 350744961713Sgirish 350844961713Sgirish #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 350944961713Sgirish dma_p->orig_ioaddr_pp = 35104045d941Ssowmini (unsigned char *)dma_p->dma_cookie.dmac_laddress; 351144961713Sgirish dma_p->orig_alength = length; 351244961713Sgirish dma_p->orig_kaddrp = kaddrp; 351344961713Sgirish dma_p->orig_vatopa = (uint64_t)va_to_pa(kaddrp); 351444961713Sgirish #endif 351544961713Sgirish 351644961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_dma_mem_alloc: " 35174045d941Ssowmini "dma buffer allocated: dma_p $%p " 35184045d941Ssowmini "return dmac_ladress from cookie $%p cookie dmac_size %d " 35194045d941Ssowmini "dma_p->ioaddr_p $%p " 35204045d941Ssowmini "dma_p->orig_ioaddr_p $%p " 35214045d941Ssowmini "orig_vatopa $%p " 35224045d941Ssowmini "alength %d (0x%x) " 35234045d941Ssowmini "kaddrp $%p " 35244045d941Ssowmini "length %d (0x%x)", 35254045d941Ssowmini dma_p, 35264045d941Ssowmini dma_p->dma_cookie.dmac_laddress, dma_p->dma_cookie.dmac_size, 35274045d941Ssowmini dma_p->ioaddr_pp, 35284045d941Ssowmini dma_p->orig_ioaddr_pp, 35294045d941Ssowmini dma_p->orig_vatopa, 35304045d941Ssowmini dma_p->alength, dma_p->alength, 35314045d941Ssowmini kaddrp, 35324045d941Ssowmini length, length)); 353344961713Sgirish 353444961713Sgirish return (NXGE_OK); 353544961713Sgirish } 353644961713Sgirish 353744961713Sgirish static void 353844961713Sgirish nxge_dma_mem_free(p_nxge_dma_common_t dma_p) 353944961713Sgirish { 354044961713Sgirish if (dma_p->dma_handle != NULL) { 354144961713Sgirish if (dma_p->ncookies) { 354244961713Sgirish (void) ddi_dma_unbind_handle(dma_p->dma_handle); 354344961713Sgirish dma_p->ncookies = 0; 354444961713Sgirish } 354544961713Sgirish ddi_dma_free_handle(&dma_p->dma_handle); 354644961713Sgirish dma_p->dma_handle = NULL; 354744961713Sgirish } 354844961713Sgirish 354944961713Sgirish if (dma_p->acc_handle != NULL) { 355044961713Sgirish ddi_dma_mem_free(&dma_p->acc_handle); 355144961713Sgirish dma_p->acc_handle = NULL; 355244961713Sgirish NPI_DMA_ACC_HANDLE_SET(dma_p, NULL); 355344961713Sgirish } 355444961713Sgirish 355544961713Sgirish #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 355644961713Sgirish if (dma_p->contig_alloc_type && 35574045d941Ssowmini dma_p->orig_kaddrp && dma_p->orig_alength) { 355844961713Sgirish NXGE_DEBUG_MSG((NULL, DMA_CTL, "nxge_dma_mem_free: " 35594045d941Ssowmini "kaddrp $%p (orig_kaddrp $%p)" 35604045d941Ssowmini "mem type %d ", 35614045d941Ssowmini "orig_alength %d " 35624045d941Ssowmini "alength 0x%x (%d)", 35634045d941Ssowmini dma_p->kaddrp, 35644045d941Ssowmini dma_p->orig_kaddrp, 35654045d941Ssowmini dma_p->contig_alloc_type, 35664045d941Ssowmini dma_p->orig_alength, 35674045d941Ssowmini dma_p->alength, dma_p->alength)); 356844961713Sgirish 356944961713Sgirish contig_mem_free(dma_p->orig_kaddrp, dma_p->orig_alength); 357044961713Sgirish dma_p->orig_alength = NULL; 357144961713Sgirish dma_p->orig_kaddrp = NULL; 357244961713Sgirish dma_p->contig_alloc_type = B_FALSE; 357344961713Sgirish } 357444961713Sgirish #endif 357544961713Sgirish dma_p->kaddrp = NULL; 357644961713Sgirish dma_p->alength = NULL; 357744961713Sgirish } 357844961713Sgirish 3579678453a8Sspeer static void 3580678453a8Sspeer nxge_dma_free_rx_data_buf(p_nxge_dma_common_t dma_p) 3581678453a8Sspeer { 3582678453a8Sspeer uint64_t kaddr; 3583678453a8Sspeer uint32_t buf_size; 3584678453a8Sspeer 3585678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, "==> nxge_dma_free_rx_data_buf")); 3586678453a8Sspeer 3587678453a8Sspeer if (dma_p->dma_handle != NULL) { 3588678453a8Sspeer if (dma_p->ncookies) { 3589678453a8Sspeer (void) ddi_dma_unbind_handle(dma_p->dma_handle); 3590678453a8Sspeer dma_p->ncookies = 0; 3591678453a8Sspeer } 3592678453a8Sspeer ddi_dma_free_handle(&dma_p->dma_handle); 3593678453a8Sspeer dma_p->dma_handle = NULL; 3594678453a8Sspeer } 3595678453a8Sspeer 3596678453a8Sspeer if (dma_p->acc_handle != NULL) { 3597678453a8Sspeer ddi_dma_mem_free(&dma_p->acc_handle); 3598678453a8Sspeer dma_p->acc_handle = NULL; 3599678453a8Sspeer NPI_DMA_ACC_HANDLE_SET(dma_p, NULL); 3600678453a8Sspeer } 3601678453a8Sspeer 3602678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, 3603678453a8Sspeer "==> nxge_dma_free_rx_data_buf: dmap $%p buf_alloc_state %d", 3604678453a8Sspeer dma_p, 3605678453a8Sspeer dma_p->buf_alloc_state)); 3606678453a8Sspeer 3607678453a8Sspeer if (!(dma_p->buf_alloc_state & BUF_ALLOCATED_WAIT_FREE)) { 3608678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, 3609678453a8Sspeer "<== nxge_dma_free_rx_data_buf: " 3610678453a8Sspeer "outstanding data buffers")); 3611678453a8Sspeer return; 3612678453a8Sspeer } 3613678453a8Sspeer 3614678453a8Sspeer #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 3615678453a8Sspeer if (dma_p->contig_alloc_type && 36164045d941Ssowmini dma_p->orig_kaddrp && dma_p->orig_alength) { 3617678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, "nxge_dma_free_rx_data_buf: " 3618678453a8Sspeer "kaddrp $%p (orig_kaddrp $%p)" 3619678453a8Sspeer "mem type %d ", 3620678453a8Sspeer "orig_alength %d " 3621678453a8Sspeer "alength 0x%x (%d)", 3622678453a8Sspeer dma_p->kaddrp, 3623678453a8Sspeer dma_p->orig_kaddrp, 3624678453a8Sspeer dma_p->contig_alloc_type, 3625678453a8Sspeer dma_p->orig_alength, 3626678453a8Sspeer dma_p->alength, dma_p->alength)); 3627678453a8Sspeer 3628678453a8Sspeer kaddr = (uint64_t)dma_p->orig_kaddrp; 3629678453a8Sspeer buf_size = dma_p->orig_alength; 3630678453a8Sspeer nxge_free_buf(CONTIG_MEM_ALLOC, kaddr, buf_size); 3631678453a8Sspeer dma_p->orig_alength = NULL; 3632678453a8Sspeer dma_p->orig_kaddrp = NULL; 3633678453a8Sspeer dma_p->contig_alloc_type = B_FALSE; 3634678453a8Sspeer dma_p->kaddrp = NULL; 3635678453a8Sspeer dma_p->alength = NULL; 3636678453a8Sspeer return; 3637678453a8Sspeer } 3638678453a8Sspeer #endif 3639678453a8Sspeer 3640678453a8Sspeer if (dma_p->kmem_alloc_type) { 3641678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, 3642678453a8Sspeer "nxge_dma_free_rx_data_buf: free kmem " 36434045d941Ssowmini "kaddrp $%p (orig_kaddrp $%p)" 36444045d941Ssowmini "alloc type %d " 36454045d941Ssowmini "orig_alength %d " 36464045d941Ssowmini "alength 0x%x (%d)", 36474045d941Ssowmini dma_p->kaddrp, 36484045d941Ssowmini dma_p->orig_kaddrp, 36494045d941Ssowmini dma_p->kmem_alloc_type, 36504045d941Ssowmini dma_p->orig_alength, 36514045d941Ssowmini dma_p->alength, dma_p->alength)); 3652678453a8Sspeer #if defined(__i386) 3653678453a8Sspeer kaddr = (uint64_t)(uint32_t)dma_p->kaddrp; 3654678453a8Sspeer #else 3655678453a8Sspeer kaddr = (uint64_t)dma_p->kaddrp; 3656678453a8Sspeer #endif 3657678453a8Sspeer buf_size = dma_p->orig_alength; 3658678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, 3659678453a8Sspeer "nxge_dma_free_rx_data_buf: free dmap $%p " 3660678453a8Sspeer "kaddr $%p buf_size %d", 3661678453a8Sspeer dma_p, 3662678453a8Sspeer kaddr, buf_size)); 3663678453a8Sspeer nxge_free_buf(KMEM_ALLOC, kaddr, buf_size); 3664678453a8Sspeer dma_p->alength = 0; 3665678453a8Sspeer dma_p->orig_alength = 0; 3666678453a8Sspeer dma_p->kaddrp = NULL; 3667678453a8Sspeer dma_p->kmem_alloc_type = B_FALSE; 3668678453a8Sspeer } 3669678453a8Sspeer 3670678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_dma_free_rx_data_buf")); 3671678453a8Sspeer } 3672678453a8Sspeer 367344961713Sgirish /* 367444961713Sgirish * nxge_m_start() -- start transmitting and receiving. 367544961713Sgirish * 367644961713Sgirish * This function is called by the MAC layer when the first 367744961713Sgirish * stream is open to prepare the hardware ready for sending 367844961713Sgirish * and transmitting packets. 367944961713Sgirish */ 368044961713Sgirish static int 368144961713Sgirish nxge_m_start(void *arg) 368244961713Sgirish { 368344961713Sgirish p_nxge_t nxgep = (p_nxge_t)arg; 368444961713Sgirish 368544961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_start")); 368644961713Sgirish 36876f157acbSml if (nxge_peu_reset_enable && !nxgep->nxge_link_poll_timerid) { 36886f157acbSml (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 36896f157acbSml } 36906f157acbSml 369144961713Sgirish MUTEX_ENTER(nxgep->genlock); 369214ea4bb7Ssd if (nxge_init(nxgep) != NXGE_OK) { 369344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 36944045d941Ssowmini "<== nxge_m_start: initialization failed")); 369544961713Sgirish MUTEX_EXIT(nxgep->genlock); 369644961713Sgirish return (EIO); 369744961713Sgirish } 369844961713Sgirish 369914ea4bb7Ssd if (nxgep->nxge_mac_state == NXGE_MAC_STARTED) 370014ea4bb7Ssd goto nxge_m_start_exit; 370144961713Sgirish /* 370244961713Sgirish * Start timer to check the system error and tx hangs 370344961713Sgirish */ 3704678453a8Sspeer if (!isLDOMguest(nxgep)) 3705678453a8Sspeer nxgep->nxge_timerid = nxge_start_timer(nxgep, 3706678453a8Sspeer nxge_check_hw_state, NXGE_CHECK_TIMER); 3707678453a8Sspeer #if defined(sun4v) 3708678453a8Sspeer else 3709678453a8Sspeer nxge_hio_start_timer(nxgep); 3710678453a8Sspeer #endif 371144961713Sgirish 3712a3c5bd6dSspeer nxgep->link_notify = B_TRUE; 3713a3c5bd6dSspeer 371444961713Sgirish nxgep->nxge_mac_state = NXGE_MAC_STARTED; 371544961713Sgirish 371614ea4bb7Ssd nxge_m_start_exit: 371744961713Sgirish MUTEX_EXIT(nxgep->genlock); 371844961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_start")); 371944961713Sgirish return (0); 372044961713Sgirish } 372144961713Sgirish 372244961713Sgirish /* 372344961713Sgirish * nxge_m_stop(): stop transmitting and receiving. 372444961713Sgirish */ 372544961713Sgirish static void 372644961713Sgirish nxge_m_stop(void *arg) 372744961713Sgirish { 372844961713Sgirish p_nxge_t nxgep = (p_nxge_t)arg; 372944961713Sgirish 373044961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_stop")); 373144961713Sgirish 373244961713Sgirish if (nxgep->nxge_timerid) { 373344961713Sgirish nxge_stop_timer(nxgep, nxgep->nxge_timerid); 373444961713Sgirish nxgep->nxge_timerid = 0; 373544961713Sgirish } 3736a3c5bd6dSspeer 3737a3c5bd6dSspeer MUTEX_ENTER(nxgep->genlock); 3738678453a8Sspeer nxgep->nxge_mac_state = NXGE_MAC_STOPPING; 373944961713Sgirish nxge_uninit(nxgep); 374044961713Sgirish 374144961713Sgirish nxgep->nxge_mac_state = NXGE_MAC_STOPPED; 374244961713Sgirish 374344961713Sgirish MUTEX_EXIT(nxgep->genlock); 374444961713Sgirish 374544961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_stop")); 374644961713Sgirish } 374744961713Sgirish 374844961713Sgirish static int 374944961713Sgirish nxge_m_unicst(void *arg, const uint8_t *macaddr) 375044961713Sgirish { 375144961713Sgirish p_nxge_t nxgep = (p_nxge_t)arg; 375244961713Sgirish struct ether_addr addrp; 375344961713Sgirish 375444961713Sgirish NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_m_unicst")); 375544961713Sgirish 375644961713Sgirish bcopy(macaddr, (uint8_t *)&addrp, ETHERADDRL); 375744961713Sgirish if (nxge_set_mac_addr(nxgep, &addrp)) { 375844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 37594045d941Ssowmini "<== nxge_m_unicst: set unitcast failed")); 376044961713Sgirish return (EINVAL); 376144961713Sgirish } 376244961713Sgirish 376344961713Sgirish NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_m_unicst")); 376444961713Sgirish 376544961713Sgirish return (0); 376644961713Sgirish } 376744961713Sgirish 376844961713Sgirish static int 376944961713Sgirish nxge_m_multicst(void *arg, boolean_t add, const uint8_t *mca) 377044961713Sgirish { 377144961713Sgirish p_nxge_t nxgep = (p_nxge_t)arg; 377244961713Sgirish struct ether_addr addrp; 377344961713Sgirish 377444961713Sgirish NXGE_DEBUG_MSG((nxgep, MAC_CTL, 37754045d941Ssowmini "==> nxge_m_multicst: add %d", add)); 377644961713Sgirish 377744961713Sgirish bcopy(mca, (uint8_t *)&addrp, ETHERADDRL); 377844961713Sgirish if (add) { 377944961713Sgirish if (nxge_add_mcast_addr(nxgep, &addrp)) { 378044961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 37814045d941Ssowmini "<== nxge_m_multicst: add multicast failed")); 378244961713Sgirish return (EINVAL); 378344961713Sgirish } 378444961713Sgirish } else { 378544961713Sgirish if (nxge_del_mcast_addr(nxgep, &addrp)) { 378644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 37874045d941Ssowmini "<== nxge_m_multicst: del multicast failed")); 378844961713Sgirish return (EINVAL); 378944961713Sgirish } 379044961713Sgirish } 379144961713Sgirish 379244961713Sgirish NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_m_multicst")); 379344961713Sgirish 379444961713Sgirish return (0); 379544961713Sgirish } 379644961713Sgirish 379744961713Sgirish static int 379844961713Sgirish nxge_m_promisc(void *arg, boolean_t on) 379944961713Sgirish { 380044961713Sgirish p_nxge_t nxgep = (p_nxge_t)arg; 380144961713Sgirish 380244961713Sgirish NXGE_DEBUG_MSG((nxgep, MAC_CTL, 38034045d941Ssowmini "==> nxge_m_promisc: on %d", on)); 380444961713Sgirish 380544961713Sgirish if (nxge_set_promisc(nxgep, on)) { 380644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 38074045d941Ssowmini "<== nxge_m_promisc: set promisc failed")); 380844961713Sgirish return (EINVAL); 380944961713Sgirish } 381044961713Sgirish 381144961713Sgirish NXGE_DEBUG_MSG((nxgep, MAC_CTL, 38124045d941Ssowmini "<== nxge_m_promisc: on %d", on)); 381344961713Sgirish 381444961713Sgirish return (0); 381544961713Sgirish } 381644961713Sgirish 381744961713Sgirish static void 381844961713Sgirish nxge_m_ioctl(void *arg, queue_t *wq, mblk_t *mp) 381944961713Sgirish { 382044961713Sgirish p_nxge_t nxgep = (p_nxge_t)arg; 382156d930aeSspeer struct iocblk *iocp; 382244961713Sgirish boolean_t need_privilege; 382344961713Sgirish int err; 382444961713Sgirish int cmd; 382544961713Sgirish 382644961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_ioctl")); 382744961713Sgirish 382844961713Sgirish iocp = (struct iocblk *)mp->b_rptr; 382944961713Sgirish iocp->ioc_error = 0; 383044961713Sgirish need_privilege = B_TRUE; 383144961713Sgirish cmd = iocp->ioc_cmd; 383244961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_ioctl: cmd 0x%08x", cmd)); 383344961713Sgirish switch (cmd) { 383444961713Sgirish default: 383544961713Sgirish miocnak(wq, mp, 0, EINVAL); 383644961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_ioctl: invalid")); 383744961713Sgirish return; 383844961713Sgirish 383944961713Sgirish case LB_GET_INFO_SIZE: 384044961713Sgirish case LB_GET_INFO: 384144961713Sgirish case LB_GET_MODE: 384244961713Sgirish need_privilege = B_FALSE; 384344961713Sgirish break; 384444961713Sgirish case LB_SET_MODE: 384544961713Sgirish break; 384644961713Sgirish 384744961713Sgirish 384844961713Sgirish case NXGE_GET_MII: 384944961713Sgirish case NXGE_PUT_MII: 385044961713Sgirish case NXGE_GET64: 385144961713Sgirish case NXGE_PUT64: 385244961713Sgirish case NXGE_GET_TX_RING_SZ: 385344961713Sgirish case NXGE_GET_TX_DESC: 385444961713Sgirish case NXGE_TX_SIDE_RESET: 385544961713Sgirish case NXGE_RX_SIDE_RESET: 385644961713Sgirish case NXGE_GLOBAL_RESET: 385744961713Sgirish case NXGE_RESET_MAC: 385844961713Sgirish case NXGE_TX_REGS_DUMP: 385944961713Sgirish case NXGE_RX_REGS_DUMP: 386044961713Sgirish case NXGE_INT_REGS_DUMP: 386144961713Sgirish case NXGE_VIR_INT_REGS_DUMP: 386244961713Sgirish case NXGE_PUT_TCAM: 386344961713Sgirish case NXGE_GET_TCAM: 386444961713Sgirish case NXGE_RTRACE: 386544961713Sgirish case NXGE_RDUMP: 386644961713Sgirish 386744961713Sgirish need_privilege = B_FALSE; 386844961713Sgirish break; 386944961713Sgirish case NXGE_INJECT_ERR: 387044961713Sgirish cmn_err(CE_NOTE, "!nxge_m_ioctl: Inject error\n"); 387144961713Sgirish nxge_err_inject(nxgep, wq, mp); 387244961713Sgirish break; 387344961713Sgirish } 387444961713Sgirish 387544961713Sgirish if (need_privilege) { 387656d930aeSspeer err = secpolicy_net_config(iocp->ioc_cr, B_FALSE); 387744961713Sgirish if (err != 0) { 387844961713Sgirish miocnak(wq, mp, 0, err); 387944961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 38804045d941Ssowmini "<== nxge_m_ioctl: no priv")); 388144961713Sgirish return; 388244961713Sgirish } 388344961713Sgirish } 388444961713Sgirish 388544961713Sgirish switch (cmd) { 388644961713Sgirish 388744961713Sgirish case LB_GET_MODE: 388844961713Sgirish case LB_SET_MODE: 388944961713Sgirish case LB_GET_INFO_SIZE: 389044961713Sgirish case LB_GET_INFO: 389144961713Sgirish nxge_loopback_ioctl(nxgep, wq, mp, iocp); 389244961713Sgirish break; 389344961713Sgirish 389444961713Sgirish case NXGE_GET_MII: 389544961713Sgirish case NXGE_PUT_MII: 389644961713Sgirish case NXGE_PUT_TCAM: 389744961713Sgirish case NXGE_GET_TCAM: 389844961713Sgirish case NXGE_GET64: 389944961713Sgirish case NXGE_PUT64: 390044961713Sgirish case NXGE_GET_TX_RING_SZ: 390144961713Sgirish case NXGE_GET_TX_DESC: 390244961713Sgirish case NXGE_TX_SIDE_RESET: 390344961713Sgirish case NXGE_RX_SIDE_RESET: 390444961713Sgirish case NXGE_GLOBAL_RESET: 390544961713Sgirish case NXGE_RESET_MAC: 390644961713Sgirish case NXGE_TX_REGS_DUMP: 390744961713Sgirish case NXGE_RX_REGS_DUMP: 390844961713Sgirish case NXGE_INT_REGS_DUMP: 390944961713Sgirish case NXGE_VIR_INT_REGS_DUMP: 391044961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 39114045d941Ssowmini "==> nxge_m_ioctl: cmd 0x%x", cmd)); 391244961713Sgirish nxge_hw_ioctl(nxgep, wq, mp, iocp); 391344961713Sgirish break; 391444961713Sgirish } 391544961713Sgirish 391644961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_ioctl")); 391744961713Sgirish } 391844961713Sgirish 391944961713Sgirish extern void nxge_rx_hw_blank(void *arg, time_t ticks, uint_t count); 392044961713Sgirish 392144961713Sgirish static void 392244961713Sgirish nxge_m_resources(void *arg) 392344961713Sgirish { 392444961713Sgirish p_nxge_t nxgep = arg; 392544961713Sgirish mac_rx_fifo_t mrf; 3926678453a8Sspeer 3927678453a8Sspeer nxge_grp_set_t *set = &nxgep->rx_set; 3928678453a8Sspeer uint8_t rdc; 3929678453a8Sspeer 3930678453a8Sspeer rx_rcr_ring_t *ring; 393144961713Sgirish 393244961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_m_resources")); 393344961713Sgirish 393444961713Sgirish MUTEX_ENTER(nxgep->genlock); 393514ea4bb7Ssd 3936678453a8Sspeer if (set->owned.map == 0) { 3937678453a8Sspeer NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 3938678453a8Sspeer "nxge_m_resources: no receive resources")); 3939678453a8Sspeer goto nxge_m_resources_exit; 3940678453a8Sspeer } 3941678453a8Sspeer 394214ea4bb7Ssd /* 394358324dfcSspeer * CR 6492541 Check to see if the drv_state has been initialized, 394414ea4bb7Ssd * if not * call nxge_init(). 394514ea4bb7Ssd */ 394614ea4bb7Ssd if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 3947678453a8Sspeer if (nxge_init(nxgep) != NXGE_OK) 394814ea4bb7Ssd goto nxge_m_resources_exit; 394914ea4bb7Ssd } 395014ea4bb7Ssd 395144961713Sgirish mrf.mrf_type = MAC_RX_FIFO; 395244961713Sgirish mrf.mrf_blank = nxge_rx_hw_blank; 395344961713Sgirish mrf.mrf_arg = (void *)nxgep; 395444961713Sgirish 395544961713Sgirish mrf.mrf_normal_blank_time = 128; 395644961713Sgirish mrf.mrf_normal_pkt_count = 8; 395744961713Sgirish 395814ea4bb7Ssd /* 395914ea4bb7Ssd * Export our receive resources to the MAC layer. 396014ea4bb7Ssd */ 3961678453a8Sspeer for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 3962678453a8Sspeer if ((1 << rdc) & set->owned.map) { 3963678453a8Sspeer ring = nxgep->rx_rcr_rings->rcr_rings[rdc]; 3964678453a8Sspeer if (ring == 0) { 3965678453a8Sspeer /* 3966678453a8Sspeer * This is a big deal only if we are 3967678453a8Sspeer * *not* in an LDOMs environment. 3968678453a8Sspeer */ 3969678453a8Sspeer if (nxgep->environs == SOLARIS_DOMAIN) { 3970678453a8Sspeer cmn_err(CE_NOTE, 3971678453a8Sspeer "==> nxge_m_resources: " 3972678453a8Sspeer "ring %d == 0", rdc); 3973678453a8Sspeer } 3974678453a8Sspeer continue; 3975678453a8Sspeer } 3976678453a8Sspeer ring->rcr_mac_handle = mac_resource_add 3977678453a8Sspeer (nxgep->mach, (mac_resource_t *)&mrf); 397844961713Sgirish 3979678453a8Sspeer NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 3980678453a8Sspeer "==> nxge_m_resources: RDC %d RCR %p MAC handle %p", 3981678453a8Sspeer rdc, ring, ring->rcr_mac_handle)); 3982678453a8Sspeer } 398344961713Sgirish } 398444961713Sgirish 398514ea4bb7Ssd nxge_m_resources_exit: 398644961713Sgirish MUTEX_EXIT(nxgep->genlock); 398744961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_m_resources")); 398844961713Sgirish } 398944961713Sgirish 3990678453a8Sspeer void 399158324dfcSspeer nxge_mmac_kstat_update(p_nxge_t nxgep, mac_addr_slot_t slot, boolean_t factory) 399258324dfcSspeer { 399358324dfcSspeer p_nxge_mmac_stats_t mmac_stats; 399458324dfcSspeer int i; 399558324dfcSspeer nxge_mmac_t *mmac_info; 399658324dfcSspeer 399758324dfcSspeer mmac_info = &nxgep->nxge_mmac_info; 399858324dfcSspeer 399958324dfcSspeer mmac_stats = &nxgep->statsp->mmac_stats; 400058324dfcSspeer mmac_stats->mmac_max_cnt = mmac_info->num_mmac; 400158324dfcSspeer mmac_stats->mmac_avail_cnt = mmac_info->naddrfree; 400258324dfcSspeer 400358324dfcSspeer for (i = 0; i < ETHERADDRL; i++) { 400458324dfcSspeer if (factory) { 400558324dfcSspeer mmac_stats->mmac_avail_pool[slot-1].ether_addr_octet[i] 40064045d941Ssowmini = mmac_info->factory_mac_pool[slot][ 40074045d941Ssowmini (ETHERADDRL-1) - i]; 400858324dfcSspeer } else { 400958324dfcSspeer mmac_stats->mmac_avail_pool[slot-1].ether_addr_octet[i] 40104045d941Ssowmini = mmac_info->mac_pool[slot].addr[ 40114045d941Ssowmini (ETHERADDRL - 1) - i]; 401258324dfcSspeer } 401358324dfcSspeer } 401458324dfcSspeer } 401558324dfcSspeer 401658324dfcSspeer /* 401758324dfcSspeer * nxge_altmac_set() -- Set an alternate MAC address 401858324dfcSspeer */ 401958324dfcSspeer static int 402058324dfcSspeer nxge_altmac_set(p_nxge_t nxgep, uint8_t *maddr, mac_addr_slot_t slot) 402158324dfcSspeer { 402258324dfcSspeer uint8_t addrn; 402358324dfcSspeer uint8_t portn; 402458324dfcSspeer npi_mac_addr_t altmac; 40257b9fa28bSspeer hostinfo_t mac_rdc; 40267b9fa28bSspeer p_nxge_class_pt_cfg_t clscfgp; 402758324dfcSspeer 402858324dfcSspeer altmac.w2 = ((uint16_t)maddr[0] << 8) | ((uint16_t)maddr[1] & 0x0ff); 402958324dfcSspeer altmac.w1 = ((uint16_t)maddr[2] << 8) | ((uint16_t)maddr[3] & 0x0ff); 403058324dfcSspeer altmac.w0 = ((uint16_t)maddr[4] << 8) | ((uint16_t)maddr[5] & 0x0ff); 403158324dfcSspeer 403258324dfcSspeer portn = nxgep->mac.portnum; 403358324dfcSspeer addrn = (uint8_t)slot - 1; 403458324dfcSspeer 403558324dfcSspeer if (npi_mac_altaddr_entry(nxgep->npi_handle, OP_SET, portn, 40364045d941Ssowmini addrn, &altmac) != NPI_SUCCESS) 403758324dfcSspeer return (EIO); 40387b9fa28bSspeer 40397b9fa28bSspeer /* 40407b9fa28bSspeer * Set the rdc table number for the host info entry 40417b9fa28bSspeer * for this mac address slot. 40427b9fa28bSspeer */ 40437b9fa28bSspeer clscfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 40447b9fa28bSspeer mac_rdc.value = 0; 40457b9fa28bSspeer mac_rdc.bits.w0.rdc_tbl_num = clscfgp->mac_host_info[addrn].rdctbl; 40467b9fa28bSspeer mac_rdc.bits.w0.mac_pref = clscfgp->mac_host_info[addrn].mpr_npr; 40477b9fa28bSspeer 40487b9fa28bSspeer if (npi_mac_hostinfo_entry(nxgep->npi_handle, OP_SET, 40497b9fa28bSspeer nxgep->function_num, addrn, &mac_rdc) != NPI_SUCCESS) { 40507b9fa28bSspeer return (EIO); 40517b9fa28bSspeer } 40527b9fa28bSspeer 405358324dfcSspeer /* 405458324dfcSspeer * Enable comparison with the alternate MAC address. 405558324dfcSspeer * While the first alternate addr is enabled by bit 1 of register 405658324dfcSspeer * BMAC_ALTAD_CMPEN, it is enabled by bit 0 of register 405758324dfcSspeer * XMAC_ADDR_CMPEN, so slot needs to be converted to addrn 405858324dfcSspeer * accordingly before calling npi_mac_altaddr_entry. 405958324dfcSspeer */ 406058324dfcSspeer if (portn == XMAC_PORT_0 || portn == XMAC_PORT_1) 406158324dfcSspeer addrn = (uint8_t)slot - 1; 406258324dfcSspeer else 406358324dfcSspeer addrn = (uint8_t)slot; 406458324dfcSspeer 406558324dfcSspeer if (npi_mac_altaddr_enable(nxgep->npi_handle, portn, addrn) 40664045d941Ssowmini != NPI_SUCCESS) 406758324dfcSspeer return (EIO); 406858324dfcSspeer 406958324dfcSspeer return (0); 407058324dfcSspeer } 407158324dfcSspeer 407258324dfcSspeer /* 407358324dfcSspeer * nxeg_m_mmac_add() - find an unused address slot, set the address 407458324dfcSspeer * value to the one specified, enable the port to start filtering on 407558324dfcSspeer * the new MAC address. Returns 0 on success. 407658324dfcSspeer */ 4077678453a8Sspeer int 407858324dfcSspeer nxge_m_mmac_add(void *arg, mac_multi_addr_t *maddr) 407958324dfcSspeer { 408058324dfcSspeer p_nxge_t nxgep = arg; 408158324dfcSspeer mac_addr_slot_t slot; 408258324dfcSspeer nxge_mmac_t *mmac_info; 408358324dfcSspeer int err; 408458324dfcSspeer nxge_status_t status; 408558324dfcSspeer 408658324dfcSspeer mutex_enter(nxgep->genlock); 408758324dfcSspeer 408858324dfcSspeer /* 408958324dfcSspeer * Make sure that nxge is initialized, if _start() has 409058324dfcSspeer * not been called. 409158324dfcSspeer */ 409258324dfcSspeer if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 409358324dfcSspeer status = nxge_init(nxgep); 409458324dfcSspeer if (status != NXGE_OK) { 409558324dfcSspeer mutex_exit(nxgep->genlock); 409658324dfcSspeer return (ENXIO); 409758324dfcSspeer } 409858324dfcSspeer } 409958324dfcSspeer 410058324dfcSspeer mmac_info = &nxgep->nxge_mmac_info; 410158324dfcSspeer if (mmac_info->naddrfree == 0) { 410258324dfcSspeer mutex_exit(nxgep->genlock); 410358324dfcSspeer return (ENOSPC); 410458324dfcSspeer } 410558324dfcSspeer if (!mac_unicst_verify(nxgep->mach, maddr->mma_addr, 41064045d941Ssowmini maddr->mma_addrlen)) { 410758324dfcSspeer mutex_exit(nxgep->genlock); 410858324dfcSspeer return (EINVAL); 410958324dfcSspeer } 411058324dfcSspeer /* 411158324dfcSspeer * Search for the first available slot. Because naddrfree 411258324dfcSspeer * is not zero, we are guaranteed to find one. 411358324dfcSspeer * Slot 0 is for unique (primary) MAC. The first alternate 411458324dfcSspeer * MAC slot is slot 1. 411558324dfcSspeer * Each of the first two ports of Neptune has 16 alternate 4116678453a8Sspeer * MAC slots but only the first 7 (of 15) slots have assigned factory 411758324dfcSspeer * MAC addresses. We first search among the slots without bundled 411858324dfcSspeer * factory MACs. If we fail to find one in that range, then we 411958324dfcSspeer * search the slots with bundled factory MACs. A factory MAC 412058324dfcSspeer * will be wasted while the slot is used with a user MAC address. 412158324dfcSspeer * But the slot could be used by factory MAC again after calling 412258324dfcSspeer * nxge_m_mmac_remove and nxge_m_mmac_reserve. 412358324dfcSspeer */ 412458324dfcSspeer if (mmac_info->num_factory_mmac < mmac_info->num_mmac) { 412558324dfcSspeer for (slot = mmac_info->num_factory_mmac + 1; 41264045d941Ssowmini slot <= mmac_info->num_mmac; slot++) { 412758324dfcSspeer if (!(mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED)) 412858324dfcSspeer break; 412958324dfcSspeer } 413058324dfcSspeer if (slot > mmac_info->num_mmac) { 413158324dfcSspeer for (slot = 1; slot <= mmac_info->num_factory_mmac; 41324045d941Ssowmini slot++) { 413358324dfcSspeer if (!(mmac_info->mac_pool[slot].flags 41344045d941Ssowmini & MMAC_SLOT_USED)) 413558324dfcSspeer break; 413658324dfcSspeer } 413758324dfcSspeer } 413858324dfcSspeer } else { 413958324dfcSspeer for (slot = 1; slot <= mmac_info->num_mmac; slot++) { 414058324dfcSspeer if (!(mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED)) 414158324dfcSspeer break; 414258324dfcSspeer } 414358324dfcSspeer } 414458324dfcSspeer ASSERT(slot <= mmac_info->num_mmac); 414558324dfcSspeer if ((err = nxge_altmac_set(nxgep, maddr->mma_addr, slot)) != 0) { 414658324dfcSspeer mutex_exit(nxgep->genlock); 414758324dfcSspeer return (err); 414858324dfcSspeer } 414958324dfcSspeer bcopy(maddr->mma_addr, mmac_info->mac_pool[slot].addr, ETHERADDRL); 415058324dfcSspeer mmac_info->mac_pool[slot].flags |= MMAC_SLOT_USED; 415158324dfcSspeer mmac_info->mac_pool[slot].flags &= ~MMAC_VENDOR_ADDR; 415258324dfcSspeer mmac_info->naddrfree--; 415358324dfcSspeer nxge_mmac_kstat_update(nxgep, slot, B_FALSE); 415458324dfcSspeer 415558324dfcSspeer maddr->mma_slot = slot; 415658324dfcSspeer 415758324dfcSspeer mutex_exit(nxgep->genlock); 415858324dfcSspeer return (0); 415958324dfcSspeer } 416058324dfcSspeer 416158324dfcSspeer /* 416258324dfcSspeer * This function reserves an unused slot and programs the slot and the HW 416358324dfcSspeer * with a factory mac address. 416458324dfcSspeer */ 416558324dfcSspeer static int 416658324dfcSspeer nxge_m_mmac_reserve(void *arg, mac_multi_addr_t *maddr) 416758324dfcSspeer { 416858324dfcSspeer p_nxge_t nxgep = arg; 416958324dfcSspeer mac_addr_slot_t slot; 417058324dfcSspeer nxge_mmac_t *mmac_info; 417158324dfcSspeer int err; 417258324dfcSspeer nxge_status_t status; 417358324dfcSspeer 417458324dfcSspeer mutex_enter(nxgep->genlock); 417558324dfcSspeer 417658324dfcSspeer /* 417758324dfcSspeer * Make sure that nxge is initialized, if _start() has 417858324dfcSspeer * not been called. 417958324dfcSspeer */ 418058324dfcSspeer if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 418158324dfcSspeer status = nxge_init(nxgep); 418258324dfcSspeer if (status != NXGE_OK) { 418358324dfcSspeer mutex_exit(nxgep->genlock); 418458324dfcSspeer return (ENXIO); 418558324dfcSspeer } 418658324dfcSspeer } 418758324dfcSspeer 418858324dfcSspeer mmac_info = &nxgep->nxge_mmac_info; 418958324dfcSspeer if (mmac_info->naddrfree == 0) { 419058324dfcSspeer mutex_exit(nxgep->genlock); 419158324dfcSspeer return (ENOSPC); 419258324dfcSspeer } 419358324dfcSspeer 419458324dfcSspeer slot = maddr->mma_slot; 419558324dfcSspeer if (slot == -1) { /* -1: Take the first available slot */ 419658324dfcSspeer for (slot = 1; slot <= mmac_info->num_factory_mmac; slot++) { 419758324dfcSspeer if (!(mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED)) 419858324dfcSspeer break; 419958324dfcSspeer } 420058324dfcSspeer if (slot > mmac_info->num_factory_mmac) { 420158324dfcSspeer mutex_exit(nxgep->genlock); 420258324dfcSspeer return (ENOSPC); 420358324dfcSspeer } 420458324dfcSspeer } 420558324dfcSspeer if (slot < 1 || slot > mmac_info->num_factory_mmac) { 420658324dfcSspeer /* 420758324dfcSspeer * Do not support factory MAC at a slot greater than 420858324dfcSspeer * num_factory_mmac even when there are available factory 420958324dfcSspeer * MAC addresses because the alternate MACs are bundled with 421058324dfcSspeer * slot[1] through slot[num_factory_mmac] 421158324dfcSspeer */ 421258324dfcSspeer mutex_exit(nxgep->genlock); 421358324dfcSspeer return (EINVAL); 421458324dfcSspeer } 421558324dfcSspeer if (mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED) { 421658324dfcSspeer mutex_exit(nxgep->genlock); 421758324dfcSspeer return (EBUSY); 421858324dfcSspeer } 421958324dfcSspeer /* Verify the address to be reserved */ 422058324dfcSspeer if (!mac_unicst_verify(nxgep->mach, 42214045d941Ssowmini mmac_info->factory_mac_pool[slot], ETHERADDRL)) { 422258324dfcSspeer mutex_exit(nxgep->genlock); 422358324dfcSspeer return (EINVAL); 422458324dfcSspeer } 422558324dfcSspeer if (err = nxge_altmac_set(nxgep, 42264045d941Ssowmini mmac_info->factory_mac_pool[slot], slot)) { 422758324dfcSspeer mutex_exit(nxgep->genlock); 422858324dfcSspeer return (err); 422958324dfcSspeer } 423058324dfcSspeer bcopy(mmac_info->factory_mac_pool[slot], maddr->mma_addr, ETHERADDRL); 423158324dfcSspeer mmac_info->mac_pool[slot].flags |= MMAC_SLOT_USED | MMAC_VENDOR_ADDR; 423258324dfcSspeer mmac_info->naddrfree--; 423358324dfcSspeer 423458324dfcSspeer nxge_mmac_kstat_update(nxgep, slot, B_TRUE); 423558324dfcSspeer mutex_exit(nxgep->genlock); 423658324dfcSspeer 423758324dfcSspeer /* Pass info back to the caller */ 423858324dfcSspeer maddr->mma_slot = slot; 423958324dfcSspeer maddr->mma_addrlen = ETHERADDRL; 424058324dfcSspeer maddr->mma_flags = MMAC_SLOT_USED | MMAC_VENDOR_ADDR; 424158324dfcSspeer 424258324dfcSspeer return (0); 424358324dfcSspeer } 424458324dfcSspeer 424558324dfcSspeer /* 424658324dfcSspeer * Remove the specified mac address and update the HW not to filter 424758324dfcSspeer * the mac address anymore. 424858324dfcSspeer */ 4249678453a8Sspeer int 425058324dfcSspeer nxge_m_mmac_remove(void *arg, mac_addr_slot_t slot) 425158324dfcSspeer { 425258324dfcSspeer p_nxge_t nxgep = arg; 425358324dfcSspeer nxge_mmac_t *mmac_info; 425458324dfcSspeer uint8_t addrn; 425558324dfcSspeer uint8_t portn; 425658324dfcSspeer int err = 0; 425758324dfcSspeer nxge_status_t status; 425858324dfcSspeer 425958324dfcSspeer mutex_enter(nxgep->genlock); 426058324dfcSspeer 426158324dfcSspeer /* 426258324dfcSspeer * Make sure that nxge is initialized, if _start() has 426358324dfcSspeer * not been called. 426458324dfcSspeer */ 426558324dfcSspeer if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 426658324dfcSspeer status = nxge_init(nxgep); 426758324dfcSspeer if (status != NXGE_OK) { 426858324dfcSspeer mutex_exit(nxgep->genlock); 426958324dfcSspeer return (ENXIO); 427058324dfcSspeer } 427158324dfcSspeer } 427258324dfcSspeer 427358324dfcSspeer mmac_info = &nxgep->nxge_mmac_info; 427458324dfcSspeer if (slot < 1 || slot > mmac_info->num_mmac) { 427558324dfcSspeer mutex_exit(nxgep->genlock); 427658324dfcSspeer return (EINVAL); 427758324dfcSspeer } 427858324dfcSspeer 427958324dfcSspeer portn = nxgep->mac.portnum; 428058324dfcSspeer if (portn == XMAC_PORT_0 || portn == XMAC_PORT_1) 428158324dfcSspeer addrn = (uint8_t)slot - 1; 428258324dfcSspeer else 428358324dfcSspeer addrn = (uint8_t)slot; 428458324dfcSspeer 428558324dfcSspeer if (mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED) { 428658324dfcSspeer if (npi_mac_altaddr_disable(nxgep->npi_handle, portn, addrn) 42874045d941Ssowmini == NPI_SUCCESS) { 428858324dfcSspeer mmac_info->naddrfree++; 428958324dfcSspeer mmac_info->mac_pool[slot].flags &= ~MMAC_SLOT_USED; 429058324dfcSspeer /* 429158324dfcSspeer * Regardless if the MAC we just stopped filtering 429258324dfcSspeer * is a user addr or a facory addr, we must set 429358324dfcSspeer * the MMAC_VENDOR_ADDR flag if this slot has an 429458324dfcSspeer * associated factory MAC to indicate that a factory 429558324dfcSspeer * MAC is available. 429658324dfcSspeer */ 429758324dfcSspeer if (slot <= mmac_info->num_factory_mmac) { 429858324dfcSspeer mmac_info->mac_pool[slot].flags 42994045d941Ssowmini |= MMAC_VENDOR_ADDR; 430058324dfcSspeer } 430158324dfcSspeer /* 430258324dfcSspeer * Clear mac_pool[slot].addr so that kstat shows 0 430358324dfcSspeer * alternate MAC address if the slot is not used. 430458324dfcSspeer * (But nxge_m_mmac_get returns the factory MAC even 430558324dfcSspeer * when the slot is not used!) 430658324dfcSspeer */ 430758324dfcSspeer bzero(mmac_info->mac_pool[slot].addr, ETHERADDRL); 430858324dfcSspeer nxge_mmac_kstat_update(nxgep, slot, B_FALSE); 430958324dfcSspeer } else { 431058324dfcSspeer err = EIO; 431158324dfcSspeer } 431258324dfcSspeer } else { 431358324dfcSspeer err = EINVAL; 431458324dfcSspeer } 431558324dfcSspeer 431658324dfcSspeer mutex_exit(nxgep->genlock); 431758324dfcSspeer return (err); 431858324dfcSspeer } 431958324dfcSspeer 432058324dfcSspeer /* 432158324dfcSspeer * Modify a mac address added by nxge_m_mmac_add or nxge_m_mmac_reserve(). 432258324dfcSspeer */ 432358324dfcSspeer static int 432458324dfcSspeer nxge_m_mmac_modify(void *arg, mac_multi_addr_t *maddr) 432558324dfcSspeer { 432658324dfcSspeer p_nxge_t nxgep = arg; 432758324dfcSspeer mac_addr_slot_t slot; 432858324dfcSspeer nxge_mmac_t *mmac_info; 432958324dfcSspeer int err = 0; 433058324dfcSspeer nxge_status_t status; 433158324dfcSspeer 433258324dfcSspeer if (!mac_unicst_verify(nxgep->mach, maddr->mma_addr, 43334045d941Ssowmini maddr->mma_addrlen)) 433458324dfcSspeer return (EINVAL); 433558324dfcSspeer 433658324dfcSspeer slot = maddr->mma_slot; 433758324dfcSspeer 433858324dfcSspeer mutex_enter(nxgep->genlock); 433958324dfcSspeer 434058324dfcSspeer /* 434158324dfcSspeer * Make sure that nxge is initialized, if _start() has 434258324dfcSspeer * not been called. 434358324dfcSspeer */ 434458324dfcSspeer if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 434558324dfcSspeer status = nxge_init(nxgep); 434658324dfcSspeer if (status != NXGE_OK) { 434758324dfcSspeer mutex_exit(nxgep->genlock); 434858324dfcSspeer return (ENXIO); 434958324dfcSspeer } 435058324dfcSspeer } 435158324dfcSspeer 435258324dfcSspeer mmac_info = &nxgep->nxge_mmac_info; 435358324dfcSspeer if (slot < 1 || slot > mmac_info->num_mmac) { 435458324dfcSspeer mutex_exit(nxgep->genlock); 435558324dfcSspeer return (EINVAL); 435658324dfcSspeer } 435758324dfcSspeer if (mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED) { 435858324dfcSspeer if ((err = nxge_altmac_set(nxgep, maddr->mma_addr, slot)) 43594045d941Ssowmini != 0) { 436058324dfcSspeer bcopy(maddr->mma_addr, mmac_info->mac_pool[slot].addr, 43614045d941Ssowmini ETHERADDRL); 436258324dfcSspeer /* 436358324dfcSspeer * Assume that the MAC passed down from the caller 436458324dfcSspeer * is not a factory MAC address (The user should 436558324dfcSspeer * call mmac_remove followed by mmac_reserve if 436658324dfcSspeer * he wants to use the factory MAC for this slot). 436758324dfcSspeer */ 436858324dfcSspeer mmac_info->mac_pool[slot].flags &= ~MMAC_VENDOR_ADDR; 436958324dfcSspeer nxge_mmac_kstat_update(nxgep, slot, B_FALSE); 437058324dfcSspeer } 437158324dfcSspeer } else { 437258324dfcSspeer err = EINVAL; 437358324dfcSspeer } 437458324dfcSspeer mutex_exit(nxgep->genlock); 437558324dfcSspeer return (err); 437658324dfcSspeer } 437758324dfcSspeer 437858324dfcSspeer /* 437958324dfcSspeer * nxge_m_mmac_get() - Get the MAC address and other information 438058324dfcSspeer * related to the slot. mma_flags should be set to 0 in the call. 438158324dfcSspeer * Note: although kstat shows MAC address as zero when a slot is 438258324dfcSspeer * not used, Crossbow expects nxge_m_mmac_get to copy factory MAC 438358324dfcSspeer * to the caller as long as the slot is not using a user MAC address. 438458324dfcSspeer * The following table shows the rules, 438558324dfcSspeer * 438658324dfcSspeer * USED VENDOR mma_addr 438758324dfcSspeer * ------------------------------------------------------------ 438858324dfcSspeer * (1) Slot uses a user MAC: yes no user MAC 438958324dfcSspeer * (2) Slot uses a factory MAC: yes yes factory MAC 439058324dfcSspeer * (3) Slot is not used but is 439158324dfcSspeer * factory MAC capable: no yes factory MAC 439258324dfcSspeer * (4) Slot is not used and is 439358324dfcSspeer * not factory MAC capable: no no 0 439458324dfcSspeer * ------------------------------------------------------------ 439558324dfcSspeer */ 439658324dfcSspeer static int 439758324dfcSspeer nxge_m_mmac_get(void *arg, mac_multi_addr_t *maddr) 439858324dfcSspeer { 439958324dfcSspeer nxge_t *nxgep = arg; 440058324dfcSspeer mac_addr_slot_t slot; 440158324dfcSspeer nxge_mmac_t *mmac_info; 440258324dfcSspeer nxge_status_t status; 440358324dfcSspeer 440458324dfcSspeer slot = maddr->mma_slot; 440558324dfcSspeer 440658324dfcSspeer mutex_enter(nxgep->genlock); 440758324dfcSspeer 440858324dfcSspeer /* 440958324dfcSspeer * Make sure that nxge is initialized, if _start() has 441058324dfcSspeer * not been called. 441158324dfcSspeer */ 441258324dfcSspeer if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 441358324dfcSspeer status = nxge_init(nxgep); 441458324dfcSspeer if (status != NXGE_OK) { 441558324dfcSspeer mutex_exit(nxgep->genlock); 441658324dfcSspeer return (ENXIO); 441758324dfcSspeer } 441858324dfcSspeer } 441958324dfcSspeer 442058324dfcSspeer mmac_info = &nxgep->nxge_mmac_info; 442158324dfcSspeer 442258324dfcSspeer if (slot < 1 || slot > mmac_info->num_mmac) { 442358324dfcSspeer mutex_exit(nxgep->genlock); 442458324dfcSspeer return (EINVAL); 442558324dfcSspeer } 442658324dfcSspeer maddr->mma_flags = 0; 442758324dfcSspeer if (mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED) 442858324dfcSspeer maddr->mma_flags |= MMAC_SLOT_USED; 442958324dfcSspeer 443058324dfcSspeer if (mmac_info->mac_pool[slot].flags & MMAC_VENDOR_ADDR) { 443158324dfcSspeer maddr->mma_flags |= MMAC_VENDOR_ADDR; 443258324dfcSspeer bcopy(mmac_info->factory_mac_pool[slot], 44334045d941Ssowmini maddr->mma_addr, ETHERADDRL); 443458324dfcSspeer maddr->mma_addrlen = ETHERADDRL; 443558324dfcSspeer } else { 443658324dfcSspeer if (maddr->mma_flags & MMAC_SLOT_USED) { 443758324dfcSspeer bcopy(mmac_info->mac_pool[slot].addr, 44384045d941Ssowmini maddr->mma_addr, ETHERADDRL); 443958324dfcSspeer maddr->mma_addrlen = ETHERADDRL; 444058324dfcSspeer } else { 444158324dfcSspeer bzero(maddr->mma_addr, ETHERADDRL); 444258324dfcSspeer maddr->mma_addrlen = 0; 444358324dfcSspeer } 444458324dfcSspeer } 444558324dfcSspeer mutex_exit(nxgep->genlock); 444658324dfcSspeer return (0); 444758324dfcSspeer } 444858324dfcSspeer 444944961713Sgirish static boolean_t 445044961713Sgirish nxge_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 445144961713Sgirish { 445258324dfcSspeer nxge_t *nxgep = arg; 445358324dfcSspeer uint32_t *txflags = cap_data; 445458324dfcSspeer multiaddress_capab_t *mmacp = cap_data; 445544961713Sgirish 445658324dfcSspeer switch (cap) { 445758324dfcSspeer case MAC_CAPAB_HCKSUM: 4458678453a8Sspeer NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4459b4d05839Sml "==> nxge_m_getcapab: checksum %d", nxge_cksum_offload)); 4460b4d05839Sml if (nxge_cksum_offload <= 1) { 4461678453a8Sspeer *txflags = HCKSUM_INET_PARTIAL; 4462678453a8Sspeer } 446344961713Sgirish break; 4464678453a8Sspeer 446544961713Sgirish case MAC_CAPAB_POLL: 446644961713Sgirish /* 446744961713Sgirish * There's nothing for us to fill in, simply returning 446844961713Sgirish * B_TRUE stating that we support polling is sufficient. 446944961713Sgirish */ 447044961713Sgirish break; 447144961713Sgirish 447258324dfcSspeer case MAC_CAPAB_MULTIADDRESS: 4473678453a8Sspeer mmacp = (multiaddress_capab_t *)cap_data; 447458324dfcSspeer mutex_enter(nxgep->genlock); 447558324dfcSspeer 447658324dfcSspeer mmacp->maddr_naddr = nxgep->nxge_mmac_info.num_mmac; 447758324dfcSspeer mmacp->maddr_naddrfree = nxgep->nxge_mmac_info.naddrfree; 4478b4d05839Sml mmacp->maddr_flag = 0; /* 0 is required by PSARC2006/265 */ 447958324dfcSspeer /* 448058324dfcSspeer * maddr_handle is driver's private data, passed back to 448158324dfcSspeer * entry point functions as arg. 448258324dfcSspeer */ 448358324dfcSspeer mmacp->maddr_handle = nxgep; 448458324dfcSspeer mmacp->maddr_add = nxge_m_mmac_add; 448558324dfcSspeer mmacp->maddr_remove = nxge_m_mmac_remove; 448658324dfcSspeer mmacp->maddr_modify = nxge_m_mmac_modify; 448758324dfcSspeer mmacp->maddr_get = nxge_m_mmac_get; 448858324dfcSspeer mmacp->maddr_reserve = nxge_m_mmac_reserve; 448958324dfcSspeer 449058324dfcSspeer mutex_exit(nxgep->genlock); 449158324dfcSspeer break; 4492678453a8Sspeer 449330ac2e7bSml case MAC_CAPAB_LSO: { 449430ac2e7bSml mac_capab_lso_t *cap_lso = cap_data; 449530ac2e7bSml 44963d16f8e7Sml if (nxgep->soft_lso_enable) { 4497b4d05839Sml if (nxge_cksum_offload <= 1) { 4498b4d05839Sml cap_lso->lso_flags = LSO_TX_BASIC_TCP_IPV4; 4499b4d05839Sml if (nxge_lso_max > NXGE_LSO_MAXLEN) { 4500b4d05839Sml nxge_lso_max = NXGE_LSO_MAXLEN; 4501b4d05839Sml } 4502b4d05839Sml cap_lso->lso_basic_tcp_ipv4.lso_max = 4503b4d05839Sml nxge_lso_max; 450430ac2e7bSml } 450530ac2e7bSml break; 450630ac2e7bSml } else { 450730ac2e7bSml return (B_FALSE); 450830ac2e7bSml } 450930ac2e7bSml } 451030ac2e7bSml 4511678453a8Sspeer #if defined(sun4v) 4512678453a8Sspeer case MAC_CAPAB_RINGS: { 4513678453a8Sspeer mac_capab_rings_t *mrings = (mac_capab_rings_t *)cap_data; 4514678453a8Sspeer 4515678453a8Sspeer /* 4516678453a8Sspeer * Only the service domain driver responds to 4517678453a8Sspeer * this capability request. 4518678453a8Sspeer */ 4519678453a8Sspeer if (isLDOMservice(nxgep)) { 4520678453a8Sspeer mrings->mr_handle = (void *)nxgep; 4521678453a8Sspeer 4522678453a8Sspeer /* 4523678453a8Sspeer * No dynamic allocation of groups and 4524678453a8Sspeer * rings at this time. Shares dictate the 45256f157acbSml * configuration. 4526678453a8Sspeer */ 4527678453a8Sspeer mrings->mr_gadd_ring = NULL; 4528678453a8Sspeer mrings->mr_grem_ring = NULL; 4529678453a8Sspeer mrings->mr_rget = NULL; 4530678453a8Sspeer mrings->mr_gget = nxge_hio_group_get; 4531678453a8Sspeer 4532678453a8Sspeer if (mrings->mr_type == MAC_RING_TYPE_RX) { 4533678453a8Sspeer mrings->mr_rnum = 8; /* XXX */ 4534678453a8Sspeer mrings->mr_gnum = 6; /* XXX */ 4535678453a8Sspeer } else { 4536678453a8Sspeer mrings->mr_rnum = 8; /* XXX */ 4537678453a8Sspeer mrings->mr_gnum = 0; /* XXX */ 4538678453a8Sspeer } 4539678453a8Sspeer } else 4540678453a8Sspeer return (B_FALSE); 4541678453a8Sspeer break; 4542678453a8Sspeer } 4543678453a8Sspeer 4544678453a8Sspeer case MAC_CAPAB_SHARES: { 4545678453a8Sspeer mac_capab_share_t *mshares = (mac_capab_share_t *)cap_data; 4546678453a8Sspeer 4547678453a8Sspeer /* 4548678453a8Sspeer * Only the service domain driver responds to 4549678453a8Sspeer * this capability request. 4550678453a8Sspeer */ 4551678453a8Sspeer if (isLDOMservice(nxgep)) { 4552678453a8Sspeer mshares->ms_snum = 3; 4553678453a8Sspeer mshares->ms_handle = (void *)nxgep; 4554678453a8Sspeer mshares->ms_salloc = nxge_hio_share_alloc; 4555678453a8Sspeer mshares->ms_sfree = nxge_hio_share_free; 4556678453a8Sspeer mshares->ms_sadd = NULL; 4557678453a8Sspeer mshares->ms_sremove = NULL; 4558678453a8Sspeer mshares->ms_squery = nxge_hio_share_query; 4559678453a8Sspeer } else 4560678453a8Sspeer return (B_FALSE); 4561678453a8Sspeer break; 4562678453a8Sspeer } 4563678453a8Sspeer #endif 456444961713Sgirish default: 456544961713Sgirish return (B_FALSE); 456644961713Sgirish } 456744961713Sgirish return (B_TRUE); 456844961713Sgirish } 456944961713Sgirish 45701bd6825cSml static boolean_t 45711bd6825cSml nxge_param_locked(mac_prop_id_t pr_num) 45721bd6825cSml { 45731bd6825cSml /* 45741bd6825cSml * All adv_* parameters are locked (read-only) while 45751bd6825cSml * the device is in any sort of loopback mode ... 45761bd6825cSml */ 45771bd6825cSml switch (pr_num) { 45783fd94f8cSam case MAC_PROP_ADV_1000FDX_CAP: 45793fd94f8cSam case MAC_PROP_EN_1000FDX_CAP: 45803fd94f8cSam case MAC_PROP_ADV_1000HDX_CAP: 45813fd94f8cSam case MAC_PROP_EN_1000HDX_CAP: 45823fd94f8cSam case MAC_PROP_ADV_100FDX_CAP: 45833fd94f8cSam case MAC_PROP_EN_100FDX_CAP: 45843fd94f8cSam case MAC_PROP_ADV_100HDX_CAP: 45853fd94f8cSam case MAC_PROP_EN_100HDX_CAP: 45863fd94f8cSam case MAC_PROP_ADV_10FDX_CAP: 45873fd94f8cSam case MAC_PROP_EN_10FDX_CAP: 45883fd94f8cSam case MAC_PROP_ADV_10HDX_CAP: 45893fd94f8cSam case MAC_PROP_EN_10HDX_CAP: 45903fd94f8cSam case MAC_PROP_AUTONEG: 45913fd94f8cSam case MAC_PROP_FLOWCTRL: 45921bd6825cSml return (B_TRUE); 45931bd6825cSml } 45941bd6825cSml return (B_FALSE); 45951bd6825cSml } 45961bd6825cSml 45971bd6825cSml /* 45981bd6825cSml * callback functions for set/get of properties 45991bd6825cSml */ 46001bd6825cSml static int 46011bd6825cSml nxge_m_setprop(void *barg, const char *pr_name, mac_prop_id_t pr_num, 46021bd6825cSml uint_t pr_valsize, const void *pr_val) 46031bd6825cSml { 46041bd6825cSml nxge_t *nxgep = barg; 46051bd6825cSml p_nxge_param_t param_arr; 46061bd6825cSml p_nxge_stats_t statsp; 46071bd6825cSml int err = 0; 46081bd6825cSml uint8_t val; 46091bd6825cSml uint32_t cur_mtu, new_mtu, old_framesize; 46101bd6825cSml link_flowctrl_t fl; 46111bd6825cSml 46121bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_setprop")); 46131bd6825cSml param_arr = nxgep->param_arr; 46141bd6825cSml statsp = nxgep->statsp; 46151bd6825cSml mutex_enter(nxgep->genlock); 46161bd6825cSml if (statsp->port_stats.lb_mode != nxge_lb_normal && 46171bd6825cSml nxge_param_locked(pr_num)) { 46181bd6825cSml /* 46191bd6825cSml * All adv_* parameters are locked (read-only) 46201bd6825cSml * while the device is in any sort of loopback mode. 46211bd6825cSml */ 46221bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 46231bd6825cSml "==> nxge_m_setprop: loopback mode: read only")); 46241bd6825cSml mutex_exit(nxgep->genlock); 46251bd6825cSml return (EBUSY); 46261bd6825cSml } 46271bd6825cSml 46281bd6825cSml val = *(uint8_t *)pr_val; 46291bd6825cSml switch (pr_num) { 46303fd94f8cSam case MAC_PROP_EN_1000FDX_CAP: 46311bd6825cSml nxgep->param_en_1000fdx = val; 46321bd6825cSml param_arr[param_anar_1000fdx].value = val; 46331bd6825cSml 46341bd6825cSml goto reprogram; 46351bd6825cSml 46363fd94f8cSam case MAC_PROP_EN_100FDX_CAP: 46371bd6825cSml nxgep->param_en_100fdx = val; 46381bd6825cSml param_arr[param_anar_100fdx].value = val; 46391bd6825cSml 46401bd6825cSml goto reprogram; 46411bd6825cSml 46423fd94f8cSam case MAC_PROP_EN_10FDX_CAP: 46431bd6825cSml nxgep->param_en_10fdx = val; 46441bd6825cSml param_arr[param_anar_10fdx].value = val; 46451bd6825cSml 46461bd6825cSml goto reprogram; 46471bd6825cSml 46483fd94f8cSam case MAC_PROP_EN_1000HDX_CAP: 46493fd94f8cSam case MAC_PROP_EN_100HDX_CAP: 46503fd94f8cSam case MAC_PROP_EN_10HDX_CAP: 46513fd94f8cSam case MAC_PROP_ADV_1000FDX_CAP: 46523fd94f8cSam case MAC_PROP_ADV_1000HDX_CAP: 46533fd94f8cSam case MAC_PROP_ADV_100FDX_CAP: 46543fd94f8cSam case MAC_PROP_ADV_100HDX_CAP: 46553fd94f8cSam case MAC_PROP_ADV_10FDX_CAP: 46563fd94f8cSam case MAC_PROP_ADV_10HDX_CAP: 46573fd94f8cSam case MAC_PROP_STATUS: 46583fd94f8cSam case MAC_PROP_SPEED: 46593fd94f8cSam case MAC_PROP_DUPLEX: 46601bd6825cSml err = EINVAL; /* cannot set read-only properties */ 46611bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 46621bd6825cSml "==> nxge_m_setprop: read only property %d", 46631bd6825cSml pr_num)); 46641bd6825cSml break; 46651bd6825cSml 46663fd94f8cSam case MAC_PROP_AUTONEG: 46671bd6825cSml param_arr[param_autoneg].value = val; 46681bd6825cSml 46691bd6825cSml goto reprogram; 46701bd6825cSml 46713fd94f8cSam case MAC_PROP_MTU: 46721bd6825cSml if (nxgep->nxge_mac_state == NXGE_MAC_STARTED) { 46731bd6825cSml err = EBUSY; 46741bd6825cSml break; 46751bd6825cSml } 46761bd6825cSml 46771bd6825cSml cur_mtu = nxgep->mac.default_mtu; 46781bd6825cSml bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 46791bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 46801bd6825cSml "==> nxge_m_setprop: set MTU: %d is_jumbo %d", 46811bd6825cSml new_mtu, nxgep->mac.is_jumbo)); 46821bd6825cSml 46831bd6825cSml if (new_mtu == cur_mtu) { 46841bd6825cSml err = 0; 46851bd6825cSml break; 46861bd6825cSml } 46871bd6825cSml if (new_mtu < NXGE_DEFAULT_MTU || 46881bd6825cSml new_mtu > NXGE_MAXIMUM_MTU) { 46891bd6825cSml err = EINVAL; 46901bd6825cSml break; 46911bd6825cSml } 46921bd6825cSml 46931bd6825cSml if ((new_mtu > NXGE_DEFAULT_MTU) && 46941bd6825cSml !nxgep->mac.is_jumbo) { 46951bd6825cSml err = EINVAL; 46961bd6825cSml break; 46971bd6825cSml } 46981bd6825cSml 46991bd6825cSml old_framesize = (uint32_t)nxgep->mac.maxframesize; 47001bd6825cSml nxgep->mac.maxframesize = (uint16_t) 47011bd6825cSml (new_mtu + NXGE_EHEADER_VLAN_CRC); 47021bd6825cSml if (nxge_mac_set_framesize(nxgep)) { 4703c2d37b8bSml nxgep->mac.maxframesize = 4704c2d37b8bSml (uint16_t)old_framesize; 47051bd6825cSml err = EINVAL; 47061bd6825cSml break; 47071bd6825cSml } 47081bd6825cSml 47091bd6825cSml err = mac_maxsdu_update(nxgep->mach, new_mtu); 47101bd6825cSml if (err) { 4711c2d37b8bSml nxgep->mac.maxframesize = 4712c2d37b8bSml (uint16_t)old_framesize; 47131bd6825cSml err = EINVAL; 47141bd6825cSml break; 47151bd6825cSml } 47161bd6825cSml 47171bd6825cSml nxgep->mac.default_mtu = new_mtu; 47181bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 47191bd6825cSml "==> nxge_m_setprop: set MTU: %d maxframe %d", 47201bd6825cSml new_mtu, nxgep->mac.maxframesize)); 47211bd6825cSml break; 47221bd6825cSml 47233fd94f8cSam case MAC_PROP_FLOWCTRL: 47241bd6825cSml bcopy(pr_val, &fl, sizeof (fl)); 47251bd6825cSml switch (fl) { 47261bd6825cSml default: 47271bd6825cSml err = EINVAL; 47281bd6825cSml break; 47291bd6825cSml 47301bd6825cSml case LINK_FLOWCTRL_NONE: 47311bd6825cSml param_arr[param_anar_pause].value = 0; 47321bd6825cSml break; 47331bd6825cSml 47341bd6825cSml case LINK_FLOWCTRL_RX: 47351bd6825cSml param_arr[param_anar_pause].value = 1; 47361bd6825cSml break; 47371bd6825cSml 47381bd6825cSml case LINK_FLOWCTRL_TX: 47391bd6825cSml case LINK_FLOWCTRL_BI: 47401bd6825cSml err = EINVAL; 47411bd6825cSml break; 47421bd6825cSml } 47431bd6825cSml 47441bd6825cSml reprogram: 47451bd6825cSml if (err == 0) { 47461bd6825cSml if (!nxge_param_link_update(nxgep)) { 47471bd6825cSml err = EINVAL; 47481bd6825cSml } 47491bd6825cSml } 47501bd6825cSml break; 47513fd94f8cSam case MAC_PROP_PRIVATE: 47521bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 47531bd6825cSml "==> nxge_m_setprop: private property")); 47541bd6825cSml err = nxge_set_priv_prop(nxgep, pr_name, pr_valsize, 47551bd6825cSml pr_val); 47561bd6825cSml break; 47574045d941Ssowmini 47584045d941Ssowmini default: 47594045d941Ssowmini err = ENOTSUP; 47604045d941Ssowmini break; 47611bd6825cSml } 47621bd6825cSml 47631bd6825cSml mutex_exit(nxgep->genlock); 47641bd6825cSml 47651bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 47661bd6825cSml "<== nxge_m_setprop (return %d)", err)); 47671bd6825cSml return (err); 47681bd6825cSml } 47691bd6825cSml 47701bd6825cSml static int 47711bd6825cSml nxge_m_getprop(void *barg, const char *pr_name, mac_prop_id_t pr_num, 47724045d941Ssowmini uint_t pr_flags, uint_t pr_valsize, void *pr_val) 47731bd6825cSml { 47741bd6825cSml nxge_t *nxgep = barg; 47751bd6825cSml p_nxge_param_t param_arr = nxgep->param_arr; 47761bd6825cSml p_nxge_stats_t statsp = nxgep->statsp; 47771bd6825cSml int err = 0; 47781bd6825cSml link_flowctrl_t fl; 47791bd6825cSml uint64_t tmp = 0; 47804045d941Ssowmini link_state_t ls; 47813fd94f8cSam boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 47821bd6825cSml 47831bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 47841bd6825cSml "==> nxge_m_getprop: pr_num %d", pr_num)); 47854045d941Ssowmini 47864045d941Ssowmini if (pr_valsize == 0) 47874045d941Ssowmini return (EINVAL); 47884045d941Ssowmini 47893fd94f8cSam if ((is_default) && (pr_num != MAC_PROP_PRIVATE)) { 47904045d941Ssowmini err = nxge_get_def_val(nxgep, pr_num, pr_valsize, pr_val); 47914045d941Ssowmini return (err); 47924045d941Ssowmini } 47934045d941Ssowmini 47941bd6825cSml bzero(pr_val, pr_valsize); 47951bd6825cSml switch (pr_num) { 47963fd94f8cSam case MAC_PROP_DUPLEX: 47971bd6825cSml *(uint8_t *)pr_val = statsp->mac_stats.link_duplex; 47981bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 47991bd6825cSml "==> nxge_m_getprop: duplex mode %d", 48001bd6825cSml *(uint8_t *)pr_val)); 48011bd6825cSml break; 48021bd6825cSml 48033fd94f8cSam case MAC_PROP_SPEED: 48041bd6825cSml if (pr_valsize < sizeof (uint64_t)) 48051bd6825cSml return (EINVAL); 48061bd6825cSml tmp = statsp->mac_stats.link_speed * 1000000ull; 48071bd6825cSml bcopy(&tmp, pr_val, sizeof (tmp)); 48081bd6825cSml break; 48091bd6825cSml 48103fd94f8cSam case MAC_PROP_STATUS: 48114045d941Ssowmini if (pr_valsize < sizeof (link_state_t)) 48121bd6825cSml return (EINVAL); 48134045d941Ssowmini if (!statsp->mac_stats.link_up) 48144045d941Ssowmini ls = LINK_STATE_DOWN; 48154045d941Ssowmini else 48164045d941Ssowmini ls = LINK_STATE_UP; 48174045d941Ssowmini bcopy(&ls, pr_val, sizeof (ls)); 48181bd6825cSml break; 48191bd6825cSml 48203fd94f8cSam case MAC_PROP_AUTONEG: 48211bd6825cSml *(uint8_t *)pr_val = 48221bd6825cSml param_arr[param_autoneg].value; 48231bd6825cSml break; 48241bd6825cSml 48253fd94f8cSam case MAC_PROP_FLOWCTRL: 48261bd6825cSml if (pr_valsize < sizeof (link_flowctrl_t)) 48271bd6825cSml return (EINVAL); 48281bd6825cSml 48291bd6825cSml fl = LINK_FLOWCTRL_NONE; 48301bd6825cSml if (param_arr[param_anar_pause].value) { 48311bd6825cSml fl = LINK_FLOWCTRL_RX; 48321bd6825cSml } 48331bd6825cSml bcopy(&fl, pr_val, sizeof (fl)); 48341bd6825cSml break; 48351bd6825cSml 48363fd94f8cSam case MAC_PROP_ADV_1000FDX_CAP: 48371bd6825cSml *(uint8_t *)pr_val = 48381bd6825cSml param_arr[param_anar_1000fdx].value; 48391bd6825cSml break; 48401bd6825cSml 48413fd94f8cSam case MAC_PROP_EN_1000FDX_CAP: 48421bd6825cSml *(uint8_t *)pr_val = nxgep->param_en_1000fdx; 48431bd6825cSml break; 48441bd6825cSml 48453fd94f8cSam case MAC_PROP_ADV_100FDX_CAP: 48461bd6825cSml *(uint8_t *)pr_val = 48471bd6825cSml param_arr[param_anar_100fdx].value; 48481bd6825cSml break; 48491bd6825cSml 48503fd94f8cSam case MAC_PROP_EN_100FDX_CAP: 48511bd6825cSml *(uint8_t *)pr_val = nxgep->param_en_100fdx; 48521bd6825cSml break; 48531bd6825cSml 48543fd94f8cSam case MAC_PROP_ADV_10FDX_CAP: 48551bd6825cSml *(uint8_t *)pr_val = 48561bd6825cSml param_arr[param_anar_10fdx].value; 48571bd6825cSml break; 48581bd6825cSml 48593fd94f8cSam case MAC_PROP_EN_10FDX_CAP: 48601bd6825cSml *(uint8_t *)pr_val = nxgep->param_en_10fdx; 48611bd6825cSml break; 48621bd6825cSml 48633fd94f8cSam case MAC_PROP_EN_1000HDX_CAP: 48643fd94f8cSam case MAC_PROP_EN_100HDX_CAP: 48653fd94f8cSam case MAC_PROP_EN_10HDX_CAP: 48663fd94f8cSam case MAC_PROP_ADV_1000HDX_CAP: 48673fd94f8cSam case MAC_PROP_ADV_100HDX_CAP: 48683fd94f8cSam case MAC_PROP_ADV_10HDX_CAP: 48694045d941Ssowmini err = ENOTSUP; 48701bd6825cSml break; 48711bd6825cSml 48723fd94f8cSam case MAC_PROP_PRIVATE: 48734045d941Ssowmini err = nxge_get_priv_prop(nxgep, pr_name, pr_flags, 48744045d941Ssowmini pr_valsize, pr_val); 48754045d941Ssowmini break; 48761bd6825cSml default: 48774045d941Ssowmini err = EINVAL; 48784045d941Ssowmini break; 48791bd6825cSml } 48801bd6825cSml 48811bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_getprop")); 48821bd6825cSml 48831bd6825cSml return (err); 48841bd6825cSml } 48851bd6825cSml 48861bd6825cSml /* ARGSUSED */ 48871bd6825cSml static int 48881bd6825cSml nxge_set_priv_prop(p_nxge_t nxgep, const char *pr_name, uint_t pr_valsize, 48891bd6825cSml const void *pr_val) 48901bd6825cSml { 48911bd6825cSml p_nxge_param_t param_arr = nxgep->param_arr; 48921bd6825cSml int err = 0; 48931bd6825cSml long result; 48941bd6825cSml 48951bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 48961bd6825cSml "==> nxge_set_priv_prop: name %s", pr_name)); 48971bd6825cSml 48981bd6825cSml if (strcmp(pr_name, "_accept_jumbo") == 0) { 48991bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 49001bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 49011bd6825cSml "<== nxge_set_priv_prop: name %s " 49021bd6825cSml "pr_val %s result %d " 49031bd6825cSml "param %d is_jumbo %d", 49041bd6825cSml pr_name, pr_val, result, 49051bd6825cSml param_arr[param_accept_jumbo].value, 49061bd6825cSml nxgep->mac.is_jumbo)); 49071bd6825cSml 49081bd6825cSml if (result > 1 || result < 0) { 49091bd6825cSml err = EINVAL; 49101bd6825cSml } else { 49111bd6825cSml if (nxgep->mac.is_jumbo == 49121bd6825cSml (uint32_t)result) { 49131bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 49141bd6825cSml "no change (%d %d)", 49151bd6825cSml nxgep->mac.is_jumbo, 49161bd6825cSml result)); 49171bd6825cSml return (0); 49181bd6825cSml } 49191bd6825cSml } 49201bd6825cSml 49211bd6825cSml param_arr[param_accept_jumbo].value = result; 49221bd6825cSml nxgep->mac.is_jumbo = B_FALSE; 49231bd6825cSml if (result) { 49241bd6825cSml nxgep->mac.is_jumbo = B_TRUE; 49251bd6825cSml } 49261bd6825cSml 49271bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 49281bd6825cSml "<== nxge_set_priv_prop: name %s (value %d) is_jumbo %d", 49291bd6825cSml pr_name, result, nxgep->mac.is_jumbo)); 49301bd6825cSml 49311bd6825cSml return (err); 49321bd6825cSml } 49331bd6825cSml 49341bd6825cSml /* Blanking */ 49351bd6825cSml if (strcmp(pr_name, "_rxdma_intr_time") == 0) { 49361bd6825cSml err = nxge_param_rx_intr_time(nxgep, NULL, NULL, 49371bd6825cSml (char *)pr_val, 49381bd6825cSml (caddr_t)¶m_arr[param_rxdma_intr_time]); 49391bd6825cSml if (err) { 49401bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 49411bd6825cSml "<== nxge_set_priv_prop: " 49421bd6825cSml "unable to set (%s)", pr_name)); 49431bd6825cSml err = EINVAL; 49441bd6825cSml } else { 49451bd6825cSml err = 0; 49461bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 49471bd6825cSml "<== nxge_set_priv_prop: " 49481bd6825cSml "set (%s)", pr_name)); 49491bd6825cSml } 49501bd6825cSml 49511bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 49521bd6825cSml "<== nxge_set_priv_prop: name %s (value %d)", 49531bd6825cSml pr_name, result)); 49541bd6825cSml 49551bd6825cSml return (err); 49561bd6825cSml } 49571bd6825cSml 49581bd6825cSml if (strcmp(pr_name, "_rxdma_intr_pkts") == 0) { 49591bd6825cSml err = nxge_param_rx_intr_pkts(nxgep, NULL, NULL, 49601bd6825cSml (char *)pr_val, 49611bd6825cSml (caddr_t)¶m_arr[param_rxdma_intr_pkts]); 49621bd6825cSml if (err) { 49631bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 49641bd6825cSml "<== nxge_set_priv_prop: " 49651bd6825cSml "unable to set (%s)", pr_name)); 49661bd6825cSml err = EINVAL; 49671bd6825cSml } else { 49681bd6825cSml err = 0; 49691bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 49701bd6825cSml "<== nxge_set_priv_prop: " 49711bd6825cSml "set (%s)", pr_name)); 49721bd6825cSml } 49731bd6825cSml 49741bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 49751bd6825cSml "<== nxge_set_priv_prop: name %s (value %d)", 49761bd6825cSml pr_name, result)); 49771bd6825cSml 49781bd6825cSml return (err); 49791bd6825cSml } 49801bd6825cSml 49811bd6825cSml /* Classification */ 49821bd6825cSml if (strcmp(pr_name, "_class_opt_ipv4_tcp") == 0) { 49831bd6825cSml if (pr_val == NULL) { 49841bd6825cSml err = EINVAL; 49851bd6825cSml return (err); 49861bd6825cSml } 49871bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 49881bd6825cSml 49891bd6825cSml err = nxge_param_set_ip_opt(nxgep, NULL, 49901bd6825cSml NULL, (char *)pr_val, 49911bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv4_tcp]); 49921bd6825cSml 49931bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 49941bd6825cSml "<== nxge_set_priv_prop: name %s (value 0x%x)", 49951bd6825cSml pr_name, result)); 49961bd6825cSml 49971bd6825cSml return (err); 49981bd6825cSml } 49991bd6825cSml 50001bd6825cSml if (strcmp(pr_name, "_class_opt_ipv4_udp") == 0) { 50011bd6825cSml if (pr_val == NULL) { 50021bd6825cSml err = EINVAL; 50031bd6825cSml return (err); 50041bd6825cSml } 50051bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 50061bd6825cSml 50071bd6825cSml err = nxge_param_set_ip_opt(nxgep, NULL, 50081bd6825cSml NULL, (char *)pr_val, 50091bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv4_udp]); 50101bd6825cSml 50111bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 50121bd6825cSml "<== nxge_set_priv_prop: name %s (value 0x%x)", 50131bd6825cSml pr_name, result)); 50141bd6825cSml 50151bd6825cSml return (err); 50161bd6825cSml } 50171bd6825cSml if (strcmp(pr_name, "_class_opt_ipv4_ah") == 0) { 50181bd6825cSml if (pr_val == NULL) { 50191bd6825cSml err = EINVAL; 50201bd6825cSml return (err); 50211bd6825cSml } 50221bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 50231bd6825cSml 50241bd6825cSml err = nxge_param_set_ip_opt(nxgep, NULL, 50251bd6825cSml NULL, (char *)pr_val, 50261bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv4_ah]); 50271bd6825cSml 50281bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 50291bd6825cSml "<== nxge_set_priv_prop: name %s (value 0x%x)", 50301bd6825cSml pr_name, result)); 50311bd6825cSml 50321bd6825cSml return (err); 50331bd6825cSml } 50341bd6825cSml if (strcmp(pr_name, "_class_opt_ipv4_sctp") == 0) { 50351bd6825cSml if (pr_val == NULL) { 50361bd6825cSml err = EINVAL; 50371bd6825cSml return (err); 50381bd6825cSml } 50391bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 50401bd6825cSml 50411bd6825cSml err = nxge_param_set_ip_opt(nxgep, NULL, 50421bd6825cSml NULL, (char *)pr_val, 50431bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv4_sctp]); 50441bd6825cSml 50451bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 50461bd6825cSml "<== nxge_set_priv_prop: name %s (value 0x%x)", 50471bd6825cSml pr_name, result)); 50481bd6825cSml 50491bd6825cSml return (err); 50501bd6825cSml } 50511bd6825cSml 50521bd6825cSml if (strcmp(pr_name, "_class_opt_ipv6_tcp") == 0) { 50531bd6825cSml if (pr_val == NULL) { 50541bd6825cSml err = EINVAL; 50551bd6825cSml return (err); 50561bd6825cSml } 50571bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 50581bd6825cSml 50591bd6825cSml err = nxge_param_set_ip_opt(nxgep, NULL, 50601bd6825cSml NULL, (char *)pr_val, 50611bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv6_tcp]); 50621bd6825cSml 50631bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 50641bd6825cSml "<== nxge_set_priv_prop: name %s (value 0x%x)", 50651bd6825cSml pr_name, result)); 50661bd6825cSml 50671bd6825cSml return (err); 50681bd6825cSml } 50691bd6825cSml 50701bd6825cSml if (strcmp(pr_name, "_class_opt_ipv6_udp") == 0) { 50711bd6825cSml if (pr_val == NULL) { 50721bd6825cSml err = EINVAL; 50731bd6825cSml return (err); 50741bd6825cSml } 50751bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 50761bd6825cSml 50771bd6825cSml err = nxge_param_set_ip_opt(nxgep, NULL, 50781bd6825cSml NULL, (char *)pr_val, 50791bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv6_udp]); 50801bd6825cSml 50811bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 50821bd6825cSml "<== nxge_set_priv_prop: name %s (value 0x%x)", 50831bd6825cSml pr_name, result)); 50841bd6825cSml 50851bd6825cSml return (err); 50861bd6825cSml } 50871bd6825cSml if (strcmp(pr_name, "_class_opt_ipv6_ah") == 0) { 50881bd6825cSml if (pr_val == NULL) { 50891bd6825cSml err = EINVAL; 50901bd6825cSml return (err); 50911bd6825cSml } 50921bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 50931bd6825cSml 50941bd6825cSml err = nxge_param_set_ip_opt(nxgep, NULL, 50951bd6825cSml NULL, (char *)pr_val, 50961bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv6_ah]); 50971bd6825cSml 50981bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 50991bd6825cSml "<== nxge_set_priv_prop: name %s (value 0x%x)", 51001bd6825cSml pr_name, result)); 51011bd6825cSml 51021bd6825cSml return (err); 51031bd6825cSml } 51041bd6825cSml if (strcmp(pr_name, "_class_opt_ipv6_sctp") == 0) { 51051bd6825cSml if (pr_val == NULL) { 51061bd6825cSml err = EINVAL; 51071bd6825cSml return (err); 51081bd6825cSml } 51091bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 51101bd6825cSml 51111bd6825cSml err = nxge_param_set_ip_opt(nxgep, NULL, 51121bd6825cSml NULL, (char *)pr_val, 51131bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv6_sctp]); 51141bd6825cSml 51151bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 51161bd6825cSml "<== nxge_set_priv_prop: name %s (value 0x%x)", 51171bd6825cSml pr_name, result)); 51181bd6825cSml 51191bd6825cSml return (err); 51201bd6825cSml } 51211bd6825cSml 51221bd6825cSml if (strcmp(pr_name, "_soft_lso_enable") == 0) { 51231bd6825cSml if (nxgep->nxge_mac_state == NXGE_MAC_STARTED) { 51241bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 51251bd6825cSml "==> nxge_set_priv_prop: name %s (busy)", pr_name)); 51261bd6825cSml err = EBUSY; 51271bd6825cSml return (err); 51281bd6825cSml } 51291bd6825cSml if (pr_val == NULL) { 51301bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 51311bd6825cSml "==> nxge_set_priv_prop: name %s (null)", pr_name)); 51321bd6825cSml err = EINVAL; 51331bd6825cSml return (err); 51341bd6825cSml } 51351bd6825cSml 51361bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 51371bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 51381bd6825cSml "<== nxge_set_priv_prop: name %s " 51391bd6825cSml "(lso %d pr_val %s value %d)", 51401bd6825cSml pr_name, nxgep->soft_lso_enable, pr_val, result)); 51411bd6825cSml 51421bd6825cSml if (result > 1 || result < 0) { 51431bd6825cSml err = EINVAL; 51441bd6825cSml } else { 51451bd6825cSml if (nxgep->soft_lso_enable == (uint32_t)result) { 51461bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 51471bd6825cSml "no change (%d %d)", 51481bd6825cSml nxgep->soft_lso_enable, result)); 51491bd6825cSml return (0); 51501bd6825cSml } 51511bd6825cSml } 51521bd6825cSml 51531bd6825cSml nxgep->soft_lso_enable = (int)result; 51541bd6825cSml 51551bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 51561bd6825cSml "<== nxge_set_priv_prop: name %s (value %d)", 51571bd6825cSml pr_name, result)); 51581bd6825cSml 51591bd6825cSml return (err); 51601bd6825cSml } 516100161856Syc /* 516200161856Syc * Commands like "ndd -set /dev/nxge0 adv_10gfdx_cap 1" cause the 516300161856Syc * following code to be executed. 516400161856Syc */ 51654045d941Ssowmini if (strcmp(pr_name, "_adv_10gfdx_cap") == 0) { 51664045d941Ssowmini err = nxge_param_set_mac(nxgep, NULL, NULL, (char *)pr_val, 51674045d941Ssowmini (caddr_t)¶m_arr[param_anar_10gfdx]); 51684045d941Ssowmini return (err); 51694045d941Ssowmini } 51704045d941Ssowmini if (strcmp(pr_name, "_adv_pause_cap") == 0) { 51714045d941Ssowmini err = nxge_param_set_mac(nxgep, NULL, NULL, (char *)pr_val, 51724045d941Ssowmini (caddr_t)¶m_arr[param_anar_pause]); 51734045d941Ssowmini return (err); 51744045d941Ssowmini } 51751bd6825cSml 51761bd6825cSml return (EINVAL); 51771bd6825cSml } 51781bd6825cSml 51791bd6825cSml static int 51804045d941Ssowmini nxge_get_priv_prop(p_nxge_t nxgep, const char *pr_name, uint_t pr_flags, 51814045d941Ssowmini uint_t pr_valsize, void *pr_val) 51821bd6825cSml { 51831bd6825cSml p_nxge_param_t param_arr = nxgep->param_arr; 51841bd6825cSml char valstr[MAXNAMELEN]; 51851bd6825cSml int err = EINVAL; 51861bd6825cSml uint_t strsize; 51873fd94f8cSam boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 51881bd6825cSml 51891bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 51901bd6825cSml "==> nxge_get_priv_prop: property %s", pr_name)); 51911bd6825cSml 51921bd6825cSml /* function number */ 51931bd6825cSml if (strcmp(pr_name, "_function_number") == 0) { 51944045d941Ssowmini if (is_default) 51954045d941Ssowmini return (ENOTSUP); 51964045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%d", 51974045d941Ssowmini nxgep->function_num); 51981bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 51991bd6825cSml "==> nxge_get_priv_prop: name %s " 52001bd6825cSml "(value %d valstr %s)", 52011bd6825cSml pr_name, nxgep->function_num, valstr)); 52021bd6825cSml 52031bd6825cSml err = 0; 52041bd6825cSml goto done; 52051bd6825cSml } 52061bd6825cSml 52071bd6825cSml /* Neptune firmware version */ 52081bd6825cSml if (strcmp(pr_name, "_fw_version") == 0) { 52094045d941Ssowmini if (is_default) 52104045d941Ssowmini return (ENOTSUP); 52114045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%s", 52124045d941Ssowmini nxgep->vpd_info.ver); 52131bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 52141bd6825cSml "==> nxge_get_priv_prop: name %s " 52151bd6825cSml "(value %d valstr %s)", 52161bd6825cSml pr_name, nxgep->vpd_info.ver, valstr)); 52171bd6825cSml 52181bd6825cSml err = 0; 52191bd6825cSml goto done; 52201bd6825cSml } 52211bd6825cSml 52221bd6825cSml /* port PHY mode */ 52231bd6825cSml if (strcmp(pr_name, "_port_mode") == 0) { 52244045d941Ssowmini if (is_default) 52254045d941Ssowmini return (ENOTSUP); 52261bd6825cSml switch (nxgep->mac.portmode) { 52271bd6825cSml case PORT_1G_COPPER: 52284045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "1G copper %s", 52291bd6825cSml nxgep->hot_swappable_phy ? 52301bd6825cSml "[Hot Swappable]" : ""); 52311bd6825cSml break; 52321bd6825cSml case PORT_1G_FIBER: 52334045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "1G fiber %s", 52341bd6825cSml nxgep->hot_swappable_phy ? 52351bd6825cSml "[hot swappable]" : ""); 52361bd6825cSml break; 52371bd6825cSml case PORT_10G_COPPER: 52384045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), 52394045d941Ssowmini "10G copper %s", 52401bd6825cSml nxgep->hot_swappable_phy ? 52411bd6825cSml "[hot swappable]" : ""); 52421bd6825cSml break; 52431bd6825cSml case PORT_10G_FIBER: 52444045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "10G fiber %s", 52451bd6825cSml nxgep->hot_swappable_phy ? 52461bd6825cSml "[hot swappable]" : ""); 52471bd6825cSml break; 52481bd6825cSml case PORT_10G_SERDES: 52494045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), 52504045d941Ssowmini "10G serdes %s", nxgep->hot_swappable_phy ? 52511bd6825cSml "[hot swappable]" : ""); 52521bd6825cSml break; 52531bd6825cSml case PORT_1G_SERDES: 52544045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "1G serdes %s", 52551bd6825cSml nxgep->hot_swappable_phy ? 52561bd6825cSml "[hot swappable]" : ""); 52571bd6825cSml break; 525800161856Syc case PORT_1G_TN1010: 525900161856Syc (void) snprintf(valstr, sizeof (valstr), 526000161856Syc "1G TN1010 copper %s", nxgep->hot_swappable_phy ? 526100161856Syc "[hot swappable]" : ""); 526200161856Syc break; 526300161856Syc case PORT_10G_TN1010: 526400161856Syc (void) snprintf(valstr, sizeof (valstr), 526500161856Syc "10G TN1010 copper %s", nxgep->hot_swappable_phy ? 526600161856Syc "[hot swappable]" : ""); 526700161856Syc break; 52681bd6825cSml case PORT_1G_RGMII_FIBER: 52694045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), 52704045d941Ssowmini "1G rgmii fiber %s", nxgep->hot_swappable_phy ? 52711bd6825cSml "[hot swappable]" : ""); 52721bd6825cSml break; 52731bd6825cSml case PORT_HSP_MODE: 52744045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), 5275c2d37b8bSml "phy not present[hot swappable]"); 52761bd6825cSml break; 52771bd6825cSml default: 52784045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "unknown %s", 52791bd6825cSml nxgep->hot_swappable_phy ? 52801bd6825cSml "[hot swappable]" : ""); 52811bd6825cSml break; 52821bd6825cSml } 52831bd6825cSml 52841bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 52851bd6825cSml "==> nxge_get_priv_prop: name %s (value %s)", 52861bd6825cSml pr_name, valstr)); 52871bd6825cSml 52881bd6825cSml err = 0; 52891bd6825cSml goto done; 52901bd6825cSml } 52911bd6825cSml 52921bd6825cSml /* Hot swappable PHY */ 52931bd6825cSml if (strcmp(pr_name, "_hot_swap_phy") == 0) { 52944045d941Ssowmini if (is_default) 52954045d941Ssowmini return (ENOTSUP); 52964045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%s", 52971bd6825cSml nxgep->hot_swappable_phy ? 52981bd6825cSml "yes" : "no"); 52991bd6825cSml 53001bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 53011bd6825cSml "==> nxge_get_priv_prop: name %s " 53021bd6825cSml "(value %d valstr %s)", 53031bd6825cSml pr_name, nxgep->hot_swappable_phy, valstr)); 53041bd6825cSml 53051bd6825cSml err = 0; 53061bd6825cSml goto done; 53071bd6825cSml } 53081bd6825cSml 53091bd6825cSml 53101bd6825cSml /* accept jumbo */ 53111bd6825cSml if (strcmp(pr_name, "_accept_jumbo") == 0) { 53124045d941Ssowmini if (is_default) 53134045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%d", 0); 53144045d941Ssowmini else 53154045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), 53164045d941Ssowmini "%d", nxgep->mac.is_jumbo); 53171bd6825cSml err = 0; 53181bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 53191bd6825cSml "==> nxge_get_priv_prop: name %s (value %d (%d, %d))", 53201bd6825cSml pr_name, 53211bd6825cSml (uint32_t)param_arr[param_accept_jumbo].value, 53221bd6825cSml nxgep->mac.is_jumbo, 53231bd6825cSml nxge_jumbo_enable)); 53241bd6825cSml 53251bd6825cSml goto done; 53261bd6825cSml } 53271bd6825cSml 53281bd6825cSml /* Receive Interrupt Blanking Parameters */ 53291bd6825cSml if (strcmp(pr_name, "_rxdma_intr_time") == 0) { 53304045d941Ssowmini err = 0; 53314045d941Ssowmini if (is_default) { 53324045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), 53334045d941Ssowmini "%d", RXDMA_RCR_TO_DEFAULT); 53344045d941Ssowmini goto done; 53354045d941Ssowmini } 53364045d941Ssowmini 53374045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%d", 53384045d941Ssowmini nxgep->intr_timeout); 53391bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 53401bd6825cSml "==> nxge_get_priv_prop: name %s (value %d)", 53411bd6825cSml pr_name, 53421bd6825cSml (uint32_t)nxgep->intr_timeout)); 53431bd6825cSml goto done; 53441bd6825cSml } 53451bd6825cSml 53461bd6825cSml if (strcmp(pr_name, "_rxdma_intr_pkts") == 0) { 53474045d941Ssowmini err = 0; 53484045d941Ssowmini if (is_default) { 53494045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), 53504045d941Ssowmini "%d", RXDMA_RCR_PTHRES_DEFAULT); 53514045d941Ssowmini goto done; 53524045d941Ssowmini } 53534045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%d", 53544045d941Ssowmini nxgep->intr_threshold); 53551bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 53561bd6825cSml "==> nxge_get_priv_prop: name %s (value %d)", 53571bd6825cSml pr_name, (uint32_t)nxgep->intr_threshold)); 53581bd6825cSml 53591bd6825cSml goto done; 53601bd6825cSml } 53611bd6825cSml 53621bd6825cSml /* Classification and Load Distribution Configuration */ 53631bd6825cSml if (strcmp(pr_name, "_class_opt_ipv4_tcp") == 0) { 53644045d941Ssowmini if (is_default) { 53654045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 53664045d941Ssowmini NXGE_CLASS_FLOW_GEN_SERVER); 53674045d941Ssowmini err = 0; 53684045d941Ssowmini goto done; 53694045d941Ssowmini } 53701bd6825cSml err = nxge_dld_get_ip_opt(nxgep, 53711bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv4_tcp]); 53721bd6825cSml 53734045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 53741bd6825cSml (int)param_arr[param_class_opt_ipv4_tcp].value); 53751bd6825cSml 53761bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 53771bd6825cSml "==> nxge_get_priv_prop: %s", valstr)); 53781bd6825cSml goto done; 53791bd6825cSml } 53801bd6825cSml 53811bd6825cSml if (strcmp(pr_name, "_class_opt_ipv4_udp") == 0) { 53824045d941Ssowmini if (is_default) { 53834045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 53844045d941Ssowmini NXGE_CLASS_FLOW_GEN_SERVER); 53854045d941Ssowmini err = 0; 53864045d941Ssowmini goto done; 53874045d941Ssowmini } 53881bd6825cSml err = nxge_dld_get_ip_opt(nxgep, 53891bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv4_udp]); 53901bd6825cSml 53914045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 53921bd6825cSml (int)param_arr[param_class_opt_ipv4_udp].value); 53931bd6825cSml 53941bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 53951bd6825cSml "==> nxge_get_priv_prop: %s", valstr)); 53961bd6825cSml goto done; 53971bd6825cSml } 53981bd6825cSml if (strcmp(pr_name, "_class_opt_ipv4_ah") == 0) { 53994045d941Ssowmini if (is_default) { 54004045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 54014045d941Ssowmini NXGE_CLASS_FLOW_GEN_SERVER); 54024045d941Ssowmini err = 0; 54034045d941Ssowmini goto done; 54044045d941Ssowmini } 54051bd6825cSml err = nxge_dld_get_ip_opt(nxgep, 54061bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv4_ah]); 54071bd6825cSml 54084045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 54091bd6825cSml (int)param_arr[param_class_opt_ipv4_ah].value); 54101bd6825cSml 54111bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 54121bd6825cSml "==> nxge_get_priv_prop: %s", valstr)); 54131bd6825cSml goto done; 54141bd6825cSml } 54151bd6825cSml 54161bd6825cSml if (strcmp(pr_name, "_class_opt_ipv4_sctp") == 0) { 54174045d941Ssowmini if (is_default) { 54184045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 54194045d941Ssowmini NXGE_CLASS_FLOW_GEN_SERVER); 54204045d941Ssowmini err = 0; 54214045d941Ssowmini goto done; 54224045d941Ssowmini } 54231bd6825cSml err = nxge_dld_get_ip_opt(nxgep, 54241bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv4_sctp]); 54251bd6825cSml 54264045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 54271bd6825cSml (int)param_arr[param_class_opt_ipv4_sctp].value); 54281bd6825cSml 54291bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 54301bd6825cSml "==> nxge_get_priv_prop: %s", valstr)); 54311bd6825cSml goto done; 54321bd6825cSml } 54331bd6825cSml 54341bd6825cSml if (strcmp(pr_name, "_class_opt_ipv6_tcp") == 0) { 54354045d941Ssowmini if (is_default) { 54364045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 54374045d941Ssowmini NXGE_CLASS_FLOW_GEN_SERVER); 54384045d941Ssowmini err = 0; 54394045d941Ssowmini goto done; 54404045d941Ssowmini } 54411bd6825cSml err = nxge_dld_get_ip_opt(nxgep, 54421bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv6_tcp]); 54431bd6825cSml 54444045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 54451bd6825cSml (int)param_arr[param_class_opt_ipv6_tcp].value); 54461bd6825cSml 54471bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 54481bd6825cSml "==> nxge_get_priv_prop: %s", valstr)); 54491bd6825cSml goto done; 54501bd6825cSml } 54511bd6825cSml 54521bd6825cSml if (strcmp(pr_name, "_class_opt_ipv6_udp") == 0) { 54534045d941Ssowmini if (is_default) { 54544045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 54554045d941Ssowmini NXGE_CLASS_FLOW_GEN_SERVER); 54564045d941Ssowmini err = 0; 54574045d941Ssowmini goto done; 54584045d941Ssowmini } 54591bd6825cSml err = nxge_dld_get_ip_opt(nxgep, 54601bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv6_udp]); 54611bd6825cSml 54624045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 54631bd6825cSml (int)param_arr[param_class_opt_ipv6_udp].value); 54641bd6825cSml 54651bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 54661bd6825cSml "==> nxge_get_priv_prop: %s", valstr)); 54671bd6825cSml goto done; 54681bd6825cSml } 54691bd6825cSml 54701bd6825cSml if (strcmp(pr_name, "_class_opt_ipv6_ah") == 0) { 54714045d941Ssowmini if (is_default) { 54724045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 54734045d941Ssowmini NXGE_CLASS_FLOW_GEN_SERVER); 54744045d941Ssowmini err = 0; 54754045d941Ssowmini goto done; 54764045d941Ssowmini } 54771bd6825cSml err = nxge_dld_get_ip_opt(nxgep, 54781bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv6_ah]); 54791bd6825cSml 54804045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 54811bd6825cSml (int)param_arr[param_class_opt_ipv6_ah].value); 54821bd6825cSml 54831bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 54841bd6825cSml "==> nxge_get_priv_prop: %s", valstr)); 54851bd6825cSml goto done; 54861bd6825cSml } 54871bd6825cSml 54881bd6825cSml if (strcmp(pr_name, "_class_opt_ipv6_sctp") == 0) { 54894045d941Ssowmini if (is_default) { 54904045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 54914045d941Ssowmini NXGE_CLASS_FLOW_GEN_SERVER); 54924045d941Ssowmini err = 0; 54934045d941Ssowmini goto done; 54944045d941Ssowmini } 54951bd6825cSml err = nxge_dld_get_ip_opt(nxgep, 54961bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv6_sctp]); 54971bd6825cSml 54984045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 54991bd6825cSml (int)param_arr[param_class_opt_ipv6_sctp].value); 55001bd6825cSml 55011bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 55021bd6825cSml "==> nxge_get_priv_prop: %s", valstr)); 55031bd6825cSml goto done; 55041bd6825cSml } 55051bd6825cSml 55061bd6825cSml /* Software LSO */ 55071bd6825cSml if (strcmp(pr_name, "_soft_lso_enable") == 0) { 55084045d941Ssowmini if (is_default) { 55094045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%d", 0); 55104045d941Ssowmini err = 0; 55114045d941Ssowmini goto done; 55124045d941Ssowmini } 55134045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), 55144045d941Ssowmini "%d", nxgep->soft_lso_enable); 55151bd6825cSml err = 0; 55161bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 55171bd6825cSml "==> nxge_get_priv_prop: name %s (value %d)", 55181bd6825cSml pr_name, nxgep->soft_lso_enable)); 55191bd6825cSml 55201bd6825cSml goto done; 55211bd6825cSml } 55224045d941Ssowmini if (strcmp(pr_name, "_adv_10gfdx_cap") == 0) { 55234045d941Ssowmini err = 0; 55244045d941Ssowmini if (is_default || 55254045d941Ssowmini nxgep->param_arr[param_anar_10gfdx].value != 0) { 55264045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%d", 1); 55274045d941Ssowmini goto done; 55284045d941Ssowmini } else { 55294045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%d", 0); 55304045d941Ssowmini goto done; 55314045d941Ssowmini } 55324045d941Ssowmini } 55334045d941Ssowmini if (strcmp(pr_name, "_adv_pause_cap") == 0) { 55344045d941Ssowmini err = 0; 55354045d941Ssowmini if (is_default || 55364045d941Ssowmini nxgep->param_arr[param_anar_pause].value != 0) { 55374045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%d", 1); 55384045d941Ssowmini goto done; 55394045d941Ssowmini } else { 55404045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%d", 0); 55414045d941Ssowmini goto done; 55424045d941Ssowmini } 55434045d941Ssowmini } 55441bd6825cSml 55451bd6825cSml done: 55461bd6825cSml if (err == 0) { 55471bd6825cSml strsize = (uint_t)strlen(valstr); 55481bd6825cSml if (pr_valsize < strsize) { 55491bd6825cSml err = ENOBUFS; 55501bd6825cSml } else { 55511bd6825cSml (void) strlcpy(pr_val, valstr, pr_valsize); 55521bd6825cSml } 55531bd6825cSml } 55541bd6825cSml 55551bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 55561bd6825cSml "<== nxge_get_priv_prop: return %d", err)); 55571bd6825cSml return (err); 55581bd6825cSml } 55591bd6825cSml 556044961713Sgirish /* 556144961713Sgirish * Module loading and removing entry points. 556244961713Sgirish */ 556344961713Sgirish 55646f157acbSml DDI_DEFINE_STREAM_OPS(nxge_dev_ops, nulldev, nulldev, nxge_attach, nxge_detach, 55656f157acbSml nodev, NULL, D_MP, NULL); 556644961713Sgirish 55672e59129aSraghus #define NXGE_DESC_VER "Sun NIU 10Gb Ethernet" 556844961713Sgirish 556944961713Sgirish /* 557044961713Sgirish * Module linkage information for the kernel. 557144961713Sgirish */ 557244961713Sgirish static struct modldrv nxge_modldrv = { 557344961713Sgirish &mod_driverops, 557444961713Sgirish NXGE_DESC_VER, 557544961713Sgirish &nxge_dev_ops 557644961713Sgirish }; 557744961713Sgirish 557844961713Sgirish static struct modlinkage modlinkage = { 557944961713Sgirish MODREV_1, (void *) &nxge_modldrv, NULL 558044961713Sgirish }; 558144961713Sgirish 558244961713Sgirish int 558344961713Sgirish _init(void) 558444961713Sgirish { 558544961713Sgirish int status; 558644961713Sgirish 558744961713Sgirish NXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _init")); 558844961713Sgirish mac_init_ops(&nxge_dev_ops, "nxge"); 558944961713Sgirish status = ddi_soft_state_init(&nxge_list, sizeof (nxge_t), 0); 559044961713Sgirish if (status != 0) { 559144961713Sgirish NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 55924045d941Ssowmini "failed to init device soft state")); 559344961713Sgirish goto _init_exit; 559444961713Sgirish } 559544961713Sgirish status = mod_install(&modlinkage); 559644961713Sgirish if (status != 0) { 559744961713Sgirish ddi_soft_state_fini(&nxge_list); 559844961713Sgirish NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, "Mod install failed")); 559944961713Sgirish goto _init_exit; 560044961713Sgirish } 560144961713Sgirish 560244961713Sgirish MUTEX_INIT(&nxge_common_lock, NULL, MUTEX_DRIVER, NULL); 560344961713Sgirish 560444961713Sgirish _init_exit: 560544961713Sgirish NXGE_DEBUG_MSG((NULL, MOD_CTL, "_init status = 0x%X", status)); 560644961713Sgirish 560744961713Sgirish return (status); 560844961713Sgirish } 560944961713Sgirish 561044961713Sgirish int 561144961713Sgirish _fini(void) 561244961713Sgirish { 561344961713Sgirish int status; 561444961713Sgirish 561544961713Sgirish NXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _fini")); 561644961713Sgirish 561744961713Sgirish NXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _fini: mod_remove")); 5618a3c5bd6dSspeer 5619a3c5bd6dSspeer if (nxge_mblks_pending) 5620a3c5bd6dSspeer return (EBUSY); 5621a3c5bd6dSspeer 562244961713Sgirish status = mod_remove(&modlinkage); 562344961713Sgirish if (status != DDI_SUCCESS) { 562444961713Sgirish NXGE_DEBUG_MSG((NULL, MOD_CTL, 56254045d941Ssowmini "Module removal failed 0x%08x", 56264045d941Ssowmini status)); 562744961713Sgirish goto _fini_exit; 562844961713Sgirish } 562944961713Sgirish 563044961713Sgirish mac_fini_ops(&nxge_dev_ops); 563144961713Sgirish 563244961713Sgirish ddi_soft_state_fini(&nxge_list); 563344961713Sgirish 563444961713Sgirish MUTEX_DESTROY(&nxge_common_lock); 563544961713Sgirish _fini_exit: 563644961713Sgirish NXGE_DEBUG_MSG((NULL, MOD_CTL, "_fini status = 0x%08x", status)); 563744961713Sgirish 563844961713Sgirish return (status); 563944961713Sgirish } 564044961713Sgirish 564144961713Sgirish int 564244961713Sgirish _info(struct modinfo *modinfop) 564344961713Sgirish { 564444961713Sgirish int status; 564544961713Sgirish 564644961713Sgirish NXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _info")); 564744961713Sgirish status = mod_info(&modlinkage, modinfop); 564844961713Sgirish NXGE_DEBUG_MSG((NULL, MOD_CTL, " _info status = 0x%X", status)); 564944961713Sgirish 565044961713Sgirish return (status); 565144961713Sgirish } 565244961713Sgirish 565344961713Sgirish /*ARGSUSED*/ 565444961713Sgirish static nxge_status_t 565544961713Sgirish nxge_add_intrs(p_nxge_t nxgep) 565644961713Sgirish { 565744961713Sgirish 565844961713Sgirish int intr_types; 565944961713Sgirish int type = 0; 566044961713Sgirish int ddi_status = DDI_SUCCESS; 566144961713Sgirish nxge_status_t status = NXGE_OK; 566244961713Sgirish 566344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs")); 566444961713Sgirish 566544961713Sgirish nxgep->nxge_intr_type.intr_registered = B_FALSE; 566644961713Sgirish nxgep->nxge_intr_type.intr_enabled = B_FALSE; 566744961713Sgirish nxgep->nxge_intr_type.msi_intx_cnt = 0; 566844961713Sgirish nxgep->nxge_intr_type.intr_added = 0; 566944961713Sgirish nxgep->nxge_intr_type.niu_msi_enable = B_FALSE; 567044961713Sgirish nxgep->nxge_intr_type.intr_type = 0; 567144961713Sgirish 567244961713Sgirish if (nxgep->niu_type == N2_NIU) { 567344961713Sgirish nxgep->nxge_intr_type.niu_msi_enable = B_TRUE; 567444961713Sgirish } else if (nxge_msi_enable) { 567544961713Sgirish nxgep->nxge_intr_type.niu_msi_enable = B_TRUE; 567644961713Sgirish } 567744961713Sgirish 567844961713Sgirish /* Get the supported interrupt types */ 567944961713Sgirish if ((ddi_status = ddi_intr_get_supported_types(nxgep->dip, &intr_types)) 56804045d941Ssowmini != DDI_SUCCESS) { 568144961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_add_intrs: " 56824045d941Ssowmini "ddi_intr_get_supported_types failed: status 0x%08x", 56834045d941Ssowmini ddi_status)); 568444961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 568544961713Sgirish } 568644961713Sgirish nxgep->nxge_intr_type.intr_types = intr_types; 568744961713Sgirish 568844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 56894045d941Ssowmini "ddi_intr_get_supported_types: 0x%08x", intr_types)); 569044961713Sgirish 569144961713Sgirish /* 569244961713Sgirish * Solaris MSIX is not supported yet. use MSI for now. 569344961713Sgirish * nxge_msi_enable (1): 569444961713Sgirish * 1 - MSI 2 - MSI-X others - FIXED 569544961713Sgirish */ 569644961713Sgirish switch (nxge_msi_enable) { 569744961713Sgirish default: 569844961713Sgirish type = DDI_INTR_TYPE_FIXED; 569944961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: " 57004045d941Ssowmini "use fixed (intx emulation) type %08x", 57014045d941Ssowmini type)); 570244961713Sgirish break; 570344961713Sgirish 570444961713Sgirish case 2: 570544961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: " 57064045d941Ssowmini "ddi_intr_get_supported_types: 0x%08x", intr_types)); 570744961713Sgirish if (intr_types & DDI_INTR_TYPE_MSIX) { 570844961713Sgirish type = DDI_INTR_TYPE_MSIX; 570944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 57104045d941Ssowmini "ddi_intr_get_supported_types: MSIX 0x%08x", 57114045d941Ssowmini type)); 571244961713Sgirish } else if (intr_types & DDI_INTR_TYPE_MSI) { 571344961713Sgirish type = DDI_INTR_TYPE_MSI; 571444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 57154045d941Ssowmini "ddi_intr_get_supported_types: MSI 0x%08x", 57164045d941Ssowmini type)); 571744961713Sgirish } else if (intr_types & DDI_INTR_TYPE_FIXED) { 571844961713Sgirish type = DDI_INTR_TYPE_FIXED; 571944961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: " 57204045d941Ssowmini "ddi_intr_get_supported_types: MSXED0x%08x", 57214045d941Ssowmini type)); 572244961713Sgirish } 572344961713Sgirish break; 572444961713Sgirish 572544961713Sgirish case 1: 572644961713Sgirish if (intr_types & DDI_INTR_TYPE_MSI) { 572744961713Sgirish type = DDI_INTR_TYPE_MSI; 572844961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: " 57294045d941Ssowmini "ddi_intr_get_supported_types: MSI 0x%08x", 57304045d941Ssowmini type)); 573144961713Sgirish } else if (intr_types & DDI_INTR_TYPE_MSIX) { 573244961713Sgirish type = DDI_INTR_TYPE_MSIX; 573344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 57344045d941Ssowmini "ddi_intr_get_supported_types: MSIX 0x%08x", 57354045d941Ssowmini type)); 573644961713Sgirish } else if (intr_types & DDI_INTR_TYPE_FIXED) { 573744961713Sgirish type = DDI_INTR_TYPE_FIXED; 573844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 57394045d941Ssowmini "ddi_intr_get_supported_types: MSXED0x%08x", 57404045d941Ssowmini type)); 574144961713Sgirish } 574244961713Sgirish } 574344961713Sgirish 574444961713Sgirish nxgep->nxge_intr_type.intr_type = type; 574544961713Sgirish if ((type == DDI_INTR_TYPE_MSIX || type == DDI_INTR_TYPE_MSI || 57464045d941Ssowmini type == DDI_INTR_TYPE_FIXED) && 57474045d941Ssowmini nxgep->nxge_intr_type.niu_msi_enable) { 574844961713Sgirish if ((status = nxge_add_intrs_adv(nxgep)) != DDI_SUCCESS) { 574944961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 57504045d941Ssowmini " nxge_add_intrs: " 57514045d941Ssowmini " nxge_add_intrs_adv failed: status 0x%08x", 57524045d941Ssowmini status)); 575344961713Sgirish return (status); 575444961713Sgirish } else { 575544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 57564045d941Ssowmini "interrupts registered : type %d", type)); 575744961713Sgirish nxgep->nxge_intr_type.intr_registered = B_TRUE; 575844961713Sgirish 575944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 57604045d941Ssowmini "\nAdded advanced nxge add_intr_adv " 57614045d941Ssowmini "intr type 0x%x\n", type)); 576244961713Sgirish 576344961713Sgirish return (status); 576444961713Sgirish } 576544961713Sgirish } 576644961713Sgirish 576744961713Sgirish if (!nxgep->nxge_intr_type.intr_registered) { 576844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "==> nxge_add_intrs: " 57694045d941Ssowmini "failed to register interrupts")); 577044961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 577144961713Sgirish } 577244961713Sgirish 577344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_add_intrs")); 577444961713Sgirish return (status); 577544961713Sgirish } 577644961713Sgirish 577744961713Sgirish /*ARGSUSED*/ 577844961713Sgirish static nxge_status_t 577944961713Sgirish nxge_add_soft_intrs(p_nxge_t nxgep) 578044961713Sgirish { 578144961713Sgirish 578244961713Sgirish int ddi_status = DDI_SUCCESS; 578344961713Sgirish nxge_status_t status = NXGE_OK; 578444961713Sgirish 578544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_soft_intrs")); 578644961713Sgirish 578744961713Sgirish nxgep->resched_id = NULL; 578844961713Sgirish nxgep->resched_running = B_FALSE; 578944961713Sgirish ddi_status = ddi_add_softintr(nxgep->dip, DDI_SOFTINT_LOW, 57904045d941Ssowmini &nxgep->resched_id, 57914045d941Ssowmini NULL, NULL, nxge_reschedule, (caddr_t)nxgep); 579244961713Sgirish if (ddi_status != DDI_SUCCESS) { 579344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_add_soft_intrs: " 57944045d941Ssowmini "ddi_add_softintrs failed: status 0x%08x", 57954045d941Ssowmini ddi_status)); 579644961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 579744961713Sgirish } 579844961713Sgirish 579944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_ddi_add_soft_intrs")); 580044961713Sgirish 580144961713Sgirish return (status); 580244961713Sgirish } 580344961713Sgirish 580444961713Sgirish static nxge_status_t 580544961713Sgirish nxge_add_intrs_adv(p_nxge_t nxgep) 580644961713Sgirish { 580744961713Sgirish int intr_type; 580844961713Sgirish p_nxge_intr_t intrp; 580944961713Sgirish 581044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs_adv")); 581144961713Sgirish 581244961713Sgirish intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 581344961713Sgirish intr_type = intrp->intr_type; 581444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs_adv: type 0x%x", 58154045d941Ssowmini intr_type)); 581644961713Sgirish 581744961713Sgirish switch (intr_type) { 581844961713Sgirish case DDI_INTR_TYPE_MSI: /* 0x2 */ 581944961713Sgirish case DDI_INTR_TYPE_MSIX: /* 0x4 */ 582044961713Sgirish return (nxge_add_intrs_adv_type(nxgep, intr_type)); 582144961713Sgirish 582244961713Sgirish case DDI_INTR_TYPE_FIXED: /* 0x1 */ 582344961713Sgirish return (nxge_add_intrs_adv_type_fix(nxgep, intr_type)); 582444961713Sgirish 582544961713Sgirish default: 582644961713Sgirish return (NXGE_ERROR); 582744961713Sgirish } 582844961713Sgirish } 582944961713Sgirish 583044961713Sgirish 583144961713Sgirish /*ARGSUSED*/ 583244961713Sgirish static nxge_status_t 583344961713Sgirish nxge_add_intrs_adv_type(p_nxge_t nxgep, uint32_t int_type) 583444961713Sgirish { 583544961713Sgirish dev_info_t *dip = nxgep->dip; 583644961713Sgirish p_nxge_ldg_t ldgp; 583744961713Sgirish p_nxge_intr_t intrp; 583844961713Sgirish uint_t *inthandler; 583944961713Sgirish void *arg1, *arg2; 584044961713Sgirish int behavior; 5841ec090658Sml int nintrs, navail, nrequest; 584244961713Sgirish int nactual, nrequired; 584344961713Sgirish int inum = 0; 584444961713Sgirish int x, y; 584544961713Sgirish int ddi_status = DDI_SUCCESS; 584644961713Sgirish nxge_status_t status = NXGE_OK; 584744961713Sgirish 584844961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs_adv_type")); 584944961713Sgirish intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 585044961713Sgirish intrp->start_inum = 0; 585144961713Sgirish 585244961713Sgirish ddi_status = ddi_intr_get_nintrs(dip, int_type, &nintrs); 585344961713Sgirish if ((ddi_status != DDI_SUCCESS) || (nintrs == 0)) { 585444961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 58554045d941Ssowmini "ddi_intr_get_nintrs() failed, status: 0x%x%, " 58564045d941Ssowmini "nintrs: %d", ddi_status, nintrs)); 585744961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 585844961713Sgirish } 585944961713Sgirish 586044961713Sgirish ddi_status = ddi_intr_get_navail(dip, int_type, &navail); 586144961713Sgirish if ((ddi_status != DDI_SUCCESS) || (navail == 0)) { 586244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 58634045d941Ssowmini "ddi_intr_get_navail() failed, status: 0x%x%, " 58644045d941Ssowmini "nintrs: %d", ddi_status, navail)); 586544961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 586644961713Sgirish } 586744961713Sgirish 586844961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 58694045d941Ssowmini "ddi_intr_get_navail() returned: nintrs %d, navail %d", 58704045d941Ssowmini nintrs, navail)); 587144961713Sgirish 5872ec090658Sml /* PSARC/2007/453 MSI-X interrupt limit override */ 5873ec090658Sml if (int_type == DDI_INTR_TYPE_MSIX) { 5874ec090658Sml nrequest = nxge_create_msi_property(nxgep); 5875ec090658Sml if (nrequest < navail) { 5876ec090658Sml navail = nrequest; 5877ec090658Sml NXGE_DEBUG_MSG((nxgep, INT_CTL, 5878ec090658Sml "nxge_add_intrs_adv_type: nintrs %d " 5879ec090658Sml "navail %d (nrequest %d)", 5880ec090658Sml nintrs, navail, nrequest)); 5881ec090658Sml } 5882ec090658Sml } 5883ec090658Sml 588444961713Sgirish if (int_type == DDI_INTR_TYPE_MSI && !ISP2(navail)) { 588544961713Sgirish /* MSI must be power of 2 */ 588644961713Sgirish if ((navail & 16) == 16) { 588744961713Sgirish navail = 16; 588844961713Sgirish } else if ((navail & 8) == 8) { 588944961713Sgirish navail = 8; 589044961713Sgirish } else if ((navail & 4) == 4) { 589144961713Sgirish navail = 4; 589244961713Sgirish } else if ((navail & 2) == 2) { 589344961713Sgirish navail = 2; 589444961713Sgirish } else { 589544961713Sgirish navail = 1; 589644961713Sgirish } 589744961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 58984045d941Ssowmini "ddi_intr_get_navail(): (msi power of 2) nintrs %d, " 58994045d941Ssowmini "navail %d", nintrs, navail)); 590044961713Sgirish } 590144961713Sgirish 590244961713Sgirish behavior = ((int_type == DDI_INTR_TYPE_FIXED) ? DDI_INTR_ALLOC_STRICT : 59034045d941Ssowmini DDI_INTR_ALLOC_NORMAL); 590444961713Sgirish intrp->intr_size = navail * sizeof (ddi_intr_handle_t); 590544961713Sgirish intrp->htable = kmem_alloc(intrp->intr_size, KM_SLEEP); 590644961713Sgirish ddi_status = ddi_intr_alloc(dip, intrp->htable, int_type, inum, 59074045d941Ssowmini navail, &nactual, behavior); 590844961713Sgirish if (ddi_status != DDI_SUCCESS || nactual == 0) { 590944961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 59104045d941Ssowmini " ddi_intr_alloc() failed: %d", 59114045d941Ssowmini ddi_status)); 591244961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 591344961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 591444961713Sgirish } 591544961713Sgirish 591644961713Sgirish if ((ddi_status = ddi_intr_get_pri(intrp->htable[0], 59174045d941Ssowmini (uint_t *)&intrp->pri)) != DDI_SUCCESS) { 591844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 59194045d941Ssowmini " ddi_intr_get_pri() failed: %d", 59204045d941Ssowmini ddi_status)); 592144961713Sgirish /* Free already allocated interrupts */ 592244961713Sgirish for (y = 0; y < nactual; y++) { 592344961713Sgirish (void) ddi_intr_free(intrp->htable[y]); 592444961713Sgirish } 592544961713Sgirish 592644961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 592744961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 592844961713Sgirish } 592944961713Sgirish 593044961713Sgirish nrequired = 0; 593144961713Sgirish switch (nxgep->niu_type) { 593244961713Sgirish default: 593344961713Sgirish status = nxge_ldgv_init(nxgep, &nactual, &nrequired); 593444961713Sgirish break; 593544961713Sgirish 593644961713Sgirish case N2_NIU: 593744961713Sgirish status = nxge_ldgv_init_n2(nxgep, &nactual, &nrequired); 593844961713Sgirish break; 593944961713Sgirish } 594044961713Sgirish 594144961713Sgirish if (status != NXGE_OK) { 594244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 59434045d941Ssowmini "nxge_add_intrs_adv_typ:nxge_ldgv_init " 59444045d941Ssowmini "failed: 0x%x", status)); 594544961713Sgirish /* Free already allocated interrupts */ 594644961713Sgirish for (y = 0; y < nactual; y++) { 594744961713Sgirish (void) ddi_intr_free(intrp->htable[y]); 594844961713Sgirish } 594944961713Sgirish 595044961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 595144961713Sgirish return (status); 595244961713Sgirish } 595344961713Sgirish 595444961713Sgirish ldgp = nxgep->ldgvp->ldgp; 595544961713Sgirish for (x = 0; x < nrequired; x++, ldgp++) { 595644961713Sgirish ldgp->vector = (uint8_t)x; 595744961713Sgirish ldgp->intdata = SID_DATA(ldgp->func, x); 595844961713Sgirish arg1 = ldgp->ldvp; 595944961713Sgirish arg2 = nxgep; 596044961713Sgirish if (ldgp->nldvs == 1) { 596144961713Sgirish inthandler = (uint_t *)ldgp->ldvp->ldv_intr_handler; 596244961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 59634045d941Ssowmini "nxge_add_intrs_adv_type: " 59644045d941Ssowmini "arg1 0x%x arg2 0x%x: " 59654045d941Ssowmini "1-1 int handler (entry %d intdata 0x%x)\n", 59664045d941Ssowmini arg1, arg2, 59674045d941Ssowmini x, ldgp->intdata)); 596844961713Sgirish } else if (ldgp->nldvs > 1) { 596944961713Sgirish inthandler = (uint_t *)ldgp->sys_intr_handler; 597044961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 59714045d941Ssowmini "nxge_add_intrs_adv_type: " 59724045d941Ssowmini "arg1 0x%x arg2 0x%x: " 59734045d941Ssowmini "nldevs %d int handler " 59744045d941Ssowmini "(entry %d intdata 0x%x)\n", 59754045d941Ssowmini arg1, arg2, 59764045d941Ssowmini ldgp->nldvs, x, ldgp->intdata)); 597744961713Sgirish } 597844961713Sgirish 597944961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 59804045d941Ssowmini "==> nxge_add_intrs_adv_type: ddi_add_intr(inum) #%d " 59814045d941Ssowmini "htable 0x%llx", x, intrp->htable[x])); 598244961713Sgirish 598344961713Sgirish if ((ddi_status = ddi_intr_add_handler(intrp->htable[x], 59844045d941Ssowmini (ddi_intr_handler_t *)inthandler, arg1, arg2)) 59854045d941Ssowmini != DDI_SUCCESS) { 598644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 59874045d941Ssowmini "==> nxge_add_intrs_adv_type: failed #%d " 59884045d941Ssowmini "status 0x%x", x, ddi_status)); 598944961713Sgirish for (y = 0; y < intrp->intr_added; y++) { 599044961713Sgirish (void) ddi_intr_remove_handler( 59914045d941Ssowmini intrp->htable[y]); 599244961713Sgirish } 599344961713Sgirish /* Free already allocated intr */ 599444961713Sgirish for (y = 0; y < nactual; y++) { 599544961713Sgirish (void) ddi_intr_free(intrp->htable[y]); 599644961713Sgirish } 599744961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 599844961713Sgirish 599944961713Sgirish (void) nxge_ldgv_uninit(nxgep); 600044961713Sgirish 600144961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 600244961713Sgirish } 600344961713Sgirish intrp->intr_added++; 600444961713Sgirish } 600544961713Sgirish 600644961713Sgirish intrp->msi_intx_cnt = nactual; 600744961713Sgirish 600844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 60094045d941Ssowmini "Requested: %d, Allowed: %d msi_intx_cnt %d intr_added %d", 60104045d941Ssowmini navail, nactual, 60114045d941Ssowmini intrp->msi_intx_cnt, 60124045d941Ssowmini intrp->intr_added)); 601344961713Sgirish 601444961713Sgirish (void) ddi_intr_get_cap(intrp->htable[0], &intrp->intr_cap); 601544961713Sgirish 601644961713Sgirish (void) nxge_intr_ldgv_init(nxgep); 601744961713Sgirish 601844961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_add_intrs_adv_type")); 601944961713Sgirish 602044961713Sgirish return (status); 602144961713Sgirish } 602244961713Sgirish 602344961713Sgirish /*ARGSUSED*/ 602444961713Sgirish static nxge_status_t 602544961713Sgirish nxge_add_intrs_adv_type_fix(p_nxge_t nxgep, uint32_t int_type) 602644961713Sgirish { 602744961713Sgirish dev_info_t *dip = nxgep->dip; 602844961713Sgirish p_nxge_ldg_t ldgp; 602944961713Sgirish p_nxge_intr_t intrp; 603044961713Sgirish uint_t *inthandler; 603144961713Sgirish void *arg1, *arg2; 603244961713Sgirish int behavior; 603344961713Sgirish int nintrs, navail; 603444961713Sgirish int nactual, nrequired; 603544961713Sgirish int inum = 0; 603644961713Sgirish int x, y; 603744961713Sgirish int ddi_status = DDI_SUCCESS; 603844961713Sgirish nxge_status_t status = NXGE_OK; 603944961713Sgirish 604044961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs_adv_type_fix")); 604144961713Sgirish intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 604244961713Sgirish intrp->start_inum = 0; 604344961713Sgirish 604444961713Sgirish ddi_status = ddi_intr_get_nintrs(dip, int_type, &nintrs); 604544961713Sgirish if ((ddi_status != DDI_SUCCESS) || (nintrs == 0)) { 604644961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 60474045d941Ssowmini "ddi_intr_get_nintrs() failed, status: 0x%x%, " 60484045d941Ssowmini "nintrs: %d", status, nintrs)); 604944961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 605044961713Sgirish } 605144961713Sgirish 605244961713Sgirish ddi_status = ddi_intr_get_navail(dip, int_type, &navail); 605344961713Sgirish if ((ddi_status != DDI_SUCCESS) || (navail == 0)) { 605444961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 60554045d941Ssowmini "ddi_intr_get_navail() failed, status: 0x%x%, " 60564045d941Ssowmini "nintrs: %d", ddi_status, navail)); 605744961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 605844961713Sgirish } 605944961713Sgirish 606044961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 60614045d941Ssowmini "ddi_intr_get_navail() returned: nintrs %d, naavail %d", 60624045d941Ssowmini nintrs, navail)); 606344961713Sgirish 606444961713Sgirish behavior = ((int_type == DDI_INTR_TYPE_FIXED) ? DDI_INTR_ALLOC_STRICT : 60654045d941Ssowmini DDI_INTR_ALLOC_NORMAL); 606644961713Sgirish intrp->intr_size = navail * sizeof (ddi_intr_handle_t); 606744961713Sgirish intrp->htable = kmem_alloc(intrp->intr_size, KM_SLEEP); 606844961713Sgirish ddi_status = ddi_intr_alloc(dip, intrp->htable, int_type, inum, 60694045d941Ssowmini navail, &nactual, behavior); 607044961713Sgirish if (ddi_status != DDI_SUCCESS || nactual == 0) { 607144961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 60724045d941Ssowmini " ddi_intr_alloc() failed: %d", 60734045d941Ssowmini ddi_status)); 607444961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 607544961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 607644961713Sgirish } 607744961713Sgirish 607844961713Sgirish if ((ddi_status = ddi_intr_get_pri(intrp->htable[0], 60794045d941Ssowmini (uint_t *)&intrp->pri)) != DDI_SUCCESS) { 608044961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 60814045d941Ssowmini " ddi_intr_get_pri() failed: %d", 60824045d941Ssowmini ddi_status)); 608344961713Sgirish /* Free already allocated interrupts */ 608444961713Sgirish for (y = 0; y < nactual; y++) { 608544961713Sgirish (void) ddi_intr_free(intrp->htable[y]); 608644961713Sgirish } 608744961713Sgirish 608844961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 608944961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 609044961713Sgirish } 609144961713Sgirish 609244961713Sgirish nrequired = 0; 609344961713Sgirish switch (nxgep->niu_type) { 609444961713Sgirish default: 609544961713Sgirish status = nxge_ldgv_init(nxgep, &nactual, &nrequired); 609644961713Sgirish break; 609744961713Sgirish 609844961713Sgirish case N2_NIU: 609944961713Sgirish status = nxge_ldgv_init_n2(nxgep, &nactual, &nrequired); 610044961713Sgirish break; 610144961713Sgirish } 610244961713Sgirish 610344961713Sgirish if (status != NXGE_OK) { 610444961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 61054045d941Ssowmini "nxge_add_intrs_adv_type_fix:nxge_ldgv_init " 61064045d941Ssowmini "failed: 0x%x", status)); 610744961713Sgirish /* Free already allocated interrupts */ 610844961713Sgirish for (y = 0; y < nactual; y++) { 610944961713Sgirish (void) ddi_intr_free(intrp->htable[y]); 611044961713Sgirish } 611144961713Sgirish 611244961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 611344961713Sgirish return (status); 611444961713Sgirish } 611544961713Sgirish 611644961713Sgirish ldgp = nxgep->ldgvp->ldgp; 611744961713Sgirish for (x = 0; x < nrequired; x++, ldgp++) { 611844961713Sgirish ldgp->vector = (uint8_t)x; 611944961713Sgirish if (nxgep->niu_type != N2_NIU) { 612044961713Sgirish ldgp->intdata = SID_DATA(ldgp->func, x); 612144961713Sgirish } 612244961713Sgirish 612344961713Sgirish arg1 = ldgp->ldvp; 612444961713Sgirish arg2 = nxgep; 612544961713Sgirish if (ldgp->nldvs == 1) { 612644961713Sgirish inthandler = (uint_t *)ldgp->ldvp->ldv_intr_handler; 612744961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 61284045d941Ssowmini "nxge_add_intrs_adv_type_fix: " 61294045d941Ssowmini "1-1 int handler(%d) ldg %d ldv %d " 61304045d941Ssowmini "arg1 $%p arg2 $%p\n", 61314045d941Ssowmini x, ldgp->ldg, ldgp->ldvp->ldv, 61324045d941Ssowmini arg1, arg2)); 613344961713Sgirish } else if (ldgp->nldvs > 1) { 613444961713Sgirish inthandler = (uint_t *)ldgp->sys_intr_handler; 613544961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 61364045d941Ssowmini "nxge_add_intrs_adv_type_fix: " 61374045d941Ssowmini "shared ldv %d int handler(%d) ldv %d ldg %d" 61384045d941Ssowmini "arg1 0x%016llx arg2 0x%016llx\n", 61394045d941Ssowmini x, ldgp->nldvs, ldgp->ldg, ldgp->ldvp->ldv, 61404045d941Ssowmini arg1, arg2)); 614144961713Sgirish } 614244961713Sgirish 614344961713Sgirish if ((ddi_status = ddi_intr_add_handler(intrp->htable[x], 61444045d941Ssowmini (ddi_intr_handler_t *)inthandler, arg1, arg2)) 61454045d941Ssowmini != DDI_SUCCESS) { 614644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 61474045d941Ssowmini "==> nxge_add_intrs_adv_type_fix: failed #%d " 61484045d941Ssowmini "status 0x%x", x, ddi_status)); 614944961713Sgirish for (y = 0; y < intrp->intr_added; y++) { 615044961713Sgirish (void) ddi_intr_remove_handler( 61514045d941Ssowmini intrp->htable[y]); 615244961713Sgirish } 615344961713Sgirish for (y = 0; y < nactual; y++) { 615444961713Sgirish (void) ddi_intr_free(intrp->htable[y]); 615544961713Sgirish } 615644961713Sgirish /* Free already allocated intr */ 615744961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 615844961713Sgirish 615944961713Sgirish (void) nxge_ldgv_uninit(nxgep); 616044961713Sgirish 616144961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 616244961713Sgirish } 616344961713Sgirish intrp->intr_added++; 616444961713Sgirish } 616544961713Sgirish 616644961713Sgirish intrp->msi_intx_cnt = nactual; 616744961713Sgirish 616844961713Sgirish (void) ddi_intr_get_cap(intrp->htable[0], &intrp->intr_cap); 616944961713Sgirish 617044961713Sgirish status = nxge_intr_ldgv_init(nxgep); 617144961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_add_intrs_adv_type_fix")); 617244961713Sgirish 617344961713Sgirish return (status); 617444961713Sgirish } 617544961713Sgirish 617644961713Sgirish static void 617744961713Sgirish nxge_remove_intrs(p_nxge_t nxgep) 617844961713Sgirish { 617944961713Sgirish int i, inum; 618044961713Sgirish p_nxge_intr_t intrp; 618144961713Sgirish 618244961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_remove_intrs")); 618344961713Sgirish intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 618444961713Sgirish if (!intrp->intr_registered) { 618544961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 61864045d941Ssowmini "<== nxge_remove_intrs: interrupts not registered")); 618744961713Sgirish return; 618844961713Sgirish } 618944961713Sgirish 619044961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_remove_intrs:advanced")); 619144961713Sgirish 619244961713Sgirish if (intrp->intr_cap & DDI_INTR_FLAG_BLOCK) { 619344961713Sgirish (void) ddi_intr_block_disable(intrp->htable, 61944045d941Ssowmini intrp->intr_added); 619544961713Sgirish } else { 619644961713Sgirish for (i = 0; i < intrp->intr_added; i++) { 619744961713Sgirish (void) ddi_intr_disable(intrp->htable[i]); 619844961713Sgirish } 619944961713Sgirish } 620044961713Sgirish 620144961713Sgirish for (inum = 0; inum < intrp->intr_added; inum++) { 620244961713Sgirish if (intrp->htable[inum]) { 620344961713Sgirish (void) ddi_intr_remove_handler(intrp->htable[inum]); 620444961713Sgirish } 620544961713Sgirish } 620644961713Sgirish 620744961713Sgirish for (inum = 0; inum < intrp->msi_intx_cnt; inum++) { 620844961713Sgirish if (intrp->htable[inum]) { 620944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 62104045d941Ssowmini "nxge_remove_intrs: ddi_intr_free inum %d " 62114045d941Ssowmini "msi_intx_cnt %d intr_added %d", 62124045d941Ssowmini inum, 62134045d941Ssowmini intrp->msi_intx_cnt, 62144045d941Ssowmini intrp->intr_added)); 621544961713Sgirish 621644961713Sgirish (void) ddi_intr_free(intrp->htable[inum]); 621744961713Sgirish } 621844961713Sgirish } 621944961713Sgirish 622044961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 622144961713Sgirish intrp->intr_registered = B_FALSE; 622244961713Sgirish intrp->intr_enabled = B_FALSE; 622344961713Sgirish intrp->msi_intx_cnt = 0; 622444961713Sgirish intrp->intr_added = 0; 622544961713Sgirish 6226a3c5bd6dSspeer (void) nxge_ldgv_uninit(nxgep); 6227a3c5bd6dSspeer 6228ec090658Sml (void) ddi_prop_remove(DDI_DEV_T_NONE, nxgep->dip, 6229ec090658Sml "#msix-request"); 6230ec090658Sml 623144961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_remove_intrs")); 623244961713Sgirish } 623344961713Sgirish 623444961713Sgirish /*ARGSUSED*/ 623544961713Sgirish static void 623644961713Sgirish nxge_remove_soft_intrs(p_nxge_t nxgep) 623744961713Sgirish { 623844961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_remove_soft_intrs")); 623944961713Sgirish if (nxgep->resched_id) { 624044961713Sgirish ddi_remove_softintr(nxgep->resched_id); 624144961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 62424045d941Ssowmini "==> nxge_remove_soft_intrs: removed")); 624344961713Sgirish nxgep->resched_id = NULL; 624444961713Sgirish } 624544961713Sgirish 624644961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_remove_soft_intrs")); 624744961713Sgirish } 624844961713Sgirish 624944961713Sgirish /*ARGSUSED*/ 625044961713Sgirish static void 625144961713Sgirish nxge_intrs_enable(p_nxge_t nxgep) 625244961713Sgirish { 625344961713Sgirish p_nxge_intr_t intrp; 625444961713Sgirish int i; 625544961713Sgirish int status; 625644961713Sgirish 625744961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_enable")); 625844961713Sgirish 625944961713Sgirish intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 626044961713Sgirish 626144961713Sgirish if (!intrp->intr_registered) { 626244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_intrs_enable: " 62634045d941Ssowmini "interrupts are not registered")); 626444961713Sgirish return; 626544961713Sgirish } 626644961713Sgirish 626744961713Sgirish if (intrp->intr_enabled) { 626844961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 62694045d941Ssowmini "<== nxge_intrs_enable: already enabled")); 627044961713Sgirish return; 627144961713Sgirish } 627244961713Sgirish 627344961713Sgirish if (intrp->intr_cap & DDI_INTR_FLAG_BLOCK) { 627444961713Sgirish status = ddi_intr_block_enable(intrp->htable, 62754045d941Ssowmini intrp->intr_added); 627644961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_enable " 62774045d941Ssowmini "block enable - status 0x%x total inums #%d\n", 62784045d941Ssowmini status, intrp->intr_added)); 627944961713Sgirish } else { 628044961713Sgirish for (i = 0; i < intrp->intr_added; i++) { 628144961713Sgirish status = ddi_intr_enable(intrp->htable[i]); 628244961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_enable " 62834045d941Ssowmini "ddi_intr_enable:enable - status 0x%x " 62844045d941Ssowmini "total inums %d enable inum #%d\n", 62854045d941Ssowmini status, intrp->intr_added, i)); 628644961713Sgirish if (status == DDI_SUCCESS) { 628744961713Sgirish intrp->intr_enabled = B_TRUE; 628844961713Sgirish } 628944961713Sgirish } 629044961713Sgirish } 629144961713Sgirish 629244961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intrs_enable")); 629344961713Sgirish } 629444961713Sgirish 629544961713Sgirish /*ARGSUSED*/ 629644961713Sgirish static void 629744961713Sgirish nxge_intrs_disable(p_nxge_t nxgep) 629844961713Sgirish { 629944961713Sgirish p_nxge_intr_t intrp; 630044961713Sgirish int i; 630144961713Sgirish 630244961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_disable")); 630344961713Sgirish 630444961713Sgirish intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 630544961713Sgirish 630644961713Sgirish if (!intrp->intr_registered) { 630744961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intrs_disable: " 63084045d941Ssowmini "interrupts are not registered")); 630944961713Sgirish return; 631044961713Sgirish } 631144961713Sgirish 631244961713Sgirish if (intrp->intr_cap & DDI_INTR_FLAG_BLOCK) { 631344961713Sgirish (void) ddi_intr_block_disable(intrp->htable, 63144045d941Ssowmini intrp->intr_added); 631544961713Sgirish } else { 631644961713Sgirish for (i = 0; i < intrp->intr_added; i++) { 631744961713Sgirish (void) ddi_intr_disable(intrp->htable[i]); 631844961713Sgirish } 631944961713Sgirish } 632044961713Sgirish 632144961713Sgirish intrp->intr_enabled = B_FALSE; 632244961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intrs_disable")); 632344961713Sgirish } 632444961713Sgirish 632544961713Sgirish static nxge_status_t 632644961713Sgirish nxge_mac_register(p_nxge_t nxgep) 632744961713Sgirish { 632844961713Sgirish mac_register_t *macp; 632944961713Sgirish int status; 633044961713Sgirish 633144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_mac_register")); 633244961713Sgirish 633344961713Sgirish if ((macp = mac_alloc(MAC_VERSION)) == NULL) 633444961713Sgirish return (NXGE_ERROR); 633544961713Sgirish 633644961713Sgirish macp->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 633744961713Sgirish macp->m_driver = nxgep; 633844961713Sgirish macp->m_dip = nxgep->dip; 633944961713Sgirish macp->m_src_addr = nxgep->ouraddr.ether_addr_octet; 634044961713Sgirish macp->m_callbacks = &nxge_m_callbacks; 634144961713Sgirish macp->m_min_sdu = 0; 63421bd6825cSml nxgep->mac.default_mtu = nxgep->mac.maxframesize - 63431bd6825cSml NXGE_EHEADER_VLAN_CRC; 63441bd6825cSml macp->m_max_sdu = nxgep->mac.default_mtu; 6345d62bc4baSyz macp->m_margin = VLAN_TAGSZ; 63464045d941Ssowmini macp->m_priv_props = nxge_priv_props; 63474045d941Ssowmini macp->m_priv_prop_count = NXGE_MAX_PRIV_PROPS; 634844961713Sgirish 63491bd6825cSml NXGE_DEBUG_MSG((nxgep, MAC_CTL, 63501bd6825cSml "==> nxge_mac_register: instance %d " 63511bd6825cSml "max_sdu %d margin %d maxframe %d (header %d)", 63521bd6825cSml nxgep->instance, 63531bd6825cSml macp->m_max_sdu, macp->m_margin, 63541bd6825cSml nxgep->mac.maxframesize, 63551bd6825cSml NXGE_EHEADER_VLAN_CRC)); 63561bd6825cSml 635744961713Sgirish status = mac_register(macp, &nxgep->mach); 635844961713Sgirish mac_free(macp); 635944961713Sgirish 636044961713Sgirish if (status != 0) { 636144961713Sgirish cmn_err(CE_WARN, 63624045d941Ssowmini "!nxge_mac_register failed (status %d instance %d)", 63634045d941Ssowmini status, nxgep->instance); 636444961713Sgirish return (NXGE_ERROR); 636544961713Sgirish } 636644961713Sgirish 636744961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_mac_register success " 63684045d941Ssowmini "(instance %d)", nxgep->instance)); 636944961713Sgirish 637044961713Sgirish return (NXGE_OK); 637144961713Sgirish } 637244961713Sgirish 637344961713Sgirish void 637444961713Sgirish nxge_err_inject(p_nxge_t nxgep, queue_t *wq, mblk_t *mp) 637544961713Sgirish { 637644961713Sgirish ssize_t size; 637744961713Sgirish mblk_t *nmp; 637844961713Sgirish uint8_t blk_id; 637944961713Sgirish uint8_t chan; 638044961713Sgirish uint32_t err_id; 638144961713Sgirish err_inject_t *eip; 638244961713Sgirish 638344961713Sgirish NXGE_DEBUG_MSG((nxgep, STR_CTL, "==> nxge_err_inject")); 638444961713Sgirish 638544961713Sgirish size = 1024; 638644961713Sgirish nmp = mp->b_cont; 638744961713Sgirish eip = (err_inject_t *)nmp->b_rptr; 638844961713Sgirish blk_id = eip->blk_id; 638944961713Sgirish err_id = eip->err_id; 639044961713Sgirish chan = eip->chan; 639144961713Sgirish cmn_err(CE_NOTE, "!blk_id = 0x%x\n", blk_id); 639244961713Sgirish cmn_err(CE_NOTE, "!err_id = 0x%x\n", err_id); 639344961713Sgirish cmn_err(CE_NOTE, "!chan = 0x%x\n", chan); 639444961713Sgirish switch (blk_id) { 639544961713Sgirish case MAC_BLK_ID: 639644961713Sgirish break; 639744961713Sgirish case TXMAC_BLK_ID: 639844961713Sgirish break; 639944961713Sgirish case RXMAC_BLK_ID: 640044961713Sgirish break; 640144961713Sgirish case MIF_BLK_ID: 640244961713Sgirish break; 640344961713Sgirish case IPP_BLK_ID: 640444961713Sgirish nxge_ipp_inject_err(nxgep, err_id); 640544961713Sgirish break; 640644961713Sgirish case TXC_BLK_ID: 640744961713Sgirish nxge_txc_inject_err(nxgep, err_id); 640844961713Sgirish break; 640944961713Sgirish case TXDMA_BLK_ID: 641044961713Sgirish nxge_txdma_inject_err(nxgep, err_id, chan); 641144961713Sgirish break; 641244961713Sgirish case RXDMA_BLK_ID: 641344961713Sgirish nxge_rxdma_inject_err(nxgep, err_id, chan); 641444961713Sgirish break; 641544961713Sgirish case ZCP_BLK_ID: 641644961713Sgirish nxge_zcp_inject_err(nxgep, err_id); 641744961713Sgirish break; 641844961713Sgirish case ESPC_BLK_ID: 641944961713Sgirish break; 642044961713Sgirish case FFLP_BLK_ID: 642144961713Sgirish break; 642244961713Sgirish case PHY_BLK_ID: 642344961713Sgirish break; 642444961713Sgirish case ETHER_SERDES_BLK_ID: 642544961713Sgirish break; 642644961713Sgirish case PCIE_SERDES_BLK_ID: 642744961713Sgirish break; 642844961713Sgirish case VIR_BLK_ID: 642944961713Sgirish break; 643044961713Sgirish } 643144961713Sgirish 643244961713Sgirish nmp->b_wptr = nmp->b_rptr + size; 643344961713Sgirish NXGE_DEBUG_MSG((nxgep, STR_CTL, "<== nxge_err_inject")); 643444961713Sgirish 643544961713Sgirish miocack(wq, mp, (int)size, 0); 643644961713Sgirish } 643744961713Sgirish 643844961713Sgirish static int 643944961713Sgirish nxge_init_common_dev(p_nxge_t nxgep) 644044961713Sgirish { 644144961713Sgirish p_nxge_hw_list_t hw_p; 644244961713Sgirish dev_info_t *p_dip; 644344961713Sgirish 644444961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, "==> nxge_init_common_device")); 644544961713Sgirish 644644961713Sgirish p_dip = nxgep->p_dip; 644744961713Sgirish MUTEX_ENTER(&nxge_common_lock); 644844961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 64494045d941Ssowmini "==> nxge_init_common_dev:func # %d", 64504045d941Ssowmini nxgep->function_num)); 645144961713Sgirish /* 645244961713Sgirish * Loop through existing per neptune hardware list. 645344961713Sgirish */ 645444961713Sgirish for (hw_p = nxge_hw_list; hw_p; hw_p = hw_p->next) { 645544961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 64564045d941Ssowmini "==> nxge_init_common_device:func # %d " 64574045d941Ssowmini "hw_p $%p parent dip $%p", 64584045d941Ssowmini nxgep->function_num, 64594045d941Ssowmini hw_p, 64604045d941Ssowmini p_dip)); 646144961713Sgirish if (hw_p->parent_devp == p_dip) { 646244961713Sgirish nxgep->nxge_hw_p = hw_p; 646344961713Sgirish hw_p->ndevs++; 646444961713Sgirish hw_p->nxge_p[nxgep->function_num] = nxgep; 646544961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 64664045d941Ssowmini "==> nxge_init_common_device:func # %d " 64674045d941Ssowmini "hw_p $%p parent dip $%p " 64684045d941Ssowmini "ndevs %d (found)", 64694045d941Ssowmini nxgep->function_num, 64704045d941Ssowmini hw_p, 64714045d941Ssowmini p_dip, 64724045d941Ssowmini hw_p->ndevs)); 647344961713Sgirish break; 647444961713Sgirish } 647544961713Sgirish } 647644961713Sgirish 647744961713Sgirish if (hw_p == NULL) { 647844961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 64794045d941Ssowmini "==> nxge_init_common_device:func # %d " 64804045d941Ssowmini "parent dip $%p (new)", 64814045d941Ssowmini nxgep->function_num, 64824045d941Ssowmini p_dip)); 648344961713Sgirish hw_p = kmem_zalloc(sizeof (nxge_hw_list_t), KM_SLEEP); 648444961713Sgirish hw_p->parent_devp = p_dip; 648544961713Sgirish hw_p->magic = NXGE_NEPTUNE_MAGIC; 648644961713Sgirish nxgep->nxge_hw_p = hw_p; 648744961713Sgirish hw_p->ndevs++; 648844961713Sgirish hw_p->nxge_p[nxgep->function_num] = nxgep; 648944961713Sgirish hw_p->next = nxge_hw_list; 649059ac0c16Sdavemq if (nxgep->niu_type == N2_NIU) { 649159ac0c16Sdavemq hw_p->niu_type = N2_NIU; 649259ac0c16Sdavemq hw_p->platform_type = P_NEPTUNE_NIU; 649359ac0c16Sdavemq } else { 649459ac0c16Sdavemq hw_p->niu_type = NIU_TYPE_NONE; 64952e59129aSraghus hw_p->platform_type = P_NEPTUNE_NONE; 649659ac0c16Sdavemq } 649744961713Sgirish 649844961713Sgirish MUTEX_INIT(&hw_p->nxge_cfg_lock, NULL, MUTEX_DRIVER, NULL); 649944961713Sgirish MUTEX_INIT(&hw_p->nxge_tcam_lock, NULL, MUTEX_DRIVER, NULL); 650044961713Sgirish MUTEX_INIT(&hw_p->nxge_vlan_lock, NULL, MUTEX_DRIVER, NULL); 650144961713Sgirish MUTEX_INIT(&hw_p->nxge_mdio_lock, NULL, MUTEX_DRIVER, NULL); 650244961713Sgirish 650344961713Sgirish nxge_hw_list = hw_p; 650459ac0c16Sdavemq 650559ac0c16Sdavemq (void) nxge_scan_ports_phy(nxgep, nxge_hw_list); 650644961713Sgirish } 650744961713Sgirish 650844961713Sgirish MUTEX_EXIT(&nxge_common_lock); 650959ac0c16Sdavemq 65102e59129aSraghus nxgep->platform_type = hw_p->platform_type; 651159ac0c16Sdavemq if (nxgep->niu_type != N2_NIU) { 651259ac0c16Sdavemq nxgep->niu_type = hw_p->niu_type; 651359ac0c16Sdavemq } 651459ac0c16Sdavemq 651544961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 65164045d941Ssowmini "==> nxge_init_common_device (nxge_hw_list) $%p", 65174045d941Ssowmini nxge_hw_list)); 651844961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, "<== nxge_init_common_device")); 651944961713Sgirish 652044961713Sgirish return (NXGE_OK); 652144961713Sgirish } 652244961713Sgirish 652344961713Sgirish static void 652444961713Sgirish nxge_uninit_common_dev(p_nxge_t nxgep) 652544961713Sgirish { 652644961713Sgirish p_nxge_hw_list_t hw_p, h_hw_p; 65270b0beae0Sspeer p_nxge_dma_pt_cfg_t p_dma_cfgp; 65280b0beae0Sspeer p_nxge_hw_pt_cfg_t p_cfgp; 652944961713Sgirish dev_info_t *p_dip; 653044961713Sgirish 653144961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, "==> nxge_uninit_common_device")); 653244961713Sgirish if (nxgep->nxge_hw_p == NULL) { 653344961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 65344045d941Ssowmini "<== nxge_uninit_common_device (no common)")); 653544961713Sgirish return; 653644961713Sgirish } 653744961713Sgirish 653844961713Sgirish MUTEX_ENTER(&nxge_common_lock); 653944961713Sgirish h_hw_p = nxge_hw_list; 654044961713Sgirish for (hw_p = nxge_hw_list; hw_p; hw_p = hw_p->next) { 654144961713Sgirish p_dip = hw_p->parent_devp; 654244961713Sgirish if (nxgep->nxge_hw_p == hw_p && 65434045d941Ssowmini p_dip == nxgep->p_dip && 65444045d941Ssowmini nxgep->nxge_hw_p->magic == NXGE_NEPTUNE_MAGIC && 65454045d941Ssowmini hw_p->magic == NXGE_NEPTUNE_MAGIC) { 654644961713Sgirish 654744961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 65484045d941Ssowmini "==> nxge_uninit_common_device:func # %d " 65494045d941Ssowmini "hw_p $%p parent dip $%p " 65504045d941Ssowmini "ndevs %d (found)", 65514045d941Ssowmini nxgep->function_num, 65524045d941Ssowmini hw_p, 65534045d941Ssowmini p_dip, 65544045d941Ssowmini hw_p->ndevs)); 655544961713Sgirish 65560b0beae0Sspeer /* 65570b0beae0Sspeer * Release the RDC table, a shared resoruce 65580b0beae0Sspeer * of the nxge hardware. The RDC table was 65590b0beae0Sspeer * assigned to this instance of nxge in 65600b0beae0Sspeer * nxge_use_cfg_dma_config(). 65610b0beae0Sspeer */ 65620b0beae0Sspeer p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 65630b0beae0Sspeer p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 65640b0beae0Sspeer (void) nxge_fzc_rdc_tbl_unbind(nxgep, 6565c6e5ef56Syc p_cfgp->def_mac_rxdma_grpid); 65660b0beae0Sspeer 656744961713Sgirish if (hw_p->ndevs) { 656844961713Sgirish hw_p->ndevs--; 656944961713Sgirish } 657044961713Sgirish hw_p->nxge_p[nxgep->function_num] = NULL; 657144961713Sgirish if (!hw_p->ndevs) { 657244961713Sgirish MUTEX_DESTROY(&hw_p->nxge_vlan_lock); 657344961713Sgirish MUTEX_DESTROY(&hw_p->nxge_tcam_lock); 657444961713Sgirish MUTEX_DESTROY(&hw_p->nxge_cfg_lock); 657544961713Sgirish MUTEX_DESTROY(&hw_p->nxge_mdio_lock); 657644961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 65774045d941Ssowmini "==> nxge_uninit_common_device: " 65784045d941Ssowmini "func # %d " 65794045d941Ssowmini "hw_p $%p parent dip $%p " 65804045d941Ssowmini "ndevs %d (last)", 65814045d941Ssowmini nxgep->function_num, 65824045d941Ssowmini hw_p, 65834045d941Ssowmini p_dip, 65844045d941Ssowmini hw_p->ndevs)); 658544961713Sgirish 6586678453a8Sspeer nxge_hio_uninit(nxgep); 6587678453a8Sspeer 658844961713Sgirish if (hw_p == nxge_hw_list) { 658944961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 65904045d941Ssowmini "==> nxge_uninit_common_device:" 65914045d941Ssowmini "remove head func # %d " 65924045d941Ssowmini "hw_p $%p parent dip $%p " 65934045d941Ssowmini "ndevs %d (head)", 65944045d941Ssowmini nxgep->function_num, 65954045d941Ssowmini hw_p, 65964045d941Ssowmini p_dip, 65974045d941Ssowmini hw_p->ndevs)); 659844961713Sgirish nxge_hw_list = hw_p->next; 659944961713Sgirish } else { 660044961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 66014045d941Ssowmini "==> nxge_uninit_common_device:" 66024045d941Ssowmini "remove middle func # %d " 66034045d941Ssowmini "hw_p $%p parent dip $%p " 66044045d941Ssowmini "ndevs %d (middle)", 66054045d941Ssowmini nxgep->function_num, 66064045d941Ssowmini hw_p, 66074045d941Ssowmini p_dip, 66084045d941Ssowmini hw_p->ndevs)); 660944961713Sgirish h_hw_p->next = hw_p->next; 661044961713Sgirish } 661144961713Sgirish 6612678453a8Sspeer nxgep->nxge_hw_p = NULL; 661344961713Sgirish KMEM_FREE(hw_p, sizeof (nxge_hw_list_t)); 661444961713Sgirish } 661544961713Sgirish break; 661644961713Sgirish } else { 661744961713Sgirish h_hw_p = hw_p; 661844961713Sgirish } 661944961713Sgirish } 662044961713Sgirish 662144961713Sgirish MUTEX_EXIT(&nxge_common_lock); 662244961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 66234045d941Ssowmini "==> nxge_uninit_common_device (nxge_hw_list) $%p", 66244045d941Ssowmini nxge_hw_list)); 662544961713Sgirish 662644961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, "<= nxge_uninit_common_device")); 662744961713Sgirish } 662859ac0c16Sdavemq 662959ac0c16Sdavemq /* 66302e59129aSraghus * Determines the number of ports from the niu_type or the platform type. 663159ac0c16Sdavemq * Returns the number of ports, or returns zero on failure. 663259ac0c16Sdavemq */ 663359ac0c16Sdavemq 663459ac0c16Sdavemq int 66352e59129aSraghus nxge_get_nports(p_nxge_t nxgep) 663659ac0c16Sdavemq { 663759ac0c16Sdavemq int nports = 0; 663859ac0c16Sdavemq 66392e59129aSraghus switch (nxgep->niu_type) { 664059ac0c16Sdavemq case N2_NIU: 664159ac0c16Sdavemq case NEPTUNE_2_10GF: 664259ac0c16Sdavemq nports = 2; 664359ac0c16Sdavemq break; 664459ac0c16Sdavemq case NEPTUNE_4_1GC: 664559ac0c16Sdavemq case NEPTUNE_2_10GF_2_1GC: 664659ac0c16Sdavemq case NEPTUNE_1_10GF_3_1GC: 664759ac0c16Sdavemq case NEPTUNE_1_1GC_1_10GF_2_1GC: 664859a835ddSjoycey case NEPTUNE_2_10GF_2_1GRF: 664959ac0c16Sdavemq nports = 4; 665059ac0c16Sdavemq break; 665159ac0c16Sdavemq default: 66522e59129aSraghus switch (nxgep->platform_type) { 66532e59129aSraghus case P_NEPTUNE_NIU: 66542e59129aSraghus case P_NEPTUNE_ATLAS_2PORT: 66552e59129aSraghus nports = 2; 66562e59129aSraghus break; 66572e59129aSraghus case P_NEPTUNE_ATLAS_4PORT: 66582e59129aSraghus case P_NEPTUNE_MARAMBA_P0: 66592e59129aSraghus case P_NEPTUNE_MARAMBA_P1: 6660d81011f0Ssbehera case P_NEPTUNE_ALONSO: 66612e59129aSraghus nports = 4; 66622e59129aSraghus break; 66632e59129aSraghus default: 66642e59129aSraghus break; 66652e59129aSraghus } 666659ac0c16Sdavemq break; 666759ac0c16Sdavemq } 666859ac0c16Sdavemq 666959ac0c16Sdavemq return (nports); 667059ac0c16Sdavemq } 6671ec090658Sml 6672ec090658Sml /* 6673ec090658Sml * The following two functions are to support 6674ec090658Sml * PSARC/2007/453 MSI-X interrupt limit override. 6675ec090658Sml */ 6676ec090658Sml static int 6677ec090658Sml nxge_create_msi_property(p_nxge_t nxgep) 6678ec090658Sml { 6679ec090658Sml int nmsi; 6680ec090658Sml extern int ncpus; 6681ec090658Sml 6682ec090658Sml NXGE_DEBUG_MSG((nxgep, MOD_CTL, "==>nxge_create_msi_property")); 6683ec090658Sml 6684ec090658Sml switch (nxgep->mac.portmode) { 6685ec090658Sml case PORT_10G_COPPER: 6686ec090658Sml case PORT_10G_FIBER: 668700161856Syc case PORT_10G_TN1010: 6688ec090658Sml (void) ddi_prop_create(DDI_DEV_T_NONE, nxgep->dip, 6689ec090658Sml DDI_PROP_CANSLEEP, "#msix-request", NULL, 0); 6690ec090658Sml /* 6691ec090658Sml * The maximum MSI-X requested will be 8. 6692ec090658Sml * If the # of CPUs is less than 8, we will reqeust 6693ec090658Sml * # MSI-X based on the # of CPUs. 6694ec090658Sml */ 6695ec090658Sml if (ncpus >= NXGE_MSIX_REQUEST_10G) { 6696ec090658Sml nmsi = NXGE_MSIX_REQUEST_10G; 6697ec090658Sml } else { 6698ec090658Sml nmsi = ncpus; 6699ec090658Sml } 6700ec090658Sml NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6701ec090658Sml "==>nxge_create_msi_property(10G): exists 0x%x (nmsi %d)", 6702ec090658Sml ddi_prop_exists(DDI_DEV_T_NONE, nxgep->dip, 6703ec090658Sml DDI_PROP_CANSLEEP, "#msix-request"), nmsi)); 6704ec090658Sml break; 6705ec090658Sml 6706ec090658Sml default: 6707ec090658Sml nmsi = NXGE_MSIX_REQUEST_1G; 6708ec090658Sml NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6709ec090658Sml "==>nxge_create_msi_property(1G): exists 0x%x (nmsi %d)", 6710ec090658Sml ddi_prop_exists(DDI_DEV_T_NONE, nxgep->dip, 6711ec090658Sml DDI_PROP_CANSLEEP, "#msix-request"), nmsi)); 6712ec090658Sml break; 6713ec090658Sml } 6714ec090658Sml 6715ec090658Sml NXGE_DEBUG_MSG((nxgep, MOD_CTL, "<==nxge_create_msi_property")); 6716ec090658Sml return (nmsi); 6717ec090658Sml } 67184045d941Ssowmini 67194045d941Ssowmini /* ARGSUSED */ 67204045d941Ssowmini static int 67214045d941Ssowmini nxge_get_def_val(nxge_t *nxgep, mac_prop_id_t pr_num, uint_t pr_valsize, 67224045d941Ssowmini void *pr_val) 67234045d941Ssowmini { 67244045d941Ssowmini int err = 0; 67254045d941Ssowmini link_flowctrl_t fl; 67264045d941Ssowmini 67274045d941Ssowmini switch (pr_num) { 67283fd94f8cSam case MAC_PROP_AUTONEG: 67294045d941Ssowmini *(uint8_t *)pr_val = 1; 67304045d941Ssowmini break; 67313fd94f8cSam case MAC_PROP_FLOWCTRL: 67324045d941Ssowmini if (pr_valsize < sizeof (link_flowctrl_t)) 67334045d941Ssowmini return (EINVAL); 67344045d941Ssowmini fl = LINK_FLOWCTRL_RX; 67354045d941Ssowmini bcopy(&fl, pr_val, sizeof (fl)); 67364045d941Ssowmini break; 67373fd94f8cSam case MAC_PROP_ADV_1000FDX_CAP: 67383fd94f8cSam case MAC_PROP_EN_1000FDX_CAP: 67394045d941Ssowmini *(uint8_t *)pr_val = 1; 67404045d941Ssowmini break; 67413fd94f8cSam case MAC_PROP_ADV_100FDX_CAP: 67423fd94f8cSam case MAC_PROP_EN_100FDX_CAP: 67434045d941Ssowmini *(uint8_t *)pr_val = 1; 67444045d941Ssowmini break; 67454045d941Ssowmini default: 67464045d941Ssowmini err = ENOTSUP; 67474045d941Ssowmini break; 67484045d941Ssowmini } 67494045d941Ssowmini return (err); 67504045d941Ssowmini } 67516f157acbSml 67526f157acbSml 67536f157acbSml /* 67546f157acbSml * The following is a software around for the Neptune hardware's 67556f157acbSml * interrupt bugs; The Neptune hardware may generate spurious interrupts when 67566f157acbSml * an interrupr handler is removed. 67576f157acbSml */ 67586f157acbSml #define NXGE_PCI_PORT_LOGIC_OFFSET 0x98 67596f157acbSml #define NXGE_PIM_RESET (1ULL << 29) 67606f157acbSml #define NXGE_GLU_RESET (1ULL << 30) 67616f157acbSml #define NXGE_NIU_RESET (1ULL << 31) 67626f157acbSml #define NXGE_PCI_RESET_ALL (NXGE_PIM_RESET | \ 67636f157acbSml NXGE_GLU_RESET | \ 67646f157acbSml NXGE_NIU_RESET) 67656f157acbSml 67666f157acbSml #define NXGE_WAIT_QUITE_TIME 200000 67676f157acbSml #define NXGE_WAIT_QUITE_RETRY 40 67686f157acbSml #define NXGE_PCI_RESET_WAIT 1000000 /* one second */ 67696f157acbSml 67706f157acbSml static void 67716f157acbSml nxge_niu_peu_reset(p_nxge_t nxgep) 67726f157acbSml { 67736f157acbSml uint32_t rvalue; 67746f157acbSml p_nxge_hw_list_t hw_p; 67756f157acbSml p_nxge_t fnxgep; 67766f157acbSml int i, j; 67776f157acbSml 67786f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, "==> nxge_niu_peu_reset")); 67796f157acbSml if ((hw_p = nxgep->nxge_hw_p) == NULL) { 67806f157acbSml NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 67816f157acbSml "==> nxge_niu_peu_reset: NULL hardware pointer")); 67826f157acbSml return; 67836f157acbSml } 67846f157acbSml 67856f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 67866f157acbSml "==> nxge_niu_peu_reset: flags 0x%x link timer id %d timer id %d", 67876f157acbSml hw_p->flags, nxgep->nxge_link_poll_timerid, 67886f157acbSml nxgep->nxge_timerid)); 67896f157acbSml 67906f157acbSml MUTEX_ENTER(&hw_p->nxge_cfg_lock); 67916f157acbSml /* 67926f157acbSml * Make sure other instances from the same hardware 67936f157acbSml * stop sending PIO and in quiescent state. 67946f157acbSml */ 67956f157acbSml for (i = 0; i < NXGE_MAX_PORTS; i++) { 67966f157acbSml fnxgep = hw_p->nxge_p[i]; 67976f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 67986f157acbSml "==> nxge_niu_peu_reset: checking entry %d " 67996f157acbSml "nxgep $%p", i, fnxgep)); 68006f157acbSml #ifdef NXGE_DEBUG 68016f157acbSml if (fnxgep) { 68026f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 68036f157acbSml "==> nxge_niu_peu_reset: entry %d (function %d) " 68046f157acbSml "link timer id %d hw timer id %d", 68056f157acbSml i, fnxgep->function_num, 68066f157acbSml fnxgep->nxge_link_poll_timerid, 68076f157acbSml fnxgep->nxge_timerid)); 68086f157acbSml } 68096f157acbSml #endif 68106f157acbSml if (fnxgep && fnxgep != nxgep && 68116f157acbSml (fnxgep->nxge_timerid || fnxgep->nxge_link_poll_timerid)) { 68126f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 68136f157acbSml "==> nxge_niu_peu_reset: checking $%p " 68146f157acbSml "(function %d) timer ids", 68156f157acbSml fnxgep, fnxgep->function_num)); 68166f157acbSml for (j = 0; j < NXGE_WAIT_QUITE_RETRY; j++) { 68176f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 68186f157acbSml "==> nxge_niu_peu_reset: waiting")); 68196f157acbSml NXGE_DELAY(NXGE_WAIT_QUITE_TIME); 68206f157acbSml if (!fnxgep->nxge_timerid && 68216f157acbSml !fnxgep->nxge_link_poll_timerid) { 68226f157acbSml break; 68236f157acbSml } 68246f157acbSml } 68256f157acbSml NXGE_DELAY(NXGE_WAIT_QUITE_TIME); 68266f157acbSml if (fnxgep->nxge_timerid || 68276f157acbSml fnxgep->nxge_link_poll_timerid) { 68286f157acbSml MUTEX_EXIT(&hw_p->nxge_cfg_lock); 68296f157acbSml NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 68306f157acbSml "<== nxge_niu_peu_reset: cannot reset " 68316f157acbSml "hardware (devices are still in use)")); 68326f157acbSml return; 68336f157acbSml } 68346f157acbSml } 68356f157acbSml } 68366f157acbSml 68376f157acbSml if ((hw_p->flags & COMMON_RESET_NIU_PCI) != COMMON_RESET_NIU_PCI) { 68386f157acbSml hw_p->flags |= COMMON_RESET_NIU_PCI; 68396f157acbSml rvalue = pci_config_get32(nxgep->dev_regs->nxge_pciregh, 68406f157acbSml NXGE_PCI_PORT_LOGIC_OFFSET); 68416f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 68426f157acbSml "nxge_niu_peu_reset: read offset 0x%x (%d) " 68436f157acbSml "(data 0x%x)", 68446f157acbSml NXGE_PCI_PORT_LOGIC_OFFSET, 68456f157acbSml NXGE_PCI_PORT_LOGIC_OFFSET, 68466f157acbSml rvalue)); 68476f157acbSml 68486f157acbSml rvalue |= NXGE_PCI_RESET_ALL; 68496f157acbSml pci_config_put32(nxgep->dev_regs->nxge_pciregh, 68506f157acbSml NXGE_PCI_PORT_LOGIC_OFFSET, rvalue); 68516f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 68526f157acbSml "nxge_niu_peu_reset: RESETTING NIU: write NIU reset 0x%x", 68536f157acbSml rvalue)); 68546f157acbSml 68556f157acbSml NXGE_DELAY(NXGE_PCI_RESET_WAIT); 68566f157acbSml } 68576f157acbSml 68586f157acbSml MUTEX_EXIT(&hw_p->nxge_cfg_lock); 68596f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_niu_peu_reset")); 68606f157acbSml } 6861d6d3405fSml 6862d6d3405fSml static void 6863d6d3405fSml nxge_set_pci_replay_timeout(p_nxge_t nxgep) 6864d6d3405fSml { 6865d6d3405fSml p_dev_regs_t dev_regs; 6866d6d3405fSml uint32_t value; 6867d6d3405fSml 6868d6d3405fSml NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_set_pci_replay_timeout")); 6869d6d3405fSml 6870d6d3405fSml if (!nxge_set_replay_timer) { 6871d6d3405fSml NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6872d6d3405fSml "==> nxge_set_pci_replay_timeout: will not change " 6873d6d3405fSml "the timeout")); 6874d6d3405fSml return; 6875d6d3405fSml } 6876d6d3405fSml 6877d6d3405fSml dev_regs = nxgep->dev_regs; 6878d6d3405fSml NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6879d6d3405fSml "==> nxge_set_pci_replay_timeout: dev_regs 0x%p pcireg 0x%p", 6880d6d3405fSml dev_regs, dev_regs->nxge_pciregh)); 6881d6d3405fSml 6882d6d3405fSml if (dev_regs == NULL || (dev_regs->nxge_pciregh == NULL)) { 6883f720bc57Syc NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6884d6d3405fSml "==> nxge_set_pci_replay_timeout: NULL dev_regs $%p or " 6885d6d3405fSml "no PCI handle", 6886d6d3405fSml dev_regs)); 6887d6d3405fSml return; 6888d6d3405fSml } 6889d6d3405fSml value = (pci_config_get32(dev_regs->nxge_pciregh, 6890d6d3405fSml PCI_REPLAY_TIMEOUT_CFG_OFFSET) | 6891d6d3405fSml (nxge_replay_timeout << PCI_REPLAY_TIMEOUT_SHIFT)); 6892d6d3405fSml 6893d6d3405fSml NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6894d6d3405fSml "nxge_set_pci_replay_timeout: replay timeout value before set 0x%x " 6895d6d3405fSml "(timeout value to set 0x%x at offset 0x%x) value 0x%x", 6896d6d3405fSml pci_config_get32(dev_regs->nxge_pciregh, 6897d6d3405fSml PCI_REPLAY_TIMEOUT_CFG_OFFSET), nxge_replay_timeout, 6898d6d3405fSml PCI_REPLAY_TIMEOUT_CFG_OFFSET, value)); 6899d6d3405fSml 6900d6d3405fSml pci_config_put32(dev_regs->nxge_pciregh, PCI_REPLAY_TIMEOUT_CFG_OFFSET, 6901d6d3405fSml value); 6902d6d3405fSml 6903d6d3405fSml NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6904d6d3405fSml "nxge_set_pci_replay_timeout: replay timeout value after set 0x%x", 6905d6d3405fSml pci_config_get32(dev_regs->nxge_pciregh, 6906d6d3405fSml PCI_REPLAY_TIMEOUT_CFG_OFFSET))); 6907d6d3405fSml 6908d6d3405fSml NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_set_pci_replay_timeout")); 6909d6d3405fSml } 6910