144961713Sgirish /* 244961713Sgirish * CDDL HEADER START 344961713Sgirish * 444961713Sgirish * The contents of this file are subject to the terms of the 544961713Sgirish * Common Development and Distribution License (the "License"). 644961713Sgirish * You may not use this file except in compliance with the License. 744961713Sgirish * 844961713Sgirish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 944961713Sgirish * or http://www.opensolaris.org/os/licensing. 1044961713Sgirish * See the License for the specific language governing permissions 1144961713Sgirish * and limitations under the License. 1244961713Sgirish * 1344961713Sgirish * When distributing Covered Code, include this CDDL HEADER in each 1444961713Sgirish * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1544961713Sgirish * If applicable, add the following below this CDDL HEADER, with the 1644961713Sgirish * fields enclosed by brackets "[]" replaced with your own identifying 1744961713Sgirish * information: Portions Copyright [yyyy] [name of copyright owner] 1844961713Sgirish * 1944961713Sgirish * CDDL HEADER END 2044961713Sgirish */ 2148056c53SMichael Speer 2244961713Sgirish /* 237b26d9ffSSantwona Behera * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 2444961713Sgirish * Use is subject to license terms. 2544961713Sgirish */ 2644961713Sgirish 2744961713Sgirish /* 2844961713Sgirish * SunOs MT STREAMS NIU/Neptune 10Gb Ethernet Device Driver. 2944961713Sgirish */ 3044961713Sgirish #include <sys/nxge/nxge_impl.h> 31678453a8Sspeer #include <sys/nxge/nxge_hio.h> 32678453a8Sspeer #include <sys/nxge/nxge_rxdma.h> 3314ea4bb7Ssd #include <sys/pcie.h> 3444961713Sgirish 3544961713Sgirish uint32_t nxge_use_partition = 0; /* debug partition flag */ 3644961713Sgirish uint32_t nxge_dma_obp_props_only = 1; /* use obp published props */ 3744961713Sgirish uint32_t nxge_use_rdc_intr = 1; /* debug to assign rdc intr */ 3844961713Sgirish /* 39ec090658Sml * PSARC/2007/453 MSI-X interrupt limit override 4044961713Sgirish */ 41ec090658Sml uint32_t nxge_msi_enable = 2; 4244961713Sgirish 436f157acbSml /* 446f157acbSml * Software workaround for a Neptune (PCI-E) 456f157acbSml * hardware interrupt bug which the hardware 466f157acbSml * may generate spurious interrupts after the 476f157acbSml * device interrupt handler was removed. If this flag 486f157acbSml * is enabled, the driver will reset the 496f157acbSml * hardware when devices are being detached. 506f157acbSml */ 516f157acbSml uint32_t nxge_peu_reset_enable = 0; 526f157acbSml 53b4d05839Sml /* 54b4d05839Sml * Software workaround for the hardware 55b4d05839Sml * checksum bugs that affect packet transmission 56b4d05839Sml * and receive: 57b4d05839Sml * 58b4d05839Sml * Usage of nxge_cksum_offload: 59b4d05839Sml * 60b4d05839Sml * (1) nxge_cksum_offload = 0 (default): 61b4d05839Sml * - transmits packets: 62b4d05839Sml * TCP: uses the hardware checksum feature. 63b4d05839Sml * UDP: driver will compute the software checksum 64b4d05839Sml * based on the partial checksum computed 65b4d05839Sml * by the IP layer. 66b4d05839Sml * - receives packets 67b4d05839Sml * TCP: marks packets checksum flags based on hardware result. 68b4d05839Sml * UDP: will not mark checksum flags. 69b4d05839Sml * 70b4d05839Sml * (2) nxge_cksum_offload = 1: 71b4d05839Sml * - transmit packets: 72b4d05839Sml * TCP/UDP: uses the hardware checksum feature. 73b4d05839Sml * - receives packets 74b4d05839Sml * TCP/UDP: marks packet checksum flags based on hardware result. 75b4d05839Sml * 76b4d05839Sml * (3) nxge_cksum_offload = 2: 77b4d05839Sml * - The driver will not register its checksum capability. 78b4d05839Sml * Checksum for both TCP and UDP will be computed 79b4d05839Sml * by the stack. 80b4d05839Sml * - The software LSO is not allowed in this case. 81b4d05839Sml * 82b4d05839Sml * (4) nxge_cksum_offload > 2: 83b4d05839Sml * - Will be treated as it is set to 2 84b4d05839Sml * (stack will compute the checksum). 85b4d05839Sml * 86b4d05839Sml * (5) If the hardware bug is fixed, this workaround 87b4d05839Sml * needs to be updated accordingly to reflect 88b4d05839Sml * the new hardware revision. 89b4d05839Sml */ 90b4d05839Sml uint32_t nxge_cksum_offload = 0; 91678453a8Sspeer 9244961713Sgirish /* 9344961713Sgirish * Globals: tunable parameters (/etc/system or adb) 9444961713Sgirish * 9544961713Sgirish */ 9644961713Sgirish uint32_t nxge_rbr_size = NXGE_RBR_RBB_DEFAULT; 9744961713Sgirish uint32_t nxge_rbr_spare_size = 0; 9844961713Sgirish uint32_t nxge_rcr_size = NXGE_RCR_DEFAULT; 99*4df55fdeSJanie Lu uint16_t nxge_rdc_buf_offset = SW_OFFSET_NO_OFFSET; 10044961713Sgirish uint32_t nxge_tx_ring_size = NXGE_TX_RING_DEFAULT; 101b3a0105bSspeer boolean_t nxge_no_msg = B_TRUE; /* control message display */ 10244961713Sgirish uint32_t nxge_no_link_notify = 0; /* control DL_NOTIFY */ 10344961713Sgirish uint32_t nxge_bcopy_thresh = TX_BCOPY_MAX; 10444961713Sgirish uint32_t nxge_dvma_thresh = TX_FASTDVMA_MIN; 10544961713Sgirish uint32_t nxge_dma_stream_thresh = TX_STREAM_MIN; 10644961713Sgirish uint32_t nxge_jumbo_mtu = TX_JUMBO_MTU; 1071f8914d5Sml nxge_tx_mode_t nxge_tx_scheme = NXGE_USE_SERIAL; 10844961713Sgirish 10930ac2e7bSml /* MAX LSO size */ 11030ac2e7bSml #define NXGE_LSO_MAXLEN 65535 11130ac2e7bSml uint32_t nxge_lso_max = NXGE_LSO_MAXLEN; 11230ac2e7bSml 11344961713Sgirish 11444961713Sgirish /* 11544961713Sgirish * Add tunable to reduce the amount of time spent in the 11644961713Sgirish * ISR doing Rx Processing. 11744961713Sgirish */ 11844961713Sgirish uint32_t nxge_max_rx_pkts = 1024; 11944961713Sgirish 12044961713Sgirish /* 12144961713Sgirish * Tunables to manage the receive buffer blocks. 12244961713Sgirish * 12344961713Sgirish * nxge_rx_threshold_hi: copy all buffers. 12444961713Sgirish * nxge_rx_bcopy_size_type: receive buffer block size type. 12544961713Sgirish * nxge_rx_threshold_lo: copy only up to tunable block size type. 12644961713Sgirish */ 12744961713Sgirish nxge_rxbuf_threshold_t nxge_rx_threshold_hi = NXGE_RX_COPY_6; 12844961713Sgirish nxge_rxbuf_type_t nxge_rx_buf_size_type = RCR_PKTBUFSZ_0; 12944961713Sgirish nxge_rxbuf_threshold_t nxge_rx_threshold_lo = NXGE_RX_COPY_3; 13044961713Sgirish 131678453a8Sspeer /* Use kmem_alloc() to allocate data buffers. */ 132ef523517SMichael Speer #if defined(__sparc) 133d00f30bbSspeer uint32_t nxge_use_kmem_alloc = 1; 134ef523517SMichael Speer #elif defined(__i386) 135d00f30bbSspeer uint32_t nxge_use_kmem_alloc = 0; 136ef523517SMichael Speer #else 137ef523517SMichael Speer uint32_t nxge_use_kmem_alloc = 1; 138678453a8Sspeer #endif 139678453a8Sspeer 14044961713Sgirish rtrace_t npi_rtracebuf; 14144961713Sgirish 142d6d3405fSml /* 143d6d3405fSml * The hardware sometimes fails to allow enough time for the link partner 144d6d3405fSml * to send an acknowledgement for packets that the hardware sent to it. The 145d6d3405fSml * hardware resends the packets earlier than it should be in those instances. 146d6d3405fSml * This behavior caused some switches to acknowledge the wrong packets 147d6d3405fSml * and it triggered the fatal error. 148d6d3405fSml * This software workaround is to set the replay timer to a value 149d6d3405fSml * suggested by the hardware team. 150d6d3405fSml * 151d6d3405fSml * PCI config space replay timer register: 152d6d3405fSml * The following replay timeout value is 0xc 153d6d3405fSml * for bit 14:18. 154d6d3405fSml */ 155d6d3405fSml #define PCI_REPLAY_TIMEOUT_CFG_OFFSET 0xb8 156d6d3405fSml #define PCI_REPLAY_TIMEOUT_SHIFT 14 157d6d3405fSml 158d6d3405fSml uint32_t nxge_set_replay_timer = 1; 159d6d3405fSml uint32_t nxge_replay_timeout = 0xc; 160d6d3405fSml 161cf020df9Sml /* 162cf020df9Sml * The transmit serialization sometimes causes 163cf020df9Sml * longer sleep before calling the driver transmit 164cf020df9Sml * function as it sleeps longer than it should. 165cf020df9Sml * The performace group suggests that a time wait tunable 166cf020df9Sml * can be used to set the maximum wait time when needed 167cf020df9Sml * and the default is set to 1 tick. 168cf020df9Sml */ 169cf020df9Sml uint32_t nxge_tx_serial_maxsleep = 1; 170cf020df9Sml 17144961713Sgirish #if defined(sun4v) 17244961713Sgirish /* 17344961713Sgirish * Hypervisor N2/NIU services information. 17444961713Sgirish */ 175*4df55fdeSJanie Lu /* 176*4df55fdeSJanie Lu * The following is the default API supported: 177*4df55fdeSJanie Lu * major 1 and minor 1. 178*4df55fdeSJanie Lu * 179*4df55fdeSJanie Lu * Please update the MAX_NIU_MAJORS, 180*4df55fdeSJanie Lu * MAX_NIU_MINORS, and minor number supported 181*4df55fdeSJanie Lu * when the newer Hypervior API interfaces 182*4df55fdeSJanie Lu * are added. Also, please update nxge_hsvc_register() 183*4df55fdeSJanie Lu * if needed. 184*4df55fdeSJanie Lu */ 18544961713Sgirish static hsvc_info_t niu_hsvc = { 18644961713Sgirish HSVC_REV_1, NULL, HSVC_GROUP_NIU, NIU_MAJOR_VER, 18744961713Sgirish NIU_MINOR_VER, "nxge" 18844961713Sgirish }; 189678453a8Sspeer 190678453a8Sspeer static int nxge_hsvc_register(p_nxge_t); 19144961713Sgirish #endif 19244961713Sgirish 19344961713Sgirish /* 19444961713Sgirish * Function Prototypes 19544961713Sgirish */ 19644961713Sgirish static int nxge_attach(dev_info_t *, ddi_attach_cmd_t); 19744961713Sgirish static int nxge_detach(dev_info_t *, ddi_detach_cmd_t); 19844961713Sgirish static void nxge_unattach(p_nxge_t); 19919397407SSherry Moore static int nxge_quiesce(dev_info_t *); 20044961713Sgirish 20144961713Sgirish #if NXGE_PROPERTY 20244961713Sgirish static void nxge_remove_hard_properties(p_nxge_t); 20344961713Sgirish #endif 20444961713Sgirish 205678453a8Sspeer /* 206678453a8Sspeer * These two functions are required by nxge_hio.c 207678453a8Sspeer */ 208da14cebeSEric Cheng extern int nxge_m_mmac_remove(void *arg, int slot); 209651ce697SMichael Speer extern void nxge_grp_cleanup(p_nxge_t nxge); 210678453a8Sspeer 21144961713Sgirish static nxge_status_t nxge_setup_system_dma_pages(p_nxge_t); 21244961713Sgirish 21344961713Sgirish static nxge_status_t nxge_setup_mutexes(p_nxge_t); 21444961713Sgirish static void nxge_destroy_mutexes(p_nxge_t); 21544961713Sgirish 21644961713Sgirish static nxge_status_t nxge_map_regs(p_nxge_t nxgep); 21744961713Sgirish static void nxge_unmap_regs(p_nxge_t nxgep); 21844961713Sgirish #ifdef NXGE_DEBUG 21944961713Sgirish static void nxge_test_map_regs(p_nxge_t nxgep); 22044961713Sgirish #endif 22144961713Sgirish 22244961713Sgirish static nxge_status_t nxge_add_intrs(p_nxge_t nxgep); 22344961713Sgirish static void nxge_remove_intrs(p_nxge_t nxgep); 22444961713Sgirish 22544961713Sgirish static nxge_status_t nxge_add_intrs_adv(p_nxge_t nxgep); 22644961713Sgirish static nxge_status_t nxge_add_intrs_adv_type(p_nxge_t, uint32_t); 22744961713Sgirish static nxge_status_t nxge_add_intrs_adv_type_fix(p_nxge_t, uint32_t); 22844961713Sgirish static void nxge_intrs_enable(p_nxge_t nxgep); 22944961713Sgirish static void nxge_intrs_disable(p_nxge_t nxgep); 23044961713Sgirish 23144961713Sgirish static void nxge_suspend(p_nxge_t); 23244961713Sgirish static nxge_status_t nxge_resume(p_nxge_t); 23344961713Sgirish 23444961713Sgirish static nxge_status_t nxge_setup_dev(p_nxge_t); 23544961713Sgirish static void nxge_destroy_dev(p_nxge_t); 23644961713Sgirish 23744961713Sgirish static nxge_status_t nxge_alloc_mem_pool(p_nxge_t); 23844961713Sgirish static void nxge_free_mem_pool(p_nxge_t); 23944961713Sgirish 240678453a8Sspeer nxge_status_t nxge_alloc_rx_mem_pool(p_nxge_t); 24144961713Sgirish static void nxge_free_rx_mem_pool(p_nxge_t); 24244961713Sgirish 243678453a8Sspeer nxge_status_t nxge_alloc_tx_mem_pool(p_nxge_t); 24444961713Sgirish static void nxge_free_tx_mem_pool(p_nxge_t); 24544961713Sgirish 24644961713Sgirish static nxge_status_t nxge_dma_mem_alloc(p_nxge_t, dma_method_t, 24744961713Sgirish struct ddi_dma_attr *, 24844961713Sgirish size_t, ddi_device_acc_attr_t *, uint_t, 24944961713Sgirish p_nxge_dma_common_t); 25044961713Sgirish 25144961713Sgirish static void nxge_dma_mem_free(p_nxge_dma_common_t); 252678453a8Sspeer static void nxge_dma_free_rx_data_buf(p_nxge_dma_common_t); 25344961713Sgirish 25444961713Sgirish static nxge_status_t nxge_alloc_rx_buf_dma(p_nxge_t, uint16_t, 25544961713Sgirish p_nxge_dma_common_t *, size_t, size_t, uint32_t *); 25644961713Sgirish static void nxge_free_rx_buf_dma(p_nxge_t, p_nxge_dma_common_t, uint32_t); 25744961713Sgirish 25844961713Sgirish static nxge_status_t nxge_alloc_rx_cntl_dma(p_nxge_t, uint16_t, 25944961713Sgirish p_nxge_dma_common_t *, size_t); 26044961713Sgirish static void nxge_free_rx_cntl_dma(p_nxge_t, p_nxge_dma_common_t); 26144961713Sgirish 262678453a8Sspeer extern nxge_status_t nxge_alloc_tx_buf_dma(p_nxge_t, uint16_t, 26344961713Sgirish p_nxge_dma_common_t *, size_t, size_t, uint32_t *); 26444961713Sgirish static void nxge_free_tx_buf_dma(p_nxge_t, p_nxge_dma_common_t, uint32_t); 26544961713Sgirish 266678453a8Sspeer extern nxge_status_t nxge_alloc_tx_cntl_dma(p_nxge_t, uint16_t, 26744961713Sgirish p_nxge_dma_common_t *, 26844961713Sgirish size_t); 26944961713Sgirish static void nxge_free_tx_cntl_dma(p_nxge_t, p_nxge_dma_common_t); 27044961713Sgirish 27144961713Sgirish static int nxge_init_common_dev(p_nxge_t); 27244961713Sgirish static void nxge_uninit_common_dev(p_nxge_t); 2734045d941Ssowmini extern int nxge_param_set_mac(p_nxge_t, queue_t *, mblk_t *, 2744045d941Ssowmini char *, caddr_t); 275e759c33aSMichael Speer #if defined(sun4v) 276e759c33aSMichael Speer extern nxge_status_t nxge_hio_rdc_enable(p_nxge_t nxgep); 277e759c33aSMichael Speer extern nxge_status_t nxge_hio_rdc_intr_arm(p_nxge_t nxge, boolean_t arm); 278e759c33aSMichael Speer #endif 27944961713Sgirish 28044961713Sgirish /* 28144961713Sgirish * The next declarations are for the GLDv3 interface. 28244961713Sgirish */ 28344961713Sgirish static int nxge_m_start(void *); 28444961713Sgirish static void nxge_m_stop(void *); 28544961713Sgirish static int nxge_m_multicst(void *, boolean_t, const uint8_t *); 28644961713Sgirish static int nxge_m_promisc(void *, boolean_t); 28744961713Sgirish static void nxge_m_ioctl(void *, queue_t *, mblk_t *); 28863f531d1SSriharsha Basavapatna nxge_status_t nxge_mac_register(p_nxge_t); 289da14cebeSEric Cheng static int nxge_altmac_set(p_nxge_t nxgep, uint8_t *mac_addr, 290da14cebeSEric Cheng int slot, int rdctbl, boolean_t usetbl); 291da14cebeSEric Cheng void nxge_mmac_kstat_update(p_nxge_t nxgep, int slot, 29258324dfcSspeer boolean_t factory); 293da14cebeSEric Cheng 294da14cebeSEric Cheng static void nxge_m_getfactaddr(void *, uint_t, uint8_t *); 2951bd6825cSml static boolean_t nxge_m_getcapab(void *, mac_capab_t, void *); 2961bd6825cSml static int nxge_m_setprop(void *, const char *, mac_prop_id_t, 2971bd6825cSml uint_t, const void *); 2981bd6825cSml static int nxge_m_getprop(void *, const char *, mac_prop_id_t, 299afdda45fSVasumathi Sundaram - Sun Microsystems uint_t, uint_t, void *, uint_t *); 3001bd6825cSml static int nxge_set_priv_prop(nxge_t *, const char *, uint_t, 3011bd6825cSml const void *); 3024045d941Ssowmini static int nxge_get_priv_prop(nxge_t *, const char *, uint_t, uint_t, 303afdda45fSVasumathi Sundaram - Sun Microsystems void *, uint_t *); 3044045d941Ssowmini static int nxge_get_def_val(nxge_t *, mac_prop_id_t, uint_t, void *); 305da14cebeSEric Cheng static void nxge_fill_ring(void *, mac_ring_type_t, const int, const int, 306da14cebeSEric Cheng mac_ring_info_t *, mac_ring_handle_t); 307da14cebeSEric Cheng static void nxge_group_add_ring(mac_group_driver_t, mac_ring_driver_t, 308da14cebeSEric Cheng mac_ring_type_t); 309da14cebeSEric Cheng static void nxge_group_rem_ring(mac_group_driver_t, mac_ring_driver_t, 310da14cebeSEric Cheng mac_ring_type_t); 3114045d941Ssowmini 3126f157acbSml static void nxge_niu_peu_reset(p_nxge_t nxgep); 313d6d3405fSml static void nxge_set_pci_replay_timeout(nxge_t *); 3144045d941Ssowmini 3154045d941Ssowmini mac_priv_prop_t nxge_priv_props[] = { 3164045d941Ssowmini {"_adv_10gfdx_cap", MAC_PROP_PERM_RW}, 3174045d941Ssowmini {"_adv_pause_cap", MAC_PROP_PERM_RW}, 3184045d941Ssowmini {"_function_number", MAC_PROP_PERM_READ}, 3194045d941Ssowmini {"_fw_version", MAC_PROP_PERM_READ}, 3204045d941Ssowmini {"_port_mode", MAC_PROP_PERM_READ}, 3214045d941Ssowmini {"_hot_swap_phy", MAC_PROP_PERM_READ}, 3224045d941Ssowmini {"_rxdma_intr_time", MAC_PROP_PERM_RW}, 3234045d941Ssowmini {"_rxdma_intr_pkts", MAC_PROP_PERM_RW}, 3244045d941Ssowmini {"_class_opt_ipv4_tcp", MAC_PROP_PERM_RW}, 3254045d941Ssowmini {"_class_opt_ipv4_udp", MAC_PROP_PERM_RW}, 3264045d941Ssowmini {"_class_opt_ipv4_ah", MAC_PROP_PERM_RW}, 3274045d941Ssowmini {"_class_opt_ipv4_sctp", MAC_PROP_PERM_RW}, 3284045d941Ssowmini {"_class_opt_ipv6_tcp", MAC_PROP_PERM_RW}, 3294045d941Ssowmini {"_class_opt_ipv6_udp", MAC_PROP_PERM_RW}, 3304045d941Ssowmini {"_class_opt_ipv6_ah", MAC_PROP_PERM_RW}, 3314045d941Ssowmini {"_class_opt_ipv6_sctp", MAC_PROP_PERM_RW}, 3324045d941Ssowmini {"_soft_lso_enable", MAC_PROP_PERM_RW} 3334045d941Ssowmini }; 3344045d941Ssowmini 3354045d941Ssowmini #define NXGE_MAX_PRIV_PROPS \ 3364045d941Ssowmini (sizeof (nxge_priv_props)/sizeof (mac_priv_prop_t)) 3371bd6825cSml 33844961713Sgirish #define NXGE_NEPTUNE_MAGIC 0x4E584745UL 33944961713Sgirish #define MAX_DUMP_SZ 256 34044961713Sgirish 3411bd6825cSml #define NXGE_M_CALLBACK_FLAGS \ 342da14cebeSEric Cheng (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP) 34344961713Sgirish 344678453a8Sspeer mac_callbacks_t nxge_m_callbacks = { 34544961713Sgirish NXGE_M_CALLBACK_FLAGS, 34644961713Sgirish nxge_m_stat, 34744961713Sgirish nxge_m_start, 34844961713Sgirish nxge_m_stop, 34944961713Sgirish nxge_m_promisc, 35044961713Sgirish nxge_m_multicst, 351da14cebeSEric Cheng NULL, 352da14cebeSEric Cheng NULL, 35344961713Sgirish nxge_m_ioctl, 3541bd6825cSml nxge_m_getcapab, 3551bd6825cSml NULL, 3561bd6825cSml NULL, 3571bd6825cSml nxge_m_setprop, 3581bd6825cSml nxge_m_getprop 35944961713Sgirish }; 36044961713Sgirish 36144961713Sgirish void 36244961713Sgirish nxge_err_inject(p_nxge_t, queue_t *, mblk_t *); 36344961713Sgirish 364ec090658Sml /* PSARC/2007/453 MSI-X interrupt limit override. */ 365ec090658Sml #define NXGE_MSIX_REQUEST_10G 8 366ec090658Sml #define NXGE_MSIX_REQUEST_1G 2 367ec090658Sml static int nxge_create_msi_property(p_nxge_t); 368ef755e7aStc /* 369ef755e7aStc * For applications that care about the 370ef755e7aStc * latency, it was requested by PAE and the 371ef755e7aStc * customers that the driver has tunables that 372ef755e7aStc * allow the user to tune it to a higher number 373ef755e7aStc * interrupts to spread the interrupts among 374ef755e7aStc * multiple channels. The DDI framework limits 375ef755e7aStc * the maximum number of MSI-X resources to allocate 376ef755e7aStc * to 8 (ddi_msix_alloc_limit). If more than 8 377ef755e7aStc * is set, ddi_msix_alloc_limit must be set accordingly. 378ef755e7aStc * The default number of MSI interrupts are set to 379ef755e7aStc * 8 for 10G and 2 for 1G link. 380ef755e7aStc */ 381ef755e7aStc #define NXGE_MSIX_MAX_ALLOWED 32 382ef755e7aStc uint32_t nxge_msix_10g_intrs = NXGE_MSIX_REQUEST_10G; 383ef755e7aStc uint32_t nxge_msix_1g_intrs = NXGE_MSIX_REQUEST_1G; 384ec090658Sml 38544961713Sgirish /* 38644961713Sgirish * These global variables control the message 38744961713Sgirish * output. 38844961713Sgirish */ 38944961713Sgirish out_dbgmsg_t nxge_dbgmsg_out = DBG_CONSOLE | STR_LOG; 390678453a8Sspeer uint64_t nxge_debug_level; 39144961713Sgirish 39244961713Sgirish /* 39344961713Sgirish * This list contains the instance structures for the Neptune 39444961713Sgirish * devices present in the system. The lock exists to guarantee 39544961713Sgirish * mutually exclusive access to the list. 39644961713Sgirish */ 39744961713Sgirish void *nxge_list = NULL; 39844961713Sgirish void *nxge_hw_list = NULL; 39944961713Sgirish nxge_os_mutex_t nxge_common_lock; 4003b2d9860SMichael Speer nxge_os_mutex_t nxgedebuglock; 40144961713Sgirish 40244961713Sgirish extern uint64_t npi_debug_level; 40344961713Sgirish 40444961713Sgirish extern nxge_status_t nxge_ldgv_init(p_nxge_t, int *, int *); 40544961713Sgirish extern nxge_status_t nxge_ldgv_init_n2(p_nxge_t, int *, int *); 40644961713Sgirish extern nxge_status_t nxge_ldgv_uninit(p_nxge_t); 40744961713Sgirish extern nxge_status_t nxge_intr_ldgv_init(p_nxge_t); 40844961713Sgirish extern void nxge_fm_init(p_nxge_t, 40944961713Sgirish ddi_device_acc_attr_t *, 41044961713Sgirish ddi_dma_attr_t *); 41144961713Sgirish extern void nxge_fm_fini(p_nxge_t); 41258324dfcSspeer extern npi_status_t npi_mac_altaddr_disable(npi_handle_t, uint8_t, uint8_t); 41344961713Sgirish 41444961713Sgirish /* 41544961713Sgirish * Count used to maintain the number of buffers being used 41644961713Sgirish * by Neptune instances and loaned up to the upper layers. 41744961713Sgirish */ 41844961713Sgirish uint32_t nxge_mblks_pending = 0; 41944961713Sgirish 42044961713Sgirish /* 42144961713Sgirish * Device register access attributes for PIO. 42244961713Sgirish */ 42344961713Sgirish static ddi_device_acc_attr_t nxge_dev_reg_acc_attr = { 424837c1ac4SStephen Hanson DDI_DEVICE_ATTR_V1, 42544961713Sgirish DDI_STRUCTURE_LE_ACC, 42644961713Sgirish DDI_STRICTORDER_ACC, 427837c1ac4SStephen Hanson DDI_DEFAULT_ACC 42844961713Sgirish }; 42944961713Sgirish 43044961713Sgirish /* 43144961713Sgirish * Device descriptor access attributes for DMA. 43244961713Sgirish */ 43344961713Sgirish static ddi_device_acc_attr_t nxge_dev_desc_dma_acc_attr = { 43444961713Sgirish DDI_DEVICE_ATTR_V0, 43544961713Sgirish DDI_STRUCTURE_LE_ACC, 43644961713Sgirish DDI_STRICTORDER_ACC 43744961713Sgirish }; 43844961713Sgirish 43944961713Sgirish /* 44044961713Sgirish * Device buffer access attributes for DMA. 44144961713Sgirish */ 44244961713Sgirish static ddi_device_acc_attr_t nxge_dev_buf_dma_acc_attr = { 44344961713Sgirish DDI_DEVICE_ATTR_V0, 44444961713Sgirish DDI_STRUCTURE_BE_ACC, 44544961713Sgirish DDI_STRICTORDER_ACC 44644961713Sgirish }; 44744961713Sgirish 44844961713Sgirish ddi_dma_attr_t nxge_desc_dma_attr = { 44944961713Sgirish DMA_ATTR_V0, /* version number. */ 45044961713Sgirish 0, /* low address */ 45144961713Sgirish 0xffffffffffffffff, /* high address */ 45244961713Sgirish 0xffffffffffffffff, /* address counter max */ 45344961713Sgirish #ifndef NIU_PA_WORKAROUND 45444961713Sgirish 0x100000, /* alignment */ 45544961713Sgirish #else 45644961713Sgirish 0x2000, 45744961713Sgirish #endif 45844961713Sgirish 0xfc00fc, /* dlim_burstsizes */ 45944961713Sgirish 0x1, /* minimum transfer size */ 46044961713Sgirish 0xffffffffffffffff, /* maximum transfer size */ 46144961713Sgirish 0xffffffffffffffff, /* maximum segment size */ 46244961713Sgirish 1, /* scatter/gather list length */ 46344961713Sgirish (unsigned int) 1, /* granularity */ 46444961713Sgirish 0 /* attribute flags */ 46544961713Sgirish }; 46644961713Sgirish 46744961713Sgirish ddi_dma_attr_t nxge_tx_dma_attr = { 46844961713Sgirish DMA_ATTR_V0, /* version number. */ 46944961713Sgirish 0, /* low address */ 47044961713Sgirish 0xffffffffffffffff, /* high address */ 47144961713Sgirish 0xffffffffffffffff, /* address counter max */ 47244961713Sgirish #if defined(_BIG_ENDIAN) 47344961713Sgirish 0x2000, /* alignment */ 47444961713Sgirish #else 47544961713Sgirish 0x1000, /* alignment */ 47644961713Sgirish #endif 47744961713Sgirish 0xfc00fc, /* dlim_burstsizes */ 47844961713Sgirish 0x1, /* minimum transfer size */ 47944961713Sgirish 0xffffffffffffffff, /* maximum transfer size */ 48044961713Sgirish 0xffffffffffffffff, /* maximum segment size */ 48144961713Sgirish 5, /* scatter/gather list length */ 48244961713Sgirish (unsigned int) 1, /* granularity */ 48344961713Sgirish 0 /* attribute flags */ 48444961713Sgirish }; 48544961713Sgirish 48644961713Sgirish ddi_dma_attr_t nxge_rx_dma_attr = { 48744961713Sgirish DMA_ATTR_V0, /* version number. */ 48844961713Sgirish 0, /* low address */ 48944961713Sgirish 0xffffffffffffffff, /* high address */ 49044961713Sgirish 0xffffffffffffffff, /* address counter max */ 49144961713Sgirish 0x2000, /* alignment */ 49244961713Sgirish 0xfc00fc, /* dlim_burstsizes */ 49344961713Sgirish 0x1, /* minimum transfer size */ 49444961713Sgirish 0xffffffffffffffff, /* maximum transfer size */ 49544961713Sgirish 0xffffffffffffffff, /* maximum segment size */ 49644961713Sgirish 1, /* scatter/gather list length */ 49744961713Sgirish (unsigned int) 1, /* granularity */ 4980e2bd521Ssbehera DDI_DMA_RELAXED_ORDERING /* attribute flags */ 49944961713Sgirish }; 50044961713Sgirish 50144961713Sgirish ddi_dma_lim_t nxge_dma_limits = { 50244961713Sgirish (uint_t)0, /* dlim_addr_lo */ 50344961713Sgirish (uint_t)0xffffffff, /* dlim_addr_hi */ 50444961713Sgirish (uint_t)0xffffffff, /* dlim_cntr_max */ 50544961713Sgirish (uint_t)0xfc00fc, /* dlim_burstsizes for 32 and 64 bit xfers */ 50644961713Sgirish 0x1, /* dlim_minxfer */ 50744961713Sgirish 1024 /* dlim_speed */ 50844961713Sgirish }; 50944961713Sgirish 51044961713Sgirish dma_method_t nxge_force_dma = DVMA; 51144961713Sgirish 51244961713Sgirish /* 51344961713Sgirish * dma chunk sizes. 51444961713Sgirish * 51544961713Sgirish * Try to allocate the largest possible size 51644961713Sgirish * so that fewer number of dma chunks would be managed 51744961713Sgirish */ 51844961713Sgirish #ifdef NIU_PA_WORKAROUND 51944961713Sgirish size_t alloc_sizes [] = {0x2000}; 52044961713Sgirish #else 52144961713Sgirish size_t alloc_sizes [] = {0x1000, 0x2000, 0x4000, 0x8000, 52244961713Sgirish 0x10000, 0x20000, 0x40000, 0x80000, 52330ac2e7bSml 0x100000, 0x200000, 0x400000, 0x800000, 52430ac2e7bSml 0x1000000, 0x2000000, 0x4000000}; 52544961713Sgirish #endif 52644961713Sgirish 52744961713Sgirish /* 52844961713Sgirish * Translate "dev_t" to a pointer to the associated "dev_info_t". 52944961713Sgirish */ 53044961713Sgirish 531678453a8Sspeer extern void nxge_get_environs(nxge_t *); 532678453a8Sspeer 53344961713Sgirish static int 53444961713Sgirish nxge_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 53544961713Sgirish { 53644961713Sgirish p_nxge_t nxgep = NULL; 53744961713Sgirish int instance; 53844961713Sgirish int status = DDI_SUCCESS; 53944961713Sgirish uint8_t portn; 54058324dfcSspeer nxge_mmac_t *mmac_info; 54144961713Sgirish 54244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_attach")); 54344961713Sgirish 54444961713Sgirish /* 54544961713Sgirish * Get the device instance since we'll need to setup 54644961713Sgirish * or retrieve a soft state for this instance. 54744961713Sgirish */ 54844961713Sgirish instance = ddi_get_instance(dip); 54944961713Sgirish 55044961713Sgirish switch (cmd) { 55144961713Sgirish case DDI_ATTACH: 55244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_ATTACH")); 55344961713Sgirish break; 55444961713Sgirish 55544961713Sgirish case DDI_RESUME: 55644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_RESUME")); 55744961713Sgirish nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance); 55844961713Sgirish if (nxgep == NULL) { 55944961713Sgirish status = DDI_FAILURE; 56044961713Sgirish break; 56144961713Sgirish } 56244961713Sgirish if (nxgep->dip != dip) { 56344961713Sgirish status = DDI_FAILURE; 56444961713Sgirish break; 56544961713Sgirish } 56644961713Sgirish if (nxgep->suspended == DDI_PM_SUSPEND) { 56744961713Sgirish status = ddi_dev_is_needed(nxgep->dip, 0, 1); 56844961713Sgirish } else { 56956d930aeSspeer status = nxge_resume(nxgep); 57044961713Sgirish } 57144961713Sgirish goto nxge_attach_exit; 57244961713Sgirish 57344961713Sgirish case DDI_PM_RESUME: 57444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_PM_RESUME")); 57544961713Sgirish nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance); 57644961713Sgirish if (nxgep == NULL) { 57744961713Sgirish status = DDI_FAILURE; 57844961713Sgirish break; 57944961713Sgirish } 58044961713Sgirish if (nxgep->dip != dip) { 58144961713Sgirish status = DDI_FAILURE; 58244961713Sgirish break; 58344961713Sgirish } 58456d930aeSspeer status = nxge_resume(nxgep); 58544961713Sgirish goto nxge_attach_exit; 58644961713Sgirish 58744961713Sgirish default: 58844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing unknown")); 58944961713Sgirish status = DDI_FAILURE; 59044961713Sgirish goto nxge_attach_exit; 59144961713Sgirish } 59244961713Sgirish 59344961713Sgirish 59444961713Sgirish if (ddi_soft_state_zalloc(nxge_list, instance) == DDI_FAILURE) { 59544961713Sgirish status = DDI_FAILURE; 59644961713Sgirish goto nxge_attach_exit; 59744961713Sgirish } 59844961713Sgirish 59944961713Sgirish nxgep = ddi_get_soft_state(nxge_list, instance); 60044961713Sgirish if (nxgep == NULL) { 6012e59129aSraghus status = NXGE_ERROR; 6022e59129aSraghus goto nxge_attach_fail2; 60344961713Sgirish } 60444961713Sgirish 60598ecde52Stm nxgep->nxge_magic = NXGE_MAGIC; 60698ecde52Stm 60744961713Sgirish nxgep->drv_state = 0; 60844961713Sgirish nxgep->dip = dip; 60944961713Sgirish nxgep->instance = instance; 61044961713Sgirish nxgep->p_dip = ddi_get_parent(dip); 61144961713Sgirish nxgep->nxge_debug_level = nxge_debug_level; 61244961713Sgirish npi_debug_level = nxge_debug_level; 61344961713Sgirish 614678453a8Sspeer /* Are we a guest running in a Hybrid I/O environment? */ 615678453a8Sspeer nxge_get_environs(nxgep); 61644961713Sgirish 61744961713Sgirish status = nxge_map_regs(nxgep); 618678453a8Sspeer 61944961713Sgirish if (status != NXGE_OK) { 62044961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_map_regs failed")); 6212e59129aSraghus goto nxge_attach_fail3; 62244961713Sgirish } 62344961713Sgirish 624837c1ac4SStephen Hanson nxge_fm_init(nxgep, &nxge_dev_reg_acc_attr, &nxge_rx_dma_attr); 625678453a8Sspeer 626678453a8Sspeer /* Create & initialize the per-Neptune data structure */ 627678453a8Sspeer /* (even if we're a guest). */ 62844961713Sgirish status = nxge_init_common_dev(nxgep); 62944961713Sgirish if (status != NXGE_OK) { 63044961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6314045d941Ssowmini "nxge_init_common_dev failed")); 6322e59129aSraghus goto nxge_attach_fail4; 63344961713Sgirish } 63444961713Sgirish 635d6d3405fSml /* 636d6d3405fSml * Software workaround: set the replay timer. 637d6d3405fSml */ 638d6d3405fSml if (nxgep->niu_type != N2_NIU) { 639d6d3405fSml nxge_set_pci_replay_timeout(nxgep); 640d6d3405fSml } 641d6d3405fSml 642678453a8Sspeer #if defined(sun4v) 643678453a8Sspeer /* This is required by nxge_hio_init(), which follows. */ 644678453a8Sspeer if ((status = nxge_hsvc_register(nxgep)) != DDI_SUCCESS) 6459d5b8bc5SMichael Speer goto nxge_attach_fail4; 646678453a8Sspeer #endif 647678453a8Sspeer 648678453a8Sspeer if ((status = nxge_hio_init(nxgep)) != NXGE_OK) { 649678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6504045d941Ssowmini "nxge_hio_init failed")); 651678453a8Sspeer goto nxge_attach_fail4; 652678453a8Sspeer } 653678453a8Sspeer 65459ac0c16Sdavemq if (nxgep->niu_type == NEPTUNE_2_10GF) { 65559ac0c16Sdavemq if (nxgep->function_num > 1) { 6564202ea4bSsbehera NXGE_DEBUG_MSG((nxgep, DDI_CTL, "Unsupported" 65759ac0c16Sdavemq " function %d. Only functions 0 and 1 are " 65859ac0c16Sdavemq "supported for this card.", nxgep->function_num)); 65959ac0c16Sdavemq status = NXGE_ERROR; 6602e59129aSraghus goto nxge_attach_fail4; 66159ac0c16Sdavemq } 66259ac0c16Sdavemq } 66359ac0c16Sdavemq 664678453a8Sspeer if (isLDOMguest(nxgep)) { 665678453a8Sspeer /* 666678453a8Sspeer * Use the function number here. 667678453a8Sspeer */ 668678453a8Sspeer nxgep->mac.portnum = nxgep->function_num; 669678453a8Sspeer nxgep->mac.porttype = PORT_TYPE_LOGICAL; 670678453a8Sspeer 671678453a8Sspeer /* XXX We'll set the MAC address counts to 1 for now. */ 672678453a8Sspeer mmac_info = &nxgep->nxge_mmac_info; 673678453a8Sspeer mmac_info->num_mmac = 1; 674678453a8Sspeer mmac_info->naddrfree = 1; 67558324dfcSspeer } else { 676678453a8Sspeer portn = NXGE_GET_PORT_NUM(nxgep->function_num); 677678453a8Sspeer nxgep->mac.portnum = portn; 678678453a8Sspeer if ((portn == 0) || (portn == 1)) 679678453a8Sspeer nxgep->mac.porttype = PORT_TYPE_XMAC; 680678453a8Sspeer else 681678453a8Sspeer nxgep->mac.porttype = PORT_TYPE_BMAC; 682678453a8Sspeer /* 683678453a8Sspeer * Neptune has 4 ports, the first 2 ports use XMAC (10G MAC) 684678453a8Sspeer * internally, the rest 2 ports use BMAC (1G "Big" MAC). 685678453a8Sspeer * The two types of MACs have different characterizations. 686678453a8Sspeer */ 687678453a8Sspeer mmac_info = &nxgep->nxge_mmac_info; 688678453a8Sspeer if (nxgep->function_num < 2) { 689678453a8Sspeer mmac_info->num_mmac = XMAC_MAX_ALT_ADDR_ENTRY; 690678453a8Sspeer mmac_info->naddrfree = XMAC_MAX_ALT_ADDR_ENTRY; 691678453a8Sspeer } else { 692678453a8Sspeer mmac_info->num_mmac = BMAC_MAX_ALT_ADDR_ENTRY; 693678453a8Sspeer mmac_info->naddrfree = BMAC_MAX_ALT_ADDR_ENTRY; 694678453a8Sspeer } 69558324dfcSspeer } 69644961713Sgirish /* 69744961713Sgirish * Setup the Ndd parameters for the this instance. 69844961713Sgirish */ 69944961713Sgirish nxge_init_param(nxgep); 70044961713Sgirish 70144961713Sgirish /* 70244961713Sgirish * Setup Register Tracing Buffer. 70344961713Sgirish */ 70444961713Sgirish npi_rtrace_buf_init((rtrace_t *)&npi_rtracebuf); 70544961713Sgirish 70644961713Sgirish /* init stats ptr */ 70744961713Sgirish nxge_init_statsp(nxgep); 70856d930aeSspeer 7092e59129aSraghus /* 710678453a8Sspeer * Copy the vpd info from eeprom to a local data 711678453a8Sspeer * structure, and then check its validity. 7122e59129aSraghus */ 713678453a8Sspeer if (!isLDOMguest(nxgep)) { 714678453a8Sspeer int *regp; 715678453a8Sspeer uint_t reglen; 716678453a8Sspeer int rv; 71756d930aeSspeer 718678453a8Sspeer nxge_vpd_info_get(nxgep); 71944961713Sgirish 720678453a8Sspeer /* Find the NIU config handle. */ 721678453a8Sspeer rv = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, 722678453a8Sspeer ddi_get_parent(nxgep->dip), DDI_PROP_DONTPASS, 723678453a8Sspeer "reg", ®p, ®len); 724678453a8Sspeer 725678453a8Sspeer if (rv != DDI_PROP_SUCCESS) { 726678453a8Sspeer goto nxge_attach_fail5; 727678453a8Sspeer } 728678453a8Sspeer /* 729678453a8Sspeer * The address_hi, that is the first int, in the reg 730678453a8Sspeer * property consists of config handle, but need to remove 731678453a8Sspeer * the bits 28-31 which are OBP specific info. 732678453a8Sspeer */ 733678453a8Sspeer nxgep->niu_cfg_hdl = (*regp) & 0xFFFFFFF; 734678453a8Sspeer ddi_prop_free(regp); 73544961713Sgirish } 73644961713Sgirish 73748056c53SMichael Speer /* 73848056c53SMichael Speer * Set the defaults for the MTU size. 73948056c53SMichael Speer */ 74048056c53SMichael Speer nxge_hw_id_init(nxgep); 74148056c53SMichael Speer 742678453a8Sspeer if (isLDOMguest(nxgep)) { 743678453a8Sspeer uchar_t *prop_val; 744678453a8Sspeer uint_t prop_len; 7457b1f684aSSriharsha Basavapatna uint32_t max_frame_size; 74644961713Sgirish 747678453a8Sspeer extern void nxge_get_logical_props(p_nxge_t); 748678453a8Sspeer 749678453a8Sspeer nxgep->statsp->mac_stats.xcvr_inuse = LOGICAL_XCVR; 750678453a8Sspeer nxgep->mac.portmode = PORT_LOGICAL; 751678453a8Sspeer (void) ddi_prop_update_string(DDI_DEV_T_NONE, nxgep->dip, 752678453a8Sspeer "phy-type", "virtual transceiver"); 753678453a8Sspeer 754678453a8Sspeer nxgep->nports = 1; 755678453a8Sspeer nxgep->board_ver = 0; /* XXX What? */ 756678453a8Sspeer 757678453a8Sspeer /* 758678453a8Sspeer * local-mac-address property gives us info on which 759678453a8Sspeer * specific MAC address the Hybrid resource is associated 760678453a8Sspeer * with. 761678453a8Sspeer */ 762678453a8Sspeer if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0, 763678453a8Sspeer "local-mac-address", &prop_val, 764678453a8Sspeer &prop_len) != DDI_PROP_SUCCESS) { 765678453a8Sspeer goto nxge_attach_fail5; 766678453a8Sspeer } 767678453a8Sspeer if (prop_len != ETHERADDRL) { 768678453a8Sspeer ddi_prop_free(prop_val); 769678453a8Sspeer goto nxge_attach_fail5; 770678453a8Sspeer } 771678453a8Sspeer ether_copy(prop_val, nxgep->hio_mac_addr); 772678453a8Sspeer ddi_prop_free(prop_val); 773678453a8Sspeer nxge_get_logical_props(nxgep); 774678453a8Sspeer 7757b1f684aSSriharsha Basavapatna /* 7767b1f684aSSriharsha Basavapatna * Enable Jumbo property based on the "max-frame-size" 7777b1f684aSSriharsha Basavapatna * property value. 7787b1f684aSSriharsha Basavapatna */ 7797b1f684aSSriharsha Basavapatna max_frame_size = ddi_prop_get_int(DDI_DEV_T_ANY, 7807b1f684aSSriharsha Basavapatna nxgep->dip, DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, 7817b1f684aSSriharsha Basavapatna "max-frame-size", NXGE_MTU_DEFAULT_MAX); 7827b1f684aSSriharsha Basavapatna if ((max_frame_size > NXGE_MTU_DEFAULT_MAX) && 7837b1f684aSSriharsha Basavapatna (max_frame_size <= TX_JUMBO_MTU)) { 7847b1f684aSSriharsha Basavapatna nxgep->mac.is_jumbo = B_TRUE; 7857b1f684aSSriharsha Basavapatna nxgep->mac.maxframesize = (uint16_t)max_frame_size; 7867b1f684aSSriharsha Basavapatna nxgep->mac.default_mtu = nxgep->mac.maxframesize - 7877b1f684aSSriharsha Basavapatna NXGE_EHEADER_VLAN_CRC; 7887b1f684aSSriharsha Basavapatna } 789678453a8Sspeer } else { 790678453a8Sspeer status = nxge_xcvr_find(nxgep); 791678453a8Sspeer 792678453a8Sspeer if (status != NXGE_OK) { 793678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_attach: " 7944045d941Ssowmini " Couldn't determine card type" 7954045d941Ssowmini " .... exit ")); 796678453a8Sspeer goto nxge_attach_fail5; 797678453a8Sspeer } 798678453a8Sspeer 799678453a8Sspeer status = nxge_get_config_properties(nxgep); 800678453a8Sspeer 801678453a8Sspeer if (status != NXGE_OK) { 802678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 8034045d941Ssowmini "get_hw create failed")); 804678453a8Sspeer goto nxge_attach_fail; 805678453a8Sspeer } 80644961713Sgirish } 80744961713Sgirish 80844961713Sgirish /* 80944961713Sgirish * Setup the Kstats for the driver. 81044961713Sgirish */ 81144961713Sgirish nxge_setup_kstats(nxgep); 81244961713Sgirish 813678453a8Sspeer if (!isLDOMguest(nxgep)) 814678453a8Sspeer nxge_setup_param(nxgep); 81544961713Sgirish 81644961713Sgirish status = nxge_setup_system_dma_pages(nxgep); 81744961713Sgirish if (status != NXGE_OK) { 81844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "set dma page failed")); 81944961713Sgirish goto nxge_attach_fail; 82044961713Sgirish } 82144961713Sgirish 822678453a8Sspeer 823678453a8Sspeer if (!isLDOMguest(nxgep)) 824678453a8Sspeer nxge_hw_init_niu_common(nxgep); 82544961713Sgirish 82644961713Sgirish status = nxge_setup_mutexes(nxgep); 82744961713Sgirish if (status != NXGE_OK) { 82844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "set mutex failed")); 82944961713Sgirish goto nxge_attach_fail; 83044961713Sgirish } 83144961713Sgirish 832678453a8Sspeer #if defined(sun4v) 833678453a8Sspeer if (isLDOMguest(nxgep)) { 834678453a8Sspeer /* Find our VR & channel sets. */ 835678453a8Sspeer status = nxge_hio_vr_add(nxgep); 836ef523517SMichael Speer if (status != DDI_SUCCESS) { 837ef523517SMichael Speer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 838330cd344SMichael Speer "nxge_hio_vr_add failed")); 839330cd344SMichael Speer (void) hsvc_unregister(&nxgep->niu_hsvc); 840330cd344SMichael Speer nxgep->niu_hsvc_available = B_FALSE; 841ef523517SMichael Speer goto nxge_attach_fail; 842330cd344SMichael Speer } 843678453a8Sspeer goto nxge_attach_exit; 844678453a8Sspeer } 845678453a8Sspeer #endif 846678453a8Sspeer 84744961713Sgirish status = nxge_setup_dev(nxgep); 84844961713Sgirish if (status != DDI_SUCCESS) { 84944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "set dev failed")); 85044961713Sgirish goto nxge_attach_fail; 85144961713Sgirish } 85244961713Sgirish 85344961713Sgirish status = nxge_add_intrs(nxgep); 85444961713Sgirish if (status != DDI_SUCCESS) { 85544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "add_intr failed")); 85644961713Sgirish goto nxge_attach_fail; 85744961713Sgirish } 858330cd344SMichael Speer 85900161856Syc /* If a guest, register with vio_net instead. */ 8602e59129aSraghus if ((status = nxge_mac_register(nxgep)) != NXGE_OK) { 86144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 862678453a8Sspeer "unable to register to mac layer (%d)", status)); 86344961713Sgirish goto nxge_attach_fail; 86444961713Sgirish } 86544961713Sgirish 86644961713Sgirish mac_link_update(nxgep->mach, LINK_STATE_UNKNOWN); 86744961713Sgirish 868678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DDI_CTL, 869678453a8Sspeer "registered to mac (instance %d)", instance)); 87044961713Sgirish 87100161856Syc /* nxge_link_monitor calls xcvr.check_link recursively */ 87244961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 87344961713Sgirish 87444961713Sgirish goto nxge_attach_exit; 87544961713Sgirish 87644961713Sgirish nxge_attach_fail: 87744961713Sgirish nxge_unattach(nxgep); 8782e59129aSraghus goto nxge_attach_fail1; 8792e59129aSraghus 8802e59129aSraghus nxge_attach_fail5: 8812e59129aSraghus /* 8822e59129aSraghus * Tear down the ndd parameters setup. 8832e59129aSraghus */ 8842e59129aSraghus nxge_destroy_param(nxgep); 8852e59129aSraghus 8862e59129aSraghus /* 8872e59129aSraghus * Tear down the kstat setup. 8882e59129aSraghus */ 8892e59129aSraghus nxge_destroy_kstats(nxgep); 8902e59129aSraghus 8912e59129aSraghus nxge_attach_fail4: 8922e59129aSraghus if (nxgep->nxge_hw_p) { 8932e59129aSraghus nxge_uninit_common_dev(nxgep); 8942e59129aSraghus nxgep->nxge_hw_p = NULL; 8952e59129aSraghus } 8962e59129aSraghus 8972e59129aSraghus nxge_attach_fail3: 8982e59129aSraghus /* 8992e59129aSraghus * Unmap the register setup. 9002e59129aSraghus */ 9012e59129aSraghus nxge_unmap_regs(nxgep); 9022e59129aSraghus 9032e59129aSraghus nxge_fm_fini(nxgep); 9042e59129aSraghus 9052e59129aSraghus nxge_attach_fail2: 9062e59129aSraghus ddi_soft_state_free(nxge_list, nxgep->instance); 9072e59129aSraghus 9082e59129aSraghus nxge_attach_fail1: 90956d930aeSspeer if (status != NXGE_OK) 91056d930aeSspeer status = (NXGE_ERROR | NXGE_DDI_FAILED); 91144961713Sgirish nxgep = NULL; 91244961713Sgirish 91344961713Sgirish nxge_attach_exit: 91444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_attach status = 0x%08x", 9154045d941Ssowmini status)); 91644961713Sgirish 91744961713Sgirish return (status); 91844961713Sgirish } 91944961713Sgirish 92044961713Sgirish static int 92144961713Sgirish nxge_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 92244961713Sgirish { 92344961713Sgirish int status = DDI_SUCCESS; 92444961713Sgirish int instance; 92544961713Sgirish p_nxge_t nxgep = NULL; 92644961713Sgirish 92744961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_detach")); 92844961713Sgirish instance = ddi_get_instance(dip); 92944961713Sgirish nxgep = ddi_get_soft_state(nxge_list, instance); 93044961713Sgirish if (nxgep == NULL) { 93144961713Sgirish status = DDI_FAILURE; 93244961713Sgirish goto nxge_detach_exit; 93344961713Sgirish } 93444961713Sgirish 93544961713Sgirish switch (cmd) { 93644961713Sgirish case DDI_DETACH: 93744961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_DETACH")); 93844961713Sgirish break; 93944961713Sgirish 94044961713Sgirish case DDI_PM_SUSPEND: 94144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_PM_SUSPEND")); 94244961713Sgirish nxgep->suspended = DDI_PM_SUSPEND; 94344961713Sgirish nxge_suspend(nxgep); 94444961713Sgirish break; 94544961713Sgirish 94644961713Sgirish case DDI_SUSPEND: 94744961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_SUSPEND")); 94844961713Sgirish if (nxgep->suspended != DDI_PM_SUSPEND) { 94944961713Sgirish nxgep->suspended = DDI_SUSPEND; 95044961713Sgirish nxge_suspend(nxgep); 95144961713Sgirish } 95244961713Sgirish break; 95344961713Sgirish 95444961713Sgirish default: 95544961713Sgirish status = DDI_FAILURE; 95644961713Sgirish } 95744961713Sgirish 95844961713Sgirish if (cmd != DDI_DETACH) 95944961713Sgirish goto nxge_detach_exit; 96044961713Sgirish 96144961713Sgirish /* 96244961713Sgirish * Stop the xcvr polling. 96344961713Sgirish */ 96444961713Sgirish nxgep->suspended = cmd; 96544961713Sgirish 96644961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 96744961713Sgirish 96863f531d1SSriharsha Basavapatna if (nxgep->mach && (status = mac_unregister(nxgep->mach)) != 0) { 96944961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 9704045d941Ssowmini "<== nxge_detach status = 0x%08X", status)); 97144961713Sgirish return (DDI_FAILURE); 97244961713Sgirish } 97344961713Sgirish 97444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 9754045d941Ssowmini "<== nxge_detach (mac_unregister) status = 0x%08X", status)); 97644961713Sgirish 97744961713Sgirish nxge_unattach(nxgep); 97844961713Sgirish nxgep = NULL; 97944961713Sgirish 98044961713Sgirish nxge_detach_exit: 98144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_detach status = 0x%08X", 9824045d941Ssowmini status)); 98344961713Sgirish 98444961713Sgirish return (status); 98544961713Sgirish } 98644961713Sgirish 98744961713Sgirish static void 98844961713Sgirish nxge_unattach(p_nxge_t nxgep) 98944961713Sgirish { 99044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_unattach")); 99144961713Sgirish 99244961713Sgirish if (nxgep == NULL || nxgep->dev_regs == NULL) { 99344961713Sgirish return; 99444961713Sgirish } 99544961713Sgirish 99698ecde52Stm nxgep->nxge_magic = 0; 99798ecde52Stm 99844961713Sgirish if (nxgep->nxge_timerid) { 99944961713Sgirish nxge_stop_timer(nxgep, nxgep->nxge_timerid); 100044961713Sgirish nxgep->nxge_timerid = 0; 100144961713Sgirish } 100244961713Sgirish 10036f157acbSml /* 10046f157acbSml * If this flag is set, it will affect the Neptune 10056f157acbSml * only. 10066f157acbSml */ 10076f157acbSml if ((nxgep->niu_type != N2_NIU) && nxge_peu_reset_enable) { 10086f157acbSml nxge_niu_peu_reset(nxgep); 10096f157acbSml } 10106f157acbSml 1011678453a8Sspeer #if defined(sun4v) 1012678453a8Sspeer if (isLDOMguest(nxgep)) { 1013d00f30bbSspeer (void) nxge_hio_vr_release(nxgep); 1014678453a8Sspeer } 1015678453a8Sspeer #endif 1016678453a8Sspeer 101753560810Ssbehera if (nxgep->nxge_hw_p) { 101853560810Ssbehera nxge_uninit_common_dev(nxgep); 101953560810Ssbehera nxgep->nxge_hw_p = NULL; 102053560810Ssbehera } 102153560810Ssbehera 102244961713Sgirish #if defined(sun4v) 102344961713Sgirish if (nxgep->niu_type == N2_NIU && nxgep->niu_hsvc_available == B_TRUE) { 102444961713Sgirish (void) hsvc_unregister(&nxgep->niu_hsvc); 102544961713Sgirish nxgep->niu_hsvc_available = B_FALSE; 102644961713Sgirish } 102744961713Sgirish #endif 102844961713Sgirish /* 102944961713Sgirish * Stop any further interrupts. 103044961713Sgirish */ 103144961713Sgirish nxge_remove_intrs(nxgep); 103244961713Sgirish 103344961713Sgirish /* 103444961713Sgirish * Stop the device and free resources. 103544961713Sgirish */ 1036678453a8Sspeer if (!isLDOMguest(nxgep)) { 1037678453a8Sspeer nxge_destroy_dev(nxgep); 1038678453a8Sspeer } 103944961713Sgirish 104044961713Sgirish /* 104144961713Sgirish * Tear down the ndd parameters setup. 104244961713Sgirish */ 104344961713Sgirish nxge_destroy_param(nxgep); 104444961713Sgirish 104544961713Sgirish /* 104644961713Sgirish * Tear down the kstat setup. 104744961713Sgirish */ 104844961713Sgirish nxge_destroy_kstats(nxgep); 104944961713Sgirish 105044961713Sgirish /* 105144961713Sgirish * Destroy all mutexes. 105244961713Sgirish */ 105344961713Sgirish nxge_destroy_mutexes(nxgep); 105444961713Sgirish 105544961713Sgirish /* 105644961713Sgirish * Remove the list of ndd parameters which 105744961713Sgirish * were setup during attach. 105844961713Sgirish */ 105944961713Sgirish if (nxgep->dip) { 106044961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL, 10614045d941Ssowmini " nxge_unattach: remove all properties")); 106244961713Sgirish 106344961713Sgirish (void) ddi_prop_remove_all(nxgep->dip); 106444961713Sgirish } 106544961713Sgirish 106644961713Sgirish #if NXGE_PROPERTY 106744961713Sgirish nxge_remove_hard_properties(nxgep); 106844961713Sgirish #endif 106944961713Sgirish 107044961713Sgirish /* 107144961713Sgirish * Unmap the register setup. 107244961713Sgirish */ 107344961713Sgirish nxge_unmap_regs(nxgep); 107444961713Sgirish 107544961713Sgirish nxge_fm_fini(nxgep); 107644961713Sgirish 107744961713Sgirish ddi_soft_state_free(nxge_list, nxgep->instance); 107844961713Sgirish 107944961713Sgirish NXGE_DEBUG_MSG((NULL, DDI_CTL, "<== nxge_unattach")); 108044961713Sgirish } 108144961713Sgirish 1082678453a8Sspeer #if defined(sun4v) 1083678453a8Sspeer int 10849d5b8bc5SMichael Speer nxge_hsvc_register(nxge_t *nxgep) 1085678453a8Sspeer { 1086678453a8Sspeer nxge_status_t status; 1087*4df55fdeSJanie Lu int i, j; 1088678453a8Sspeer 1089*4df55fdeSJanie Lu NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hsvc_register")); 1090*4df55fdeSJanie Lu if (nxgep->niu_type != N2_NIU) { 1091*4df55fdeSJanie Lu NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hsvc_register")); 1092*4df55fdeSJanie Lu return (DDI_SUCCESS); 1093678453a8Sspeer } 1094678453a8Sspeer 1095*4df55fdeSJanie Lu /* 1096*4df55fdeSJanie Lu * Currently, the NIU Hypervisor API supports two major versions: 1097*4df55fdeSJanie Lu * version 1 and 2. 1098*4df55fdeSJanie Lu * If Hypervisor introduces a higher major or minor version, 1099*4df55fdeSJanie Lu * please update NIU_MAJOR_HI and NIU_MINOR_HI accordingly. 1100*4df55fdeSJanie Lu */ 1101*4df55fdeSJanie Lu nxgep->niu_hsvc_available = B_FALSE; 1102*4df55fdeSJanie Lu bcopy(&niu_hsvc, &nxgep->niu_hsvc, 1103*4df55fdeSJanie Lu sizeof (hsvc_info_t)); 1104*4df55fdeSJanie Lu 1105*4df55fdeSJanie Lu for (i = NIU_MAJOR_HI; i > 0; i--) { 1106*4df55fdeSJanie Lu nxgep->niu_hsvc.hsvc_major = i; 1107*4df55fdeSJanie Lu for (j = NIU_MINOR_HI; j >= 0; j--) { 1108*4df55fdeSJanie Lu nxgep->niu_hsvc.hsvc_minor = j; 1109*4df55fdeSJanie Lu NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1110*4df55fdeSJanie Lu "nxge_hsvc_register: %s: negotiating " 1111*4df55fdeSJanie Lu "hypervisor services revision %d " 1112*4df55fdeSJanie Lu "group: 0x%lx major: 0x%lx " 1113*4df55fdeSJanie Lu "minor: 0x%lx", 1114*4df55fdeSJanie Lu nxgep->niu_hsvc.hsvc_modname, 1115*4df55fdeSJanie Lu nxgep->niu_hsvc.hsvc_rev, 1116*4df55fdeSJanie Lu nxgep->niu_hsvc.hsvc_group, 1117*4df55fdeSJanie Lu nxgep->niu_hsvc.hsvc_major, 1118*4df55fdeSJanie Lu nxgep->niu_hsvc.hsvc_minor, 1119*4df55fdeSJanie Lu nxgep->niu_min_ver)); 1120*4df55fdeSJanie Lu 1121*4df55fdeSJanie Lu if ((status = hsvc_register(&nxgep->niu_hsvc, 1122*4df55fdeSJanie Lu &nxgep->niu_min_ver)) == 0) { 1123*4df55fdeSJanie Lu /* Use the supported minor */ 1124*4df55fdeSJanie Lu nxgep->niu_hsvc.hsvc_minor = nxgep->niu_min_ver; 1125*4df55fdeSJanie Lu NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1126*4df55fdeSJanie Lu "nxge_hsvc_register: %s: negotiated " 1127*4df55fdeSJanie Lu "hypervisor services revision %d " 1128*4df55fdeSJanie Lu "group: 0x%lx major: 0x%lx " 1129*4df55fdeSJanie Lu "minor: 0x%lx (niu_min_ver 0x%lx)", 1130*4df55fdeSJanie Lu nxgep->niu_hsvc.hsvc_modname, 1131*4df55fdeSJanie Lu nxgep->niu_hsvc.hsvc_rev, 1132*4df55fdeSJanie Lu nxgep->niu_hsvc.hsvc_group, 1133*4df55fdeSJanie Lu nxgep->niu_hsvc.hsvc_major, 1134*4df55fdeSJanie Lu nxgep->niu_hsvc.hsvc_minor, 1135*4df55fdeSJanie Lu nxgep->niu_min_ver)); 1136*4df55fdeSJanie Lu 1137*4df55fdeSJanie Lu nxgep->niu_hsvc_available = B_TRUE; 1138*4df55fdeSJanie Lu NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1139*4df55fdeSJanie Lu "<== nxge_hsvc_register: " 1140*4df55fdeSJanie Lu "NIU Hypervisor service enabled")); 1141*4df55fdeSJanie Lu return (DDI_SUCCESS); 1142*4df55fdeSJanie Lu } 1143*4df55fdeSJanie Lu 1144*4df55fdeSJanie Lu NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1145*4df55fdeSJanie Lu "nxge_hsvc_register: %s: negotiated failed - " 1146*4df55fdeSJanie Lu "try lower major number " 1147*4df55fdeSJanie Lu "hypervisor services revision %d " 1148*4df55fdeSJanie Lu "group: 0x%lx major: 0x%lx minor: 0x%lx " 1149*4df55fdeSJanie Lu "errno: %d", 1150*4df55fdeSJanie Lu nxgep->niu_hsvc.hsvc_modname, 1151*4df55fdeSJanie Lu nxgep->niu_hsvc.hsvc_rev, 1152*4df55fdeSJanie Lu nxgep->niu_hsvc.hsvc_group, 1153*4df55fdeSJanie Lu nxgep->niu_hsvc.hsvc_major, 1154*4df55fdeSJanie Lu nxgep->niu_hsvc.hsvc_minor, status)); 1155*4df55fdeSJanie Lu } 1156*4df55fdeSJanie Lu } 1157*4df55fdeSJanie Lu 1158*4df55fdeSJanie Lu NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1159*4df55fdeSJanie Lu "nxge_hsvc_register: %s: cannot negotiate " 1160*4df55fdeSJanie Lu "hypervisor services revision %d group: 0x%lx " 1161*4df55fdeSJanie Lu "major: 0x%lx minor: 0x%lx errno: %d", 1162*4df55fdeSJanie Lu niu_hsvc.hsvc_modname, niu_hsvc.hsvc_rev, 1163*4df55fdeSJanie Lu niu_hsvc.hsvc_group, niu_hsvc.hsvc_major, 1164*4df55fdeSJanie Lu niu_hsvc.hsvc_minor, status)); 1165*4df55fdeSJanie Lu 1166*4df55fdeSJanie Lu NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1167*4df55fdeSJanie Lu "<== nxge_hsvc_register: Register to NIU Hypervisor failed")); 1168*4df55fdeSJanie Lu 1169*4df55fdeSJanie Lu return (DDI_FAILURE); 1170678453a8Sspeer } 1171678453a8Sspeer #endif 1172678453a8Sspeer 117344961713Sgirish static char n2_siu_name[] = "niu"; 117444961713Sgirish 117544961713Sgirish static nxge_status_t 117644961713Sgirish nxge_map_regs(p_nxge_t nxgep) 117744961713Sgirish { 117844961713Sgirish int ddi_status = DDI_SUCCESS; 117944961713Sgirish p_dev_regs_t dev_regs; 118044961713Sgirish char buf[MAXPATHLEN + 1]; 118144961713Sgirish char *devname; 118244961713Sgirish #ifdef NXGE_DEBUG 118344961713Sgirish char *sysname; 118444961713Sgirish #endif 118544961713Sgirish off_t regsize; 118644961713Sgirish nxge_status_t status = NXGE_OK; 118714ea4bb7Ssd #if !defined(_BIG_ENDIAN) 118814ea4bb7Ssd off_t pci_offset; 118914ea4bb7Ssd uint16_t pcie_devctl; 119014ea4bb7Ssd #endif 119144961713Sgirish 1192678453a8Sspeer if (isLDOMguest(nxgep)) { 1193678453a8Sspeer return (nxge_guest_regs_map(nxgep)); 1194678453a8Sspeer } 1195678453a8Sspeer 119644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_map_regs")); 119744961713Sgirish nxgep->dev_regs = NULL; 119844961713Sgirish dev_regs = KMEM_ZALLOC(sizeof (dev_regs_t), KM_SLEEP); 119944961713Sgirish dev_regs->nxge_regh = NULL; 120044961713Sgirish dev_regs->nxge_pciregh = NULL; 120144961713Sgirish dev_regs->nxge_msix_regh = NULL; 120244961713Sgirish dev_regs->nxge_vir_regh = NULL; 120344961713Sgirish dev_regs->nxge_vir2_regh = NULL; 120459ac0c16Sdavemq nxgep->niu_type = NIU_TYPE_NONE; 120544961713Sgirish 120644961713Sgirish devname = ddi_pathname(nxgep->dip, buf); 120744961713Sgirish ASSERT(strlen(devname) > 0); 120844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 12094045d941Ssowmini "nxge_map_regs: pathname devname %s", devname)); 121044961713Sgirish 121100161856Syc /* 121200161856Syc * The driver is running on a N2-NIU system if devname is something 121300161856Syc * like "/niu@80/network@0" 121400161856Syc */ 121544961713Sgirish if (strstr(devname, n2_siu_name)) { 121644961713Sgirish /* N2/NIU */ 121744961713Sgirish nxgep->niu_type = N2_NIU; 121844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 12194045d941Ssowmini "nxge_map_regs: N2/NIU devname %s", devname)); 1220*4df55fdeSJanie Lu /* 1221*4df55fdeSJanie Lu * Get function number: 1222*4df55fdeSJanie Lu * - N2/NIU: "/niu@80/network@0" and "/niu@80/network@1" 1223*4df55fdeSJanie Lu */ 122444961713Sgirish nxgep->function_num = 12254045d941Ssowmini (devname[strlen(devname) -1] == '1' ? 1 : 0); 122644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 12274045d941Ssowmini "nxge_map_regs: N2/NIU function number %d", 12284045d941Ssowmini nxgep->function_num)); 122944961713Sgirish } else { 123044961713Sgirish int *prop_val; 123144961713Sgirish uint_t prop_len; 123244961713Sgirish uint8_t func_num; 123344961713Sgirish 123444961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 12354045d941Ssowmini 0, "reg", 12364045d941Ssowmini &prop_val, &prop_len) != DDI_PROP_SUCCESS) { 123744961713Sgirish NXGE_DEBUG_MSG((nxgep, VPD_CTL, 12384045d941Ssowmini "Reg property not found")); 123944961713Sgirish ddi_status = DDI_FAILURE; 124044961713Sgirish goto nxge_map_regs_fail0; 124144961713Sgirish 124244961713Sgirish } else { 124344961713Sgirish func_num = (prop_val[0] >> 8) & 0x7; 124444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 12454045d941Ssowmini "Reg property found: fun # %d", 12464045d941Ssowmini func_num)); 124744961713Sgirish nxgep->function_num = func_num; 1248678453a8Sspeer if (isLDOMguest(nxgep)) { 1249678453a8Sspeer nxgep->function_num /= 2; 1250678453a8Sspeer return (NXGE_OK); 1251678453a8Sspeer } 125244961713Sgirish ddi_prop_free(prop_val); 125344961713Sgirish } 125444961713Sgirish } 125544961713Sgirish 125644961713Sgirish switch (nxgep->niu_type) { 125744961713Sgirish default: 125844961713Sgirish (void) ddi_dev_regsize(nxgep->dip, 0, ®size); 125944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 12604045d941Ssowmini "nxge_map_regs: pci config size 0x%x", regsize)); 126144961713Sgirish 126244961713Sgirish ddi_status = ddi_regs_map_setup(nxgep->dip, 0, 12634045d941Ssowmini (caddr_t *)&(dev_regs->nxge_pciregp), 0, 0, 12644045d941Ssowmini &nxge_dev_reg_acc_attr, &dev_regs->nxge_pciregh); 126544961713Sgirish if (ddi_status != DDI_SUCCESS) { 126644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 12674045d941Ssowmini "ddi_map_regs, nxge bus config regs failed")); 126844961713Sgirish goto nxge_map_regs_fail0; 126944961713Sgirish } 127044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 12714045d941Ssowmini "nxge_map_reg: PCI config addr 0x%0llx " 12724045d941Ssowmini " handle 0x%0llx", dev_regs->nxge_pciregp, 12734045d941Ssowmini dev_regs->nxge_pciregh)); 127444961713Sgirish /* 127544961713Sgirish * IMP IMP 127644961713Sgirish * workaround for bit swapping bug in HW 127744961713Sgirish * which ends up in no-snoop = yes 127844961713Sgirish * resulting, in DMA not synched properly 127944961713Sgirish */ 128044961713Sgirish #if !defined(_BIG_ENDIAN) 128114ea4bb7Ssd /* workarounds for x86 systems */ 128214ea4bb7Ssd pci_offset = 0x80 + PCIE_DEVCTL; 128348056c53SMichael Speer pcie_devctl = pci_config_get16(dev_regs->nxge_pciregh, 128448056c53SMichael Speer pci_offset); 128548056c53SMichael Speer pcie_devctl &= ~PCIE_DEVCTL_ENABLE_NO_SNOOP; 128614ea4bb7Ssd pcie_devctl |= PCIE_DEVCTL_RO_EN; 128714ea4bb7Ssd pci_config_put16(dev_regs->nxge_pciregh, pci_offset, 12884045d941Ssowmini pcie_devctl); 128944961713Sgirish #endif 129014ea4bb7Ssd 129144961713Sgirish (void) ddi_dev_regsize(nxgep->dip, 1, ®size); 129244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 12934045d941Ssowmini "nxge_map_regs: pio size 0x%x", regsize)); 129444961713Sgirish /* set up the device mapped register */ 129544961713Sgirish ddi_status = ddi_regs_map_setup(nxgep->dip, 1, 12964045d941Ssowmini (caddr_t *)&(dev_regs->nxge_regp), 0, 0, 12974045d941Ssowmini &nxge_dev_reg_acc_attr, &dev_regs->nxge_regh); 129844961713Sgirish if (ddi_status != DDI_SUCCESS) { 129944961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 13004045d941Ssowmini "ddi_map_regs for Neptune global reg failed")); 130144961713Sgirish goto nxge_map_regs_fail1; 130244961713Sgirish } 130344961713Sgirish 130444961713Sgirish /* set up the msi/msi-x mapped register */ 130544961713Sgirish (void) ddi_dev_regsize(nxgep->dip, 2, ®size); 130644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 13074045d941Ssowmini "nxge_map_regs: msix size 0x%x", regsize)); 130844961713Sgirish ddi_status = ddi_regs_map_setup(nxgep->dip, 2, 13094045d941Ssowmini (caddr_t *)&(dev_regs->nxge_msix_regp), 0, 0, 13104045d941Ssowmini &nxge_dev_reg_acc_attr, &dev_regs->nxge_msix_regh); 131144961713Sgirish if (ddi_status != DDI_SUCCESS) { 131244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 13134045d941Ssowmini "ddi_map_regs for msi reg failed")); 131444961713Sgirish goto nxge_map_regs_fail2; 131544961713Sgirish } 131644961713Sgirish 131744961713Sgirish /* set up the vio region mapped register */ 131844961713Sgirish (void) ddi_dev_regsize(nxgep->dip, 3, ®size); 131944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 13204045d941Ssowmini "nxge_map_regs: vio size 0x%x", regsize)); 132144961713Sgirish ddi_status = ddi_regs_map_setup(nxgep->dip, 3, 13224045d941Ssowmini (caddr_t *)&(dev_regs->nxge_vir_regp), 0, 0, 13234045d941Ssowmini &nxge_dev_reg_acc_attr, &dev_regs->nxge_vir_regh); 132444961713Sgirish 132544961713Sgirish if (ddi_status != DDI_SUCCESS) { 132644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 13274045d941Ssowmini "ddi_map_regs for nxge vio reg failed")); 132844961713Sgirish goto nxge_map_regs_fail3; 132944961713Sgirish } 133044961713Sgirish nxgep->dev_regs = dev_regs; 133144961713Sgirish 133244961713Sgirish NPI_PCI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_pciregh); 133344961713Sgirish NPI_PCI_ADD_HANDLE_SET(nxgep, 13344045d941Ssowmini (npi_reg_ptr_t)dev_regs->nxge_pciregp); 133544961713Sgirish NPI_MSI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_msix_regh); 133644961713Sgirish NPI_MSI_ADD_HANDLE_SET(nxgep, 13374045d941Ssowmini (npi_reg_ptr_t)dev_regs->nxge_msix_regp); 133844961713Sgirish 133944961713Sgirish NPI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh); 134044961713Sgirish NPI_ADD_HANDLE_SET(nxgep, (npi_reg_ptr_t)dev_regs->nxge_regp); 134144961713Sgirish 134244961713Sgirish NPI_REG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh); 134344961713Sgirish NPI_REG_ADD_HANDLE_SET(nxgep, 13444045d941Ssowmini (npi_reg_ptr_t)dev_regs->nxge_regp); 134544961713Sgirish 134644961713Sgirish NPI_VREG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_vir_regh); 134744961713Sgirish NPI_VREG_ADD_HANDLE_SET(nxgep, 13484045d941Ssowmini (npi_reg_ptr_t)dev_regs->nxge_vir_regp); 134944961713Sgirish 135044961713Sgirish break; 135144961713Sgirish 135244961713Sgirish case N2_NIU: 135344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "ddi_map_regs, NIU")); 135444961713Sgirish /* 135544961713Sgirish * Set up the device mapped register (FWARC 2006/556) 135644961713Sgirish * (changed back to 1: reg starts at 1!) 135744961713Sgirish */ 135844961713Sgirish (void) ddi_dev_regsize(nxgep->dip, 1, ®size); 135944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 13604045d941Ssowmini "nxge_map_regs: dev size 0x%x", regsize)); 136144961713Sgirish ddi_status = ddi_regs_map_setup(nxgep->dip, 1, 13624045d941Ssowmini (caddr_t *)&(dev_regs->nxge_regp), 0, 0, 13634045d941Ssowmini &nxge_dev_reg_acc_attr, &dev_regs->nxge_regh); 136444961713Sgirish 136544961713Sgirish if (ddi_status != DDI_SUCCESS) { 136644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 13674045d941Ssowmini "ddi_map_regs for N2/NIU, global reg failed ")); 136844961713Sgirish goto nxge_map_regs_fail1; 136944961713Sgirish } 137044961713Sgirish 1371678453a8Sspeer /* set up the first vio region mapped register */ 137244961713Sgirish (void) ddi_dev_regsize(nxgep->dip, 2, ®size); 137344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 13744045d941Ssowmini "nxge_map_regs: vio (1) size 0x%x", regsize)); 137544961713Sgirish ddi_status = ddi_regs_map_setup(nxgep->dip, 2, 13764045d941Ssowmini (caddr_t *)&(dev_regs->nxge_vir_regp), 0, 0, 13774045d941Ssowmini &nxge_dev_reg_acc_attr, &dev_regs->nxge_vir_regh); 137844961713Sgirish 137944961713Sgirish if (ddi_status != DDI_SUCCESS) { 138044961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 13814045d941Ssowmini "ddi_map_regs for nxge vio reg failed")); 138244961713Sgirish goto nxge_map_regs_fail2; 138344961713Sgirish } 1384678453a8Sspeer /* set up the second vio region mapped register */ 138544961713Sgirish (void) ddi_dev_regsize(nxgep->dip, 3, ®size); 138644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 13874045d941Ssowmini "nxge_map_regs: vio (3) size 0x%x", regsize)); 138844961713Sgirish ddi_status = ddi_regs_map_setup(nxgep->dip, 3, 13894045d941Ssowmini (caddr_t *)&(dev_regs->nxge_vir2_regp), 0, 0, 13904045d941Ssowmini &nxge_dev_reg_acc_attr, &dev_regs->nxge_vir2_regh); 139144961713Sgirish 139244961713Sgirish if (ddi_status != DDI_SUCCESS) { 139344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 13944045d941Ssowmini "ddi_map_regs for nxge vio2 reg failed")); 139544961713Sgirish goto nxge_map_regs_fail3; 139644961713Sgirish } 139744961713Sgirish nxgep->dev_regs = dev_regs; 139844961713Sgirish 139944961713Sgirish NPI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh); 140044961713Sgirish NPI_ADD_HANDLE_SET(nxgep, (npi_reg_ptr_t)dev_regs->nxge_regp); 140144961713Sgirish 140244961713Sgirish NPI_REG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh); 140344961713Sgirish NPI_REG_ADD_HANDLE_SET(nxgep, 14044045d941Ssowmini (npi_reg_ptr_t)dev_regs->nxge_regp); 140544961713Sgirish 140644961713Sgirish NPI_VREG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_vir_regh); 140744961713Sgirish NPI_VREG_ADD_HANDLE_SET(nxgep, 14084045d941Ssowmini (npi_reg_ptr_t)dev_regs->nxge_vir_regp); 140944961713Sgirish 141044961713Sgirish NPI_V2REG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_vir2_regh); 141144961713Sgirish NPI_V2REG_ADD_HANDLE_SET(nxgep, 14124045d941Ssowmini (npi_reg_ptr_t)dev_regs->nxge_vir2_regp); 141344961713Sgirish 141444961713Sgirish break; 141544961713Sgirish } 141644961713Sgirish 141744961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "nxge_map_reg: hardware addr 0x%0llx " 14184045d941Ssowmini " handle 0x%0llx", dev_regs->nxge_regp, dev_regs->nxge_regh)); 141944961713Sgirish 142044961713Sgirish goto nxge_map_regs_exit; 142144961713Sgirish nxge_map_regs_fail3: 142244961713Sgirish if (dev_regs->nxge_msix_regh) { 142344961713Sgirish ddi_regs_map_free(&dev_regs->nxge_msix_regh); 142444961713Sgirish } 142544961713Sgirish if (dev_regs->nxge_vir_regh) { 142644961713Sgirish ddi_regs_map_free(&dev_regs->nxge_regh); 142744961713Sgirish } 142844961713Sgirish nxge_map_regs_fail2: 142944961713Sgirish if (dev_regs->nxge_regh) { 143044961713Sgirish ddi_regs_map_free(&dev_regs->nxge_regh); 143144961713Sgirish } 143244961713Sgirish nxge_map_regs_fail1: 143344961713Sgirish if (dev_regs->nxge_pciregh) { 143444961713Sgirish ddi_regs_map_free(&dev_regs->nxge_pciregh); 143544961713Sgirish } 143644961713Sgirish nxge_map_regs_fail0: 143744961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "Freeing register set memory")); 143844961713Sgirish kmem_free(dev_regs, sizeof (dev_regs_t)); 143944961713Sgirish 144044961713Sgirish nxge_map_regs_exit: 144144961713Sgirish if (ddi_status != DDI_SUCCESS) 144244961713Sgirish status |= (NXGE_ERROR | NXGE_DDI_FAILED); 144344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_map_regs")); 144444961713Sgirish return (status); 144544961713Sgirish } 144644961713Sgirish 144744961713Sgirish static void 144844961713Sgirish nxge_unmap_regs(p_nxge_t nxgep) 144944961713Sgirish { 145044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_unmap_regs")); 1451678453a8Sspeer 1452678453a8Sspeer if (isLDOMguest(nxgep)) { 1453678453a8Sspeer nxge_guest_regs_map_free(nxgep); 1454678453a8Sspeer return; 1455678453a8Sspeer } 1456678453a8Sspeer 145744961713Sgirish if (nxgep->dev_regs) { 145844961713Sgirish if (nxgep->dev_regs->nxge_pciregh) { 145944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 14604045d941Ssowmini "==> nxge_unmap_regs: bus")); 146144961713Sgirish ddi_regs_map_free(&nxgep->dev_regs->nxge_pciregh); 146244961713Sgirish nxgep->dev_regs->nxge_pciregh = NULL; 146344961713Sgirish } 146444961713Sgirish if (nxgep->dev_regs->nxge_regh) { 146544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 14664045d941Ssowmini "==> nxge_unmap_regs: device registers")); 146744961713Sgirish ddi_regs_map_free(&nxgep->dev_regs->nxge_regh); 146844961713Sgirish nxgep->dev_regs->nxge_regh = NULL; 146944961713Sgirish } 147044961713Sgirish if (nxgep->dev_regs->nxge_msix_regh) { 147144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 14724045d941Ssowmini "==> nxge_unmap_regs: device interrupts")); 147344961713Sgirish ddi_regs_map_free(&nxgep->dev_regs->nxge_msix_regh); 147444961713Sgirish nxgep->dev_regs->nxge_msix_regh = NULL; 147544961713Sgirish } 147644961713Sgirish if (nxgep->dev_regs->nxge_vir_regh) { 147744961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 14784045d941Ssowmini "==> nxge_unmap_regs: vio region")); 147944961713Sgirish ddi_regs_map_free(&nxgep->dev_regs->nxge_vir_regh); 148044961713Sgirish nxgep->dev_regs->nxge_vir_regh = NULL; 148144961713Sgirish } 148244961713Sgirish if (nxgep->dev_regs->nxge_vir2_regh) { 148344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 14844045d941Ssowmini "==> nxge_unmap_regs: vio2 region")); 148544961713Sgirish ddi_regs_map_free(&nxgep->dev_regs->nxge_vir2_regh); 148644961713Sgirish nxgep->dev_regs->nxge_vir2_regh = NULL; 148744961713Sgirish } 148844961713Sgirish 148944961713Sgirish kmem_free(nxgep->dev_regs, sizeof (dev_regs_t)); 149044961713Sgirish nxgep->dev_regs = NULL; 149144961713Sgirish } 149244961713Sgirish 149344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_unmap_regs")); 149444961713Sgirish } 149544961713Sgirish 149644961713Sgirish static nxge_status_t 149744961713Sgirish nxge_setup_mutexes(p_nxge_t nxgep) 149844961713Sgirish { 149944961713Sgirish int ddi_status = DDI_SUCCESS; 150044961713Sgirish nxge_status_t status = NXGE_OK; 150144961713Sgirish nxge_classify_t *classify_ptr; 150244961713Sgirish int partition; 150344961713Sgirish 150444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_setup_mutexes")); 150544961713Sgirish 150644961713Sgirish /* 150744961713Sgirish * Get the interrupt cookie so the mutexes can be 150858324dfcSspeer * Initialized. 150944961713Sgirish */ 1510678453a8Sspeer if (isLDOMguest(nxgep)) { 1511678453a8Sspeer nxgep->interrupt_cookie = 0; 1512678453a8Sspeer } else { 1513678453a8Sspeer ddi_status = ddi_get_iblock_cookie(nxgep->dip, 0, 1514678453a8Sspeer &nxgep->interrupt_cookie); 1515678453a8Sspeer 1516678453a8Sspeer if (ddi_status != DDI_SUCCESS) { 1517678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1518678453a8Sspeer "<== nxge_setup_mutexes: failed 0x%x", 1519678453a8Sspeer ddi_status)); 1520678453a8Sspeer goto nxge_setup_mutexes_exit; 1521678453a8Sspeer } 152244961713Sgirish } 152344961713Sgirish 152498ecde52Stm cv_init(&nxgep->poll_cv, NULL, CV_DRIVER, NULL); 152598ecde52Stm MUTEX_INIT(&nxgep->poll_lock, NULL, 152698ecde52Stm MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 152798ecde52Stm 152844961713Sgirish /* 152998ecde52Stm * Initialize mutexes for this device. 153044961713Sgirish */ 153144961713Sgirish MUTEX_INIT(nxgep->genlock, NULL, 15324045d941Ssowmini MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 153344961713Sgirish MUTEX_INIT(&nxgep->ouraddr_lock, NULL, 15344045d941Ssowmini MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 153544961713Sgirish MUTEX_INIT(&nxgep->mif_lock, NULL, 15364045d941Ssowmini MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1537678453a8Sspeer MUTEX_INIT(&nxgep->group_lock, NULL, 1538678453a8Sspeer MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 153944961713Sgirish RW_INIT(&nxgep->filter_lock, NULL, 15404045d941Ssowmini RW_DRIVER, (void *)nxgep->interrupt_cookie); 154144961713Sgirish 154244961713Sgirish classify_ptr = &nxgep->classifier; 154344961713Sgirish /* 154444961713Sgirish * FFLP Mutexes are never used in interrupt context 154544961713Sgirish * as fflp operation can take very long time to 154644961713Sgirish * complete and hence not suitable to invoke from interrupt 154744961713Sgirish * handlers. 154844961713Sgirish */ 154944961713Sgirish MUTEX_INIT(&classify_ptr->tcam_lock, NULL, 155059ac0c16Sdavemq NXGE_MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 15512e59129aSraghus if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) { 155244961713Sgirish MUTEX_INIT(&classify_ptr->fcram_lock, NULL, 155359ac0c16Sdavemq NXGE_MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 155444961713Sgirish for (partition = 0; partition < MAX_PARTITION; partition++) { 155544961713Sgirish MUTEX_INIT(&classify_ptr->hash_lock[partition], NULL, 155644961713Sgirish NXGE_MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 155744961713Sgirish } 155844961713Sgirish } 155944961713Sgirish 156044961713Sgirish nxge_setup_mutexes_exit: 156144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 156259ac0c16Sdavemq "<== nxge_setup_mutexes status = %x", status)); 156344961713Sgirish 156444961713Sgirish if (ddi_status != DDI_SUCCESS) 156544961713Sgirish status |= (NXGE_ERROR | NXGE_DDI_FAILED); 156644961713Sgirish 156744961713Sgirish return (status); 156844961713Sgirish } 156944961713Sgirish 157044961713Sgirish static void 157144961713Sgirish nxge_destroy_mutexes(p_nxge_t nxgep) 157244961713Sgirish { 157344961713Sgirish int partition; 157444961713Sgirish nxge_classify_t *classify_ptr; 157544961713Sgirish 157644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_mutexes")); 157744961713Sgirish RW_DESTROY(&nxgep->filter_lock); 1578678453a8Sspeer MUTEX_DESTROY(&nxgep->group_lock); 157944961713Sgirish MUTEX_DESTROY(&nxgep->mif_lock); 158044961713Sgirish MUTEX_DESTROY(&nxgep->ouraddr_lock); 158144961713Sgirish MUTEX_DESTROY(nxgep->genlock); 158244961713Sgirish 158344961713Sgirish classify_ptr = &nxgep->classifier; 158444961713Sgirish MUTEX_DESTROY(&classify_ptr->tcam_lock); 158544961713Sgirish 158698ecde52Stm /* Destroy all polling resources. */ 158798ecde52Stm MUTEX_DESTROY(&nxgep->poll_lock); 158898ecde52Stm cv_destroy(&nxgep->poll_cv); 158998ecde52Stm 159098ecde52Stm /* free data structures, based on HW type */ 15912e59129aSraghus if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) { 159244961713Sgirish MUTEX_DESTROY(&classify_ptr->fcram_lock); 159344961713Sgirish for (partition = 0; partition < MAX_PARTITION; partition++) { 159444961713Sgirish MUTEX_DESTROY(&classify_ptr->hash_lock[partition]); 159544961713Sgirish } 159644961713Sgirish } 159744961713Sgirish 159844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_mutexes")); 159944961713Sgirish } 160044961713Sgirish 160144961713Sgirish nxge_status_t 160244961713Sgirish nxge_init(p_nxge_t nxgep) 160344961713Sgirish { 1604678453a8Sspeer nxge_status_t status = NXGE_OK; 160544961713Sgirish 160644961713Sgirish NXGE_DEBUG_MSG((nxgep, STR_CTL, "==> nxge_init")); 160744961713Sgirish 160814ea4bb7Ssd if (nxgep->drv_state & STATE_HW_INITIALIZED) { 160914ea4bb7Ssd return (status); 161014ea4bb7Ssd } 161114ea4bb7Ssd 161244961713Sgirish /* 161344961713Sgirish * Allocate system memory for the receive/transmit buffer blocks 161444961713Sgirish * and receive/transmit descriptor rings. 161544961713Sgirish */ 161644961713Sgirish status = nxge_alloc_mem_pool(nxgep); 161744961713Sgirish if (status != NXGE_OK) { 161844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "alloc mem failed\n")); 161944961713Sgirish goto nxge_init_fail1; 162044961713Sgirish } 162144961713Sgirish 1622678453a8Sspeer if (!isLDOMguest(nxgep)) { 1623678453a8Sspeer /* 1624678453a8Sspeer * Initialize and enable the TXC registers. 1625678453a8Sspeer * (Globally enable the Tx controller, 1626678453a8Sspeer * enable the port, configure the dma channel bitmap, 1627678453a8Sspeer * configure the max burst size). 1628678453a8Sspeer */ 1629678453a8Sspeer status = nxge_txc_init(nxgep); 1630678453a8Sspeer if (status != NXGE_OK) { 1631678453a8Sspeer NXGE_ERROR_MSG((nxgep, 1632678453a8Sspeer NXGE_ERR_CTL, "init txc failed\n")); 1633678453a8Sspeer goto nxge_init_fail2; 1634678453a8Sspeer } 163544961713Sgirish } 163644961713Sgirish 163744961713Sgirish /* 163844961713Sgirish * Initialize and enable TXDMA channels. 163944961713Sgirish */ 164044961713Sgirish status = nxge_init_txdma_channels(nxgep); 164144961713Sgirish if (status != NXGE_OK) { 164244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init txdma failed\n")); 164344961713Sgirish goto nxge_init_fail3; 164444961713Sgirish } 164544961713Sgirish 164644961713Sgirish /* 164744961713Sgirish * Initialize and enable RXDMA channels. 164844961713Sgirish */ 164944961713Sgirish status = nxge_init_rxdma_channels(nxgep); 165044961713Sgirish if (status != NXGE_OK) { 165144961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init rxdma failed\n")); 165244961713Sgirish goto nxge_init_fail4; 165344961713Sgirish } 165444961713Sgirish 1655678453a8Sspeer /* 1656678453a8Sspeer * The guest domain is now done. 1657678453a8Sspeer */ 1658678453a8Sspeer if (isLDOMguest(nxgep)) { 1659678453a8Sspeer nxgep->drv_state |= STATE_HW_INITIALIZED; 1660678453a8Sspeer goto nxge_init_exit; 1661678453a8Sspeer } 1662678453a8Sspeer 166344961713Sgirish /* 166444961713Sgirish * Initialize TCAM and FCRAM (Neptune). 166544961713Sgirish */ 166644961713Sgirish status = nxge_classify_init(nxgep); 166744961713Sgirish if (status != NXGE_OK) { 166844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init classify failed\n")); 166944961713Sgirish goto nxge_init_fail5; 167044961713Sgirish } 167144961713Sgirish 167244961713Sgirish /* 167344961713Sgirish * Initialize ZCP 167444961713Sgirish */ 167544961713Sgirish status = nxge_zcp_init(nxgep); 167644961713Sgirish if (status != NXGE_OK) { 167744961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init ZCP failed\n")); 167844961713Sgirish goto nxge_init_fail5; 167944961713Sgirish } 168044961713Sgirish 168144961713Sgirish /* 168244961713Sgirish * Initialize IPP. 168344961713Sgirish */ 168444961713Sgirish status = nxge_ipp_init(nxgep); 168544961713Sgirish if (status != NXGE_OK) { 168644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init IPP failed\n")); 168744961713Sgirish goto nxge_init_fail5; 168844961713Sgirish } 168944961713Sgirish 169044961713Sgirish /* 169144961713Sgirish * Initialize the MAC block. 169244961713Sgirish */ 169344961713Sgirish status = nxge_mac_init(nxgep); 169444961713Sgirish if (status != NXGE_OK) { 169544961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init MAC failed\n")); 169644961713Sgirish goto nxge_init_fail5; 169744961713Sgirish } 169844961713Sgirish 169944961713Sgirish /* 1700e759c33aSMichael Speer * Enable the interrrupts for DDI. 170144961713Sgirish */ 1702e759c33aSMichael Speer nxge_intrs_enable(nxgep); 1703e759c33aSMichael Speer 170444961713Sgirish nxgep->drv_state |= STATE_HW_INITIALIZED; 170544961713Sgirish 170644961713Sgirish goto nxge_init_exit; 170744961713Sgirish 170844961713Sgirish nxge_init_fail5: 170944961713Sgirish nxge_uninit_rxdma_channels(nxgep); 171044961713Sgirish nxge_init_fail4: 171144961713Sgirish nxge_uninit_txdma_channels(nxgep); 171244961713Sgirish nxge_init_fail3: 1713678453a8Sspeer if (!isLDOMguest(nxgep)) { 1714678453a8Sspeer (void) nxge_txc_uninit(nxgep); 1715678453a8Sspeer } 171644961713Sgirish nxge_init_fail2: 171744961713Sgirish nxge_free_mem_pool(nxgep); 171844961713Sgirish nxge_init_fail1: 171944961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 17204045d941Ssowmini "<== nxge_init status (failed) = 0x%08x", status)); 172144961713Sgirish return (status); 172244961713Sgirish 172344961713Sgirish nxge_init_exit: 172444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_init status = 0x%08x", 17254045d941Ssowmini status)); 172644961713Sgirish return (status); 172744961713Sgirish } 172844961713Sgirish 172944961713Sgirish 173044961713Sgirish timeout_id_t 173144961713Sgirish nxge_start_timer(p_nxge_t nxgep, fptrv_t func, int msec) 173244961713Sgirish { 17334045d941Ssowmini if ((nxgep->suspended == 0) || (nxgep->suspended == DDI_RESUME)) { 173444961713Sgirish return (timeout(func, (caddr_t)nxgep, 17354045d941Ssowmini drv_usectohz(1000 * msec))); 173644961713Sgirish } 173744961713Sgirish return (NULL); 173844961713Sgirish } 173944961713Sgirish 174044961713Sgirish /*ARGSUSED*/ 174144961713Sgirish void 174244961713Sgirish nxge_stop_timer(p_nxge_t nxgep, timeout_id_t timerid) 174344961713Sgirish { 174444961713Sgirish if (timerid) { 174544961713Sgirish (void) untimeout(timerid); 174644961713Sgirish } 174744961713Sgirish } 174844961713Sgirish 174944961713Sgirish void 175044961713Sgirish nxge_uninit(p_nxge_t nxgep) 175144961713Sgirish { 175244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_uninit")); 175344961713Sgirish 175444961713Sgirish if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 175544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 17564045d941Ssowmini "==> nxge_uninit: not initialized")); 175744961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 17584045d941Ssowmini "<== nxge_uninit")); 175944961713Sgirish return; 176044961713Sgirish } 176144961713Sgirish 1762e759c33aSMichael Speer if (!isLDOMguest(nxgep)) { 1763e759c33aSMichael Speer /* 1764e759c33aSMichael Speer * Reset the receive MAC side. 1765e759c33aSMichael Speer */ 1766e759c33aSMichael Speer (void) nxge_rx_mac_disable(nxgep); 1767e759c33aSMichael Speer 1768e759c33aSMichael Speer /* 1769e759c33aSMichael Speer * Drain the IPP. 1770e759c33aSMichael Speer */ 1771e759c33aSMichael Speer (void) nxge_ipp_drain(nxgep); 1772e759c33aSMichael Speer } 1773e759c33aSMichael Speer 177444961713Sgirish /* stop timer */ 177544961713Sgirish if (nxgep->nxge_timerid) { 177644961713Sgirish nxge_stop_timer(nxgep, nxgep->nxge_timerid); 177744961713Sgirish nxgep->nxge_timerid = 0; 177844961713Sgirish } 177944961713Sgirish 178044961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 178144961713Sgirish (void) nxge_intr_hw_disable(nxgep); 178244961713Sgirish 178344961713Sgirish 178444961713Sgirish /* Disable and soft reset the IPP */ 1785678453a8Sspeer if (!isLDOMguest(nxgep)) 1786678453a8Sspeer (void) nxge_ipp_disable(nxgep); 178744961713Sgirish 1788a3c5bd6dSspeer /* Free classification resources */ 1789a3c5bd6dSspeer (void) nxge_classify_uninit(nxgep); 1790a3c5bd6dSspeer 179144961713Sgirish /* 179244961713Sgirish * Reset the transmit/receive DMA side. 179344961713Sgirish */ 179444961713Sgirish (void) nxge_txdma_hw_mode(nxgep, NXGE_DMA_STOP); 179544961713Sgirish (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_STOP); 179644961713Sgirish 179744961713Sgirish nxge_uninit_txdma_channels(nxgep); 179844961713Sgirish nxge_uninit_rxdma_channels(nxgep); 179944961713Sgirish 180044961713Sgirish /* 180144961713Sgirish * Reset the transmit MAC side. 180244961713Sgirish */ 180344961713Sgirish (void) nxge_tx_mac_disable(nxgep); 180444961713Sgirish 180544961713Sgirish nxge_free_mem_pool(nxgep); 180644961713Sgirish 18076f157acbSml /* 18086f157acbSml * Start the timer if the reset flag is not set. 18096f157acbSml * If this reset flag is set, the link monitor 18106f157acbSml * will not be started in order to stop furthur bus 18116f157acbSml * activities coming from this interface. 18126f157acbSml * The driver will start the monitor function 18136f157acbSml * if the interface was initialized again later. 18146f157acbSml */ 18156f157acbSml if (!nxge_peu_reset_enable) { 18166f157acbSml (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 18176f157acbSml } 181844961713Sgirish 181944961713Sgirish nxgep->drv_state &= ~STATE_HW_INITIALIZED; 182044961713Sgirish 182144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_uninit: " 18224045d941Ssowmini "nxge_mblks_pending %d", nxge_mblks_pending)); 182344961713Sgirish } 182444961713Sgirish 182544961713Sgirish void 182644961713Sgirish nxge_get64(p_nxge_t nxgep, p_mblk_t mp) 182744961713Sgirish { 182844961713Sgirish uint64_t reg; 182944961713Sgirish uint64_t regdata; 183044961713Sgirish int i, retry; 183144961713Sgirish 183244961713Sgirish bcopy((char *)mp->b_rptr, (char *)®, sizeof (uint64_t)); 183344961713Sgirish regdata = 0; 183444961713Sgirish retry = 1; 183544961713Sgirish 183644961713Sgirish for (i = 0; i < retry; i++) { 183744961713Sgirish NXGE_REG_RD64(nxgep->npi_handle, reg, ®data); 183844961713Sgirish } 183944961713Sgirish bcopy((char *)®data, (char *)mp->b_rptr, sizeof (uint64_t)); 184044961713Sgirish } 184144961713Sgirish 184244961713Sgirish void 184344961713Sgirish nxge_put64(p_nxge_t nxgep, p_mblk_t mp) 184444961713Sgirish { 184544961713Sgirish uint64_t reg; 184644961713Sgirish uint64_t buf[2]; 184744961713Sgirish 184844961713Sgirish bcopy((char *)mp->b_rptr, (char *)&buf[0], 2 * sizeof (uint64_t)); 184944961713Sgirish reg = buf[0]; 185044961713Sgirish 185144961713Sgirish NXGE_NPI_PIO_WRITE64(nxgep->npi_handle, reg, buf[1]); 185244961713Sgirish } 185344961713Sgirish 185444961713Sgirish /*ARGSUSED*/ 185544961713Sgirish /*VARARGS*/ 185644961713Sgirish void 185744961713Sgirish nxge_debug_msg(p_nxge_t nxgep, uint64_t level, char *fmt, ...) 185844961713Sgirish { 185944961713Sgirish char msg_buffer[1048]; 186044961713Sgirish char prefix_buffer[32]; 186144961713Sgirish int instance; 186244961713Sgirish uint64_t debug_level; 186344961713Sgirish int cmn_level = CE_CONT; 186444961713Sgirish va_list ap; 186544961713Sgirish 1866678453a8Sspeer if (nxgep && nxgep->nxge_debug_level != nxge_debug_level) { 1867678453a8Sspeer /* In case a developer has changed nxge_debug_level. */ 1868678453a8Sspeer if (nxgep->nxge_debug_level != nxge_debug_level) 1869678453a8Sspeer nxgep->nxge_debug_level = nxge_debug_level; 1870678453a8Sspeer } 1871678453a8Sspeer 187244961713Sgirish debug_level = (nxgep == NULL) ? nxge_debug_level : 18734045d941Ssowmini nxgep->nxge_debug_level; 187444961713Sgirish 187544961713Sgirish if ((level & debug_level) || 18764045d941Ssowmini (level == NXGE_NOTE) || 18774045d941Ssowmini (level == NXGE_ERR_CTL)) { 187844961713Sgirish /* do the msg processing */ 187944961713Sgirish MUTEX_ENTER(&nxgedebuglock); 188044961713Sgirish 188144961713Sgirish if ((level & NXGE_NOTE)) { 188244961713Sgirish cmn_level = CE_NOTE; 188344961713Sgirish } 188444961713Sgirish 188544961713Sgirish if (level & NXGE_ERR_CTL) { 188644961713Sgirish cmn_level = CE_WARN; 188744961713Sgirish } 188844961713Sgirish 188944961713Sgirish va_start(ap, fmt); 189044961713Sgirish (void) vsprintf(msg_buffer, fmt, ap); 189144961713Sgirish va_end(ap); 189244961713Sgirish if (nxgep == NULL) { 189344961713Sgirish instance = -1; 189444961713Sgirish (void) sprintf(prefix_buffer, "%s :", "nxge"); 189544961713Sgirish } else { 189644961713Sgirish instance = nxgep->instance; 189744961713Sgirish (void) sprintf(prefix_buffer, 18984045d941Ssowmini "%s%d :", "nxge", instance); 189944961713Sgirish } 190044961713Sgirish 190144961713Sgirish MUTEX_EXIT(&nxgedebuglock); 190244961713Sgirish cmn_err(cmn_level, "!%s %s\n", 19034045d941Ssowmini prefix_buffer, msg_buffer); 190444961713Sgirish 190544961713Sgirish } 190644961713Sgirish } 190744961713Sgirish 190844961713Sgirish char * 190944961713Sgirish nxge_dump_packet(char *addr, int size) 191044961713Sgirish { 191144961713Sgirish uchar_t *ap = (uchar_t *)addr; 191244961713Sgirish int i; 191344961713Sgirish static char etherbuf[1024]; 191444961713Sgirish char *cp = etherbuf; 191544961713Sgirish char digits[] = "0123456789abcdef"; 191644961713Sgirish 191744961713Sgirish if (!size) 191844961713Sgirish size = 60; 191944961713Sgirish 192044961713Sgirish if (size > MAX_DUMP_SZ) { 192144961713Sgirish /* Dump the leading bytes */ 192244961713Sgirish for (i = 0; i < MAX_DUMP_SZ/2; i++) { 192344961713Sgirish if (*ap > 0x0f) 192444961713Sgirish *cp++ = digits[*ap >> 4]; 192544961713Sgirish *cp++ = digits[*ap++ & 0xf]; 192644961713Sgirish *cp++ = ':'; 192744961713Sgirish } 192844961713Sgirish for (i = 0; i < 20; i++) 192944961713Sgirish *cp++ = '.'; 193044961713Sgirish /* Dump the last MAX_DUMP_SZ/2 bytes */ 193144961713Sgirish ap = (uchar_t *)(addr + (size - MAX_DUMP_SZ/2)); 193244961713Sgirish for (i = 0; i < MAX_DUMP_SZ/2; i++) { 193344961713Sgirish if (*ap > 0x0f) 193444961713Sgirish *cp++ = digits[*ap >> 4]; 193544961713Sgirish *cp++ = digits[*ap++ & 0xf]; 193644961713Sgirish *cp++ = ':'; 193744961713Sgirish } 193844961713Sgirish } else { 193944961713Sgirish for (i = 0; i < size; i++) { 194044961713Sgirish if (*ap > 0x0f) 194144961713Sgirish *cp++ = digits[*ap >> 4]; 194244961713Sgirish *cp++ = digits[*ap++ & 0xf]; 194344961713Sgirish *cp++ = ':'; 194444961713Sgirish } 194544961713Sgirish } 194644961713Sgirish *--cp = 0; 194744961713Sgirish return (etherbuf); 194844961713Sgirish } 194944961713Sgirish 195044961713Sgirish #ifdef NXGE_DEBUG 195144961713Sgirish static void 195244961713Sgirish nxge_test_map_regs(p_nxge_t nxgep) 195344961713Sgirish { 195444961713Sgirish ddi_acc_handle_t cfg_handle; 195544961713Sgirish p_pci_cfg_t cfg_ptr; 195644961713Sgirish ddi_acc_handle_t dev_handle; 195744961713Sgirish char *dev_ptr; 195844961713Sgirish ddi_acc_handle_t pci_config_handle; 195944961713Sgirish uint32_t regval; 196044961713Sgirish int i; 196144961713Sgirish 196244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_test_map_regs")); 196344961713Sgirish 196444961713Sgirish dev_handle = nxgep->dev_regs->nxge_regh; 196544961713Sgirish dev_ptr = (char *)nxgep->dev_regs->nxge_regp; 196644961713Sgirish 19672e59129aSraghus if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) { 196844961713Sgirish cfg_handle = nxgep->dev_regs->nxge_pciregh; 196944961713Sgirish cfg_ptr = (void *)nxgep->dev_regs->nxge_pciregp; 197044961713Sgirish 197144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 197259ac0c16Sdavemq "Neptune PCI regp cfg_ptr 0x%llx", (char *)cfg_ptr)); 197344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 197459ac0c16Sdavemq "Neptune PCI cfg_ptr vendor id ptr 0x%llx", 197559ac0c16Sdavemq &cfg_ptr->vendorid)); 197644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 197759ac0c16Sdavemq "\tvendorid 0x%x devid 0x%x", 197859ac0c16Sdavemq NXGE_PIO_READ16(cfg_handle, &cfg_ptr->vendorid, 0), 197959ac0c16Sdavemq NXGE_PIO_READ16(cfg_handle, &cfg_ptr->devid, 0))); 198044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 198159ac0c16Sdavemq "PCI BAR: base 0x%x base14 0x%x base 18 0x%x " 198259ac0c16Sdavemq "bar1c 0x%x", 198359ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base, 0), 198459ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base14, 0), 198559ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base18, 0), 198659ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base1c, 0))); 198744961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 198859ac0c16Sdavemq "\nNeptune PCI BAR: base20 0x%x base24 0x%x " 198959ac0c16Sdavemq "base 28 0x%x bar2c 0x%x\n", 199059ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base20, 0), 199159ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base24, 0), 199259ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base28, 0), 199359ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base2c, 0))); 199444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 199559ac0c16Sdavemq "\nNeptune PCI BAR: base30 0x%x\n", 199659ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base30, 0))); 199744961713Sgirish 199844961713Sgirish cfg_handle = nxgep->dev_regs->nxge_pciregh; 199944961713Sgirish cfg_ptr = (void *)nxgep->dev_regs->nxge_pciregp; 200044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 200159ac0c16Sdavemq "first 0x%llx second 0x%llx third 0x%llx " 200259ac0c16Sdavemq "last 0x%llx ", 200359ac0c16Sdavemq NXGE_PIO_READ64(dev_handle, 200459ac0c16Sdavemq (uint64_t *)(dev_ptr + 0), 0), 200559ac0c16Sdavemq NXGE_PIO_READ64(dev_handle, 200659ac0c16Sdavemq (uint64_t *)(dev_ptr + 8), 0), 200759ac0c16Sdavemq NXGE_PIO_READ64(dev_handle, 200859ac0c16Sdavemq (uint64_t *)(dev_ptr + 16), 0), 200959ac0c16Sdavemq NXGE_PIO_READ64(cfg_handle, 201059ac0c16Sdavemq (uint64_t *)(dev_ptr + 24), 0))); 201144961713Sgirish } 201244961713Sgirish } 201344961713Sgirish 201444961713Sgirish #endif 201544961713Sgirish 201644961713Sgirish static void 201744961713Sgirish nxge_suspend(p_nxge_t nxgep) 201844961713Sgirish { 201944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_suspend")); 202044961713Sgirish 202144961713Sgirish nxge_intrs_disable(nxgep); 202244961713Sgirish nxge_destroy_dev(nxgep); 202344961713Sgirish 202444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_suspend")); 202544961713Sgirish } 202644961713Sgirish 202744961713Sgirish static nxge_status_t 202844961713Sgirish nxge_resume(p_nxge_t nxgep) 202944961713Sgirish { 203044961713Sgirish nxge_status_t status = NXGE_OK; 203144961713Sgirish 203244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_resume")); 203344961713Sgirish 203491c98b31Sjoycey nxgep->suspended = DDI_RESUME; 203591c98b31Sjoycey (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 203691c98b31Sjoycey (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_START); 203791c98b31Sjoycey (void) nxge_txdma_hw_mode(nxgep, NXGE_DMA_START); 203891c98b31Sjoycey (void) nxge_rx_mac_enable(nxgep); 203991c98b31Sjoycey (void) nxge_tx_mac_enable(nxgep); 204091c98b31Sjoycey nxge_intrs_enable(nxgep); 204144961713Sgirish nxgep->suspended = 0; 204244961713Sgirish 204344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 20444045d941Ssowmini "<== nxge_resume status = 0x%x", status)); 204544961713Sgirish return (status); 204644961713Sgirish } 204744961713Sgirish 204844961713Sgirish static nxge_status_t 204944961713Sgirish nxge_setup_dev(p_nxge_t nxgep) 205044961713Sgirish { 205144961713Sgirish nxge_status_t status = NXGE_OK; 205244961713Sgirish 205344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_setup_dev port %d", 205459ac0c16Sdavemq nxgep->mac.portnum)); 205544961713Sgirish 205644961713Sgirish status = nxge_link_init(nxgep); 205714ea4bb7Ssd 205814ea4bb7Ssd if (fm_check_acc_handle(nxgep->dev_regs->nxge_regh) != DDI_FM_OK) { 205914ea4bb7Ssd NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 20604045d941Ssowmini "port%d Bad register acc handle", nxgep->mac.portnum)); 206114ea4bb7Ssd status = NXGE_ERROR; 206214ea4bb7Ssd } 206314ea4bb7Ssd 206444961713Sgirish if (status != NXGE_OK) { 206544961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 20664045d941Ssowmini " nxge_setup_dev status " 20674045d941Ssowmini "(xcvr init 0x%08x)", status)); 206844961713Sgirish goto nxge_setup_dev_exit; 206944961713Sgirish } 207044961713Sgirish 207144961713Sgirish nxge_setup_dev_exit: 207244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 20734045d941Ssowmini "<== nxge_setup_dev port %d status = 0x%08x", 20744045d941Ssowmini nxgep->mac.portnum, status)); 207544961713Sgirish 207644961713Sgirish return (status); 207744961713Sgirish } 207844961713Sgirish 207944961713Sgirish static void 208044961713Sgirish nxge_destroy_dev(p_nxge_t nxgep) 208144961713Sgirish { 208244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_dev")); 208344961713Sgirish 208444961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 208544961713Sgirish 208644961713Sgirish (void) nxge_hw_stop(nxgep); 208744961713Sgirish 208844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_dev")); 208944961713Sgirish } 209044961713Sgirish 209144961713Sgirish static nxge_status_t 209244961713Sgirish nxge_setup_system_dma_pages(p_nxge_t nxgep) 209344961713Sgirish { 209444961713Sgirish int ddi_status = DDI_SUCCESS; 209544961713Sgirish uint_t count; 209644961713Sgirish ddi_dma_cookie_t cookie; 209744961713Sgirish uint_t iommu_pagesize; 209844961713Sgirish nxge_status_t status = NXGE_OK; 209944961713Sgirish 2100678453a8Sspeer NXGE_ERROR_MSG((nxgep, DDI_CTL, "==> nxge_setup_system_dma_pages")); 210144961713Sgirish nxgep->sys_page_sz = ddi_ptob(nxgep->dip, (ulong_t)1); 210244961713Sgirish if (nxgep->niu_type != N2_NIU) { 210344961713Sgirish iommu_pagesize = dvma_pagesize(nxgep->dip); 210444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 21054045d941Ssowmini " nxge_setup_system_dma_pages: page %d (ddi_ptob %d) " 21064045d941Ssowmini " default_block_size %d iommu_pagesize %d", 21074045d941Ssowmini nxgep->sys_page_sz, 21084045d941Ssowmini ddi_ptob(nxgep->dip, (ulong_t)1), 21094045d941Ssowmini nxgep->rx_default_block_size, 21104045d941Ssowmini iommu_pagesize)); 211144961713Sgirish 211244961713Sgirish if (iommu_pagesize != 0) { 211344961713Sgirish if (nxgep->sys_page_sz == iommu_pagesize) { 211444961713Sgirish if (iommu_pagesize > 0x4000) 211544961713Sgirish nxgep->sys_page_sz = 0x4000; 211644961713Sgirish } else { 211744961713Sgirish if (nxgep->sys_page_sz > iommu_pagesize) 211844961713Sgirish nxgep->sys_page_sz = iommu_pagesize; 211944961713Sgirish } 212044961713Sgirish } 212144961713Sgirish } 212244961713Sgirish nxgep->sys_page_mask = ~(nxgep->sys_page_sz - 1); 212344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 21244045d941Ssowmini "==> nxge_setup_system_dma_pages: page %d (ddi_ptob %d) " 21254045d941Ssowmini "default_block_size %d page mask %d", 21264045d941Ssowmini nxgep->sys_page_sz, 21274045d941Ssowmini ddi_ptob(nxgep->dip, (ulong_t)1), 21284045d941Ssowmini nxgep->rx_default_block_size, 21294045d941Ssowmini nxgep->sys_page_mask)); 213044961713Sgirish 213144961713Sgirish 213244961713Sgirish switch (nxgep->sys_page_sz) { 213344961713Sgirish default: 213444961713Sgirish nxgep->sys_page_sz = 0x1000; 213544961713Sgirish nxgep->sys_page_mask = ~(nxgep->sys_page_sz - 1); 213644961713Sgirish nxgep->rx_default_block_size = 0x1000; 213744961713Sgirish nxgep->rx_bksize_code = RBR_BKSIZE_4K; 213844961713Sgirish break; 213944961713Sgirish case 0x1000: 214044961713Sgirish nxgep->rx_default_block_size = 0x1000; 214144961713Sgirish nxgep->rx_bksize_code = RBR_BKSIZE_4K; 214244961713Sgirish break; 214344961713Sgirish case 0x2000: 214444961713Sgirish nxgep->rx_default_block_size = 0x2000; 214544961713Sgirish nxgep->rx_bksize_code = RBR_BKSIZE_8K; 214644961713Sgirish break; 214744961713Sgirish case 0x4000: 214844961713Sgirish nxgep->rx_default_block_size = 0x4000; 214944961713Sgirish nxgep->rx_bksize_code = RBR_BKSIZE_16K; 215044961713Sgirish break; 215144961713Sgirish case 0x8000: 215244961713Sgirish nxgep->rx_default_block_size = 0x8000; 215344961713Sgirish nxgep->rx_bksize_code = RBR_BKSIZE_32K; 215444961713Sgirish break; 215544961713Sgirish } 215644961713Sgirish 215744961713Sgirish #ifndef USE_RX_BIG_BUF 215844961713Sgirish nxge_rx_dma_attr.dma_attr_align = nxgep->sys_page_sz; 215944961713Sgirish #else 216044961713Sgirish nxgep->rx_default_block_size = 0x2000; 216144961713Sgirish nxgep->rx_bksize_code = RBR_BKSIZE_8K; 216244961713Sgirish #endif 216344961713Sgirish /* 216444961713Sgirish * Get the system DMA burst size. 216544961713Sgirish */ 216644961713Sgirish ddi_status = ddi_dma_alloc_handle(nxgep->dip, &nxge_tx_dma_attr, 21674045d941Ssowmini DDI_DMA_DONTWAIT, 0, 21684045d941Ssowmini &nxgep->dmasparehandle); 216944961713Sgirish if (ddi_status != DDI_SUCCESS) { 217044961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 21714045d941Ssowmini "ddi_dma_alloc_handle: failed " 21724045d941Ssowmini " status 0x%x", ddi_status)); 217344961713Sgirish goto nxge_get_soft_properties_exit; 217444961713Sgirish } 217544961713Sgirish 217644961713Sgirish ddi_status = ddi_dma_addr_bind_handle(nxgep->dmasparehandle, NULL, 21774045d941Ssowmini (caddr_t)nxgep->dmasparehandle, 21784045d941Ssowmini sizeof (nxgep->dmasparehandle), 21794045d941Ssowmini DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 21804045d941Ssowmini DDI_DMA_DONTWAIT, 0, 21814045d941Ssowmini &cookie, &count); 218244961713Sgirish if (ddi_status != DDI_DMA_MAPPED) { 218344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 21844045d941Ssowmini "Binding spare handle to find system" 21854045d941Ssowmini " burstsize failed.")); 218644961713Sgirish ddi_status = DDI_FAILURE; 218744961713Sgirish goto nxge_get_soft_properties_fail1; 218844961713Sgirish } 218944961713Sgirish 219044961713Sgirish nxgep->sys_burst_sz = ddi_dma_burstsizes(nxgep->dmasparehandle); 219144961713Sgirish (void) ddi_dma_unbind_handle(nxgep->dmasparehandle); 219244961713Sgirish 219344961713Sgirish nxge_get_soft_properties_fail1: 219444961713Sgirish ddi_dma_free_handle(&nxgep->dmasparehandle); 219544961713Sgirish 219644961713Sgirish nxge_get_soft_properties_exit: 219744961713Sgirish 219844961713Sgirish if (ddi_status != DDI_SUCCESS) 219944961713Sgirish status |= (NXGE_ERROR | NXGE_DDI_FAILED); 220044961713Sgirish 220144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 22024045d941Ssowmini "<== nxge_setup_system_dma_pages status = 0x%08x", status)); 220344961713Sgirish return (status); 220444961713Sgirish } 220544961713Sgirish 220644961713Sgirish static nxge_status_t 220744961713Sgirish nxge_alloc_mem_pool(p_nxge_t nxgep) 220844961713Sgirish { 220944961713Sgirish nxge_status_t status = NXGE_OK; 221044961713Sgirish 221144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_alloc_mem_pool")); 221244961713Sgirish 221344961713Sgirish status = nxge_alloc_rx_mem_pool(nxgep); 221444961713Sgirish if (status != NXGE_OK) { 221544961713Sgirish return (NXGE_ERROR); 221644961713Sgirish } 221744961713Sgirish 221844961713Sgirish status = nxge_alloc_tx_mem_pool(nxgep); 221944961713Sgirish if (status != NXGE_OK) { 222044961713Sgirish nxge_free_rx_mem_pool(nxgep); 222144961713Sgirish return (NXGE_ERROR); 222244961713Sgirish } 222344961713Sgirish 222444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_alloc_mem_pool")); 222544961713Sgirish return (NXGE_OK); 222644961713Sgirish } 222744961713Sgirish 222844961713Sgirish static void 222944961713Sgirish nxge_free_mem_pool(p_nxge_t nxgep) 223044961713Sgirish { 223144961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM_CTL, "==> nxge_free_mem_pool")); 223244961713Sgirish 223344961713Sgirish nxge_free_rx_mem_pool(nxgep); 223444961713Sgirish nxge_free_tx_mem_pool(nxgep); 223544961713Sgirish 223644961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM_CTL, "<== nxge_free_mem_pool")); 223744961713Sgirish } 223844961713Sgirish 2239678453a8Sspeer nxge_status_t 224044961713Sgirish nxge_alloc_rx_mem_pool(p_nxge_t nxgep) 224144961713Sgirish { 2242678453a8Sspeer uint32_t rdc_max; 224344961713Sgirish p_nxge_dma_pt_cfg_t p_all_cfgp; 224444961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 224544961713Sgirish p_nxge_dma_pool_t dma_poolp; 224644961713Sgirish p_nxge_dma_common_t *dma_buf_p; 224744961713Sgirish p_nxge_dma_pool_t dma_cntl_poolp; 224844961713Sgirish p_nxge_dma_common_t *dma_cntl_p; 224944961713Sgirish uint32_t *num_chunks; /* per dma */ 225044961713Sgirish nxge_status_t status = NXGE_OK; 225144961713Sgirish 225244961713Sgirish uint32_t nxge_port_rbr_size; 225344961713Sgirish uint32_t nxge_port_rbr_spare_size; 225444961713Sgirish uint32_t nxge_port_rcr_size; 2255678453a8Sspeer uint32_t rx_cntl_alloc_size; 225644961713Sgirish 225744961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rx_mem_pool")); 225844961713Sgirish 225944961713Sgirish p_all_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 226044961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_all_cfgp->hw_config; 2261678453a8Sspeer rdc_max = NXGE_MAX_RDCS; 226244961713Sgirish 226344961713Sgirish /* 2264678453a8Sspeer * Allocate memory for the common DMA data structures. 226544961713Sgirish */ 226644961713Sgirish dma_poolp = (p_nxge_dma_pool_t)KMEM_ZALLOC(sizeof (nxge_dma_pool_t), 22674045d941Ssowmini KM_SLEEP); 226844961713Sgirish dma_buf_p = (p_nxge_dma_common_t *)KMEM_ZALLOC( 22694045d941Ssowmini sizeof (p_nxge_dma_common_t) * rdc_max, KM_SLEEP); 227044961713Sgirish 227144961713Sgirish dma_cntl_poolp = (p_nxge_dma_pool_t) 22724045d941Ssowmini KMEM_ZALLOC(sizeof (nxge_dma_pool_t), KM_SLEEP); 227344961713Sgirish dma_cntl_p = (p_nxge_dma_common_t *)KMEM_ZALLOC( 22744045d941Ssowmini sizeof (p_nxge_dma_common_t) * rdc_max, KM_SLEEP); 227544961713Sgirish 227644961713Sgirish num_chunks = (uint32_t *)KMEM_ZALLOC( 22774045d941Ssowmini sizeof (uint32_t) * rdc_max, KM_SLEEP); 227844961713Sgirish 227944961713Sgirish /* 2280678453a8Sspeer * Assume that each DMA channel will be configured with 2281678453a8Sspeer * the default block size. 2282678453a8Sspeer * rbr block counts are modulo the batch count (16). 228344961713Sgirish */ 228444961713Sgirish nxge_port_rbr_size = p_all_cfgp->rbr_size; 228544961713Sgirish nxge_port_rcr_size = p_all_cfgp->rcr_size; 228644961713Sgirish 228744961713Sgirish if (!nxge_port_rbr_size) { 228844961713Sgirish nxge_port_rbr_size = NXGE_RBR_RBB_DEFAULT; 228944961713Sgirish } 229044961713Sgirish if (nxge_port_rbr_size % NXGE_RXDMA_POST_BATCH) { 229144961713Sgirish nxge_port_rbr_size = (NXGE_RXDMA_POST_BATCH * 22924045d941Ssowmini (nxge_port_rbr_size / NXGE_RXDMA_POST_BATCH + 1)); 229344961713Sgirish } 229444961713Sgirish 229544961713Sgirish p_all_cfgp->rbr_size = nxge_port_rbr_size; 229644961713Sgirish nxge_port_rbr_spare_size = nxge_rbr_spare_size; 229744961713Sgirish 229844961713Sgirish if (nxge_port_rbr_spare_size % NXGE_RXDMA_POST_BATCH) { 229944961713Sgirish nxge_port_rbr_spare_size = (NXGE_RXDMA_POST_BATCH * 23004045d941Ssowmini (nxge_port_rbr_spare_size / NXGE_RXDMA_POST_BATCH + 1)); 230144961713Sgirish } 230230ac2e7bSml if (nxge_port_rbr_size > RBR_DEFAULT_MAX_BLKS) { 230330ac2e7bSml NXGE_DEBUG_MSG((nxgep, MEM_CTL, 230430ac2e7bSml "nxge_alloc_rx_mem_pool: RBR size too high %d, " 230530ac2e7bSml "set to default %d", 230630ac2e7bSml nxge_port_rbr_size, RBR_DEFAULT_MAX_BLKS)); 230730ac2e7bSml nxge_port_rbr_size = RBR_DEFAULT_MAX_BLKS; 230830ac2e7bSml } 230930ac2e7bSml if (nxge_port_rcr_size > RCR_DEFAULT_MAX) { 231030ac2e7bSml NXGE_DEBUG_MSG((nxgep, MEM_CTL, 231130ac2e7bSml "nxge_alloc_rx_mem_pool: RCR too high %d, " 231230ac2e7bSml "set to default %d", 231330ac2e7bSml nxge_port_rcr_size, RCR_DEFAULT_MAX)); 231430ac2e7bSml nxge_port_rcr_size = RCR_DEFAULT_MAX; 231530ac2e7bSml } 231644961713Sgirish 231744961713Sgirish /* 231844961713Sgirish * N2/NIU has limitation on the descriptor sizes (contiguous 231944961713Sgirish * memory allocation on data buffers to 4M (contig_mem_alloc) 232044961713Sgirish * and little endian for control buffers (must use the ddi/dki mem alloc 232144961713Sgirish * function). 232244961713Sgirish */ 232344961713Sgirish #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 232444961713Sgirish if (nxgep->niu_type == N2_NIU) { 232544961713Sgirish nxge_port_rbr_spare_size = 0; 232644961713Sgirish if ((nxge_port_rbr_size > NXGE_NIU_CONTIG_RBR_MAX) || 23274045d941Ssowmini (!ISP2(nxge_port_rbr_size))) { 232844961713Sgirish nxge_port_rbr_size = NXGE_NIU_CONTIG_RBR_MAX; 232944961713Sgirish } 233044961713Sgirish if ((nxge_port_rcr_size > NXGE_NIU_CONTIG_RCR_MAX) || 23314045d941Ssowmini (!ISP2(nxge_port_rcr_size))) { 233244961713Sgirish nxge_port_rcr_size = NXGE_NIU_CONTIG_RCR_MAX; 233344961713Sgirish } 233444961713Sgirish } 233544961713Sgirish #endif 233644961713Sgirish 233744961713Sgirish /* 233844961713Sgirish * Addresses of receive block ring, receive completion ring and the 233944961713Sgirish * mailbox must be all cache-aligned (64 bytes). 234044961713Sgirish */ 234144961713Sgirish rx_cntl_alloc_size = nxge_port_rbr_size + nxge_port_rbr_spare_size; 234244961713Sgirish rx_cntl_alloc_size *= (sizeof (rx_desc_t)); 234344961713Sgirish rx_cntl_alloc_size += (sizeof (rcr_entry_t) * nxge_port_rcr_size); 234444961713Sgirish rx_cntl_alloc_size += sizeof (rxdma_mailbox_t); 234544961713Sgirish 234644961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_alloc_rx_mem_pool: " 23474045d941Ssowmini "nxge_port_rbr_size = %d nxge_port_rbr_spare_size = %d " 23484045d941Ssowmini "nxge_port_rcr_size = %d " 23494045d941Ssowmini "rx_cntl_alloc_size = %d", 23504045d941Ssowmini nxge_port_rbr_size, nxge_port_rbr_spare_size, 23514045d941Ssowmini nxge_port_rcr_size, 23524045d941Ssowmini rx_cntl_alloc_size)); 235344961713Sgirish 235444961713Sgirish #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 235544961713Sgirish if (nxgep->niu_type == N2_NIU) { 2356678453a8Sspeer uint32_t rx_buf_alloc_size = (nxgep->rx_default_block_size * 2357678453a8Sspeer (nxge_port_rbr_size + nxge_port_rbr_spare_size)); 2358678453a8Sspeer 235944961713Sgirish if (!ISP2(rx_buf_alloc_size)) { 236044961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 23614045d941Ssowmini "==> nxge_alloc_rx_mem_pool: " 23624045d941Ssowmini " must be power of 2")); 236344961713Sgirish status |= (NXGE_ERROR | NXGE_DDI_FAILED); 236444961713Sgirish goto nxge_alloc_rx_mem_pool_exit; 236544961713Sgirish } 236644961713Sgirish 236744961713Sgirish if (rx_buf_alloc_size > (1 << 22)) { 236844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 23694045d941Ssowmini "==> nxge_alloc_rx_mem_pool: " 23704045d941Ssowmini " limit size to 4M")); 237144961713Sgirish status |= (NXGE_ERROR | NXGE_DDI_FAILED); 237244961713Sgirish goto nxge_alloc_rx_mem_pool_exit; 237344961713Sgirish } 237444961713Sgirish 237544961713Sgirish if (rx_cntl_alloc_size < 0x2000) { 237644961713Sgirish rx_cntl_alloc_size = 0x2000; 237744961713Sgirish } 237844961713Sgirish } 237944961713Sgirish #endif 238044961713Sgirish nxgep->nxge_port_rbr_size = nxge_port_rbr_size; 238144961713Sgirish nxgep->nxge_port_rcr_size = nxge_port_rcr_size; 2382678453a8Sspeer nxgep->nxge_port_rbr_spare_size = nxge_port_rbr_spare_size; 2383678453a8Sspeer nxgep->nxge_port_rx_cntl_alloc_size = rx_cntl_alloc_size; 238444961713Sgirish 2385678453a8Sspeer dma_poolp->ndmas = p_cfgp->max_rdcs; 238644961713Sgirish dma_poolp->num_chunks = num_chunks; 238744961713Sgirish dma_poolp->buf_allocated = B_TRUE; 238844961713Sgirish nxgep->rx_buf_pool_p = dma_poolp; 238944961713Sgirish dma_poolp->dma_buf_pool_p = dma_buf_p; 239044961713Sgirish 2391678453a8Sspeer dma_cntl_poolp->ndmas = p_cfgp->max_rdcs; 239244961713Sgirish dma_cntl_poolp->buf_allocated = B_TRUE; 239344961713Sgirish nxgep->rx_cntl_pool_p = dma_cntl_poolp; 239444961713Sgirish dma_cntl_poolp->dma_buf_pool_p = dma_cntl_p; 239544961713Sgirish 2396678453a8Sspeer /* Allocate the receive rings, too. */ 2397678453a8Sspeer nxgep->rx_rbr_rings = 23984045d941Ssowmini KMEM_ZALLOC(sizeof (rx_rbr_rings_t), KM_SLEEP); 2399678453a8Sspeer nxgep->rx_rbr_rings->rbr_rings = 24004045d941Ssowmini KMEM_ZALLOC(sizeof (p_rx_rbr_ring_t) * rdc_max, KM_SLEEP); 2401678453a8Sspeer nxgep->rx_rcr_rings = 24024045d941Ssowmini KMEM_ZALLOC(sizeof (rx_rcr_rings_t), KM_SLEEP); 2403678453a8Sspeer nxgep->rx_rcr_rings->rcr_rings = 24044045d941Ssowmini KMEM_ZALLOC(sizeof (p_rx_rcr_ring_t) * rdc_max, KM_SLEEP); 2405678453a8Sspeer nxgep->rx_mbox_areas_p = 24064045d941Ssowmini KMEM_ZALLOC(sizeof (rx_mbox_areas_t), KM_SLEEP); 2407678453a8Sspeer nxgep->rx_mbox_areas_p->rxmbox_areas = 24084045d941Ssowmini KMEM_ZALLOC(sizeof (p_rx_mbox_t) * rdc_max, KM_SLEEP); 2409678453a8Sspeer 2410678453a8Sspeer nxgep->rx_rbr_rings->ndmas = nxgep->rx_rcr_rings->ndmas = 2411678453a8Sspeer p_cfgp->max_rdcs; 241244961713Sgirish 241344961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 24144045d941Ssowmini "<== nxge_alloc_rx_mem_pool:status 0x%08x", status)); 241544961713Sgirish 2416678453a8Sspeer nxge_alloc_rx_mem_pool_exit: 2417678453a8Sspeer return (status); 2418678453a8Sspeer } 2419678453a8Sspeer 2420678453a8Sspeer /* 2421678453a8Sspeer * nxge_alloc_rxb 2422678453a8Sspeer * 2423678453a8Sspeer * Allocate buffers for an RDC. 2424678453a8Sspeer * 2425678453a8Sspeer * Arguments: 2426678453a8Sspeer * nxgep 2427678453a8Sspeer * channel The channel to map into our kernel space. 2428678453a8Sspeer * 2429678453a8Sspeer * Notes: 2430678453a8Sspeer * 2431678453a8Sspeer * NPI function calls: 2432678453a8Sspeer * 2433678453a8Sspeer * NXGE function calls: 2434678453a8Sspeer * 2435678453a8Sspeer * Registers accessed: 2436678453a8Sspeer * 2437678453a8Sspeer * Context: 2438678453a8Sspeer * 2439678453a8Sspeer * Taking apart: 2440678453a8Sspeer * 2441678453a8Sspeer * Open questions: 2442678453a8Sspeer * 2443678453a8Sspeer */ 2444678453a8Sspeer nxge_status_t 2445678453a8Sspeer nxge_alloc_rxb( 2446678453a8Sspeer p_nxge_t nxgep, 2447678453a8Sspeer int channel) 2448678453a8Sspeer { 2449678453a8Sspeer size_t rx_buf_alloc_size; 2450678453a8Sspeer nxge_status_t status = NXGE_OK; 2451678453a8Sspeer 2452678453a8Sspeer nxge_dma_common_t **data; 2453678453a8Sspeer nxge_dma_common_t **control; 2454678453a8Sspeer uint32_t *num_chunks; 2455678453a8Sspeer 2456678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rbb")); 2457678453a8Sspeer 2458678453a8Sspeer /* 2459678453a8Sspeer * Allocate memory for the receive buffers and descriptor rings. 2460678453a8Sspeer * Replace these allocation functions with the interface functions 2461678453a8Sspeer * provided by the partition manager if/when they are available. 2462678453a8Sspeer */ 2463678453a8Sspeer 2464678453a8Sspeer /* 2465678453a8Sspeer * Allocate memory for the receive buffer blocks. 2466678453a8Sspeer */ 2467678453a8Sspeer rx_buf_alloc_size = (nxgep->rx_default_block_size * 24684045d941Ssowmini (nxgep->nxge_port_rbr_size + nxgep->nxge_port_rbr_spare_size)); 2469678453a8Sspeer 2470678453a8Sspeer data = &nxgep->rx_buf_pool_p->dma_buf_pool_p[channel]; 2471678453a8Sspeer num_chunks = &nxgep->rx_buf_pool_p->num_chunks[channel]; 2472678453a8Sspeer 2473678453a8Sspeer if ((status = nxge_alloc_rx_buf_dma( 2474678453a8Sspeer nxgep, channel, data, rx_buf_alloc_size, 2475678453a8Sspeer nxgep->rx_default_block_size, num_chunks)) != NXGE_OK) { 2476678453a8Sspeer return (status); 247744961713Sgirish } 247844961713Sgirish 2479678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_alloc_rxb(): " 2480678453a8Sspeer "dma %d dma_buf_p %llx &dma_buf_p %llx", channel, *data, data)); 2481678453a8Sspeer 2482678453a8Sspeer /* 2483678453a8Sspeer * Allocate memory for descriptor rings and mailbox. 2484678453a8Sspeer */ 2485678453a8Sspeer control = &nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel]; 2486678453a8Sspeer 2487678453a8Sspeer if ((status = nxge_alloc_rx_cntl_dma( 2488678453a8Sspeer nxgep, channel, control, nxgep->nxge_port_rx_cntl_alloc_size)) 2489678453a8Sspeer != NXGE_OK) { 2490678453a8Sspeer nxge_free_rx_cntl_dma(nxgep, *control); 2491678453a8Sspeer (*data)->buf_alloc_state |= BUF_ALLOCATED_WAIT_FREE; 2492678453a8Sspeer nxge_free_rx_buf_dma(nxgep, *data, *num_chunks); 2493678453a8Sspeer return (status); 2494678453a8Sspeer } 249544961713Sgirish 249644961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 2497678453a8Sspeer "<== nxge_alloc_rx_mem_pool:status 0x%08x", status)); 249844961713Sgirish 249944961713Sgirish return (status); 250044961713Sgirish } 250144961713Sgirish 2502678453a8Sspeer void 2503678453a8Sspeer nxge_free_rxb( 2504678453a8Sspeer p_nxge_t nxgep, 2505678453a8Sspeer int channel) 2506678453a8Sspeer { 2507678453a8Sspeer nxge_dma_common_t *data; 2508678453a8Sspeer nxge_dma_common_t *control; 2509678453a8Sspeer uint32_t num_chunks; 2510678453a8Sspeer 2511678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rbb")); 2512678453a8Sspeer 2513678453a8Sspeer data = nxgep->rx_buf_pool_p->dma_buf_pool_p[channel]; 2514678453a8Sspeer num_chunks = nxgep->rx_buf_pool_p->num_chunks[channel]; 2515678453a8Sspeer nxge_free_rx_buf_dma(nxgep, data, num_chunks); 2516678453a8Sspeer 2517678453a8Sspeer nxgep->rx_buf_pool_p->dma_buf_pool_p[channel] = 0; 2518678453a8Sspeer nxgep->rx_buf_pool_p->num_chunks[channel] = 0; 2519678453a8Sspeer 2520678453a8Sspeer control = nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel]; 2521678453a8Sspeer nxge_free_rx_cntl_dma(nxgep, control); 2522678453a8Sspeer 2523678453a8Sspeer nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel] = 0; 2524678453a8Sspeer 2525678453a8Sspeer KMEM_FREE(data, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK); 2526678453a8Sspeer KMEM_FREE(control, sizeof (nxge_dma_common_t)); 2527678453a8Sspeer 2528678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_alloc_rbb")); 2529678453a8Sspeer } 2530678453a8Sspeer 253144961713Sgirish static void 253244961713Sgirish nxge_free_rx_mem_pool(p_nxge_t nxgep) 253344961713Sgirish { 2534678453a8Sspeer int rdc_max = NXGE_MAX_RDCS; 253544961713Sgirish 253644961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_free_rx_mem_pool")); 253744961713Sgirish 2538678453a8Sspeer if (!nxgep->rx_buf_pool_p || !nxgep->rx_buf_pool_p->buf_allocated) { 253944961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 25404045d941Ssowmini "<== nxge_free_rx_mem_pool " 25414045d941Ssowmini "(null rx buf pool or buf not allocated")); 254244961713Sgirish return; 254344961713Sgirish } 2544678453a8Sspeer if (!nxgep->rx_cntl_pool_p || !nxgep->rx_cntl_pool_p->buf_allocated) { 254544961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 25464045d941Ssowmini "<== nxge_free_rx_mem_pool " 25474045d941Ssowmini "(null rx cntl buf pool or cntl buf not allocated")); 254844961713Sgirish return; 254944961713Sgirish } 255044961713Sgirish 2551678453a8Sspeer KMEM_FREE(nxgep->rx_cntl_pool_p->dma_buf_pool_p, 2552678453a8Sspeer sizeof (p_nxge_dma_common_t) * rdc_max); 2553678453a8Sspeer KMEM_FREE(nxgep->rx_cntl_pool_p, sizeof (nxge_dma_pool_t)); 255444961713Sgirish 2555678453a8Sspeer KMEM_FREE(nxgep->rx_buf_pool_p->num_chunks, 2556678453a8Sspeer sizeof (uint32_t) * rdc_max); 2557678453a8Sspeer KMEM_FREE(nxgep->rx_buf_pool_p->dma_buf_pool_p, 2558678453a8Sspeer sizeof (p_nxge_dma_common_t) * rdc_max); 2559678453a8Sspeer KMEM_FREE(nxgep->rx_buf_pool_p, sizeof (nxge_dma_pool_t)); 256044961713Sgirish 2561678453a8Sspeer nxgep->rx_buf_pool_p = 0; 2562678453a8Sspeer nxgep->rx_cntl_pool_p = 0; 256344961713Sgirish 2564678453a8Sspeer KMEM_FREE(nxgep->rx_rbr_rings->rbr_rings, 2565678453a8Sspeer sizeof (p_rx_rbr_ring_t) * rdc_max); 2566678453a8Sspeer KMEM_FREE(nxgep->rx_rbr_rings, sizeof (rx_rbr_rings_t)); 2567678453a8Sspeer KMEM_FREE(nxgep->rx_rcr_rings->rcr_rings, 2568678453a8Sspeer sizeof (p_rx_rcr_ring_t) * rdc_max); 2569678453a8Sspeer KMEM_FREE(nxgep->rx_rcr_rings, sizeof (rx_rcr_rings_t)); 2570678453a8Sspeer KMEM_FREE(nxgep->rx_mbox_areas_p->rxmbox_areas, 2571678453a8Sspeer sizeof (p_rx_mbox_t) * rdc_max); 2572678453a8Sspeer KMEM_FREE(nxgep->rx_mbox_areas_p, sizeof (rx_mbox_areas_t)); 257344961713Sgirish 2574678453a8Sspeer nxgep->rx_rbr_rings = 0; 2575678453a8Sspeer nxgep->rx_rcr_rings = 0; 2576678453a8Sspeer nxgep->rx_mbox_areas_p = 0; 257744961713Sgirish 257844961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_free_rx_mem_pool")); 257944961713Sgirish } 258044961713Sgirish 258144961713Sgirish 258244961713Sgirish static nxge_status_t 258344961713Sgirish nxge_alloc_rx_buf_dma(p_nxge_t nxgep, uint16_t dma_channel, 258444961713Sgirish p_nxge_dma_common_t *dmap, 258544961713Sgirish size_t alloc_size, size_t block_size, uint32_t *num_chunks) 258644961713Sgirish { 258744961713Sgirish p_nxge_dma_common_t rx_dmap; 258844961713Sgirish nxge_status_t status = NXGE_OK; 258944961713Sgirish size_t total_alloc_size; 259044961713Sgirish size_t allocated = 0; 259144961713Sgirish int i, size_index, array_size; 2592678453a8Sspeer boolean_t use_kmem_alloc = B_FALSE; 259344961713Sgirish 259444961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rx_buf_dma")); 259544961713Sgirish 259644961713Sgirish rx_dmap = (p_nxge_dma_common_t) 25974045d941Ssowmini KMEM_ZALLOC(sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK, 25984045d941Ssowmini KM_SLEEP); 259944961713Sgirish 260044961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 26014045d941Ssowmini " alloc_rx_buf_dma rdc %d asize %x bsize %x bbuf %llx ", 26024045d941Ssowmini dma_channel, alloc_size, block_size, dmap)); 260344961713Sgirish 260444961713Sgirish total_alloc_size = alloc_size; 260544961713Sgirish 260644961713Sgirish #if defined(RX_USE_RECLAIM_POST) 260744961713Sgirish total_alloc_size = alloc_size + alloc_size/4; 260844961713Sgirish #endif 260944961713Sgirish 261044961713Sgirish i = 0; 261144961713Sgirish size_index = 0; 261244961713Sgirish array_size = sizeof (alloc_sizes)/sizeof (size_t); 26137b26d9ffSSantwona Behera while ((size_index < array_size) && 26147b26d9ffSSantwona Behera (alloc_sizes[size_index] < alloc_size)) 26154045d941Ssowmini size_index++; 261644961713Sgirish if (size_index >= array_size) { 261744961713Sgirish size_index = array_size - 1; 261844961713Sgirish } 261944961713Sgirish 2620678453a8Sspeer /* For Neptune, use kmem_alloc if the kmem flag is set. */ 2621678453a8Sspeer if (nxgep->niu_type != N2_NIU && nxge_use_kmem_alloc) { 2622678453a8Sspeer use_kmem_alloc = B_TRUE; 2623678453a8Sspeer #if defined(__i386) || defined(__amd64) 2624678453a8Sspeer size_index = 0; 2625678453a8Sspeer #endif 2626678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2627678453a8Sspeer "==> nxge_alloc_rx_buf_dma: " 2628678453a8Sspeer "Neptune use kmem_alloc() - size_index %d", 2629678453a8Sspeer size_index)); 2630678453a8Sspeer } 2631678453a8Sspeer 263244961713Sgirish while ((allocated < total_alloc_size) && 26334045d941Ssowmini (size_index >= 0) && (i < NXGE_DMA_BLOCK)) { 263444961713Sgirish rx_dmap[i].dma_chunk_index = i; 263544961713Sgirish rx_dmap[i].block_size = block_size; 263644961713Sgirish rx_dmap[i].alength = alloc_sizes[size_index]; 263744961713Sgirish rx_dmap[i].orig_alength = rx_dmap[i].alength; 263844961713Sgirish rx_dmap[i].nblocks = alloc_sizes[size_index] / block_size; 263944961713Sgirish rx_dmap[i].dma_channel = dma_channel; 264044961713Sgirish rx_dmap[i].contig_alloc_type = B_FALSE; 2641678453a8Sspeer rx_dmap[i].kmem_alloc_type = B_FALSE; 2642678453a8Sspeer rx_dmap[i].buf_alloc_type = DDI_MEM_ALLOC; 264344961713Sgirish 264444961713Sgirish /* 264544961713Sgirish * N2/NIU: data buffers must be contiguous as the driver 264644961713Sgirish * needs to call Hypervisor api to set up 264744961713Sgirish * logical pages. 264844961713Sgirish */ 264944961713Sgirish if ((nxgep->niu_type == N2_NIU) && (NXGE_DMA_BLOCK == 1)) { 265044961713Sgirish rx_dmap[i].contig_alloc_type = B_TRUE; 2651678453a8Sspeer rx_dmap[i].buf_alloc_type = CONTIG_MEM_ALLOC; 2652678453a8Sspeer } else if (use_kmem_alloc) { 2653678453a8Sspeer /* For Neptune, use kmem_alloc */ 2654678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2655678453a8Sspeer "==> nxge_alloc_rx_buf_dma: " 2656678453a8Sspeer "Neptune use kmem_alloc()")); 2657678453a8Sspeer rx_dmap[i].kmem_alloc_type = B_TRUE; 2658678453a8Sspeer rx_dmap[i].buf_alloc_type = KMEM_ALLOC; 265944961713Sgirish } 266044961713Sgirish 266144961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 26624045d941Ssowmini "alloc_rx_buf_dma rdc %d chunk %d bufp %llx size %x " 26634045d941Ssowmini "i %d nblocks %d alength %d", 26644045d941Ssowmini dma_channel, i, &rx_dmap[i], block_size, 26654045d941Ssowmini i, rx_dmap[i].nblocks, 26664045d941Ssowmini rx_dmap[i].alength)); 266744961713Sgirish status = nxge_dma_mem_alloc(nxgep, nxge_force_dma, 26684045d941Ssowmini &nxge_rx_dma_attr, 26694045d941Ssowmini rx_dmap[i].alength, 26704045d941Ssowmini &nxge_dev_buf_dma_acc_attr, 26714045d941Ssowmini DDI_DMA_READ | DDI_DMA_STREAMING, 26724045d941Ssowmini (p_nxge_dma_common_t)(&rx_dmap[i])); 267344961713Sgirish if (status != NXGE_OK) { 267444961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2675678453a8Sspeer "nxge_alloc_rx_buf_dma: Alloc Failed: " 2676678453a8Sspeer "dma %d size_index %d size requested %d", 2677678453a8Sspeer dma_channel, 2678678453a8Sspeer size_index, 2679678453a8Sspeer rx_dmap[i].alength)); 268044961713Sgirish size_index--; 268144961713Sgirish } else { 2682678453a8Sspeer rx_dmap[i].buf_alloc_state = BUF_ALLOCATED; 2683678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2684678453a8Sspeer " nxge_alloc_rx_buf_dma DONE alloc mem: " 2685678453a8Sspeer "dma %d dma_buf_p $%p kaddrp $%p alength %d " 2686678453a8Sspeer "buf_alloc_state %d alloc_type %d", 2687678453a8Sspeer dma_channel, 2688678453a8Sspeer &rx_dmap[i], 2689678453a8Sspeer rx_dmap[i].kaddrp, 2690678453a8Sspeer rx_dmap[i].alength, 2691678453a8Sspeer rx_dmap[i].buf_alloc_state, 2692678453a8Sspeer rx_dmap[i].buf_alloc_type)); 2693678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2694678453a8Sspeer " alloc_rx_buf_dma allocated rdc %d " 2695678453a8Sspeer "chunk %d size %x dvma %x bufp %llx kaddrp $%p", 2696678453a8Sspeer dma_channel, i, rx_dmap[i].alength, 2697678453a8Sspeer rx_dmap[i].ioaddr_pp, &rx_dmap[i], 2698678453a8Sspeer rx_dmap[i].kaddrp)); 269944961713Sgirish i++; 270044961713Sgirish allocated += alloc_sizes[size_index]; 270144961713Sgirish } 270244961713Sgirish } 270344961713Sgirish 270444961713Sgirish if (allocated < total_alloc_size) { 270530ac2e7bSml NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2706678453a8Sspeer "==> nxge_alloc_rx_buf_dma: not enough for channel %d " 270730ac2e7bSml "allocated 0x%x requested 0x%x", 270830ac2e7bSml dma_channel, 270930ac2e7bSml allocated, total_alloc_size)); 271030ac2e7bSml status = NXGE_ERROR; 271144961713Sgirish goto nxge_alloc_rx_mem_fail1; 271244961713Sgirish } 271344961713Sgirish 271430ac2e7bSml NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2715678453a8Sspeer "==> nxge_alloc_rx_buf_dma: Allocated for channel %d " 271630ac2e7bSml "allocated 0x%x requested 0x%x", 271730ac2e7bSml dma_channel, 271830ac2e7bSml allocated, total_alloc_size)); 271930ac2e7bSml 272044961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 27214045d941Ssowmini " alloc_rx_buf_dma rdc %d allocated %d chunks", 27224045d941Ssowmini dma_channel, i)); 272344961713Sgirish *num_chunks = i; 272444961713Sgirish *dmap = rx_dmap; 272544961713Sgirish 272644961713Sgirish goto nxge_alloc_rx_mem_exit; 272744961713Sgirish 272844961713Sgirish nxge_alloc_rx_mem_fail1: 272944961713Sgirish KMEM_FREE(rx_dmap, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK); 273044961713Sgirish 273144961713Sgirish nxge_alloc_rx_mem_exit: 273244961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 27334045d941Ssowmini "<== nxge_alloc_rx_buf_dma status 0x%08x", status)); 273444961713Sgirish 273544961713Sgirish return (status); 273644961713Sgirish } 273744961713Sgirish 273844961713Sgirish /*ARGSUSED*/ 273944961713Sgirish static void 274044961713Sgirish nxge_free_rx_buf_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap, 274144961713Sgirish uint32_t num_chunks) 274244961713Sgirish { 274344961713Sgirish int i; 274444961713Sgirish 274544961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 27464045d941Ssowmini "==> nxge_free_rx_buf_dma: # of chunks %d", num_chunks)); 274744961713Sgirish 2748678453a8Sspeer if (dmap == 0) 2749678453a8Sspeer return; 2750678453a8Sspeer 275144961713Sgirish for (i = 0; i < num_chunks; i++) { 275244961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 27534045d941Ssowmini "==> nxge_free_rx_buf_dma: chunk %d dmap 0x%llx", 27544045d941Ssowmini i, dmap)); 2755678453a8Sspeer nxge_dma_free_rx_data_buf(dmap++); 275644961713Sgirish } 275744961713Sgirish 275844961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_free_rx_buf_dma")); 275944961713Sgirish } 276044961713Sgirish 276144961713Sgirish /*ARGSUSED*/ 276244961713Sgirish static nxge_status_t 276344961713Sgirish nxge_alloc_rx_cntl_dma(p_nxge_t nxgep, uint16_t dma_channel, 276444961713Sgirish p_nxge_dma_common_t *dmap, size_t size) 276544961713Sgirish { 276644961713Sgirish p_nxge_dma_common_t rx_dmap; 276744961713Sgirish nxge_status_t status = NXGE_OK; 276844961713Sgirish 276944961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rx_cntl_dma")); 277044961713Sgirish 277144961713Sgirish rx_dmap = (p_nxge_dma_common_t) 27724045d941Ssowmini KMEM_ZALLOC(sizeof (nxge_dma_common_t), KM_SLEEP); 277344961713Sgirish 277444961713Sgirish rx_dmap->contig_alloc_type = B_FALSE; 2775678453a8Sspeer rx_dmap->kmem_alloc_type = B_FALSE; 277644961713Sgirish 277744961713Sgirish status = nxge_dma_mem_alloc(nxgep, nxge_force_dma, 27784045d941Ssowmini &nxge_desc_dma_attr, 27794045d941Ssowmini size, 27804045d941Ssowmini &nxge_dev_desc_dma_acc_attr, 27814045d941Ssowmini DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 27824045d941Ssowmini rx_dmap); 278344961713Sgirish if (status != NXGE_OK) { 278444961713Sgirish goto nxge_alloc_rx_cntl_dma_fail1; 278544961713Sgirish } 278644961713Sgirish 278744961713Sgirish *dmap = rx_dmap; 278844961713Sgirish goto nxge_alloc_rx_cntl_dma_exit; 278944961713Sgirish 279044961713Sgirish nxge_alloc_rx_cntl_dma_fail1: 279144961713Sgirish KMEM_FREE(rx_dmap, sizeof (nxge_dma_common_t)); 279244961713Sgirish 279344961713Sgirish nxge_alloc_rx_cntl_dma_exit: 279444961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 27954045d941Ssowmini "<== nxge_alloc_rx_cntl_dma status 0x%08x", status)); 279644961713Sgirish 2797678453a8Sspeer return (status); 2798678453a8Sspeer } 2799678453a8Sspeer 2800678453a8Sspeer /*ARGSUSED*/ 2801678453a8Sspeer static void 2802678453a8Sspeer nxge_free_rx_cntl_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap) 2803678453a8Sspeer { 2804678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_free_rx_cntl_dma")); 2805678453a8Sspeer 2806678453a8Sspeer if (dmap == 0) 2807678453a8Sspeer return; 2808678453a8Sspeer 2809678453a8Sspeer nxge_dma_mem_free(dmap); 2810678453a8Sspeer 2811678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_free_rx_cntl_dma")); 2812678453a8Sspeer } 2813678453a8Sspeer 2814678453a8Sspeer typedef struct { 2815678453a8Sspeer size_t tx_size; 2816678453a8Sspeer size_t cr_size; 2817678453a8Sspeer size_t threshhold; 2818678453a8Sspeer } nxge_tdc_sizes_t; 2819678453a8Sspeer 2820678453a8Sspeer static 2821678453a8Sspeer nxge_status_t 2822678453a8Sspeer nxge_tdc_sizes( 2823678453a8Sspeer nxge_t *nxgep, 2824678453a8Sspeer nxge_tdc_sizes_t *sizes) 2825678453a8Sspeer { 2826678453a8Sspeer uint32_t threshhold; /* The bcopy() threshhold */ 2827678453a8Sspeer size_t tx_size; /* Transmit buffer size */ 2828678453a8Sspeer size_t cr_size; /* Completion ring size */ 2829678453a8Sspeer 2830678453a8Sspeer /* 2831678453a8Sspeer * Assume that each DMA channel will be configured with the 2832678453a8Sspeer * default transmit buffer size for copying transmit data. 2833678453a8Sspeer * (If a packet is bigger than this, it will not be copied.) 2834678453a8Sspeer */ 2835678453a8Sspeer if (nxgep->niu_type == N2_NIU) { 2836678453a8Sspeer threshhold = TX_BCOPY_SIZE; 2837678453a8Sspeer } else { 2838678453a8Sspeer threshhold = nxge_bcopy_thresh; 2839678453a8Sspeer } 2840678453a8Sspeer tx_size = nxge_tx_ring_size * threshhold; 2841678453a8Sspeer 2842678453a8Sspeer cr_size = nxge_tx_ring_size * sizeof (tx_desc_t); 2843678453a8Sspeer cr_size += sizeof (txdma_mailbox_t); 2844678453a8Sspeer 2845678453a8Sspeer #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 2846678453a8Sspeer if (nxgep->niu_type == N2_NIU) { 2847678453a8Sspeer if (!ISP2(tx_size)) { 2848678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 28494045d941Ssowmini "==> nxge_tdc_sizes: Tx size" 28504045d941Ssowmini " must be power of 2")); 2851678453a8Sspeer return (NXGE_ERROR); 2852678453a8Sspeer } 2853678453a8Sspeer 2854678453a8Sspeer if (tx_size > (1 << 22)) { 2855678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 28564045d941Ssowmini "==> nxge_tdc_sizes: Tx size" 28574045d941Ssowmini " limited to 4M")); 2858678453a8Sspeer return (NXGE_ERROR); 2859678453a8Sspeer } 2860678453a8Sspeer 2861678453a8Sspeer if (cr_size < 0x2000) 2862678453a8Sspeer cr_size = 0x2000; 2863678453a8Sspeer } 2864678453a8Sspeer #endif 2865678453a8Sspeer 2866678453a8Sspeer sizes->threshhold = threshhold; 2867678453a8Sspeer sizes->tx_size = tx_size; 2868678453a8Sspeer sizes->cr_size = cr_size; 2869678453a8Sspeer 2870678453a8Sspeer return (NXGE_OK); 2871678453a8Sspeer } 2872678453a8Sspeer /* 2873678453a8Sspeer * nxge_alloc_txb 2874678453a8Sspeer * 2875678453a8Sspeer * Allocate buffers for an TDC. 2876678453a8Sspeer * 2877678453a8Sspeer * Arguments: 2878678453a8Sspeer * nxgep 2879678453a8Sspeer * channel The channel to map into our kernel space. 2880678453a8Sspeer * 2881678453a8Sspeer * Notes: 2882678453a8Sspeer * 2883678453a8Sspeer * NPI function calls: 2884678453a8Sspeer * 2885678453a8Sspeer * NXGE function calls: 2886678453a8Sspeer * 2887678453a8Sspeer * Registers accessed: 2888678453a8Sspeer * 2889678453a8Sspeer * Context: 2890678453a8Sspeer * 2891678453a8Sspeer * Taking apart: 2892678453a8Sspeer * 2893678453a8Sspeer * Open questions: 2894678453a8Sspeer * 2895678453a8Sspeer */ 2896678453a8Sspeer nxge_status_t 2897678453a8Sspeer nxge_alloc_txb( 2898678453a8Sspeer p_nxge_t nxgep, 2899678453a8Sspeer int channel) 2900678453a8Sspeer { 2901678453a8Sspeer nxge_dma_common_t **dma_buf_p; 2902678453a8Sspeer nxge_dma_common_t **dma_cntl_p; 2903678453a8Sspeer uint32_t *num_chunks; 2904678453a8Sspeer nxge_status_t status = NXGE_OK; 2905678453a8Sspeer 2906678453a8Sspeer nxge_tdc_sizes_t sizes; 2907678453a8Sspeer 2908678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_tbb")); 2909678453a8Sspeer 2910678453a8Sspeer if (nxge_tdc_sizes(nxgep, &sizes) != NXGE_OK) 2911678453a8Sspeer return (NXGE_ERROR); 2912678453a8Sspeer 2913678453a8Sspeer /* 2914678453a8Sspeer * Allocate memory for transmit buffers and descriptor rings. 2915678453a8Sspeer * Replace these allocation functions with the interface functions 2916678453a8Sspeer * provided by the partition manager Real Soon Now. 2917678453a8Sspeer */ 2918678453a8Sspeer dma_buf_p = &nxgep->tx_buf_pool_p->dma_buf_pool_p[channel]; 2919678453a8Sspeer num_chunks = &nxgep->tx_buf_pool_p->num_chunks[channel]; 2920678453a8Sspeer 2921678453a8Sspeer dma_cntl_p = &nxgep->tx_cntl_pool_p->dma_buf_pool_p[channel]; 2922678453a8Sspeer 2923678453a8Sspeer /* 2924678453a8Sspeer * Allocate memory for transmit buffers and descriptor rings. 2925678453a8Sspeer * Replace allocation functions with interface functions provided 2926678453a8Sspeer * by the partition manager when it is available. 2927678453a8Sspeer * 2928678453a8Sspeer * Allocate memory for the transmit buffer pool. 2929678453a8Sspeer */ 2930678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, 29314045d941Ssowmini "sizes: tx: %ld, cr:%ld, th:%ld", 29324045d941Ssowmini sizes.tx_size, sizes.cr_size, sizes.threshhold)); 2933678453a8Sspeer 2934678453a8Sspeer *num_chunks = 0; 2935678453a8Sspeer status = nxge_alloc_tx_buf_dma(nxgep, channel, dma_buf_p, 2936678453a8Sspeer sizes.tx_size, sizes.threshhold, num_chunks); 2937678453a8Sspeer if (status != NXGE_OK) { 2938678453a8Sspeer cmn_err(CE_NOTE, "nxge_alloc_tx_buf_dma failed!"); 2939678453a8Sspeer return (status); 2940678453a8Sspeer } 2941678453a8Sspeer 2942678453a8Sspeer /* 2943678453a8Sspeer * Allocate memory for descriptor rings and mailbox. 2944678453a8Sspeer */ 2945678453a8Sspeer status = nxge_alloc_tx_cntl_dma(nxgep, channel, dma_cntl_p, 2946678453a8Sspeer sizes.cr_size); 2947678453a8Sspeer if (status != NXGE_OK) { 2948678453a8Sspeer nxge_free_tx_buf_dma(nxgep, *dma_buf_p, *num_chunks); 2949678453a8Sspeer cmn_err(CE_NOTE, "nxge_alloc_tx_cntl_dma failed!"); 2950678453a8Sspeer return (status); 2951678453a8Sspeer } 2952678453a8Sspeer 2953678453a8Sspeer return (NXGE_OK); 2954678453a8Sspeer } 2955678453a8Sspeer 2956678453a8Sspeer void 2957678453a8Sspeer nxge_free_txb( 2958678453a8Sspeer p_nxge_t nxgep, 2959678453a8Sspeer int channel) 2960678453a8Sspeer { 2961678453a8Sspeer nxge_dma_common_t *data; 2962678453a8Sspeer nxge_dma_common_t *control; 2963678453a8Sspeer uint32_t num_chunks; 2964678453a8Sspeer 2965678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_free_txb")); 2966678453a8Sspeer 2967678453a8Sspeer data = nxgep->tx_buf_pool_p->dma_buf_pool_p[channel]; 2968678453a8Sspeer num_chunks = nxgep->tx_buf_pool_p->num_chunks[channel]; 2969678453a8Sspeer nxge_free_tx_buf_dma(nxgep, data, num_chunks); 2970678453a8Sspeer 2971678453a8Sspeer nxgep->tx_buf_pool_p->dma_buf_pool_p[channel] = 0; 2972678453a8Sspeer nxgep->tx_buf_pool_p->num_chunks[channel] = 0; 2973678453a8Sspeer 2974678453a8Sspeer control = nxgep->tx_cntl_pool_p->dma_buf_pool_p[channel]; 2975678453a8Sspeer nxge_free_tx_cntl_dma(nxgep, control); 297644961713Sgirish 2977678453a8Sspeer nxgep->tx_cntl_pool_p->dma_buf_pool_p[channel] = 0; 297844961713Sgirish 2979678453a8Sspeer KMEM_FREE(data, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK); 2980678453a8Sspeer KMEM_FREE(control, sizeof (nxge_dma_common_t)); 298144961713Sgirish 2982678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_free_txb")); 298344961713Sgirish } 298444961713Sgirish 2985678453a8Sspeer /* 2986678453a8Sspeer * nxge_alloc_tx_mem_pool 2987678453a8Sspeer * 2988678453a8Sspeer * This function allocates all of the per-port TDC control data structures. 2989678453a8Sspeer * The per-channel (TDC) data structures are allocated when needed. 2990678453a8Sspeer * 2991678453a8Sspeer * Arguments: 2992678453a8Sspeer * nxgep 2993678453a8Sspeer * 2994678453a8Sspeer * Notes: 2995678453a8Sspeer * 2996678453a8Sspeer * Context: 2997678453a8Sspeer * Any domain 2998678453a8Sspeer */ 2999678453a8Sspeer nxge_status_t 300044961713Sgirish nxge_alloc_tx_mem_pool(p_nxge_t nxgep) 300144961713Sgirish { 3002678453a8Sspeer nxge_hw_pt_cfg_t *p_cfgp; 3003678453a8Sspeer nxge_dma_pool_t *dma_poolp; 3004678453a8Sspeer nxge_dma_common_t **dma_buf_p; 3005678453a8Sspeer nxge_dma_pool_t *dma_cntl_poolp; 3006678453a8Sspeer nxge_dma_common_t **dma_cntl_p; 300744961713Sgirish uint32_t *num_chunks; /* per dma */ 3008678453a8Sspeer int tdc_max; 300944961713Sgirish 301044961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM_CTL, "==> nxge_alloc_tx_mem_pool")); 301144961713Sgirish 3012678453a8Sspeer p_cfgp = &nxgep->pt_config.hw_config; 3013678453a8Sspeer tdc_max = NXGE_MAX_TDCS; 301444961713Sgirish 301544961713Sgirish /* 301644961713Sgirish * Allocate memory for each transmit DMA channel. 301744961713Sgirish */ 301844961713Sgirish dma_poolp = (p_nxge_dma_pool_t)KMEM_ZALLOC(sizeof (nxge_dma_pool_t), 30194045d941Ssowmini KM_SLEEP); 302044961713Sgirish dma_buf_p = (p_nxge_dma_common_t *)KMEM_ZALLOC( 30214045d941Ssowmini sizeof (p_nxge_dma_common_t) * tdc_max, KM_SLEEP); 302244961713Sgirish 302344961713Sgirish dma_cntl_poolp = (p_nxge_dma_pool_t) 30244045d941Ssowmini KMEM_ZALLOC(sizeof (nxge_dma_pool_t), KM_SLEEP); 302544961713Sgirish dma_cntl_p = (p_nxge_dma_common_t *)KMEM_ZALLOC( 30264045d941Ssowmini sizeof (p_nxge_dma_common_t) * tdc_max, KM_SLEEP); 302744961713Sgirish 302830ac2e7bSml if (nxge_tx_ring_size > TDC_DEFAULT_MAX) { 302930ac2e7bSml NXGE_DEBUG_MSG((nxgep, MEM_CTL, 303030ac2e7bSml "nxge_alloc_tx_mem_pool: TDC too high %d, " 303130ac2e7bSml "set to default %d", 303230ac2e7bSml nxge_tx_ring_size, TDC_DEFAULT_MAX)); 303330ac2e7bSml nxge_tx_ring_size = TDC_DEFAULT_MAX; 303430ac2e7bSml } 303530ac2e7bSml 303644961713Sgirish #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 303744961713Sgirish /* 303844961713Sgirish * N2/NIU has limitation on the descriptor sizes (contiguous 303944961713Sgirish * memory allocation on data buffers to 4M (contig_mem_alloc) 304044961713Sgirish * and little endian for control buffers (must use the ddi/dki mem alloc 304144961713Sgirish * function). The transmit ring is limited to 8K (includes the 304244961713Sgirish * mailbox). 304344961713Sgirish */ 304444961713Sgirish if (nxgep->niu_type == N2_NIU) { 304544961713Sgirish if ((nxge_tx_ring_size > NXGE_NIU_CONTIG_TX_MAX) || 30464045d941Ssowmini (!ISP2(nxge_tx_ring_size))) { 304744961713Sgirish nxge_tx_ring_size = NXGE_NIU_CONTIG_TX_MAX; 304844961713Sgirish } 304944961713Sgirish } 305044961713Sgirish #endif 305144961713Sgirish 305244961713Sgirish nxgep->nxge_port_tx_ring_size = nxge_tx_ring_size; 305344961713Sgirish 305444961713Sgirish num_chunks = (uint32_t *)KMEM_ZALLOC( 30554045d941Ssowmini sizeof (uint32_t) * tdc_max, KM_SLEEP); 305644961713Sgirish 3057678453a8Sspeer dma_poolp->ndmas = p_cfgp->tdc.owned; 305844961713Sgirish dma_poolp->num_chunks = num_chunks; 305944961713Sgirish dma_poolp->dma_buf_pool_p = dma_buf_p; 306044961713Sgirish nxgep->tx_buf_pool_p = dma_poolp; 306144961713Sgirish 3062678453a8Sspeer dma_poolp->buf_allocated = B_TRUE; 3063678453a8Sspeer 3064678453a8Sspeer dma_cntl_poolp->ndmas = p_cfgp->tdc.owned; 306544961713Sgirish dma_cntl_poolp->dma_buf_pool_p = dma_cntl_p; 306644961713Sgirish nxgep->tx_cntl_pool_p = dma_cntl_poolp; 306744961713Sgirish 3068678453a8Sspeer dma_cntl_poolp->buf_allocated = B_TRUE; 306944961713Sgirish 3070678453a8Sspeer nxgep->tx_rings = 3071678453a8Sspeer KMEM_ZALLOC(sizeof (tx_rings_t), KM_SLEEP); 3072678453a8Sspeer nxgep->tx_rings->rings = 3073678453a8Sspeer KMEM_ZALLOC(sizeof (p_tx_ring_t) * tdc_max, KM_SLEEP); 3074678453a8Sspeer nxgep->tx_mbox_areas_p = 3075678453a8Sspeer KMEM_ZALLOC(sizeof (tx_mbox_areas_t), KM_SLEEP); 3076678453a8Sspeer nxgep->tx_mbox_areas_p->txmbox_areas_p = 3077678453a8Sspeer KMEM_ZALLOC(sizeof (p_tx_mbox_t) * tdc_max, KM_SLEEP); 307844961713Sgirish 3079678453a8Sspeer nxgep->tx_rings->ndmas = p_cfgp->tdc.owned; 308044961713Sgirish 308144961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM_CTL, 30824045d941Ssowmini "==> nxge_alloc_tx_mem_pool: ndmas %d poolp->ndmas %d", 30834045d941Ssowmini tdc_max, dma_poolp->ndmas)); 308444961713Sgirish 3085678453a8Sspeer return (NXGE_OK); 308644961713Sgirish } 308744961713Sgirish 3088678453a8Sspeer nxge_status_t 308944961713Sgirish nxge_alloc_tx_buf_dma(p_nxge_t nxgep, uint16_t dma_channel, 309044961713Sgirish p_nxge_dma_common_t *dmap, size_t alloc_size, 309144961713Sgirish size_t block_size, uint32_t *num_chunks) 309244961713Sgirish { 309344961713Sgirish p_nxge_dma_common_t tx_dmap; 309444961713Sgirish nxge_status_t status = NXGE_OK; 309544961713Sgirish size_t total_alloc_size; 309644961713Sgirish size_t allocated = 0; 309744961713Sgirish int i, size_index, array_size; 309844961713Sgirish 309944961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_tx_buf_dma")); 310044961713Sgirish 310144961713Sgirish tx_dmap = (p_nxge_dma_common_t) 31024045d941Ssowmini KMEM_ZALLOC(sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK, 31034045d941Ssowmini KM_SLEEP); 310444961713Sgirish 310544961713Sgirish total_alloc_size = alloc_size; 310644961713Sgirish i = 0; 310744961713Sgirish size_index = 0; 310844961713Sgirish array_size = sizeof (alloc_sizes) / sizeof (size_t); 31097b26d9ffSSantwona Behera while ((size_index < array_size) && 31107b26d9ffSSantwona Behera (alloc_sizes[size_index] < alloc_size)) 311144961713Sgirish size_index++; 311244961713Sgirish if (size_index >= array_size) { 311344961713Sgirish size_index = array_size - 1; 311444961713Sgirish } 311544961713Sgirish 311644961713Sgirish while ((allocated < total_alloc_size) && 31174045d941Ssowmini (size_index >= 0) && (i < NXGE_DMA_BLOCK)) { 311844961713Sgirish 311944961713Sgirish tx_dmap[i].dma_chunk_index = i; 312044961713Sgirish tx_dmap[i].block_size = block_size; 312144961713Sgirish tx_dmap[i].alength = alloc_sizes[size_index]; 312244961713Sgirish tx_dmap[i].orig_alength = tx_dmap[i].alength; 312344961713Sgirish tx_dmap[i].nblocks = alloc_sizes[size_index] / block_size; 312444961713Sgirish tx_dmap[i].dma_channel = dma_channel; 312544961713Sgirish tx_dmap[i].contig_alloc_type = B_FALSE; 3126678453a8Sspeer tx_dmap[i].kmem_alloc_type = B_FALSE; 312744961713Sgirish 312844961713Sgirish /* 312944961713Sgirish * N2/NIU: data buffers must be contiguous as the driver 313044961713Sgirish * needs to call Hypervisor api to set up 313144961713Sgirish * logical pages. 313244961713Sgirish */ 313344961713Sgirish if ((nxgep->niu_type == N2_NIU) && (NXGE_DMA_BLOCK == 1)) { 313444961713Sgirish tx_dmap[i].contig_alloc_type = B_TRUE; 313544961713Sgirish } 313644961713Sgirish 313744961713Sgirish status = nxge_dma_mem_alloc(nxgep, nxge_force_dma, 31384045d941Ssowmini &nxge_tx_dma_attr, 31394045d941Ssowmini tx_dmap[i].alength, 31404045d941Ssowmini &nxge_dev_buf_dma_acc_attr, 31414045d941Ssowmini DDI_DMA_WRITE | DDI_DMA_STREAMING, 31424045d941Ssowmini (p_nxge_dma_common_t)(&tx_dmap[i])); 314344961713Sgirish if (status != NXGE_OK) { 314444961713Sgirish size_index--; 314544961713Sgirish } else { 314644961713Sgirish i++; 314744961713Sgirish allocated += alloc_sizes[size_index]; 314844961713Sgirish } 314944961713Sgirish } 315044961713Sgirish 315144961713Sgirish if (allocated < total_alloc_size) { 315230ac2e7bSml NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 315330ac2e7bSml "==> nxge_alloc_tx_buf_dma: not enough channel %d: " 315430ac2e7bSml "allocated 0x%x requested 0x%x", 315530ac2e7bSml dma_channel, 315630ac2e7bSml allocated, total_alloc_size)); 315730ac2e7bSml status = NXGE_ERROR; 315844961713Sgirish goto nxge_alloc_tx_mem_fail1; 315944961713Sgirish } 316044961713Sgirish 316130ac2e7bSml NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 316230ac2e7bSml "==> nxge_alloc_tx_buf_dma: Allocated for channel %d: " 316330ac2e7bSml "allocated 0x%x requested 0x%x", 316430ac2e7bSml dma_channel, 316530ac2e7bSml allocated, total_alloc_size)); 316630ac2e7bSml 316744961713Sgirish *num_chunks = i; 316844961713Sgirish *dmap = tx_dmap; 316944961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 31704045d941Ssowmini "==> nxge_alloc_tx_buf_dma dmap 0x%016llx num chunks %d", 31714045d941Ssowmini *dmap, i)); 317244961713Sgirish goto nxge_alloc_tx_mem_exit; 317344961713Sgirish 317444961713Sgirish nxge_alloc_tx_mem_fail1: 317544961713Sgirish KMEM_FREE(tx_dmap, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK); 317644961713Sgirish 317744961713Sgirish nxge_alloc_tx_mem_exit: 317844961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 31794045d941Ssowmini "<== nxge_alloc_tx_buf_dma status 0x%08x", status)); 318044961713Sgirish 318144961713Sgirish return (status); 318244961713Sgirish } 318344961713Sgirish 318444961713Sgirish /*ARGSUSED*/ 318544961713Sgirish static void 318644961713Sgirish nxge_free_tx_buf_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap, 318744961713Sgirish uint32_t num_chunks) 318844961713Sgirish { 318944961713Sgirish int i; 319044961713Sgirish 319144961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM_CTL, "==> nxge_free_tx_buf_dma")); 319244961713Sgirish 3193678453a8Sspeer if (dmap == 0) 3194678453a8Sspeer return; 3195678453a8Sspeer 319644961713Sgirish for (i = 0; i < num_chunks; i++) { 319744961713Sgirish nxge_dma_mem_free(dmap++); 319844961713Sgirish } 319944961713Sgirish 320044961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM_CTL, "<== nxge_free_tx_buf_dma")); 320144961713Sgirish } 320244961713Sgirish 320344961713Sgirish /*ARGSUSED*/ 3204678453a8Sspeer nxge_status_t 320544961713Sgirish nxge_alloc_tx_cntl_dma(p_nxge_t nxgep, uint16_t dma_channel, 320644961713Sgirish p_nxge_dma_common_t *dmap, size_t size) 320744961713Sgirish { 320844961713Sgirish p_nxge_dma_common_t tx_dmap; 320944961713Sgirish nxge_status_t status = NXGE_OK; 321044961713Sgirish 321144961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_tx_cntl_dma")); 321244961713Sgirish tx_dmap = (p_nxge_dma_common_t) 32134045d941Ssowmini KMEM_ZALLOC(sizeof (nxge_dma_common_t), KM_SLEEP); 321444961713Sgirish 321544961713Sgirish tx_dmap->contig_alloc_type = B_FALSE; 3216678453a8Sspeer tx_dmap->kmem_alloc_type = B_FALSE; 321744961713Sgirish 321844961713Sgirish status = nxge_dma_mem_alloc(nxgep, nxge_force_dma, 32194045d941Ssowmini &nxge_desc_dma_attr, 32204045d941Ssowmini size, 32214045d941Ssowmini &nxge_dev_desc_dma_acc_attr, 32224045d941Ssowmini DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 32234045d941Ssowmini tx_dmap); 322444961713Sgirish if (status != NXGE_OK) { 322544961713Sgirish goto nxge_alloc_tx_cntl_dma_fail1; 322644961713Sgirish } 322744961713Sgirish 322844961713Sgirish *dmap = tx_dmap; 322944961713Sgirish goto nxge_alloc_tx_cntl_dma_exit; 323044961713Sgirish 323144961713Sgirish nxge_alloc_tx_cntl_dma_fail1: 323244961713Sgirish KMEM_FREE(tx_dmap, sizeof (nxge_dma_common_t)); 323344961713Sgirish 323444961713Sgirish nxge_alloc_tx_cntl_dma_exit: 323544961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 32364045d941Ssowmini "<== nxge_alloc_tx_cntl_dma status 0x%08x", status)); 323744961713Sgirish 323844961713Sgirish return (status); 323944961713Sgirish } 324044961713Sgirish 324144961713Sgirish /*ARGSUSED*/ 324244961713Sgirish static void 324344961713Sgirish nxge_free_tx_cntl_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap) 324444961713Sgirish { 324544961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_free_tx_cntl_dma")); 324644961713Sgirish 3247678453a8Sspeer if (dmap == 0) 3248678453a8Sspeer return; 3249678453a8Sspeer 325044961713Sgirish nxge_dma_mem_free(dmap); 325144961713Sgirish 325244961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_free_tx_cntl_dma")); 325344961713Sgirish } 325444961713Sgirish 3255678453a8Sspeer /* 3256678453a8Sspeer * nxge_free_tx_mem_pool 3257678453a8Sspeer * 3258678453a8Sspeer * This function frees all of the per-port TDC control data structures. 3259678453a8Sspeer * The per-channel (TDC) data structures are freed when the channel 3260678453a8Sspeer * is stopped. 3261678453a8Sspeer * 3262678453a8Sspeer * Arguments: 3263678453a8Sspeer * nxgep 3264678453a8Sspeer * 3265678453a8Sspeer * Notes: 3266678453a8Sspeer * 3267678453a8Sspeer * Context: 3268678453a8Sspeer * Any domain 3269678453a8Sspeer */ 327044961713Sgirish static void 327144961713Sgirish nxge_free_tx_mem_pool(p_nxge_t nxgep) 327244961713Sgirish { 3273678453a8Sspeer int tdc_max = NXGE_MAX_TDCS; 327444961713Sgirish 3275678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_free_tx_mem_pool")); 327644961713Sgirish 3277678453a8Sspeer if (!nxgep->tx_buf_pool_p || !nxgep->tx_buf_pool_p->buf_allocated) { 3278678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 32794045d941Ssowmini "<== nxge_free_tx_mem_pool " 32804045d941Ssowmini "(null tx buf pool or buf not allocated")); 328144961713Sgirish return; 328244961713Sgirish } 3283678453a8Sspeer if (!nxgep->tx_cntl_pool_p || !nxgep->tx_cntl_pool_p->buf_allocated) { 3284678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 32854045d941Ssowmini "<== nxge_free_tx_mem_pool " 32864045d941Ssowmini "(null tx cntl buf pool or cntl buf not allocated")); 328744961713Sgirish return; 328844961713Sgirish } 328944961713Sgirish 3290678453a8Sspeer /* 1. Free the mailboxes. */ 3291678453a8Sspeer KMEM_FREE(nxgep->tx_mbox_areas_p->txmbox_areas_p, 3292678453a8Sspeer sizeof (p_tx_mbox_t) * tdc_max); 3293678453a8Sspeer KMEM_FREE(nxgep->tx_mbox_areas_p, sizeof (tx_mbox_areas_t)); 329444961713Sgirish 3295678453a8Sspeer nxgep->tx_mbox_areas_p = 0; 329644961713Sgirish 3297678453a8Sspeer /* 2. Free the transmit ring arrays. */ 3298678453a8Sspeer KMEM_FREE(nxgep->tx_rings->rings, 3299678453a8Sspeer sizeof (p_tx_ring_t) * tdc_max); 3300678453a8Sspeer KMEM_FREE(nxgep->tx_rings, sizeof (tx_rings_t)); 330144961713Sgirish 3302678453a8Sspeer nxgep->tx_rings = 0; 330344961713Sgirish 3304678453a8Sspeer /* 3. Free the completion ring data structures. */ 3305678453a8Sspeer KMEM_FREE(nxgep->tx_cntl_pool_p->dma_buf_pool_p, 3306678453a8Sspeer sizeof (p_nxge_dma_common_t) * tdc_max); 3307678453a8Sspeer KMEM_FREE(nxgep->tx_cntl_pool_p, sizeof (nxge_dma_pool_t)); 330844961713Sgirish 3309678453a8Sspeer nxgep->tx_cntl_pool_p = 0; 331044961713Sgirish 3311678453a8Sspeer /* 4. Free the data ring data structures. */ 3312678453a8Sspeer KMEM_FREE(nxgep->tx_buf_pool_p->num_chunks, 3313678453a8Sspeer sizeof (uint32_t) * tdc_max); 3314678453a8Sspeer KMEM_FREE(nxgep->tx_buf_pool_p->dma_buf_pool_p, 3315678453a8Sspeer sizeof (p_nxge_dma_common_t) * tdc_max); 3316678453a8Sspeer KMEM_FREE(nxgep->tx_buf_pool_p, sizeof (nxge_dma_pool_t)); 331744961713Sgirish 3318678453a8Sspeer nxgep->tx_buf_pool_p = 0; 3319678453a8Sspeer 3320678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_free_tx_mem_pool")); 332144961713Sgirish } 332244961713Sgirish 332344961713Sgirish /*ARGSUSED*/ 332444961713Sgirish static nxge_status_t 332544961713Sgirish nxge_dma_mem_alloc(p_nxge_t nxgep, dma_method_t method, 332644961713Sgirish struct ddi_dma_attr *dma_attrp, 332744961713Sgirish size_t length, ddi_device_acc_attr_t *acc_attr_p, uint_t xfer_flags, 332844961713Sgirish p_nxge_dma_common_t dma_p) 332944961713Sgirish { 333044961713Sgirish caddr_t kaddrp; 333144961713Sgirish int ddi_status = DDI_SUCCESS; 333244961713Sgirish boolean_t contig_alloc_type; 3333678453a8Sspeer boolean_t kmem_alloc_type; 333444961713Sgirish 333544961713Sgirish contig_alloc_type = dma_p->contig_alloc_type; 333644961713Sgirish 333744961713Sgirish if (contig_alloc_type && (nxgep->niu_type != N2_NIU)) { 333844961713Sgirish /* 333944961713Sgirish * contig_alloc_type for contiguous memory only allowed 334044961713Sgirish * for N2/NIU. 334144961713Sgirish */ 334244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 33434045d941Ssowmini "nxge_dma_mem_alloc: alloc type not allowed (%d)", 33444045d941Ssowmini dma_p->contig_alloc_type)); 334544961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 334644961713Sgirish } 334744961713Sgirish 334844961713Sgirish dma_p->dma_handle = NULL; 334944961713Sgirish dma_p->acc_handle = NULL; 335044961713Sgirish dma_p->kaddrp = dma_p->last_kaddrp = NULL; 335144961713Sgirish dma_p->first_ioaddr_pp = dma_p->last_ioaddr_pp = NULL; 335244961713Sgirish ddi_status = ddi_dma_alloc_handle(nxgep->dip, dma_attrp, 33534045d941Ssowmini DDI_DMA_DONTWAIT, NULL, &dma_p->dma_handle); 335444961713Sgirish if (ddi_status != DDI_SUCCESS) { 335544961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 33564045d941Ssowmini "nxge_dma_mem_alloc:ddi_dma_alloc_handle failed.")); 335744961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 335844961713Sgirish } 335944961713Sgirish 3360678453a8Sspeer kmem_alloc_type = dma_p->kmem_alloc_type; 3361678453a8Sspeer 336244961713Sgirish switch (contig_alloc_type) { 336344961713Sgirish case B_FALSE: 3364678453a8Sspeer switch (kmem_alloc_type) { 3365678453a8Sspeer case B_FALSE: 3366678453a8Sspeer ddi_status = ddi_dma_mem_alloc(dma_p->dma_handle, 33674045d941Ssowmini length, 33684045d941Ssowmini acc_attr_p, 33694045d941Ssowmini xfer_flags, 33704045d941Ssowmini DDI_DMA_DONTWAIT, 0, &kaddrp, &dma_p->alength, 33714045d941Ssowmini &dma_p->acc_handle); 3372678453a8Sspeer if (ddi_status != DDI_SUCCESS) { 3373678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3374678453a8Sspeer "nxge_dma_mem_alloc: " 3375678453a8Sspeer "ddi_dma_mem_alloc failed")); 3376678453a8Sspeer ddi_dma_free_handle(&dma_p->dma_handle); 3377678453a8Sspeer dma_p->dma_handle = NULL; 3378678453a8Sspeer return (NXGE_ERROR | NXGE_DDI_FAILED); 3379678453a8Sspeer } 3380678453a8Sspeer if (dma_p->alength < length) { 3381678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3382678453a8Sspeer "nxge_dma_mem_alloc:di_dma_mem_alloc " 3383678453a8Sspeer "< length.")); 338444961713Sgirish ddi_dma_mem_free(&dma_p->acc_handle); 3385678453a8Sspeer ddi_dma_free_handle(&dma_p->dma_handle); 338644961713Sgirish dma_p->acc_handle = NULL; 3387678453a8Sspeer dma_p->dma_handle = NULL; 3388678453a8Sspeer return (NXGE_ERROR); 338944961713Sgirish } 339044961713Sgirish 3391678453a8Sspeer ddi_status = ddi_dma_addr_bind_handle(dma_p->dma_handle, 3392678453a8Sspeer NULL, 3393678453a8Sspeer kaddrp, dma_p->alength, xfer_flags, 3394678453a8Sspeer DDI_DMA_DONTWAIT, 3395678453a8Sspeer 0, &dma_p->dma_cookie, &dma_p->ncookies); 3396678453a8Sspeer if (ddi_status != DDI_DMA_MAPPED) { 3397678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3398678453a8Sspeer "nxge_dma_mem_alloc: ddi_dma_addr_bind " 3399678453a8Sspeer "failed " 3400678453a8Sspeer "(staus 0x%x ncookies %d.)", ddi_status, 3401678453a8Sspeer dma_p->ncookies)); 3402678453a8Sspeer if (dma_p->acc_handle) { 3403678453a8Sspeer ddi_dma_mem_free(&dma_p->acc_handle); 3404678453a8Sspeer dma_p->acc_handle = NULL; 3405678453a8Sspeer } 3406678453a8Sspeer ddi_dma_free_handle(&dma_p->dma_handle); 3407678453a8Sspeer dma_p->dma_handle = NULL; 3408678453a8Sspeer return (NXGE_ERROR | NXGE_DDI_FAILED); 3409678453a8Sspeer } 3410678453a8Sspeer 3411678453a8Sspeer if (dma_p->ncookies != 1) { 3412678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, 3413678453a8Sspeer "nxge_dma_mem_alloc:ddi_dma_addr_bind " 3414678453a8Sspeer "> 1 cookie" 3415678453a8Sspeer "(staus 0x%x ncookies %d.)", ddi_status, 3416678453a8Sspeer dma_p->ncookies)); 3417330cd344SMichael Speer (void) ddi_dma_unbind_handle(dma_p->dma_handle); 3418678453a8Sspeer if (dma_p->acc_handle) { 3419678453a8Sspeer ddi_dma_mem_free(&dma_p->acc_handle); 3420678453a8Sspeer dma_p->acc_handle = NULL; 3421678453a8Sspeer } 3422678453a8Sspeer ddi_dma_free_handle(&dma_p->dma_handle); 3423678453a8Sspeer dma_p->dma_handle = NULL; 3424330cd344SMichael Speer dma_p->acc_handle = NULL; 3425678453a8Sspeer return (NXGE_ERROR); 3426678453a8Sspeer } 3427678453a8Sspeer break; 3428678453a8Sspeer 3429678453a8Sspeer case B_TRUE: 3430678453a8Sspeer kaddrp = KMEM_ALLOC(length, KM_NOSLEEP); 3431678453a8Sspeer if (kaddrp == NULL) { 3432678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3433678453a8Sspeer "nxge_dma_mem_alloc:ddi_dma_mem_alloc " 3434678453a8Sspeer "kmem alloc failed")); 3435678453a8Sspeer return (NXGE_ERROR); 3436678453a8Sspeer } 3437678453a8Sspeer 3438678453a8Sspeer dma_p->alength = length; 3439678453a8Sspeer ddi_status = ddi_dma_addr_bind_handle(dma_p->dma_handle, 3440678453a8Sspeer NULL, kaddrp, dma_p->alength, xfer_flags, 3441678453a8Sspeer DDI_DMA_DONTWAIT, 0, 3442678453a8Sspeer &dma_p->dma_cookie, &dma_p->ncookies); 3443678453a8Sspeer if (ddi_status != DDI_DMA_MAPPED) { 3444678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3445678453a8Sspeer "nxge_dma_mem_alloc:ddi_dma_addr_bind: " 3446678453a8Sspeer "(kmem_alloc) failed kaddrp $%p length %d " 3447678453a8Sspeer "(staus 0x%x (%d) ncookies %d.)", 3448678453a8Sspeer kaddrp, length, 3449678453a8Sspeer ddi_status, ddi_status, dma_p->ncookies)); 3450678453a8Sspeer KMEM_FREE(kaddrp, length); 3451678453a8Sspeer dma_p->acc_handle = NULL; 3452678453a8Sspeer ddi_dma_free_handle(&dma_p->dma_handle); 3453678453a8Sspeer dma_p->dma_handle = NULL; 3454678453a8Sspeer dma_p->kaddrp = NULL; 3455678453a8Sspeer return (NXGE_ERROR | NXGE_DDI_FAILED); 3456678453a8Sspeer } 3457678453a8Sspeer 3458678453a8Sspeer if (dma_p->ncookies != 1) { 3459678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, 3460678453a8Sspeer "nxge_dma_mem_alloc:ddi_dma_addr_bind " 3461678453a8Sspeer "(kmem_alloc) > 1 cookie" 3462678453a8Sspeer "(staus 0x%x ncookies %d.)", ddi_status, 34634045d941Ssowmini dma_p->ncookies)); 3464678453a8Sspeer (void) ddi_dma_unbind_handle(dma_p->dma_handle); 3465330cd344SMichael Speer KMEM_FREE(kaddrp, length); 3466678453a8Sspeer ddi_dma_free_handle(&dma_p->dma_handle); 3467678453a8Sspeer dma_p->dma_handle = NULL; 3468330cd344SMichael Speer dma_p->acc_handle = NULL; 3469678453a8Sspeer dma_p->kaddrp = NULL; 3470678453a8Sspeer return (NXGE_ERROR); 347144961713Sgirish } 3472678453a8Sspeer 3473678453a8Sspeer dma_p->kaddrp = kaddrp; 3474678453a8Sspeer 3475678453a8Sspeer NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 34764045d941Ssowmini "nxge_dma_mem_alloc: kmem_alloc dmap $%p " 34774045d941Ssowmini "kaddr $%p alength %d", 34784045d941Ssowmini dma_p, 34794045d941Ssowmini kaddrp, 34804045d941Ssowmini dma_p->alength)); 3481678453a8Sspeer break; 348244961713Sgirish } 348344961713Sgirish break; 348444961713Sgirish 348544961713Sgirish #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 348644961713Sgirish case B_TRUE: 348744961713Sgirish kaddrp = (caddr_t)contig_mem_alloc(length); 348844961713Sgirish if (kaddrp == NULL) { 348944961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 34904045d941Ssowmini "nxge_dma_mem_alloc:contig_mem_alloc failed.")); 349144961713Sgirish ddi_dma_free_handle(&dma_p->dma_handle); 349244961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 349344961713Sgirish } 349444961713Sgirish 349544961713Sgirish dma_p->alength = length; 349644961713Sgirish ddi_status = ddi_dma_addr_bind_handle(dma_p->dma_handle, NULL, 34974045d941Ssowmini kaddrp, dma_p->alength, xfer_flags, DDI_DMA_DONTWAIT, 0, 34984045d941Ssowmini &dma_p->dma_cookie, &dma_p->ncookies); 349944961713Sgirish if (ddi_status != DDI_DMA_MAPPED) { 350044961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 35014045d941Ssowmini "nxge_dma_mem_alloc:di_dma_addr_bind failed " 35024045d941Ssowmini "(status 0x%x ncookies %d.)", ddi_status, 35034045d941Ssowmini dma_p->ncookies)); 350444961713Sgirish 350544961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 35064045d941Ssowmini "==> nxge_dma_mem_alloc: (not mapped)" 35074045d941Ssowmini "length %lu (0x%x) " 35084045d941Ssowmini "free contig kaddrp $%p " 35094045d941Ssowmini "va_to_pa $%p", 35104045d941Ssowmini length, length, 35114045d941Ssowmini kaddrp, 35124045d941Ssowmini va_to_pa(kaddrp))); 351344961713Sgirish 351444961713Sgirish 351544961713Sgirish contig_mem_free((void *)kaddrp, length); 351644961713Sgirish ddi_dma_free_handle(&dma_p->dma_handle); 351744961713Sgirish 351844961713Sgirish dma_p->dma_handle = NULL; 351944961713Sgirish dma_p->acc_handle = NULL; 352044961713Sgirish dma_p->alength = NULL; 352144961713Sgirish dma_p->kaddrp = NULL; 352244961713Sgirish 352344961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 352444961713Sgirish } 352544961713Sgirish 352644961713Sgirish if (dma_p->ncookies != 1 || 35274045d941Ssowmini (dma_p->dma_cookie.dmac_laddress == NULL)) { 352844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 35294045d941Ssowmini "nxge_dma_mem_alloc:di_dma_addr_bind > 1 " 35304045d941Ssowmini "cookie or " 35314045d941Ssowmini "dmac_laddress is NULL $%p size %d " 35324045d941Ssowmini " (status 0x%x ncookies %d.)", 35334045d941Ssowmini ddi_status, 35344045d941Ssowmini dma_p->dma_cookie.dmac_laddress, 35354045d941Ssowmini dma_p->dma_cookie.dmac_size, 35364045d941Ssowmini dma_p->ncookies)); 353744961713Sgirish 353844961713Sgirish contig_mem_free((void *)kaddrp, length); 353956d930aeSspeer (void) ddi_dma_unbind_handle(dma_p->dma_handle); 354044961713Sgirish ddi_dma_free_handle(&dma_p->dma_handle); 354144961713Sgirish 354244961713Sgirish dma_p->alength = 0; 354344961713Sgirish dma_p->dma_handle = NULL; 354444961713Sgirish dma_p->acc_handle = NULL; 354544961713Sgirish dma_p->kaddrp = NULL; 354644961713Sgirish 354744961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 354844961713Sgirish } 354944961713Sgirish break; 355044961713Sgirish 355144961713Sgirish #else 355244961713Sgirish case B_TRUE: 355344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 35544045d941Ssowmini "nxge_dma_mem_alloc: invalid alloc type for !sun4v")); 355544961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 355644961713Sgirish #endif 355744961713Sgirish } 355844961713Sgirish 355944961713Sgirish dma_p->kaddrp = kaddrp; 356044961713Sgirish dma_p->last_kaddrp = (unsigned char *)kaddrp + 35614045d941Ssowmini dma_p->alength - RXBUF_64B_ALIGNED; 3562adfcba55Sjoycey #if defined(__i386) 3563adfcba55Sjoycey dma_p->ioaddr_pp = 35644045d941Ssowmini (unsigned char *)(uint32_t)dma_p->dma_cookie.dmac_laddress; 3565adfcba55Sjoycey #else 356644961713Sgirish dma_p->ioaddr_pp = (unsigned char *)dma_p->dma_cookie.dmac_laddress; 3567adfcba55Sjoycey #endif 356844961713Sgirish dma_p->last_ioaddr_pp = 3569adfcba55Sjoycey #if defined(__i386) 35704045d941Ssowmini (unsigned char *)(uint32_t)dma_p->dma_cookie.dmac_laddress + 3571adfcba55Sjoycey #else 35724045d941Ssowmini (unsigned char *)dma_p->dma_cookie.dmac_laddress + 3573adfcba55Sjoycey #endif 35744045d941Ssowmini dma_p->alength - RXBUF_64B_ALIGNED; 357544961713Sgirish 357644961713Sgirish NPI_DMA_ACC_HANDLE_SET(dma_p, dma_p->acc_handle); 357744961713Sgirish 357844961713Sgirish #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 357944961713Sgirish dma_p->orig_ioaddr_pp = 35804045d941Ssowmini (unsigned char *)dma_p->dma_cookie.dmac_laddress; 358144961713Sgirish dma_p->orig_alength = length; 358244961713Sgirish dma_p->orig_kaddrp = kaddrp; 358344961713Sgirish dma_p->orig_vatopa = (uint64_t)va_to_pa(kaddrp); 358444961713Sgirish #endif 358544961713Sgirish 358644961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_dma_mem_alloc: " 35874045d941Ssowmini "dma buffer allocated: dma_p $%p " 35884045d941Ssowmini "return dmac_ladress from cookie $%p cookie dmac_size %d " 35894045d941Ssowmini "dma_p->ioaddr_p $%p " 35904045d941Ssowmini "dma_p->orig_ioaddr_p $%p " 35914045d941Ssowmini "orig_vatopa $%p " 35924045d941Ssowmini "alength %d (0x%x) " 35934045d941Ssowmini "kaddrp $%p " 35944045d941Ssowmini "length %d (0x%x)", 35954045d941Ssowmini dma_p, 35964045d941Ssowmini dma_p->dma_cookie.dmac_laddress, dma_p->dma_cookie.dmac_size, 35974045d941Ssowmini dma_p->ioaddr_pp, 35984045d941Ssowmini dma_p->orig_ioaddr_pp, 35994045d941Ssowmini dma_p->orig_vatopa, 36004045d941Ssowmini dma_p->alength, dma_p->alength, 36014045d941Ssowmini kaddrp, 36024045d941Ssowmini length, length)); 360344961713Sgirish 360444961713Sgirish return (NXGE_OK); 360544961713Sgirish } 360644961713Sgirish 360744961713Sgirish static void 360844961713Sgirish nxge_dma_mem_free(p_nxge_dma_common_t dma_p) 360944961713Sgirish { 361044961713Sgirish if (dma_p->dma_handle != NULL) { 361144961713Sgirish if (dma_p->ncookies) { 361244961713Sgirish (void) ddi_dma_unbind_handle(dma_p->dma_handle); 361344961713Sgirish dma_p->ncookies = 0; 361444961713Sgirish } 361544961713Sgirish ddi_dma_free_handle(&dma_p->dma_handle); 361644961713Sgirish dma_p->dma_handle = NULL; 361744961713Sgirish } 361844961713Sgirish 361944961713Sgirish if (dma_p->acc_handle != NULL) { 362044961713Sgirish ddi_dma_mem_free(&dma_p->acc_handle); 362144961713Sgirish dma_p->acc_handle = NULL; 362244961713Sgirish NPI_DMA_ACC_HANDLE_SET(dma_p, NULL); 362344961713Sgirish } 362444961713Sgirish 362544961713Sgirish #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 362644961713Sgirish if (dma_p->contig_alloc_type && 36274045d941Ssowmini dma_p->orig_kaddrp && dma_p->orig_alength) { 362844961713Sgirish NXGE_DEBUG_MSG((NULL, DMA_CTL, "nxge_dma_mem_free: " 36294045d941Ssowmini "kaddrp $%p (orig_kaddrp $%p)" 36304045d941Ssowmini "mem type %d ", 36314045d941Ssowmini "orig_alength %d " 36324045d941Ssowmini "alength 0x%x (%d)", 36334045d941Ssowmini dma_p->kaddrp, 36344045d941Ssowmini dma_p->orig_kaddrp, 36354045d941Ssowmini dma_p->contig_alloc_type, 36364045d941Ssowmini dma_p->orig_alength, 36374045d941Ssowmini dma_p->alength, dma_p->alength)); 363844961713Sgirish 363944961713Sgirish contig_mem_free(dma_p->orig_kaddrp, dma_p->orig_alength); 364044961713Sgirish dma_p->orig_alength = NULL; 364144961713Sgirish dma_p->orig_kaddrp = NULL; 364244961713Sgirish dma_p->contig_alloc_type = B_FALSE; 364344961713Sgirish } 364444961713Sgirish #endif 364544961713Sgirish dma_p->kaddrp = NULL; 364644961713Sgirish dma_p->alength = NULL; 364744961713Sgirish } 364844961713Sgirish 3649678453a8Sspeer static void 3650678453a8Sspeer nxge_dma_free_rx_data_buf(p_nxge_dma_common_t dma_p) 3651678453a8Sspeer { 3652678453a8Sspeer uint64_t kaddr; 3653678453a8Sspeer uint32_t buf_size; 3654678453a8Sspeer 3655678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, "==> nxge_dma_free_rx_data_buf")); 3656678453a8Sspeer 3657678453a8Sspeer if (dma_p->dma_handle != NULL) { 3658678453a8Sspeer if (dma_p->ncookies) { 3659678453a8Sspeer (void) ddi_dma_unbind_handle(dma_p->dma_handle); 3660678453a8Sspeer dma_p->ncookies = 0; 3661678453a8Sspeer } 3662678453a8Sspeer ddi_dma_free_handle(&dma_p->dma_handle); 3663678453a8Sspeer dma_p->dma_handle = NULL; 3664678453a8Sspeer } 3665678453a8Sspeer 3666678453a8Sspeer if (dma_p->acc_handle != NULL) { 3667678453a8Sspeer ddi_dma_mem_free(&dma_p->acc_handle); 3668678453a8Sspeer dma_p->acc_handle = NULL; 3669678453a8Sspeer NPI_DMA_ACC_HANDLE_SET(dma_p, NULL); 3670678453a8Sspeer } 3671678453a8Sspeer 3672678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, 3673678453a8Sspeer "==> nxge_dma_free_rx_data_buf: dmap $%p buf_alloc_state %d", 3674678453a8Sspeer dma_p, 3675678453a8Sspeer dma_p->buf_alloc_state)); 3676678453a8Sspeer 3677678453a8Sspeer if (!(dma_p->buf_alloc_state & BUF_ALLOCATED_WAIT_FREE)) { 3678678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, 3679678453a8Sspeer "<== nxge_dma_free_rx_data_buf: " 3680678453a8Sspeer "outstanding data buffers")); 3681678453a8Sspeer return; 3682678453a8Sspeer } 3683678453a8Sspeer 3684678453a8Sspeer #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 3685678453a8Sspeer if (dma_p->contig_alloc_type && 36864045d941Ssowmini dma_p->orig_kaddrp && dma_p->orig_alength) { 3687678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, "nxge_dma_free_rx_data_buf: " 3688678453a8Sspeer "kaddrp $%p (orig_kaddrp $%p)" 3689678453a8Sspeer "mem type %d ", 3690678453a8Sspeer "orig_alength %d " 3691678453a8Sspeer "alength 0x%x (%d)", 3692678453a8Sspeer dma_p->kaddrp, 3693678453a8Sspeer dma_p->orig_kaddrp, 3694678453a8Sspeer dma_p->contig_alloc_type, 3695678453a8Sspeer dma_p->orig_alength, 3696678453a8Sspeer dma_p->alength, dma_p->alength)); 3697678453a8Sspeer 3698678453a8Sspeer kaddr = (uint64_t)dma_p->orig_kaddrp; 3699678453a8Sspeer buf_size = dma_p->orig_alength; 3700678453a8Sspeer nxge_free_buf(CONTIG_MEM_ALLOC, kaddr, buf_size); 3701678453a8Sspeer dma_p->orig_alength = NULL; 3702678453a8Sspeer dma_p->orig_kaddrp = NULL; 3703678453a8Sspeer dma_p->contig_alloc_type = B_FALSE; 3704678453a8Sspeer dma_p->kaddrp = NULL; 3705678453a8Sspeer dma_p->alength = NULL; 3706678453a8Sspeer return; 3707678453a8Sspeer } 3708678453a8Sspeer #endif 3709678453a8Sspeer 3710678453a8Sspeer if (dma_p->kmem_alloc_type) { 3711678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, 3712678453a8Sspeer "nxge_dma_free_rx_data_buf: free kmem " 37134045d941Ssowmini "kaddrp $%p (orig_kaddrp $%p)" 37144045d941Ssowmini "alloc type %d " 37154045d941Ssowmini "orig_alength %d " 37164045d941Ssowmini "alength 0x%x (%d)", 37174045d941Ssowmini dma_p->kaddrp, 37184045d941Ssowmini dma_p->orig_kaddrp, 37194045d941Ssowmini dma_p->kmem_alloc_type, 37204045d941Ssowmini dma_p->orig_alength, 37214045d941Ssowmini dma_p->alength, dma_p->alength)); 3722678453a8Sspeer #if defined(__i386) 3723678453a8Sspeer kaddr = (uint64_t)(uint32_t)dma_p->kaddrp; 3724678453a8Sspeer #else 3725678453a8Sspeer kaddr = (uint64_t)dma_p->kaddrp; 3726678453a8Sspeer #endif 3727678453a8Sspeer buf_size = dma_p->orig_alength; 3728678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, 3729678453a8Sspeer "nxge_dma_free_rx_data_buf: free dmap $%p " 3730678453a8Sspeer "kaddr $%p buf_size %d", 3731678453a8Sspeer dma_p, 3732678453a8Sspeer kaddr, buf_size)); 3733678453a8Sspeer nxge_free_buf(KMEM_ALLOC, kaddr, buf_size); 3734678453a8Sspeer dma_p->alength = 0; 3735678453a8Sspeer dma_p->orig_alength = 0; 3736678453a8Sspeer dma_p->kaddrp = NULL; 3737678453a8Sspeer dma_p->kmem_alloc_type = B_FALSE; 3738678453a8Sspeer } 3739678453a8Sspeer 3740678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_dma_free_rx_data_buf")); 3741678453a8Sspeer } 3742678453a8Sspeer 374344961713Sgirish /* 374444961713Sgirish * nxge_m_start() -- start transmitting and receiving. 374544961713Sgirish * 374644961713Sgirish * This function is called by the MAC layer when the first 374744961713Sgirish * stream is open to prepare the hardware ready for sending 374844961713Sgirish * and transmitting packets. 374944961713Sgirish */ 375044961713Sgirish static int 375144961713Sgirish nxge_m_start(void *arg) 375244961713Sgirish { 375344961713Sgirish p_nxge_t nxgep = (p_nxge_t)arg; 375444961713Sgirish 375544961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_start")); 375644961713Sgirish 3757e759c33aSMichael Speer /* 3758e759c33aSMichael Speer * Are we already started? 3759e759c33aSMichael Speer */ 3760e759c33aSMichael Speer if (nxgep->nxge_mac_state == NXGE_MAC_STARTED) { 3761e759c33aSMichael Speer return (0); 3762e759c33aSMichael Speer } 3763e759c33aSMichael Speer 37646f157acbSml if (nxge_peu_reset_enable && !nxgep->nxge_link_poll_timerid) { 37656f157acbSml (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 37666f157acbSml } 37676f157acbSml 3768e759c33aSMichael Speer /* 3769e759c33aSMichael Speer * Make sure RX MAC is disabled while we initialize. 3770e759c33aSMichael Speer */ 3771e759c33aSMichael Speer if (!isLDOMguest(nxgep)) { 3772e759c33aSMichael Speer (void) nxge_rx_mac_disable(nxgep); 3773e759c33aSMichael Speer } 3774e759c33aSMichael Speer 3775e759c33aSMichael Speer /* 3776e759c33aSMichael Speer * Grab the global lock. 3777e759c33aSMichael Speer */ 377844961713Sgirish MUTEX_ENTER(nxgep->genlock); 3779e759c33aSMichael Speer 3780e759c33aSMichael Speer /* 3781e759c33aSMichael Speer * Initialize the driver and hardware. 3782e759c33aSMichael Speer */ 378314ea4bb7Ssd if (nxge_init(nxgep) != NXGE_OK) { 378444961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 37854045d941Ssowmini "<== nxge_m_start: initialization failed")); 378644961713Sgirish MUTEX_EXIT(nxgep->genlock); 378744961713Sgirish return (EIO); 378844961713Sgirish } 378944961713Sgirish 379044961713Sgirish /* 379144961713Sgirish * Start timer to check the system error and tx hangs 379244961713Sgirish */ 3793678453a8Sspeer if (!isLDOMguest(nxgep)) 3794678453a8Sspeer nxgep->nxge_timerid = nxge_start_timer(nxgep, 3795678453a8Sspeer nxge_check_hw_state, NXGE_CHECK_TIMER); 3796e759c33aSMichael Speer #if defined(sun4v) 3797678453a8Sspeer else 3798678453a8Sspeer nxge_hio_start_timer(nxgep); 3799678453a8Sspeer #endif 380044961713Sgirish 3801a3c5bd6dSspeer nxgep->link_notify = B_TRUE; 380244961713Sgirish nxgep->nxge_mac_state = NXGE_MAC_STARTED; 380344961713Sgirish 3804e759c33aSMichael Speer /* 3805e759c33aSMichael Speer * Let the global lock go, since we are intialized. 3806e759c33aSMichael Speer */ 380744961713Sgirish MUTEX_EXIT(nxgep->genlock); 3808e759c33aSMichael Speer 3809e759c33aSMichael Speer /* 3810e759c33aSMichael Speer * Let the MAC start receiving packets, now that 3811e759c33aSMichael Speer * we are initialized. 3812e759c33aSMichael Speer */ 3813e759c33aSMichael Speer if (!isLDOMguest(nxgep)) { 3814e759c33aSMichael Speer if (nxge_rx_mac_enable(nxgep) != NXGE_OK) { 3815e759c33aSMichael Speer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3816e759c33aSMichael Speer "<== nxge_m_start: enable of RX mac failed")); 3817e759c33aSMichael Speer return (EIO); 3818e759c33aSMichael Speer } 3819e759c33aSMichael Speer 3820e759c33aSMichael Speer /* 3821e759c33aSMichael Speer * Enable hardware interrupts. 3822e759c33aSMichael Speer */ 3823e759c33aSMichael Speer nxge_intr_hw_enable(nxgep); 3824e759c33aSMichael Speer } 3825e759c33aSMichael Speer #if defined(sun4v) 3826e759c33aSMichael Speer else { 3827e759c33aSMichael Speer /* 3828e759c33aSMichael Speer * In guest domain we enable RDCs and their interrupts as 3829e759c33aSMichael Speer * the last step. 3830e759c33aSMichael Speer */ 3831e759c33aSMichael Speer if (nxge_hio_rdc_enable(nxgep) != NXGE_OK) { 3832e759c33aSMichael Speer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3833e759c33aSMichael Speer "<== nxge_m_start: enable of RDCs failed")); 3834e759c33aSMichael Speer return (EIO); 3835e759c33aSMichael Speer } 3836e759c33aSMichael Speer 3837e759c33aSMichael Speer if (nxge_hio_rdc_intr_arm(nxgep, B_TRUE) != NXGE_OK) { 3838e759c33aSMichael Speer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3839e759c33aSMichael Speer "<== nxge_m_start: intrs enable for RDCs failed")); 3840e759c33aSMichael Speer return (EIO); 3841e759c33aSMichael Speer } 3842e759c33aSMichael Speer } 3843e759c33aSMichael Speer #endif 384444961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_start")); 384544961713Sgirish return (0); 384644961713Sgirish } 384744961713Sgirish 3848da14cebeSEric Cheng static boolean_t 3849da14cebeSEric Cheng nxge_check_groups_stopped(p_nxge_t nxgep) 3850da14cebeSEric Cheng { 3851da14cebeSEric Cheng int i; 3852da14cebeSEric Cheng 3853da14cebeSEric Cheng for (i = 0; i < NXGE_MAX_RDC_GROUPS; i++) { 3854da14cebeSEric Cheng if (nxgep->rx_hio_groups[i].started) 3855da14cebeSEric Cheng return (B_FALSE); 3856da14cebeSEric Cheng } 3857da14cebeSEric Cheng 3858da14cebeSEric Cheng return (B_TRUE); 3859da14cebeSEric Cheng } 3860da14cebeSEric Cheng 386144961713Sgirish /* 386244961713Sgirish * nxge_m_stop(): stop transmitting and receiving. 386344961713Sgirish */ 386444961713Sgirish static void 386544961713Sgirish nxge_m_stop(void *arg) 386644961713Sgirish { 386744961713Sgirish p_nxge_t nxgep = (p_nxge_t)arg; 3868da14cebeSEric Cheng boolean_t groups_stopped; 386944961713Sgirish 387044961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_stop")); 387144961713Sgirish 3872e759c33aSMichael Speer /* 3873e759c33aSMichael Speer * Are the groups stopped? 3874e759c33aSMichael Speer */ 3875da14cebeSEric Cheng groups_stopped = nxge_check_groups_stopped(nxgep); 3876e759c33aSMichael Speer ASSERT(groups_stopped == B_TRUE); 3877da14cebeSEric Cheng if (!groups_stopped) { 3878da14cebeSEric Cheng cmn_err(CE_WARN, "nxge(%d): groups are not stopped!\n", 3879da14cebeSEric Cheng nxgep->instance); 3880da14cebeSEric Cheng return; 3881da14cebeSEric Cheng } 3882da14cebeSEric Cheng 3883e759c33aSMichael Speer if (!isLDOMguest(nxgep)) { 3884e759c33aSMichael Speer /* 3885e759c33aSMichael Speer * Disable the RX mac. 3886e759c33aSMichael Speer */ 3887e759c33aSMichael Speer (void) nxge_rx_mac_disable(nxgep); 3888e759c33aSMichael Speer 3889e759c33aSMichael Speer /* 3890e759c33aSMichael Speer * Wait for the IPP to drain. 3891e759c33aSMichael Speer */ 3892e759c33aSMichael Speer (void) nxge_ipp_drain(nxgep); 3893e759c33aSMichael Speer 3894e759c33aSMichael Speer /* 3895e759c33aSMichael Speer * Disable hardware interrupts. 3896e759c33aSMichael Speer */ 3897e759c33aSMichael Speer nxge_intr_hw_disable(nxgep); 3898e759c33aSMichael Speer } 3899e759c33aSMichael Speer #if defined(sun4v) 3900e759c33aSMichael Speer else { 3901e759c33aSMichael Speer (void) nxge_hio_rdc_intr_arm(nxgep, B_FALSE); 3902e759c33aSMichael Speer } 3903e759c33aSMichael Speer #endif 3904e759c33aSMichael Speer 3905e759c33aSMichael Speer /* 3906e759c33aSMichael Speer * Grab the global lock. 3907e759c33aSMichael Speer */ 3908d7cf53fcSmisaki Miyashita MUTEX_ENTER(nxgep->genlock); 3909d7cf53fcSmisaki Miyashita 3910e759c33aSMichael Speer nxgep->nxge_mac_state = NXGE_MAC_STOPPING; 391144961713Sgirish if (nxgep->nxge_timerid) { 391244961713Sgirish nxge_stop_timer(nxgep, nxgep->nxge_timerid); 391344961713Sgirish nxgep->nxge_timerid = 0; 391444961713Sgirish } 3915a3c5bd6dSspeer 3916e759c33aSMichael Speer /* 3917e759c33aSMichael Speer * Clean up. 3918e759c33aSMichael Speer */ 391944961713Sgirish nxge_uninit(nxgep); 392044961713Sgirish 392144961713Sgirish nxgep->nxge_mac_state = NXGE_MAC_STOPPED; 392244961713Sgirish 3923e759c33aSMichael Speer /* 3924e759c33aSMichael Speer * Let go of the global lock. 3925e759c33aSMichael Speer */ 392644961713Sgirish MUTEX_EXIT(nxgep->genlock); 392744961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_stop")); 392844961713Sgirish } 392944961713Sgirish 393044961713Sgirish static int 393144961713Sgirish nxge_m_multicst(void *arg, boolean_t add, const uint8_t *mca) 393244961713Sgirish { 393344961713Sgirish p_nxge_t nxgep = (p_nxge_t)arg; 393444961713Sgirish struct ether_addr addrp; 393544961713Sgirish 393644961713Sgirish NXGE_DEBUG_MSG((nxgep, MAC_CTL, 39374045d941Ssowmini "==> nxge_m_multicst: add %d", add)); 393844961713Sgirish 393944961713Sgirish bcopy(mca, (uint8_t *)&addrp, ETHERADDRL); 394044961713Sgirish if (add) { 394144961713Sgirish if (nxge_add_mcast_addr(nxgep, &addrp)) { 394244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 39434045d941Ssowmini "<== nxge_m_multicst: add multicast failed")); 394444961713Sgirish return (EINVAL); 394544961713Sgirish } 394644961713Sgirish } else { 394744961713Sgirish if (nxge_del_mcast_addr(nxgep, &addrp)) { 394844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 39494045d941Ssowmini "<== nxge_m_multicst: del multicast failed")); 395044961713Sgirish return (EINVAL); 395144961713Sgirish } 395244961713Sgirish } 395344961713Sgirish 395444961713Sgirish NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_m_multicst")); 395544961713Sgirish 395644961713Sgirish return (0); 395744961713Sgirish } 395844961713Sgirish 395944961713Sgirish static int 396044961713Sgirish nxge_m_promisc(void *arg, boolean_t on) 396144961713Sgirish { 396244961713Sgirish p_nxge_t nxgep = (p_nxge_t)arg; 396344961713Sgirish 396444961713Sgirish NXGE_DEBUG_MSG((nxgep, MAC_CTL, 39654045d941Ssowmini "==> nxge_m_promisc: on %d", on)); 396644961713Sgirish 396744961713Sgirish if (nxge_set_promisc(nxgep, on)) { 396844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 39694045d941Ssowmini "<== nxge_m_promisc: set promisc failed")); 397044961713Sgirish return (EINVAL); 397144961713Sgirish } 397244961713Sgirish 397344961713Sgirish NXGE_DEBUG_MSG((nxgep, MAC_CTL, 39744045d941Ssowmini "<== nxge_m_promisc: on %d", on)); 397544961713Sgirish 397644961713Sgirish return (0); 397744961713Sgirish } 397844961713Sgirish 397944961713Sgirish static void 398044961713Sgirish nxge_m_ioctl(void *arg, queue_t *wq, mblk_t *mp) 398144961713Sgirish { 398244961713Sgirish p_nxge_t nxgep = (p_nxge_t)arg; 398356d930aeSspeer struct iocblk *iocp; 398444961713Sgirish boolean_t need_privilege; 398544961713Sgirish int err; 398644961713Sgirish int cmd; 398744961713Sgirish 398844961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_ioctl")); 398944961713Sgirish 399044961713Sgirish iocp = (struct iocblk *)mp->b_rptr; 399144961713Sgirish iocp->ioc_error = 0; 399244961713Sgirish need_privilege = B_TRUE; 399344961713Sgirish cmd = iocp->ioc_cmd; 399444961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_ioctl: cmd 0x%08x", cmd)); 399544961713Sgirish switch (cmd) { 399644961713Sgirish default: 399744961713Sgirish miocnak(wq, mp, 0, EINVAL); 399844961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_ioctl: invalid")); 399944961713Sgirish return; 400044961713Sgirish 400144961713Sgirish case LB_GET_INFO_SIZE: 400244961713Sgirish case LB_GET_INFO: 400344961713Sgirish case LB_GET_MODE: 400444961713Sgirish need_privilege = B_FALSE; 400544961713Sgirish break; 400644961713Sgirish case LB_SET_MODE: 400744961713Sgirish break; 400844961713Sgirish 400944961713Sgirish 401044961713Sgirish case NXGE_GET_MII: 401144961713Sgirish case NXGE_PUT_MII: 401244961713Sgirish case NXGE_GET64: 401344961713Sgirish case NXGE_PUT64: 401444961713Sgirish case NXGE_GET_TX_RING_SZ: 401544961713Sgirish case NXGE_GET_TX_DESC: 401644961713Sgirish case NXGE_TX_SIDE_RESET: 401744961713Sgirish case NXGE_RX_SIDE_RESET: 401844961713Sgirish case NXGE_GLOBAL_RESET: 401944961713Sgirish case NXGE_RESET_MAC: 402044961713Sgirish case NXGE_TX_REGS_DUMP: 402144961713Sgirish case NXGE_RX_REGS_DUMP: 402244961713Sgirish case NXGE_INT_REGS_DUMP: 402344961713Sgirish case NXGE_VIR_INT_REGS_DUMP: 402444961713Sgirish case NXGE_PUT_TCAM: 402544961713Sgirish case NXGE_GET_TCAM: 402644961713Sgirish case NXGE_RTRACE: 402744961713Sgirish case NXGE_RDUMP: 4028*4df55fdeSJanie Lu case NXGE_RX_CLASS: 4029*4df55fdeSJanie Lu case NXGE_RX_HASH: 403044961713Sgirish 403144961713Sgirish need_privilege = B_FALSE; 403244961713Sgirish break; 403344961713Sgirish case NXGE_INJECT_ERR: 403444961713Sgirish cmn_err(CE_NOTE, "!nxge_m_ioctl: Inject error\n"); 403544961713Sgirish nxge_err_inject(nxgep, wq, mp); 403644961713Sgirish break; 403744961713Sgirish } 403844961713Sgirish 403944961713Sgirish if (need_privilege) { 404056d930aeSspeer err = secpolicy_net_config(iocp->ioc_cr, B_FALSE); 404144961713Sgirish if (err != 0) { 404244961713Sgirish miocnak(wq, mp, 0, err); 404344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 40444045d941Ssowmini "<== nxge_m_ioctl: no priv")); 404544961713Sgirish return; 404644961713Sgirish } 404744961713Sgirish } 404844961713Sgirish 404944961713Sgirish switch (cmd) { 405044961713Sgirish 405144961713Sgirish case LB_GET_MODE: 405244961713Sgirish case LB_SET_MODE: 405344961713Sgirish case LB_GET_INFO_SIZE: 405444961713Sgirish case LB_GET_INFO: 405544961713Sgirish nxge_loopback_ioctl(nxgep, wq, mp, iocp); 405644961713Sgirish break; 405744961713Sgirish 405844961713Sgirish case NXGE_GET_MII: 405944961713Sgirish case NXGE_PUT_MII: 406044961713Sgirish case NXGE_PUT_TCAM: 406144961713Sgirish case NXGE_GET_TCAM: 406244961713Sgirish case NXGE_GET64: 406344961713Sgirish case NXGE_PUT64: 406444961713Sgirish case NXGE_GET_TX_RING_SZ: 406544961713Sgirish case NXGE_GET_TX_DESC: 406644961713Sgirish case NXGE_TX_SIDE_RESET: 406744961713Sgirish case NXGE_RX_SIDE_RESET: 406844961713Sgirish case NXGE_GLOBAL_RESET: 406944961713Sgirish case NXGE_RESET_MAC: 407044961713Sgirish case NXGE_TX_REGS_DUMP: 407144961713Sgirish case NXGE_RX_REGS_DUMP: 407244961713Sgirish case NXGE_INT_REGS_DUMP: 407344961713Sgirish case NXGE_VIR_INT_REGS_DUMP: 407444961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 40754045d941Ssowmini "==> nxge_m_ioctl: cmd 0x%x", cmd)); 407644961713Sgirish nxge_hw_ioctl(nxgep, wq, mp, iocp); 407744961713Sgirish break; 4078*4df55fdeSJanie Lu case NXGE_RX_CLASS: 4079*4df55fdeSJanie Lu if (nxge_rxclass_ioctl(nxgep, wq, mp->b_cont) < 0) 4080*4df55fdeSJanie Lu miocnak(wq, mp, 0, EINVAL); 4081*4df55fdeSJanie Lu else 4082*4df55fdeSJanie Lu miocack(wq, mp, sizeof (rx_class_cfg_t), 0); 4083*4df55fdeSJanie Lu break; 4084*4df55fdeSJanie Lu case NXGE_RX_HASH: 4085*4df55fdeSJanie Lu 4086*4df55fdeSJanie Lu if (nxge_rxhash_ioctl(nxgep, wq, mp->b_cont) < 0) 4087*4df55fdeSJanie Lu miocnak(wq, mp, 0, EINVAL); 4088*4df55fdeSJanie Lu else 4089*4df55fdeSJanie Lu miocack(wq, mp, sizeof (cfg_cmd_t), 0); 4090*4df55fdeSJanie Lu break; 409144961713Sgirish } 409244961713Sgirish 409344961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_ioctl")); 409444961713Sgirish } 409544961713Sgirish 409644961713Sgirish extern void nxge_rx_hw_blank(void *arg, time_t ticks, uint_t count); 409744961713Sgirish 4098678453a8Sspeer void 4099da14cebeSEric Cheng nxge_mmac_kstat_update(p_nxge_t nxgep, int slot, boolean_t factory) 410058324dfcSspeer { 410158324dfcSspeer p_nxge_mmac_stats_t mmac_stats; 410258324dfcSspeer int i; 410358324dfcSspeer nxge_mmac_t *mmac_info; 410458324dfcSspeer 410558324dfcSspeer mmac_info = &nxgep->nxge_mmac_info; 410658324dfcSspeer 410758324dfcSspeer mmac_stats = &nxgep->statsp->mmac_stats; 410858324dfcSspeer mmac_stats->mmac_max_cnt = mmac_info->num_mmac; 410958324dfcSspeer mmac_stats->mmac_avail_cnt = mmac_info->naddrfree; 411058324dfcSspeer 411158324dfcSspeer for (i = 0; i < ETHERADDRL; i++) { 411258324dfcSspeer if (factory) { 411358324dfcSspeer mmac_stats->mmac_avail_pool[slot-1].ether_addr_octet[i] 41144045d941Ssowmini = mmac_info->factory_mac_pool[slot][ 41154045d941Ssowmini (ETHERADDRL-1) - i]; 411658324dfcSspeer } else { 411758324dfcSspeer mmac_stats->mmac_avail_pool[slot-1].ether_addr_octet[i] 41184045d941Ssowmini = mmac_info->mac_pool[slot].addr[ 41194045d941Ssowmini (ETHERADDRL - 1) - i]; 412058324dfcSspeer } 412158324dfcSspeer } 412258324dfcSspeer } 412358324dfcSspeer 412458324dfcSspeer /* 412558324dfcSspeer * nxge_altmac_set() -- Set an alternate MAC address 412658324dfcSspeer */ 4127da14cebeSEric Cheng static int 4128da14cebeSEric Cheng nxge_altmac_set(p_nxge_t nxgep, uint8_t *maddr, int slot, 4129da14cebeSEric Cheng int rdctbl, boolean_t usetbl) 413058324dfcSspeer { 413158324dfcSspeer uint8_t addrn; 413258324dfcSspeer uint8_t portn; 413358324dfcSspeer npi_mac_addr_t altmac; 41347b9fa28bSspeer hostinfo_t mac_rdc; 41357b9fa28bSspeer p_nxge_class_pt_cfg_t clscfgp; 413658324dfcSspeer 4137da14cebeSEric Cheng 413858324dfcSspeer altmac.w2 = ((uint16_t)maddr[0] << 8) | ((uint16_t)maddr[1] & 0x0ff); 413958324dfcSspeer altmac.w1 = ((uint16_t)maddr[2] << 8) | ((uint16_t)maddr[3] & 0x0ff); 414058324dfcSspeer altmac.w0 = ((uint16_t)maddr[4] << 8) | ((uint16_t)maddr[5] & 0x0ff); 414158324dfcSspeer 414258324dfcSspeer portn = nxgep->mac.portnum; 414358324dfcSspeer addrn = (uint8_t)slot - 1; 414458324dfcSspeer 4145da14cebeSEric Cheng if (npi_mac_altaddr_entry(nxgep->npi_handle, OP_SET, 4146da14cebeSEric Cheng nxgep->function_num, addrn, &altmac) != NPI_SUCCESS) 414758324dfcSspeer return (EIO); 41487b9fa28bSspeer 41497b9fa28bSspeer /* 41507b9fa28bSspeer * Set the rdc table number for the host info entry 41517b9fa28bSspeer * for this mac address slot. 41527b9fa28bSspeer */ 41537b9fa28bSspeer clscfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 41547b9fa28bSspeer mac_rdc.value = 0; 4155da14cebeSEric Cheng if (usetbl) 4156da14cebeSEric Cheng mac_rdc.bits.w0.rdc_tbl_num = rdctbl; 4157da14cebeSEric Cheng else 4158da14cebeSEric Cheng mac_rdc.bits.w0.rdc_tbl_num = 4159da14cebeSEric Cheng clscfgp->mac_host_info[addrn].rdctbl; 41607b9fa28bSspeer mac_rdc.bits.w0.mac_pref = clscfgp->mac_host_info[addrn].mpr_npr; 41617b9fa28bSspeer 41627b9fa28bSspeer if (npi_mac_hostinfo_entry(nxgep->npi_handle, OP_SET, 41637b9fa28bSspeer nxgep->function_num, addrn, &mac_rdc) != NPI_SUCCESS) { 41647b9fa28bSspeer return (EIO); 41657b9fa28bSspeer } 41667b9fa28bSspeer 416758324dfcSspeer /* 416858324dfcSspeer * Enable comparison with the alternate MAC address. 416958324dfcSspeer * While the first alternate addr is enabled by bit 1 of register 417058324dfcSspeer * BMAC_ALTAD_CMPEN, it is enabled by bit 0 of register 417158324dfcSspeer * XMAC_ADDR_CMPEN, so slot needs to be converted to addrn 417258324dfcSspeer * accordingly before calling npi_mac_altaddr_entry. 417358324dfcSspeer */ 417458324dfcSspeer if (portn == XMAC_PORT_0 || portn == XMAC_PORT_1) 417558324dfcSspeer addrn = (uint8_t)slot - 1; 417658324dfcSspeer else 417758324dfcSspeer addrn = (uint8_t)slot; 417858324dfcSspeer 4179da14cebeSEric Cheng if (npi_mac_altaddr_enable(nxgep->npi_handle, 4180da14cebeSEric Cheng nxgep->function_num, addrn) != NPI_SUCCESS) { 418158324dfcSspeer return (EIO); 4182da14cebeSEric Cheng } 4183da14cebeSEric Cheng 418458324dfcSspeer return (0); 418558324dfcSspeer } 418658324dfcSspeer 418758324dfcSspeer /* 4188da14cebeSEric Cheng * nxeg_m_mmac_add_g() - find an unused address slot, set the address 418958324dfcSspeer * value to the one specified, enable the port to start filtering on 419058324dfcSspeer * the new MAC address. Returns 0 on success. 419158324dfcSspeer */ 4192678453a8Sspeer int 4193da14cebeSEric Cheng nxge_m_mmac_add_g(void *arg, const uint8_t *maddr, int rdctbl, 4194da14cebeSEric Cheng boolean_t usetbl) 419558324dfcSspeer { 419658324dfcSspeer p_nxge_t nxgep = arg; 4197da14cebeSEric Cheng int slot; 419858324dfcSspeer nxge_mmac_t *mmac_info; 419958324dfcSspeer int err; 420058324dfcSspeer nxge_status_t status; 420158324dfcSspeer 420258324dfcSspeer mutex_enter(nxgep->genlock); 420358324dfcSspeer 420458324dfcSspeer /* 420558324dfcSspeer * Make sure that nxge is initialized, if _start() has 420658324dfcSspeer * not been called. 420758324dfcSspeer */ 420858324dfcSspeer if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 420958324dfcSspeer status = nxge_init(nxgep); 421058324dfcSspeer if (status != NXGE_OK) { 421158324dfcSspeer mutex_exit(nxgep->genlock); 421258324dfcSspeer return (ENXIO); 421358324dfcSspeer } 421458324dfcSspeer } 421558324dfcSspeer 421658324dfcSspeer mmac_info = &nxgep->nxge_mmac_info; 421758324dfcSspeer if (mmac_info->naddrfree == 0) { 421858324dfcSspeer mutex_exit(nxgep->genlock); 421958324dfcSspeer return (ENOSPC); 422058324dfcSspeer } 4221da14cebeSEric Cheng 422258324dfcSspeer /* 422358324dfcSspeer * Search for the first available slot. Because naddrfree 422458324dfcSspeer * is not zero, we are guaranteed to find one. 422558324dfcSspeer * Each of the first two ports of Neptune has 16 alternate 4226678453a8Sspeer * MAC slots but only the first 7 (of 15) slots have assigned factory 422758324dfcSspeer * MAC addresses. We first search among the slots without bundled 422858324dfcSspeer * factory MACs. If we fail to find one in that range, then we 422958324dfcSspeer * search the slots with bundled factory MACs. A factory MAC 423058324dfcSspeer * will be wasted while the slot is used with a user MAC address. 423158324dfcSspeer * But the slot could be used by factory MAC again after calling 423258324dfcSspeer * nxge_m_mmac_remove and nxge_m_mmac_reserve. 423358324dfcSspeer */ 4234da14cebeSEric Cheng for (slot = 0; slot <= mmac_info->num_mmac; slot++) { 4235da14cebeSEric Cheng if (!(mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED)) 4236da14cebeSEric Cheng break; 423758324dfcSspeer } 4238da14cebeSEric Cheng 423958324dfcSspeer ASSERT(slot <= mmac_info->num_mmac); 4240e857d0f3SMichael Speer 4241da14cebeSEric Cheng if ((err = nxge_altmac_set(nxgep, (uint8_t *)maddr, slot, rdctbl, 4242da14cebeSEric Cheng usetbl)) != 0) { 424358324dfcSspeer mutex_exit(nxgep->genlock); 424458324dfcSspeer return (err); 424558324dfcSspeer } 4246e857d0f3SMichael Speer 4247da14cebeSEric Cheng bcopy(maddr, mmac_info->mac_pool[slot].addr, ETHERADDRL); 424858324dfcSspeer mmac_info->mac_pool[slot].flags |= MMAC_SLOT_USED; 424958324dfcSspeer mmac_info->mac_pool[slot].flags &= ~MMAC_VENDOR_ADDR; 425058324dfcSspeer mmac_info->naddrfree--; 425158324dfcSspeer nxge_mmac_kstat_update(nxgep, slot, B_FALSE); 425258324dfcSspeer 425358324dfcSspeer mutex_exit(nxgep->genlock); 425458324dfcSspeer return (0); 425558324dfcSspeer } 425658324dfcSspeer 425758324dfcSspeer /* 425858324dfcSspeer * Remove the specified mac address and update the HW not to filter 425958324dfcSspeer * the mac address anymore. 426058324dfcSspeer */ 4261678453a8Sspeer int 4262da14cebeSEric Cheng nxge_m_mmac_remove(void *arg, int slot) 426358324dfcSspeer { 426458324dfcSspeer p_nxge_t nxgep = arg; 426558324dfcSspeer nxge_mmac_t *mmac_info; 426658324dfcSspeer uint8_t addrn; 426758324dfcSspeer uint8_t portn; 426858324dfcSspeer int err = 0; 426958324dfcSspeer nxge_status_t status; 427058324dfcSspeer 427158324dfcSspeer mutex_enter(nxgep->genlock); 427258324dfcSspeer 427358324dfcSspeer /* 427458324dfcSspeer * Make sure that nxge is initialized, if _start() has 427558324dfcSspeer * not been called. 427658324dfcSspeer */ 427758324dfcSspeer if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 427858324dfcSspeer status = nxge_init(nxgep); 427958324dfcSspeer if (status != NXGE_OK) { 428058324dfcSspeer mutex_exit(nxgep->genlock); 428158324dfcSspeer return (ENXIO); 428258324dfcSspeer } 428358324dfcSspeer } 428458324dfcSspeer 428558324dfcSspeer mmac_info = &nxgep->nxge_mmac_info; 428658324dfcSspeer if (slot < 1 || slot > mmac_info->num_mmac) { 428758324dfcSspeer mutex_exit(nxgep->genlock); 428858324dfcSspeer return (EINVAL); 428958324dfcSspeer } 429058324dfcSspeer 429158324dfcSspeer portn = nxgep->mac.portnum; 429258324dfcSspeer if (portn == XMAC_PORT_0 || portn == XMAC_PORT_1) 429358324dfcSspeer addrn = (uint8_t)slot - 1; 429458324dfcSspeer else 429558324dfcSspeer addrn = (uint8_t)slot; 429658324dfcSspeer 429758324dfcSspeer if (mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED) { 429858324dfcSspeer if (npi_mac_altaddr_disable(nxgep->npi_handle, portn, addrn) 42994045d941Ssowmini == NPI_SUCCESS) { 430058324dfcSspeer mmac_info->naddrfree++; 430158324dfcSspeer mmac_info->mac_pool[slot].flags &= ~MMAC_SLOT_USED; 430258324dfcSspeer /* 430358324dfcSspeer * Regardless if the MAC we just stopped filtering 430458324dfcSspeer * is a user addr or a facory addr, we must set 430558324dfcSspeer * the MMAC_VENDOR_ADDR flag if this slot has an 430658324dfcSspeer * associated factory MAC to indicate that a factory 430758324dfcSspeer * MAC is available. 430858324dfcSspeer */ 430958324dfcSspeer if (slot <= mmac_info->num_factory_mmac) { 431058324dfcSspeer mmac_info->mac_pool[slot].flags 43114045d941Ssowmini |= MMAC_VENDOR_ADDR; 431258324dfcSspeer } 431358324dfcSspeer /* 431458324dfcSspeer * Clear mac_pool[slot].addr so that kstat shows 0 431558324dfcSspeer * alternate MAC address if the slot is not used. 431658324dfcSspeer * (But nxge_m_mmac_get returns the factory MAC even 431758324dfcSspeer * when the slot is not used!) 431858324dfcSspeer */ 431958324dfcSspeer bzero(mmac_info->mac_pool[slot].addr, ETHERADDRL); 432058324dfcSspeer nxge_mmac_kstat_update(nxgep, slot, B_FALSE); 432158324dfcSspeer } else { 432258324dfcSspeer err = EIO; 432358324dfcSspeer } 432458324dfcSspeer } else { 432558324dfcSspeer err = EINVAL; 432658324dfcSspeer } 432758324dfcSspeer 432858324dfcSspeer mutex_exit(nxgep->genlock); 432958324dfcSspeer return (err); 433058324dfcSspeer } 433158324dfcSspeer 433258324dfcSspeer /* 4333da14cebeSEric Cheng * The callback to query all the factory addresses. naddr must be the same as 4334da14cebeSEric Cheng * the number of factory addresses (returned by MAC_CAPAB_MULTIFACTADDR), and 4335da14cebeSEric Cheng * mcm_addr is the space allocated for keep all the addresses, whose size is 4336da14cebeSEric Cheng * naddr * MAXMACADDRLEN. 433758324dfcSspeer */ 4338da14cebeSEric Cheng static void 4339da14cebeSEric Cheng nxge_m_getfactaddr(void *arg, uint_t naddr, uint8_t *addr) 434058324dfcSspeer { 4341da14cebeSEric Cheng nxge_t *nxgep = arg; 4342da14cebeSEric Cheng nxge_mmac_t *mmac_info; 4343da14cebeSEric Cheng int i; 434458324dfcSspeer 434558324dfcSspeer mutex_enter(nxgep->genlock); 434658324dfcSspeer 434758324dfcSspeer mmac_info = &nxgep->nxge_mmac_info; 4348da14cebeSEric Cheng ASSERT(naddr == mmac_info->num_factory_mmac); 434958324dfcSspeer 4350da14cebeSEric Cheng for (i = 0; i < naddr; i++) { 4351da14cebeSEric Cheng bcopy(mmac_info->factory_mac_pool[i + 1], 4352da14cebeSEric Cheng addr + i * MAXMACADDRLEN, ETHERADDRL); 435358324dfcSspeer } 435458324dfcSspeer 435558324dfcSspeer mutex_exit(nxgep->genlock); 435658324dfcSspeer } 435758324dfcSspeer 4358da14cebeSEric Cheng 435944961713Sgirish static boolean_t 436044961713Sgirish nxge_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 436144961713Sgirish { 436258324dfcSspeer nxge_t *nxgep = arg; 436358324dfcSspeer uint32_t *txflags = cap_data; 436444961713Sgirish 436558324dfcSspeer switch (cap) { 436658324dfcSspeer case MAC_CAPAB_HCKSUM: 4367678453a8Sspeer NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4368b4d05839Sml "==> nxge_m_getcapab: checksum %d", nxge_cksum_offload)); 4369b4d05839Sml if (nxge_cksum_offload <= 1) { 4370678453a8Sspeer *txflags = HCKSUM_INET_PARTIAL; 4371678453a8Sspeer } 437244961713Sgirish break; 4373678453a8Sspeer 4374da14cebeSEric Cheng case MAC_CAPAB_MULTIFACTADDR: { 4375da14cebeSEric Cheng mac_capab_multifactaddr_t *mfacp = cap_data; 437644961713Sgirish 437763f531d1SSriharsha Basavapatna if (!isLDOMguest(nxgep)) { 437863f531d1SSriharsha Basavapatna mutex_enter(nxgep->genlock); 437963f531d1SSriharsha Basavapatna mfacp->mcm_naddr = 438063f531d1SSriharsha Basavapatna nxgep->nxge_mmac_info.num_factory_mmac; 438163f531d1SSriharsha Basavapatna mfacp->mcm_getaddr = nxge_m_getfactaddr; 438263f531d1SSriharsha Basavapatna mutex_exit(nxgep->genlock); 438363f531d1SSriharsha Basavapatna } 438458324dfcSspeer break; 4385da14cebeSEric Cheng } 4386678453a8Sspeer 438730ac2e7bSml case MAC_CAPAB_LSO: { 438830ac2e7bSml mac_capab_lso_t *cap_lso = cap_data; 438930ac2e7bSml 43903d16f8e7Sml if (nxgep->soft_lso_enable) { 4391b4d05839Sml if (nxge_cksum_offload <= 1) { 4392b4d05839Sml cap_lso->lso_flags = LSO_TX_BASIC_TCP_IPV4; 4393b4d05839Sml if (nxge_lso_max > NXGE_LSO_MAXLEN) { 4394b4d05839Sml nxge_lso_max = NXGE_LSO_MAXLEN; 4395b4d05839Sml } 4396b4d05839Sml cap_lso->lso_basic_tcp_ipv4.lso_max = 4397b4d05839Sml nxge_lso_max; 439830ac2e7bSml } 439930ac2e7bSml break; 440030ac2e7bSml } else { 440130ac2e7bSml return (B_FALSE); 440230ac2e7bSml } 440330ac2e7bSml } 440430ac2e7bSml 4405678453a8Sspeer case MAC_CAPAB_RINGS: { 4406da14cebeSEric Cheng mac_capab_rings_t *cap_rings = cap_data; 4407da14cebeSEric Cheng p_nxge_hw_pt_cfg_t p_cfgp = &nxgep->pt_config.hw_config; 4408678453a8Sspeer 4409da14cebeSEric Cheng mutex_enter(nxgep->genlock); 4410da14cebeSEric Cheng if (cap_rings->mr_type == MAC_RING_TYPE_RX) { 441163f531d1SSriharsha Basavapatna if (isLDOMguest(nxgep)) { 441263f531d1SSriharsha Basavapatna cap_rings->mr_group_type = 441363f531d1SSriharsha Basavapatna MAC_GROUP_TYPE_STATIC; 441463f531d1SSriharsha Basavapatna cap_rings->mr_rnum = 441563f531d1SSriharsha Basavapatna NXGE_HIO_SHARE_MAX_CHANNELS; 441663f531d1SSriharsha Basavapatna cap_rings->mr_rget = nxge_fill_ring; 441763f531d1SSriharsha Basavapatna cap_rings->mr_gnum = 1; 441863f531d1SSriharsha Basavapatna cap_rings->mr_gget = nxge_hio_group_get; 441963f531d1SSriharsha Basavapatna cap_rings->mr_gaddring = NULL; 442063f531d1SSriharsha Basavapatna cap_rings->mr_gremring = NULL; 442163f531d1SSriharsha Basavapatna } else { 442263f531d1SSriharsha Basavapatna /* 442363f531d1SSriharsha Basavapatna * Service Domain. 442463f531d1SSriharsha Basavapatna */ 442563f531d1SSriharsha Basavapatna cap_rings->mr_group_type = 442663f531d1SSriharsha Basavapatna MAC_GROUP_TYPE_DYNAMIC; 442763f531d1SSriharsha Basavapatna cap_rings->mr_rnum = p_cfgp->max_rdcs; 442863f531d1SSriharsha Basavapatna cap_rings->mr_rget = nxge_fill_ring; 442963f531d1SSriharsha Basavapatna cap_rings->mr_gnum = p_cfgp->max_rdc_grpids; 443063f531d1SSriharsha Basavapatna cap_rings->mr_gget = nxge_hio_group_get; 443163f531d1SSriharsha Basavapatna cap_rings->mr_gaddring = nxge_group_add_ring; 443263f531d1SSriharsha Basavapatna cap_rings->mr_gremring = nxge_group_rem_ring; 443363f531d1SSriharsha Basavapatna } 4434da14cebeSEric Cheng 4435da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, RX_CTL, 4436da14cebeSEric Cheng "==> nxge_m_getcapab: rx nrings[%d] ngroups[%d]", 4437da14cebeSEric Cheng p_cfgp->max_rdcs, p_cfgp->max_rdc_grpids)); 4438da14cebeSEric Cheng } else { 443963f531d1SSriharsha Basavapatna /* 444063f531d1SSriharsha Basavapatna * TX Rings. 444163f531d1SSriharsha Basavapatna */ 444263f531d1SSriharsha Basavapatna if (isLDOMguest(nxgep)) { 444363f531d1SSriharsha Basavapatna cap_rings->mr_group_type = 444463f531d1SSriharsha Basavapatna MAC_GROUP_TYPE_STATIC; 444563f531d1SSriharsha Basavapatna cap_rings->mr_rnum = 444663f531d1SSriharsha Basavapatna NXGE_HIO_SHARE_MAX_CHANNELS; 444763f531d1SSriharsha Basavapatna cap_rings->mr_rget = nxge_fill_ring; 444863f531d1SSriharsha Basavapatna cap_rings->mr_gnum = 0; 444963f531d1SSriharsha Basavapatna cap_rings->mr_gget = NULL; 445063f531d1SSriharsha Basavapatna cap_rings->mr_gaddring = NULL; 445163f531d1SSriharsha Basavapatna cap_rings->mr_gremring = NULL; 445263f531d1SSriharsha Basavapatna } else { 445363f531d1SSriharsha Basavapatna /* 445463f531d1SSriharsha Basavapatna * Service Domain. 445563f531d1SSriharsha Basavapatna */ 445663f531d1SSriharsha Basavapatna cap_rings->mr_group_type = 445763f531d1SSriharsha Basavapatna MAC_GROUP_TYPE_DYNAMIC; 445863f531d1SSriharsha Basavapatna cap_rings->mr_rnum = p_cfgp->tdc.count; 445963f531d1SSriharsha Basavapatna cap_rings->mr_rget = nxge_fill_ring; 446063f531d1SSriharsha Basavapatna 446163f531d1SSriharsha Basavapatna /* 446263f531d1SSriharsha Basavapatna * Share capable. 446363f531d1SSriharsha Basavapatna * 446463f531d1SSriharsha Basavapatna * Do not report the default group: hence -1 446563f531d1SSriharsha Basavapatna */ 4466da14cebeSEric Cheng cap_rings->mr_gnum = 4467da14cebeSEric Cheng NXGE_MAX_TDC_GROUPS / nxgep->nports - 1; 446863f531d1SSriharsha Basavapatna cap_rings->mr_gget = nxge_hio_group_get; 446963f531d1SSriharsha Basavapatna cap_rings->mr_gaddring = nxge_group_add_ring; 447063f531d1SSriharsha Basavapatna cap_rings->mr_gremring = nxge_group_rem_ring; 4471678453a8Sspeer } 4472da14cebeSEric Cheng 4473da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, TX_CTL, 4474da14cebeSEric Cheng "==> nxge_m_getcapab: tx rings # of rings %d", 4475da14cebeSEric Cheng p_cfgp->tdc.count)); 4476da14cebeSEric Cheng } 4477da14cebeSEric Cheng mutex_exit(nxgep->genlock); 4478678453a8Sspeer break; 4479678453a8Sspeer } 4480678453a8Sspeer 4481da14cebeSEric Cheng #if defined(sun4v) 4482678453a8Sspeer case MAC_CAPAB_SHARES: { 4483678453a8Sspeer mac_capab_share_t *mshares = (mac_capab_share_t *)cap_data; 4484678453a8Sspeer 4485678453a8Sspeer /* 4486678453a8Sspeer * Only the service domain driver responds to 4487678453a8Sspeer * this capability request. 4488678453a8Sspeer */ 4489da14cebeSEric Cheng mutex_enter(nxgep->genlock); 4490678453a8Sspeer if (isLDOMservice(nxgep)) { 4491678453a8Sspeer mshares->ms_snum = 3; 4492678453a8Sspeer mshares->ms_handle = (void *)nxgep; 4493678453a8Sspeer mshares->ms_salloc = nxge_hio_share_alloc; 4494678453a8Sspeer mshares->ms_sfree = nxge_hio_share_free; 4495da14cebeSEric Cheng mshares->ms_sadd = nxge_hio_share_add_group; 4496da14cebeSEric Cheng mshares->ms_sremove = nxge_hio_share_rem_group; 4497678453a8Sspeer mshares->ms_squery = nxge_hio_share_query; 4498da14cebeSEric Cheng mshares->ms_sbind = nxge_hio_share_bind; 4499da14cebeSEric Cheng mshares->ms_sunbind = nxge_hio_share_unbind; 4500da14cebeSEric Cheng mutex_exit(nxgep->genlock); 4501da14cebeSEric Cheng } else { 4502da14cebeSEric Cheng mutex_exit(nxgep->genlock); 4503678453a8Sspeer return (B_FALSE); 4504da14cebeSEric Cheng } 4505678453a8Sspeer break; 4506678453a8Sspeer } 4507678453a8Sspeer #endif 450844961713Sgirish default: 450944961713Sgirish return (B_FALSE); 451044961713Sgirish } 451144961713Sgirish return (B_TRUE); 451244961713Sgirish } 451344961713Sgirish 45141bd6825cSml static boolean_t 45151bd6825cSml nxge_param_locked(mac_prop_id_t pr_num) 45161bd6825cSml { 45171bd6825cSml /* 45181bd6825cSml * All adv_* parameters are locked (read-only) while 45191bd6825cSml * the device is in any sort of loopback mode ... 45201bd6825cSml */ 45211bd6825cSml switch (pr_num) { 45223fd94f8cSam case MAC_PROP_ADV_1000FDX_CAP: 45233fd94f8cSam case MAC_PROP_EN_1000FDX_CAP: 45243fd94f8cSam case MAC_PROP_ADV_1000HDX_CAP: 45253fd94f8cSam case MAC_PROP_EN_1000HDX_CAP: 45263fd94f8cSam case MAC_PROP_ADV_100FDX_CAP: 45273fd94f8cSam case MAC_PROP_EN_100FDX_CAP: 45283fd94f8cSam case MAC_PROP_ADV_100HDX_CAP: 45293fd94f8cSam case MAC_PROP_EN_100HDX_CAP: 45303fd94f8cSam case MAC_PROP_ADV_10FDX_CAP: 45313fd94f8cSam case MAC_PROP_EN_10FDX_CAP: 45323fd94f8cSam case MAC_PROP_ADV_10HDX_CAP: 45333fd94f8cSam case MAC_PROP_EN_10HDX_CAP: 45343fd94f8cSam case MAC_PROP_AUTONEG: 45353fd94f8cSam case MAC_PROP_FLOWCTRL: 45361bd6825cSml return (B_TRUE); 45371bd6825cSml } 45381bd6825cSml return (B_FALSE); 45391bd6825cSml } 45401bd6825cSml 45411bd6825cSml /* 45421bd6825cSml * callback functions for set/get of properties 45431bd6825cSml */ 45441bd6825cSml static int 45451bd6825cSml nxge_m_setprop(void *barg, const char *pr_name, mac_prop_id_t pr_num, 45461bd6825cSml uint_t pr_valsize, const void *pr_val) 45471bd6825cSml { 45481bd6825cSml nxge_t *nxgep = barg; 45491bd6825cSml p_nxge_param_t param_arr; 45501bd6825cSml p_nxge_stats_t statsp; 45511bd6825cSml int err = 0; 45521bd6825cSml uint8_t val; 45531bd6825cSml uint32_t cur_mtu, new_mtu, old_framesize; 45541bd6825cSml link_flowctrl_t fl; 45551bd6825cSml 45561bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_setprop")); 45571bd6825cSml param_arr = nxgep->param_arr; 45581bd6825cSml statsp = nxgep->statsp; 45591bd6825cSml mutex_enter(nxgep->genlock); 45601bd6825cSml if (statsp->port_stats.lb_mode != nxge_lb_normal && 45611bd6825cSml nxge_param_locked(pr_num)) { 45621bd6825cSml /* 45631bd6825cSml * All adv_* parameters are locked (read-only) 45641bd6825cSml * while the device is in any sort of loopback mode. 45651bd6825cSml */ 45661bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 45671bd6825cSml "==> nxge_m_setprop: loopback mode: read only")); 45681bd6825cSml mutex_exit(nxgep->genlock); 45691bd6825cSml return (EBUSY); 45701bd6825cSml } 45711bd6825cSml 45721bd6825cSml val = *(uint8_t *)pr_val; 45731bd6825cSml switch (pr_num) { 45743fd94f8cSam case MAC_PROP_EN_1000FDX_CAP: 45751bd6825cSml nxgep->param_en_1000fdx = val; 45761bd6825cSml param_arr[param_anar_1000fdx].value = val; 45771bd6825cSml 45781bd6825cSml goto reprogram; 45791bd6825cSml 45803fd94f8cSam case MAC_PROP_EN_100FDX_CAP: 45811bd6825cSml nxgep->param_en_100fdx = val; 45821bd6825cSml param_arr[param_anar_100fdx].value = val; 45831bd6825cSml 45841bd6825cSml goto reprogram; 45851bd6825cSml 45863fd94f8cSam case MAC_PROP_EN_10FDX_CAP: 45871bd6825cSml nxgep->param_en_10fdx = val; 45881bd6825cSml param_arr[param_anar_10fdx].value = val; 45891bd6825cSml 45901bd6825cSml goto reprogram; 45911bd6825cSml 45923fd94f8cSam case MAC_PROP_EN_1000HDX_CAP: 45933fd94f8cSam case MAC_PROP_EN_100HDX_CAP: 45943fd94f8cSam case MAC_PROP_EN_10HDX_CAP: 45953fd94f8cSam case MAC_PROP_ADV_1000FDX_CAP: 45963fd94f8cSam case MAC_PROP_ADV_1000HDX_CAP: 45973fd94f8cSam case MAC_PROP_ADV_100FDX_CAP: 45983fd94f8cSam case MAC_PROP_ADV_100HDX_CAP: 45993fd94f8cSam case MAC_PROP_ADV_10FDX_CAP: 46003fd94f8cSam case MAC_PROP_ADV_10HDX_CAP: 46013fd94f8cSam case MAC_PROP_STATUS: 46023fd94f8cSam case MAC_PROP_SPEED: 46033fd94f8cSam case MAC_PROP_DUPLEX: 46041bd6825cSml err = EINVAL; /* cannot set read-only properties */ 46051bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 46061bd6825cSml "==> nxge_m_setprop: read only property %d", 46071bd6825cSml pr_num)); 46081bd6825cSml break; 46091bd6825cSml 46103fd94f8cSam case MAC_PROP_AUTONEG: 46111bd6825cSml param_arr[param_autoneg].value = val; 46121bd6825cSml 46131bd6825cSml goto reprogram; 46141bd6825cSml 46153fd94f8cSam case MAC_PROP_MTU: 46161bd6825cSml cur_mtu = nxgep->mac.default_mtu; 46171bd6825cSml bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 46181bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 46191bd6825cSml "==> nxge_m_setprop: set MTU: %d is_jumbo %d", 46201bd6825cSml new_mtu, nxgep->mac.is_jumbo)); 46211bd6825cSml 46221bd6825cSml if (new_mtu == cur_mtu) { 46231bd6825cSml err = 0; 46241bd6825cSml break; 46251bd6825cSml } 462648056c53SMichael Speer 4627afdda45fSVasumathi Sundaram - Sun Microsystems if (nxgep->nxge_mac_state == NXGE_MAC_STARTED) { 4628afdda45fSVasumathi Sundaram - Sun Microsystems err = EBUSY; 4629afdda45fSVasumathi Sundaram - Sun Microsystems break; 4630afdda45fSVasumathi Sundaram - Sun Microsystems } 46311bd6825cSml 463248056c53SMichael Speer if ((new_mtu < NXGE_DEFAULT_MTU) || 463348056c53SMichael Speer (new_mtu > NXGE_MAXIMUM_MTU)) { 46341bd6825cSml err = EINVAL; 46351bd6825cSml break; 46361bd6825cSml } 46371bd6825cSml 46381bd6825cSml old_framesize = (uint32_t)nxgep->mac.maxframesize; 46391bd6825cSml nxgep->mac.maxframesize = (uint16_t) 46401bd6825cSml (new_mtu + NXGE_EHEADER_VLAN_CRC); 46411bd6825cSml if (nxge_mac_set_framesize(nxgep)) { 4642c2d37b8bSml nxgep->mac.maxframesize = 4643c2d37b8bSml (uint16_t)old_framesize; 46441bd6825cSml err = EINVAL; 46451bd6825cSml break; 46461bd6825cSml } 46471bd6825cSml 46481bd6825cSml err = mac_maxsdu_update(nxgep->mach, new_mtu); 46491bd6825cSml if (err) { 4650c2d37b8bSml nxgep->mac.maxframesize = 4651c2d37b8bSml (uint16_t)old_framesize; 46521bd6825cSml err = EINVAL; 46531bd6825cSml break; 46541bd6825cSml } 46551bd6825cSml 46561bd6825cSml nxgep->mac.default_mtu = new_mtu; 465748056c53SMichael Speer if (new_mtu > NXGE_DEFAULT_MTU) 465848056c53SMichael Speer nxgep->mac.is_jumbo = B_TRUE; 465948056c53SMichael Speer else 466048056c53SMichael Speer nxgep->mac.is_jumbo = B_FALSE; 466148056c53SMichael Speer 46621bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 46631bd6825cSml "==> nxge_m_setprop: set MTU: %d maxframe %d", 46641bd6825cSml new_mtu, nxgep->mac.maxframesize)); 46651bd6825cSml break; 46661bd6825cSml 46673fd94f8cSam case MAC_PROP_FLOWCTRL: 46681bd6825cSml bcopy(pr_val, &fl, sizeof (fl)); 46691bd6825cSml switch (fl) { 46701bd6825cSml default: 46711bd6825cSml err = EINVAL; 46721bd6825cSml break; 46731bd6825cSml 46741bd6825cSml case LINK_FLOWCTRL_NONE: 46751bd6825cSml param_arr[param_anar_pause].value = 0; 46761bd6825cSml break; 46771bd6825cSml 46781bd6825cSml case LINK_FLOWCTRL_RX: 46791bd6825cSml param_arr[param_anar_pause].value = 1; 46801bd6825cSml break; 46811bd6825cSml 46821bd6825cSml case LINK_FLOWCTRL_TX: 46831bd6825cSml case LINK_FLOWCTRL_BI: 46841bd6825cSml err = EINVAL; 46851bd6825cSml break; 46861bd6825cSml } 46871bd6825cSml 46881bd6825cSml reprogram: 46891bd6825cSml if (err == 0) { 46901bd6825cSml if (!nxge_param_link_update(nxgep)) { 46911bd6825cSml err = EINVAL; 46921bd6825cSml } 46931bd6825cSml } 46941bd6825cSml break; 46953fd94f8cSam case MAC_PROP_PRIVATE: 46961bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 46971bd6825cSml "==> nxge_m_setprop: private property")); 46981bd6825cSml err = nxge_set_priv_prop(nxgep, pr_name, pr_valsize, 46991bd6825cSml pr_val); 47001bd6825cSml break; 47014045d941Ssowmini 47024045d941Ssowmini default: 47034045d941Ssowmini err = ENOTSUP; 47044045d941Ssowmini break; 47051bd6825cSml } 47061bd6825cSml 47071bd6825cSml mutex_exit(nxgep->genlock); 47081bd6825cSml 47091bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 47101bd6825cSml "<== nxge_m_setprop (return %d)", err)); 47111bd6825cSml return (err); 47121bd6825cSml } 47131bd6825cSml 47141bd6825cSml static int 47151bd6825cSml nxge_m_getprop(void *barg, const char *pr_name, mac_prop_id_t pr_num, 4716afdda45fSVasumathi Sundaram - Sun Microsystems uint_t pr_flags, uint_t pr_valsize, void *pr_val, uint_t *perm) 47171bd6825cSml { 47181bd6825cSml nxge_t *nxgep = barg; 47191bd6825cSml p_nxge_param_t param_arr = nxgep->param_arr; 47201bd6825cSml p_nxge_stats_t statsp = nxgep->statsp; 47211bd6825cSml int err = 0; 47221bd6825cSml link_flowctrl_t fl; 47231bd6825cSml uint64_t tmp = 0; 47244045d941Ssowmini link_state_t ls; 47253fd94f8cSam boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 47261bd6825cSml 47271bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 47281bd6825cSml "==> nxge_m_getprop: pr_num %d", pr_num)); 47294045d941Ssowmini 47304045d941Ssowmini if (pr_valsize == 0) 47314045d941Ssowmini return (EINVAL); 47324045d941Ssowmini 4733afdda45fSVasumathi Sundaram - Sun Microsystems *perm = MAC_PROP_PERM_RW; 4734afdda45fSVasumathi Sundaram - Sun Microsystems 47353fd94f8cSam if ((is_default) && (pr_num != MAC_PROP_PRIVATE)) { 47364045d941Ssowmini err = nxge_get_def_val(nxgep, pr_num, pr_valsize, pr_val); 47374045d941Ssowmini return (err); 47384045d941Ssowmini } 47394045d941Ssowmini 47401bd6825cSml bzero(pr_val, pr_valsize); 47411bd6825cSml switch (pr_num) { 47423fd94f8cSam case MAC_PROP_DUPLEX: 4743afdda45fSVasumathi Sundaram - Sun Microsystems *perm = MAC_PROP_PERM_READ; 47441bd6825cSml *(uint8_t *)pr_val = statsp->mac_stats.link_duplex; 47451bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 47461bd6825cSml "==> nxge_m_getprop: duplex mode %d", 47471bd6825cSml *(uint8_t *)pr_val)); 47481bd6825cSml break; 47491bd6825cSml 47503fd94f8cSam case MAC_PROP_SPEED: 47511bd6825cSml if (pr_valsize < sizeof (uint64_t)) 47521bd6825cSml return (EINVAL); 4753afdda45fSVasumathi Sundaram - Sun Microsystems *perm = MAC_PROP_PERM_READ; 47541bd6825cSml tmp = statsp->mac_stats.link_speed * 1000000ull; 47551bd6825cSml bcopy(&tmp, pr_val, sizeof (tmp)); 47561bd6825cSml break; 47571bd6825cSml 47583fd94f8cSam case MAC_PROP_STATUS: 47594045d941Ssowmini if (pr_valsize < sizeof (link_state_t)) 47601bd6825cSml return (EINVAL); 4761afdda45fSVasumathi Sundaram - Sun Microsystems *perm = MAC_PROP_PERM_READ; 47624045d941Ssowmini if (!statsp->mac_stats.link_up) 47634045d941Ssowmini ls = LINK_STATE_DOWN; 47644045d941Ssowmini else 47654045d941Ssowmini ls = LINK_STATE_UP; 47664045d941Ssowmini bcopy(&ls, pr_val, sizeof (ls)); 47671bd6825cSml break; 47681bd6825cSml 47693fd94f8cSam case MAC_PROP_AUTONEG: 47701bd6825cSml *(uint8_t *)pr_val = 47711bd6825cSml param_arr[param_autoneg].value; 47721bd6825cSml break; 47731bd6825cSml 47743fd94f8cSam case MAC_PROP_FLOWCTRL: 47751bd6825cSml if (pr_valsize < sizeof (link_flowctrl_t)) 47761bd6825cSml return (EINVAL); 47771bd6825cSml 47781bd6825cSml fl = LINK_FLOWCTRL_NONE; 47791bd6825cSml if (param_arr[param_anar_pause].value) { 47801bd6825cSml fl = LINK_FLOWCTRL_RX; 47811bd6825cSml } 47821bd6825cSml bcopy(&fl, pr_val, sizeof (fl)); 47831bd6825cSml break; 47841bd6825cSml 47853fd94f8cSam case MAC_PROP_ADV_1000FDX_CAP: 4786afdda45fSVasumathi Sundaram - Sun Microsystems *perm = MAC_PROP_PERM_READ; 47871bd6825cSml *(uint8_t *)pr_val = 47881bd6825cSml param_arr[param_anar_1000fdx].value; 47891bd6825cSml break; 47901bd6825cSml 47913fd94f8cSam case MAC_PROP_EN_1000FDX_CAP: 47921bd6825cSml *(uint8_t *)pr_val = nxgep->param_en_1000fdx; 47931bd6825cSml break; 47941bd6825cSml 47953fd94f8cSam case MAC_PROP_ADV_100FDX_CAP: 4796afdda45fSVasumathi Sundaram - Sun Microsystems *perm = MAC_PROP_PERM_READ; 47971bd6825cSml *(uint8_t *)pr_val = 47981bd6825cSml param_arr[param_anar_100fdx].value; 47991bd6825cSml break; 48001bd6825cSml 48013fd94f8cSam case MAC_PROP_EN_100FDX_CAP: 48021bd6825cSml *(uint8_t *)pr_val = nxgep->param_en_100fdx; 48031bd6825cSml break; 48041bd6825cSml 48053fd94f8cSam case MAC_PROP_ADV_10FDX_CAP: 4806afdda45fSVasumathi Sundaram - Sun Microsystems *perm = MAC_PROP_PERM_READ; 48071bd6825cSml *(uint8_t *)pr_val = 48081bd6825cSml param_arr[param_anar_10fdx].value; 48091bd6825cSml break; 48101bd6825cSml 48113fd94f8cSam case MAC_PROP_EN_10FDX_CAP: 48121bd6825cSml *(uint8_t *)pr_val = nxgep->param_en_10fdx; 48131bd6825cSml break; 48141bd6825cSml 48153fd94f8cSam case MAC_PROP_EN_1000HDX_CAP: 48163fd94f8cSam case MAC_PROP_EN_100HDX_CAP: 48173fd94f8cSam case MAC_PROP_EN_10HDX_CAP: 48183fd94f8cSam case MAC_PROP_ADV_1000HDX_CAP: 48193fd94f8cSam case MAC_PROP_ADV_100HDX_CAP: 48203fd94f8cSam case MAC_PROP_ADV_10HDX_CAP: 48214045d941Ssowmini err = ENOTSUP; 48221bd6825cSml break; 48231bd6825cSml 48243fd94f8cSam case MAC_PROP_PRIVATE: 48254045d941Ssowmini err = nxge_get_priv_prop(nxgep, pr_name, pr_flags, 4826afdda45fSVasumathi Sundaram - Sun Microsystems pr_valsize, pr_val, perm); 48274045d941Ssowmini break; 4828f0f2c3a5SGirish Moodalbail 4829f0f2c3a5SGirish Moodalbail case MAC_PROP_MTU: { 4830f0f2c3a5SGirish Moodalbail mac_propval_range_t range; 4831f0f2c3a5SGirish Moodalbail 4832f0f2c3a5SGirish Moodalbail if (!(pr_flags & MAC_PROP_POSSIBLE)) 4833f0f2c3a5SGirish Moodalbail return (ENOTSUP); 4834f0f2c3a5SGirish Moodalbail if (pr_valsize < sizeof (mac_propval_range_t)) 4835f0f2c3a5SGirish Moodalbail return (EINVAL); 4836f0f2c3a5SGirish Moodalbail range.mpr_count = 1; 4837f0f2c3a5SGirish Moodalbail range.mpr_type = MAC_PROPVAL_UINT32; 4838f0f2c3a5SGirish Moodalbail range.range_uint32[0].mpur_min = 4839f0f2c3a5SGirish Moodalbail range.range_uint32[0].mpur_max = NXGE_DEFAULT_MTU; 4840290b5530SMichael Speer range.range_uint32[0].mpur_max = NXGE_MAXIMUM_MTU; 4841f0f2c3a5SGirish Moodalbail bcopy(&range, pr_val, sizeof (range)); 4842f0f2c3a5SGirish Moodalbail break; 4843f0f2c3a5SGirish Moodalbail } 48441bd6825cSml default: 48454045d941Ssowmini err = EINVAL; 48464045d941Ssowmini break; 48471bd6825cSml } 48481bd6825cSml 48491bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_getprop")); 48501bd6825cSml 48511bd6825cSml return (err); 48521bd6825cSml } 48531bd6825cSml 48541bd6825cSml /* ARGSUSED */ 48551bd6825cSml static int 48561bd6825cSml nxge_set_priv_prop(p_nxge_t nxgep, const char *pr_name, uint_t pr_valsize, 48571bd6825cSml const void *pr_val) 48581bd6825cSml { 48591bd6825cSml p_nxge_param_t param_arr = nxgep->param_arr; 48601bd6825cSml int err = 0; 48611bd6825cSml long result; 48621bd6825cSml 48631bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 48641bd6825cSml "==> nxge_set_priv_prop: name %s", pr_name)); 48651bd6825cSml 48661bd6825cSml /* Blanking */ 48671bd6825cSml if (strcmp(pr_name, "_rxdma_intr_time") == 0) { 48681bd6825cSml err = nxge_param_rx_intr_time(nxgep, NULL, NULL, 48691bd6825cSml (char *)pr_val, 48701bd6825cSml (caddr_t)¶m_arr[param_rxdma_intr_time]); 48711bd6825cSml if (err) { 48721bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 48731bd6825cSml "<== nxge_set_priv_prop: " 48741bd6825cSml "unable to set (%s)", pr_name)); 48751bd6825cSml err = EINVAL; 48761bd6825cSml } else { 48771bd6825cSml err = 0; 48781bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 48791bd6825cSml "<== nxge_set_priv_prop: " 48801bd6825cSml "set (%s)", pr_name)); 48811bd6825cSml } 48821bd6825cSml 48831bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 48841bd6825cSml "<== nxge_set_priv_prop: name %s (value %d)", 48851bd6825cSml pr_name, result)); 48861bd6825cSml 48871bd6825cSml return (err); 48881bd6825cSml } 48891bd6825cSml 48901bd6825cSml if (strcmp(pr_name, "_rxdma_intr_pkts") == 0) { 48911bd6825cSml err = nxge_param_rx_intr_pkts(nxgep, NULL, NULL, 48921bd6825cSml (char *)pr_val, 48931bd6825cSml (caddr_t)¶m_arr[param_rxdma_intr_pkts]); 48941bd6825cSml if (err) { 48951bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 48961bd6825cSml "<== nxge_set_priv_prop: " 48971bd6825cSml "unable to set (%s)", pr_name)); 48981bd6825cSml err = EINVAL; 48991bd6825cSml } else { 49001bd6825cSml err = 0; 49011bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 49021bd6825cSml "<== nxge_set_priv_prop: " 49031bd6825cSml "set (%s)", pr_name)); 49041bd6825cSml } 49051bd6825cSml 49061bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 49071bd6825cSml "<== nxge_set_priv_prop: name %s (value %d)", 49081bd6825cSml pr_name, result)); 49091bd6825cSml 49101bd6825cSml return (err); 49111bd6825cSml } 49121bd6825cSml 49131bd6825cSml /* Classification */ 49141bd6825cSml if (strcmp(pr_name, "_class_opt_ipv4_tcp") == 0) { 49151bd6825cSml if (pr_val == NULL) { 49161bd6825cSml err = EINVAL; 49171bd6825cSml return (err); 49181bd6825cSml } 49191bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 49201bd6825cSml 49211bd6825cSml err = nxge_param_set_ip_opt(nxgep, NULL, 49221bd6825cSml NULL, (char *)pr_val, 49231bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv4_tcp]); 49241bd6825cSml 49251bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 49261bd6825cSml "<== nxge_set_priv_prop: name %s (value 0x%x)", 49271bd6825cSml pr_name, result)); 49281bd6825cSml 49291bd6825cSml return (err); 49301bd6825cSml } 49311bd6825cSml 49321bd6825cSml if (strcmp(pr_name, "_class_opt_ipv4_udp") == 0) { 49331bd6825cSml if (pr_val == NULL) { 49341bd6825cSml err = EINVAL; 49351bd6825cSml return (err); 49361bd6825cSml } 49371bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 49381bd6825cSml 49391bd6825cSml err = nxge_param_set_ip_opt(nxgep, NULL, 49401bd6825cSml NULL, (char *)pr_val, 49411bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv4_udp]); 49421bd6825cSml 49431bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 49441bd6825cSml "<== nxge_set_priv_prop: name %s (value 0x%x)", 49451bd6825cSml pr_name, result)); 49461bd6825cSml 49471bd6825cSml return (err); 49481bd6825cSml } 49491bd6825cSml if (strcmp(pr_name, "_class_opt_ipv4_ah") == 0) { 49501bd6825cSml if (pr_val == NULL) { 49511bd6825cSml err = EINVAL; 49521bd6825cSml return (err); 49531bd6825cSml } 49541bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 49551bd6825cSml 49561bd6825cSml err = nxge_param_set_ip_opt(nxgep, NULL, 49571bd6825cSml NULL, (char *)pr_val, 49581bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv4_ah]); 49591bd6825cSml 49601bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 49611bd6825cSml "<== nxge_set_priv_prop: name %s (value 0x%x)", 49621bd6825cSml pr_name, result)); 49631bd6825cSml 49641bd6825cSml return (err); 49651bd6825cSml } 49661bd6825cSml if (strcmp(pr_name, "_class_opt_ipv4_sctp") == 0) { 49671bd6825cSml if (pr_val == NULL) { 49681bd6825cSml err = EINVAL; 49691bd6825cSml return (err); 49701bd6825cSml } 49711bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 49721bd6825cSml 49731bd6825cSml err = nxge_param_set_ip_opt(nxgep, NULL, 49741bd6825cSml NULL, (char *)pr_val, 49751bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv4_sctp]); 49761bd6825cSml 49771bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 49781bd6825cSml "<== nxge_set_priv_prop: name %s (value 0x%x)", 49791bd6825cSml pr_name, result)); 49801bd6825cSml 49811bd6825cSml return (err); 49821bd6825cSml } 49831bd6825cSml 49841bd6825cSml if (strcmp(pr_name, "_class_opt_ipv6_tcp") == 0) { 49851bd6825cSml if (pr_val == NULL) { 49861bd6825cSml err = EINVAL; 49871bd6825cSml return (err); 49881bd6825cSml } 49891bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 49901bd6825cSml 49911bd6825cSml err = nxge_param_set_ip_opt(nxgep, NULL, 49921bd6825cSml NULL, (char *)pr_val, 49931bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv6_tcp]); 49941bd6825cSml 49951bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 49961bd6825cSml "<== nxge_set_priv_prop: name %s (value 0x%x)", 49971bd6825cSml pr_name, result)); 49981bd6825cSml 49991bd6825cSml return (err); 50001bd6825cSml } 50011bd6825cSml 50021bd6825cSml if (strcmp(pr_name, "_class_opt_ipv6_udp") == 0) { 50031bd6825cSml if (pr_val == NULL) { 50041bd6825cSml err = EINVAL; 50051bd6825cSml return (err); 50061bd6825cSml } 50071bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 50081bd6825cSml 50091bd6825cSml err = nxge_param_set_ip_opt(nxgep, NULL, 50101bd6825cSml NULL, (char *)pr_val, 50111bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv6_udp]); 50121bd6825cSml 50131bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 50141bd6825cSml "<== nxge_set_priv_prop: name %s (value 0x%x)", 50151bd6825cSml pr_name, result)); 50161bd6825cSml 50171bd6825cSml return (err); 50181bd6825cSml } 50191bd6825cSml if (strcmp(pr_name, "_class_opt_ipv6_ah") == 0) { 50201bd6825cSml if (pr_val == NULL) { 50211bd6825cSml err = EINVAL; 50221bd6825cSml return (err); 50231bd6825cSml } 50241bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 50251bd6825cSml 50261bd6825cSml err = nxge_param_set_ip_opt(nxgep, NULL, 50271bd6825cSml NULL, (char *)pr_val, 50281bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv6_ah]); 50291bd6825cSml 50301bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 50311bd6825cSml "<== nxge_set_priv_prop: name %s (value 0x%x)", 50321bd6825cSml pr_name, result)); 50331bd6825cSml 50341bd6825cSml return (err); 50351bd6825cSml } 50361bd6825cSml if (strcmp(pr_name, "_class_opt_ipv6_sctp") == 0) { 50371bd6825cSml if (pr_val == NULL) { 50381bd6825cSml err = EINVAL; 50391bd6825cSml return (err); 50401bd6825cSml } 50411bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 50421bd6825cSml 50431bd6825cSml err = nxge_param_set_ip_opt(nxgep, NULL, 50441bd6825cSml NULL, (char *)pr_val, 50451bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv6_sctp]); 50461bd6825cSml 50471bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 50481bd6825cSml "<== nxge_set_priv_prop: name %s (value 0x%x)", 50491bd6825cSml pr_name, result)); 50501bd6825cSml 50511bd6825cSml return (err); 50521bd6825cSml } 50531bd6825cSml 50541bd6825cSml if (strcmp(pr_name, "_soft_lso_enable") == 0) { 50551bd6825cSml if (pr_val == NULL) { 50561bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 50571bd6825cSml "==> nxge_set_priv_prop: name %s (null)", pr_name)); 50581bd6825cSml err = EINVAL; 50591bd6825cSml return (err); 50601bd6825cSml } 50611bd6825cSml 50621bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 50631bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 50641bd6825cSml "<== nxge_set_priv_prop: name %s " 50651bd6825cSml "(lso %d pr_val %s value %d)", 50661bd6825cSml pr_name, nxgep->soft_lso_enable, pr_val, result)); 50671bd6825cSml 50681bd6825cSml if (result > 1 || result < 0) { 50691bd6825cSml err = EINVAL; 50701bd6825cSml } else { 50711bd6825cSml if (nxgep->soft_lso_enable == (uint32_t)result) { 50721bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 50731bd6825cSml "no change (%d %d)", 50741bd6825cSml nxgep->soft_lso_enable, result)); 50751bd6825cSml return (0); 50761bd6825cSml } 50771bd6825cSml } 50781bd6825cSml 50791bd6825cSml nxgep->soft_lso_enable = (int)result; 50801bd6825cSml 50811bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 50821bd6825cSml "<== nxge_set_priv_prop: name %s (value %d)", 50831bd6825cSml pr_name, result)); 50841bd6825cSml 50851bd6825cSml return (err); 50861bd6825cSml } 508700161856Syc /* 508800161856Syc * Commands like "ndd -set /dev/nxge0 adv_10gfdx_cap 1" cause the 508900161856Syc * following code to be executed. 509000161856Syc */ 50914045d941Ssowmini if (strcmp(pr_name, "_adv_10gfdx_cap") == 0) { 50924045d941Ssowmini err = nxge_param_set_mac(nxgep, NULL, NULL, (char *)pr_val, 50934045d941Ssowmini (caddr_t)¶m_arr[param_anar_10gfdx]); 50944045d941Ssowmini return (err); 50954045d941Ssowmini } 50964045d941Ssowmini if (strcmp(pr_name, "_adv_pause_cap") == 0) { 50974045d941Ssowmini err = nxge_param_set_mac(nxgep, NULL, NULL, (char *)pr_val, 50984045d941Ssowmini (caddr_t)¶m_arr[param_anar_pause]); 50994045d941Ssowmini return (err); 51004045d941Ssowmini } 51011bd6825cSml 51021bd6825cSml return (EINVAL); 51031bd6825cSml } 51041bd6825cSml 51051bd6825cSml static int 51064045d941Ssowmini nxge_get_priv_prop(p_nxge_t nxgep, const char *pr_name, uint_t pr_flags, 5107afdda45fSVasumathi Sundaram - Sun Microsystems uint_t pr_valsize, void *pr_val, uint_t *perm) 51081bd6825cSml { 51091bd6825cSml p_nxge_param_t param_arr = nxgep->param_arr; 51101bd6825cSml char valstr[MAXNAMELEN]; 51111bd6825cSml int err = EINVAL; 51121bd6825cSml uint_t strsize; 51133fd94f8cSam boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 51141bd6825cSml 51151bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 51161bd6825cSml "==> nxge_get_priv_prop: property %s", pr_name)); 51171bd6825cSml 51181bd6825cSml /* function number */ 51191bd6825cSml if (strcmp(pr_name, "_function_number") == 0) { 51204045d941Ssowmini if (is_default) 51214045d941Ssowmini return (ENOTSUP); 5122afdda45fSVasumathi Sundaram - Sun Microsystems *perm = MAC_PROP_PERM_READ; 51234045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%d", 51244045d941Ssowmini nxgep->function_num); 51251bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 51261bd6825cSml "==> nxge_get_priv_prop: name %s " 51271bd6825cSml "(value %d valstr %s)", 51281bd6825cSml pr_name, nxgep->function_num, valstr)); 51291bd6825cSml 51301bd6825cSml err = 0; 51311bd6825cSml goto done; 51321bd6825cSml } 51331bd6825cSml 51341bd6825cSml /* Neptune firmware version */ 51351bd6825cSml if (strcmp(pr_name, "_fw_version") == 0) { 51364045d941Ssowmini if (is_default) 51374045d941Ssowmini return (ENOTSUP); 5138afdda45fSVasumathi Sundaram - Sun Microsystems *perm = MAC_PROP_PERM_READ; 51394045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%s", 51404045d941Ssowmini nxgep->vpd_info.ver); 51411bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 51421bd6825cSml "==> nxge_get_priv_prop: name %s " 51431bd6825cSml "(value %d valstr %s)", 51441bd6825cSml pr_name, nxgep->vpd_info.ver, valstr)); 51451bd6825cSml 51461bd6825cSml err = 0; 51471bd6825cSml goto done; 51481bd6825cSml } 51491bd6825cSml 51501bd6825cSml /* port PHY mode */ 51511bd6825cSml if (strcmp(pr_name, "_port_mode") == 0) { 51524045d941Ssowmini if (is_default) 51534045d941Ssowmini return (ENOTSUP); 5154afdda45fSVasumathi Sundaram - Sun Microsystems *perm = MAC_PROP_PERM_READ; 51551bd6825cSml switch (nxgep->mac.portmode) { 51561bd6825cSml case PORT_1G_COPPER: 51574045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "1G copper %s", 51581bd6825cSml nxgep->hot_swappable_phy ? 51591bd6825cSml "[Hot Swappable]" : ""); 51601bd6825cSml break; 51611bd6825cSml case PORT_1G_FIBER: 51624045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "1G fiber %s", 51631bd6825cSml nxgep->hot_swappable_phy ? 51641bd6825cSml "[hot swappable]" : ""); 51651bd6825cSml break; 51661bd6825cSml case PORT_10G_COPPER: 51674045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), 51684045d941Ssowmini "10G copper %s", 51691bd6825cSml nxgep->hot_swappable_phy ? 51701bd6825cSml "[hot swappable]" : ""); 51711bd6825cSml break; 51721bd6825cSml case PORT_10G_FIBER: 51734045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "10G fiber %s", 51741bd6825cSml nxgep->hot_swappable_phy ? 51751bd6825cSml "[hot swappable]" : ""); 51761bd6825cSml break; 51771bd6825cSml case PORT_10G_SERDES: 51784045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), 51794045d941Ssowmini "10G serdes %s", nxgep->hot_swappable_phy ? 51801bd6825cSml "[hot swappable]" : ""); 51811bd6825cSml break; 51821bd6825cSml case PORT_1G_SERDES: 51834045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "1G serdes %s", 51841bd6825cSml nxgep->hot_swappable_phy ? 51851bd6825cSml "[hot swappable]" : ""); 51861bd6825cSml break; 518700161856Syc case PORT_1G_TN1010: 518800161856Syc (void) snprintf(valstr, sizeof (valstr), 518900161856Syc "1G TN1010 copper %s", nxgep->hot_swappable_phy ? 519000161856Syc "[hot swappable]" : ""); 519100161856Syc break; 519200161856Syc case PORT_10G_TN1010: 519300161856Syc (void) snprintf(valstr, sizeof (valstr), 519400161856Syc "10G TN1010 copper %s", nxgep->hot_swappable_phy ? 519500161856Syc "[hot swappable]" : ""); 519600161856Syc break; 51971bd6825cSml case PORT_1G_RGMII_FIBER: 51984045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), 51994045d941Ssowmini "1G rgmii fiber %s", nxgep->hot_swappable_phy ? 52001bd6825cSml "[hot swappable]" : ""); 52011bd6825cSml break; 52021bd6825cSml case PORT_HSP_MODE: 52034045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), 5204c2d37b8bSml "phy not present[hot swappable]"); 52051bd6825cSml break; 52061bd6825cSml default: 52074045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "unknown %s", 52081bd6825cSml nxgep->hot_swappable_phy ? 52091bd6825cSml "[hot swappable]" : ""); 52101bd6825cSml break; 52111bd6825cSml } 52121bd6825cSml 52131bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 52141bd6825cSml "==> nxge_get_priv_prop: name %s (value %s)", 52151bd6825cSml pr_name, valstr)); 52161bd6825cSml 52171bd6825cSml err = 0; 52181bd6825cSml goto done; 52191bd6825cSml } 52201bd6825cSml 52211bd6825cSml /* Hot swappable PHY */ 52221bd6825cSml if (strcmp(pr_name, "_hot_swap_phy") == 0) { 52234045d941Ssowmini if (is_default) 52244045d941Ssowmini return (ENOTSUP); 5225afdda45fSVasumathi Sundaram - Sun Microsystems *perm = MAC_PROP_PERM_READ; 52264045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%s", 52271bd6825cSml nxgep->hot_swappable_phy ? 52281bd6825cSml "yes" : "no"); 52291bd6825cSml 52301bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 52311bd6825cSml "==> nxge_get_priv_prop: name %s " 52321bd6825cSml "(value %d valstr %s)", 52331bd6825cSml pr_name, nxgep->hot_swappable_phy, valstr)); 52341bd6825cSml 52351bd6825cSml err = 0; 52361bd6825cSml goto done; 52371bd6825cSml } 52381bd6825cSml 52391bd6825cSml 52401bd6825cSml /* Receive Interrupt Blanking Parameters */ 52411bd6825cSml if (strcmp(pr_name, "_rxdma_intr_time") == 0) { 52424045d941Ssowmini err = 0; 52434045d941Ssowmini if (is_default) { 52444045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), 52454045d941Ssowmini "%d", RXDMA_RCR_TO_DEFAULT); 52464045d941Ssowmini goto done; 52474045d941Ssowmini } 52484045d941Ssowmini 52494045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%d", 52504045d941Ssowmini nxgep->intr_timeout); 52511bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 52521bd6825cSml "==> nxge_get_priv_prop: name %s (value %d)", 52531bd6825cSml pr_name, 52541bd6825cSml (uint32_t)nxgep->intr_timeout)); 52551bd6825cSml goto done; 52561bd6825cSml } 52571bd6825cSml 52581bd6825cSml if (strcmp(pr_name, "_rxdma_intr_pkts") == 0) { 52594045d941Ssowmini err = 0; 52604045d941Ssowmini if (is_default) { 52614045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), 52624045d941Ssowmini "%d", RXDMA_RCR_PTHRES_DEFAULT); 52634045d941Ssowmini goto done; 52644045d941Ssowmini } 52654045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%d", 52664045d941Ssowmini nxgep->intr_threshold); 52671bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 52681bd6825cSml "==> nxge_get_priv_prop: name %s (value %d)", 52691bd6825cSml pr_name, (uint32_t)nxgep->intr_threshold)); 52701bd6825cSml 52711bd6825cSml goto done; 52721bd6825cSml } 52731bd6825cSml 52741bd6825cSml /* Classification and Load Distribution Configuration */ 52751bd6825cSml if (strcmp(pr_name, "_class_opt_ipv4_tcp") == 0) { 52764045d941Ssowmini if (is_default) { 52774045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 52784045d941Ssowmini NXGE_CLASS_FLOW_GEN_SERVER); 52794045d941Ssowmini err = 0; 52804045d941Ssowmini goto done; 52814045d941Ssowmini } 52821bd6825cSml err = nxge_dld_get_ip_opt(nxgep, 52831bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv4_tcp]); 52841bd6825cSml 52854045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 52861bd6825cSml (int)param_arr[param_class_opt_ipv4_tcp].value); 52871bd6825cSml 52881bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 52891bd6825cSml "==> nxge_get_priv_prop: %s", valstr)); 52901bd6825cSml goto done; 52911bd6825cSml } 52921bd6825cSml 52931bd6825cSml if (strcmp(pr_name, "_class_opt_ipv4_udp") == 0) { 52944045d941Ssowmini if (is_default) { 52954045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 52964045d941Ssowmini NXGE_CLASS_FLOW_GEN_SERVER); 52974045d941Ssowmini err = 0; 52984045d941Ssowmini goto done; 52994045d941Ssowmini } 53001bd6825cSml err = nxge_dld_get_ip_opt(nxgep, 53011bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv4_udp]); 53021bd6825cSml 53034045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 53041bd6825cSml (int)param_arr[param_class_opt_ipv4_udp].value); 53051bd6825cSml 53061bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 53071bd6825cSml "==> nxge_get_priv_prop: %s", valstr)); 53081bd6825cSml goto done; 53091bd6825cSml } 53101bd6825cSml if (strcmp(pr_name, "_class_opt_ipv4_ah") == 0) { 53114045d941Ssowmini if (is_default) { 53124045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 53134045d941Ssowmini NXGE_CLASS_FLOW_GEN_SERVER); 53144045d941Ssowmini err = 0; 53154045d941Ssowmini goto done; 53164045d941Ssowmini } 53171bd6825cSml err = nxge_dld_get_ip_opt(nxgep, 53181bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv4_ah]); 53191bd6825cSml 53204045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 53211bd6825cSml (int)param_arr[param_class_opt_ipv4_ah].value); 53221bd6825cSml 53231bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 53241bd6825cSml "==> nxge_get_priv_prop: %s", valstr)); 53251bd6825cSml goto done; 53261bd6825cSml } 53271bd6825cSml 53281bd6825cSml if (strcmp(pr_name, "_class_opt_ipv4_sctp") == 0) { 53294045d941Ssowmini if (is_default) { 53304045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 53314045d941Ssowmini NXGE_CLASS_FLOW_GEN_SERVER); 53324045d941Ssowmini err = 0; 53334045d941Ssowmini goto done; 53344045d941Ssowmini } 53351bd6825cSml err = nxge_dld_get_ip_opt(nxgep, 53361bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv4_sctp]); 53371bd6825cSml 53384045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 53391bd6825cSml (int)param_arr[param_class_opt_ipv4_sctp].value); 53401bd6825cSml 53411bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 53421bd6825cSml "==> nxge_get_priv_prop: %s", valstr)); 53431bd6825cSml goto done; 53441bd6825cSml } 53451bd6825cSml 53461bd6825cSml if (strcmp(pr_name, "_class_opt_ipv6_tcp") == 0) { 53474045d941Ssowmini if (is_default) { 53484045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 53494045d941Ssowmini NXGE_CLASS_FLOW_GEN_SERVER); 53504045d941Ssowmini err = 0; 53514045d941Ssowmini goto done; 53524045d941Ssowmini } 53531bd6825cSml err = nxge_dld_get_ip_opt(nxgep, 53541bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv6_tcp]); 53551bd6825cSml 53564045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 53571bd6825cSml (int)param_arr[param_class_opt_ipv6_tcp].value); 53581bd6825cSml 53591bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 53601bd6825cSml "==> nxge_get_priv_prop: %s", valstr)); 53611bd6825cSml goto done; 53621bd6825cSml } 53631bd6825cSml 53641bd6825cSml if (strcmp(pr_name, "_class_opt_ipv6_udp") == 0) { 53654045d941Ssowmini if (is_default) { 53664045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 53674045d941Ssowmini NXGE_CLASS_FLOW_GEN_SERVER); 53684045d941Ssowmini err = 0; 53694045d941Ssowmini goto done; 53704045d941Ssowmini } 53711bd6825cSml err = nxge_dld_get_ip_opt(nxgep, 53721bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv6_udp]); 53731bd6825cSml 53744045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 53751bd6825cSml (int)param_arr[param_class_opt_ipv6_udp].value); 53761bd6825cSml 53771bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 53781bd6825cSml "==> nxge_get_priv_prop: %s", valstr)); 53791bd6825cSml goto done; 53801bd6825cSml } 53811bd6825cSml 53821bd6825cSml if (strcmp(pr_name, "_class_opt_ipv6_ah") == 0) { 53834045d941Ssowmini if (is_default) { 53844045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 53854045d941Ssowmini NXGE_CLASS_FLOW_GEN_SERVER); 53864045d941Ssowmini err = 0; 53874045d941Ssowmini goto done; 53884045d941Ssowmini } 53891bd6825cSml err = nxge_dld_get_ip_opt(nxgep, 53901bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv6_ah]); 53911bd6825cSml 53924045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 53931bd6825cSml (int)param_arr[param_class_opt_ipv6_ah].value); 53941bd6825cSml 53951bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 53961bd6825cSml "==> nxge_get_priv_prop: %s", valstr)); 53971bd6825cSml goto done; 53981bd6825cSml } 53991bd6825cSml 54001bd6825cSml if (strcmp(pr_name, "_class_opt_ipv6_sctp") == 0) { 54014045d941Ssowmini if (is_default) { 54024045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 54034045d941Ssowmini NXGE_CLASS_FLOW_GEN_SERVER); 54044045d941Ssowmini err = 0; 54054045d941Ssowmini goto done; 54064045d941Ssowmini } 54071bd6825cSml err = nxge_dld_get_ip_opt(nxgep, 54081bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv6_sctp]); 54091bd6825cSml 54104045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 54111bd6825cSml (int)param_arr[param_class_opt_ipv6_sctp].value); 54121bd6825cSml 54131bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 54141bd6825cSml "==> nxge_get_priv_prop: %s", valstr)); 54151bd6825cSml goto done; 54161bd6825cSml } 54171bd6825cSml 54181bd6825cSml /* Software LSO */ 54191bd6825cSml if (strcmp(pr_name, "_soft_lso_enable") == 0) { 54204045d941Ssowmini if (is_default) { 54214045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%d", 0); 54224045d941Ssowmini err = 0; 54234045d941Ssowmini goto done; 54244045d941Ssowmini } 54254045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), 54264045d941Ssowmini "%d", nxgep->soft_lso_enable); 54271bd6825cSml err = 0; 54281bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 54291bd6825cSml "==> nxge_get_priv_prop: name %s (value %d)", 54301bd6825cSml pr_name, nxgep->soft_lso_enable)); 54311bd6825cSml 54321bd6825cSml goto done; 54331bd6825cSml } 54344045d941Ssowmini if (strcmp(pr_name, "_adv_10gfdx_cap") == 0) { 54354045d941Ssowmini err = 0; 54364045d941Ssowmini if (is_default || 54374045d941Ssowmini nxgep->param_arr[param_anar_10gfdx].value != 0) { 54384045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%d", 1); 54394045d941Ssowmini goto done; 54404045d941Ssowmini } else { 54414045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%d", 0); 54424045d941Ssowmini goto done; 54434045d941Ssowmini } 54444045d941Ssowmini } 54454045d941Ssowmini if (strcmp(pr_name, "_adv_pause_cap") == 0) { 54464045d941Ssowmini err = 0; 54474045d941Ssowmini if (is_default || 54484045d941Ssowmini nxgep->param_arr[param_anar_pause].value != 0) { 54494045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%d", 1); 54504045d941Ssowmini goto done; 54514045d941Ssowmini } else { 54524045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%d", 0); 54534045d941Ssowmini goto done; 54544045d941Ssowmini } 54554045d941Ssowmini } 54561bd6825cSml 54571bd6825cSml done: 54581bd6825cSml if (err == 0) { 54591bd6825cSml strsize = (uint_t)strlen(valstr); 54601bd6825cSml if (pr_valsize < strsize) { 54611bd6825cSml err = ENOBUFS; 54621bd6825cSml } else { 54631bd6825cSml (void) strlcpy(pr_val, valstr, pr_valsize); 54641bd6825cSml } 54651bd6825cSml } 54661bd6825cSml 54671bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 54681bd6825cSml "<== nxge_get_priv_prop: return %d", err)); 54691bd6825cSml return (err); 54701bd6825cSml } 54711bd6825cSml 547244961713Sgirish /* 547344961713Sgirish * Module loading and removing entry points. 547444961713Sgirish */ 547544961713Sgirish 54766f157acbSml DDI_DEFINE_STREAM_OPS(nxge_dev_ops, nulldev, nulldev, nxge_attach, nxge_detach, 547719397407SSherry Moore nodev, NULL, D_MP, NULL, nxge_quiesce); 547844961713Sgirish 54792e59129aSraghus #define NXGE_DESC_VER "Sun NIU 10Gb Ethernet" 548044961713Sgirish 548144961713Sgirish /* 548244961713Sgirish * Module linkage information for the kernel. 548344961713Sgirish */ 548444961713Sgirish static struct modldrv nxge_modldrv = { 548544961713Sgirish &mod_driverops, 548644961713Sgirish NXGE_DESC_VER, 548744961713Sgirish &nxge_dev_ops 548844961713Sgirish }; 548944961713Sgirish 549044961713Sgirish static struct modlinkage modlinkage = { 549144961713Sgirish MODREV_1, (void *) &nxge_modldrv, NULL 549244961713Sgirish }; 549344961713Sgirish 549444961713Sgirish int 549544961713Sgirish _init(void) 549644961713Sgirish { 549744961713Sgirish int status; 549844961713Sgirish 54993b2d9860SMichael Speer MUTEX_INIT(&nxgedebuglock, NULL, MUTEX_DRIVER, NULL); 55003b2d9860SMichael Speer 550144961713Sgirish NXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _init")); 55023b2d9860SMichael Speer 550344961713Sgirish mac_init_ops(&nxge_dev_ops, "nxge"); 55043b2d9860SMichael Speer 550544961713Sgirish status = ddi_soft_state_init(&nxge_list, sizeof (nxge_t), 0); 550644961713Sgirish if (status != 0) { 550744961713Sgirish NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 55084045d941Ssowmini "failed to init device soft state")); 550944961713Sgirish goto _init_exit; 551044961713Sgirish } 55113b2d9860SMichael Speer 551244961713Sgirish status = mod_install(&modlinkage); 551344961713Sgirish if (status != 0) { 551444961713Sgirish ddi_soft_state_fini(&nxge_list); 551544961713Sgirish NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, "Mod install failed")); 551644961713Sgirish goto _init_exit; 551744961713Sgirish } 551844961713Sgirish 551944961713Sgirish MUTEX_INIT(&nxge_common_lock, NULL, MUTEX_DRIVER, NULL); 552044961713Sgirish 55213b2d9860SMichael Speer NXGE_DEBUG_MSG((NULL, MOD_CTL, "<== _init status = 0x%X", status)); 55223b2d9860SMichael Speer return (status); 552344961713Sgirish 55243b2d9860SMichael Speer _init_exit: 55253b2d9860SMichael Speer NXGE_DEBUG_MSG((NULL, MOD_CTL, "<== _init status = 0x%X", status)); 55263b2d9860SMichael Speer MUTEX_DESTROY(&nxgedebuglock); 552744961713Sgirish return (status); 552844961713Sgirish } 552944961713Sgirish 553044961713Sgirish int 553144961713Sgirish _fini(void) 553244961713Sgirish { 553344961713Sgirish int status; 553444961713Sgirish 553544961713Sgirish NXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _fini")); 553644961713Sgirish NXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _fini: mod_remove")); 5537a3c5bd6dSspeer 5538a3c5bd6dSspeer if (nxge_mblks_pending) 5539a3c5bd6dSspeer return (EBUSY); 5540a3c5bd6dSspeer 554144961713Sgirish status = mod_remove(&modlinkage); 554244961713Sgirish if (status != DDI_SUCCESS) { 554344961713Sgirish NXGE_DEBUG_MSG((NULL, MOD_CTL, 55444045d941Ssowmini "Module removal failed 0x%08x", 55454045d941Ssowmini status)); 554644961713Sgirish goto _fini_exit; 554744961713Sgirish } 554844961713Sgirish 554944961713Sgirish mac_fini_ops(&nxge_dev_ops); 555044961713Sgirish 555144961713Sgirish ddi_soft_state_fini(&nxge_list); 555244961713Sgirish 55533b2d9860SMichael Speer NXGE_DEBUG_MSG((NULL, MOD_CTL, "<== _fini status = 0x%08x", status)); 55543b2d9860SMichael Speer 555544961713Sgirish MUTEX_DESTROY(&nxge_common_lock); 55563b2d9860SMichael Speer MUTEX_DESTROY(&nxgedebuglock); 55573b2d9860SMichael Speer return (status); 555844961713Sgirish 55593b2d9860SMichael Speer _fini_exit: 55603b2d9860SMichael Speer NXGE_DEBUG_MSG((NULL, MOD_CTL, "<== _fini status = 0x%08x", status)); 556144961713Sgirish return (status); 556244961713Sgirish } 556344961713Sgirish 556444961713Sgirish int 556544961713Sgirish _info(struct modinfo *modinfop) 556644961713Sgirish { 556744961713Sgirish int status; 556844961713Sgirish 556944961713Sgirish NXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _info")); 557044961713Sgirish status = mod_info(&modlinkage, modinfop); 557144961713Sgirish NXGE_DEBUG_MSG((NULL, MOD_CTL, " _info status = 0x%X", status)); 557244961713Sgirish 557344961713Sgirish return (status); 557444961713Sgirish } 557544961713Sgirish 5576da14cebeSEric Cheng /*ARGSUSED*/ 5577da14cebeSEric Cheng static int 5578da14cebeSEric Cheng nxge_tx_ring_start(mac_ring_driver_t rdriver, uint64_t mr_gen_num) 5579da14cebeSEric Cheng { 5580da14cebeSEric Cheng p_nxge_ring_handle_t rhp = (p_nxge_ring_handle_t)rdriver; 5581da14cebeSEric Cheng p_nxge_t nxgep = rhp->nxgep; 5582da14cebeSEric Cheng uint32_t channel; 5583da14cebeSEric Cheng p_tx_ring_t ring; 5584da14cebeSEric Cheng 5585da14cebeSEric Cheng channel = nxgep->pt_config.hw_config.tdc.start + rhp->index; 5586da14cebeSEric Cheng ring = nxgep->tx_rings->rings[channel]; 5587da14cebeSEric Cheng 5588da14cebeSEric Cheng MUTEX_ENTER(&ring->lock); 5589da14cebeSEric Cheng ring->tx_ring_handle = rhp->ring_handle; 5590da14cebeSEric Cheng MUTEX_EXIT(&ring->lock); 5591da14cebeSEric Cheng 5592da14cebeSEric Cheng return (0); 5593da14cebeSEric Cheng } 5594da14cebeSEric Cheng 5595da14cebeSEric Cheng static void 5596da14cebeSEric Cheng nxge_tx_ring_stop(mac_ring_driver_t rdriver) 5597da14cebeSEric Cheng { 5598da14cebeSEric Cheng p_nxge_ring_handle_t rhp = (p_nxge_ring_handle_t)rdriver; 5599da14cebeSEric Cheng p_nxge_t nxgep = rhp->nxgep; 5600da14cebeSEric Cheng uint32_t channel; 5601da14cebeSEric Cheng p_tx_ring_t ring; 5602da14cebeSEric Cheng 5603da14cebeSEric Cheng channel = nxgep->pt_config.hw_config.tdc.start + rhp->index; 5604da14cebeSEric Cheng ring = nxgep->tx_rings->rings[channel]; 5605da14cebeSEric Cheng 5606da14cebeSEric Cheng MUTEX_ENTER(&ring->lock); 5607da14cebeSEric Cheng ring->tx_ring_handle = (mac_ring_handle_t)NULL; 5608da14cebeSEric Cheng MUTEX_EXIT(&ring->lock); 5609da14cebeSEric Cheng } 5610da14cebeSEric Cheng 5611da14cebeSEric Cheng static int 5612da14cebeSEric Cheng nxge_rx_ring_start(mac_ring_driver_t rdriver, uint64_t mr_gen_num) 5613da14cebeSEric Cheng { 5614da14cebeSEric Cheng p_nxge_ring_handle_t rhp = (p_nxge_ring_handle_t)rdriver; 5615da14cebeSEric Cheng p_nxge_t nxgep = rhp->nxgep; 5616da14cebeSEric Cheng uint32_t channel; 5617da14cebeSEric Cheng p_rx_rcr_ring_t ring; 5618da14cebeSEric Cheng int i; 5619da14cebeSEric Cheng 5620da14cebeSEric Cheng channel = nxgep->pt_config.hw_config.start_rdc + rhp->index; 5621da14cebeSEric Cheng ring = nxgep->rx_rcr_rings->rcr_rings[channel]; 5622da14cebeSEric Cheng 5623da14cebeSEric Cheng MUTEX_ENTER(&ring->lock); 5624da14cebeSEric Cheng 5625da14cebeSEric Cheng if (nxgep->rx_channel_started[channel] == B_TRUE) { 5626da14cebeSEric Cheng MUTEX_EXIT(&ring->lock); 5627da14cebeSEric Cheng return (0); 5628da14cebeSEric Cheng } 5629da14cebeSEric Cheng 5630da14cebeSEric Cheng /* set rcr_ring */ 5631da14cebeSEric Cheng for (i = 0; i < nxgep->ldgvp->maxldvs; i++) { 5632da14cebeSEric Cheng if ((nxgep->ldgvp->ldvp[i].is_rxdma == 1) && 5633da14cebeSEric Cheng (nxgep->ldgvp->ldvp[i].channel == channel)) { 5634da14cebeSEric Cheng ring->ldvp = &nxgep->ldgvp->ldvp[i]; 5635da14cebeSEric Cheng ring->ldgp = nxgep->ldgvp->ldvp[i].ldgp; 5636da14cebeSEric Cheng } 5637da14cebeSEric Cheng } 5638da14cebeSEric Cheng 5639da14cebeSEric Cheng nxgep->rx_channel_started[channel] = B_TRUE; 5640da14cebeSEric Cheng ring->rcr_mac_handle = rhp->ring_handle; 5641da14cebeSEric Cheng ring->rcr_gen_num = mr_gen_num; 5642da14cebeSEric Cheng MUTEX_EXIT(&ring->lock); 5643da14cebeSEric Cheng 5644da14cebeSEric Cheng return (0); 5645da14cebeSEric Cheng } 5646da14cebeSEric Cheng 5647da14cebeSEric Cheng static void 5648da14cebeSEric Cheng nxge_rx_ring_stop(mac_ring_driver_t rdriver) 5649da14cebeSEric Cheng { 5650da14cebeSEric Cheng p_nxge_ring_handle_t rhp = (p_nxge_ring_handle_t)rdriver; 5651da14cebeSEric Cheng p_nxge_t nxgep = rhp->nxgep; 5652da14cebeSEric Cheng uint32_t channel; 5653da14cebeSEric Cheng p_rx_rcr_ring_t ring; 5654da14cebeSEric Cheng 5655da14cebeSEric Cheng channel = nxgep->pt_config.hw_config.start_rdc + rhp->index; 5656da14cebeSEric Cheng ring = nxgep->rx_rcr_rings->rcr_rings[channel]; 5657da14cebeSEric Cheng 5658da14cebeSEric Cheng MUTEX_ENTER(&ring->lock); 5659da14cebeSEric Cheng nxgep->rx_channel_started[channel] = B_FALSE; 5660da14cebeSEric Cheng ring->rcr_mac_handle = NULL; 5661da14cebeSEric Cheng MUTEX_EXIT(&ring->lock); 5662da14cebeSEric Cheng } 5663da14cebeSEric Cheng 5664da14cebeSEric Cheng /* 5665da14cebeSEric Cheng * Callback funtion for MAC layer to register all rings. 5666da14cebeSEric Cheng */ 5667da14cebeSEric Cheng static void 5668da14cebeSEric Cheng nxge_fill_ring(void *arg, mac_ring_type_t rtype, const int rg_index, 5669da14cebeSEric Cheng const int index, mac_ring_info_t *infop, mac_ring_handle_t rh) 5670da14cebeSEric Cheng { 5671da14cebeSEric Cheng p_nxge_t nxgep = (p_nxge_t)arg; 5672da14cebeSEric Cheng p_nxge_hw_pt_cfg_t p_cfgp = &nxgep->pt_config.hw_config; 5673da14cebeSEric Cheng 5674da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, TX_CTL, 5675da14cebeSEric Cheng "==> nxge_fill_ring 0x%x index %d", rtype, index)); 5676da14cebeSEric Cheng 5677da14cebeSEric Cheng switch (rtype) { 5678da14cebeSEric Cheng case MAC_RING_TYPE_TX: { 5679da14cebeSEric Cheng p_nxge_ring_handle_t rhandlep; 5680da14cebeSEric Cheng 5681da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, TX_CTL, 5682da14cebeSEric Cheng "==> nxge_fill_ring (TX) 0x%x index %d ntdcs %d", 5683da14cebeSEric Cheng rtype, index, p_cfgp->tdc.count)); 5684da14cebeSEric Cheng 5685da14cebeSEric Cheng ASSERT((index >= 0) && (index < p_cfgp->tdc.count)); 5686da14cebeSEric Cheng rhandlep = &nxgep->tx_ring_handles[index]; 5687da14cebeSEric Cheng rhandlep->nxgep = nxgep; 5688da14cebeSEric Cheng rhandlep->index = index; 5689da14cebeSEric Cheng rhandlep->ring_handle = rh; 5690da14cebeSEric Cheng 5691da14cebeSEric Cheng infop->mri_driver = (mac_ring_driver_t)rhandlep; 5692da14cebeSEric Cheng infop->mri_start = nxge_tx_ring_start; 5693da14cebeSEric Cheng infop->mri_stop = nxge_tx_ring_stop; 5694da14cebeSEric Cheng infop->mri_tx = nxge_tx_ring_send; 5695da14cebeSEric Cheng 5696da14cebeSEric Cheng break; 5697da14cebeSEric Cheng } 5698da14cebeSEric Cheng case MAC_RING_TYPE_RX: { 5699da14cebeSEric Cheng p_nxge_ring_handle_t rhandlep; 5700da14cebeSEric Cheng int nxge_rindex; 5701da14cebeSEric Cheng mac_intr_t nxge_mac_intr; 5702da14cebeSEric Cheng 5703da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, RX_CTL, 5704da14cebeSEric Cheng "==> nxge_fill_ring (RX) 0x%x index %d nrdcs %d", 5705da14cebeSEric Cheng rtype, index, p_cfgp->max_rdcs)); 5706da14cebeSEric Cheng 5707da14cebeSEric Cheng /* 5708da14cebeSEric Cheng * 'index' is the ring index within the group. 5709da14cebeSEric Cheng * Find the ring index in the nxge instance. 5710da14cebeSEric Cheng */ 5711da14cebeSEric Cheng nxge_rindex = nxge_get_rxring_index(nxgep, rg_index, index); 5712da14cebeSEric Cheng 5713da14cebeSEric Cheng ASSERT((nxge_rindex >= 0) && (nxge_rindex < p_cfgp->max_rdcs)); 5714da14cebeSEric Cheng rhandlep = &nxgep->rx_ring_handles[nxge_rindex]; 5715da14cebeSEric Cheng rhandlep->nxgep = nxgep; 5716da14cebeSEric Cheng rhandlep->index = nxge_rindex; 5717da14cebeSEric Cheng rhandlep->ring_handle = rh; 5718da14cebeSEric Cheng 5719da14cebeSEric Cheng /* 5720da14cebeSEric Cheng * Entrypoint to enable interrupt (disable poll) and 5721da14cebeSEric Cheng * disable interrupt (enable poll). 5722da14cebeSEric Cheng */ 5723da14cebeSEric Cheng nxge_mac_intr.mi_handle = (mac_intr_handle_t)rhandlep; 5724da14cebeSEric Cheng nxge_mac_intr.mi_enable = (mac_intr_enable_t)nxge_disable_poll; 5725da14cebeSEric Cheng nxge_mac_intr.mi_disable = (mac_intr_disable_t)nxge_enable_poll; 5726da14cebeSEric Cheng infop->mri_driver = (mac_ring_driver_t)rhandlep; 5727da14cebeSEric Cheng infop->mri_start = nxge_rx_ring_start; 5728da14cebeSEric Cheng infop->mri_stop = nxge_rx_ring_stop; 5729da14cebeSEric Cheng infop->mri_intr = nxge_mac_intr; /* ??? */ 5730da14cebeSEric Cheng infop->mri_poll = nxge_rx_poll; 5731da14cebeSEric Cheng 5732da14cebeSEric Cheng break; 5733da14cebeSEric Cheng } 5734da14cebeSEric Cheng default: 5735da14cebeSEric Cheng break; 5736da14cebeSEric Cheng } 5737da14cebeSEric Cheng 5738da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_fill_ring 0x%x", 5739da14cebeSEric Cheng rtype)); 5740da14cebeSEric Cheng } 5741da14cebeSEric Cheng 5742da14cebeSEric Cheng static void 5743da14cebeSEric Cheng nxge_group_add_ring(mac_group_driver_t gh, mac_ring_driver_t rh, 5744da14cebeSEric Cheng mac_ring_type_t type) 5745da14cebeSEric Cheng { 5746da14cebeSEric Cheng nxge_ring_group_t *rgroup = (nxge_ring_group_t *)gh; 5747da14cebeSEric Cheng nxge_ring_handle_t *rhandle = (nxge_ring_handle_t *)rh; 5748da14cebeSEric Cheng nxge_t *nxge; 5749da14cebeSEric Cheng nxge_grp_t *grp; 5750da14cebeSEric Cheng nxge_rdc_grp_t *rdc_grp; 5751da14cebeSEric Cheng uint16_t channel; /* device-wise ring id */ 5752da14cebeSEric Cheng int dev_gindex; 5753da14cebeSEric Cheng int rv; 5754da14cebeSEric Cheng 5755da14cebeSEric Cheng nxge = rgroup->nxgep; 5756da14cebeSEric Cheng 5757da14cebeSEric Cheng switch (type) { 5758da14cebeSEric Cheng case MAC_RING_TYPE_TX: 5759da14cebeSEric Cheng /* 5760da14cebeSEric Cheng * nxge_grp_dc_add takes a channel number which is a 5761da14cebeSEric Cheng * "devise" ring ID. 5762da14cebeSEric Cheng */ 5763da14cebeSEric Cheng channel = nxge->pt_config.hw_config.tdc.start + rhandle->index; 5764da14cebeSEric Cheng 5765da14cebeSEric Cheng /* 5766da14cebeSEric Cheng * Remove the ring from the default group 5767da14cebeSEric Cheng */ 5768da14cebeSEric Cheng if (rgroup->gindex != 0) { 5769da14cebeSEric Cheng (void) nxge_grp_dc_remove(nxge, VP_BOUND_TX, channel); 5770da14cebeSEric Cheng } 5771da14cebeSEric Cheng 5772da14cebeSEric Cheng /* 5773da14cebeSEric Cheng * nxge->tx_set.group[] is an array of groups indexed by 5774da14cebeSEric Cheng * a "port" group ID. 5775da14cebeSEric Cheng */ 5776da14cebeSEric Cheng grp = nxge->tx_set.group[rgroup->gindex]; 5777da14cebeSEric Cheng rv = nxge_grp_dc_add(nxge, grp, VP_BOUND_TX, channel); 5778da14cebeSEric Cheng if (rv != 0) { 5779da14cebeSEric Cheng NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, 5780da14cebeSEric Cheng "nxge_group_add_ring: nxge_grp_dc_add failed")); 5781da14cebeSEric Cheng } 5782da14cebeSEric Cheng break; 5783da14cebeSEric Cheng 5784da14cebeSEric Cheng case MAC_RING_TYPE_RX: 5785da14cebeSEric Cheng /* 5786da14cebeSEric Cheng * nxge->rx_set.group[] is an array of groups indexed by 5787da14cebeSEric Cheng * a "port" group ID. 5788da14cebeSEric Cheng */ 5789da14cebeSEric Cheng grp = nxge->rx_set.group[rgroup->gindex]; 5790da14cebeSEric Cheng 5791da14cebeSEric Cheng dev_gindex = nxge->pt_config.hw_config.def_mac_rxdma_grpid + 5792da14cebeSEric Cheng rgroup->gindex; 5793da14cebeSEric Cheng rdc_grp = &nxge->pt_config.rdc_grps[dev_gindex]; 5794da14cebeSEric Cheng 5795da14cebeSEric Cheng /* 5796da14cebeSEric Cheng * nxge_grp_dc_add takes a channel number which is a 5797da14cebeSEric Cheng * "devise" ring ID. 5798da14cebeSEric Cheng */ 5799da14cebeSEric Cheng channel = nxge->pt_config.hw_config.start_rdc + rhandle->index; 5800da14cebeSEric Cheng rv = nxge_grp_dc_add(nxge, grp, VP_BOUND_RX, channel); 5801da14cebeSEric Cheng if (rv != 0) { 5802da14cebeSEric Cheng NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, 5803da14cebeSEric Cheng "nxge_group_add_ring: nxge_grp_dc_add failed")); 5804da14cebeSEric Cheng } 5805da14cebeSEric Cheng 5806da14cebeSEric Cheng rdc_grp->map |= (1 << channel); 5807da14cebeSEric Cheng rdc_grp->max_rdcs++; 5808da14cebeSEric Cheng 58094ba491f5SMichael Speer (void) nxge_init_fzc_rdc_tbl(nxge, rdc_grp, rgroup->rdctbl); 5810da14cebeSEric Cheng break; 5811da14cebeSEric Cheng } 5812da14cebeSEric Cheng } 5813da14cebeSEric Cheng 5814da14cebeSEric Cheng static void 5815da14cebeSEric Cheng nxge_group_rem_ring(mac_group_driver_t gh, mac_ring_driver_t rh, 5816da14cebeSEric Cheng mac_ring_type_t type) 5817da14cebeSEric Cheng { 5818da14cebeSEric Cheng nxge_ring_group_t *rgroup = (nxge_ring_group_t *)gh; 5819da14cebeSEric Cheng nxge_ring_handle_t *rhandle = (nxge_ring_handle_t *)rh; 5820da14cebeSEric Cheng nxge_t *nxge; 5821da14cebeSEric Cheng uint16_t channel; /* device-wise ring id */ 5822da14cebeSEric Cheng nxge_rdc_grp_t *rdc_grp; 5823da14cebeSEric Cheng int dev_gindex; 5824da14cebeSEric Cheng 5825da14cebeSEric Cheng nxge = rgroup->nxgep; 5826da14cebeSEric Cheng 5827da14cebeSEric Cheng switch (type) { 5828da14cebeSEric Cheng case MAC_RING_TYPE_TX: 5829da14cebeSEric Cheng dev_gindex = nxge->pt_config.hw_config.def_mac_txdma_grpid + 5830da14cebeSEric Cheng rgroup->gindex; 5831da14cebeSEric Cheng channel = nxge->pt_config.hw_config.tdc.start + rhandle->index; 5832da14cebeSEric Cheng nxge_grp_dc_remove(nxge, VP_BOUND_TX, channel); 5833da14cebeSEric Cheng 5834da14cebeSEric Cheng /* 5835da14cebeSEric Cheng * Add the ring back to the default group 5836da14cebeSEric Cheng */ 5837da14cebeSEric Cheng if (rgroup->gindex != 0) { 5838da14cebeSEric Cheng nxge_grp_t *grp; 5839da14cebeSEric Cheng grp = nxge->tx_set.group[0]; 5840da14cebeSEric Cheng (void) nxge_grp_dc_add(nxge, grp, VP_BOUND_TX, channel); 5841da14cebeSEric Cheng } 5842da14cebeSEric Cheng break; 5843da14cebeSEric Cheng 5844da14cebeSEric Cheng case MAC_RING_TYPE_RX: 5845da14cebeSEric Cheng dev_gindex = nxge->pt_config.hw_config.def_mac_rxdma_grpid + 5846da14cebeSEric Cheng rgroup->gindex; 5847da14cebeSEric Cheng rdc_grp = &nxge->pt_config.rdc_grps[dev_gindex]; 5848da14cebeSEric Cheng channel = rdc_grp->start_rdc + rhandle->index; 5849da14cebeSEric Cheng nxge_grp_dc_remove(nxge, VP_BOUND_RX, channel); 5850da14cebeSEric Cheng 5851da14cebeSEric Cheng rdc_grp->map &= ~(1 << channel); 5852da14cebeSEric Cheng rdc_grp->max_rdcs--; 5853da14cebeSEric Cheng 58544ba491f5SMichael Speer (void) nxge_init_fzc_rdc_tbl(nxge, rdc_grp, rgroup->rdctbl); 5855da14cebeSEric Cheng break; 5856da14cebeSEric Cheng } 5857da14cebeSEric Cheng } 5858da14cebeSEric Cheng 5859da14cebeSEric Cheng 586044961713Sgirish /*ARGSUSED*/ 586144961713Sgirish static nxge_status_t 586244961713Sgirish nxge_add_intrs(p_nxge_t nxgep) 586344961713Sgirish { 586444961713Sgirish 586544961713Sgirish int intr_types; 586644961713Sgirish int type = 0; 586744961713Sgirish int ddi_status = DDI_SUCCESS; 586844961713Sgirish nxge_status_t status = NXGE_OK; 586944961713Sgirish 587044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs")); 587144961713Sgirish 587244961713Sgirish nxgep->nxge_intr_type.intr_registered = B_FALSE; 587344961713Sgirish nxgep->nxge_intr_type.intr_enabled = B_FALSE; 587444961713Sgirish nxgep->nxge_intr_type.msi_intx_cnt = 0; 587544961713Sgirish nxgep->nxge_intr_type.intr_added = 0; 587644961713Sgirish nxgep->nxge_intr_type.niu_msi_enable = B_FALSE; 587744961713Sgirish nxgep->nxge_intr_type.intr_type = 0; 587844961713Sgirish 587944961713Sgirish if (nxgep->niu_type == N2_NIU) { 588044961713Sgirish nxgep->nxge_intr_type.niu_msi_enable = B_TRUE; 588144961713Sgirish } else if (nxge_msi_enable) { 588244961713Sgirish nxgep->nxge_intr_type.niu_msi_enable = B_TRUE; 588344961713Sgirish } 588444961713Sgirish 588544961713Sgirish /* Get the supported interrupt types */ 588644961713Sgirish if ((ddi_status = ddi_intr_get_supported_types(nxgep->dip, &intr_types)) 58874045d941Ssowmini != DDI_SUCCESS) { 588844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_add_intrs: " 58894045d941Ssowmini "ddi_intr_get_supported_types failed: status 0x%08x", 58904045d941Ssowmini ddi_status)); 589144961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 589244961713Sgirish } 589344961713Sgirish nxgep->nxge_intr_type.intr_types = intr_types; 589444961713Sgirish 589544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 58964045d941Ssowmini "ddi_intr_get_supported_types: 0x%08x", intr_types)); 589744961713Sgirish 589844961713Sgirish /* 589944961713Sgirish * Solaris MSIX is not supported yet. use MSI for now. 590044961713Sgirish * nxge_msi_enable (1): 590144961713Sgirish * 1 - MSI 2 - MSI-X others - FIXED 590244961713Sgirish */ 590344961713Sgirish switch (nxge_msi_enable) { 590444961713Sgirish default: 590544961713Sgirish type = DDI_INTR_TYPE_FIXED; 590644961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: " 59074045d941Ssowmini "use fixed (intx emulation) type %08x", 59084045d941Ssowmini type)); 590944961713Sgirish break; 591044961713Sgirish 591144961713Sgirish case 2: 591244961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: " 59134045d941Ssowmini "ddi_intr_get_supported_types: 0x%08x", intr_types)); 591444961713Sgirish if (intr_types & DDI_INTR_TYPE_MSIX) { 591544961713Sgirish type = DDI_INTR_TYPE_MSIX; 591644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 59174045d941Ssowmini "ddi_intr_get_supported_types: MSIX 0x%08x", 59184045d941Ssowmini type)); 591944961713Sgirish } else if (intr_types & DDI_INTR_TYPE_MSI) { 592044961713Sgirish type = DDI_INTR_TYPE_MSI; 592144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 59224045d941Ssowmini "ddi_intr_get_supported_types: MSI 0x%08x", 59234045d941Ssowmini type)); 592444961713Sgirish } else if (intr_types & DDI_INTR_TYPE_FIXED) { 592544961713Sgirish type = DDI_INTR_TYPE_FIXED; 592644961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: " 59274045d941Ssowmini "ddi_intr_get_supported_types: MSXED0x%08x", 59284045d941Ssowmini type)); 592944961713Sgirish } 593044961713Sgirish break; 593144961713Sgirish 593244961713Sgirish case 1: 593344961713Sgirish if (intr_types & DDI_INTR_TYPE_MSI) { 593444961713Sgirish type = DDI_INTR_TYPE_MSI; 593544961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: " 59364045d941Ssowmini "ddi_intr_get_supported_types: MSI 0x%08x", 59374045d941Ssowmini type)); 593844961713Sgirish } else if (intr_types & DDI_INTR_TYPE_MSIX) { 593944961713Sgirish type = DDI_INTR_TYPE_MSIX; 594044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 59414045d941Ssowmini "ddi_intr_get_supported_types: MSIX 0x%08x", 59424045d941Ssowmini type)); 594344961713Sgirish } else if (intr_types & DDI_INTR_TYPE_FIXED) { 594444961713Sgirish type = DDI_INTR_TYPE_FIXED; 594544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 59464045d941Ssowmini "ddi_intr_get_supported_types: MSXED0x%08x", 59474045d941Ssowmini type)); 594844961713Sgirish } 594944961713Sgirish } 595044961713Sgirish 595144961713Sgirish nxgep->nxge_intr_type.intr_type = type; 595244961713Sgirish if ((type == DDI_INTR_TYPE_MSIX || type == DDI_INTR_TYPE_MSI || 59534045d941Ssowmini type == DDI_INTR_TYPE_FIXED) && 59544045d941Ssowmini nxgep->nxge_intr_type.niu_msi_enable) { 595544961713Sgirish if ((status = nxge_add_intrs_adv(nxgep)) != DDI_SUCCESS) { 595644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 59574045d941Ssowmini " nxge_add_intrs: " 59584045d941Ssowmini " nxge_add_intrs_adv failed: status 0x%08x", 59594045d941Ssowmini status)); 596044961713Sgirish return (status); 596144961713Sgirish } else { 596244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 59634045d941Ssowmini "interrupts registered : type %d", type)); 596444961713Sgirish nxgep->nxge_intr_type.intr_registered = B_TRUE; 596544961713Sgirish 596644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 59674045d941Ssowmini "\nAdded advanced nxge add_intr_adv " 59684045d941Ssowmini "intr type 0x%x\n", type)); 596944961713Sgirish 597044961713Sgirish return (status); 597144961713Sgirish } 597244961713Sgirish } 597344961713Sgirish 597444961713Sgirish if (!nxgep->nxge_intr_type.intr_registered) { 597544961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "==> nxge_add_intrs: " 59764045d941Ssowmini "failed to register interrupts")); 597744961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 597844961713Sgirish } 597944961713Sgirish 598044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_add_intrs")); 598144961713Sgirish return (status); 598244961713Sgirish } 598344961713Sgirish 598444961713Sgirish static nxge_status_t 598544961713Sgirish nxge_add_intrs_adv(p_nxge_t nxgep) 598644961713Sgirish { 598744961713Sgirish int intr_type; 598844961713Sgirish p_nxge_intr_t intrp; 598944961713Sgirish 599044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs_adv")); 599144961713Sgirish 599244961713Sgirish intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 599344961713Sgirish intr_type = intrp->intr_type; 599444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs_adv: type 0x%x", 59954045d941Ssowmini intr_type)); 599644961713Sgirish 599744961713Sgirish switch (intr_type) { 599844961713Sgirish case DDI_INTR_TYPE_MSI: /* 0x2 */ 599944961713Sgirish case DDI_INTR_TYPE_MSIX: /* 0x4 */ 600044961713Sgirish return (nxge_add_intrs_adv_type(nxgep, intr_type)); 600144961713Sgirish 600244961713Sgirish case DDI_INTR_TYPE_FIXED: /* 0x1 */ 600344961713Sgirish return (nxge_add_intrs_adv_type_fix(nxgep, intr_type)); 600444961713Sgirish 600544961713Sgirish default: 600644961713Sgirish return (NXGE_ERROR); 600744961713Sgirish } 600844961713Sgirish } 600944961713Sgirish 601044961713Sgirish 601144961713Sgirish /*ARGSUSED*/ 601244961713Sgirish static nxge_status_t 601344961713Sgirish nxge_add_intrs_adv_type(p_nxge_t nxgep, uint32_t int_type) 601444961713Sgirish { 601544961713Sgirish dev_info_t *dip = nxgep->dip; 601644961713Sgirish p_nxge_ldg_t ldgp; 601744961713Sgirish p_nxge_intr_t intrp; 601844961713Sgirish uint_t *inthandler; 601944961713Sgirish void *arg1, *arg2; 602044961713Sgirish int behavior; 6021ec090658Sml int nintrs, navail, nrequest; 602244961713Sgirish int nactual, nrequired; 602344961713Sgirish int inum = 0; 602444961713Sgirish int x, y; 602544961713Sgirish int ddi_status = DDI_SUCCESS; 602644961713Sgirish nxge_status_t status = NXGE_OK; 602744961713Sgirish 602844961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs_adv_type")); 602944961713Sgirish intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 603044961713Sgirish intrp->start_inum = 0; 603144961713Sgirish 603244961713Sgirish ddi_status = ddi_intr_get_nintrs(dip, int_type, &nintrs); 603344961713Sgirish if ((ddi_status != DDI_SUCCESS) || (nintrs == 0)) { 603444961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 60354045d941Ssowmini "ddi_intr_get_nintrs() failed, status: 0x%x%, " 60364045d941Ssowmini "nintrs: %d", ddi_status, nintrs)); 603744961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 603844961713Sgirish } 603944961713Sgirish 604044961713Sgirish ddi_status = ddi_intr_get_navail(dip, int_type, &navail); 604144961713Sgirish if ((ddi_status != DDI_SUCCESS) || (navail == 0)) { 604244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 60434045d941Ssowmini "ddi_intr_get_navail() failed, status: 0x%x%, " 60444045d941Ssowmini "nintrs: %d", ddi_status, navail)); 604544961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 604644961713Sgirish } 604744961713Sgirish 604844961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 60494045d941Ssowmini "ddi_intr_get_navail() returned: nintrs %d, navail %d", 60504045d941Ssowmini nintrs, navail)); 605144961713Sgirish 6052ec090658Sml /* PSARC/2007/453 MSI-X interrupt limit override */ 6053ec090658Sml if (int_type == DDI_INTR_TYPE_MSIX) { 6054ec090658Sml nrequest = nxge_create_msi_property(nxgep); 6055ec090658Sml if (nrequest < navail) { 6056ec090658Sml navail = nrequest; 6057ec090658Sml NXGE_DEBUG_MSG((nxgep, INT_CTL, 6058ec090658Sml "nxge_add_intrs_adv_type: nintrs %d " 6059ec090658Sml "navail %d (nrequest %d)", 6060ec090658Sml nintrs, navail, nrequest)); 6061ec090658Sml } 6062ec090658Sml } 6063ec090658Sml 606444961713Sgirish if (int_type == DDI_INTR_TYPE_MSI && !ISP2(navail)) { 606544961713Sgirish /* MSI must be power of 2 */ 606644961713Sgirish if ((navail & 16) == 16) { 606744961713Sgirish navail = 16; 606844961713Sgirish } else if ((navail & 8) == 8) { 606944961713Sgirish navail = 8; 607044961713Sgirish } else if ((navail & 4) == 4) { 607144961713Sgirish navail = 4; 607244961713Sgirish } else if ((navail & 2) == 2) { 607344961713Sgirish navail = 2; 607444961713Sgirish } else { 607544961713Sgirish navail = 1; 607644961713Sgirish } 607744961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 60784045d941Ssowmini "ddi_intr_get_navail(): (msi power of 2) nintrs %d, " 60794045d941Ssowmini "navail %d", nintrs, navail)); 608044961713Sgirish } 608144961713Sgirish 608244961713Sgirish behavior = ((int_type == DDI_INTR_TYPE_FIXED) ? DDI_INTR_ALLOC_STRICT : 60834045d941Ssowmini DDI_INTR_ALLOC_NORMAL); 608444961713Sgirish intrp->intr_size = navail * sizeof (ddi_intr_handle_t); 608544961713Sgirish intrp->htable = kmem_alloc(intrp->intr_size, KM_SLEEP); 608644961713Sgirish ddi_status = ddi_intr_alloc(dip, intrp->htable, int_type, inum, 60874045d941Ssowmini navail, &nactual, behavior); 608844961713Sgirish if (ddi_status != DDI_SUCCESS || nactual == 0) { 608944961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 60904045d941Ssowmini " ddi_intr_alloc() failed: %d", 60914045d941Ssowmini ddi_status)); 609244961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 609344961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 609444961713Sgirish } 609544961713Sgirish 609644961713Sgirish if ((ddi_status = ddi_intr_get_pri(intrp->htable[0], 60974045d941Ssowmini (uint_t *)&intrp->pri)) != DDI_SUCCESS) { 609844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 60994045d941Ssowmini " ddi_intr_get_pri() failed: %d", 61004045d941Ssowmini ddi_status)); 610144961713Sgirish /* Free already allocated interrupts */ 610244961713Sgirish for (y = 0; y < nactual; y++) { 610344961713Sgirish (void) ddi_intr_free(intrp->htable[y]); 610444961713Sgirish } 610544961713Sgirish 610644961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 610744961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 610844961713Sgirish } 610944961713Sgirish 611044961713Sgirish nrequired = 0; 611144961713Sgirish switch (nxgep->niu_type) { 611244961713Sgirish default: 611344961713Sgirish status = nxge_ldgv_init(nxgep, &nactual, &nrequired); 611444961713Sgirish break; 611544961713Sgirish 611644961713Sgirish case N2_NIU: 611744961713Sgirish status = nxge_ldgv_init_n2(nxgep, &nactual, &nrequired); 611844961713Sgirish break; 611944961713Sgirish } 612044961713Sgirish 612144961713Sgirish if (status != NXGE_OK) { 612244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 61234045d941Ssowmini "nxge_add_intrs_adv_typ:nxge_ldgv_init " 61244045d941Ssowmini "failed: 0x%x", status)); 612544961713Sgirish /* Free already allocated interrupts */ 612644961713Sgirish for (y = 0; y < nactual; y++) { 612744961713Sgirish (void) ddi_intr_free(intrp->htable[y]); 612844961713Sgirish } 612944961713Sgirish 613044961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 613144961713Sgirish return (status); 613244961713Sgirish } 613344961713Sgirish 613444961713Sgirish ldgp = nxgep->ldgvp->ldgp; 613544961713Sgirish for (x = 0; x < nrequired; x++, ldgp++) { 613644961713Sgirish ldgp->vector = (uint8_t)x; 613744961713Sgirish ldgp->intdata = SID_DATA(ldgp->func, x); 613844961713Sgirish arg1 = ldgp->ldvp; 613944961713Sgirish arg2 = nxgep; 614044961713Sgirish if (ldgp->nldvs == 1) { 614144961713Sgirish inthandler = (uint_t *)ldgp->ldvp->ldv_intr_handler; 614244961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 61434045d941Ssowmini "nxge_add_intrs_adv_type: " 61444045d941Ssowmini "arg1 0x%x arg2 0x%x: " 61454045d941Ssowmini "1-1 int handler (entry %d intdata 0x%x)\n", 61464045d941Ssowmini arg1, arg2, 61474045d941Ssowmini x, ldgp->intdata)); 614844961713Sgirish } else if (ldgp->nldvs > 1) { 614944961713Sgirish inthandler = (uint_t *)ldgp->sys_intr_handler; 615044961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 61514045d941Ssowmini "nxge_add_intrs_adv_type: " 61524045d941Ssowmini "arg1 0x%x arg2 0x%x: " 61534045d941Ssowmini "nldevs %d int handler " 61544045d941Ssowmini "(entry %d intdata 0x%x)\n", 61554045d941Ssowmini arg1, arg2, 61564045d941Ssowmini ldgp->nldvs, x, ldgp->intdata)); 615744961713Sgirish } 615844961713Sgirish 615944961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 61604045d941Ssowmini "==> nxge_add_intrs_adv_type: ddi_add_intr(inum) #%d " 61614045d941Ssowmini "htable 0x%llx", x, intrp->htable[x])); 616244961713Sgirish 616344961713Sgirish if ((ddi_status = ddi_intr_add_handler(intrp->htable[x], 61644045d941Ssowmini (ddi_intr_handler_t *)inthandler, arg1, arg2)) 61654045d941Ssowmini != DDI_SUCCESS) { 616644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 61674045d941Ssowmini "==> nxge_add_intrs_adv_type: failed #%d " 61684045d941Ssowmini "status 0x%x", x, ddi_status)); 616944961713Sgirish for (y = 0; y < intrp->intr_added; y++) { 617044961713Sgirish (void) ddi_intr_remove_handler( 61714045d941Ssowmini intrp->htable[y]); 617244961713Sgirish } 617344961713Sgirish /* Free already allocated intr */ 617444961713Sgirish for (y = 0; y < nactual; y++) { 617544961713Sgirish (void) ddi_intr_free(intrp->htable[y]); 617644961713Sgirish } 617744961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 617844961713Sgirish 617944961713Sgirish (void) nxge_ldgv_uninit(nxgep); 618044961713Sgirish 618144961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 618244961713Sgirish } 618344961713Sgirish intrp->intr_added++; 618444961713Sgirish } 618544961713Sgirish 618644961713Sgirish intrp->msi_intx_cnt = nactual; 618744961713Sgirish 618844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 61894045d941Ssowmini "Requested: %d, Allowed: %d msi_intx_cnt %d intr_added %d", 61904045d941Ssowmini navail, nactual, 61914045d941Ssowmini intrp->msi_intx_cnt, 61924045d941Ssowmini intrp->intr_added)); 619344961713Sgirish 619444961713Sgirish (void) ddi_intr_get_cap(intrp->htable[0], &intrp->intr_cap); 619544961713Sgirish 619644961713Sgirish (void) nxge_intr_ldgv_init(nxgep); 619744961713Sgirish 619844961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_add_intrs_adv_type")); 619944961713Sgirish 620044961713Sgirish return (status); 620144961713Sgirish } 620244961713Sgirish 620344961713Sgirish /*ARGSUSED*/ 620444961713Sgirish static nxge_status_t 620544961713Sgirish nxge_add_intrs_adv_type_fix(p_nxge_t nxgep, uint32_t int_type) 620644961713Sgirish { 620744961713Sgirish dev_info_t *dip = nxgep->dip; 620844961713Sgirish p_nxge_ldg_t ldgp; 620944961713Sgirish p_nxge_intr_t intrp; 621044961713Sgirish uint_t *inthandler; 621144961713Sgirish void *arg1, *arg2; 621244961713Sgirish int behavior; 621344961713Sgirish int nintrs, navail; 621444961713Sgirish int nactual, nrequired; 621544961713Sgirish int inum = 0; 621644961713Sgirish int x, y; 621744961713Sgirish int ddi_status = DDI_SUCCESS; 621844961713Sgirish nxge_status_t status = NXGE_OK; 621944961713Sgirish 622044961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs_adv_type_fix")); 622144961713Sgirish intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 622244961713Sgirish intrp->start_inum = 0; 622344961713Sgirish 622444961713Sgirish ddi_status = ddi_intr_get_nintrs(dip, int_type, &nintrs); 622544961713Sgirish if ((ddi_status != DDI_SUCCESS) || (nintrs == 0)) { 622644961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 62274045d941Ssowmini "ddi_intr_get_nintrs() failed, status: 0x%x%, " 62284045d941Ssowmini "nintrs: %d", status, nintrs)); 622944961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 623044961713Sgirish } 623144961713Sgirish 623244961713Sgirish ddi_status = ddi_intr_get_navail(dip, int_type, &navail); 623344961713Sgirish if ((ddi_status != DDI_SUCCESS) || (navail == 0)) { 623444961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 62354045d941Ssowmini "ddi_intr_get_navail() failed, status: 0x%x%, " 62364045d941Ssowmini "nintrs: %d", ddi_status, navail)); 623744961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 623844961713Sgirish } 623944961713Sgirish 624044961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 62414045d941Ssowmini "ddi_intr_get_navail() returned: nintrs %d, naavail %d", 62424045d941Ssowmini nintrs, navail)); 624344961713Sgirish 624444961713Sgirish behavior = ((int_type == DDI_INTR_TYPE_FIXED) ? DDI_INTR_ALLOC_STRICT : 62454045d941Ssowmini DDI_INTR_ALLOC_NORMAL); 624644961713Sgirish intrp->intr_size = navail * sizeof (ddi_intr_handle_t); 624744961713Sgirish intrp->htable = kmem_alloc(intrp->intr_size, KM_SLEEP); 624844961713Sgirish ddi_status = ddi_intr_alloc(dip, intrp->htable, int_type, inum, 62494045d941Ssowmini navail, &nactual, behavior); 625044961713Sgirish if (ddi_status != DDI_SUCCESS || nactual == 0) { 625144961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 62524045d941Ssowmini " ddi_intr_alloc() failed: %d", 62534045d941Ssowmini ddi_status)); 625444961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 625544961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 625644961713Sgirish } 625744961713Sgirish 625844961713Sgirish if ((ddi_status = ddi_intr_get_pri(intrp->htable[0], 62594045d941Ssowmini (uint_t *)&intrp->pri)) != DDI_SUCCESS) { 626044961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 62614045d941Ssowmini " ddi_intr_get_pri() failed: %d", 62624045d941Ssowmini ddi_status)); 626344961713Sgirish /* Free already allocated interrupts */ 626444961713Sgirish for (y = 0; y < nactual; y++) { 626544961713Sgirish (void) ddi_intr_free(intrp->htable[y]); 626644961713Sgirish } 626744961713Sgirish 626844961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 626944961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 627044961713Sgirish } 627144961713Sgirish 627244961713Sgirish nrequired = 0; 627344961713Sgirish switch (nxgep->niu_type) { 627444961713Sgirish default: 627544961713Sgirish status = nxge_ldgv_init(nxgep, &nactual, &nrequired); 627644961713Sgirish break; 627744961713Sgirish 627844961713Sgirish case N2_NIU: 627944961713Sgirish status = nxge_ldgv_init_n2(nxgep, &nactual, &nrequired); 628044961713Sgirish break; 628144961713Sgirish } 628244961713Sgirish 628344961713Sgirish if (status != NXGE_OK) { 628444961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 62854045d941Ssowmini "nxge_add_intrs_adv_type_fix:nxge_ldgv_init " 62864045d941Ssowmini "failed: 0x%x", status)); 628744961713Sgirish /* Free already allocated interrupts */ 628844961713Sgirish for (y = 0; y < nactual; y++) { 628944961713Sgirish (void) ddi_intr_free(intrp->htable[y]); 629044961713Sgirish } 629144961713Sgirish 629244961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 629344961713Sgirish return (status); 629444961713Sgirish } 629544961713Sgirish 629644961713Sgirish ldgp = nxgep->ldgvp->ldgp; 629744961713Sgirish for (x = 0; x < nrequired; x++, ldgp++) { 629844961713Sgirish ldgp->vector = (uint8_t)x; 629944961713Sgirish if (nxgep->niu_type != N2_NIU) { 630044961713Sgirish ldgp->intdata = SID_DATA(ldgp->func, x); 630144961713Sgirish } 630244961713Sgirish 630344961713Sgirish arg1 = ldgp->ldvp; 630444961713Sgirish arg2 = nxgep; 630544961713Sgirish if (ldgp->nldvs == 1) { 630644961713Sgirish inthandler = (uint_t *)ldgp->ldvp->ldv_intr_handler; 630744961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 63084045d941Ssowmini "nxge_add_intrs_adv_type_fix: " 63094045d941Ssowmini "1-1 int handler(%d) ldg %d ldv %d " 63104045d941Ssowmini "arg1 $%p arg2 $%p\n", 63114045d941Ssowmini x, ldgp->ldg, ldgp->ldvp->ldv, 63124045d941Ssowmini arg1, arg2)); 631344961713Sgirish } else if (ldgp->nldvs > 1) { 631444961713Sgirish inthandler = (uint_t *)ldgp->sys_intr_handler; 631544961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 63164045d941Ssowmini "nxge_add_intrs_adv_type_fix: " 63174045d941Ssowmini "shared ldv %d int handler(%d) ldv %d ldg %d" 63184045d941Ssowmini "arg1 0x%016llx arg2 0x%016llx\n", 63194045d941Ssowmini x, ldgp->nldvs, ldgp->ldg, ldgp->ldvp->ldv, 63204045d941Ssowmini arg1, arg2)); 632144961713Sgirish } 632244961713Sgirish 632344961713Sgirish if ((ddi_status = ddi_intr_add_handler(intrp->htable[x], 63244045d941Ssowmini (ddi_intr_handler_t *)inthandler, arg1, arg2)) 63254045d941Ssowmini != DDI_SUCCESS) { 632644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 63274045d941Ssowmini "==> nxge_add_intrs_adv_type_fix: failed #%d " 63284045d941Ssowmini "status 0x%x", x, ddi_status)); 632944961713Sgirish for (y = 0; y < intrp->intr_added; y++) { 633044961713Sgirish (void) ddi_intr_remove_handler( 63314045d941Ssowmini intrp->htable[y]); 633244961713Sgirish } 633344961713Sgirish for (y = 0; y < nactual; y++) { 633444961713Sgirish (void) ddi_intr_free(intrp->htable[y]); 633544961713Sgirish } 633644961713Sgirish /* Free already allocated intr */ 633744961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 633844961713Sgirish 633944961713Sgirish (void) nxge_ldgv_uninit(nxgep); 634044961713Sgirish 634144961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 634244961713Sgirish } 634344961713Sgirish intrp->intr_added++; 634444961713Sgirish } 634544961713Sgirish 634644961713Sgirish intrp->msi_intx_cnt = nactual; 634744961713Sgirish 634844961713Sgirish (void) ddi_intr_get_cap(intrp->htable[0], &intrp->intr_cap); 634944961713Sgirish 635044961713Sgirish status = nxge_intr_ldgv_init(nxgep); 635144961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_add_intrs_adv_type_fix")); 635244961713Sgirish 635344961713Sgirish return (status); 635444961713Sgirish } 635544961713Sgirish 635644961713Sgirish static void 635744961713Sgirish nxge_remove_intrs(p_nxge_t nxgep) 635844961713Sgirish { 635944961713Sgirish int i, inum; 636044961713Sgirish p_nxge_intr_t intrp; 636144961713Sgirish 636244961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_remove_intrs")); 636344961713Sgirish intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 636444961713Sgirish if (!intrp->intr_registered) { 636544961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 63664045d941Ssowmini "<== nxge_remove_intrs: interrupts not registered")); 636744961713Sgirish return; 636844961713Sgirish } 636944961713Sgirish 637044961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_remove_intrs:advanced")); 637144961713Sgirish 637244961713Sgirish if (intrp->intr_cap & DDI_INTR_FLAG_BLOCK) { 637344961713Sgirish (void) ddi_intr_block_disable(intrp->htable, 63744045d941Ssowmini intrp->intr_added); 637544961713Sgirish } else { 637644961713Sgirish for (i = 0; i < intrp->intr_added; i++) { 637744961713Sgirish (void) ddi_intr_disable(intrp->htable[i]); 637844961713Sgirish } 637944961713Sgirish } 638044961713Sgirish 638144961713Sgirish for (inum = 0; inum < intrp->intr_added; inum++) { 638244961713Sgirish if (intrp->htable[inum]) { 638344961713Sgirish (void) ddi_intr_remove_handler(intrp->htable[inum]); 638444961713Sgirish } 638544961713Sgirish } 638644961713Sgirish 638744961713Sgirish for (inum = 0; inum < intrp->msi_intx_cnt; inum++) { 638844961713Sgirish if (intrp->htable[inum]) { 638944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 63904045d941Ssowmini "nxge_remove_intrs: ddi_intr_free inum %d " 63914045d941Ssowmini "msi_intx_cnt %d intr_added %d", 63924045d941Ssowmini inum, 63934045d941Ssowmini intrp->msi_intx_cnt, 63944045d941Ssowmini intrp->intr_added)); 639544961713Sgirish 639644961713Sgirish (void) ddi_intr_free(intrp->htable[inum]); 639744961713Sgirish } 639844961713Sgirish } 639944961713Sgirish 640044961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 640144961713Sgirish intrp->intr_registered = B_FALSE; 640244961713Sgirish intrp->intr_enabled = B_FALSE; 640344961713Sgirish intrp->msi_intx_cnt = 0; 640444961713Sgirish intrp->intr_added = 0; 640544961713Sgirish 6406a3c5bd6dSspeer (void) nxge_ldgv_uninit(nxgep); 6407a3c5bd6dSspeer 6408ec090658Sml (void) ddi_prop_remove(DDI_DEV_T_NONE, nxgep->dip, 6409ec090658Sml "#msix-request"); 6410ec090658Sml 641144961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_remove_intrs")); 641244961713Sgirish } 641344961713Sgirish 641444961713Sgirish /*ARGSUSED*/ 641544961713Sgirish static void 641644961713Sgirish nxge_intrs_enable(p_nxge_t nxgep) 641744961713Sgirish { 641844961713Sgirish p_nxge_intr_t intrp; 641944961713Sgirish int i; 642044961713Sgirish int status; 642144961713Sgirish 642244961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_enable")); 642344961713Sgirish 642444961713Sgirish intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 642544961713Sgirish 642644961713Sgirish if (!intrp->intr_registered) { 642744961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_intrs_enable: " 64284045d941Ssowmini "interrupts are not registered")); 642944961713Sgirish return; 643044961713Sgirish } 643144961713Sgirish 643244961713Sgirish if (intrp->intr_enabled) { 643344961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 64344045d941Ssowmini "<== nxge_intrs_enable: already enabled")); 643544961713Sgirish return; 643644961713Sgirish } 643744961713Sgirish 643844961713Sgirish if (intrp->intr_cap & DDI_INTR_FLAG_BLOCK) { 643944961713Sgirish status = ddi_intr_block_enable(intrp->htable, 64404045d941Ssowmini intrp->intr_added); 644144961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_enable " 64424045d941Ssowmini "block enable - status 0x%x total inums #%d\n", 64434045d941Ssowmini status, intrp->intr_added)); 644444961713Sgirish } else { 644544961713Sgirish for (i = 0; i < intrp->intr_added; i++) { 644644961713Sgirish status = ddi_intr_enable(intrp->htable[i]); 644744961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_enable " 64484045d941Ssowmini "ddi_intr_enable:enable - status 0x%x " 64494045d941Ssowmini "total inums %d enable inum #%d\n", 64504045d941Ssowmini status, intrp->intr_added, i)); 645144961713Sgirish if (status == DDI_SUCCESS) { 645244961713Sgirish intrp->intr_enabled = B_TRUE; 645344961713Sgirish } 645444961713Sgirish } 645544961713Sgirish } 645644961713Sgirish 645744961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intrs_enable")); 645844961713Sgirish } 645944961713Sgirish 646044961713Sgirish /*ARGSUSED*/ 646144961713Sgirish static void 646244961713Sgirish nxge_intrs_disable(p_nxge_t nxgep) 646344961713Sgirish { 646444961713Sgirish p_nxge_intr_t intrp; 646544961713Sgirish int i; 646644961713Sgirish 646744961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_disable")); 646844961713Sgirish 646944961713Sgirish intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 647044961713Sgirish 647144961713Sgirish if (!intrp->intr_registered) { 647244961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intrs_disable: " 64734045d941Ssowmini "interrupts are not registered")); 647444961713Sgirish return; 647544961713Sgirish } 647644961713Sgirish 647744961713Sgirish if (intrp->intr_cap & DDI_INTR_FLAG_BLOCK) { 647844961713Sgirish (void) ddi_intr_block_disable(intrp->htable, 64794045d941Ssowmini intrp->intr_added); 648044961713Sgirish } else { 648144961713Sgirish for (i = 0; i < intrp->intr_added; i++) { 648244961713Sgirish (void) ddi_intr_disable(intrp->htable[i]); 648344961713Sgirish } 648444961713Sgirish } 648544961713Sgirish 648644961713Sgirish intrp->intr_enabled = B_FALSE; 648744961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intrs_disable")); 648844961713Sgirish } 648944961713Sgirish 649063f531d1SSriharsha Basavapatna nxge_status_t 649144961713Sgirish nxge_mac_register(p_nxge_t nxgep) 649244961713Sgirish { 649344961713Sgirish mac_register_t *macp; 649444961713Sgirish int status; 649544961713Sgirish 649644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_mac_register")); 649744961713Sgirish 649844961713Sgirish if ((macp = mac_alloc(MAC_VERSION)) == NULL) 649944961713Sgirish return (NXGE_ERROR); 650044961713Sgirish 650144961713Sgirish macp->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 650244961713Sgirish macp->m_driver = nxgep; 650344961713Sgirish macp->m_dip = nxgep->dip; 650463f531d1SSriharsha Basavapatna if (!isLDOMguest(nxgep)) { 650563f531d1SSriharsha Basavapatna macp->m_src_addr = nxgep->ouraddr.ether_addr_octet; 650663f531d1SSriharsha Basavapatna } else { 650763f531d1SSriharsha Basavapatna macp->m_src_addr = KMEM_ZALLOC(MAXMACADDRLEN, KM_SLEEP); 650863f531d1SSriharsha Basavapatna macp->m_dst_addr = KMEM_ZALLOC(MAXMACADDRLEN, KM_SLEEP); 650963f531d1SSriharsha Basavapatna (void) memset(macp->m_src_addr, 0xff, sizeof (MAXMACADDRLEN)); 651063f531d1SSriharsha Basavapatna } 651144961713Sgirish macp->m_callbacks = &nxge_m_callbacks; 651244961713Sgirish macp->m_min_sdu = 0; 65131bd6825cSml nxgep->mac.default_mtu = nxgep->mac.maxframesize - 65141bd6825cSml NXGE_EHEADER_VLAN_CRC; 65151bd6825cSml macp->m_max_sdu = nxgep->mac.default_mtu; 6516d62bc4baSyz macp->m_margin = VLAN_TAGSZ; 65174045d941Ssowmini macp->m_priv_props = nxge_priv_props; 65184045d941Ssowmini macp->m_priv_prop_count = NXGE_MAX_PRIV_PROPS; 651963f531d1SSriharsha Basavapatna if (isLDOMguest(nxgep)) { 652063f531d1SSriharsha Basavapatna macp->m_v12n = MAC_VIRT_LEVEL1 | MAC_VIRT_SERIALIZE; 652163f531d1SSriharsha Basavapatna } else { 652263f531d1SSriharsha Basavapatna macp->m_v12n = MAC_VIRT_HIO | MAC_VIRT_LEVEL1 | \ 652363f531d1SSriharsha Basavapatna MAC_VIRT_SERIALIZE; 652463f531d1SSriharsha Basavapatna } 652544961713Sgirish 65261bd6825cSml NXGE_DEBUG_MSG((nxgep, MAC_CTL, 65271bd6825cSml "==> nxge_mac_register: instance %d " 65281bd6825cSml "max_sdu %d margin %d maxframe %d (header %d)", 65291bd6825cSml nxgep->instance, 65301bd6825cSml macp->m_max_sdu, macp->m_margin, 65311bd6825cSml nxgep->mac.maxframesize, 65321bd6825cSml NXGE_EHEADER_VLAN_CRC)); 65331bd6825cSml 653444961713Sgirish status = mac_register(macp, &nxgep->mach); 653563f531d1SSriharsha Basavapatna if (isLDOMguest(nxgep)) { 653663f531d1SSriharsha Basavapatna KMEM_FREE(macp->m_src_addr, MAXMACADDRLEN); 653763f531d1SSriharsha Basavapatna KMEM_FREE(macp->m_dst_addr, MAXMACADDRLEN); 653863f531d1SSriharsha Basavapatna } 653944961713Sgirish mac_free(macp); 654044961713Sgirish 654144961713Sgirish if (status != 0) { 654244961713Sgirish cmn_err(CE_WARN, 65434045d941Ssowmini "!nxge_mac_register failed (status %d instance %d)", 65444045d941Ssowmini status, nxgep->instance); 654544961713Sgirish return (NXGE_ERROR); 654644961713Sgirish } 654744961713Sgirish 654844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_mac_register success " 65494045d941Ssowmini "(instance %d)", nxgep->instance)); 655044961713Sgirish 655144961713Sgirish return (NXGE_OK); 655244961713Sgirish } 655344961713Sgirish 655444961713Sgirish void 655544961713Sgirish nxge_err_inject(p_nxge_t nxgep, queue_t *wq, mblk_t *mp) 655644961713Sgirish { 655744961713Sgirish ssize_t size; 655844961713Sgirish mblk_t *nmp; 655944961713Sgirish uint8_t blk_id; 656044961713Sgirish uint8_t chan; 656144961713Sgirish uint32_t err_id; 656244961713Sgirish err_inject_t *eip; 656344961713Sgirish 656444961713Sgirish NXGE_DEBUG_MSG((nxgep, STR_CTL, "==> nxge_err_inject")); 656544961713Sgirish 656644961713Sgirish size = 1024; 656744961713Sgirish nmp = mp->b_cont; 656844961713Sgirish eip = (err_inject_t *)nmp->b_rptr; 656944961713Sgirish blk_id = eip->blk_id; 657044961713Sgirish err_id = eip->err_id; 657144961713Sgirish chan = eip->chan; 657244961713Sgirish cmn_err(CE_NOTE, "!blk_id = 0x%x\n", blk_id); 657344961713Sgirish cmn_err(CE_NOTE, "!err_id = 0x%x\n", err_id); 657444961713Sgirish cmn_err(CE_NOTE, "!chan = 0x%x\n", chan); 657544961713Sgirish switch (blk_id) { 657644961713Sgirish case MAC_BLK_ID: 657744961713Sgirish break; 657844961713Sgirish case TXMAC_BLK_ID: 657944961713Sgirish break; 658044961713Sgirish case RXMAC_BLK_ID: 658144961713Sgirish break; 658244961713Sgirish case MIF_BLK_ID: 658344961713Sgirish break; 658444961713Sgirish case IPP_BLK_ID: 658544961713Sgirish nxge_ipp_inject_err(nxgep, err_id); 658644961713Sgirish break; 658744961713Sgirish case TXC_BLK_ID: 658844961713Sgirish nxge_txc_inject_err(nxgep, err_id); 658944961713Sgirish break; 659044961713Sgirish case TXDMA_BLK_ID: 659144961713Sgirish nxge_txdma_inject_err(nxgep, err_id, chan); 659244961713Sgirish break; 659344961713Sgirish case RXDMA_BLK_ID: 659444961713Sgirish nxge_rxdma_inject_err(nxgep, err_id, chan); 659544961713Sgirish break; 659644961713Sgirish case ZCP_BLK_ID: 659744961713Sgirish nxge_zcp_inject_err(nxgep, err_id); 659844961713Sgirish break; 659944961713Sgirish case ESPC_BLK_ID: 660044961713Sgirish break; 660144961713Sgirish case FFLP_BLK_ID: 660244961713Sgirish break; 660344961713Sgirish case PHY_BLK_ID: 660444961713Sgirish break; 660544961713Sgirish case ETHER_SERDES_BLK_ID: 660644961713Sgirish break; 660744961713Sgirish case PCIE_SERDES_BLK_ID: 660844961713Sgirish break; 660944961713Sgirish case VIR_BLK_ID: 661044961713Sgirish break; 661144961713Sgirish } 661244961713Sgirish 661344961713Sgirish nmp->b_wptr = nmp->b_rptr + size; 661444961713Sgirish NXGE_DEBUG_MSG((nxgep, STR_CTL, "<== nxge_err_inject")); 661544961713Sgirish 661644961713Sgirish miocack(wq, mp, (int)size, 0); 661744961713Sgirish } 661844961713Sgirish 661944961713Sgirish static int 662044961713Sgirish nxge_init_common_dev(p_nxge_t nxgep) 662144961713Sgirish { 662244961713Sgirish p_nxge_hw_list_t hw_p; 662344961713Sgirish dev_info_t *p_dip; 662444961713Sgirish 6625ef523517SMichael Speer ASSERT(nxgep != NULL); 6626ef523517SMichael Speer 662744961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, "==> nxge_init_common_device")); 662844961713Sgirish 662944961713Sgirish p_dip = nxgep->p_dip; 663044961713Sgirish MUTEX_ENTER(&nxge_common_lock); 663144961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 66324045d941Ssowmini "==> nxge_init_common_dev:func # %d", 66334045d941Ssowmini nxgep->function_num)); 663444961713Sgirish /* 663544961713Sgirish * Loop through existing per neptune hardware list. 663644961713Sgirish */ 663744961713Sgirish for (hw_p = nxge_hw_list; hw_p; hw_p = hw_p->next) { 663844961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 66394045d941Ssowmini "==> nxge_init_common_device:func # %d " 66404045d941Ssowmini "hw_p $%p parent dip $%p", 66414045d941Ssowmini nxgep->function_num, 66424045d941Ssowmini hw_p, 66434045d941Ssowmini p_dip)); 664444961713Sgirish if (hw_p->parent_devp == p_dip) { 664544961713Sgirish nxgep->nxge_hw_p = hw_p; 664644961713Sgirish hw_p->ndevs++; 664744961713Sgirish hw_p->nxge_p[nxgep->function_num] = nxgep; 664844961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 66494045d941Ssowmini "==> nxge_init_common_device:func # %d " 66504045d941Ssowmini "hw_p $%p parent dip $%p " 66514045d941Ssowmini "ndevs %d (found)", 66524045d941Ssowmini nxgep->function_num, 66534045d941Ssowmini hw_p, 66544045d941Ssowmini p_dip, 66554045d941Ssowmini hw_p->ndevs)); 665644961713Sgirish break; 665744961713Sgirish } 665844961713Sgirish } 665944961713Sgirish 666044961713Sgirish if (hw_p == NULL) { 666123b952a3SSantwona Behera 666223b952a3SSantwona Behera char **prop_val; 666323b952a3SSantwona Behera uint_t prop_len; 666423b952a3SSantwona Behera int i; 666523b952a3SSantwona Behera 666644961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 66674045d941Ssowmini "==> nxge_init_common_device:func # %d " 66684045d941Ssowmini "parent dip $%p (new)", 66694045d941Ssowmini nxgep->function_num, 66704045d941Ssowmini p_dip)); 667144961713Sgirish hw_p = kmem_zalloc(sizeof (nxge_hw_list_t), KM_SLEEP); 667244961713Sgirish hw_p->parent_devp = p_dip; 667344961713Sgirish hw_p->magic = NXGE_NEPTUNE_MAGIC; 667444961713Sgirish nxgep->nxge_hw_p = hw_p; 667544961713Sgirish hw_p->ndevs++; 667644961713Sgirish hw_p->nxge_p[nxgep->function_num] = nxgep; 667744961713Sgirish hw_p->next = nxge_hw_list; 667859ac0c16Sdavemq if (nxgep->niu_type == N2_NIU) { 667959ac0c16Sdavemq hw_p->niu_type = N2_NIU; 668059ac0c16Sdavemq hw_p->platform_type = P_NEPTUNE_NIU; 6681*4df55fdeSJanie Lu hw_p->tcam_size = TCAM_NIU_TCAM_MAX_ENTRY; 668259ac0c16Sdavemq } else { 668359ac0c16Sdavemq hw_p->niu_type = NIU_TYPE_NONE; 66842e59129aSraghus hw_p->platform_type = P_NEPTUNE_NONE; 6685*4df55fdeSJanie Lu hw_p->tcam_size = TCAM_NXGE_TCAM_MAX_ENTRY; 668659ac0c16Sdavemq } 668744961713Sgirish 6688*4df55fdeSJanie Lu hw_p->tcam = KMEM_ZALLOC(sizeof (tcam_flow_spec_t) * 6689*4df55fdeSJanie Lu hw_p->tcam_size, KM_SLEEP); 6690*4df55fdeSJanie Lu 669144961713Sgirish MUTEX_INIT(&hw_p->nxge_cfg_lock, NULL, MUTEX_DRIVER, NULL); 669244961713Sgirish MUTEX_INIT(&hw_p->nxge_tcam_lock, NULL, MUTEX_DRIVER, NULL); 669344961713Sgirish MUTEX_INIT(&hw_p->nxge_vlan_lock, NULL, MUTEX_DRIVER, NULL); 669444961713Sgirish MUTEX_INIT(&hw_p->nxge_mdio_lock, NULL, MUTEX_DRIVER, NULL); 669544961713Sgirish 669644961713Sgirish nxge_hw_list = hw_p; 669759ac0c16Sdavemq 669823b952a3SSantwona Behera if (ddi_prop_lookup_string_array(DDI_DEV_T_ANY, nxgep->dip, 0, 669923b952a3SSantwona Behera "compatible", &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 670023b952a3SSantwona Behera for (i = 0; i < prop_len; i++) { 670123b952a3SSantwona Behera if ((strcmp((caddr_t)prop_val[i], 670223b952a3SSantwona Behera NXGE_ROCK_COMPATIBLE) == 0)) { 670323b952a3SSantwona Behera hw_p->platform_type = P_NEPTUNE_ROCK; 670423b952a3SSantwona Behera NXGE_DEBUG_MSG((nxgep, MOD_CTL, 670523b952a3SSantwona Behera "ROCK hw_p->platform_type %d", 670623b952a3SSantwona Behera hw_p->platform_type)); 670723b952a3SSantwona Behera break; 670823b952a3SSantwona Behera } 670923b952a3SSantwona Behera NXGE_DEBUG_MSG((nxgep, MOD_CTL, 671023b952a3SSantwona Behera "nxge_init_common_dev: read compatible" 671123b952a3SSantwona Behera " property[%d] val[%s]", 671223b952a3SSantwona Behera i, (caddr_t)prop_val[i])); 671323b952a3SSantwona Behera } 671423b952a3SSantwona Behera } 671523b952a3SSantwona Behera 671623b952a3SSantwona Behera ddi_prop_free(prop_val); 671723b952a3SSantwona Behera 671859ac0c16Sdavemq (void) nxge_scan_ports_phy(nxgep, nxge_hw_list); 671944961713Sgirish } 672044961713Sgirish 672144961713Sgirish MUTEX_EXIT(&nxge_common_lock); 672259ac0c16Sdavemq 67232e59129aSraghus nxgep->platform_type = hw_p->platform_type; 672423b952a3SSantwona Behera NXGE_DEBUG_MSG((nxgep, MOD_CTL, "nxgep->platform_type %d", 672523b952a3SSantwona Behera nxgep->platform_type)); 672659ac0c16Sdavemq if (nxgep->niu_type != N2_NIU) { 672759ac0c16Sdavemq nxgep->niu_type = hw_p->niu_type; 672859ac0c16Sdavemq } 672959ac0c16Sdavemq 673044961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 67314045d941Ssowmini "==> nxge_init_common_device (nxge_hw_list) $%p", 67324045d941Ssowmini nxge_hw_list)); 673344961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, "<== nxge_init_common_device")); 673444961713Sgirish 673544961713Sgirish return (NXGE_OK); 673644961713Sgirish } 673744961713Sgirish 673844961713Sgirish static void 673944961713Sgirish nxge_uninit_common_dev(p_nxge_t nxgep) 674044961713Sgirish { 674144961713Sgirish p_nxge_hw_list_t hw_p, h_hw_p; 67420b0beae0Sspeer p_nxge_dma_pt_cfg_t p_dma_cfgp; 67430b0beae0Sspeer p_nxge_hw_pt_cfg_t p_cfgp; 674444961713Sgirish dev_info_t *p_dip; 674544961713Sgirish 6746ef523517SMichael Speer ASSERT(nxgep != NULL); 6747ef523517SMichael Speer 674844961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, "==> nxge_uninit_common_device")); 674944961713Sgirish if (nxgep->nxge_hw_p == NULL) { 675044961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 67514045d941Ssowmini "<== nxge_uninit_common_device (no common)")); 675244961713Sgirish return; 675344961713Sgirish } 675444961713Sgirish 675544961713Sgirish MUTEX_ENTER(&nxge_common_lock); 675644961713Sgirish h_hw_p = nxge_hw_list; 675744961713Sgirish for (hw_p = nxge_hw_list; hw_p; hw_p = hw_p->next) { 675844961713Sgirish p_dip = hw_p->parent_devp; 675944961713Sgirish if (nxgep->nxge_hw_p == hw_p && 67604045d941Ssowmini p_dip == nxgep->p_dip && 67614045d941Ssowmini nxgep->nxge_hw_p->magic == NXGE_NEPTUNE_MAGIC && 67624045d941Ssowmini hw_p->magic == NXGE_NEPTUNE_MAGIC) { 676344961713Sgirish 676444961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 67654045d941Ssowmini "==> nxge_uninit_common_device:func # %d " 67664045d941Ssowmini "hw_p $%p parent dip $%p " 67674045d941Ssowmini "ndevs %d (found)", 67684045d941Ssowmini nxgep->function_num, 67694045d941Ssowmini hw_p, 67704045d941Ssowmini p_dip, 67714045d941Ssowmini hw_p->ndevs)); 677244961713Sgirish 67730b0beae0Sspeer /* 67740b0beae0Sspeer * Release the RDC table, a shared resoruce 67750b0beae0Sspeer * of the nxge hardware. The RDC table was 67760b0beae0Sspeer * assigned to this instance of nxge in 67770b0beae0Sspeer * nxge_use_cfg_dma_config(). 67780b0beae0Sspeer */ 67799d5b8bc5SMichael Speer if (!isLDOMguest(nxgep)) { 67809d5b8bc5SMichael Speer p_dma_cfgp = 67819d5b8bc5SMichael Speer (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 67829d5b8bc5SMichael Speer p_cfgp = 67839d5b8bc5SMichael Speer (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 67849d5b8bc5SMichael Speer (void) nxge_fzc_rdc_tbl_unbind(nxgep, 67859d5b8bc5SMichael Speer p_cfgp->def_mac_rxdma_grpid); 6786651ce697SMichael Speer 6787651ce697SMichael Speer /* Cleanup any outstanding groups. */ 6788651ce697SMichael Speer nxge_grp_cleanup(nxgep); 67899d5b8bc5SMichael Speer } 67900b0beae0Sspeer 679144961713Sgirish if (hw_p->ndevs) { 679244961713Sgirish hw_p->ndevs--; 679344961713Sgirish } 679444961713Sgirish hw_p->nxge_p[nxgep->function_num] = NULL; 679544961713Sgirish if (!hw_p->ndevs) { 6796*4df55fdeSJanie Lu KMEM_FREE(hw_p->tcam, 6797*4df55fdeSJanie Lu sizeof (tcam_flow_spec_t) * 6798*4df55fdeSJanie Lu hw_p->tcam_size); 679944961713Sgirish MUTEX_DESTROY(&hw_p->nxge_vlan_lock); 680044961713Sgirish MUTEX_DESTROY(&hw_p->nxge_tcam_lock); 680144961713Sgirish MUTEX_DESTROY(&hw_p->nxge_cfg_lock); 680244961713Sgirish MUTEX_DESTROY(&hw_p->nxge_mdio_lock); 680344961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 68044045d941Ssowmini "==> nxge_uninit_common_device: " 68054045d941Ssowmini "func # %d " 68064045d941Ssowmini "hw_p $%p parent dip $%p " 68074045d941Ssowmini "ndevs %d (last)", 68084045d941Ssowmini nxgep->function_num, 68094045d941Ssowmini hw_p, 68104045d941Ssowmini p_dip, 68114045d941Ssowmini hw_p->ndevs)); 681244961713Sgirish 6813678453a8Sspeer nxge_hio_uninit(nxgep); 6814678453a8Sspeer 681544961713Sgirish if (hw_p == nxge_hw_list) { 681644961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 68174045d941Ssowmini "==> nxge_uninit_common_device:" 68184045d941Ssowmini "remove head func # %d " 68194045d941Ssowmini "hw_p $%p parent dip $%p " 68204045d941Ssowmini "ndevs %d (head)", 68214045d941Ssowmini nxgep->function_num, 68224045d941Ssowmini hw_p, 68234045d941Ssowmini p_dip, 68244045d941Ssowmini hw_p->ndevs)); 682544961713Sgirish nxge_hw_list = hw_p->next; 682644961713Sgirish } else { 682744961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 68284045d941Ssowmini "==> nxge_uninit_common_device:" 68294045d941Ssowmini "remove middle func # %d " 68304045d941Ssowmini "hw_p $%p parent dip $%p " 68314045d941Ssowmini "ndevs %d (middle)", 68324045d941Ssowmini nxgep->function_num, 68334045d941Ssowmini hw_p, 68344045d941Ssowmini p_dip, 68354045d941Ssowmini hw_p->ndevs)); 683644961713Sgirish h_hw_p->next = hw_p->next; 683744961713Sgirish } 683844961713Sgirish 6839678453a8Sspeer nxgep->nxge_hw_p = NULL; 684044961713Sgirish KMEM_FREE(hw_p, sizeof (nxge_hw_list_t)); 684144961713Sgirish } 684244961713Sgirish break; 684344961713Sgirish } else { 684444961713Sgirish h_hw_p = hw_p; 684544961713Sgirish } 684644961713Sgirish } 684744961713Sgirish 684844961713Sgirish MUTEX_EXIT(&nxge_common_lock); 684944961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 68504045d941Ssowmini "==> nxge_uninit_common_device (nxge_hw_list) $%p", 68514045d941Ssowmini nxge_hw_list)); 685244961713Sgirish 685344961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, "<= nxge_uninit_common_device")); 685444961713Sgirish } 685559ac0c16Sdavemq 685659ac0c16Sdavemq /* 68572e59129aSraghus * Determines the number of ports from the niu_type or the platform type. 685859ac0c16Sdavemq * Returns the number of ports, or returns zero on failure. 685959ac0c16Sdavemq */ 686059ac0c16Sdavemq 686159ac0c16Sdavemq int 68622e59129aSraghus nxge_get_nports(p_nxge_t nxgep) 686359ac0c16Sdavemq { 686459ac0c16Sdavemq int nports = 0; 686559ac0c16Sdavemq 68662e59129aSraghus switch (nxgep->niu_type) { 686759ac0c16Sdavemq case N2_NIU: 686859ac0c16Sdavemq case NEPTUNE_2_10GF: 686959ac0c16Sdavemq nports = 2; 687059ac0c16Sdavemq break; 687159ac0c16Sdavemq case NEPTUNE_4_1GC: 687259ac0c16Sdavemq case NEPTUNE_2_10GF_2_1GC: 687359ac0c16Sdavemq case NEPTUNE_1_10GF_3_1GC: 687459ac0c16Sdavemq case NEPTUNE_1_1GC_1_10GF_2_1GC: 687559a835ddSjoycey case NEPTUNE_2_10GF_2_1GRF: 687659ac0c16Sdavemq nports = 4; 687759ac0c16Sdavemq break; 687859ac0c16Sdavemq default: 68792e59129aSraghus switch (nxgep->platform_type) { 68802e59129aSraghus case P_NEPTUNE_NIU: 68812e59129aSraghus case P_NEPTUNE_ATLAS_2PORT: 68822e59129aSraghus nports = 2; 68832e59129aSraghus break; 68842e59129aSraghus case P_NEPTUNE_ATLAS_4PORT: 68852e59129aSraghus case P_NEPTUNE_MARAMBA_P0: 68862e59129aSraghus case P_NEPTUNE_MARAMBA_P1: 688723b952a3SSantwona Behera case P_NEPTUNE_ROCK: 6888d81011f0Ssbehera case P_NEPTUNE_ALONSO: 68892e59129aSraghus nports = 4; 68902e59129aSraghus break; 68912e59129aSraghus default: 68922e59129aSraghus break; 68932e59129aSraghus } 689459ac0c16Sdavemq break; 689559ac0c16Sdavemq } 689659ac0c16Sdavemq 689759ac0c16Sdavemq return (nports); 689859ac0c16Sdavemq } 6899ec090658Sml 6900ec090658Sml /* 6901ec090658Sml * The following two functions are to support 6902ec090658Sml * PSARC/2007/453 MSI-X interrupt limit override. 6903ec090658Sml */ 6904ec090658Sml static int 6905ec090658Sml nxge_create_msi_property(p_nxge_t nxgep) 6906ec090658Sml { 6907ec090658Sml int nmsi; 6908ec090658Sml extern int ncpus; 6909ec090658Sml 6910ec090658Sml NXGE_DEBUG_MSG((nxgep, MOD_CTL, "==>nxge_create_msi_property")); 6911ec090658Sml 6912ec090658Sml switch (nxgep->mac.portmode) { 6913ec090658Sml case PORT_10G_COPPER: 6914ec090658Sml case PORT_10G_FIBER: 691500161856Syc case PORT_10G_TN1010: 6916ec090658Sml (void) ddi_prop_create(DDI_DEV_T_NONE, nxgep->dip, 6917ec090658Sml DDI_PROP_CANSLEEP, "#msix-request", NULL, 0); 6918ec090658Sml /* 6919ec090658Sml * The maximum MSI-X requested will be 8. 6920ef755e7aStc * If the # of CPUs is less than 8, we will request 6921ef755e7aStc * # MSI-X based on the # of CPUs (default). 6922ec090658Sml */ 6923ef755e7aStc NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6924ef755e7aStc "==>nxge_create_msi_property (10G): nxge_msix_10g_intrs %d", 6925ef755e7aStc nxge_msix_10g_intrs)); 6926ef755e7aStc if ((nxge_msix_10g_intrs == 0) || 6927ef755e7aStc (nxge_msix_10g_intrs > NXGE_MSIX_MAX_ALLOWED)) { 6928ec090658Sml nmsi = NXGE_MSIX_REQUEST_10G; 6929ef755e7aStc NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6930ef755e7aStc "==>nxge_create_msi_property (10G): reset to 8")); 6931ec090658Sml } else { 6932ef755e7aStc nmsi = nxge_msix_10g_intrs; 6933ef755e7aStc } 6934ef755e7aStc 6935ef755e7aStc /* 6936ef755e7aStc * If # of interrupts requested is 8 (default), 6937ef755e7aStc * the checking of the number of cpus will be 6938ef755e7aStc * be maintained. 6939ef755e7aStc */ 6940ef755e7aStc if ((nmsi == NXGE_MSIX_REQUEST_10G) && 6941ef755e7aStc (ncpus < nmsi)) { 6942ef755e7aStc NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6943ef755e7aStc "==>nxge_create_msi_property (10G): reset to 8")); 6944ec090658Sml nmsi = ncpus; 6945ec090658Sml } 6946ec090658Sml NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6947ec090658Sml "==>nxge_create_msi_property(10G): exists 0x%x (nmsi %d)", 6948ec090658Sml ddi_prop_exists(DDI_DEV_T_NONE, nxgep->dip, 6949ec090658Sml DDI_PROP_CANSLEEP, "#msix-request"), nmsi)); 6950ec090658Sml break; 6951ec090658Sml 6952ec090658Sml default: 6953ef755e7aStc (void) ddi_prop_create(DDI_DEV_T_NONE, nxgep->dip, 6954ef755e7aStc DDI_PROP_CANSLEEP, "#msix-request", NULL, 0); 6955ef755e7aStc NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6956ef755e7aStc "==>nxge_create_msi_property (1G): nxge_msix_1g_intrs %d", 6957ef755e7aStc nxge_msix_1g_intrs)); 6958ef755e7aStc if ((nxge_msix_1g_intrs == 0) || 6959ef755e7aStc (nxge_msix_1g_intrs > NXGE_MSIX_MAX_ALLOWED)) { 6960ef755e7aStc nmsi = NXGE_MSIX_REQUEST_1G; 6961ef755e7aStc NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6962ef755e7aStc "==>nxge_create_msi_property (1G): reset to 2")); 6963ef755e7aStc } else { 6964ef755e7aStc nmsi = nxge_msix_1g_intrs; 6965ef755e7aStc } 6966ec090658Sml NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6967ec090658Sml "==>nxge_create_msi_property(1G): exists 0x%x (nmsi %d)", 6968ec090658Sml ddi_prop_exists(DDI_DEV_T_NONE, nxgep->dip, 6969ec090658Sml DDI_PROP_CANSLEEP, "#msix-request"), nmsi)); 6970ec090658Sml break; 6971ec090658Sml } 6972ec090658Sml 6973ec090658Sml NXGE_DEBUG_MSG((nxgep, MOD_CTL, "<==nxge_create_msi_property")); 6974ec090658Sml return (nmsi); 6975ec090658Sml } 69764045d941Ssowmini 69774045d941Ssowmini /* ARGSUSED */ 69784045d941Ssowmini static int 69794045d941Ssowmini nxge_get_def_val(nxge_t *nxgep, mac_prop_id_t pr_num, uint_t pr_valsize, 69804045d941Ssowmini void *pr_val) 69814045d941Ssowmini { 69824045d941Ssowmini int err = 0; 69834045d941Ssowmini link_flowctrl_t fl; 69844045d941Ssowmini 69854045d941Ssowmini switch (pr_num) { 69863fd94f8cSam case MAC_PROP_AUTONEG: 69874045d941Ssowmini *(uint8_t *)pr_val = 1; 69884045d941Ssowmini break; 69893fd94f8cSam case MAC_PROP_FLOWCTRL: 69904045d941Ssowmini if (pr_valsize < sizeof (link_flowctrl_t)) 69914045d941Ssowmini return (EINVAL); 69924045d941Ssowmini fl = LINK_FLOWCTRL_RX; 69934045d941Ssowmini bcopy(&fl, pr_val, sizeof (fl)); 69944045d941Ssowmini break; 69953fd94f8cSam case MAC_PROP_ADV_1000FDX_CAP: 69963fd94f8cSam case MAC_PROP_EN_1000FDX_CAP: 69974045d941Ssowmini *(uint8_t *)pr_val = 1; 69984045d941Ssowmini break; 69993fd94f8cSam case MAC_PROP_ADV_100FDX_CAP: 70003fd94f8cSam case MAC_PROP_EN_100FDX_CAP: 70014045d941Ssowmini *(uint8_t *)pr_val = 1; 70024045d941Ssowmini break; 70034045d941Ssowmini default: 70044045d941Ssowmini err = ENOTSUP; 70054045d941Ssowmini break; 70064045d941Ssowmini } 70074045d941Ssowmini return (err); 70084045d941Ssowmini } 70096f157acbSml 70106f157acbSml 70116f157acbSml /* 70126f157acbSml * The following is a software around for the Neptune hardware's 70136f157acbSml * interrupt bugs; The Neptune hardware may generate spurious interrupts when 70146f157acbSml * an interrupr handler is removed. 70156f157acbSml */ 70166f157acbSml #define NXGE_PCI_PORT_LOGIC_OFFSET 0x98 70176f157acbSml #define NXGE_PIM_RESET (1ULL << 29) 70186f157acbSml #define NXGE_GLU_RESET (1ULL << 30) 70196f157acbSml #define NXGE_NIU_RESET (1ULL << 31) 70206f157acbSml #define NXGE_PCI_RESET_ALL (NXGE_PIM_RESET | \ 70216f157acbSml NXGE_GLU_RESET | \ 70226f157acbSml NXGE_NIU_RESET) 70236f157acbSml 70246f157acbSml #define NXGE_WAIT_QUITE_TIME 200000 70256f157acbSml #define NXGE_WAIT_QUITE_RETRY 40 70266f157acbSml #define NXGE_PCI_RESET_WAIT 1000000 /* one second */ 70276f157acbSml 70286f157acbSml static void 70296f157acbSml nxge_niu_peu_reset(p_nxge_t nxgep) 70306f157acbSml { 70316f157acbSml uint32_t rvalue; 70326f157acbSml p_nxge_hw_list_t hw_p; 70336f157acbSml p_nxge_t fnxgep; 70346f157acbSml int i, j; 70356f157acbSml 70366f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, "==> nxge_niu_peu_reset")); 70376f157acbSml if ((hw_p = nxgep->nxge_hw_p) == NULL) { 70386f157acbSml NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 70396f157acbSml "==> nxge_niu_peu_reset: NULL hardware pointer")); 70406f157acbSml return; 70416f157acbSml } 70426f157acbSml 70436f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 70446f157acbSml "==> nxge_niu_peu_reset: flags 0x%x link timer id %d timer id %d", 70456f157acbSml hw_p->flags, nxgep->nxge_link_poll_timerid, 70466f157acbSml nxgep->nxge_timerid)); 70476f157acbSml 70486f157acbSml MUTEX_ENTER(&hw_p->nxge_cfg_lock); 70496f157acbSml /* 70506f157acbSml * Make sure other instances from the same hardware 70516f157acbSml * stop sending PIO and in quiescent state. 70526f157acbSml */ 70536f157acbSml for (i = 0; i < NXGE_MAX_PORTS; i++) { 70546f157acbSml fnxgep = hw_p->nxge_p[i]; 70556f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 70566f157acbSml "==> nxge_niu_peu_reset: checking entry %d " 70576f157acbSml "nxgep $%p", i, fnxgep)); 70586f157acbSml #ifdef NXGE_DEBUG 70596f157acbSml if (fnxgep) { 70606f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 70616f157acbSml "==> nxge_niu_peu_reset: entry %d (function %d) " 70626f157acbSml "link timer id %d hw timer id %d", 70636f157acbSml i, fnxgep->function_num, 70646f157acbSml fnxgep->nxge_link_poll_timerid, 70656f157acbSml fnxgep->nxge_timerid)); 70666f157acbSml } 70676f157acbSml #endif 70686f157acbSml if (fnxgep && fnxgep != nxgep && 70696f157acbSml (fnxgep->nxge_timerid || fnxgep->nxge_link_poll_timerid)) { 70706f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 70716f157acbSml "==> nxge_niu_peu_reset: checking $%p " 70726f157acbSml "(function %d) timer ids", 70736f157acbSml fnxgep, fnxgep->function_num)); 70746f157acbSml for (j = 0; j < NXGE_WAIT_QUITE_RETRY; j++) { 70756f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 70766f157acbSml "==> nxge_niu_peu_reset: waiting")); 70776f157acbSml NXGE_DELAY(NXGE_WAIT_QUITE_TIME); 70786f157acbSml if (!fnxgep->nxge_timerid && 70796f157acbSml !fnxgep->nxge_link_poll_timerid) { 70806f157acbSml break; 70816f157acbSml } 70826f157acbSml } 70836f157acbSml NXGE_DELAY(NXGE_WAIT_QUITE_TIME); 70846f157acbSml if (fnxgep->nxge_timerid || 70856f157acbSml fnxgep->nxge_link_poll_timerid) { 70866f157acbSml MUTEX_EXIT(&hw_p->nxge_cfg_lock); 70876f157acbSml NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 70886f157acbSml "<== nxge_niu_peu_reset: cannot reset " 70896f157acbSml "hardware (devices are still in use)")); 70906f157acbSml return; 70916f157acbSml } 70926f157acbSml } 70936f157acbSml } 70946f157acbSml 70956f157acbSml if ((hw_p->flags & COMMON_RESET_NIU_PCI) != COMMON_RESET_NIU_PCI) { 70966f157acbSml hw_p->flags |= COMMON_RESET_NIU_PCI; 70976f157acbSml rvalue = pci_config_get32(nxgep->dev_regs->nxge_pciregh, 70986f157acbSml NXGE_PCI_PORT_LOGIC_OFFSET); 70996f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 71006f157acbSml "nxge_niu_peu_reset: read offset 0x%x (%d) " 71016f157acbSml "(data 0x%x)", 71026f157acbSml NXGE_PCI_PORT_LOGIC_OFFSET, 71036f157acbSml NXGE_PCI_PORT_LOGIC_OFFSET, 71046f157acbSml rvalue)); 71056f157acbSml 71066f157acbSml rvalue |= NXGE_PCI_RESET_ALL; 71076f157acbSml pci_config_put32(nxgep->dev_regs->nxge_pciregh, 71086f157acbSml NXGE_PCI_PORT_LOGIC_OFFSET, rvalue); 71096f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 71106f157acbSml "nxge_niu_peu_reset: RESETTING NIU: write NIU reset 0x%x", 71116f157acbSml rvalue)); 71126f157acbSml 71136f157acbSml NXGE_DELAY(NXGE_PCI_RESET_WAIT); 71146f157acbSml } 71156f157acbSml 71166f157acbSml MUTEX_EXIT(&hw_p->nxge_cfg_lock); 71176f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_niu_peu_reset")); 71186f157acbSml } 7119d6d3405fSml 7120d6d3405fSml static void 7121d6d3405fSml nxge_set_pci_replay_timeout(p_nxge_t nxgep) 7122d6d3405fSml { 7123da14cebeSEric Cheng p_dev_regs_t dev_regs; 7124d6d3405fSml uint32_t value; 7125d6d3405fSml 7126d6d3405fSml NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_set_pci_replay_timeout")); 7127d6d3405fSml 7128d6d3405fSml if (!nxge_set_replay_timer) { 7129d6d3405fSml NXGE_DEBUG_MSG((nxgep, DDI_CTL, 7130d6d3405fSml "==> nxge_set_pci_replay_timeout: will not change " 7131d6d3405fSml "the timeout")); 7132d6d3405fSml return; 7133d6d3405fSml } 7134d6d3405fSml 7135d6d3405fSml dev_regs = nxgep->dev_regs; 7136d6d3405fSml NXGE_DEBUG_MSG((nxgep, DDI_CTL, 7137d6d3405fSml "==> nxge_set_pci_replay_timeout: dev_regs 0x%p pcireg 0x%p", 7138d6d3405fSml dev_regs, dev_regs->nxge_pciregh)); 7139d6d3405fSml 7140d6d3405fSml if (dev_regs == NULL || (dev_regs->nxge_pciregh == NULL)) { 7141f720bc57Syc NXGE_DEBUG_MSG((nxgep, DDI_CTL, 7142d6d3405fSml "==> nxge_set_pci_replay_timeout: NULL dev_regs $%p or " 7143d6d3405fSml "no PCI handle", 7144d6d3405fSml dev_regs)); 7145d6d3405fSml return; 7146d6d3405fSml } 7147d6d3405fSml value = (pci_config_get32(dev_regs->nxge_pciregh, 7148d6d3405fSml PCI_REPLAY_TIMEOUT_CFG_OFFSET) | 7149d6d3405fSml (nxge_replay_timeout << PCI_REPLAY_TIMEOUT_SHIFT)); 7150d6d3405fSml 7151d6d3405fSml NXGE_DEBUG_MSG((nxgep, DDI_CTL, 7152d6d3405fSml "nxge_set_pci_replay_timeout: replay timeout value before set 0x%x " 7153d6d3405fSml "(timeout value to set 0x%x at offset 0x%x) value 0x%x", 7154d6d3405fSml pci_config_get32(dev_regs->nxge_pciregh, 7155d6d3405fSml PCI_REPLAY_TIMEOUT_CFG_OFFSET), nxge_replay_timeout, 7156d6d3405fSml PCI_REPLAY_TIMEOUT_CFG_OFFSET, value)); 7157d6d3405fSml 7158d6d3405fSml pci_config_put32(dev_regs->nxge_pciregh, PCI_REPLAY_TIMEOUT_CFG_OFFSET, 7159d6d3405fSml value); 7160d6d3405fSml 7161d6d3405fSml NXGE_DEBUG_MSG((nxgep, DDI_CTL, 7162d6d3405fSml "nxge_set_pci_replay_timeout: replay timeout value after set 0x%x", 7163d6d3405fSml pci_config_get32(dev_regs->nxge_pciregh, 7164d6d3405fSml PCI_REPLAY_TIMEOUT_CFG_OFFSET))); 7165d6d3405fSml 7166d6d3405fSml NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_set_pci_replay_timeout")); 7167d6d3405fSml } 716819397407SSherry Moore 716919397407SSherry Moore /* 717019397407SSherry Moore * quiesce(9E) entry point. 717119397407SSherry Moore * 717219397407SSherry Moore * This function is called when the system is single-threaded at high 717319397407SSherry Moore * PIL with preemption disabled. Therefore, this function must not be 717419397407SSherry Moore * blocked. 717519397407SSherry Moore * 717619397407SSherry Moore * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 717719397407SSherry Moore * DDI_FAILURE indicates an error condition and should almost never happen. 717819397407SSherry Moore */ 717919397407SSherry Moore static int 718019397407SSherry Moore nxge_quiesce(dev_info_t *dip) 718119397407SSherry Moore { 718219397407SSherry Moore int instance = ddi_get_instance(dip); 718319397407SSherry Moore p_nxge_t nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance); 718419397407SSherry Moore 718519397407SSherry Moore if (nxgep == NULL) 718619397407SSherry Moore return (DDI_FAILURE); 718719397407SSherry Moore 718819397407SSherry Moore /* Turn off debugging */ 718919397407SSherry Moore nxge_debug_level = NO_DEBUG; 719019397407SSherry Moore nxgep->nxge_debug_level = NO_DEBUG; 719119397407SSherry Moore npi_debug_level = NO_DEBUG; 719219397407SSherry Moore 719319397407SSherry Moore /* 719419397407SSherry Moore * Stop link monitor only when linkchkmod is interrupt based 719519397407SSherry Moore */ 719619397407SSherry Moore if (nxgep->mac.linkchkmode == LINKCHK_INTR) { 719719397407SSherry Moore (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 719819397407SSherry Moore } 719919397407SSherry Moore 720019397407SSherry Moore (void) nxge_intr_hw_disable(nxgep); 720119397407SSherry Moore 720219397407SSherry Moore /* 720319397407SSherry Moore * Reset the receive MAC side. 720419397407SSherry Moore */ 720519397407SSherry Moore (void) nxge_rx_mac_disable(nxgep); 720619397407SSherry Moore 720719397407SSherry Moore /* Disable and soft reset the IPP */ 720819397407SSherry Moore if (!isLDOMguest(nxgep)) 720919397407SSherry Moore (void) nxge_ipp_disable(nxgep); 721019397407SSherry Moore 721119397407SSherry Moore /* 721219397407SSherry Moore * Reset the transmit/receive DMA side. 721319397407SSherry Moore */ 721419397407SSherry Moore (void) nxge_txdma_hw_mode(nxgep, NXGE_DMA_STOP); 721519397407SSherry Moore (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_STOP); 721619397407SSherry Moore 721719397407SSherry Moore /* 721819397407SSherry Moore * Reset the transmit MAC side. 721919397407SSherry Moore */ 722019397407SSherry Moore (void) nxge_tx_mac_disable(nxgep); 722119397407SSherry Moore 722219397407SSherry Moore return (DDI_SUCCESS); 722319397407SSherry Moore } 7224