144961713Sgirish /* 244961713Sgirish * CDDL HEADER START 344961713Sgirish * 444961713Sgirish * The contents of this file are subject to the terms of the 544961713Sgirish * Common Development and Distribution License (the "License"). 644961713Sgirish * You may not use this file except in compliance with the License. 744961713Sgirish * 844961713Sgirish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 944961713Sgirish * or http://www.opensolaris.org/os/licensing. 1044961713Sgirish * See the License for the specific language governing permissions 1144961713Sgirish * and limitations under the License. 1244961713Sgirish * 1344961713Sgirish * When distributing Covered Code, include this CDDL HEADER in each 1444961713Sgirish * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1544961713Sgirish * If applicable, add the following below this CDDL HEADER, with the 1644961713Sgirish * fields enclosed by brackets "[]" replaced with your own identifying 1744961713Sgirish * information: Portions Copyright [yyyy] [name of copyright owner] 1844961713Sgirish * 1944961713Sgirish * CDDL HEADER END 2044961713Sgirish */ 2144961713Sgirish /* 2230ac2e7bSml * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 2344961713Sgirish * Use is subject to license terms. 2444961713Sgirish */ 2544961713Sgirish 2644961713Sgirish /* 2744961713Sgirish * SunOs MT STREAMS NIU/Neptune 10Gb Ethernet Device Driver. 2844961713Sgirish */ 2944961713Sgirish #include <sys/nxge/nxge_impl.h> 30678453a8Sspeer #include <sys/nxge/nxge_hio.h> 31678453a8Sspeer #include <sys/nxge/nxge_rxdma.h> 3214ea4bb7Ssd #include <sys/pcie.h> 3344961713Sgirish 3444961713Sgirish uint32_t nxge_use_partition = 0; /* debug partition flag */ 3544961713Sgirish uint32_t nxge_dma_obp_props_only = 1; /* use obp published props */ 3644961713Sgirish uint32_t nxge_use_rdc_intr = 1; /* debug to assign rdc intr */ 3744961713Sgirish /* 38ec090658Sml * PSARC/2007/453 MSI-X interrupt limit override 39ec090658Sml * (This PSARC case is limited to MSI-X vectors 40ec090658Sml * and SPARC platforms only). 4144961713Sgirish */ 42ec090658Sml #if defined(_BIG_ENDIAN) 43ec090658Sml uint32_t nxge_msi_enable = 2; 44ec090658Sml #else 45ec090658Sml uint32_t nxge_msi_enable = 1; 46ec090658Sml #endif 4744961713Sgirish 486f157acbSml /* 496f157acbSml * Software workaround for a Neptune (PCI-E) 506f157acbSml * hardware interrupt bug which the hardware 516f157acbSml * may generate spurious interrupts after the 526f157acbSml * device interrupt handler was removed. If this flag 536f157acbSml * is enabled, the driver will reset the 546f157acbSml * hardware when devices are being detached. 556f157acbSml */ 566f157acbSml uint32_t nxge_peu_reset_enable = 0; 576f157acbSml 58b4d05839Sml /* 59b4d05839Sml * Software workaround for the hardware 60b4d05839Sml * checksum bugs that affect packet transmission 61b4d05839Sml * and receive: 62b4d05839Sml * 63b4d05839Sml * Usage of nxge_cksum_offload: 64b4d05839Sml * 65b4d05839Sml * (1) nxge_cksum_offload = 0 (default): 66b4d05839Sml * - transmits packets: 67b4d05839Sml * TCP: uses the hardware checksum feature. 68b4d05839Sml * UDP: driver will compute the software checksum 69b4d05839Sml * based on the partial checksum computed 70b4d05839Sml * by the IP layer. 71b4d05839Sml * - receives packets 72b4d05839Sml * TCP: marks packets checksum flags based on hardware result. 73b4d05839Sml * UDP: will not mark checksum flags. 74b4d05839Sml * 75b4d05839Sml * (2) nxge_cksum_offload = 1: 76b4d05839Sml * - transmit packets: 77b4d05839Sml * TCP/UDP: uses the hardware checksum feature. 78b4d05839Sml * - receives packets 79b4d05839Sml * TCP/UDP: marks packet checksum flags based on hardware result. 80b4d05839Sml * 81b4d05839Sml * (3) nxge_cksum_offload = 2: 82b4d05839Sml * - The driver will not register its checksum capability. 83b4d05839Sml * Checksum for both TCP and UDP will be computed 84b4d05839Sml * by the stack. 85b4d05839Sml * - The software LSO is not allowed in this case. 86b4d05839Sml * 87b4d05839Sml * (4) nxge_cksum_offload > 2: 88b4d05839Sml * - Will be treated as it is set to 2 89b4d05839Sml * (stack will compute the checksum). 90b4d05839Sml * 91b4d05839Sml * (5) If the hardware bug is fixed, this workaround 92b4d05839Sml * needs to be updated accordingly to reflect 93b4d05839Sml * the new hardware revision. 94b4d05839Sml */ 95b4d05839Sml uint32_t nxge_cksum_offload = 0; 96678453a8Sspeer 9744961713Sgirish /* 9844961713Sgirish * Globals: tunable parameters (/etc/system or adb) 9944961713Sgirish * 10044961713Sgirish */ 10144961713Sgirish uint32_t nxge_rbr_size = NXGE_RBR_RBB_DEFAULT; 10244961713Sgirish uint32_t nxge_rbr_spare_size = 0; 10344961713Sgirish uint32_t nxge_rcr_size = NXGE_RCR_DEFAULT; 10444961713Sgirish uint32_t nxge_tx_ring_size = NXGE_TX_RING_DEFAULT; 105b3a0105bSspeer boolean_t nxge_no_msg = B_TRUE; /* control message display */ 10644961713Sgirish uint32_t nxge_no_link_notify = 0; /* control DL_NOTIFY */ 10744961713Sgirish uint32_t nxge_bcopy_thresh = TX_BCOPY_MAX; 10844961713Sgirish uint32_t nxge_dvma_thresh = TX_FASTDVMA_MIN; 10944961713Sgirish uint32_t nxge_dma_stream_thresh = TX_STREAM_MIN; 11044961713Sgirish uint32_t nxge_jumbo_mtu = TX_JUMBO_MTU; 11144961713Sgirish boolean_t nxge_jumbo_enable = B_FALSE; 11244961713Sgirish uint16_t nxge_rcr_timeout = NXGE_RDC_RCR_TIMEOUT; 11344961713Sgirish uint16_t nxge_rcr_threshold = NXGE_RDC_RCR_THRESHOLD; 1141f8914d5Sml nxge_tx_mode_t nxge_tx_scheme = NXGE_USE_SERIAL; 11544961713Sgirish 11630ac2e7bSml /* MAX LSO size */ 11730ac2e7bSml #define NXGE_LSO_MAXLEN 65535 11830ac2e7bSml uint32_t nxge_lso_max = NXGE_LSO_MAXLEN; 11930ac2e7bSml 12044961713Sgirish /* 12144961713Sgirish * Debugging flags: 12244961713Sgirish * nxge_no_tx_lb : transmit load balancing 12344961713Sgirish * nxge_tx_lb_policy: 0 - TCP port (default) 12444961713Sgirish * 3 - DEST MAC 12544961713Sgirish */ 12644961713Sgirish uint32_t nxge_no_tx_lb = 0; 12744961713Sgirish uint32_t nxge_tx_lb_policy = NXGE_TX_LB_TCPUDP; 12844961713Sgirish 12944961713Sgirish /* 13044961713Sgirish * Add tunable to reduce the amount of time spent in the 13144961713Sgirish * ISR doing Rx Processing. 13244961713Sgirish */ 13344961713Sgirish uint32_t nxge_max_rx_pkts = 1024; 13444961713Sgirish 13544961713Sgirish /* 13644961713Sgirish * Tunables to manage the receive buffer blocks. 13744961713Sgirish * 13844961713Sgirish * nxge_rx_threshold_hi: copy all buffers. 13944961713Sgirish * nxge_rx_bcopy_size_type: receive buffer block size type. 14044961713Sgirish * nxge_rx_threshold_lo: copy only up to tunable block size type. 14144961713Sgirish */ 14244961713Sgirish nxge_rxbuf_threshold_t nxge_rx_threshold_hi = NXGE_RX_COPY_6; 14344961713Sgirish nxge_rxbuf_type_t nxge_rx_buf_size_type = RCR_PKTBUFSZ_0; 14444961713Sgirish nxge_rxbuf_threshold_t nxge_rx_threshold_lo = NXGE_RX_COPY_3; 14544961713Sgirish 146678453a8Sspeer /* Use kmem_alloc() to allocate data buffers. */ 147b1000363Sml #if defined(_BIG_ENDIAN) 148d00f30bbSspeer uint32_t nxge_use_kmem_alloc = 1; 149678453a8Sspeer #else 150d00f30bbSspeer uint32_t nxge_use_kmem_alloc = 0; 151678453a8Sspeer #endif 152678453a8Sspeer 15344961713Sgirish rtrace_t npi_rtracebuf; 15444961713Sgirish 155d6d3405fSml /* 156d6d3405fSml * The hardware sometimes fails to allow enough time for the link partner 157d6d3405fSml * to send an acknowledgement for packets that the hardware sent to it. The 158d6d3405fSml * hardware resends the packets earlier than it should be in those instances. 159d6d3405fSml * This behavior caused some switches to acknowledge the wrong packets 160d6d3405fSml * and it triggered the fatal error. 161d6d3405fSml * This software workaround is to set the replay timer to a value 162d6d3405fSml * suggested by the hardware team. 163d6d3405fSml * 164d6d3405fSml * PCI config space replay timer register: 165d6d3405fSml * The following replay timeout value is 0xc 166d6d3405fSml * for bit 14:18. 167d6d3405fSml */ 168d6d3405fSml #define PCI_REPLAY_TIMEOUT_CFG_OFFSET 0xb8 169d6d3405fSml #define PCI_REPLAY_TIMEOUT_SHIFT 14 170d6d3405fSml 171d6d3405fSml uint32_t nxge_set_replay_timer = 1; 172d6d3405fSml uint32_t nxge_replay_timeout = 0xc; 173d6d3405fSml 174cf020df9Sml /* 175cf020df9Sml * The transmit serialization sometimes causes 176cf020df9Sml * longer sleep before calling the driver transmit 177cf020df9Sml * function as it sleeps longer than it should. 178cf020df9Sml * The performace group suggests that a time wait tunable 179cf020df9Sml * can be used to set the maximum wait time when needed 180cf020df9Sml * and the default is set to 1 tick. 181cf020df9Sml */ 182cf020df9Sml uint32_t nxge_tx_serial_maxsleep = 1; 183cf020df9Sml 18444961713Sgirish #if defined(sun4v) 18544961713Sgirish /* 18644961713Sgirish * Hypervisor N2/NIU services information. 18744961713Sgirish */ 18844961713Sgirish static hsvc_info_t niu_hsvc = { 18944961713Sgirish HSVC_REV_1, NULL, HSVC_GROUP_NIU, NIU_MAJOR_VER, 19044961713Sgirish NIU_MINOR_VER, "nxge" 19144961713Sgirish }; 192678453a8Sspeer 193678453a8Sspeer static int nxge_hsvc_register(p_nxge_t); 19444961713Sgirish #endif 19544961713Sgirish 19644961713Sgirish /* 19744961713Sgirish * Function Prototypes 19844961713Sgirish */ 19944961713Sgirish static int nxge_attach(dev_info_t *, ddi_attach_cmd_t); 20044961713Sgirish static int nxge_detach(dev_info_t *, ddi_detach_cmd_t); 20144961713Sgirish static void nxge_unattach(p_nxge_t); 202*19397407SSherry Moore static int nxge_quiesce(dev_info_t *); 20344961713Sgirish 20444961713Sgirish #if NXGE_PROPERTY 20544961713Sgirish static void nxge_remove_hard_properties(p_nxge_t); 20644961713Sgirish #endif 20744961713Sgirish 208678453a8Sspeer /* 209678453a8Sspeer * These two functions are required by nxge_hio.c 210678453a8Sspeer */ 211678453a8Sspeer extern int nxge_m_mmac_add(void *arg, mac_multi_addr_t *maddr); 212678453a8Sspeer extern int nxge_m_mmac_remove(void *arg, mac_addr_slot_t slot); 213678453a8Sspeer 21444961713Sgirish static nxge_status_t nxge_setup_system_dma_pages(p_nxge_t); 21544961713Sgirish 21644961713Sgirish static nxge_status_t nxge_setup_mutexes(p_nxge_t); 21744961713Sgirish static void nxge_destroy_mutexes(p_nxge_t); 21844961713Sgirish 21944961713Sgirish static nxge_status_t nxge_map_regs(p_nxge_t nxgep); 22044961713Sgirish static void nxge_unmap_regs(p_nxge_t nxgep); 22144961713Sgirish #ifdef NXGE_DEBUG 22244961713Sgirish static void nxge_test_map_regs(p_nxge_t nxgep); 22344961713Sgirish #endif 22444961713Sgirish 22544961713Sgirish static nxge_status_t nxge_add_intrs(p_nxge_t nxgep); 22644961713Sgirish static nxge_status_t nxge_add_soft_intrs(p_nxge_t nxgep); 22744961713Sgirish static void nxge_remove_intrs(p_nxge_t nxgep); 22844961713Sgirish static void nxge_remove_soft_intrs(p_nxge_t nxgep); 22944961713Sgirish 23044961713Sgirish static nxge_status_t nxge_add_intrs_adv(p_nxge_t nxgep); 23144961713Sgirish static nxge_status_t nxge_add_intrs_adv_type(p_nxge_t, uint32_t); 23244961713Sgirish static nxge_status_t nxge_add_intrs_adv_type_fix(p_nxge_t, uint32_t); 23344961713Sgirish static void nxge_intrs_enable(p_nxge_t nxgep); 23444961713Sgirish static void nxge_intrs_disable(p_nxge_t nxgep); 23544961713Sgirish 23644961713Sgirish static void nxge_suspend(p_nxge_t); 23744961713Sgirish static nxge_status_t nxge_resume(p_nxge_t); 23844961713Sgirish 23944961713Sgirish static nxge_status_t nxge_setup_dev(p_nxge_t); 24044961713Sgirish static void nxge_destroy_dev(p_nxge_t); 24144961713Sgirish 24244961713Sgirish static nxge_status_t nxge_alloc_mem_pool(p_nxge_t); 24344961713Sgirish static void nxge_free_mem_pool(p_nxge_t); 24444961713Sgirish 245678453a8Sspeer nxge_status_t nxge_alloc_rx_mem_pool(p_nxge_t); 24644961713Sgirish static void nxge_free_rx_mem_pool(p_nxge_t); 24744961713Sgirish 248678453a8Sspeer nxge_status_t nxge_alloc_tx_mem_pool(p_nxge_t); 24944961713Sgirish static void nxge_free_tx_mem_pool(p_nxge_t); 25044961713Sgirish 25144961713Sgirish static nxge_status_t nxge_dma_mem_alloc(p_nxge_t, dma_method_t, 25244961713Sgirish struct ddi_dma_attr *, 25344961713Sgirish size_t, ddi_device_acc_attr_t *, uint_t, 25444961713Sgirish p_nxge_dma_common_t); 25544961713Sgirish 25644961713Sgirish static void nxge_dma_mem_free(p_nxge_dma_common_t); 257678453a8Sspeer static void nxge_dma_free_rx_data_buf(p_nxge_dma_common_t); 25844961713Sgirish 25944961713Sgirish static nxge_status_t nxge_alloc_rx_buf_dma(p_nxge_t, uint16_t, 26044961713Sgirish p_nxge_dma_common_t *, size_t, size_t, uint32_t *); 26144961713Sgirish static void nxge_free_rx_buf_dma(p_nxge_t, p_nxge_dma_common_t, uint32_t); 26244961713Sgirish 26344961713Sgirish static nxge_status_t nxge_alloc_rx_cntl_dma(p_nxge_t, uint16_t, 26444961713Sgirish p_nxge_dma_common_t *, size_t); 26544961713Sgirish static void nxge_free_rx_cntl_dma(p_nxge_t, p_nxge_dma_common_t); 26644961713Sgirish 267678453a8Sspeer extern nxge_status_t nxge_alloc_tx_buf_dma(p_nxge_t, uint16_t, 26844961713Sgirish p_nxge_dma_common_t *, size_t, size_t, uint32_t *); 26944961713Sgirish static void nxge_free_tx_buf_dma(p_nxge_t, p_nxge_dma_common_t, uint32_t); 27044961713Sgirish 271678453a8Sspeer extern nxge_status_t nxge_alloc_tx_cntl_dma(p_nxge_t, uint16_t, 27244961713Sgirish p_nxge_dma_common_t *, 27344961713Sgirish size_t); 27444961713Sgirish static void nxge_free_tx_cntl_dma(p_nxge_t, p_nxge_dma_common_t); 27544961713Sgirish 27644961713Sgirish static int nxge_init_common_dev(p_nxge_t); 27744961713Sgirish static void nxge_uninit_common_dev(p_nxge_t); 2784045d941Ssowmini extern int nxge_param_set_mac(p_nxge_t, queue_t *, mblk_t *, 2794045d941Ssowmini char *, caddr_t); 28044961713Sgirish 28144961713Sgirish /* 28244961713Sgirish * The next declarations are for the GLDv3 interface. 28344961713Sgirish */ 28444961713Sgirish static int nxge_m_start(void *); 28544961713Sgirish static void nxge_m_stop(void *); 28644961713Sgirish static int nxge_m_unicst(void *, const uint8_t *); 28744961713Sgirish static int nxge_m_multicst(void *, boolean_t, const uint8_t *); 28844961713Sgirish static int nxge_m_promisc(void *, boolean_t); 28944961713Sgirish static void nxge_m_ioctl(void *, queue_t *, mblk_t *); 29044961713Sgirish static void nxge_m_resources(void *); 29144961713Sgirish mblk_t *nxge_m_tx(void *arg, mblk_t *); 29244961713Sgirish static nxge_status_t nxge_mac_register(p_nxge_t); 29358324dfcSspeer static int nxge_altmac_set(p_nxge_t nxgep, uint8_t *mac_addr, 29458324dfcSspeer mac_addr_slot_t slot); 295678453a8Sspeer void nxge_mmac_kstat_update(p_nxge_t nxgep, mac_addr_slot_t slot, 29658324dfcSspeer boolean_t factory); 29758324dfcSspeer static int nxge_m_mmac_reserve(void *arg, mac_multi_addr_t *maddr); 29858324dfcSspeer static int nxge_m_mmac_modify(void *arg, mac_multi_addr_t *maddr); 29958324dfcSspeer static int nxge_m_mmac_get(void *arg, mac_multi_addr_t *maddr); 3001bd6825cSml static boolean_t nxge_m_getcapab(void *, mac_capab_t, void *); 3011bd6825cSml static int nxge_m_setprop(void *, const char *, mac_prop_id_t, 3021bd6825cSml uint_t, const void *); 3031bd6825cSml static int nxge_m_getprop(void *, const char *, mac_prop_id_t, 3044045d941Ssowmini uint_t, uint_t, void *); 3051bd6825cSml static int nxge_set_priv_prop(nxge_t *, const char *, uint_t, 3061bd6825cSml const void *); 3074045d941Ssowmini static int nxge_get_priv_prop(nxge_t *, const char *, uint_t, uint_t, 3081bd6825cSml void *); 3094045d941Ssowmini static int nxge_get_def_val(nxge_t *, mac_prop_id_t, uint_t, void *); 3104045d941Ssowmini 3116f157acbSml static void nxge_niu_peu_reset(p_nxge_t nxgep); 312d6d3405fSml static void nxge_set_pci_replay_timeout(nxge_t *); 3134045d941Ssowmini 3144045d941Ssowmini mac_priv_prop_t nxge_priv_props[] = { 3154045d941Ssowmini {"_adv_10gfdx_cap", MAC_PROP_PERM_RW}, 3164045d941Ssowmini {"_adv_pause_cap", MAC_PROP_PERM_RW}, 3174045d941Ssowmini {"_function_number", MAC_PROP_PERM_READ}, 3184045d941Ssowmini {"_fw_version", MAC_PROP_PERM_READ}, 3194045d941Ssowmini {"_port_mode", MAC_PROP_PERM_READ}, 3204045d941Ssowmini {"_hot_swap_phy", MAC_PROP_PERM_READ}, 3214045d941Ssowmini {"_accept_jumbo", MAC_PROP_PERM_RW}, 3224045d941Ssowmini {"_rxdma_intr_time", MAC_PROP_PERM_RW}, 3234045d941Ssowmini {"_rxdma_intr_pkts", MAC_PROP_PERM_RW}, 3244045d941Ssowmini {"_class_opt_ipv4_tcp", MAC_PROP_PERM_RW}, 3254045d941Ssowmini {"_class_opt_ipv4_udp", MAC_PROP_PERM_RW}, 3264045d941Ssowmini {"_class_opt_ipv4_ah", MAC_PROP_PERM_RW}, 3274045d941Ssowmini {"_class_opt_ipv4_sctp", MAC_PROP_PERM_RW}, 3284045d941Ssowmini {"_class_opt_ipv6_tcp", MAC_PROP_PERM_RW}, 3294045d941Ssowmini {"_class_opt_ipv6_udp", MAC_PROP_PERM_RW}, 3304045d941Ssowmini {"_class_opt_ipv6_ah", MAC_PROP_PERM_RW}, 3314045d941Ssowmini {"_class_opt_ipv6_sctp", MAC_PROP_PERM_RW}, 3324045d941Ssowmini {"_soft_lso_enable", MAC_PROP_PERM_RW} 3334045d941Ssowmini }; 3344045d941Ssowmini 3354045d941Ssowmini #define NXGE_MAX_PRIV_PROPS \ 3364045d941Ssowmini (sizeof (nxge_priv_props)/sizeof (mac_priv_prop_t)) 3371bd6825cSml 3381bd6825cSml #define NXGE_M_CALLBACK_FLAGS\ 3391bd6825cSml (MC_RESOURCES | MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP) 3401bd6825cSml 34144961713Sgirish 34244961713Sgirish #define NXGE_NEPTUNE_MAGIC 0x4E584745UL 34344961713Sgirish #define MAX_DUMP_SZ 256 34444961713Sgirish 3451bd6825cSml #define NXGE_M_CALLBACK_FLAGS \ 3461bd6825cSml (MC_RESOURCES | MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP) 34744961713Sgirish 348678453a8Sspeer mac_callbacks_t nxge_m_callbacks = { 34944961713Sgirish NXGE_M_CALLBACK_FLAGS, 35044961713Sgirish nxge_m_stat, 35144961713Sgirish nxge_m_start, 35244961713Sgirish nxge_m_stop, 35344961713Sgirish nxge_m_promisc, 35444961713Sgirish nxge_m_multicst, 35544961713Sgirish nxge_m_unicst, 35644961713Sgirish nxge_m_tx, 35744961713Sgirish nxge_m_resources, 35844961713Sgirish nxge_m_ioctl, 3591bd6825cSml nxge_m_getcapab, 3601bd6825cSml NULL, 3611bd6825cSml NULL, 3621bd6825cSml nxge_m_setprop, 3631bd6825cSml nxge_m_getprop 36444961713Sgirish }; 36544961713Sgirish 36644961713Sgirish void 36744961713Sgirish nxge_err_inject(p_nxge_t, queue_t *, mblk_t *); 36844961713Sgirish 369ec090658Sml /* PSARC/2007/453 MSI-X interrupt limit override. */ 370ec090658Sml #define NXGE_MSIX_REQUEST_10G 8 371ec090658Sml #define NXGE_MSIX_REQUEST_1G 2 372ec090658Sml static int nxge_create_msi_property(p_nxge_t); 373ec090658Sml 37444961713Sgirish /* 37544961713Sgirish * These global variables control the message 37644961713Sgirish * output. 37744961713Sgirish */ 37844961713Sgirish out_dbgmsg_t nxge_dbgmsg_out = DBG_CONSOLE | STR_LOG; 379678453a8Sspeer uint64_t nxge_debug_level; 38044961713Sgirish 38144961713Sgirish /* 38244961713Sgirish * This list contains the instance structures for the Neptune 38344961713Sgirish * devices present in the system. The lock exists to guarantee 38444961713Sgirish * mutually exclusive access to the list. 38544961713Sgirish */ 38644961713Sgirish void *nxge_list = NULL; 38744961713Sgirish 38844961713Sgirish void *nxge_hw_list = NULL; 38944961713Sgirish nxge_os_mutex_t nxge_common_lock; 39044961713Sgirish 39144961713Sgirish extern uint64_t npi_debug_level; 39244961713Sgirish 39344961713Sgirish extern nxge_status_t nxge_ldgv_init(p_nxge_t, int *, int *); 39444961713Sgirish extern nxge_status_t nxge_ldgv_init_n2(p_nxge_t, int *, int *); 39544961713Sgirish extern nxge_status_t nxge_ldgv_uninit(p_nxge_t); 39644961713Sgirish extern nxge_status_t nxge_intr_ldgv_init(p_nxge_t); 39744961713Sgirish extern void nxge_fm_init(p_nxge_t, 39844961713Sgirish ddi_device_acc_attr_t *, 39944961713Sgirish ddi_device_acc_attr_t *, 40044961713Sgirish ddi_dma_attr_t *); 40144961713Sgirish extern void nxge_fm_fini(p_nxge_t); 40258324dfcSspeer extern npi_status_t npi_mac_altaddr_disable(npi_handle_t, uint8_t, uint8_t); 40344961713Sgirish 40444961713Sgirish /* 40544961713Sgirish * Count used to maintain the number of buffers being used 40644961713Sgirish * by Neptune instances and loaned up to the upper layers. 40744961713Sgirish */ 40844961713Sgirish uint32_t nxge_mblks_pending = 0; 40944961713Sgirish 41044961713Sgirish /* 41144961713Sgirish * Device register access attributes for PIO. 41244961713Sgirish */ 41344961713Sgirish static ddi_device_acc_attr_t nxge_dev_reg_acc_attr = { 41444961713Sgirish DDI_DEVICE_ATTR_V0, 41544961713Sgirish DDI_STRUCTURE_LE_ACC, 41644961713Sgirish DDI_STRICTORDER_ACC, 41744961713Sgirish }; 41844961713Sgirish 41944961713Sgirish /* 42044961713Sgirish * Device descriptor access attributes for DMA. 42144961713Sgirish */ 42244961713Sgirish static ddi_device_acc_attr_t nxge_dev_desc_dma_acc_attr = { 42344961713Sgirish DDI_DEVICE_ATTR_V0, 42444961713Sgirish DDI_STRUCTURE_LE_ACC, 42544961713Sgirish DDI_STRICTORDER_ACC 42644961713Sgirish }; 42744961713Sgirish 42844961713Sgirish /* 42944961713Sgirish * Device buffer access attributes for DMA. 43044961713Sgirish */ 43144961713Sgirish static ddi_device_acc_attr_t nxge_dev_buf_dma_acc_attr = { 43244961713Sgirish DDI_DEVICE_ATTR_V0, 43344961713Sgirish DDI_STRUCTURE_BE_ACC, 43444961713Sgirish DDI_STRICTORDER_ACC 43544961713Sgirish }; 43644961713Sgirish 43744961713Sgirish ddi_dma_attr_t nxge_desc_dma_attr = { 43844961713Sgirish DMA_ATTR_V0, /* version number. */ 43944961713Sgirish 0, /* low address */ 44044961713Sgirish 0xffffffffffffffff, /* high address */ 44144961713Sgirish 0xffffffffffffffff, /* address counter max */ 44244961713Sgirish #ifndef NIU_PA_WORKAROUND 44344961713Sgirish 0x100000, /* alignment */ 44444961713Sgirish #else 44544961713Sgirish 0x2000, 44644961713Sgirish #endif 44744961713Sgirish 0xfc00fc, /* dlim_burstsizes */ 44844961713Sgirish 0x1, /* minimum transfer size */ 44944961713Sgirish 0xffffffffffffffff, /* maximum transfer size */ 45044961713Sgirish 0xffffffffffffffff, /* maximum segment size */ 45144961713Sgirish 1, /* scatter/gather list length */ 45244961713Sgirish (unsigned int) 1, /* granularity */ 45344961713Sgirish 0 /* attribute flags */ 45444961713Sgirish }; 45544961713Sgirish 45644961713Sgirish ddi_dma_attr_t nxge_tx_dma_attr = { 45744961713Sgirish DMA_ATTR_V0, /* version number. */ 45844961713Sgirish 0, /* low address */ 45944961713Sgirish 0xffffffffffffffff, /* high address */ 46044961713Sgirish 0xffffffffffffffff, /* address counter max */ 46144961713Sgirish #if defined(_BIG_ENDIAN) 46244961713Sgirish 0x2000, /* alignment */ 46344961713Sgirish #else 46444961713Sgirish 0x1000, /* alignment */ 46544961713Sgirish #endif 46644961713Sgirish 0xfc00fc, /* dlim_burstsizes */ 46744961713Sgirish 0x1, /* minimum transfer size */ 46844961713Sgirish 0xffffffffffffffff, /* maximum transfer size */ 46944961713Sgirish 0xffffffffffffffff, /* maximum segment size */ 47044961713Sgirish 5, /* scatter/gather list length */ 47144961713Sgirish (unsigned int) 1, /* granularity */ 47244961713Sgirish 0 /* attribute flags */ 47344961713Sgirish }; 47444961713Sgirish 47544961713Sgirish ddi_dma_attr_t nxge_rx_dma_attr = { 47644961713Sgirish DMA_ATTR_V0, /* version number. */ 47744961713Sgirish 0, /* low address */ 47844961713Sgirish 0xffffffffffffffff, /* high address */ 47944961713Sgirish 0xffffffffffffffff, /* address counter max */ 48044961713Sgirish 0x2000, /* alignment */ 48144961713Sgirish 0xfc00fc, /* dlim_burstsizes */ 48244961713Sgirish 0x1, /* minimum transfer size */ 48344961713Sgirish 0xffffffffffffffff, /* maximum transfer size */ 48444961713Sgirish 0xffffffffffffffff, /* maximum segment size */ 48544961713Sgirish 1, /* scatter/gather list length */ 48644961713Sgirish (unsigned int) 1, /* granularity */ 4870e2bd521Ssbehera DDI_DMA_RELAXED_ORDERING /* attribute flags */ 48844961713Sgirish }; 48944961713Sgirish 49044961713Sgirish ddi_dma_lim_t nxge_dma_limits = { 49144961713Sgirish (uint_t)0, /* dlim_addr_lo */ 49244961713Sgirish (uint_t)0xffffffff, /* dlim_addr_hi */ 49344961713Sgirish (uint_t)0xffffffff, /* dlim_cntr_max */ 49444961713Sgirish (uint_t)0xfc00fc, /* dlim_burstsizes for 32 and 64 bit xfers */ 49544961713Sgirish 0x1, /* dlim_minxfer */ 49644961713Sgirish 1024 /* dlim_speed */ 49744961713Sgirish }; 49844961713Sgirish 49944961713Sgirish dma_method_t nxge_force_dma = DVMA; 50044961713Sgirish 50144961713Sgirish /* 50244961713Sgirish * dma chunk sizes. 50344961713Sgirish * 50444961713Sgirish * Try to allocate the largest possible size 50544961713Sgirish * so that fewer number of dma chunks would be managed 50644961713Sgirish */ 50744961713Sgirish #ifdef NIU_PA_WORKAROUND 50844961713Sgirish size_t alloc_sizes [] = {0x2000}; 50944961713Sgirish #else 51044961713Sgirish size_t alloc_sizes [] = {0x1000, 0x2000, 0x4000, 0x8000, 51144961713Sgirish 0x10000, 0x20000, 0x40000, 0x80000, 51230ac2e7bSml 0x100000, 0x200000, 0x400000, 0x800000, 51330ac2e7bSml 0x1000000, 0x2000000, 0x4000000}; 51444961713Sgirish #endif 51544961713Sgirish 51644961713Sgirish /* 51744961713Sgirish * Translate "dev_t" to a pointer to the associated "dev_info_t". 51844961713Sgirish */ 51944961713Sgirish 520678453a8Sspeer extern void nxge_get_environs(nxge_t *); 521678453a8Sspeer 52244961713Sgirish static int 52344961713Sgirish nxge_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 52444961713Sgirish { 52544961713Sgirish p_nxge_t nxgep = NULL; 52644961713Sgirish int instance; 52744961713Sgirish int status = DDI_SUCCESS; 52844961713Sgirish uint8_t portn; 52958324dfcSspeer nxge_mmac_t *mmac_info; 5307b1f684aSSriharsha Basavapatna p_nxge_param_t param_arr; 53144961713Sgirish 53244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_attach")); 53344961713Sgirish 53444961713Sgirish /* 53544961713Sgirish * Get the device instance since we'll need to setup 53644961713Sgirish * or retrieve a soft state for this instance. 53744961713Sgirish */ 53844961713Sgirish instance = ddi_get_instance(dip); 53944961713Sgirish 54044961713Sgirish switch (cmd) { 54144961713Sgirish case DDI_ATTACH: 54244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_ATTACH")); 54344961713Sgirish break; 54444961713Sgirish 54544961713Sgirish case DDI_RESUME: 54644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_RESUME")); 54744961713Sgirish nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance); 54844961713Sgirish if (nxgep == NULL) { 54944961713Sgirish status = DDI_FAILURE; 55044961713Sgirish break; 55144961713Sgirish } 55244961713Sgirish if (nxgep->dip != dip) { 55344961713Sgirish status = DDI_FAILURE; 55444961713Sgirish break; 55544961713Sgirish } 55644961713Sgirish if (nxgep->suspended == DDI_PM_SUSPEND) { 55744961713Sgirish status = ddi_dev_is_needed(nxgep->dip, 0, 1); 55844961713Sgirish } else { 55956d930aeSspeer status = nxge_resume(nxgep); 56044961713Sgirish } 56144961713Sgirish goto nxge_attach_exit; 56244961713Sgirish 56344961713Sgirish case DDI_PM_RESUME: 56444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_PM_RESUME")); 56544961713Sgirish nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance); 56644961713Sgirish if (nxgep == NULL) { 56744961713Sgirish status = DDI_FAILURE; 56844961713Sgirish break; 56944961713Sgirish } 57044961713Sgirish if (nxgep->dip != dip) { 57144961713Sgirish status = DDI_FAILURE; 57244961713Sgirish break; 57344961713Sgirish } 57456d930aeSspeer status = nxge_resume(nxgep); 57544961713Sgirish goto nxge_attach_exit; 57644961713Sgirish 57744961713Sgirish default: 57844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing unknown")); 57944961713Sgirish status = DDI_FAILURE; 58044961713Sgirish goto nxge_attach_exit; 58144961713Sgirish } 58244961713Sgirish 58344961713Sgirish 58444961713Sgirish if (ddi_soft_state_zalloc(nxge_list, instance) == DDI_FAILURE) { 58544961713Sgirish status = DDI_FAILURE; 58644961713Sgirish goto nxge_attach_exit; 58744961713Sgirish } 58844961713Sgirish 58944961713Sgirish nxgep = ddi_get_soft_state(nxge_list, instance); 59044961713Sgirish if (nxgep == NULL) { 5912e59129aSraghus status = NXGE_ERROR; 5922e59129aSraghus goto nxge_attach_fail2; 59344961713Sgirish } 59444961713Sgirish 59598ecde52Stm nxgep->nxge_magic = NXGE_MAGIC; 59698ecde52Stm 59744961713Sgirish nxgep->drv_state = 0; 59844961713Sgirish nxgep->dip = dip; 59944961713Sgirish nxgep->instance = instance; 60044961713Sgirish nxgep->p_dip = ddi_get_parent(dip); 60144961713Sgirish nxgep->nxge_debug_level = nxge_debug_level; 60244961713Sgirish npi_debug_level = nxge_debug_level; 60344961713Sgirish 604678453a8Sspeer /* Are we a guest running in a Hybrid I/O environment? */ 605678453a8Sspeer nxge_get_environs(nxgep); 60644961713Sgirish 60744961713Sgirish status = nxge_map_regs(nxgep); 608678453a8Sspeer 60944961713Sgirish if (status != NXGE_OK) { 61044961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_map_regs failed")); 6112e59129aSraghus goto nxge_attach_fail3; 61244961713Sgirish } 61344961713Sgirish 614678453a8Sspeer nxge_fm_init(nxgep, &nxge_dev_reg_acc_attr, 615678453a8Sspeer &nxge_dev_desc_dma_acc_attr, 616678453a8Sspeer &nxge_rx_dma_attr); 617678453a8Sspeer 618678453a8Sspeer /* Create & initialize the per-Neptune data structure */ 619678453a8Sspeer /* (even if we're a guest). */ 62044961713Sgirish status = nxge_init_common_dev(nxgep); 62144961713Sgirish if (status != NXGE_OK) { 62244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6234045d941Ssowmini "nxge_init_common_dev failed")); 6242e59129aSraghus goto nxge_attach_fail4; 62544961713Sgirish } 62644961713Sgirish 627d6d3405fSml /* 628d6d3405fSml * Software workaround: set the replay timer. 629d6d3405fSml */ 630d6d3405fSml if (nxgep->niu_type != N2_NIU) { 631d6d3405fSml nxge_set_pci_replay_timeout(nxgep); 632d6d3405fSml } 633d6d3405fSml 634678453a8Sspeer #if defined(sun4v) 635678453a8Sspeer /* This is required by nxge_hio_init(), which follows. */ 636678453a8Sspeer if ((status = nxge_hsvc_register(nxgep)) != DDI_SUCCESS) 6379d5b8bc5SMichael Speer goto nxge_attach_fail4; 638678453a8Sspeer #endif 639678453a8Sspeer 640678453a8Sspeer if ((status = nxge_hio_init(nxgep)) != NXGE_OK) { 641678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6424045d941Ssowmini "nxge_hio_init failed")); 643678453a8Sspeer goto nxge_attach_fail4; 644678453a8Sspeer } 645678453a8Sspeer 64659ac0c16Sdavemq if (nxgep->niu_type == NEPTUNE_2_10GF) { 64759ac0c16Sdavemq if (nxgep->function_num > 1) { 6484202ea4bSsbehera NXGE_DEBUG_MSG((nxgep, DDI_CTL, "Unsupported" 64959ac0c16Sdavemq " function %d. Only functions 0 and 1 are " 65059ac0c16Sdavemq "supported for this card.", nxgep->function_num)); 65159ac0c16Sdavemq status = NXGE_ERROR; 6522e59129aSraghus goto nxge_attach_fail4; 65359ac0c16Sdavemq } 65459ac0c16Sdavemq } 65559ac0c16Sdavemq 656678453a8Sspeer if (isLDOMguest(nxgep)) { 657678453a8Sspeer /* 658678453a8Sspeer * Use the function number here. 659678453a8Sspeer */ 660678453a8Sspeer nxgep->mac.portnum = nxgep->function_num; 661678453a8Sspeer nxgep->mac.porttype = PORT_TYPE_LOGICAL; 662678453a8Sspeer 663678453a8Sspeer /* XXX We'll set the MAC address counts to 1 for now. */ 664678453a8Sspeer mmac_info = &nxgep->nxge_mmac_info; 665678453a8Sspeer mmac_info->num_mmac = 1; 666678453a8Sspeer mmac_info->naddrfree = 1; 66758324dfcSspeer } else { 668678453a8Sspeer portn = NXGE_GET_PORT_NUM(nxgep->function_num); 669678453a8Sspeer nxgep->mac.portnum = portn; 670678453a8Sspeer if ((portn == 0) || (portn == 1)) 671678453a8Sspeer nxgep->mac.porttype = PORT_TYPE_XMAC; 672678453a8Sspeer else 673678453a8Sspeer nxgep->mac.porttype = PORT_TYPE_BMAC; 674678453a8Sspeer /* 675678453a8Sspeer * Neptune has 4 ports, the first 2 ports use XMAC (10G MAC) 676678453a8Sspeer * internally, the rest 2 ports use BMAC (1G "Big" MAC). 677678453a8Sspeer * The two types of MACs have different characterizations. 678678453a8Sspeer */ 679678453a8Sspeer mmac_info = &nxgep->nxge_mmac_info; 680678453a8Sspeer if (nxgep->function_num < 2) { 681678453a8Sspeer mmac_info->num_mmac = XMAC_MAX_ALT_ADDR_ENTRY; 682678453a8Sspeer mmac_info->naddrfree = XMAC_MAX_ALT_ADDR_ENTRY; 683678453a8Sspeer } else { 684678453a8Sspeer mmac_info->num_mmac = BMAC_MAX_ALT_ADDR_ENTRY; 685678453a8Sspeer mmac_info->naddrfree = BMAC_MAX_ALT_ADDR_ENTRY; 686678453a8Sspeer } 68758324dfcSspeer } 68844961713Sgirish /* 68944961713Sgirish * Setup the Ndd parameters for the this instance. 69044961713Sgirish */ 69144961713Sgirish nxge_init_param(nxgep); 69244961713Sgirish 69344961713Sgirish /* 69444961713Sgirish * Setup Register Tracing Buffer. 69544961713Sgirish */ 69644961713Sgirish npi_rtrace_buf_init((rtrace_t *)&npi_rtracebuf); 69744961713Sgirish 69844961713Sgirish /* init stats ptr */ 69944961713Sgirish nxge_init_statsp(nxgep); 70056d930aeSspeer 7012e59129aSraghus /* 702678453a8Sspeer * Copy the vpd info from eeprom to a local data 703678453a8Sspeer * structure, and then check its validity. 7042e59129aSraghus */ 705678453a8Sspeer if (!isLDOMguest(nxgep)) { 706678453a8Sspeer int *regp; 707678453a8Sspeer uint_t reglen; 708678453a8Sspeer int rv; 70956d930aeSspeer 710678453a8Sspeer nxge_vpd_info_get(nxgep); 71144961713Sgirish 712678453a8Sspeer /* Find the NIU config handle. */ 713678453a8Sspeer rv = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, 714678453a8Sspeer ddi_get_parent(nxgep->dip), DDI_PROP_DONTPASS, 715678453a8Sspeer "reg", ®p, ®len); 716678453a8Sspeer 717678453a8Sspeer if (rv != DDI_PROP_SUCCESS) { 718678453a8Sspeer goto nxge_attach_fail5; 719678453a8Sspeer } 720678453a8Sspeer /* 721678453a8Sspeer * The address_hi, that is the first int, in the reg 722678453a8Sspeer * property consists of config handle, but need to remove 723678453a8Sspeer * the bits 28-31 which are OBP specific info. 724678453a8Sspeer */ 725678453a8Sspeer nxgep->niu_cfg_hdl = (*regp) & 0xFFFFFFF; 726678453a8Sspeer ddi_prop_free(regp); 72744961713Sgirish } 72844961713Sgirish 729678453a8Sspeer if (isLDOMguest(nxgep)) { 730678453a8Sspeer uchar_t *prop_val; 731678453a8Sspeer uint_t prop_len; 7327b1f684aSSriharsha Basavapatna uint32_t max_frame_size; 73344961713Sgirish 734678453a8Sspeer extern void nxge_get_logical_props(p_nxge_t); 735678453a8Sspeer 736678453a8Sspeer nxgep->statsp->mac_stats.xcvr_inuse = LOGICAL_XCVR; 737678453a8Sspeer nxgep->mac.portmode = PORT_LOGICAL; 738678453a8Sspeer (void) ddi_prop_update_string(DDI_DEV_T_NONE, nxgep->dip, 739678453a8Sspeer "phy-type", "virtual transceiver"); 740678453a8Sspeer 741678453a8Sspeer nxgep->nports = 1; 742678453a8Sspeer nxgep->board_ver = 0; /* XXX What? */ 743678453a8Sspeer 744678453a8Sspeer /* 745678453a8Sspeer * local-mac-address property gives us info on which 746678453a8Sspeer * specific MAC address the Hybrid resource is associated 747678453a8Sspeer * with. 748678453a8Sspeer */ 749678453a8Sspeer if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0, 750678453a8Sspeer "local-mac-address", &prop_val, 751678453a8Sspeer &prop_len) != DDI_PROP_SUCCESS) { 752678453a8Sspeer goto nxge_attach_fail5; 753678453a8Sspeer } 754678453a8Sspeer if (prop_len != ETHERADDRL) { 755678453a8Sspeer ddi_prop_free(prop_val); 756678453a8Sspeer goto nxge_attach_fail5; 757678453a8Sspeer } 758678453a8Sspeer ether_copy(prop_val, nxgep->hio_mac_addr); 759678453a8Sspeer ddi_prop_free(prop_val); 760678453a8Sspeer nxge_get_logical_props(nxgep); 761678453a8Sspeer 7627b1f684aSSriharsha Basavapatna /* 7637b1f684aSSriharsha Basavapatna * Enable Jumbo property based on the "max-frame-size" 7647b1f684aSSriharsha Basavapatna * property value. 7657b1f684aSSriharsha Basavapatna */ 7667b1f684aSSriharsha Basavapatna max_frame_size = ddi_prop_get_int(DDI_DEV_T_ANY, 7677b1f684aSSriharsha Basavapatna nxgep->dip, DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, 7687b1f684aSSriharsha Basavapatna "max-frame-size", NXGE_MTU_DEFAULT_MAX); 7697b1f684aSSriharsha Basavapatna if ((max_frame_size > NXGE_MTU_DEFAULT_MAX) && 7707b1f684aSSriharsha Basavapatna (max_frame_size <= TX_JUMBO_MTU)) { 7717b1f684aSSriharsha Basavapatna param_arr = nxgep->param_arr; 7727b1f684aSSriharsha Basavapatna 7737b1f684aSSriharsha Basavapatna param_arr[param_accept_jumbo].value = 1; 7747b1f684aSSriharsha Basavapatna nxgep->mac.is_jumbo = B_TRUE; 7757b1f684aSSriharsha Basavapatna nxgep->mac.maxframesize = (uint16_t)max_frame_size; 7767b1f684aSSriharsha Basavapatna nxgep->mac.default_mtu = nxgep->mac.maxframesize - 7777b1f684aSSriharsha Basavapatna NXGE_EHEADER_VLAN_CRC; 7787b1f684aSSriharsha Basavapatna } 779678453a8Sspeer } else { 780678453a8Sspeer status = nxge_xcvr_find(nxgep); 781678453a8Sspeer 782678453a8Sspeer if (status != NXGE_OK) { 783678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_attach: " 7844045d941Ssowmini " Couldn't determine card type" 7854045d941Ssowmini " .... exit ")); 786678453a8Sspeer goto nxge_attach_fail5; 787678453a8Sspeer } 788678453a8Sspeer 789678453a8Sspeer status = nxge_get_config_properties(nxgep); 790678453a8Sspeer 791678453a8Sspeer if (status != NXGE_OK) { 792678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 7934045d941Ssowmini "get_hw create failed")); 794678453a8Sspeer goto nxge_attach_fail; 795678453a8Sspeer } 79644961713Sgirish } 79744961713Sgirish 79844961713Sgirish /* 79944961713Sgirish * Setup the Kstats for the driver. 80044961713Sgirish */ 80144961713Sgirish nxge_setup_kstats(nxgep); 80244961713Sgirish 803678453a8Sspeer if (!isLDOMguest(nxgep)) 804678453a8Sspeer nxge_setup_param(nxgep); 80544961713Sgirish 80644961713Sgirish status = nxge_setup_system_dma_pages(nxgep); 80744961713Sgirish if (status != NXGE_OK) { 80844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "set dma page failed")); 80944961713Sgirish goto nxge_attach_fail; 81044961713Sgirish } 81144961713Sgirish 81244961713Sgirish nxge_hw_id_init(nxgep); 813678453a8Sspeer 814678453a8Sspeer if (!isLDOMguest(nxgep)) 815678453a8Sspeer nxge_hw_init_niu_common(nxgep); 81644961713Sgirish 81744961713Sgirish status = nxge_setup_mutexes(nxgep); 81844961713Sgirish if (status != NXGE_OK) { 81944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "set mutex failed")); 82044961713Sgirish goto nxge_attach_fail; 82144961713Sgirish } 82244961713Sgirish 823678453a8Sspeer #if defined(sun4v) 824678453a8Sspeer if (isLDOMguest(nxgep)) { 825678453a8Sspeer /* Find our VR & channel sets. */ 826678453a8Sspeer status = nxge_hio_vr_add(nxgep); 827678453a8Sspeer goto nxge_attach_exit; 828678453a8Sspeer } 829678453a8Sspeer #endif 830678453a8Sspeer 83144961713Sgirish status = nxge_setup_dev(nxgep); 83244961713Sgirish if (status != DDI_SUCCESS) { 83344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "set dev failed")); 83444961713Sgirish goto nxge_attach_fail; 83544961713Sgirish } 83644961713Sgirish 83744961713Sgirish status = nxge_add_intrs(nxgep); 83844961713Sgirish if (status != DDI_SUCCESS) { 83944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "add_intr failed")); 84044961713Sgirish goto nxge_attach_fail; 84144961713Sgirish } 84244961713Sgirish status = nxge_add_soft_intrs(nxgep); 84344961713Sgirish if (status != DDI_SUCCESS) { 844678453a8Sspeer NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 845678453a8Sspeer "add_soft_intr failed")); 84644961713Sgirish goto nxge_attach_fail; 84744961713Sgirish } 84844961713Sgirish 84944961713Sgirish /* 85044961713Sgirish * Enable interrupts. 85144961713Sgirish */ 85244961713Sgirish nxge_intrs_enable(nxgep); 85344961713Sgirish 85400161856Syc /* If a guest, register with vio_net instead. */ 8552e59129aSraghus if ((status = nxge_mac_register(nxgep)) != NXGE_OK) { 85644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 857678453a8Sspeer "unable to register to mac layer (%d)", status)); 85844961713Sgirish goto nxge_attach_fail; 85944961713Sgirish } 86044961713Sgirish 86144961713Sgirish mac_link_update(nxgep->mach, LINK_STATE_UNKNOWN); 86244961713Sgirish 863678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DDI_CTL, 864678453a8Sspeer "registered to mac (instance %d)", instance)); 86544961713Sgirish 86600161856Syc /* nxge_link_monitor calls xcvr.check_link recursively */ 86744961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 86844961713Sgirish 86944961713Sgirish goto nxge_attach_exit; 87044961713Sgirish 87144961713Sgirish nxge_attach_fail: 87244961713Sgirish nxge_unattach(nxgep); 8732e59129aSraghus goto nxge_attach_fail1; 8742e59129aSraghus 8752e59129aSraghus nxge_attach_fail5: 8762e59129aSraghus /* 8772e59129aSraghus * Tear down the ndd parameters setup. 8782e59129aSraghus */ 8792e59129aSraghus nxge_destroy_param(nxgep); 8802e59129aSraghus 8812e59129aSraghus /* 8822e59129aSraghus * Tear down the kstat setup. 8832e59129aSraghus */ 8842e59129aSraghus nxge_destroy_kstats(nxgep); 8852e59129aSraghus 8862e59129aSraghus nxge_attach_fail4: 8872e59129aSraghus if (nxgep->nxge_hw_p) { 8882e59129aSraghus nxge_uninit_common_dev(nxgep); 8892e59129aSraghus nxgep->nxge_hw_p = NULL; 8902e59129aSraghus } 8912e59129aSraghus 8922e59129aSraghus nxge_attach_fail3: 8932e59129aSraghus /* 8942e59129aSraghus * Unmap the register setup. 8952e59129aSraghus */ 8962e59129aSraghus nxge_unmap_regs(nxgep); 8972e59129aSraghus 8982e59129aSraghus nxge_fm_fini(nxgep); 8992e59129aSraghus 9002e59129aSraghus nxge_attach_fail2: 9012e59129aSraghus ddi_soft_state_free(nxge_list, nxgep->instance); 9022e59129aSraghus 9032e59129aSraghus nxge_attach_fail1: 90456d930aeSspeer if (status != NXGE_OK) 90556d930aeSspeer status = (NXGE_ERROR | NXGE_DDI_FAILED); 90644961713Sgirish nxgep = NULL; 90744961713Sgirish 90844961713Sgirish nxge_attach_exit: 90944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_attach status = 0x%08x", 9104045d941Ssowmini status)); 91144961713Sgirish 91244961713Sgirish return (status); 91344961713Sgirish } 91444961713Sgirish 91544961713Sgirish static int 91644961713Sgirish nxge_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 91744961713Sgirish { 91844961713Sgirish int status = DDI_SUCCESS; 91944961713Sgirish int instance; 92044961713Sgirish p_nxge_t nxgep = NULL; 92144961713Sgirish 92244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_detach")); 92344961713Sgirish instance = ddi_get_instance(dip); 92444961713Sgirish nxgep = ddi_get_soft_state(nxge_list, instance); 92544961713Sgirish if (nxgep == NULL) { 92644961713Sgirish status = DDI_FAILURE; 92744961713Sgirish goto nxge_detach_exit; 92844961713Sgirish } 92944961713Sgirish 93044961713Sgirish switch (cmd) { 93144961713Sgirish case DDI_DETACH: 93244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_DETACH")); 93344961713Sgirish break; 93444961713Sgirish 93544961713Sgirish case DDI_PM_SUSPEND: 93644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_PM_SUSPEND")); 93744961713Sgirish nxgep->suspended = DDI_PM_SUSPEND; 93844961713Sgirish nxge_suspend(nxgep); 93944961713Sgirish break; 94044961713Sgirish 94144961713Sgirish case DDI_SUSPEND: 94244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_SUSPEND")); 94344961713Sgirish if (nxgep->suspended != DDI_PM_SUSPEND) { 94444961713Sgirish nxgep->suspended = DDI_SUSPEND; 94544961713Sgirish nxge_suspend(nxgep); 94644961713Sgirish } 94744961713Sgirish break; 94844961713Sgirish 94944961713Sgirish default: 95044961713Sgirish status = DDI_FAILURE; 95144961713Sgirish } 95244961713Sgirish 95344961713Sgirish if (cmd != DDI_DETACH) 95444961713Sgirish goto nxge_detach_exit; 95544961713Sgirish 95644961713Sgirish /* 95744961713Sgirish * Stop the xcvr polling. 95844961713Sgirish */ 95944961713Sgirish nxgep->suspended = cmd; 96044961713Sgirish 96144961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 96244961713Sgirish 963678453a8Sspeer if (isLDOMguest(nxgep)) { 964d7cf53fcSmisaki Miyashita if (nxgep->nxge_mac_state == NXGE_MAC_STARTED) 965d7cf53fcSmisaki Miyashita nxge_m_stop((void *)nxgep); 966678453a8Sspeer nxge_hio_unregister(nxgep); 967678453a8Sspeer } else if (nxgep->mach && (status = mac_unregister(nxgep->mach)) != 0) { 96844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 9694045d941Ssowmini "<== nxge_detach status = 0x%08X", status)); 97044961713Sgirish return (DDI_FAILURE); 97144961713Sgirish } 97244961713Sgirish 97344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 9744045d941Ssowmini "<== nxge_detach (mac_unregister) status = 0x%08X", status)); 97544961713Sgirish 97644961713Sgirish nxge_unattach(nxgep); 97744961713Sgirish nxgep = NULL; 97844961713Sgirish 97944961713Sgirish nxge_detach_exit: 98044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_detach status = 0x%08X", 9814045d941Ssowmini status)); 98244961713Sgirish 98344961713Sgirish return (status); 98444961713Sgirish } 98544961713Sgirish 98644961713Sgirish static void 98744961713Sgirish nxge_unattach(p_nxge_t nxgep) 98844961713Sgirish { 98944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_unattach")); 99044961713Sgirish 99144961713Sgirish if (nxgep == NULL || nxgep->dev_regs == NULL) { 99244961713Sgirish return; 99344961713Sgirish } 99444961713Sgirish 99598ecde52Stm nxgep->nxge_magic = 0; 99698ecde52Stm 99744961713Sgirish if (nxgep->nxge_timerid) { 99844961713Sgirish nxge_stop_timer(nxgep, nxgep->nxge_timerid); 99944961713Sgirish nxgep->nxge_timerid = 0; 100044961713Sgirish } 100144961713Sgirish 10026f157acbSml /* 10036f157acbSml * If this flag is set, it will affect the Neptune 10046f157acbSml * only. 10056f157acbSml */ 10066f157acbSml if ((nxgep->niu_type != N2_NIU) && nxge_peu_reset_enable) { 10076f157acbSml nxge_niu_peu_reset(nxgep); 10086f157acbSml } 10096f157acbSml 1010678453a8Sspeer #if defined(sun4v) 1011678453a8Sspeer if (isLDOMguest(nxgep)) { 1012d00f30bbSspeer (void) nxge_hio_vr_release(nxgep); 1013678453a8Sspeer } 1014678453a8Sspeer #endif 1015678453a8Sspeer 101653560810Ssbehera if (nxgep->nxge_hw_p) { 101753560810Ssbehera nxge_uninit_common_dev(nxgep); 101853560810Ssbehera nxgep->nxge_hw_p = NULL; 101953560810Ssbehera } 102053560810Ssbehera 102144961713Sgirish #if defined(sun4v) 102244961713Sgirish if (nxgep->niu_type == N2_NIU && nxgep->niu_hsvc_available == B_TRUE) { 102344961713Sgirish (void) hsvc_unregister(&nxgep->niu_hsvc); 102444961713Sgirish nxgep->niu_hsvc_available = B_FALSE; 102544961713Sgirish } 102644961713Sgirish #endif 102744961713Sgirish /* 102844961713Sgirish * Stop any further interrupts. 102944961713Sgirish */ 103044961713Sgirish nxge_remove_intrs(nxgep); 103144961713Sgirish 103244961713Sgirish /* remove soft interrups */ 103344961713Sgirish nxge_remove_soft_intrs(nxgep); 103444961713Sgirish 103544961713Sgirish /* 103644961713Sgirish * Stop the device and free resources. 103744961713Sgirish */ 1038678453a8Sspeer if (!isLDOMguest(nxgep)) { 1039678453a8Sspeer nxge_destroy_dev(nxgep); 1040678453a8Sspeer } 104144961713Sgirish 104244961713Sgirish /* 104344961713Sgirish * Tear down the ndd parameters setup. 104444961713Sgirish */ 104544961713Sgirish nxge_destroy_param(nxgep); 104644961713Sgirish 104744961713Sgirish /* 104844961713Sgirish * Tear down the kstat setup. 104944961713Sgirish */ 105044961713Sgirish nxge_destroy_kstats(nxgep); 105144961713Sgirish 105244961713Sgirish /* 105344961713Sgirish * Destroy all mutexes. 105444961713Sgirish */ 105544961713Sgirish nxge_destroy_mutexes(nxgep); 105644961713Sgirish 105744961713Sgirish /* 105844961713Sgirish * Remove the list of ndd parameters which 105944961713Sgirish * were setup during attach. 106044961713Sgirish */ 106144961713Sgirish if (nxgep->dip) { 106244961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL, 10634045d941Ssowmini " nxge_unattach: remove all properties")); 106444961713Sgirish 106544961713Sgirish (void) ddi_prop_remove_all(nxgep->dip); 106644961713Sgirish } 106744961713Sgirish 106844961713Sgirish #if NXGE_PROPERTY 106944961713Sgirish nxge_remove_hard_properties(nxgep); 107044961713Sgirish #endif 107144961713Sgirish 107244961713Sgirish /* 107344961713Sgirish * Unmap the register setup. 107444961713Sgirish */ 107544961713Sgirish nxge_unmap_regs(nxgep); 107644961713Sgirish 107744961713Sgirish nxge_fm_fini(nxgep); 107844961713Sgirish 107944961713Sgirish ddi_soft_state_free(nxge_list, nxgep->instance); 108044961713Sgirish 108144961713Sgirish NXGE_DEBUG_MSG((NULL, DDI_CTL, "<== nxge_unattach")); 108244961713Sgirish } 108344961713Sgirish 1084678453a8Sspeer #if defined(sun4v) 1085678453a8Sspeer int 10869d5b8bc5SMichael Speer nxge_hsvc_register(nxge_t *nxgep) 1087678453a8Sspeer { 1088678453a8Sspeer nxge_status_t status; 1089678453a8Sspeer 1090678453a8Sspeer if (nxgep->niu_type == N2_NIU) { 1091678453a8Sspeer nxgep->niu_hsvc_available = B_FALSE; 1092678453a8Sspeer bcopy(&niu_hsvc, &nxgep->niu_hsvc, sizeof (hsvc_info_t)); 1093678453a8Sspeer if ((status = hsvc_register(&nxgep->niu_hsvc, 1094678453a8Sspeer &nxgep->niu_min_ver)) != 0) { 1095678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1096678453a8Sspeer "nxge_attach: %s: cannot negotiate " 1097678453a8Sspeer "hypervisor services revision %d group: 0x%lx " 1098678453a8Sspeer "major: 0x%lx minor: 0x%lx errno: %d", 1099678453a8Sspeer niu_hsvc.hsvc_modname, niu_hsvc.hsvc_rev, 1100678453a8Sspeer niu_hsvc.hsvc_group, niu_hsvc.hsvc_major, 1101678453a8Sspeer niu_hsvc.hsvc_minor, status)); 1102678453a8Sspeer return (DDI_FAILURE); 1103678453a8Sspeer } 1104678453a8Sspeer nxgep->niu_hsvc_available = B_TRUE; 1105678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DDI_CTL, 11064045d941Ssowmini "NIU Hypervisor service enabled")); 1107678453a8Sspeer } 1108678453a8Sspeer 1109678453a8Sspeer return (DDI_SUCCESS); 1110678453a8Sspeer } 1111678453a8Sspeer #endif 1112678453a8Sspeer 111344961713Sgirish static char n2_siu_name[] = "niu"; 111444961713Sgirish 111544961713Sgirish static nxge_status_t 111644961713Sgirish nxge_map_regs(p_nxge_t nxgep) 111744961713Sgirish { 111844961713Sgirish int ddi_status = DDI_SUCCESS; 111944961713Sgirish p_dev_regs_t dev_regs; 112044961713Sgirish char buf[MAXPATHLEN + 1]; 112144961713Sgirish char *devname; 112244961713Sgirish #ifdef NXGE_DEBUG 112344961713Sgirish char *sysname; 112444961713Sgirish #endif 112544961713Sgirish off_t regsize; 112644961713Sgirish nxge_status_t status = NXGE_OK; 112714ea4bb7Ssd #if !defined(_BIG_ENDIAN) 112814ea4bb7Ssd off_t pci_offset; 112914ea4bb7Ssd uint16_t pcie_devctl; 113014ea4bb7Ssd #endif 113144961713Sgirish 1132678453a8Sspeer if (isLDOMguest(nxgep)) { 1133678453a8Sspeer return (nxge_guest_regs_map(nxgep)); 1134678453a8Sspeer } 1135678453a8Sspeer 113644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_map_regs")); 113744961713Sgirish nxgep->dev_regs = NULL; 113844961713Sgirish dev_regs = KMEM_ZALLOC(sizeof (dev_regs_t), KM_SLEEP); 113944961713Sgirish dev_regs->nxge_regh = NULL; 114044961713Sgirish dev_regs->nxge_pciregh = NULL; 114144961713Sgirish dev_regs->nxge_msix_regh = NULL; 114244961713Sgirish dev_regs->nxge_vir_regh = NULL; 114344961713Sgirish dev_regs->nxge_vir2_regh = NULL; 114459ac0c16Sdavemq nxgep->niu_type = NIU_TYPE_NONE; 114544961713Sgirish 114644961713Sgirish devname = ddi_pathname(nxgep->dip, buf); 114744961713Sgirish ASSERT(strlen(devname) > 0); 114844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 11494045d941Ssowmini "nxge_map_regs: pathname devname %s", devname)); 115044961713Sgirish 115100161856Syc /* 115200161856Syc * The driver is running on a N2-NIU system if devname is something 115300161856Syc * like "/niu@80/network@0" 115400161856Syc */ 115544961713Sgirish if (strstr(devname, n2_siu_name)) { 115644961713Sgirish /* N2/NIU */ 115744961713Sgirish nxgep->niu_type = N2_NIU; 115844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 11594045d941Ssowmini "nxge_map_regs: N2/NIU devname %s", devname)); 116044961713Sgirish /* get function number */ 116144961713Sgirish nxgep->function_num = 11624045d941Ssowmini (devname[strlen(devname) -1] == '1' ? 1 : 0); 116344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 11644045d941Ssowmini "nxge_map_regs: N2/NIU function number %d", 11654045d941Ssowmini nxgep->function_num)); 116644961713Sgirish } else { 116744961713Sgirish int *prop_val; 116844961713Sgirish uint_t prop_len; 116944961713Sgirish uint8_t func_num; 117044961713Sgirish 117144961713Sgirish if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 11724045d941Ssowmini 0, "reg", 11734045d941Ssowmini &prop_val, &prop_len) != DDI_PROP_SUCCESS) { 117444961713Sgirish NXGE_DEBUG_MSG((nxgep, VPD_CTL, 11754045d941Ssowmini "Reg property not found")); 117644961713Sgirish ddi_status = DDI_FAILURE; 117744961713Sgirish goto nxge_map_regs_fail0; 117844961713Sgirish 117944961713Sgirish } else { 118044961713Sgirish func_num = (prop_val[0] >> 8) & 0x7; 118144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 11824045d941Ssowmini "Reg property found: fun # %d", 11834045d941Ssowmini func_num)); 118444961713Sgirish nxgep->function_num = func_num; 1185678453a8Sspeer if (isLDOMguest(nxgep)) { 1186678453a8Sspeer nxgep->function_num /= 2; 1187678453a8Sspeer return (NXGE_OK); 1188678453a8Sspeer } 118944961713Sgirish ddi_prop_free(prop_val); 119044961713Sgirish } 119144961713Sgirish } 119244961713Sgirish 119344961713Sgirish switch (nxgep->niu_type) { 119444961713Sgirish default: 119544961713Sgirish (void) ddi_dev_regsize(nxgep->dip, 0, ®size); 119644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 11974045d941Ssowmini "nxge_map_regs: pci config size 0x%x", regsize)); 119844961713Sgirish 119944961713Sgirish ddi_status = ddi_regs_map_setup(nxgep->dip, 0, 12004045d941Ssowmini (caddr_t *)&(dev_regs->nxge_pciregp), 0, 0, 12014045d941Ssowmini &nxge_dev_reg_acc_attr, &dev_regs->nxge_pciregh); 120244961713Sgirish if (ddi_status != DDI_SUCCESS) { 120344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 12044045d941Ssowmini "ddi_map_regs, nxge bus config regs failed")); 120544961713Sgirish goto nxge_map_regs_fail0; 120644961713Sgirish } 120744961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 12084045d941Ssowmini "nxge_map_reg: PCI config addr 0x%0llx " 12094045d941Ssowmini " handle 0x%0llx", dev_regs->nxge_pciregp, 12104045d941Ssowmini dev_regs->nxge_pciregh)); 121144961713Sgirish /* 121244961713Sgirish * IMP IMP 121344961713Sgirish * workaround for bit swapping bug in HW 121444961713Sgirish * which ends up in no-snoop = yes 121544961713Sgirish * resulting, in DMA not synched properly 121644961713Sgirish */ 121744961713Sgirish #if !defined(_BIG_ENDIAN) 121814ea4bb7Ssd /* workarounds for x86 systems */ 121914ea4bb7Ssd pci_offset = 0x80 + PCIE_DEVCTL; 122014ea4bb7Ssd pcie_devctl = 0x0; 122114ea4bb7Ssd pcie_devctl &= PCIE_DEVCTL_ENABLE_NO_SNOOP; 122214ea4bb7Ssd pcie_devctl |= PCIE_DEVCTL_RO_EN; 122314ea4bb7Ssd pci_config_put16(dev_regs->nxge_pciregh, pci_offset, 12244045d941Ssowmini pcie_devctl); 122544961713Sgirish #endif 122614ea4bb7Ssd 122744961713Sgirish (void) ddi_dev_regsize(nxgep->dip, 1, ®size); 122844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 12294045d941Ssowmini "nxge_map_regs: pio size 0x%x", regsize)); 123044961713Sgirish /* set up the device mapped register */ 123144961713Sgirish ddi_status = ddi_regs_map_setup(nxgep->dip, 1, 12324045d941Ssowmini (caddr_t *)&(dev_regs->nxge_regp), 0, 0, 12334045d941Ssowmini &nxge_dev_reg_acc_attr, &dev_regs->nxge_regh); 123444961713Sgirish if (ddi_status != DDI_SUCCESS) { 123544961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 12364045d941Ssowmini "ddi_map_regs for Neptune global reg failed")); 123744961713Sgirish goto nxge_map_regs_fail1; 123844961713Sgirish } 123944961713Sgirish 124044961713Sgirish /* set up the msi/msi-x mapped register */ 124144961713Sgirish (void) ddi_dev_regsize(nxgep->dip, 2, ®size); 124244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 12434045d941Ssowmini "nxge_map_regs: msix size 0x%x", regsize)); 124444961713Sgirish ddi_status = ddi_regs_map_setup(nxgep->dip, 2, 12454045d941Ssowmini (caddr_t *)&(dev_regs->nxge_msix_regp), 0, 0, 12464045d941Ssowmini &nxge_dev_reg_acc_attr, &dev_regs->nxge_msix_regh); 124744961713Sgirish if (ddi_status != DDI_SUCCESS) { 124844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 12494045d941Ssowmini "ddi_map_regs for msi reg failed")); 125044961713Sgirish goto nxge_map_regs_fail2; 125144961713Sgirish } 125244961713Sgirish 125344961713Sgirish /* set up the vio region mapped register */ 125444961713Sgirish (void) ddi_dev_regsize(nxgep->dip, 3, ®size); 125544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 12564045d941Ssowmini "nxge_map_regs: vio size 0x%x", regsize)); 125744961713Sgirish ddi_status = ddi_regs_map_setup(nxgep->dip, 3, 12584045d941Ssowmini (caddr_t *)&(dev_regs->nxge_vir_regp), 0, 0, 12594045d941Ssowmini &nxge_dev_reg_acc_attr, &dev_regs->nxge_vir_regh); 126044961713Sgirish 126144961713Sgirish if (ddi_status != DDI_SUCCESS) { 126244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 12634045d941Ssowmini "ddi_map_regs for nxge vio reg failed")); 126444961713Sgirish goto nxge_map_regs_fail3; 126544961713Sgirish } 126644961713Sgirish nxgep->dev_regs = dev_regs; 126744961713Sgirish 126844961713Sgirish NPI_PCI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_pciregh); 126944961713Sgirish NPI_PCI_ADD_HANDLE_SET(nxgep, 12704045d941Ssowmini (npi_reg_ptr_t)dev_regs->nxge_pciregp); 127144961713Sgirish NPI_MSI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_msix_regh); 127244961713Sgirish NPI_MSI_ADD_HANDLE_SET(nxgep, 12734045d941Ssowmini (npi_reg_ptr_t)dev_regs->nxge_msix_regp); 127444961713Sgirish 127544961713Sgirish NPI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh); 127644961713Sgirish NPI_ADD_HANDLE_SET(nxgep, (npi_reg_ptr_t)dev_regs->nxge_regp); 127744961713Sgirish 127844961713Sgirish NPI_REG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh); 127944961713Sgirish NPI_REG_ADD_HANDLE_SET(nxgep, 12804045d941Ssowmini (npi_reg_ptr_t)dev_regs->nxge_regp); 128144961713Sgirish 128244961713Sgirish NPI_VREG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_vir_regh); 128344961713Sgirish NPI_VREG_ADD_HANDLE_SET(nxgep, 12844045d941Ssowmini (npi_reg_ptr_t)dev_regs->nxge_vir_regp); 128544961713Sgirish 128644961713Sgirish break; 128744961713Sgirish 128844961713Sgirish case N2_NIU: 128944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "ddi_map_regs, NIU")); 129044961713Sgirish /* 129144961713Sgirish * Set up the device mapped register (FWARC 2006/556) 129244961713Sgirish * (changed back to 1: reg starts at 1!) 129344961713Sgirish */ 129444961713Sgirish (void) ddi_dev_regsize(nxgep->dip, 1, ®size); 129544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 12964045d941Ssowmini "nxge_map_regs: dev size 0x%x", regsize)); 129744961713Sgirish ddi_status = ddi_regs_map_setup(nxgep->dip, 1, 12984045d941Ssowmini (caddr_t *)&(dev_regs->nxge_regp), 0, 0, 12994045d941Ssowmini &nxge_dev_reg_acc_attr, &dev_regs->nxge_regh); 130044961713Sgirish 130144961713Sgirish if (ddi_status != DDI_SUCCESS) { 130244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 13034045d941Ssowmini "ddi_map_regs for N2/NIU, global reg failed ")); 130444961713Sgirish goto nxge_map_regs_fail1; 130544961713Sgirish } 130644961713Sgirish 1307678453a8Sspeer /* set up the first vio region mapped register */ 130844961713Sgirish (void) ddi_dev_regsize(nxgep->dip, 2, ®size); 130944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 13104045d941Ssowmini "nxge_map_regs: vio (1) size 0x%x", regsize)); 131144961713Sgirish ddi_status = ddi_regs_map_setup(nxgep->dip, 2, 13124045d941Ssowmini (caddr_t *)&(dev_regs->nxge_vir_regp), 0, 0, 13134045d941Ssowmini &nxge_dev_reg_acc_attr, &dev_regs->nxge_vir_regh); 131444961713Sgirish 131544961713Sgirish if (ddi_status != DDI_SUCCESS) { 131644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 13174045d941Ssowmini "ddi_map_regs for nxge vio reg failed")); 131844961713Sgirish goto nxge_map_regs_fail2; 131944961713Sgirish } 1320678453a8Sspeer /* set up the second vio region mapped register */ 132144961713Sgirish (void) ddi_dev_regsize(nxgep->dip, 3, ®size); 132244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 13234045d941Ssowmini "nxge_map_regs: vio (3) size 0x%x", regsize)); 132444961713Sgirish ddi_status = ddi_regs_map_setup(nxgep->dip, 3, 13254045d941Ssowmini (caddr_t *)&(dev_regs->nxge_vir2_regp), 0, 0, 13264045d941Ssowmini &nxge_dev_reg_acc_attr, &dev_regs->nxge_vir2_regh); 132744961713Sgirish 132844961713Sgirish if (ddi_status != DDI_SUCCESS) { 132944961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 13304045d941Ssowmini "ddi_map_regs for nxge vio2 reg failed")); 133144961713Sgirish goto nxge_map_regs_fail3; 133244961713Sgirish } 133344961713Sgirish nxgep->dev_regs = dev_regs; 133444961713Sgirish 133544961713Sgirish NPI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh); 133644961713Sgirish NPI_ADD_HANDLE_SET(nxgep, (npi_reg_ptr_t)dev_regs->nxge_regp); 133744961713Sgirish 133844961713Sgirish NPI_REG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh); 133944961713Sgirish NPI_REG_ADD_HANDLE_SET(nxgep, 13404045d941Ssowmini (npi_reg_ptr_t)dev_regs->nxge_regp); 134144961713Sgirish 134244961713Sgirish NPI_VREG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_vir_regh); 134344961713Sgirish NPI_VREG_ADD_HANDLE_SET(nxgep, 13444045d941Ssowmini (npi_reg_ptr_t)dev_regs->nxge_vir_regp); 134544961713Sgirish 134644961713Sgirish NPI_V2REG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_vir2_regh); 134744961713Sgirish NPI_V2REG_ADD_HANDLE_SET(nxgep, 13484045d941Ssowmini (npi_reg_ptr_t)dev_regs->nxge_vir2_regp); 134944961713Sgirish 135044961713Sgirish break; 135144961713Sgirish } 135244961713Sgirish 135344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "nxge_map_reg: hardware addr 0x%0llx " 13544045d941Ssowmini " handle 0x%0llx", dev_regs->nxge_regp, dev_regs->nxge_regh)); 135544961713Sgirish 135644961713Sgirish goto nxge_map_regs_exit; 135744961713Sgirish nxge_map_regs_fail3: 135844961713Sgirish if (dev_regs->nxge_msix_regh) { 135944961713Sgirish ddi_regs_map_free(&dev_regs->nxge_msix_regh); 136044961713Sgirish } 136144961713Sgirish if (dev_regs->nxge_vir_regh) { 136244961713Sgirish ddi_regs_map_free(&dev_regs->nxge_regh); 136344961713Sgirish } 136444961713Sgirish nxge_map_regs_fail2: 136544961713Sgirish if (dev_regs->nxge_regh) { 136644961713Sgirish ddi_regs_map_free(&dev_regs->nxge_regh); 136744961713Sgirish } 136844961713Sgirish nxge_map_regs_fail1: 136944961713Sgirish if (dev_regs->nxge_pciregh) { 137044961713Sgirish ddi_regs_map_free(&dev_regs->nxge_pciregh); 137144961713Sgirish } 137244961713Sgirish nxge_map_regs_fail0: 137344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "Freeing register set memory")); 137444961713Sgirish kmem_free(dev_regs, sizeof (dev_regs_t)); 137544961713Sgirish 137644961713Sgirish nxge_map_regs_exit: 137744961713Sgirish if (ddi_status != DDI_SUCCESS) 137844961713Sgirish status |= (NXGE_ERROR | NXGE_DDI_FAILED); 137944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_map_regs")); 138044961713Sgirish return (status); 138144961713Sgirish } 138244961713Sgirish 138344961713Sgirish static void 138444961713Sgirish nxge_unmap_regs(p_nxge_t nxgep) 138544961713Sgirish { 138644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_unmap_regs")); 1387678453a8Sspeer 1388678453a8Sspeer if (isLDOMguest(nxgep)) { 1389678453a8Sspeer nxge_guest_regs_map_free(nxgep); 1390678453a8Sspeer return; 1391678453a8Sspeer } 1392678453a8Sspeer 139344961713Sgirish if (nxgep->dev_regs) { 139444961713Sgirish if (nxgep->dev_regs->nxge_pciregh) { 139544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 13964045d941Ssowmini "==> nxge_unmap_regs: bus")); 139744961713Sgirish ddi_regs_map_free(&nxgep->dev_regs->nxge_pciregh); 139844961713Sgirish nxgep->dev_regs->nxge_pciregh = NULL; 139944961713Sgirish } 140044961713Sgirish if (nxgep->dev_regs->nxge_regh) { 140144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 14024045d941Ssowmini "==> nxge_unmap_regs: device registers")); 140344961713Sgirish ddi_regs_map_free(&nxgep->dev_regs->nxge_regh); 140444961713Sgirish nxgep->dev_regs->nxge_regh = NULL; 140544961713Sgirish } 140644961713Sgirish if (nxgep->dev_regs->nxge_msix_regh) { 140744961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 14084045d941Ssowmini "==> nxge_unmap_regs: device interrupts")); 140944961713Sgirish ddi_regs_map_free(&nxgep->dev_regs->nxge_msix_regh); 141044961713Sgirish nxgep->dev_regs->nxge_msix_regh = NULL; 141144961713Sgirish } 141244961713Sgirish if (nxgep->dev_regs->nxge_vir_regh) { 141344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 14144045d941Ssowmini "==> nxge_unmap_regs: vio region")); 141544961713Sgirish ddi_regs_map_free(&nxgep->dev_regs->nxge_vir_regh); 141644961713Sgirish nxgep->dev_regs->nxge_vir_regh = NULL; 141744961713Sgirish } 141844961713Sgirish if (nxgep->dev_regs->nxge_vir2_regh) { 141944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 14204045d941Ssowmini "==> nxge_unmap_regs: vio2 region")); 142144961713Sgirish ddi_regs_map_free(&nxgep->dev_regs->nxge_vir2_regh); 142244961713Sgirish nxgep->dev_regs->nxge_vir2_regh = NULL; 142344961713Sgirish } 142444961713Sgirish 142544961713Sgirish kmem_free(nxgep->dev_regs, sizeof (dev_regs_t)); 142644961713Sgirish nxgep->dev_regs = NULL; 142744961713Sgirish } 142844961713Sgirish 142944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_unmap_regs")); 143044961713Sgirish } 143144961713Sgirish 143244961713Sgirish static nxge_status_t 143344961713Sgirish nxge_setup_mutexes(p_nxge_t nxgep) 143444961713Sgirish { 143544961713Sgirish int ddi_status = DDI_SUCCESS; 143644961713Sgirish nxge_status_t status = NXGE_OK; 143744961713Sgirish nxge_classify_t *classify_ptr; 143844961713Sgirish int partition; 143944961713Sgirish 144044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_setup_mutexes")); 144144961713Sgirish 144244961713Sgirish /* 144344961713Sgirish * Get the interrupt cookie so the mutexes can be 144458324dfcSspeer * Initialized. 144544961713Sgirish */ 1446678453a8Sspeer if (isLDOMguest(nxgep)) { 1447678453a8Sspeer nxgep->interrupt_cookie = 0; 1448678453a8Sspeer } else { 1449678453a8Sspeer ddi_status = ddi_get_iblock_cookie(nxgep->dip, 0, 1450678453a8Sspeer &nxgep->interrupt_cookie); 1451678453a8Sspeer 1452678453a8Sspeer if (ddi_status != DDI_SUCCESS) { 1453678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1454678453a8Sspeer "<== nxge_setup_mutexes: failed 0x%x", 1455678453a8Sspeer ddi_status)); 1456678453a8Sspeer goto nxge_setup_mutexes_exit; 1457678453a8Sspeer } 145844961713Sgirish } 145944961713Sgirish 146098ecde52Stm cv_init(&nxgep->poll_cv, NULL, CV_DRIVER, NULL); 146198ecde52Stm MUTEX_INIT(&nxgep->poll_lock, NULL, 146298ecde52Stm MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 146398ecde52Stm 146444961713Sgirish /* 146598ecde52Stm * Initialize mutexes for this device. 146644961713Sgirish */ 146744961713Sgirish MUTEX_INIT(nxgep->genlock, NULL, 14684045d941Ssowmini MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 146944961713Sgirish MUTEX_INIT(&nxgep->ouraddr_lock, NULL, 14704045d941Ssowmini MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 147144961713Sgirish MUTEX_INIT(&nxgep->mif_lock, NULL, 14724045d941Ssowmini MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1473678453a8Sspeer MUTEX_INIT(&nxgep->group_lock, NULL, 1474678453a8Sspeer MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 147544961713Sgirish RW_INIT(&nxgep->filter_lock, NULL, 14764045d941Ssowmini RW_DRIVER, (void *)nxgep->interrupt_cookie); 147744961713Sgirish 147844961713Sgirish classify_ptr = &nxgep->classifier; 147944961713Sgirish /* 148044961713Sgirish * FFLP Mutexes are never used in interrupt context 148144961713Sgirish * as fflp operation can take very long time to 148244961713Sgirish * complete and hence not suitable to invoke from interrupt 148344961713Sgirish * handlers. 148444961713Sgirish */ 148544961713Sgirish MUTEX_INIT(&classify_ptr->tcam_lock, NULL, 148659ac0c16Sdavemq NXGE_MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 14872e59129aSraghus if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) { 148844961713Sgirish MUTEX_INIT(&classify_ptr->fcram_lock, NULL, 148959ac0c16Sdavemq NXGE_MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 149044961713Sgirish for (partition = 0; partition < MAX_PARTITION; partition++) { 149144961713Sgirish MUTEX_INIT(&classify_ptr->hash_lock[partition], NULL, 149244961713Sgirish NXGE_MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 149344961713Sgirish } 149444961713Sgirish } 149544961713Sgirish 149644961713Sgirish nxge_setup_mutexes_exit: 149744961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 149859ac0c16Sdavemq "<== nxge_setup_mutexes status = %x", status)); 149944961713Sgirish 150044961713Sgirish if (ddi_status != DDI_SUCCESS) 150144961713Sgirish status |= (NXGE_ERROR | NXGE_DDI_FAILED); 150244961713Sgirish 150344961713Sgirish return (status); 150444961713Sgirish } 150544961713Sgirish 150644961713Sgirish static void 150744961713Sgirish nxge_destroy_mutexes(p_nxge_t nxgep) 150844961713Sgirish { 150944961713Sgirish int partition; 151044961713Sgirish nxge_classify_t *classify_ptr; 151144961713Sgirish 151244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_mutexes")); 151344961713Sgirish RW_DESTROY(&nxgep->filter_lock); 1514678453a8Sspeer MUTEX_DESTROY(&nxgep->group_lock); 151544961713Sgirish MUTEX_DESTROY(&nxgep->mif_lock); 151644961713Sgirish MUTEX_DESTROY(&nxgep->ouraddr_lock); 151744961713Sgirish MUTEX_DESTROY(nxgep->genlock); 151844961713Sgirish 151944961713Sgirish classify_ptr = &nxgep->classifier; 152044961713Sgirish MUTEX_DESTROY(&classify_ptr->tcam_lock); 152144961713Sgirish 152298ecde52Stm /* Destroy all polling resources. */ 152398ecde52Stm MUTEX_DESTROY(&nxgep->poll_lock); 152498ecde52Stm cv_destroy(&nxgep->poll_cv); 152598ecde52Stm 152698ecde52Stm /* free data structures, based on HW type */ 15272e59129aSraghus if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) { 152844961713Sgirish MUTEX_DESTROY(&classify_ptr->fcram_lock); 152944961713Sgirish for (partition = 0; partition < MAX_PARTITION; partition++) { 153044961713Sgirish MUTEX_DESTROY(&classify_ptr->hash_lock[partition]); 153144961713Sgirish } 153244961713Sgirish } 153344961713Sgirish 153444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_mutexes")); 153544961713Sgirish } 153644961713Sgirish 153744961713Sgirish nxge_status_t 153844961713Sgirish nxge_init(p_nxge_t nxgep) 153944961713Sgirish { 1540678453a8Sspeer nxge_status_t status = NXGE_OK; 154144961713Sgirish 154244961713Sgirish NXGE_DEBUG_MSG((nxgep, STR_CTL, "==> nxge_init")); 154344961713Sgirish 154414ea4bb7Ssd if (nxgep->drv_state & STATE_HW_INITIALIZED) { 154514ea4bb7Ssd return (status); 154614ea4bb7Ssd } 154714ea4bb7Ssd 154844961713Sgirish /* 154944961713Sgirish * Allocate system memory for the receive/transmit buffer blocks 155044961713Sgirish * and receive/transmit descriptor rings. 155144961713Sgirish */ 155244961713Sgirish status = nxge_alloc_mem_pool(nxgep); 155344961713Sgirish if (status != NXGE_OK) { 155444961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "alloc mem failed\n")); 155544961713Sgirish goto nxge_init_fail1; 155644961713Sgirish } 155744961713Sgirish 1558678453a8Sspeer if (!isLDOMguest(nxgep)) { 1559678453a8Sspeer /* 1560678453a8Sspeer * Initialize and enable the TXC registers. 1561678453a8Sspeer * (Globally enable the Tx controller, 1562678453a8Sspeer * enable the port, configure the dma channel bitmap, 1563678453a8Sspeer * configure the max burst size). 1564678453a8Sspeer */ 1565678453a8Sspeer status = nxge_txc_init(nxgep); 1566678453a8Sspeer if (status != NXGE_OK) { 1567678453a8Sspeer NXGE_ERROR_MSG((nxgep, 1568678453a8Sspeer NXGE_ERR_CTL, "init txc failed\n")); 1569678453a8Sspeer goto nxge_init_fail2; 1570678453a8Sspeer } 157144961713Sgirish } 157244961713Sgirish 157344961713Sgirish /* 157444961713Sgirish * Initialize and enable TXDMA channels. 157544961713Sgirish */ 157644961713Sgirish status = nxge_init_txdma_channels(nxgep); 157744961713Sgirish if (status != NXGE_OK) { 157844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init txdma failed\n")); 157944961713Sgirish goto nxge_init_fail3; 158044961713Sgirish } 158144961713Sgirish 158244961713Sgirish /* 158344961713Sgirish * Initialize and enable RXDMA channels. 158444961713Sgirish */ 158544961713Sgirish status = nxge_init_rxdma_channels(nxgep); 158644961713Sgirish if (status != NXGE_OK) { 158744961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init rxdma failed\n")); 158844961713Sgirish goto nxge_init_fail4; 158944961713Sgirish } 159044961713Sgirish 1591678453a8Sspeer /* 1592678453a8Sspeer * The guest domain is now done. 1593678453a8Sspeer */ 1594678453a8Sspeer if (isLDOMguest(nxgep)) { 1595678453a8Sspeer nxgep->drv_state |= STATE_HW_INITIALIZED; 1596678453a8Sspeer goto nxge_init_exit; 1597678453a8Sspeer } 1598678453a8Sspeer 159944961713Sgirish /* 160044961713Sgirish * Initialize TCAM and FCRAM (Neptune). 160144961713Sgirish */ 160244961713Sgirish status = nxge_classify_init(nxgep); 160344961713Sgirish if (status != NXGE_OK) { 160444961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init classify failed\n")); 160544961713Sgirish goto nxge_init_fail5; 160644961713Sgirish } 160744961713Sgirish 160844961713Sgirish /* 160944961713Sgirish * Initialize ZCP 161044961713Sgirish */ 161144961713Sgirish status = nxge_zcp_init(nxgep); 161244961713Sgirish if (status != NXGE_OK) { 161344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init ZCP failed\n")); 161444961713Sgirish goto nxge_init_fail5; 161544961713Sgirish } 161644961713Sgirish 161744961713Sgirish /* 161844961713Sgirish * Initialize IPP. 161944961713Sgirish */ 162044961713Sgirish status = nxge_ipp_init(nxgep); 162144961713Sgirish if (status != NXGE_OK) { 162244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init IPP failed\n")); 162344961713Sgirish goto nxge_init_fail5; 162444961713Sgirish } 162544961713Sgirish 162644961713Sgirish /* 162744961713Sgirish * Initialize the MAC block. 162844961713Sgirish */ 162944961713Sgirish status = nxge_mac_init(nxgep); 163044961713Sgirish if (status != NXGE_OK) { 163144961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init MAC failed\n")); 163244961713Sgirish goto nxge_init_fail5; 163344961713Sgirish } 163444961713Sgirish 1635678453a8Sspeer nxge_intrs_enable(nxgep); /* XXX What changes do I need to make here? */ 163644961713Sgirish 163744961713Sgirish /* 163844961713Sgirish * Enable hardware interrupts. 163944961713Sgirish */ 164044961713Sgirish nxge_intr_hw_enable(nxgep); 164144961713Sgirish nxgep->drv_state |= STATE_HW_INITIALIZED; 164244961713Sgirish 164344961713Sgirish goto nxge_init_exit; 164444961713Sgirish 164544961713Sgirish nxge_init_fail5: 164644961713Sgirish nxge_uninit_rxdma_channels(nxgep); 164744961713Sgirish nxge_init_fail4: 164844961713Sgirish nxge_uninit_txdma_channels(nxgep); 164944961713Sgirish nxge_init_fail3: 1650678453a8Sspeer if (!isLDOMguest(nxgep)) { 1651678453a8Sspeer (void) nxge_txc_uninit(nxgep); 1652678453a8Sspeer } 165344961713Sgirish nxge_init_fail2: 165444961713Sgirish nxge_free_mem_pool(nxgep); 165544961713Sgirish nxge_init_fail1: 165644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 16574045d941Ssowmini "<== nxge_init status (failed) = 0x%08x", status)); 165844961713Sgirish return (status); 165944961713Sgirish 166044961713Sgirish nxge_init_exit: 166144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_init status = 0x%08x", 16624045d941Ssowmini status)); 166344961713Sgirish return (status); 166444961713Sgirish } 166544961713Sgirish 166644961713Sgirish 166744961713Sgirish timeout_id_t 166844961713Sgirish nxge_start_timer(p_nxge_t nxgep, fptrv_t func, int msec) 166944961713Sgirish { 16704045d941Ssowmini if ((nxgep->suspended == 0) || (nxgep->suspended == DDI_RESUME)) { 167144961713Sgirish return (timeout(func, (caddr_t)nxgep, 16724045d941Ssowmini drv_usectohz(1000 * msec))); 167344961713Sgirish } 167444961713Sgirish return (NULL); 167544961713Sgirish } 167644961713Sgirish 167744961713Sgirish /*ARGSUSED*/ 167844961713Sgirish void 167944961713Sgirish nxge_stop_timer(p_nxge_t nxgep, timeout_id_t timerid) 168044961713Sgirish { 168144961713Sgirish if (timerid) { 168244961713Sgirish (void) untimeout(timerid); 168344961713Sgirish } 168444961713Sgirish } 168544961713Sgirish 168644961713Sgirish void 168744961713Sgirish nxge_uninit(p_nxge_t nxgep) 168844961713Sgirish { 168944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_uninit")); 169044961713Sgirish 169144961713Sgirish if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 169244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 16934045d941Ssowmini "==> nxge_uninit: not initialized")); 169444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 16954045d941Ssowmini "<== nxge_uninit")); 169644961713Sgirish return; 169744961713Sgirish } 169844961713Sgirish 169944961713Sgirish /* stop timer */ 170044961713Sgirish if (nxgep->nxge_timerid) { 170144961713Sgirish nxge_stop_timer(nxgep, nxgep->nxge_timerid); 170244961713Sgirish nxgep->nxge_timerid = 0; 170344961713Sgirish } 170444961713Sgirish 170544961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 170644961713Sgirish (void) nxge_intr_hw_disable(nxgep); 170744961713Sgirish 170844961713Sgirish /* 170944961713Sgirish * Reset the receive MAC side. 171044961713Sgirish */ 171144961713Sgirish (void) nxge_rx_mac_disable(nxgep); 171244961713Sgirish 171344961713Sgirish /* Disable and soft reset the IPP */ 1714678453a8Sspeer if (!isLDOMguest(nxgep)) 1715678453a8Sspeer (void) nxge_ipp_disable(nxgep); 171644961713Sgirish 1717a3c5bd6dSspeer /* Free classification resources */ 1718a3c5bd6dSspeer (void) nxge_classify_uninit(nxgep); 1719a3c5bd6dSspeer 172044961713Sgirish /* 172144961713Sgirish * Reset the transmit/receive DMA side. 172244961713Sgirish */ 172344961713Sgirish (void) nxge_txdma_hw_mode(nxgep, NXGE_DMA_STOP); 172444961713Sgirish (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_STOP); 172544961713Sgirish 172644961713Sgirish nxge_uninit_txdma_channels(nxgep); 172744961713Sgirish nxge_uninit_rxdma_channels(nxgep); 172844961713Sgirish 172944961713Sgirish /* 173044961713Sgirish * Reset the transmit MAC side. 173144961713Sgirish */ 173244961713Sgirish (void) nxge_tx_mac_disable(nxgep); 173344961713Sgirish 173444961713Sgirish nxge_free_mem_pool(nxgep); 173544961713Sgirish 17366f157acbSml /* 17376f157acbSml * Start the timer if the reset flag is not set. 17386f157acbSml * If this reset flag is set, the link monitor 17396f157acbSml * will not be started in order to stop furthur bus 17406f157acbSml * activities coming from this interface. 17416f157acbSml * The driver will start the monitor function 17426f157acbSml * if the interface was initialized again later. 17436f157acbSml */ 17446f157acbSml if (!nxge_peu_reset_enable) { 17456f157acbSml (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 17466f157acbSml } 174744961713Sgirish 174844961713Sgirish nxgep->drv_state &= ~STATE_HW_INITIALIZED; 174944961713Sgirish 175044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_uninit: " 17514045d941Ssowmini "nxge_mblks_pending %d", nxge_mblks_pending)); 175244961713Sgirish } 175344961713Sgirish 175444961713Sgirish void 175544961713Sgirish nxge_get64(p_nxge_t nxgep, p_mblk_t mp) 175644961713Sgirish { 1757adfcba55Sjoycey #if defined(__i386) 1758adfcba55Sjoycey size_t reg; 1759adfcba55Sjoycey #else 176044961713Sgirish uint64_t reg; 1761adfcba55Sjoycey #endif 176244961713Sgirish uint64_t regdata; 176344961713Sgirish int i, retry; 176444961713Sgirish 176544961713Sgirish bcopy((char *)mp->b_rptr, (char *)®, sizeof (uint64_t)); 176644961713Sgirish regdata = 0; 176744961713Sgirish retry = 1; 176844961713Sgirish 176944961713Sgirish for (i = 0; i < retry; i++) { 177044961713Sgirish NXGE_REG_RD64(nxgep->npi_handle, reg, ®data); 177144961713Sgirish } 177244961713Sgirish bcopy((char *)®data, (char *)mp->b_rptr, sizeof (uint64_t)); 177344961713Sgirish } 177444961713Sgirish 177544961713Sgirish void 177644961713Sgirish nxge_put64(p_nxge_t nxgep, p_mblk_t mp) 177744961713Sgirish { 1778adfcba55Sjoycey #if defined(__i386) 1779adfcba55Sjoycey size_t reg; 1780adfcba55Sjoycey #else 178144961713Sgirish uint64_t reg; 1782adfcba55Sjoycey #endif 178344961713Sgirish uint64_t buf[2]; 178444961713Sgirish 178544961713Sgirish bcopy((char *)mp->b_rptr, (char *)&buf[0], 2 * sizeof (uint64_t)); 17867a8b1321Sjoycey #if defined(__i386) 17877a8b1321Sjoycey reg = (size_t)buf[0]; 17887a8b1321Sjoycey #else 178944961713Sgirish reg = buf[0]; 17907a8b1321Sjoycey #endif 179144961713Sgirish 179244961713Sgirish NXGE_NPI_PIO_WRITE64(nxgep->npi_handle, reg, buf[1]); 179344961713Sgirish } 179444961713Sgirish 179544961713Sgirish 179644961713Sgirish nxge_os_mutex_t nxgedebuglock; 179744961713Sgirish int nxge_debug_init = 0; 179844961713Sgirish 179944961713Sgirish /*ARGSUSED*/ 180044961713Sgirish /*VARARGS*/ 180144961713Sgirish void 180244961713Sgirish nxge_debug_msg(p_nxge_t nxgep, uint64_t level, char *fmt, ...) 180344961713Sgirish { 180444961713Sgirish char msg_buffer[1048]; 180544961713Sgirish char prefix_buffer[32]; 180644961713Sgirish int instance; 180744961713Sgirish uint64_t debug_level; 180844961713Sgirish int cmn_level = CE_CONT; 180944961713Sgirish va_list ap; 181044961713Sgirish 1811678453a8Sspeer if (nxgep && nxgep->nxge_debug_level != nxge_debug_level) { 1812678453a8Sspeer /* In case a developer has changed nxge_debug_level. */ 1813678453a8Sspeer if (nxgep->nxge_debug_level != nxge_debug_level) 1814678453a8Sspeer nxgep->nxge_debug_level = nxge_debug_level; 1815678453a8Sspeer } 1816678453a8Sspeer 181744961713Sgirish debug_level = (nxgep == NULL) ? nxge_debug_level : 18184045d941Ssowmini nxgep->nxge_debug_level; 181944961713Sgirish 182044961713Sgirish if ((level & debug_level) || 18214045d941Ssowmini (level == NXGE_NOTE) || 18224045d941Ssowmini (level == NXGE_ERR_CTL)) { 182344961713Sgirish /* do the msg processing */ 182444961713Sgirish if (nxge_debug_init == 0) { 182544961713Sgirish MUTEX_INIT(&nxgedebuglock, NULL, MUTEX_DRIVER, NULL); 182644961713Sgirish nxge_debug_init = 1; 182744961713Sgirish } 182844961713Sgirish 182944961713Sgirish MUTEX_ENTER(&nxgedebuglock); 183044961713Sgirish 183144961713Sgirish if ((level & NXGE_NOTE)) { 183244961713Sgirish cmn_level = CE_NOTE; 183344961713Sgirish } 183444961713Sgirish 183544961713Sgirish if (level & NXGE_ERR_CTL) { 183644961713Sgirish cmn_level = CE_WARN; 183744961713Sgirish } 183844961713Sgirish 183944961713Sgirish va_start(ap, fmt); 184044961713Sgirish (void) vsprintf(msg_buffer, fmt, ap); 184144961713Sgirish va_end(ap); 184244961713Sgirish if (nxgep == NULL) { 184344961713Sgirish instance = -1; 184444961713Sgirish (void) sprintf(prefix_buffer, "%s :", "nxge"); 184544961713Sgirish } else { 184644961713Sgirish instance = nxgep->instance; 184744961713Sgirish (void) sprintf(prefix_buffer, 18484045d941Ssowmini "%s%d :", "nxge", instance); 184944961713Sgirish } 185044961713Sgirish 185144961713Sgirish MUTEX_EXIT(&nxgedebuglock); 185244961713Sgirish cmn_err(cmn_level, "!%s %s\n", 18534045d941Ssowmini prefix_buffer, msg_buffer); 185444961713Sgirish 185544961713Sgirish } 185644961713Sgirish } 185744961713Sgirish 185844961713Sgirish char * 185944961713Sgirish nxge_dump_packet(char *addr, int size) 186044961713Sgirish { 186144961713Sgirish uchar_t *ap = (uchar_t *)addr; 186244961713Sgirish int i; 186344961713Sgirish static char etherbuf[1024]; 186444961713Sgirish char *cp = etherbuf; 186544961713Sgirish char digits[] = "0123456789abcdef"; 186644961713Sgirish 186744961713Sgirish if (!size) 186844961713Sgirish size = 60; 186944961713Sgirish 187044961713Sgirish if (size > MAX_DUMP_SZ) { 187144961713Sgirish /* Dump the leading bytes */ 187244961713Sgirish for (i = 0; i < MAX_DUMP_SZ/2; i++) { 187344961713Sgirish if (*ap > 0x0f) 187444961713Sgirish *cp++ = digits[*ap >> 4]; 187544961713Sgirish *cp++ = digits[*ap++ & 0xf]; 187644961713Sgirish *cp++ = ':'; 187744961713Sgirish } 187844961713Sgirish for (i = 0; i < 20; i++) 187944961713Sgirish *cp++ = '.'; 188044961713Sgirish /* Dump the last MAX_DUMP_SZ/2 bytes */ 188144961713Sgirish ap = (uchar_t *)(addr + (size - MAX_DUMP_SZ/2)); 188244961713Sgirish for (i = 0; i < MAX_DUMP_SZ/2; i++) { 188344961713Sgirish if (*ap > 0x0f) 188444961713Sgirish *cp++ = digits[*ap >> 4]; 188544961713Sgirish *cp++ = digits[*ap++ & 0xf]; 188644961713Sgirish *cp++ = ':'; 188744961713Sgirish } 188844961713Sgirish } else { 188944961713Sgirish for (i = 0; i < size; i++) { 189044961713Sgirish if (*ap > 0x0f) 189144961713Sgirish *cp++ = digits[*ap >> 4]; 189244961713Sgirish *cp++ = digits[*ap++ & 0xf]; 189344961713Sgirish *cp++ = ':'; 189444961713Sgirish } 189544961713Sgirish } 189644961713Sgirish *--cp = 0; 189744961713Sgirish return (etherbuf); 189844961713Sgirish } 189944961713Sgirish 190044961713Sgirish #ifdef NXGE_DEBUG 190144961713Sgirish static void 190244961713Sgirish nxge_test_map_regs(p_nxge_t nxgep) 190344961713Sgirish { 190444961713Sgirish ddi_acc_handle_t cfg_handle; 190544961713Sgirish p_pci_cfg_t cfg_ptr; 190644961713Sgirish ddi_acc_handle_t dev_handle; 190744961713Sgirish char *dev_ptr; 190844961713Sgirish ddi_acc_handle_t pci_config_handle; 190944961713Sgirish uint32_t regval; 191044961713Sgirish int i; 191144961713Sgirish 191244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_test_map_regs")); 191344961713Sgirish 191444961713Sgirish dev_handle = nxgep->dev_regs->nxge_regh; 191544961713Sgirish dev_ptr = (char *)nxgep->dev_regs->nxge_regp; 191644961713Sgirish 19172e59129aSraghus if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) { 191844961713Sgirish cfg_handle = nxgep->dev_regs->nxge_pciregh; 191944961713Sgirish cfg_ptr = (void *)nxgep->dev_regs->nxge_pciregp; 192044961713Sgirish 192144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 192259ac0c16Sdavemq "Neptune PCI regp cfg_ptr 0x%llx", (char *)cfg_ptr)); 192344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 192459ac0c16Sdavemq "Neptune PCI cfg_ptr vendor id ptr 0x%llx", 192559ac0c16Sdavemq &cfg_ptr->vendorid)); 192644961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 192759ac0c16Sdavemq "\tvendorid 0x%x devid 0x%x", 192859ac0c16Sdavemq NXGE_PIO_READ16(cfg_handle, &cfg_ptr->vendorid, 0), 192959ac0c16Sdavemq NXGE_PIO_READ16(cfg_handle, &cfg_ptr->devid, 0))); 193044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 193159ac0c16Sdavemq "PCI BAR: base 0x%x base14 0x%x base 18 0x%x " 193259ac0c16Sdavemq "bar1c 0x%x", 193359ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base, 0), 193459ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base14, 0), 193559ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base18, 0), 193659ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base1c, 0))); 193744961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 193859ac0c16Sdavemq "\nNeptune PCI BAR: base20 0x%x base24 0x%x " 193959ac0c16Sdavemq "base 28 0x%x bar2c 0x%x\n", 194059ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base20, 0), 194159ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base24, 0), 194259ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base28, 0), 194359ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base2c, 0))); 194444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 194559ac0c16Sdavemq "\nNeptune PCI BAR: base30 0x%x\n", 194659ac0c16Sdavemq NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base30, 0))); 194744961713Sgirish 194844961713Sgirish cfg_handle = nxgep->dev_regs->nxge_pciregh; 194944961713Sgirish cfg_ptr = (void *)nxgep->dev_regs->nxge_pciregp; 195044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 195159ac0c16Sdavemq "first 0x%llx second 0x%llx third 0x%llx " 195259ac0c16Sdavemq "last 0x%llx ", 195359ac0c16Sdavemq NXGE_PIO_READ64(dev_handle, 195459ac0c16Sdavemq (uint64_t *)(dev_ptr + 0), 0), 195559ac0c16Sdavemq NXGE_PIO_READ64(dev_handle, 195659ac0c16Sdavemq (uint64_t *)(dev_ptr + 8), 0), 195759ac0c16Sdavemq NXGE_PIO_READ64(dev_handle, 195859ac0c16Sdavemq (uint64_t *)(dev_ptr + 16), 0), 195959ac0c16Sdavemq NXGE_PIO_READ64(cfg_handle, 196059ac0c16Sdavemq (uint64_t *)(dev_ptr + 24), 0))); 196144961713Sgirish } 196244961713Sgirish } 196344961713Sgirish 196444961713Sgirish #endif 196544961713Sgirish 196644961713Sgirish static void 196744961713Sgirish nxge_suspend(p_nxge_t nxgep) 196844961713Sgirish { 196944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_suspend")); 197044961713Sgirish 197144961713Sgirish nxge_intrs_disable(nxgep); 197244961713Sgirish nxge_destroy_dev(nxgep); 197344961713Sgirish 197444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_suspend")); 197544961713Sgirish } 197644961713Sgirish 197744961713Sgirish static nxge_status_t 197844961713Sgirish nxge_resume(p_nxge_t nxgep) 197944961713Sgirish { 198044961713Sgirish nxge_status_t status = NXGE_OK; 198144961713Sgirish 198244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_resume")); 198344961713Sgirish 198491c98b31Sjoycey nxgep->suspended = DDI_RESUME; 198591c98b31Sjoycey (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 198691c98b31Sjoycey (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_START); 198791c98b31Sjoycey (void) nxge_txdma_hw_mode(nxgep, NXGE_DMA_START); 198891c98b31Sjoycey (void) nxge_rx_mac_enable(nxgep); 198991c98b31Sjoycey (void) nxge_tx_mac_enable(nxgep); 199091c98b31Sjoycey nxge_intrs_enable(nxgep); 199144961713Sgirish nxgep->suspended = 0; 199244961713Sgirish 199344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 19944045d941Ssowmini "<== nxge_resume status = 0x%x", status)); 199544961713Sgirish return (status); 199644961713Sgirish } 199744961713Sgirish 199844961713Sgirish static nxge_status_t 199944961713Sgirish nxge_setup_dev(p_nxge_t nxgep) 200044961713Sgirish { 200144961713Sgirish nxge_status_t status = NXGE_OK; 200244961713Sgirish 200344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_setup_dev port %d", 200459ac0c16Sdavemq nxgep->mac.portnum)); 200544961713Sgirish 200644961713Sgirish status = nxge_link_init(nxgep); 200714ea4bb7Ssd 200814ea4bb7Ssd if (fm_check_acc_handle(nxgep->dev_regs->nxge_regh) != DDI_FM_OK) { 200914ea4bb7Ssd NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 20104045d941Ssowmini "port%d Bad register acc handle", nxgep->mac.portnum)); 201114ea4bb7Ssd status = NXGE_ERROR; 201214ea4bb7Ssd } 201314ea4bb7Ssd 201444961713Sgirish if (status != NXGE_OK) { 201544961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 20164045d941Ssowmini " nxge_setup_dev status " 20174045d941Ssowmini "(xcvr init 0x%08x)", status)); 201844961713Sgirish goto nxge_setup_dev_exit; 201944961713Sgirish } 202044961713Sgirish 202144961713Sgirish nxge_setup_dev_exit: 202244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 20234045d941Ssowmini "<== nxge_setup_dev port %d status = 0x%08x", 20244045d941Ssowmini nxgep->mac.portnum, status)); 202544961713Sgirish 202644961713Sgirish return (status); 202744961713Sgirish } 202844961713Sgirish 202944961713Sgirish static void 203044961713Sgirish nxge_destroy_dev(p_nxge_t nxgep) 203144961713Sgirish { 203244961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_dev")); 203344961713Sgirish 203444961713Sgirish (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 203544961713Sgirish 203644961713Sgirish (void) nxge_hw_stop(nxgep); 203744961713Sgirish 203844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_dev")); 203944961713Sgirish } 204044961713Sgirish 204144961713Sgirish static nxge_status_t 204244961713Sgirish nxge_setup_system_dma_pages(p_nxge_t nxgep) 204344961713Sgirish { 204444961713Sgirish int ddi_status = DDI_SUCCESS; 204544961713Sgirish uint_t count; 204644961713Sgirish ddi_dma_cookie_t cookie; 204744961713Sgirish uint_t iommu_pagesize; 204844961713Sgirish nxge_status_t status = NXGE_OK; 204944961713Sgirish 2050678453a8Sspeer NXGE_ERROR_MSG((nxgep, DDI_CTL, "==> nxge_setup_system_dma_pages")); 205144961713Sgirish nxgep->sys_page_sz = ddi_ptob(nxgep->dip, (ulong_t)1); 205244961713Sgirish if (nxgep->niu_type != N2_NIU) { 205344961713Sgirish iommu_pagesize = dvma_pagesize(nxgep->dip); 205444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 20554045d941Ssowmini " nxge_setup_system_dma_pages: page %d (ddi_ptob %d) " 20564045d941Ssowmini " default_block_size %d iommu_pagesize %d", 20574045d941Ssowmini nxgep->sys_page_sz, 20584045d941Ssowmini ddi_ptob(nxgep->dip, (ulong_t)1), 20594045d941Ssowmini nxgep->rx_default_block_size, 20604045d941Ssowmini iommu_pagesize)); 206144961713Sgirish 206244961713Sgirish if (iommu_pagesize != 0) { 206344961713Sgirish if (nxgep->sys_page_sz == iommu_pagesize) { 206444961713Sgirish if (iommu_pagesize > 0x4000) 206544961713Sgirish nxgep->sys_page_sz = 0x4000; 206644961713Sgirish } else { 206744961713Sgirish if (nxgep->sys_page_sz > iommu_pagesize) 206844961713Sgirish nxgep->sys_page_sz = iommu_pagesize; 206944961713Sgirish } 207044961713Sgirish } 207144961713Sgirish } 207244961713Sgirish nxgep->sys_page_mask = ~(nxgep->sys_page_sz - 1); 207344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 20744045d941Ssowmini "==> nxge_setup_system_dma_pages: page %d (ddi_ptob %d) " 20754045d941Ssowmini "default_block_size %d page mask %d", 20764045d941Ssowmini nxgep->sys_page_sz, 20774045d941Ssowmini ddi_ptob(nxgep->dip, (ulong_t)1), 20784045d941Ssowmini nxgep->rx_default_block_size, 20794045d941Ssowmini nxgep->sys_page_mask)); 208044961713Sgirish 208144961713Sgirish 208244961713Sgirish switch (nxgep->sys_page_sz) { 208344961713Sgirish default: 208444961713Sgirish nxgep->sys_page_sz = 0x1000; 208544961713Sgirish nxgep->sys_page_mask = ~(nxgep->sys_page_sz - 1); 208644961713Sgirish nxgep->rx_default_block_size = 0x1000; 208744961713Sgirish nxgep->rx_bksize_code = RBR_BKSIZE_4K; 208844961713Sgirish break; 208944961713Sgirish case 0x1000: 209044961713Sgirish nxgep->rx_default_block_size = 0x1000; 209144961713Sgirish nxgep->rx_bksize_code = RBR_BKSIZE_4K; 209244961713Sgirish break; 209344961713Sgirish case 0x2000: 209444961713Sgirish nxgep->rx_default_block_size = 0x2000; 209544961713Sgirish nxgep->rx_bksize_code = RBR_BKSIZE_8K; 209644961713Sgirish break; 209744961713Sgirish case 0x4000: 209844961713Sgirish nxgep->rx_default_block_size = 0x4000; 209944961713Sgirish nxgep->rx_bksize_code = RBR_BKSIZE_16K; 210044961713Sgirish break; 210144961713Sgirish case 0x8000: 210244961713Sgirish nxgep->rx_default_block_size = 0x8000; 210344961713Sgirish nxgep->rx_bksize_code = RBR_BKSIZE_32K; 210444961713Sgirish break; 210544961713Sgirish } 210644961713Sgirish 210744961713Sgirish #ifndef USE_RX_BIG_BUF 210844961713Sgirish nxge_rx_dma_attr.dma_attr_align = nxgep->sys_page_sz; 210944961713Sgirish #else 211044961713Sgirish nxgep->rx_default_block_size = 0x2000; 211144961713Sgirish nxgep->rx_bksize_code = RBR_BKSIZE_8K; 211244961713Sgirish #endif 211344961713Sgirish /* 211444961713Sgirish * Get the system DMA burst size. 211544961713Sgirish */ 211644961713Sgirish ddi_status = ddi_dma_alloc_handle(nxgep->dip, &nxge_tx_dma_attr, 21174045d941Ssowmini DDI_DMA_DONTWAIT, 0, 21184045d941Ssowmini &nxgep->dmasparehandle); 211944961713Sgirish if (ddi_status != DDI_SUCCESS) { 212044961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 21214045d941Ssowmini "ddi_dma_alloc_handle: failed " 21224045d941Ssowmini " status 0x%x", ddi_status)); 212344961713Sgirish goto nxge_get_soft_properties_exit; 212444961713Sgirish } 212544961713Sgirish 212644961713Sgirish ddi_status = ddi_dma_addr_bind_handle(nxgep->dmasparehandle, NULL, 21274045d941Ssowmini (caddr_t)nxgep->dmasparehandle, 21284045d941Ssowmini sizeof (nxgep->dmasparehandle), 21294045d941Ssowmini DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 21304045d941Ssowmini DDI_DMA_DONTWAIT, 0, 21314045d941Ssowmini &cookie, &count); 213244961713Sgirish if (ddi_status != DDI_DMA_MAPPED) { 213344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 21344045d941Ssowmini "Binding spare handle to find system" 21354045d941Ssowmini " burstsize failed.")); 213644961713Sgirish ddi_status = DDI_FAILURE; 213744961713Sgirish goto nxge_get_soft_properties_fail1; 213844961713Sgirish } 213944961713Sgirish 214044961713Sgirish nxgep->sys_burst_sz = ddi_dma_burstsizes(nxgep->dmasparehandle); 214144961713Sgirish (void) ddi_dma_unbind_handle(nxgep->dmasparehandle); 214244961713Sgirish 214344961713Sgirish nxge_get_soft_properties_fail1: 214444961713Sgirish ddi_dma_free_handle(&nxgep->dmasparehandle); 214544961713Sgirish 214644961713Sgirish nxge_get_soft_properties_exit: 214744961713Sgirish 214844961713Sgirish if (ddi_status != DDI_SUCCESS) 214944961713Sgirish status |= (NXGE_ERROR | NXGE_DDI_FAILED); 215044961713Sgirish 215144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 21524045d941Ssowmini "<== nxge_setup_system_dma_pages status = 0x%08x", status)); 215344961713Sgirish return (status); 215444961713Sgirish } 215544961713Sgirish 215644961713Sgirish static nxge_status_t 215744961713Sgirish nxge_alloc_mem_pool(p_nxge_t nxgep) 215844961713Sgirish { 215944961713Sgirish nxge_status_t status = NXGE_OK; 216044961713Sgirish 216144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_alloc_mem_pool")); 216244961713Sgirish 216344961713Sgirish status = nxge_alloc_rx_mem_pool(nxgep); 216444961713Sgirish if (status != NXGE_OK) { 216544961713Sgirish return (NXGE_ERROR); 216644961713Sgirish } 216744961713Sgirish 216844961713Sgirish status = nxge_alloc_tx_mem_pool(nxgep); 216944961713Sgirish if (status != NXGE_OK) { 217044961713Sgirish nxge_free_rx_mem_pool(nxgep); 217144961713Sgirish return (NXGE_ERROR); 217244961713Sgirish } 217344961713Sgirish 217444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_alloc_mem_pool")); 217544961713Sgirish return (NXGE_OK); 217644961713Sgirish } 217744961713Sgirish 217844961713Sgirish static void 217944961713Sgirish nxge_free_mem_pool(p_nxge_t nxgep) 218044961713Sgirish { 218144961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM_CTL, "==> nxge_free_mem_pool")); 218244961713Sgirish 218344961713Sgirish nxge_free_rx_mem_pool(nxgep); 218444961713Sgirish nxge_free_tx_mem_pool(nxgep); 218544961713Sgirish 218644961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM_CTL, "<== nxge_free_mem_pool")); 218744961713Sgirish } 218844961713Sgirish 2189678453a8Sspeer nxge_status_t 219044961713Sgirish nxge_alloc_rx_mem_pool(p_nxge_t nxgep) 219144961713Sgirish { 2192678453a8Sspeer uint32_t rdc_max; 219344961713Sgirish p_nxge_dma_pt_cfg_t p_all_cfgp; 219444961713Sgirish p_nxge_hw_pt_cfg_t p_cfgp; 219544961713Sgirish p_nxge_dma_pool_t dma_poolp; 219644961713Sgirish p_nxge_dma_common_t *dma_buf_p; 219744961713Sgirish p_nxge_dma_pool_t dma_cntl_poolp; 219844961713Sgirish p_nxge_dma_common_t *dma_cntl_p; 219944961713Sgirish uint32_t *num_chunks; /* per dma */ 220044961713Sgirish nxge_status_t status = NXGE_OK; 220144961713Sgirish 220244961713Sgirish uint32_t nxge_port_rbr_size; 220344961713Sgirish uint32_t nxge_port_rbr_spare_size; 220444961713Sgirish uint32_t nxge_port_rcr_size; 2205678453a8Sspeer uint32_t rx_cntl_alloc_size; 220644961713Sgirish 220744961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rx_mem_pool")); 220844961713Sgirish 220944961713Sgirish p_all_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 221044961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_all_cfgp->hw_config; 2211678453a8Sspeer rdc_max = NXGE_MAX_RDCS; 221244961713Sgirish 221344961713Sgirish /* 2214678453a8Sspeer * Allocate memory for the common DMA data structures. 221544961713Sgirish */ 221644961713Sgirish dma_poolp = (p_nxge_dma_pool_t)KMEM_ZALLOC(sizeof (nxge_dma_pool_t), 22174045d941Ssowmini KM_SLEEP); 221844961713Sgirish dma_buf_p = (p_nxge_dma_common_t *)KMEM_ZALLOC( 22194045d941Ssowmini sizeof (p_nxge_dma_common_t) * rdc_max, KM_SLEEP); 222044961713Sgirish 222144961713Sgirish dma_cntl_poolp = (p_nxge_dma_pool_t) 22224045d941Ssowmini KMEM_ZALLOC(sizeof (nxge_dma_pool_t), KM_SLEEP); 222344961713Sgirish dma_cntl_p = (p_nxge_dma_common_t *)KMEM_ZALLOC( 22244045d941Ssowmini sizeof (p_nxge_dma_common_t) * rdc_max, KM_SLEEP); 222544961713Sgirish 222644961713Sgirish num_chunks = (uint32_t *)KMEM_ZALLOC( 22274045d941Ssowmini sizeof (uint32_t) * rdc_max, KM_SLEEP); 222844961713Sgirish 222944961713Sgirish /* 2230678453a8Sspeer * Assume that each DMA channel will be configured with 2231678453a8Sspeer * the default block size. 2232678453a8Sspeer * rbr block counts are modulo the batch count (16). 223344961713Sgirish */ 223444961713Sgirish nxge_port_rbr_size = p_all_cfgp->rbr_size; 223544961713Sgirish nxge_port_rcr_size = p_all_cfgp->rcr_size; 223644961713Sgirish 223744961713Sgirish if (!nxge_port_rbr_size) { 223844961713Sgirish nxge_port_rbr_size = NXGE_RBR_RBB_DEFAULT; 223944961713Sgirish } 224044961713Sgirish if (nxge_port_rbr_size % NXGE_RXDMA_POST_BATCH) { 224144961713Sgirish nxge_port_rbr_size = (NXGE_RXDMA_POST_BATCH * 22424045d941Ssowmini (nxge_port_rbr_size / NXGE_RXDMA_POST_BATCH + 1)); 224344961713Sgirish } 224444961713Sgirish 224544961713Sgirish p_all_cfgp->rbr_size = nxge_port_rbr_size; 224644961713Sgirish nxge_port_rbr_spare_size = nxge_rbr_spare_size; 224744961713Sgirish 224844961713Sgirish if (nxge_port_rbr_spare_size % NXGE_RXDMA_POST_BATCH) { 224944961713Sgirish nxge_port_rbr_spare_size = (NXGE_RXDMA_POST_BATCH * 22504045d941Ssowmini (nxge_port_rbr_spare_size / NXGE_RXDMA_POST_BATCH + 1)); 225144961713Sgirish } 225230ac2e7bSml if (nxge_port_rbr_size > RBR_DEFAULT_MAX_BLKS) { 225330ac2e7bSml NXGE_DEBUG_MSG((nxgep, MEM_CTL, 225430ac2e7bSml "nxge_alloc_rx_mem_pool: RBR size too high %d, " 225530ac2e7bSml "set to default %d", 225630ac2e7bSml nxge_port_rbr_size, RBR_DEFAULT_MAX_BLKS)); 225730ac2e7bSml nxge_port_rbr_size = RBR_DEFAULT_MAX_BLKS; 225830ac2e7bSml } 225930ac2e7bSml if (nxge_port_rcr_size > RCR_DEFAULT_MAX) { 226030ac2e7bSml NXGE_DEBUG_MSG((nxgep, MEM_CTL, 226130ac2e7bSml "nxge_alloc_rx_mem_pool: RCR too high %d, " 226230ac2e7bSml "set to default %d", 226330ac2e7bSml nxge_port_rcr_size, RCR_DEFAULT_MAX)); 226430ac2e7bSml nxge_port_rcr_size = RCR_DEFAULT_MAX; 226530ac2e7bSml } 226644961713Sgirish 226744961713Sgirish /* 226844961713Sgirish * N2/NIU has limitation on the descriptor sizes (contiguous 226944961713Sgirish * memory allocation on data buffers to 4M (contig_mem_alloc) 227044961713Sgirish * and little endian for control buffers (must use the ddi/dki mem alloc 227144961713Sgirish * function). 227244961713Sgirish */ 227344961713Sgirish #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 227444961713Sgirish if (nxgep->niu_type == N2_NIU) { 227544961713Sgirish nxge_port_rbr_spare_size = 0; 227644961713Sgirish if ((nxge_port_rbr_size > NXGE_NIU_CONTIG_RBR_MAX) || 22774045d941Ssowmini (!ISP2(nxge_port_rbr_size))) { 227844961713Sgirish nxge_port_rbr_size = NXGE_NIU_CONTIG_RBR_MAX; 227944961713Sgirish } 228044961713Sgirish if ((nxge_port_rcr_size > NXGE_NIU_CONTIG_RCR_MAX) || 22814045d941Ssowmini (!ISP2(nxge_port_rcr_size))) { 228244961713Sgirish nxge_port_rcr_size = NXGE_NIU_CONTIG_RCR_MAX; 228344961713Sgirish } 228444961713Sgirish } 228544961713Sgirish #endif 228644961713Sgirish 228744961713Sgirish /* 228844961713Sgirish * Addresses of receive block ring, receive completion ring and the 228944961713Sgirish * mailbox must be all cache-aligned (64 bytes). 229044961713Sgirish */ 229144961713Sgirish rx_cntl_alloc_size = nxge_port_rbr_size + nxge_port_rbr_spare_size; 229244961713Sgirish rx_cntl_alloc_size *= (sizeof (rx_desc_t)); 229344961713Sgirish rx_cntl_alloc_size += (sizeof (rcr_entry_t) * nxge_port_rcr_size); 229444961713Sgirish rx_cntl_alloc_size += sizeof (rxdma_mailbox_t); 229544961713Sgirish 229644961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_alloc_rx_mem_pool: " 22974045d941Ssowmini "nxge_port_rbr_size = %d nxge_port_rbr_spare_size = %d " 22984045d941Ssowmini "nxge_port_rcr_size = %d " 22994045d941Ssowmini "rx_cntl_alloc_size = %d", 23004045d941Ssowmini nxge_port_rbr_size, nxge_port_rbr_spare_size, 23014045d941Ssowmini nxge_port_rcr_size, 23024045d941Ssowmini rx_cntl_alloc_size)); 230344961713Sgirish 230444961713Sgirish #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 230544961713Sgirish if (nxgep->niu_type == N2_NIU) { 2306678453a8Sspeer uint32_t rx_buf_alloc_size = (nxgep->rx_default_block_size * 2307678453a8Sspeer (nxge_port_rbr_size + nxge_port_rbr_spare_size)); 2308678453a8Sspeer 230944961713Sgirish if (!ISP2(rx_buf_alloc_size)) { 231044961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 23114045d941Ssowmini "==> nxge_alloc_rx_mem_pool: " 23124045d941Ssowmini " must be power of 2")); 231344961713Sgirish status |= (NXGE_ERROR | NXGE_DDI_FAILED); 231444961713Sgirish goto nxge_alloc_rx_mem_pool_exit; 231544961713Sgirish } 231644961713Sgirish 231744961713Sgirish if (rx_buf_alloc_size > (1 << 22)) { 231844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 23194045d941Ssowmini "==> nxge_alloc_rx_mem_pool: " 23204045d941Ssowmini " limit size to 4M")); 232144961713Sgirish status |= (NXGE_ERROR | NXGE_DDI_FAILED); 232244961713Sgirish goto nxge_alloc_rx_mem_pool_exit; 232344961713Sgirish } 232444961713Sgirish 232544961713Sgirish if (rx_cntl_alloc_size < 0x2000) { 232644961713Sgirish rx_cntl_alloc_size = 0x2000; 232744961713Sgirish } 232844961713Sgirish } 232944961713Sgirish #endif 233044961713Sgirish nxgep->nxge_port_rbr_size = nxge_port_rbr_size; 233144961713Sgirish nxgep->nxge_port_rcr_size = nxge_port_rcr_size; 2332678453a8Sspeer nxgep->nxge_port_rbr_spare_size = nxge_port_rbr_spare_size; 2333678453a8Sspeer nxgep->nxge_port_rx_cntl_alloc_size = rx_cntl_alloc_size; 233444961713Sgirish 2335678453a8Sspeer dma_poolp->ndmas = p_cfgp->max_rdcs; 233644961713Sgirish dma_poolp->num_chunks = num_chunks; 233744961713Sgirish dma_poolp->buf_allocated = B_TRUE; 233844961713Sgirish nxgep->rx_buf_pool_p = dma_poolp; 233944961713Sgirish dma_poolp->dma_buf_pool_p = dma_buf_p; 234044961713Sgirish 2341678453a8Sspeer dma_cntl_poolp->ndmas = p_cfgp->max_rdcs; 234244961713Sgirish dma_cntl_poolp->buf_allocated = B_TRUE; 234344961713Sgirish nxgep->rx_cntl_pool_p = dma_cntl_poolp; 234444961713Sgirish dma_cntl_poolp->dma_buf_pool_p = dma_cntl_p; 234544961713Sgirish 2346678453a8Sspeer /* Allocate the receive rings, too. */ 2347678453a8Sspeer nxgep->rx_rbr_rings = 23484045d941Ssowmini KMEM_ZALLOC(sizeof (rx_rbr_rings_t), KM_SLEEP); 2349678453a8Sspeer nxgep->rx_rbr_rings->rbr_rings = 23504045d941Ssowmini KMEM_ZALLOC(sizeof (p_rx_rbr_ring_t) * rdc_max, KM_SLEEP); 2351678453a8Sspeer nxgep->rx_rcr_rings = 23524045d941Ssowmini KMEM_ZALLOC(sizeof (rx_rcr_rings_t), KM_SLEEP); 2353678453a8Sspeer nxgep->rx_rcr_rings->rcr_rings = 23544045d941Ssowmini KMEM_ZALLOC(sizeof (p_rx_rcr_ring_t) * rdc_max, KM_SLEEP); 2355678453a8Sspeer nxgep->rx_mbox_areas_p = 23564045d941Ssowmini KMEM_ZALLOC(sizeof (rx_mbox_areas_t), KM_SLEEP); 2357678453a8Sspeer nxgep->rx_mbox_areas_p->rxmbox_areas = 23584045d941Ssowmini KMEM_ZALLOC(sizeof (p_rx_mbox_t) * rdc_max, KM_SLEEP); 2359678453a8Sspeer 2360678453a8Sspeer nxgep->rx_rbr_rings->ndmas = nxgep->rx_rcr_rings->ndmas = 2361678453a8Sspeer p_cfgp->max_rdcs; 236244961713Sgirish 236344961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 23644045d941Ssowmini "<== nxge_alloc_rx_mem_pool:status 0x%08x", status)); 236544961713Sgirish 2366678453a8Sspeer nxge_alloc_rx_mem_pool_exit: 2367678453a8Sspeer return (status); 2368678453a8Sspeer } 2369678453a8Sspeer 2370678453a8Sspeer /* 2371678453a8Sspeer * nxge_alloc_rxb 2372678453a8Sspeer * 2373678453a8Sspeer * Allocate buffers for an RDC. 2374678453a8Sspeer * 2375678453a8Sspeer * Arguments: 2376678453a8Sspeer * nxgep 2377678453a8Sspeer * channel The channel to map into our kernel space. 2378678453a8Sspeer * 2379678453a8Sspeer * Notes: 2380678453a8Sspeer * 2381678453a8Sspeer * NPI function calls: 2382678453a8Sspeer * 2383678453a8Sspeer * NXGE function calls: 2384678453a8Sspeer * 2385678453a8Sspeer * Registers accessed: 2386678453a8Sspeer * 2387678453a8Sspeer * Context: 2388678453a8Sspeer * 2389678453a8Sspeer * Taking apart: 2390678453a8Sspeer * 2391678453a8Sspeer * Open questions: 2392678453a8Sspeer * 2393678453a8Sspeer */ 2394678453a8Sspeer nxge_status_t 2395678453a8Sspeer nxge_alloc_rxb( 2396678453a8Sspeer p_nxge_t nxgep, 2397678453a8Sspeer int channel) 2398678453a8Sspeer { 2399678453a8Sspeer size_t rx_buf_alloc_size; 2400678453a8Sspeer nxge_status_t status = NXGE_OK; 2401678453a8Sspeer 2402678453a8Sspeer nxge_dma_common_t **data; 2403678453a8Sspeer nxge_dma_common_t **control; 2404678453a8Sspeer uint32_t *num_chunks; 2405678453a8Sspeer 2406678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rbb")); 2407678453a8Sspeer 2408678453a8Sspeer /* 2409678453a8Sspeer * Allocate memory for the receive buffers and descriptor rings. 2410678453a8Sspeer * Replace these allocation functions with the interface functions 2411678453a8Sspeer * provided by the partition manager if/when they are available. 2412678453a8Sspeer */ 2413678453a8Sspeer 2414678453a8Sspeer /* 2415678453a8Sspeer * Allocate memory for the receive buffer blocks. 2416678453a8Sspeer */ 2417678453a8Sspeer rx_buf_alloc_size = (nxgep->rx_default_block_size * 24184045d941Ssowmini (nxgep->nxge_port_rbr_size + nxgep->nxge_port_rbr_spare_size)); 2419678453a8Sspeer 2420678453a8Sspeer data = &nxgep->rx_buf_pool_p->dma_buf_pool_p[channel]; 2421678453a8Sspeer num_chunks = &nxgep->rx_buf_pool_p->num_chunks[channel]; 2422678453a8Sspeer 2423678453a8Sspeer if ((status = nxge_alloc_rx_buf_dma( 2424678453a8Sspeer nxgep, channel, data, rx_buf_alloc_size, 2425678453a8Sspeer nxgep->rx_default_block_size, num_chunks)) != NXGE_OK) { 2426678453a8Sspeer return (status); 242744961713Sgirish } 242844961713Sgirish 2429678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_alloc_rxb(): " 2430678453a8Sspeer "dma %d dma_buf_p %llx &dma_buf_p %llx", channel, *data, data)); 2431678453a8Sspeer 2432678453a8Sspeer /* 2433678453a8Sspeer * Allocate memory for descriptor rings and mailbox. 2434678453a8Sspeer */ 2435678453a8Sspeer control = &nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel]; 2436678453a8Sspeer 2437678453a8Sspeer if ((status = nxge_alloc_rx_cntl_dma( 2438678453a8Sspeer nxgep, channel, control, nxgep->nxge_port_rx_cntl_alloc_size)) 2439678453a8Sspeer != NXGE_OK) { 2440678453a8Sspeer nxge_free_rx_cntl_dma(nxgep, *control); 2441678453a8Sspeer (*data)->buf_alloc_state |= BUF_ALLOCATED_WAIT_FREE; 2442678453a8Sspeer nxge_free_rx_buf_dma(nxgep, *data, *num_chunks); 2443678453a8Sspeer return (status); 2444678453a8Sspeer } 244544961713Sgirish 244644961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 2447678453a8Sspeer "<== nxge_alloc_rx_mem_pool:status 0x%08x", status)); 244844961713Sgirish 244944961713Sgirish return (status); 245044961713Sgirish } 245144961713Sgirish 2452678453a8Sspeer void 2453678453a8Sspeer nxge_free_rxb( 2454678453a8Sspeer p_nxge_t nxgep, 2455678453a8Sspeer int channel) 2456678453a8Sspeer { 2457678453a8Sspeer nxge_dma_common_t *data; 2458678453a8Sspeer nxge_dma_common_t *control; 2459678453a8Sspeer uint32_t num_chunks; 2460678453a8Sspeer 2461678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rbb")); 2462678453a8Sspeer 2463678453a8Sspeer data = nxgep->rx_buf_pool_p->dma_buf_pool_p[channel]; 2464678453a8Sspeer num_chunks = nxgep->rx_buf_pool_p->num_chunks[channel]; 2465678453a8Sspeer nxge_free_rx_buf_dma(nxgep, data, num_chunks); 2466678453a8Sspeer 2467678453a8Sspeer nxgep->rx_buf_pool_p->dma_buf_pool_p[channel] = 0; 2468678453a8Sspeer nxgep->rx_buf_pool_p->num_chunks[channel] = 0; 2469678453a8Sspeer 2470678453a8Sspeer control = nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel]; 2471678453a8Sspeer nxge_free_rx_cntl_dma(nxgep, control); 2472678453a8Sspeer 2473678453a8Sspeer nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel] = 0; 2474678453a8Sspeer 2475678453a8Sspeer KMEM_FREE(data, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK); 2476678453a8Sspeer KMEM_FREE(control, sizeof (nxge_dma_common_t)); 2477678453a8Sspeer 2478678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_alloc_rbb")); 2479678453a8Sspeer } 2480678453a8Sspeer 248144961713Sgirish static void 248244961713Sgirish nxge_free_rx_mem_pool(p_nxge_t nxgep) 248344961713Sgirish { 2484678453a8Sspeer int rdc_max = NXGE_MAX_RDCS; 248544961713Sgirish 248644961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_free_rx_mem_pool")); 248744961713Sgirish 2488678453a8Sspeer if (!nxgep->rx_buf_pool_p || !nxgep->rx_buf_pool_p->buf_allocated) { 248944961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 24904045d941Ssowmini "<== nxge_free_rx_mem_pool " 24914045d941Ssowmini "(null rx buf pool or buf not allocated")); 249244961713Sgirish return; 249344961713Sgirish } 2494678453a8Sspeer if (!nxgep->rx_cntl_pool_p || !nxgep->rx_cntl_pool_p->buf_allocated) { 249544961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 24964045d941Ssowmini "<== nxge_free_rx_mem_pool " 24974045d941Ssowmini "(null rx cntl buf pool or cntl buf not allocated")); 249844961713Sgirish return; 249944961713Sgirish } 250044961713Sgirish 2501678453a8Sspeer KMEM_FREE(nxgep->rx_cntl_pool_p->dma_buf_pool_p, 2502678453a8Sspeer sizeof (p_nxge_dma_common_t) * rdc_max); 2503678453a8Sspeer KMEM_FREE(nxgep->rx_cntl_pool_p, sizeof (nxge_dma_pool_t)); 250444961713Sgirish 2505678453a8Sspeer KMEM_FREE(nxgep->rx_buf_pool_p->num_chunks, 2506678453a8Sspeer sizeof (uint32_t) * rdc_max); 2507678453a8Sspeer KMEM_FREE(nxgep->rx_buf_pool_p->dma_buf_pool_p, 2508678453a8Sspeer sizeof (p_nxge_dma_common_t) * rdc_max); 2509678453a8Sspeer KMEM_FREE(nxgep->rx_buf_pool_p, sizeof (nxge_dma_pool_t)); 251044961713Sgirish 2511678453a8Sspeer nxgep->rx_buf_pool_p = 0; 2512678453a8Sspeer nxgep->rx_cntl_pool_p = 0; 251344961713Sgirish 2514678453a8Sspeer KMEM_FREE(nxgep->rx_rbr_rings->rbr_rings, 2515678453a8Sspeer sizeof (p_rx_rbr_ring_t) * rdc_max); 2516678453a8Sspeer KMEM_FREE(nxgep->rx_rbr_rings, sizeof (rx_rbr_rings_t)); 2517678453a8Sspeer KMEM_FREE(nxgep->rx_rcr_rings->rcr_rings, 2518678453a8Sspeer sizeof (p_rx_rcr_ring_t) * rdc_max); 2519678453a8Sspeer KMEM_FREE(nxgep->rx_rcr_rings, sizeof (rx_rcr_rings_t)); 2520678453a8Sspeer KMEM_FREE(nxgep->rx_mbox_areas_p->rxmbox_areas, 2521678453a8Sspeer sizeof (p_rx_mbox_t) * rdc_max); 2522678453a8Sspeer KMEM_FREE(nxgep->rx_mbox_areas_p, sizeof (rx_mbox_areas_t)); 252344961713Sgirish 2524678453a8Sspeer nxgep->rx_rbr_rings = 0; 2525678453a8Sspeer nxgep->rx_rcr_rings = 0; 2526678453a8Sspeer nxgep->rx_mbox_areas_p = 0; 252744961713Sgirish 252844961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_free_rx_mem_pool")); 252944961713Sgirish } 253044961713Sgirish 253144961713Sgirish 253244961713Sgirish static nxge_status_t 253344961713Sgirish nxge_alloc_rx_buf_dma(p_nxge_t nxgep, uint16_t dma_channel, 253444961713Sgirish p_nxge_dma_common_t *dmap, 253544961713Sgirish size_t alloc_size, size_t block_size, uint32_t *num_chunks) 253644961713Sgirish { 253744961713Sgirish p_nxge_dma_common_t rx_dmap; 253844961713Sgirish nxge_status_t status = NXGE_OK; 253944961713Sgirish size_t total_alloc_size; 254044961713Sgirish size_t allocated = 0; 254144961713Sgirish int i, size_index, array_size; 2542678453a8Sspeer boolean_t use_kmem_alloc = B_FALSE; 254344961713Sgirish 254444961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rx_buf_dma")); 254544961713Sgirish 254644961713Sgirish rx_dmap = (p_nxge_dma_common_t) 25474045d941Ssowmini KMEM_ZALLOC(sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK, 25484045d941Ssowmini KM_SLEEP); 254944961713Sgirish 255044961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 25514045d941Ssowmini " alloc_rx_buf_dma rdc %d asize %x bsize %x bbuf %llx ", 25524045d941Ssowmini dma_channel, alloc_size, block_size, dmap)); 255344961713Sgirish 255444961713Sgirish total_alloc_size = alloc_size; 255544961713Sgirish 255644961713Sgirish #if defined(RX_USE_RECLAIM_POST) 255744961713Sgirish total_alloc_size = alloc_size + alloc_size/4; 255844961713Sgirish #endif 255944961713Sgirish 256044961713Sgirish i = 0; 256144961713Sgirish size_index = 0; 256244961713Sgirish array_size = sizeof (alloc_sizes)/sizeof (size_t); 256344961713Sgirish while ((alloc_sizes[size_index] < alloc_size) && 25644045d941Ssowmini (size_index < array_size)) 25654045d941Ssowmini size_index++; 256644961713Sgirish if (size_index >= array_size) { 256744961713Sgirish size_index = array_size - 1; 256844961713Sgirish } 256944961713Sgirish 2570678453a8Sspeer /* For Neptune, use kmem_alloc if the kmem flag is set. */ 2571678453a8Sspeer if (nxgep->niu_type != N2_NIU && nxge_use_kmem_alloc) { 2572678453a8Sspeer use_kmem_alloc = B_TRUE; 2573678453a8Sspeer #if defined(__i386) || defined(__amd64) 2574678453a8Sspeer size_index = 0; 2575678453a8Sspeer #endif 2576678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2577678453a8Sspeer "==> nxge_alloc_rx_buf_dma: " 2578678453a8Sspeer "Neptune use kmem_alloc() - size_index %d", 2579678453a8Sspeer size_index)); 2580678453a8Sspeer } 2581678453a8Sspeer 258244961713Sgirish while ((allocated < total_alloc_size) && 25834045d941Ssowmini (size_index >= 0) && (i < NXGE_DMA_BLOCK)) { 258444961713Sgirish rx_dmap[i].dma_chunk_index = i; 258544961713Sgirish rx_dmap[i].block_size = block_size; 258644961713Sgirish rx_dmap[i].alength = alloc_sizes[size_index]; 258744961713Sgirish rx_dmap[i].orig_alength = rx_dmap[i].alength; 258844961713Sgirish rx_dmap[i].nblocks = alloc_sizes[size_index] / block_size; 258944961713Sgirish rx_dmap[i].dma_channel = dma_channel; 259044961713Sgirish rx_dmap[i].contig_alloc_type = B_FALSE; 2591678453a8Sspeer rx_dmap[i].kmem_alloc_type = B_FALSE; 2592678453a8Sspeer rx_dmap[i].buf_alloc_type = DDI_MEM_ALLOC; 259344961713Sgirish 259444961713Sgirish /* 259544961713Sgirish * N2/NIU: data buffers must be contiguous as the driver 259644961713Sgirish * needs to call Hypervisor api to set up 259744961713Sgirish * logical pages. 259844961713Sgirish */ 259944961713Sgirish if ((nxgep->niu_type == N2_NIU) && (NXGE_DMA_BLOCK == 1)) { 260044961713Sgirish rx_dmap[i].contig_alloc_type = B_TRUE; 2601678453a8Sspeer rx_dmap[i].buf_alloc_type = CONTIG_MEM_ALLOC; 2602678453a8Sspeer } else if (use_kmem_alloc) { 2603678453a8Sspeer /* For Neptune, use kmem_alloc */ 2604678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2605678453a8Sspeer "==> nxge_alloc_rx_buf_dma: " 2606678453a8Sspeer "Neptune use kmem_alloc()")); 2607678453a8Sspeer rx_dmap[i].kmem_alloc_type = B_TRUE; 2608678453a8Sspeer rx_dmap[i].buf_alloc_type = KMEM_ALLOC; 260944961713Sgirish } 261044961713Sgirish 261144961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 26124045d941Ssowmini "alloc_rx_buf_dma rdc %d chunk %d bufp %llx size %x " 26134045d941Ssowmini "i %d nblocks %d alength %d", 26144045d941Ssowmini dma_channel, i, &rx_dmap[i], block_size, 26154045d941Ssowmini i, rx_dmap[i].nblocks, 26164045d941Ssowmini rx_dmap[i].alength)); 261744961713Sgirish status = nxge_dma_mem_alloc(nxgep, nxge_force_dma, 26184045d941Ssowmini &nxge_rx_dma_attr, 26194045d941Ssowmini rx_dmap[i].alength, 26204045d941Ssowmini &nxge_dev_buf_dma_acc_attr, 26214045d941Ssowmini DDI_DMA_READ | DDI_DMA_STREAMING, 26224045d941Ssowmini (p_nxge_dma_common_t)(&rx_dmap[i])); 262344961713Sgirish if (status != NXGE_OK) { 262444961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2625678453a8Sspeer "nxge_alloc_rx_buf_dma: Alloc Failed: " 2626678453a8Sspeer "dma %d size_index %d size requested %d", 2627678453a8Sspeer dma_channel, 2628678453a8Sspeer size_index, 2629678453a8Sspeer rx_dmap[i].alength)); 263044961713Sgirish size_index--; 263144961713Sgirish } else { 2632678453a8Sspeer rx_dmap[i].buf_alloc_state = BUF_ALLOCATED; 2633678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2634678453a8Sspeer " nxge_alloc_rx_buf_dma DONE alloc mem: " 2635678453a8Sspeer "dma %d dma_buf_p $%p kaddrp $%p alength %d " 2636678453a8Sspeer "buf_alloc_state %d alloc_type %d", 2637678453a8Sspeer dma_channel, 2638678453a8Sspeer &rx_dmap[i], 2639678453a8Sspeer rx_dmap[i].kaddrp, 2640678453a8Sspeer rx_dmap[i].alength, 2641678453a8Sspeer rx_dmap[i].buf_alloc_state, 2642678453a8Sspeer rx_dmap[i].buf_alloc_type)); 2643678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2644678453a8Sspeer " alloc_rx_buf_dma allocated rdc %d " 2645678453a8Sspeer "chunk %d size %x dvma %x bufp %llx kaddrp $%p", 2646678453a8Sspeer dma_channel, i, rx_dmap[i].alength, 2647678453a8Sspeer rx_dmap[i].ioaddr_pp, &rx_dmap[i], 2648678453a8Sspeer rx_dmap[i].kaddrp)); 264944961713Sgirish i++; 265044961713Sgirish allocated += alloc_sizes[size_index]; 265144961713Sgirish } 265244961713Sgirish } 265344961713Sgirish 265444961713Sgirish if (allocated < total_alloc_size) { 265530ac2e7bSml NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2656678453a8Sspeer "==> nxge_alloc_rx_buf_dma: not enough for channel %d " 265730ac2e7bSml "allocated 0x%x requested 0x%x", 265830ac2e7bSml dma_channel, 265930ac2e7bSml allocated, total_alloc_size)); 266030ac2e7bSml status = NXGE_ERROR; 266144961713Sgirish goto nxge_alloc_rx_mem_fail1; 266244961713Sgirish } 266344961713Sgirish 266430ac2e7bSml NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2665678453a8Sspeer "==> nxge_alloc_rx_buf_dma: Allocated for channel %d " 266630ac2e7bSml "allocated 0x%x requested 0x%x", 266730ac2e7bSml dma_channel, 266830ac2e7bSml allocated, total_alloc_size)); 266930ac2e7bSml 267044961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 26714045d941Ssowmini " alloc_rx_buf_dma rdc %d allocated %d chunks", 26724045d941Ssowmini dma_channel, i)); 267344961713Sgirish *num_chunks = i; 267444961713Sgirish *dmap = rx_dmap; 267544961713Sgirish 267644961713Sgirish goto nxge_alloc_rx_mem_exit; 267744961713Sgirish 267844961713Sgirish nxge_alloc_rx_mem_fail1: 267944961713Sgirish KMEM_FREE(rx_dmap, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK); 268044961713Sgirish 268144961713Sgirish nxge_alloc_rx_mem_exit: 268244961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 26834045d941Ssowmini "<== nxge_alloc_rx_buf_dma status 0x%08x", status)); 268444961713Sgirish 268544961713Sgirish return (status); 268644961713Sgirish } 268744961713Sgirish 268844961713Sgirish /*ARGSUSED*/ 268944961713Sgirish static void 269044961713Sgirish nxge_free_rx_buf_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap, 269144961713Sgirish uint32_t num_chunks) 269244961713Sgirish { 269344961713Sgirish int i; 269444961713Sgirish 269544961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 26964045d941Ssowmini "==> nxge_free_rx_buf_dma: # of chunks %d", num_chunks)); 269744961713Sgirish 2698678453a8Sspeer if (dmap == 0) 2699678453a8Sspeer return; 2700678453a8Sspeer 270144961713Sgirish for (i = 0; i < num_chunks; i++) { 270244961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 27034045d941Ssowmini "==> nxge_free_rx_buf_dma: chunk %d dmap 0x%llx", 27044045d941Ssowmini i, dmap)); 2705678453a8Sspeer nxge_dma_free_rx_data_buf(dmap++); 270644961713Sgirish } 270744961713Sgirish 270844961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_free_rx_buf_dma")); 270944961713Sgirish } 271044961713Sgirish 271144961713Sgirish /*ARGSUSED*/ 271244961713Sgirish static nxge_status_t 271344961713Sgirish nxge_alloc_rx_cntl_dma(p_nxge_t nxgep, uint16_t dma_channel, 271444961713Sgirish p_nxge_dma_common_t *dmap, size_t size) 271544961713Sgirish { 271644961713Sgirish p_nxge_dma_common_t rx_dmap; 271744961713Sgirish nxge_status_t status = NXGE_OK; 271844961713Sgirish 271944961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rx_cntl_dma")); 272044961713Sgirish 272144961713Sgirish rx_dmap = (p_nxge_dma_common_t) 27224045d941Ssowmini KMEM_ZALLOC(sizeof (nxge_dma_common_t), KM_SLEEP); 272344961713Sgirish 272444961713Sgirish rx_dmap->contig_alloc_type = B_FALSE; 2725678453a8Sspeer rx_dmap->kmem_alloc_type = B_FALSE; 272644961713Sgirish 272744961713Sgirish status = nxge_dma_mem_alloc(nxgep, nxge_force_dma, 27284045d941Ssowmini &nxge_desc_dma_attr, 27294045d941Ssowmini size, 27304045d941Ssowmini &nxge_dev_desc_dma_acc_attr, 27314045d941Ssowmini DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 27324045d941Ssowmini rx_dmap); 273344961713Sgirish if (status != NXGE_OK) { 273444961713Sgirish goto nxge_alloc_rx_cntl_dma_fail1; 273544961713Sgirish } 273644961713Sgirish 273744961713Sgirish *dmap = rx_dmap; 273844961713Sgirish goto nxge_alloc_rx_cntl_dma_exit; 273944961713Sgirish 274044961713Sgirish nxge_alloc_rx_cntl_dma_fail1: 274144961713Sgirish KMEM_FREE(rx_dmap, sizeof (nxge_dma_common_t)); 274244961713Sgirish 274344961713Sgirish nxge_alloc_rx_cntl_dma_exit: 274444961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 27454045d941Ssowmini "<== nxge_alloc_rx_cntl_dma status 0x%08x", status)); 274644961713Sgirish 2747678453a8Sspeer return (status); 2748678453a8Sspeer } 2749678453a8Sspeer 2750678453a8Sspeer /*ARGSUSED*/ 2751678453a8Sspeer static void 2752678453a8Sspeer nxge_free_rx_cntl_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap) 2753678453a8Sspeer { 2754678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_free_rx_cntl_dma")); 2755678453a8Sspeer 2756678453a8Sspeer if (dmap == 0) 2757678453a8Sspeer return; 2758678453a8Sspeer 2759678453a8Sspeer nxge_dma_mem_free(dmap); 2760678453a8Sspeer 2761678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_free_rx_cntl_dma")); 2762678453a8Sspeer } 2763678453a8Sspeer 2764678453a8Sspeer typedef struct { 2765678453a8Sspeer size_t tx_size; 2766678453a8Sspeer size_t cr_size; 2767678453a8Sspeer size_t threshhold; 2768678453a8Sspeer } nxge_tdc_sizes_t; 2769678453a8Sspeer 2770678453a8Sspeer static 2771678453a8Sspeer nxge_status_t 2772678453a8Sspeer nxge_tdc_sizes( 2773678453a8Sspeer nxge_t *nxgep, 2774678453a8Sspeer nxge_tdc_sizes_t *sizes) 2775678453a8Sspeer { 2776678453a8Sspeer uint32_t threshhold; /* The bcopy() threshhold */ 2777678453a8Sspeer size_t tx_size; /* Transmit buffer size */ 2778678453a8Sspeer size_t cr_size; /* Completion ring size */ 2779678453a8Sspeer 2780678453a8Sspeer /* 2781678453a8Sspeer * Assume that each DMA channel will be configured with the 2782678453a8Sspeer * default transmit buffer size for copying transmit data. 2783678453a8Sspeer * (If a packet is bigger than this, it will not be copied.) 2784678453a8Sspeer */ 2785678453a8Sspeer if (nxgep->niu_type == N2_NIU) { 2786678453a8Sspeer threshhold = TX_BCOPY_SIZE; 2787678453a8Sspeer } else { 2788678453a8Sspeer threshhold = nxge_bcopy_thresh; 2789678453a8Sspeer } 2790678453a8Sspeer tx_size = nxge_tx_ring_size * threshhold; 2791678453a8Sspeer 2792678453a8Sspeer cr_size = nxge_tx_ring_size * sizeof (tx_desc_t); 2793678453a8Sspeer cr_size += sizeof (txdma_mailbox_t); 2794678453a8Sspeer 2795678453a8Sspeer #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 2796678453a8Sspeer if (nxgep->niu_type == N2_NIU) { 2797678453a8Sspeer if (!ISP2(tx_size)) { 2798678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 27994045d941Ssowmini "==> nxge_tdc_sizes: Tx size" 28004045d941Ssowmini " must be power of 2")); 2801678453a8Sspeer return (NXGE_ERROR); 2802678453a8Sspeer } 2803678453a8Sspeer 2804678453a8Sspeer if (tx_size > (1 << 22)) { 2805678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 28064045d941Ssowmini "==> nxge_tdc_sizes: Tx size" 28074045d941Ssowmini " limited to 4M")); 2808678453a8Sspeer return (NXGE_ERROR); 2809678453a8Sspeer } 2810678453a8Sspeer 2811678453a8Sspeer if (cr_size < 0x2000) 2812678453a8Sspeer cr_size = 0x2000; 2813678453a8Sspeer } 2814678453a8Sspeer #endif 2815678453a8Sspeer 2816678453a8Sspeer sizes->threshhold = threshhold; 2817678453a8Sspeer sizes->tx_size = tx_size; 2818678453a8Sspeer sizes->cr_size = cr_size; 2819678453a8Sspeer 2820678453a8Sspeer return (NXGE_OK); 2821678453a8Sspeer } 2822678453a8Sspeer /* 2823678453a8Sspeer * nxge_alloc_txb 2824678453a8Sspeer * 2825678453a8Sspeer * Allocate buffers for an TDC. 2826678453a8Sspeer * 2827678453a8Sspeer * Arguments: 2828678453a8Sspeer * nxgep 2829678453a8Sspeer * channel The channel to map into our kernel space. 2830678453a8Sspeer * 2831678453a8Sspeer * Notes: 2832678453a8Sspeer * 2833678453a8Sspeer * NPI function calls: 2834678453a8Sspeer * 2835678453a8Sspeer * NXGE function calls: 2836678453a8Sspeer * 2837678453a8Sspeer * Registers accessed: 2838678453a8Sspeer * 2839678453a8Sspeer * Context: 2840678453a8Sspeer * 2841678453a8Sspeer * Taking apart: 2842678453a8Sspeer * 2843678453a8Sspeer * Open questions: 2844678453a8Sspeer * 2845678453a8Sspeer */ 2846678453a8Sspeer nxge_status_t 2847678453a8Sspeer nxge_alloc_txb( 2848678453a8Sspeer p_nxge_t nxgep, 2849678453a8Sspeer int channel) 2850678453a8Sspeer { 2851678453a8Sspeer nxge_dma_common_t **dma_buf_p; 2852678453a8Sspeer nxge_dma_common_t **dma_cntl_p; 2853678453a8Sspeer uint32_t *num_chunks; 2854678453a8Sspeer nxge_status_t status = NXGE_OK; 2855678453a8Sspeer 2856678453a8Sspeer nxge_tdc_sizes_t sizes; 2857678453a8Sspeer 2858678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_tbb")); 2859678453a8Sspeer 2860678453a8Sspeer if (nxge_tdc_sizes(nxgep, &sizes) != NXGE_OK) 2861678453a8Sspeer return (NXGE_ERROR); 2862678453a8Sspeer 2863678453a8Sspeer /* 2864678453a8Sspeer * Allocate memory for transmit buffers and descriptor rings. 2865678453a8Sspeer * Replace these allocation functions with the interface functions 2866678453a8Sspeer * provided by the partition manager Real Soon Now. 2867678453a8Sspeer */ 2868678453a8Sspeer dma_buf_p = &nxgep->tx_buf_pool_p->dma_buf_pool_p[channel]; 2869678453a8Sspeer num_chunks = &nxgep->tx_buf_pool_p->num_chunks[channel]; 2870678453a8Sspeer 2871678453a8Sspeer dma_cntl_p = &nxgep->tx_cntl_pool_p->dma_buf_pool_p[channel]; 2872678453a8Sspeer 2873678453a8Sspeer /* 2874678453a8Sspeer * Allocate memory for transmit buffers and descriptor rings. 2875678453a8Sspeer * Replace allocation functions with interface functions provided 2876678453a8Sspeer * by the partition manager when it is available. 2877678453a8Sspeer * 2878678453a8Sspeer * Allocate memory for the transmit buffer pool. 2879678453a8Sspeer */ 2880678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, 28814045d941Ssowmini "sizes: tx: %ld, cr:%ld, th:%ld", 28824045d941Ssowmini sizes.tx_size, sizes.cr_size, sizes.threshhold)); 2883678453a8Sspeer 2884678453a8Sspeer *num_chunks = 0; 2885678453a8Sspeer status = nxge_alloc_tx_buf_dma(nxgep, channel, dma_buf_p, 2886678453a8Sspeer sizes.tx_size, sizes.threshhold, num_chunks); 2887678453a8Sspeer if (status != NXGE_OK) { 2888678453a8Sspeer cmn_err(CE_NOTE, "nxge_alloc_tx_buf_dma failed!"); 2889678453a8Sspeer return (status); 2890678453a8Sspeer } 2891678453a8Sspeer 2892678453a8Sspeer /* 2893678453a8Sspeer * Allocate memory for descriptor rings and mailbox. 2894678453a8Sspeer */ 2895678453a8Sspeer status = nxge_alloc_tx_cntl_dma(nxgep, channel, dma_cntl_p, 2896678453a8Sspeer sizes.cr_size); 2897678453a8Sspeer if (status != NXGE_OK) { 2898678453a8Sspeer nxge_free_tx_buf_dma(nxgep, *dma_buf_p, *num_chunks); 2899678453a8Sspeer cmn_err(CE_NOTE, "nxge_alloc_tx_cntl_dma failed!"); 2900678453a8Sspeer return (status); 2901678453a8Sspeer } 2902678453a8Sspeer 2903678453a8Sspeer return (NXGE_OK); 2904678453a8Sspeer } 2905678453a8Sspeer 2906678453a8Sspeer void 2907678453a8Sspeer nxge_free_txb( 2908678453a8Sspeer p_nxge_t nxgep, 2909678453a8Sspeer int channel) 2910678453a8Sspeer { 2911678453a8Sspeer nxge_dma_common_t *data; 2912678453a8Sspeer nxge_dma_common_t *control; 2913678453a8Sspeer uint32_t num_chunks; 2914678453a8Sspeer 2915678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_free_txb")); 2916678453a8Sspeer 2917678453a8Sspeer data = nxgep->tx_buf_pool_p->dma_buf_pool_p[channel]; 2918678453a8Sspeer num_chunks = nxgep->tx_buf_pool_p->num_chunks[channel]; 2919678453a8Sspeer nxge_free_tx_buf_dma(nxgep, data, num_chunks); 2920678453a8Sspeer 2921678453a8Sspeer nxgep->tx_buf_pool_p->dma_buf_pool_p[channel] = 0; 2922678453a8Sspeer nxgep->tx_buf_pool_p->num_chunks[channel] = 0; 2923678453a8Sspeer 2924678453a8Sspeer control = nxgep->tx_cntl_pool_p->dma_buf_pool_p[channel]; 2925678453a8Sspeer nxge_free_tx_cntl_dma(nxgep, control); 292644961713Sgirish 2927678453a8Sspeer nxgep->tx_cntl_pool_p->dma_buf_pool_p[channel] = 0; 292844961713Sgirish 2929678453a8Sspeer KMEM_FREE(data, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK); 2930678453a8Sspeer KMEM_FREE(control, sizeof (nxge_dma_common_t)); 293144961713Sgirish 2932678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_free_txb")); 293344961713Sgirish } 293444961713Sgirish 2935678453a8Sspeer /* 2936678453a8Sspeer * nxge_alloc_tx_mem_pool 2937678453a8Sspeer * 2938678453a8Sspeer * This function allocates all of the per-port TDC control data structures. 2939678453a8Sspeer * The per-channel (TDC) data structures are allocated when needed. 2940678453a8Sspeer * 2941678453a8Sspeer * Arguments: 2942678453a8Sspeer * nxgep 2943678453a8Sspeer * 2944678453a8Sspeer * Notes: 2945678453a8Sspeer * 2946678453a8Sspeer * Context: 2947678453a8Sspeer * Any domain 2948678453a8Sspeer */ 2949678453a8Sspeer nxge_status_t 295044961713Sgirish nxge_alloc_tx_mem_pool(p_nxge_t nxgep) 295144961713Sgirish { 2952678453a8Sspeer nxge_hw_pt_cfg_t *p_cfgp; 2953678453a8Sspeer nxge_dma_pool_t *dma_poolp; 2954678453a8Sspeer nxge_dma_common_t **dma_buf_p; 2955678453a8Sspeer nxge_dma_pool_t *dma_cntl_poolp; 2956678453a8Sspeer nxge_dma_common_t **dma_cntl_p; 295744961713Sgirish uint32_t *num_chunks; /* per dma */ 2958678453a8Sspeer int tdc_max; 295944961713Sgirish 296044961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM_CTL, "==> nxge_alloc_tx_mem_pool")); 296144961713Sgirish 2962678453a8Sspeer p_cfgp = &nxgep->pt_config.hw_config; 2963678453a8Sspeer tdc_max = NXGE_MAX_TDCS; 296444961713Sgirish 296544961713Sgirish /* 296644961713Sgirish * Allocate memory for each transmit DMA channel. 296744961713Sgirish */ 296844961713Sgirish dma_poolp = (p_nxge_dma_pool_t)KMEM_ZALLOC(sizeof (nxge_dma_pool_t), 29694045d941Ssowmini KM_SLEEP); 297044961713Sgirish dma_buf_p = (p_nxge_dma_common_t *)KMEM_ZALLOC( 29714045d941Ssowmini sizeof (p_nxge_dma_common_t) * tdc_max, KM_SLEEP); 297244961713Sgirish 297344961713Sgirish dma_cntl_poolp = (p_nxge_dma_pool_t) 29744045d941Ssowmini KMEM_ZALLOC(sizeof (nxge_dma_pool_t), KM_SLEEP); 297544961713Sgirish dma_cntl_p = (p_nxge_dma_common_t *)KMEM_ZALLOC( 29764045d941Ssowmini sizeof (p_nxge_dma_common_t) * tdc_max, KM_SLEEP); 297744961713Sgirish 297830ac2e7bSml if (nxge_tx_ring_size > TDC_DEFAULT_MAX) { 297930ac2e7bSml NXGE_DEBUG_MSG((nxgep, MEM_CTL, 298030ac2e7bSml "nxge_alloc_tx_mem_pool: TDC too high %d, " 298130ac2e7bSml "set to default %d", 298230ac2e7bSml nxge_tx_ring_size, TDC_DEFAULT_MAX)); 298330ac2e7bSml nxge_tx_ring_size = TDC_DEFAULT_MAX; 298430ac2e7bSml } 298530ac2e7bSml 298644961713Sgirish #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 298744961713Sgirish /* 298844961713Sgirish * N2/NIU has limitation on the descriptor sizes (contiguous 298944961713Sgirish * memory allocation on data buffers to 4M (contig_mem_alloc) 299044961713Sgirish * and little endian for control buffers (must use the ddi/dki mem alloc 299144961713Sgirish * function). The transmit ring is limited to 8K (includes the 299244961713Sgirish * mailbox). 299344961713Sgirish */ 299444961713Sgirish if (nxgep->niu_type == N2_NIU) { 299544961713Sgirish if ((nxge_tx_ring_size > NXGE_NIU_CONTIG_TX_MAX) || 29964045d941Ssowmini (!ISP2(nxge_tx_ring_size))) { 299744961713Sgirish nxge_tx_ring_size = NXGE_NIU_CONTIG_TX_MAX; 299844961713Sgirish } 299944961713Sgirish } 300044961713Sgirish #endif 300144961713Sgirish 300244961713Sgirish nxgep->nxge_port_tx_ring_size = nxge_tx_ring_size; 300344961713Sgirish 300444961713Sgirish num_chunks = (uint32_t *)KMEM_ZALLOC( 30054045d941Ssowmini sizeof (uint32_t) * tdc_max, KM_SLEEP); 300644961713Sgirish 3007678453a8Sspeer dma_poolp->ndmas = p_cfgp->tdc.owned; 300844961713Sgirish dma_poolp->num_chunks = num_chunks; 300944961713Sgirish dma_poolp->dma_buf_pool_p = dma_buf_p; 301044961713Sgirish nxgep->tx_buf_pool_p = dma_poolp; 301144961713Sgirish 3012678453a8Sspeer dma_poolp->buf_allocated = B_TRUE; 3013678453a8Sspeer 3014678453a8Sspeer dma_cntl_poolp->ndmas = p_cfgp->tdc.owned; 301544961713Sgirish dma_cntl_poolp->dma_buf_pool_p = dma_cntl_p; 301644961713Sgirish nxgep->tx_cntl_pool_p = dma_cntl_poolp; 301744961713Sgirish 3018678453a8Sspeer dma_cntl_poolp->buf_allocated = B_TRUE; 301944961713Sgirish 3020678453a8Sspeer nxgep->tx_rings = 3021678453a8Sspeer KMEM_ZALLOC(sizeof (tx_rings_t), KM_SLEEP); 3022678453a8Sspeer nxgep->tx_rings->rings = 3023678453a8Sspeer KMEM_ZALLOC(sizeof (p_tx_ring_t) * tdc_max, KM_SLEEP); 3024678453a8Sspeer nxgep->tx_mbox_areas_p = 3025678453a8Sspeer KMEM_ZALLOC(sizeof (tx_mbox_areas_t), KM_SLEEP); 3026678453a8Sspeer nxgep->tx_mbox_areas_p->txmbox_areas_p = 3027678453a8Sspeer KMEM_ZALLOC(sizeof (p_tx_mbox_t) * tdc_max, KM_SLEEP); 302844961713Sgirish 3029678453a8Sspeer nxgep->tx_rings->ndmas = p_cfgp->tdc.owned; 303044961713Sgirish 303144961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM_CTL, 30324045d941Ssowmini "==> nxge_alloc_tx_mem_pool: ndmas %d poolp->ndmas %d", 30334045d941Ssowmini tdc_max, dma_poolp->ndmas)); 303444961713Sgirish 3035678453a8Sspeer return (NXGE_OK); 303644961713Sgirish } 303744961713Sgirish 3038678453a8Sspeer nxge_status_t 303944961713Sgirish nxge_alloc_tx_buf_dma(p_nxge_t nxgep, uint16_t dma_channel, 304044961713Sgirish p_nxge_dma_common_t *dmap, size_t alloc_size, 304144961713Sgirish size_t block_size, uint32_t *num_chunks) 304244961713Sgirish { 304344961713Sgirish p_nxge_dma_common_t tx_dmap; 304444961713Sgirish nxge_status_t status = NXGE_OK; 304544961713Sgirish size_t total_alloc_size; 304644961713Sgirish size_t allocated = 0; 304744961713Sgirish int i, size_index, array_size; 304844961713Sgirish 304944961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_tx_buf_dma")); 305044961713Sgirish 305144961713Sgirish tx_dmap = (p_nxge_dma_common_t) 30524045d941Ssowmini KMEM_ZALLOC(sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK, 30534045d941Ssowmini KM_SLEEP); 305444961713Sgirish 305544961713Sgirish total_alloc_size = alloc_size; 305644961713Sgirish i = 0; 305744961713Sgirish size_index = 0; 305844961713Sgirish array_size = sizeof (alloc_sizes) / sizeof (size_t); 305944961713Sgirish while ((alloc_sizes[size_index] < alloc_size) && 30604045d941Ssowmini (size_index < array_size)) 306144961713Sgirish size_index++; 306244961713Sgirish if (size_index >= array_size) { 306344961713Sgirish size_index = array_size - 1; 306444961713Sgirish } 306544961713Sgirish 306644961713Sgirish while ((allocated < total_alloc_size) && 30674045d941Ssowmini (size_index >= 0) && (i < NXGE_DMA_BLOCK)) { 306844961713Sgirish 306944961713Sgirish tx_dmap[i].dma_chunk_index = i; 307044961713Sgirish tx_dmap[i].block_size = block_size; 307144961713Sgirish tx_dmap[i].alength = alloc_sizes[size_index]; 307244961713Sgirish tx_dmap[i].orig_alength = tx_dmap[i].alength; 307344961713Sgirish tx_dmap[i].nblocks = alloc_sizes[size_index] / block_size; 307444961713Sgirish tx_dmap[i].dma_channel = dma_channel; 307544961713Sgirish tx_dmap[i].contig_alloc_type = B_FALSE; 3076678453a8Sspeer tx_dmap[i].kmem_alloc_type = B_FALSE; 307744961713Sgirish 307844961713Sgirish /* 307944961713Sgirish * N2/NIU: data buffers must be contiguous as the driver 308044961713Sgirish * needs to call Hypervisor api to set up 308144961713Sgirish * logical pages. 308244961713Sgirish */ 308344961713Sgirish if ((nxgep->niu_type == N2_NIU) && (NXGE_DMA_BLOCK == 1)) { 308444961713Sgirish tx_dmap[i].contig_alloc_type = B_TRUE; 308544961713Sgirish } 308644961713Sgirish 308744961713Sgirish status = nxge_dma_mem_alloc(nxgep, nxge_force_dma, 30884045d941Ssowmini &nxge_tx_dma_attr, 30894045d941Ssowmini tx_dmap[i].alength, 30904045d941Ssowmini &nxge_dev_buf_dma_acc_attr, 30914045d941Ssowmini DDI_DMA_WRITE | DDI_DMA_STREAMING, 30924045d941Ssowmini (p_nxge_dma_common_t)(&tx_dmap[i])); 309344961713Sgirish if (status != NXGE_OK) { 309444961713Sgirish size_index--; 309544961713Sgirish } else { 309644961713Sgirish i++; 309744961713Sgirish allocated += alloc_sizes[size_index]; 309844961713Sgirish } 309944961713Sgirish } 310044961713Sgirish 310144961713Sgirish if (allocated < total_alloc_size) { 310230ac2e7bSml NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 310330ac2e7bSml "==> nxge_alloc_tx_buf_dma: not enough channel %d: " 310430ac2e7bSml "allocated 0x%x requested 0x%x", 310530ac2e7bSml dma_channel, 310630ac2e7bSml allocated, total_alloc_size)); 310730ac2e7bSml status = NXGE_ERROR; 310844961713Sgirish goto nxge_alloc_tx_mem_fail1; 310944961713Sgirish } 311044961713Sgirish 311130ac2e7bSml NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 311230ac2e7bSml "==> nxge_alloc_tx_buf_dma: Allocated for channel %d: " 311330ac2e7bSml "allocated 0x%x requested 0x%x", 311430ac2e7bSml dma_channel, 311530ac2e7bSml allocated, total_alloc_size)); 311630ac2e7bSml 311744961713Sgirish *num_chunks = i; 311844961713Sgirish *dmap = tx_dmap; 311944961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 31204045d941Ssowmini "==> nxge_alloc_tx_buf_dma dmap 0x%016llx num chunks %d", 31214045d941Ssowmini *dmap, i)); 312244961713Sgirish goto nxge_alloc_tx_mem_exit; 312344961713Sgirish 312444961713Sgirish nxge_alloc_tx_mem_fail1: 312544961713Sgirish KMEM_FREE(tx_dmap, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK); 312644961713Sgirish 312744961713Sgirish nxge_alloc_tx_mem_exit: 312844961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 31294045d941Ssowmini "<== nxge_alloc_tx_buf_dma status 0x%08x", status)); 313044961713Sgirish 313144961713Sgirish return (status); 313244961713Sgirish } 313344961713Sgirish 313444961713Sgirish /*ARGSUSED*/ 313544961713Sgirish static void 313644961713Sgirish nxge_free_tx_buf_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap, 313744961713Sgirish uint32_t num_chunks) 313844961713Sgirish { 313944961713Sgirish int i; 314044961713Sgirish 314144961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM_CTL, "==> nxge_free_tx_buf_dma")); 314244961713Sgirish 3143678453a8Sspeer if (dmap == 0) 3144678453a8Sspeer return; 3145678453a8Sspeer 314644961713Sgirish for (i = 0; i < num_chunks; i++) { 314744961713Sgirish nxge_dma_mem_free(dmap++); 314844961713Sgirish } 314944961713Sgirish 315044961713Sgirish NXGE_DEBUG_MSG((nxgep, MEM_CTL, "<== nxge_free_tx_buf_dma")); 315144961713Sgirish } 315244961713Sgirish 315344961713Sgirish /*ARGSUSED*/ 3154678453a8Sspeer nxge_status_t 315544961713Sgirish nxge_alloc_tx_cntl_dma(p_nxge_t nxgep, uint16_t dma_channel, 315644961713Sgirish p_nxge_dma_common_t *dmap, size_t size) 315744961713Sgirish { 315844961713Sgirish p_nxge_dma_common_t tx_dmap; 315944961713Sgirish nxge_status_t status = NXGE_OK; 316044961713Sgirish 316144961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_tx_cntl_dma")); 316244961713Sgirish tx_dmap = (p_nxge_dma_common_t) 31634045d941Ssowmini KMEM_ZALLOC(sizeof (nxge_dma_common_t), KM_SLEEP); 316444961713Sgirish 316544961713Sgirish tx_dmap->contig_alloc_type = B_FALSE; 3166678453a8Sspeer tx_dmap->kmem_alloc_type = B_FALSE; 316744961713Sgirish 316844961713Sgirish status = nxge_dma_mem_alloc(nxgep, nxge_force_dma, 31694045d941Ssowmini &nxge_desc_dma_attr, 31704045d941Ssowmini size, 31714045d941Ssowmini &nxge_dev_desc_dma_acc_attr, 31724045d941Ssowmini DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 31734045d941Ssowmini tx_dmap); 317444961713Sgirish if (status != NXGE_OK) { 317544961713Sgirish goto nxge_alloc_tx_cntl_dma_fail1; 317644961713Sgirish } 317744961713Sgirish 317844961713Sgirish *dmap = tx_dmap; 317944961713Sgirish goto nxge_alloc_tx_cntl_dma_exit; 318044961713Sgirish 318144961713Sgirish nxge_alloc_tx_cntl_dma_fail1: 318244961713Sgirish KMEM_FREE(tx_dmap, sizeof (nxge_dma_common_t)); 318344961713Sgirish 318444961713Sgirish nxge_alloc_tx_cntl_dma_exit: 318544961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 31864045d941Ssowmini "<== nxge_alloc_tx_cntl_dma status 0x%08x", status)); 318744961713Sgirish 318844961713Sgirish return (status); 318944961713Sgirish } 319044961713Sgirish 319144961713Sgirish /*ARGSUSED*/ 319244961713Sgirish static void 319344961713Sgirish nxge_free_tx_cntl_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap) 319444961713Sgirish { 319544961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_free_tx_cntl_dma")); 319644961713Sgirish 3197678453a8Sspeer if (dmap == 0) 3198678453a8Sspeer return; 3199678453a8Sspeer 320044961713Sgirish nxge_dma_mem_free(dmap); 320144961713Sgirish 320244961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_free_tx_cntl_dma")); 320344961713Sgirish } 320444961713Sgirish 3205678453a8Sspeer /* 3206678453a8Sspeer * nxge_free_tx_mem_pool 3207678453a8Sspeer * 3208678453a8Sspeer * This function frees all of the per-port TDC control data structures. 3209678453a8Sspeer * The per-channel (TDC) data structures are freed when the channel 3210678453a8Sspeer * is stopped. 3211678453a8Sspeer * 3212678453a8Sspeer * Arguments: 3213678453a8Sspeer * nxgep 3214678453a8Sspeer * 3215678453a8Sspeer * Notes: 3216678453a8Sspeer * 3217678453a8Sspeer * Context: 3218678453a8Sspeer * Any domain 3219678453a8Sspeer */ 322044961713Sgirish static void 322144961713Sgirish nxge_free_tx_mem_pool(p_nxge_t nxgep) 322244961713Sgirish { 3223678453a8Sspeer int tdc_max = NXGE_MAX_TDCS; 322444961713Sgirish 3225678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_free_tx_mem_pool")); 322644961713Sgirish 3227678453a8Sspeer if (!nxgep->tx_buf_pool_p || !nxgep->tx_buf_pool_p->buf_allocated) { 3228678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 32294045d941Ssowmini "<== nxge_free_tx_mem_pool " 32304045d941Ssowmini "(null tx buf pool or buf not allocated")); 323144961713Sgirish return; 323244961713Sgirish } 3233678453a8Sspeer if (!nxgep->tx_cntl_pool_p || !nxgep->tx_cntl_pool_p->buf_allocated) { 3234678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 32354045d941Ssowmini "<== nxge_free_tx_mem_pool " 32364045d941Ssowmini "(null tx cntl buf pool or cntl buf not allocated")); 323744961713Sgirish return; 323844961713Sgirish } 323944961713Sgirish 3240678453a8Sspeer /* 1. Free the mailboxes. */ 3241678453a8Sspeer KMEM_FREE(nxgep->tx_mbox_areas_p->txmbox_areas_p, 3242678453a8Sspeer sizeof (p_tx_mbox_t) * tdc_max); 3243678453a8Sspeer KMEM_FREE(nxgep->tx_mbox_areas_p, sizeof (tx_mbox_areas_t)); 324444961713Sgirish 3245678453a8Sspeer nxgep->tx_mbox_areas_p = 0; 324644961713Sgirish 3247678453a8Sspeer /* 2. Free the transmit ring arrays. */ 3248678453a8Sspeer KMEM_FREE(nxgep->tx_rings->rings, 3249678453a8Sspeer sizeof (p_tx_ring_t) * tdc_max); 3250678453a8Sspeer KMEM_FREE(nxgep->tx_rings, sizeof (tx_rings_t)); 325144961713Sgirish 3252678453a8Sspeer nxgep->tx_rings = 0; 325344961713Sgirish 3254678453a8Sspeer /* 3. Free the completion ring data structures. */ 3255678453a8Sspeer KMEM_FREE(nxgep->tx_cntl_pool_p->dma_buf_pool_p, 3256678453a8Sspeer sizeof (p_nxge_dma_common_t) * tdc_max); 3257678453a8Sspeer KMEM_FREE(nxgep->tx_cntl_pool_p, sizeof (nxge_dma_pool_t)); 325844961713Sgirish 3259678453a8Sspeer nxgep->tx_cntl_pool_p = 0; 326044961713Sgirish 3261678453a8Sspeer /* 4. Free the data ring data structures. */ 3262678453a8Sspeer KMEM_FREE(nxgep->tx_buf_pool_p->num_chunks, 3263678453a8Sspeer sizeof (uint32_t) * tdc_max); 3264678453a8Sspeer KMEM_FREE(nxgep->tx_buf_pool_p->dma_buf_pool_p, 3265678453a8Sspeer sizeof (p_nxge_dma_common_t) * tdc_max); 3266678453a8Sspeer KMEM_FREE(nxgep->tx_buf_pool_p, sizeof (nxge_dma_pool_t)); 326744961713Sgirish 3268678453a8Sspeer nxgep->tx_buf_pool_p = 0; 3269678453a8Sspeer 3270678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_free_tx_mem_pool")); 327144961713Sgirish } 327244961713Sgirish 327344961713Sgirish /*ARGSUSED*/ 327444961713Sgirish static nxge_status_t 327544961713Sgirish nxge_dma_mem_alloc(p_nxge_t nxgep, dma_method_t method, 327644961713Sgirish struct ddi_dma_attr *dma_attrp, 327744961713Sgirish size_t length, ddi_device_acc_attr_t *acc_attr_p, uint_t xfer_flags, 327844961713Sgirish p_nxge_dma_common_t dma_p) 327944961713Sgirish { 328044961713Sgirish caddr_t kaddrp; 328144961713Sgirish int ddi_status = DDI_SUCCESS; 328244961713Sgirish boolean_t contig_alloc_type; 3283678453a8Sspeer boolean_t kmem_alloc_type; 328444961713Sgirish 328544961713Sgirish contig_alloc_type = dma_p->contig_alloc_type; 328644961713Sgirish 328744961713Sgirish if (contig_alloc_type && (nxgep->niu_type != N2_NIU)) { 328844961713Sgirish /* 328944961713Sgirish * contig_alloc_type for contiguous memory only allowed 329044961713Sgirish * for N2/NIU. 329144961713Sgirish */ 329244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 32934045d941Ssowmini "nxge_dma_mem_alloc: alloc type not allowed (%d)", 32944045d941Ssowmini dma_p->contig_alloc_type)); 329544961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 329644961713Sgirish } 329744961713Sgirish 329844961713Sgirish dma_p->dma_handle = NULL; 329944961713Sgirish dma_p->acc_handle = NULL; 330044961713Sgirish dma_p->kaddrp = dma_p->last_kaddrp = NULL; 330144961713Sgirish dma_p->first_ioaddr_pp = dma_p->last_ioaddr_pp = NULL; 330244961713Sgirish ddi_status = ddi_dma_alloc_handle(nxgep->dip, dma_attrp, 33034045d941Ssowmini DDI_DMA_DONTWAIT, NULL, &dma_p->dma_handle); 330444961713Sgirish if (ddi_status != DDI_SUCCESS) { 330544961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 33064045d941Ssowmini "nxge_dma_mem_alloc:ddi_dma_alloc_handle failed.")); 330744961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 330844961713Sgirish } 330944961713Sgirish 3310678453a8Sspeer kmem_alloc_type = dma_p->kmem_alloc_type; 3311678453a8Sspeer 331244961713Sgirish switch (contig_alloc_type) { 331344961713Sgirish case B_FALSE: 3314678453a8Sspeer switch (kmem_alloc_type) { 3315678453a8Sspeer case B_FALSE: 3316678453a8Sspeer ddi_status = ddi_dma_mem_alloc(dma_p->dma_handle, 33174045d941Ssowmini length, 33184045d941Ssowmini acc_attr_p, 33194045d941Ssowmini xfer_flags, 33204045d941Ssowmini DDI_DMA_DONTWAIT, 0, &kaddrp, &dma_p->alength, 33214045d941Ssowmini &dma_p->acc_handle); 3322678453a8Sspeer if (ddi_status != DDI_SUCCESS) { 3323678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3324678453a8Sspeer "nxge_dma_mem_alloc: " 3325678453a8Sspeer "ddi_dma_mem_alloc failed")); 3326678453a8Sspeer ddi_dma_free_handle(&dma_p->dma_handle); 3327678453a8Sspeer dma_p->dma_handle = NULL; 3328678453a8Sspeer return (NXGE_ERROR | NXGE_DDI_FAILED); 3329678453a8Sspeer } 3330678453a8Sspeer if (dma_p->alength < length) { 3331678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3332678453a8Sspeer "nxge_dma_mem_alloc:di_dma_mem_alloc " 3333678453a8Sspeer "< length.")); 333444961713Sgirish ddi_dma_mem_free(&dma_p->acc_handle); 3335678453a8Sspeer ddi_dma_free_handle(&dma_p->dma_handle); 333644961713Sgirish dma_p->acc_handle = NULL; 3337678453a8Sspeer dma_p->dma_handle = NULL; 3338678453a8Sspeer return (NXGE_ERROR); 333944961713Sgirish } 334044961713Sgirish 3341678453a8Sspeer ddi_status = ddi_dma_addr_bind_handle(dma_p->dma_handle, 3342678453a8Sspeer NULL, 3343678453a8Sspeer kaddrp, dma_p->alength, xfer_flags, 3344678453a8Sspeer DDI_DMA_DONTWAIT, 3345678453a8Sspeer 0, &dma_p->dma_cookie, &dma_p->ncookies); 3346678453a8Sspeer if (ddi_status != DDI_DMA_MAPPED) { 3347678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3348678453a8Sspeer "nxge_dma_mem_alloc: ddi_dma_addr_bind " 3349678453a8Sspeer "failed " 3350678453a8Sspeer "(staus 0x%x ncookies %d.)", ddi_status, 3351678453a8Sspeer dma_p->ncookies)); 3352678453a8Sspeer if (dma_p->acc_handle) { 3353678453a8Sspeer ddi_dma_mem_free(&dma_p->acc_handle); 3354678453a8Sspeer dma_p->acc_handle = NULL; 3355678453a8Sspeer } 3356678453a8Sspeer ddi_dma_free_handle(&dma_p->dma_handle); 3357678453a8Sspeer dma_p->dma_handle = NULL; 3358678453a8Sspeer return (NXGE_ERROR | NXGE_DDI_FAILED); 3359678453a8Sspeer } 3360678453a8Sspeer 3361678453a8Sspeer if (dma_p->ncookies != 1) { 3362678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, 3363678453a8Sspeer "nxge_dma_mem_alloc:ddi_dma_addr_bind " 3364678453a8Sspeer "> 1 cookie" 3365678453a8Sspeer "(staus 0x%x ncookies %d.)", ddi_status, 3366678453a8Sspeer dma_p->ncookies)); 3367678453a8Sspeer if (dma_p->acc_handle) { 3368678453a8Sspeer ddi_dma_mem_free(&dma_p->acc_handle); 3369678453a8Sspeer dma_p->acc_handle = NULL; 3370678453a8Sspeer } 3371678453a8Sspeer (void) ddi_dma_unbind_handle(dma_p->dma_handle); 3372678453a8Sspeer ddi_dma_free_handle(&dma_p->dma_handle); 3373678453a8Sspeer dma_p->dma_handle = NULL; 3374678453a8Sspeer return (NXGE_ERROR); 3375678453a8Sspeer } 3376678453a8Sspeer break; 3377678453a8Sspeer 3378678453a8Sspeer case B_TRUE: 3379678453a8Sspeer kaddrp = KMEM_ALLOC(length, KM_NOSLEEP); 3380678453a8Sspeer if (kaddrp == NULL) { 3381678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3382678453a8Sspeer "nxge_dma_mem_alloc:ddi_dma_mem_alloc " 3383678453a8Sspeer "kmem alloc failed")); 3384678453a8Sspeer return (NXGE_ERROR); 3385678453a8Sspeer } 3386678453a8Sspeer 3387678453a8Sspeer dma_p->alength = length; 3388678453a8Sspeer ddi_status = ddi_dma_addr_bind_handle(dma_p->dma_handle, 3389678453a8Sspeer NULL, kaddrp, dma_p->alength, xfer_flags, 3390678453a8Sspeer DDI_DMA_DONTWAIT, 0, 3391678453a8Sspeer &dma_p->dma_cookie, &dma_p->ncookies); 3392678453a8Sspeer if (ddi_status != DDI_DMA_MAPPED) { 3393678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3394678453a8Sspeer "nxge_dma_mem_alloc:ddi_dma_addr_bind: " 3395678453a8Sspeer "(kmem_alloc) failed kaddrp $%p length %d " 3396678453a8Sspeer "(staus 0x%x (%d) ncookies %d.)", 3397678453a8Sspeer kaddrp, length, 3398678453a8Sspeer ddi_status, ddi_status, dma_p->ncookies)); 3399678453a8Sspeer KMEM_FREE(kaddrp, length); 3400678453a8Sspeer dma_p->acc_handle = NULL; 3401678453a8Sspeer ddi_dma_free_handle(&dma_p->dma_handle); 3402678453a8Sspeer dma_p->dma_handle = NULL; 3403678453a8Sspeer dma_p->kaddrp = NULL; 3404678453a8Sspeer return (NXGE_ERROR | NXGE_DDI_FAILED); 3405678453a8Sspeer } 3406678453a8Sspeer 3407678453a8Sspeer if (dma_p->ncookies != 1) { 3408678453a8Sspeer NXGE_DEBUG_MSG((nxgep, DMA_CTL, 3409678453a8Sspeer "nxge_dma_mem_alloc:ddi_dma_addr_bind " 3410678453a8Sspeer "(kmem_alloc) > 1 cookie" 3411678453a8Sspeer "(staus 0x%x ncookies %d.)", ddi_status, 34124045d941Ssowmini dma_p->ncookies)); 3413678453a8Sspeer KMEM_FREE(kaddrp, length); 341444961713Sgirish dma_p->acc_handle = NULL; 3415678453a8Sspeer (void) ddi_dma_unbind_handle(dma_p->dma_handle); 3416678453a8Sspeer ddi_dma_free_handle(&dma_p->dma_handle); 3417678453a8Sspeer dma_p->dma_handle = NULL; 3418678453a8Sspeer dma_p->kaddrp = NULL; 3419678453a8Sspeer return (NXGE_ERROR); 342044961713Sgirish } 3421678453a8Sspeer 3422678453a8Sspeer dma_p->kaddrp = kaddrp; 3423678453a8Sspeer 3424678453a8Sspeer NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 34254045d941Ssowmini "nxge_dma_mem_alloc: kmem_alloc dmap $%p " 34264045d941Ssowmini "kaddr $%p alength %d", 34274045d941Ssowmini dma_p, 34284045d941Ssowmini kaddrp, 34294045d941Ssowmini dma_p->alength)); 3430678453a8Sspeer break; 343144961713Sgirish } 343244961713Sgirish break; 343344961713Sgirish 343444961713Sgirish #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 343544961713Sgirish case B_TRUE: 343644961713Sgirish kaddrp = (caddr_t)contig_mem_alloc(length); 343744961713Sgirish if (kaddrp == NULL) { 343844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 34394045d941Ssowmini "nxge_dma_mem_alloc:contig_mem_alloc failed.")); 344044961713Sgirish ddi_dma_free_handle(&dma_p->dma_handle); 344144961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 344244961713Sgirish } 344344961713Sgirish 344444961713Sgirish dma_p->alength = length; 344544961713Sgirish ddi_status = ddi_dma_addr_bind_handle(dma_p->dma_handle, NULL, 34464045d941Ssowmini kaddrp, dma_p->alength, xfer_flags, DDI_DMA_DONTWAIT, 0, 34474045d941Ssowmini &dma_p->dma_cookie, &dma_p->ncookies); 344844961713Sgirish if (ddi_status != DDI_DMA_MAPPED) { 344944961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 34504045d941Ssowmini "nxge_dma_mem_alloc:di_dma_addr_bind failed " 34514045d941Ssowmini "(status 0x%x ncookies %d.)", ddi_status, 34524045d941Ssowmini dma_p->ncookies)); 345344961713Sgirish 345444961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, 34554045d941Ssowmini "==> nxge_dma_mem_alloc: (not mapped)" 34564045d941Ssowmini "length %lu (0x%x) " 34574045d941Ssowmini "free contig kaddrp $%p " 34584045d941Ssowmini "va_to_pa $%p", 34594045d941Ssowmini length, length, 34604045d941Ssowmini kaddrp, 34614045d941Ssowmini va_to_pa(kaddrp))); 346244961713Sgirish 346344961713Sgirish 346444961713Sgirish contig_mem_free((void *)kaddrp, length); 346544961713Sgirish ddi_dma_free_handle(&dma_p->dma_handle); 346644961713Sgirish 346744961713Sgirish dma_p->dma_handle = NULL; 346844961713Sgirish dma_p->acc_handle = NULL; 346944961713Sgirish dma_p->alength = NULL; 347044961713Sgirish dma_p->kaddrp = NULL; 347144961713Sgirish 347244961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 347344961713Sgirish } 347444961713Sgirish 347544961713Sgirish if (dma_p->ncookies != 1 || 34764045d941Ssowmini (dma_p->dma_cookie.dmac_laddress == NULL)) { 347744961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 34784045d941Ssowmini "nxge_dma_mem_alloc:di_dma_addr_bind > 1 " 34794045d941Ssowmini "cookie or " 34804045d941Ssowmini "dmac_laddress is NULL $%p size %d " 34814045d941Ssowmini " (status 0x%x ncookies %d.)", 34824045d941Ssowmini ddi_status, 34834045d941Ssowmini dma_p->dma_cookie.dmac_laddress, 34844045d941Ssowmini dma_p->dma_cookie.dmac_size, 34854045d941Ssowmini dma_p->ncookies)); 348644961713Sgirish 348744961713Sgirish contig_mem_free((void *)kaddrp, length); 348856d930aeSspeer (void) ddi_dma_unbind_handle(dma_p->dma_handle); 348944961713Sgirish ddi_dma_free_handle(&dma_p->dma_handle); 349044961713Sgirish 349144961713Sgirish dma_p->alength = 0; 349244961713Sgirish dma_p->dma_handle = NULL; 349344961713Sgirish dma_p->acc_handle = NULL; 349444961713Sgirish dma_p->kaddrp = NULL; 349544961713Sgirish 349644961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 349744961713Sgirish } 349844961713Sgirish break; 349944961713Sgirish 350044961713Sgirish #else 350144961713Sgirish case B_TRUE: 350244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 35034045d941Ssowmini "nxge_dma_mem_alloc: invalid alloc type for !sun4v")); 350444961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 350544961713Sgirish #endif 350644961713Sgirish } 350744961713Sgirish 350844961713Sgirish dma_p->kaddrp = kaddrp; 350944961713Sgirish dma_p->last_kaddrp = (unsigned char *)kaddrp + 35104045d941Ssowmini dma_p->alength - RXBUF_64B_ALIGNED; 3511adfcba55Sjoycey #if defined(__i386) 3512adfcba55Sjoycey dma_p->ioaddr_pp = 35134045d941Ssowmini (unsigned char *)(uint32_t)dma_p->dma_cookie.dmac_laddress; 3514adfcba55Sjoycey #else 351544961713Sgirish dma_p->ioaddr_pp = (unsigned char *)dma_p->dma_cookie.dmac_laddress; 3516adfcba55Sjoycey #endif 351744961713Sgirish dma_p->last_ioaddr_pp = 3518adfcba55Sjoycey #if defined(__i386) 35194045d941Ssowmini (unsigned char *)(uint32_t)dma_p->dma_cookie.dmac_laddress + 3520adfcba55Sjoycey #else 35214045d941Ssowmini (unsigned char *)dma_p->dma_cookie.dmac_laddress + 3522adfcba55Sjoycey #endif 35234045d941Ssowmini dma_p->alength - RXBUF_64B_ALIGNED; 352444961713Sgirish 352544961713Sgirish NPI_DMA_ACC_HANDLE_SET(dma_p, dma_p->acc_handle); 352644961713Sgirish 352744961713Sgirish #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 352844961713Sgirish dma_p->orig_ioaddr_pp = 35294045d941Ssowmini (unsigned char *)dma_p->dma_cookie.dmac_laddress; 353044961713Sgirish dma_p->orig_alength = length; 353144961713Sgirish dma_p->orig_kaddrp = kaddrp; 353244961713Sgirish dma_p->orig_vatopa = (uint64_t)va_to_pa(kaddrp); 353344961713Sgirish #endif 353444961713Sgirish 353544961713Sgirish NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_dma_mem_alloc: " 35364045d941Ssowmini "dma buffer allocated: dma_p $%p " 35374045d941Ssowmini "return dmac_ladress from cookie $%p cookie dmac_size %d " 35384045d941Ssowmini "dma_p->ioaddr_p $%p " 35394045d941Ssowmini "dma_p->orig_ioaddr_p $%p " 35404045d941Ssowmini "orig_vatopa $%p " 35414045d941Ssowmini "alength %d (0x%x) " 35424045d941Ssowmini "kaddrp $%p " 35434045d941Ssowmini "length %d (0x%x)", 35444045d941Ssowmini dma_p, 35454045d941Ssowmini dma_p->dma_cookie.dmac_laddress, dma_p->dma_cookie.dmac_size, 35464045d941Ssowmini dma_p->ioaddr_pp, 35474045d941Ssowmini dma_p->orig_ioaddr_pp, 35484045d941Ssowmini dma_p->orig_vatopa, 35494045d941Ssowmini dma_p->alength, dma_p->alength, 35504045d941Ssowmini kaddrp, 35514045d941Ssowmini length, length)); 355244961713Sgirish 355344961713Sgirish return (NXGE_OK); 355444961713Sgirish } 355544961713Sgirish 355644961713Sgirish static void 355744961713Sgirish nxge_dma_mem_free(p_nxge_dma_common_t dma_p) 355844961713Sgirish { 355944961713Sgirish if (dma_p->dma_handle != NULL) { 356044961713Sgirish if (dma_p->ncookies) { 356144961713Sgirish (void) ddi_dma_unbind_handle(dma_p->dma_handle); 356244961713Sgirish dma_p->ncookies = 0; 356344961713Sgirish } 356444961713Sgirish ddi_dma_free_handle(&dma_p->dma_handle); 356544961713Sgirish dma_p->dma_handle = NULL; 356644961713Sgirish } 356744961713Sgirish 356844961713Sgirish if (dma_p->acc_handle != NULL) { 356944961713Sgirish ddi_dma_mem_free(&dma_p->acc_handle); 357044961713Sgirish dma_p->acc_handle = NULL; 357144961713Sgirish NPI_DMA_ACC_HANDLE_SET(dma_p, NULL); 357244961713Sgirish } 357344961713Sgirish 357444961713Sgirish #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 357544961713Sgirish if (dma_p->contig_alloc_type && 35764045d941Ssowmini dma_p->orig_kaddrp && dma_p->orig_alength) { 357744961713Sgirish NXGE_DEBUG_MSG((NULL, DMA_CTL, "nxge_dma_mem_free: " 35784045d941Ssowmini "kaddrp $%p (orig_kaddrp $%p)" 35794045d941Ssowmini "mem type %d ", 35804045d941Ssowmini "orig_alength %d " 35814045d941Ssowmini "alength 0x%x (%d)", 35824045d941Ssowmini dma_p->kaddrp, 35834045d941Ssowmini dma_p->orig_kaddrp, 35844045d941Ssowmini dma_p->contig_alloc_type, 35854045d941Ssowmini dma_p->orig_alength, 35864045d941Ssowmini dma_p->alength, dma_p->alength)); 358744961713Sgirish 358844961713Sgirish contig_mem_free(dma_p->orig_kaddrp, dma_p->orig_alength); 358944961713Sgirish dma_p->orig_alength = NULL; 359044961713Sgirish dma_p->orig_kaddrp = NULL; 359144961713Sgirish dma_p->contig_alloc_type = B_FALSE; 359244961713Sgirish } 359344961713Sgirish #endif 359444961713Sgirish dma_p->kaddrp = NULL; 359544961713Sgirish dma_p->alength = NULL; 359644961713Sgirish } 359744961713Sgirish 3598678453a8Sspeer static void 3599678453a8Sspeer nxge_dma_free_rx_data_buf(p_nxge_dma_common_t dma_p) 3600678453a8Sspeer { 3601678453a8Sspeer uint64_t kaddr; 3602678453a8Sspeer uint32_t buf_size; 3603678453a8Sspeer 3604678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, "==> nxge_dma_free_rx_data_buf")); 3605678453a8Sspeer 3606678453a8Sspeer if (dma_p->dma_handle != NULL) { 3607678453a8Sspeer if (dma_p->ncookies) { 3608678453a8Sspeer (void) ddi_dma_unbind_handle(dma_p->dma_handle); 3609678453a8Sspeer dma_p->ncookies = 0; 3610678453a8Sspeer } 3611678453a8Sspeer ddi_dma_free_handle(&dma_p->dma_handle); 3612678453a8Sspeer dma_p->dma_handle = NULL; 3613678453a8Sspeer } 3614678453a8Sspeer 3615678453a8Sspeer if (dma_p->acc_handle != NULL) { 3616678453a8Sspeer ddi_dma_mem_free(&dma_p->acc_handle); 3617678453a8Sspeer dma_p->acc_handle = NULL; 3618678453a8Sspeer NPI_DMA_ACC_HANDLE_SET(dma_p, NULL); 3619678453a8Sspeer } 3620678453a8Sspeer 3621678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, 3622678453a8Sspeer "==> nxge_dma_free_rx_data_buf: dmap $%p buf_alloc_state %d", 3623678453a8Sspeer dma_p, 3624678453a8Sspeer dma_p->buf_alloc_state)); 3625678453a8Sspeer 3626678453a8Sspeer if (!(dma_p->buf_alloc_state & BUF_ALLOCATED_WAIT_FREE)) { 3627678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, 3628678453a8Sspeer "<== nxge_dma_free_rx_data_buf: " 3629678453a8Sspeer "outstanding data buffers")); 3630678453a8Sspeer return; 3631678453a8Sspeer } 3632678453a8Sspeer 3633678453a8Sspeer #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 3634678453a8Sspeer if (dma_p->contig_alloc_type && 36354045d941Ssowmini dma_p->orig_kaddrp && dma_p->orig_alength) { 3636678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, "nxge_dma_free_rx_data_buf: " 3637678453a8Sspeer "kaddrp $%p (orig_kaddrp $%p)" 3638678453a8Sspeer "mem type %d ", 3639678453a8Sspeer "orig_alength %d " 3640678453a8Sspeer "alength 0x%x (%d)", 3641678453a8Sspeer dma_p->kaddrp, 3642678453a8Sspeer dma_p->orig_kaddrp, 3643678453a8Sspeer dma_p->contig_alloc_type, 3644678453a8Sspeer dma_p->orig_alength, 3645678453a8Sspeer dma_p->alength, dma_p->alength)); 3646678453a8Sspeer 3647678453a8Sspeer kaddr = (uint64_t)dma_p->orig_kaddrp; 3648678453a8Sspeer buf_size = dma_p->orig_alength; 3649678453a8Sspeer nxge_free_buf(CONTIG_MEM_ALLOC, kaddr, buf_size); 3650678453a8Sspeer dma_p->orig_alength = NULL; 3651678453a8Sspeer dma_p->orig_kaddrp = NULL; 3652678453a8Sspeer dma_p->contig_alloc_type = B_FALSE; 3653678453a8Sspeer dma_p->kaddrp = NULL; 3654678453a8Sspeer dma_p->alength = NULL; 3655678453a8Sspeer return; 3656678453a8Sspeer } 3657678453a8Sspeer #endif 3658678453a8Sspeer 3659678453a8Sspeer if (dma_p->kmem_alloc_type) { 3660678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, 3661678453a8Sspeer "nxge_dma_free_rx_data_buf: free kmem " 36624045d941Ssowmini "kaddrp $%p (orig_kaddrp $%p)" 36634045d941Ssowmini "alloc type %d " 36644045d941Ssowmini "orig_alength %d " 36654045d941Ssowmini "alength 0x%x (%d)", 36664045d941Ssowmini dma_p->kaddrp, 36674045d941Ssowmini dma_p->orig_kaddrp, 36684045d941Ssowmini dma_p->kmem_alloc_type, 36694045d941Ssowmini dma_p->orig_alength, 36704045d941Ssowmini dma_p->alength, dma_p->alength)); 3671678453a8Sspeer #if defined(__i386) 3672678453a8Sspeer kaddr = (uint64_t)(uint32_t)dma_p->kaddrp; 3673678453a8Sspeer #else 3674678453a8Sspeer kaddr = (uint64_t)dma_p->kaddrp; 3675678453a8Sspeer #endif 3676678453a8Sspeer buf_size = dma_p->orig_alength; 3677678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, 3678678453a8Sspeer "nxge_dma_free_rx_data_buf: free dmap $%p " 3679678453a8Sspeer "kaddr $%p buf_size %d", 3680678453a8Sspeer dma_p, 3681678453a8Sspeer kaddr, buf_size)); 3682678453a8Sspeer nxge_free_buf(KMEM_ALLOC, kaddr, buf_size); 3683678453a8Sspeer dma_p->alength = 0; 3684678453a8Sspeer dma_p->orig_alength = 0; 3685678453a8Sspeer dma_p->kaddrp = NULL; 3686678453a8Sspeer dma_p->kmem_alloc_type = B_FALSE; 3687678453a8Sspeer } 3688678453a8Sspeer 3689678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_dma_free_rx_data_buf")); 3690678453a8Sspeer } 3691678453a8Sspeer 369244961713Sgirish /* 369344961713Sgirish * nxge_m_start() -- start transmitting and receiving. 369444961713Sgirish * 369544961713Sgirish * This function is called by the MAC layer when the first 369644961713Sgirish * stream is open to prepare the hardware ready for sending 369744961713Sgirish * and transmitting packets. 369844961713Sgirish */ 369944961713Sgirish static int 370044961713Sgirish nxge_m_start(void *arg) 370144961713Sgirish { 370244961713Sgirish p_nxge_t nxgep = (p_nxge_t)arg; 370344961713Sgirish 370444961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_start")); 370544961713Sgirish 37066f157acbSml if (nxge_peu_reset_enable && !nxgep->nxge_link_poll_timerid) { 37076f157acbSml (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 37086f157acbSml } 37096f157acbSml 371044961713Sgirish MUTEX_ENTER(nxgep->genlock); 371114ea4bb7Ssd if (nxge_init(nxgep) != NXGE_OK) { 371244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 37134045d941Ssowmini "<== nxge_m_start: initialization failed")); 371444961713Sgirish MUTEX_EXIT(nxgep->genlock); 371544961713Sgirish return (EIO); 371644961713Sgirish } 371744961713Sgirish 371814ea4bb7Ssd if (nxgep->nxge_mac_state == NXGE_MAC_STARTED) 371914ea4bb7Ssd goto nxge_m_start_exit; 372044961713Sgirish /* 372144961713Sgirish * Start timer to check the system error and tx hangs 372244961713Sgirish */ 3723678453a8Sspeer if (!isLDOMguest(nxgep)) 3724678453a8Sspeer nxgep->nxge_timerid = nxge_start_timer(nxgep, 3725678453a8Sspeer nxge_check_hw_state, NXGE_CHECK_TIMER); 3726678453a8Sspeer #if defined(sun4v) 3727678453a8Sspeer else 3728678453a8Sspeer nxge_hio_start_timer(nxgep); 3729678453a8Sspeer #endif 373044961713Sgirish 3731a3c5bd6dSspeer nxgep->link_notify = B_TRUE; 3732a3c5bd6dSspeer 373344961713Sgirish nxgep->nxge_mac_state = NXGE_MAC_STARTED; 373444961713Sgirish 373514ea4bb7Ssd nxge_m_start_exit: 373644961713Sgirish MUTEX_EXIT(nxgep->genlock); 373744961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_start")); 373844961713Sgirish return (0); 373944961713Sgirish } 374044961713Sgirish 374144961713Sgirish /* 374244961713Sgirish * nxge_m_stop(): stop transmitting and receiving. 374344961713Sgirish */ 374444961713Sgirish static void 374544961713Sgirish nxge_m_stop(void *arg) 374644961713Sgirish { 374744961713Sgirish p_nxge_t nxgep = (p_nxge_t)arg; 374844961713Sgirish 374944961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_stop")); 375044961713Sgirish 3751d7cf53fcSmisaki Miyashita MUTEX_ENTER(nxgep->genlock); 3752d7cf53fcSmisaki Miyashita nxgep->nxge_mac_state = NXGE_MAC_STOPPING; 3753d7cf53fcSmisaki Miyashita 375444961713Sgirish if (nxgep->nxge_timerid) { 375544961713Sgirish nxge_stop_timer(nxgep, nxgep->nxge_timerid); 375644961713Sgirish nxgep->nxge_timerid = 0; 375744961713Sgirish } 3758a3c5bd6dSspeer 375944961713Sgirish nxge_uninit(nxgep); 376044961713Sgirish 376144961713Sgirish nxgep->nxge_mac_state = NXGE_MAC_STOPPED; 376244961713Sgirish 376344961713Sgirish MUTEX_EXIT(nxgep->genlock); 376444961713Sgirish 376544961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_stop")); 376644961713Sgirish } 376744961713Sgirish 376844961713Sgirish static int 376944961713Sgirish nxge_m_unicst(void *arg, const uint8_t *macaddr) 377044961713Sgirish { 377144961713Sgirish p_nxge_t nxgep = (p_nxge_t)arg; 377244961713Sgirish struct ether_addr addrp; 377344961713Sgirish 377444961713Sgirish NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_m_unicst")); 377544961713Sgirish 377644961713Sgirish bcopy(macaddr, (uint8_t *)&addrp, ETHERADDRL); 377744961713Sgirish if (nxge_set_mac_addr(nxgep, &addrp)) { 377844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 37794045d941Ssowmini "<== nxge_m_unicst: set unitcast failed")); 378044961713Sgirish return (EINVAL); 378144961713Sgirish } 378244961713Sgirish 378344961713Sgirish NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_m_unicst")); 378444961713Sgirish 378544961713Sgirish return (0); 378644961713Sgirish } 378744961713Sgirish 378844961713Sgirish static int 378944961713Sgirish nxge_m_multicst(void *arg, boolean_t add, const uint8_t *mca) 379044961713Sgirish { 379144961713Sgirish p_nxge_t nxgep = (p_nxge_t)arg; 379244961713Sgirish struct ether_addr addrp; 379344961713Sgirish 379444961713Sgirish NXGE_DEBUG_MSG((nxgep, MAC_CTL, 37954045d941Ssowmini "==> nxge_m_multicst: add %d", add)); 379644961713Sgirish 379744961713Sgirish bcopy(mca, (uint8_t *)&addrp, ETHERADDRL); 379844961713Sgirish if (add) { 379944961713Sgirish if (nxge_add_mcast_addr(nxgep, &addrp)) { 380044961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 38014045d941Ssowmini "<== nxge_m_multicst: add multicast failed")); 380244961713Sgirish return (EINVAL); 380344961713Sgirish } 380444961713Sgirish } else { 380544961713Sgirish if (nxge_del_mcast_addr(nxgep, &addrp)) { 380644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 38074045d941Ssowmini "<== nxge_m_multicst: del multicast failed")); 380844961713Sgirish return (EINVAL); 380944961713Sgirish } 381044961713Sgirish } 381144961713Sgirish 381244961713Sgirish NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_m_multicst")); 381344961713Sgirish 381444961713Sgirish return (0); 381544961713Sgirish } 381644961713Sgirish 381744961713Sgirish static int 381844961713Sgirish nxge_m_promisc(void *arg, boolean_t on) 381944961713Sgirish { 382044961713Sgirish p_nxge_t nxgep = (p_nxge_t)arg; 382144961713Sgirish 382244961713Sgirish NXGE_DEBUG_MSG((nxgep, MAC_CTL, 38234045d941Ssowmini "==> nxge_m_promisc: on %d", on)); 382444961713Sgirish 382544961713Sgirish if (nxge_set_promisc(nxgep, on)) { 382644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 38274045d941Ssowmini "<== nxge_m_promisc: set promisc failed")); 382844961713Sgirish return (EINVAL); 382944961713Sgirish } 383044961713Sgirish 383144961713Sgirish NXGE_DEBUG_MSG((nxgep, MAC_CTL, 38324045d941Ssowmini "<== nxge_m_promisc: on %d", on)); 383344961713Sgirish 383444961713Sgirish return (0); 383544961713Sgirish } 383644961713Sgirish 383744961713Sgirish static void 383844961713Sgirish nxge_m_ioctl(void *arg, queue_t *wq, mblk_t *mp) 383944961713Sgirish { 384044961713Sgirish p_nxge_t nxgep = (p_nxge_t)arg; 384156d930aeSspeer struct iocblk *iocp; 384244961713Sgirish boolean_t need_privilege; 384344961713Sgirish int err; 384444961713Sgirish int cmd; 384544961713Sgirish 384644961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_ioctl")); 384744961713Sgirish 384844961713Sgirish iocp = (struct iocblk *)mp->b_rptr; 384944961713Sgirish iocp->ioc_error = 0; 385044961713Sgirish need_privilege = B_TRUE; 385144961713Sgirish cmd = iocp->ioc_cmd; 385244961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_ioctl: cmd 0x%08x", cmd)); 385344961713Sgirish switch (cmd) { 385444961713Sgirish default: 385544961713Sgirish miocnak(wq, mp, 0, EINVAL); 385644961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_ioctl: invalid")); 385744961713Sgirish return; 385844961713Sgirish 385944961713Sgirish case LB_GET_INFO_SIZE: 386044961713Sgirish case LB_GET_INFO: 386144961713Sgirish case LB_GET_MODE: 386244961713Sgirish need_privilege = B_FALSE; 386344961713Sgirish break; 386444961713Sgirish case LB_SET_MODE: 386544961713Sgirish break; 386644961713Sgirish 386744961713Sgirish 386844961713Sgirish case NXGE_GET_MII: 386944961713Sgirish case NXGE_PUT_MII: 387044961713Sgirish case NXGE_GET64: 387144961713Sgirish case NXGE_PUT64: 387244961713Sgirish case NXGE_GET_TX_RING_SZ: 387344961713Sgirish case NXGE_GET_TX_DESC: 387444961713Sgirish case NXGE_TX_SIDE_RESET: 387544961713Sgirish case NXGE_RX_SIDE_RESET: 387644961713Sgirish case NXGE_GLOBAL_RESET: 387744961713Sgirish case NXGE_RESET_MAC: 387844961713Sgirish case NXGE_TX_REGS_DUMP: 387944961713Sgirish case NXGE_RX_REGS_DUMP: 388044961713Sgirish case NXGE_INT_REGS_DUMP: 388144961713Sgirish case NXGE_VIR_INT_REGS_DUMP: 388244961713Sgirish case NXGE_PUT_TCAM: 388344961713Sgirish case NXGE_GET_TCAM: 388444961713Sgirish case NXGE_RTRACE: 388544961713Sgirish case NXGE_RDUMP: 388644961713Sgirish 388744961713Sgirish need_privilege = B_FALSE; 388844961713Sgirish break; 388944961713Sgirish case NXGE_INJECT_ERR: 389044961713Sgirish cmn_err(CE_NOTE, "!nxge_m_ioctl: Inject error\n"); 389144961713Sgirish nxge_err_inject(nxgep, wq, mp); 389244961713Sgirish break; 389344961713Sgirish } 389444961713Sgirish 389544961713Sgirish if (need_privilege) { 389656d930aeSspeer err = secpolicy_net_config(iocp->ioc_cr, B_FALSE); 389744961713Sgirish if (err != 0) { 389844961713Sgirish miocnak(wq, mp, 0, err); 389944961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 39004045d941Ssowmini "<== nxge_m_ioctl: no priv")); 390144961713Sgirish return; 390244961713Sgirish } 390344961713Sgirish } 390444961713Sgirish 390544961713Sgirish switch (cmd) { 390644961713Sgirish 390744961713Sgirish case LB_GET_MODE: 390844961713Sgirish case LB_SET_MODE: 390944961713Sgirish case LB_GET_INFO_SIZE: 391044961713Sgirish case LB_GET_INFO: 391144961713Sgirish nxge_loopback_ioctl(nxgep, wq, mp, iocp); 391244961713Sgirish break; 391344961713Sgirish 391444961713Sgirish case NXGE_GET_MII: 391544961713Sgirish case NXGE_PUT_MII: 391644961713Sgirish case NXGE_PUT_TCAM: 391744961713Sgirish case NXGE_GET_TCAM: 391844961713Sgirish case NXGE_GET64: 391944961713Sgirish case NXGE_PUT64: 392044961713Sgirish case NXGE_GET_TX_RING_SZ: 392144961713Sgirish case NXGE_GET_TX_DESC: 392244961713Sgirish case NXGE_TX_SIDE_RESET: 392344961713Sgirish case NXGE_RX_SIDE_RESET: 392444961713Sgirish case NXGE_GLOBAL_RESET: 392544961713Sgirish case NXGE_RESET_MAC: 392644961713Sgirish case NXGE_TX_REGS_DUMP: 392744961713Sgirish case NXGE_RX_REGS_DUMP: 392844961713Sgirish case NXGE_INT_REGS_DUMP: 392944961713Sgirish case NXGE_VIR_INT_REGS_DUMP: 393044961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 39314045d941Ssowmini "==> nxge_m_ioctl: cmd 0x%x", cmd)); 393244961713Sgirish nxge_hw_ioctl(nxgep, wq, mp, iocp); 393344961713Sgirish break; 393444961713Sgirish } 393544961713Sgirish 393644961713Sgirish NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_ioctl")); 393744961713Sgirish } 393844961713Sgirish 393944961713Sgirish extern void nxge_rx_hw_blank(void *arg, time_t ticks, uint_t count); 394044961713Sgirish 394144961713Sgirish static void 394244961713Sgirish nxge_m_resources(void *arg) 394344961713Sgirish { 394444961713Sgirish p_nxge_t nxgep = arg; 394544961713Sgirish mac_rx_fifo_t mrf; 3946678453a8Sspeer 3947678453a8Sspeer nxge_grp_set_t *set = &nxgep->rx_set; 3948678453a8Sspeer uint8_t rdc; 3949678453a8Sspeer 3950678453a8Sspeer rx_rcr_ring_t *ring; 395144961713Sgirish 395244961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_m_resources")); 395344961713Sgirish 395444961713Sgirish MUTEX_ENTER(nxgep->genlock); 395514ea4bb7Ssd 3956678453a8Sspeer if (set->owned.map == 0) { 3957678453a8Sspeer NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 3958678453a8Sspeer "nxge_m_resources: no receive resources")); 3959678453a8Sspeer goto nxge_m_resources_exit; 3960678453a8Sspeer } 3961678453a8Sspeer 396214ea4bb7Ssd /* 396358324dfcSspeer * CR 6492541 Check to see if the drv_state has been initialized, 396414ea4bb7Ssd * if not * call nxge_init(). 396514ea4bb7Ssd */ 396614ea4bb7Ssd if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 3967678453a8Sspeer if (nxge_init(nxgep) != NXGE_OK) 396814ea4bb7Ssd goto nxge_m_resources_exit; 396914ea4bb7Ssd } 397014ea4bb7Ssd 397144961713Sgirish mrf.mrf_type = MAC_RX_FIFO; 397244961713Sgirish mrf.mrf_blank = nxge_rx_hw_blank; 397344961713Sgirish mrf.mrf_arg = (void *)nxgep; 397444961713Sgirish 397544961713Sgirish mrf.mrf_normal_blank_time = 128; 397644961713Sgirish mrf.mrf_normal_pkt_count = 8; 397744961713Sgirish 397814ea4bb7Ssd /* 397914ea4bb7Ssd * Export our receive resources to the MAC layer. 398014ea4bb7Ssd */ 3981678453a8Sspeer for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 3982678453a8Sspeer if ((1 << rdc) & set->owned.map) { 3983678453a8Sspeer ring = nxgep->rx_rcr_rings->rcr_rings[rdc]; 3984678453a8Sspeer if (ring == 0) { 3985678453a8Sspeer /* 3986678453a8Sspeer * This is a big deal only if we are 3987678453a8Sspeer * *not* in an LDOMs environment. 3988678453a8Sspeer */ 3989678453a8Sspeer if (nxgep->environs == SOLARIS_DOMAIN) { 3990678453a8Sspeer cmn_err(CE_NOTE, 3991678453a8Sspeer "==> nxge_m_resources: " 3992678453a8Sspeer "ring %d == 0", rdc); 3993678453a8Sspeer } 3994678453a8Sspeer continue; 3995678453a8Sspeer } 3996678453a8Sspeer ring->rcr_mac_handle = mac_resource_add 3997678453a8Sspeer (nxgep->mach, (mac_resource_t *)&mrf); 399844961713Sgirish 3999678453a8Sspeer NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4000678453a8Sspeer "==> nxge_m_resources: RDC %d RCR %p MAC handle %p", 4001678453a8Sspeer rdc, ring, ring->rcr_mac_handle)); 4002678453a8Sspeer } 400344961713Sgirish } 400444961713Sgirish 400514ea4bb7Ssd nxge_m_resources_exit: 400644961713Sgirish MUTEX_EXIT(nxgep->genlock); 400744961713Sgirish NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_m_resources")); 400844961713Sgirish } 400944961713Sgirish 4010678453a8Sspeer void 401158324dfcSspeer nxge_mmac_kstat_update(p_nxge_t nxgep, mac_addr_slot_t slot, boolean_t factory) 401258324dfcSspeer { 401358324dfcSspeer p_nxge_mmac_stats_t mmac_stats; 401458324dfcSspeer int i; 401558324dfcSspeer nxge_mmac_t *mmac_info; 401658324dfcSspeer 401758324dfcSspeer mmac_info = &nxgep->nxge_mmac_info; 401858324dfcSspeer 401958324dfcSspeer mmac_stats = &nxgep->statsp->mmac_stats; 402058324dfcSspeer mmac_stats->mmac_max_cnt = mmac_info->num_mmac; 402158324dfcSspeer mmac_stats->mmac_avail_cnt = mmac_info->naddrfree; 402258324dfcSspeer 402358324dfcSspeer for (i = 0; i < ETHERADDRL; i++) { 402458324dfcSspeer if (factory) { 402558324dfcSspeer mmac_stats->mmac_avail_pool[slot-1].ether_addr_octet[i] 40264045d941Ssowmini = mmac_info->factory_mac_pool[slot][ 40274045d941Ssowmini (ETHERADDRL-1) - i]; 402858324dfcSspeer } else { 402958324dfcSspeer mmac_stats->mmac_avail_pool[slot-1].ether_addr_octet[i] 40304045d941Ssowmini = mmac_info->mac_pool[slot].addr[ 40314045d941Ssowmini (ETHERADDRL - 1) - i]; 403258324dfcSspeer } 403358324dfcSspeer } 403458324dfcSspeer } 403558324dfcSspeer 403658324dfcSspeer /* 403758324dfcSspeer * nxge_altmac_set() -- Set an alternate MAC address 403858324dfcSspeer */ 403958324dfcSspeer static int 404058324dfcSspeer nxge_altmac_set(p_nxge_t nxgep, uint8_t *maddr, mac_addr_slot_t slot) 404158324dfcSspeer { 404258324dfcSspeer uint8_t addrn; 404358324dfcSspeer uint8_t portn; 404458324dfcSspeer npi_mac_addr_t altmac; 40457b9fa28bSspeer hostinfo_t mac_rdc; 40467b9fa28bSspeer p_nxge_class_pt_cfg_t clscfgp; 404758324dfcSspeer 404858324dfcSspeer altmac.w2 = ((uint16_t)maddr[0] << 8) | ((uint16_t)maddr[1] & 0x0ff); 404958324dfcSspeer altmac.w1 = ((uint16_t)maddr[2] << 8) | ((uint16_t)maddr[3] & 0x0ff); 405058324dfcSspeer altmac.w0 = ((uint16_t)maddr[4] << 8) | ((uint16_t)maddr[5] & 0x0ff); 405158324dfcSspeer 405258324dfcSspeer portn = nxgep->mac.portnum; 405358324dfcSspeer addrn = (uint8_t)slot - 1; 405458324dfcSspeer 405558324dfcSspeer if (npi_mac_altaddr_entry(nxgep->npi_handle, OP_SET, portn, 40564045d941Ssowmini addrn, &altmac) != NPI_SUCCESS) 405758324dfcSspeer return (EIO); 40587b9fa28bSspeer 40597b9fa28bSspeer /* 40607b9fa28bSspeer * Set the rdc table number for the host info entry 40617b9fa28bSspeer * for this mac address slot. 40627b9fa28bSspeer */ 40637b9fa28bSspeer clscfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 40647b9fa28bSspeer mac_rdc.value = 0; 40657b9fa28bSspeer mac_rdc.bits.w0.rdc_tbl_num = clscfgp->mac_host_info[addrn].rdctbl; 40667b9fa28bSspeer mac_rdc.bits.w0.mac_pref = clscfgp->mac_host_info[addrn].mpr_npr; 40677b9fa28bSspeer 40687b9fa28bSspeer if (npi_mac_hostinfo_entry(nxgep->npi_handle, OP_SET, 40697b9fa28bSspeer nxgep->function_num, addrn, &mac_rdc) != NPI_SUCCESS) { 40707b9fa28bSspeer return (EIO); 40717b9fa28bSspeer } 40727b9fa28bSspeer 407358324dfcSspeer /* 407458324dfcSspeer * Enable comparison with the alternate MAC address. 407558324dfcSspeer * While the first alternate addr is enabled by bit 1 of register 407658324dfcSspeer * BMAC_ALTAD_CMPEN, it is enabled by bit 0 of register 407758324dfcSspeer * XMAC_ADDR_CMPEN, so slot needs to be converted to addrn 407858324dfcSspeer * accordingly before calling npi_mac_altaddr_entry. 407958324dfcSspeer */ 408058324dfcSspeer if (portn == XMAC_PORT_0 || portn == XMAC_PORT_1) 408158324dfcSspeer addrn = (uint8_t)slot - 1; 408258324dfcSspeer else 408358324dfcSspeer addrn = (uint8_t)slot; 408458324dfcSspeer 408558324dfcSspeer if (npi_mac_altaddr_enable(nxgep->npi_handle, portn, addrn) 40864045d941Ssowmini != NPI_SUCCESS) 408758324dfcSspeer return (EIO); 408858324dfcSspeer 408958324dfcSspeer return (0); 409058324dfcSspeer } 409158324dfcSspeer 409258324dfcSspeer /* 409358324dfcSspeer * nxeg_m_mmac_add() - find an unused address slot, set the address 409458324dfcSspeer * value to the one specified, enable the port to start filtering on 409558324dfcSspeer * the new MAC address. Returns 0 on success. 409658324dfcSspeer */ 4097678453a8Sspeer int 409858324dfcSspeer nxge_m_mmac_add(void *arg, mac_multi_addr_t *maddr) 409958324dfcSspeer { 410058324dfcSspeer p_nxge_t nxgep = arg; 410158324dfcSspeer mac_addr_slot_t slot; 410258324dfcSspeer nxge_mmac_t *mmac_info; 410358324dfcSspeer int err; 410458324dfcSspeer nxge_status_t status; 410558324dfcSspeer 410658324dfcSspeer mutex_enter(nxgep->genlock); 410758324dfcSspeer 410858324dfcSspeer /* 410958324dfcSspeer * Make sure that nxge is initialized, if _start() has 411058324dfcSspeer * not been called. 411158324dfcSspeer */ 411258324dfcSspeer if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 411358324dfcSspeer status = nxge_init(nxgep); 411458324dfcSspeer if (status != NXGE_OK) { 411558324dfcSspeer mutex_exit(nxgep->genlock); 411658324dfcSspeer return (ENXIO); 411758324dfcSspeer } 411858324dfcSspeer } 411958324dfcSspeer 412058324dfcSspeer mmac_info = &nxgep->nxge_mmac_info; 412158324dfcSspeer if (mmac_info->naddrfree == 0) { 412258324dfcSspeer mutex_exit(nxgep->genlock); 412358324dfcSspeer return (ENOSPC); 412458324dfcSspeer } 412558324dfcSspeer if (!mac_unicst_verify(nxgep->mach, maddr->mma_addr, 41264045d941Ssowmini maddr->mma_addrlen)) { 412758324dfcSspeer mutex_exit(nxgep->genlock); 412858324dfcSspeer return (EINVAL); 412958324dfcSspeer } 413058324dfcSspeer /* 413158324dfcSspeer * Search for the first available slot. Because naddrfree 413258324dfcSspeer * is not zero, we are guaranteed to find one. 413358324dfcSspeer * Slot 0 is for unique (primary) MAC. The first alternate 413458324dfcSspeer * MAC slot is slot 1. 413558324dfcSspeer * Each of the first two ports of Neptune has 16 alternate 4136678453a8Sspeer * MAC slots but only the first 7 (of 15) slots have assigned factory 413758324dfcSspeer * MAC addresses. We first search among the slots without bundled 413858324dfcSspeer * factory MACs. If we fail to find one in that range, then we 413958324dfcSspeer * search the slots with bundled factory MACs. A factory MAC 414058324dfcSspeer * will be wasted while the slot is used with a user MAC address. 414158324dfcSspeer * But the slot could be used by factory MAC again after calling 414258324dfcSspeer * nxge_m_mmac_remove and nxge_m_mmac_reserve. 414358324dfcSspeer */ 414458324dfcSspeer if (mmac_info->num_factory_mmac < mmac_info->num_mmac) { 414558324dfcSspeer for (slot = mmac_info->num_factory_mmac + 1; 41464045d941Ssowmini slot <= mmac_info->num_mmac; slot++) { 414758324dfcSspeer if (!(mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED)) 414858324dfcSspeer break; 414958324dfcSspeer } 415058324dfcSspeer if (slot > mmac_info->num_mmac) { 415158324dfcSspeer for (slot = 1; slot <= mmac_info->num_factory_mmac; 41524045d941Ssowmini slot++) { 415358324dfcSspeer if (!(mmac_info->mac_pool[slot].flags 41544045d941Ssowmini & MMAC_SLOT_USED)) 415558324dfcSspeer break; 415658324dfcSspeer } 415758324dfcSspeer } 415858324dfcSspeer } else { 415958324dfcSspeer for (slot = 1; slot <= mmac_info->num_mmac; slot++) { 416058324dfcSspeer if (!(mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED)) 416158324dfcSspeer break; 416258324dfcSspeer } 416358324dfcSspeer } 416458324dfcSspeer ASSERT(slot <= mmac_info->num_mmac); 416558324dfcSspeer if ((err = nxge_altmac_set(nxgep, maddr->mma_addr, slot)) != 0) { 416658324dfcSspeer mutex_exit(nxgep->genlock); 416758324dfcSspeer return (err); 416858324dfcSspeer } 416958324dfcSspeer bcopy(maddr->mma_addr, mmac_info->mac_pool[slot].addr, ETHERADDRL); 417058324dfcSspeer mmac_info->mac_pool[slot].flags |= MMAC_SLOT_USED; 417158324dfcSspeer mmac_info->mac_pool[slot].flags &= ~MMAC_VENDOR_ADDR; 417258324dfcSspeer mmac_info->naddrfree--; 417358324dfcSspeer nxge_mmac_kstat_update(nxgep, slot, B_FALSE); 417458324dfcSspeer 417558324dfcSspeer maddr->mma_slot = slot; 417658324dfcSspeer 417758324dfcSspeer mutex_exit(nxgep->genlock); 417858324dfcSspeer return (0); 417958324dfcSspeer } 418058324dfcSspeer 418158324dfcSspeer /* 418258324dfcSspeer * This function reserves an unused slot and programs the slot and the HW 418358324dfcSspeer * with a factory mac address. 418458324dfcSspeer */ 418558324dfcSspeer static int 418658324dfcSspeer nxge_m_mmac_reserve(void *arg, mac_multi_addr_t *maddr) 418758324dfcSspeer { 418858324dfcSspeer p_nxge_t nxgep = arg; 418958324dfcSspeer mac_addr_slot_t slot; 419058324dfcSspeer nxge_mmac_t *mmac_info; 419158324dfcSspeer int err; 419258324dfcSspeer nxge_status_t status; 419358324dfcSspeer 419458324dfcSspeer mutex_enter(nxgep->genlock); 419558324dfcSspeer 419658324dfcSspeer /* 419758324dfcSspeer * Make sure that nxge is initialized, if _start() has 419858324dfcSspeer * not been called. 419958324dfcSspeer */ 420058324dfcSspeer if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 420158324dfcSspeer status = nxge_init(nxgep); 420258324dfcSspeer if (status != NXGE_OK) { 420358324dfcSspeer mutex_exit(nxgep->genlock); 420458324dfcSspeer return (ENXIO); 420558324dfcSspeer } 420658324dfcSspeer } 420758324dfcSspeer 420858324dfcSspeer mmac_info = &nxgep->nxge_mmac_info; 420958324dfcSspeer if (mmac_info->naddrfree == 0) { 421058324dfcSspeer mutex_exit(nxgep->genlock); 421158324dfcSspeer return (ENOSPC); 421258324dfcSspeer } 421358324dfcSspeer 421458324dfcSspeer slot = maddr->mma_slot; 421558324dfcSspeer if (slot == -1) { /* -1: Take the first available slot */ 421658324dfcSspeer for (slot = 1; slot <= mmac_info->num_factory_mmac; slot++) { 421758324dfcSspeer if (!(mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED)) 421858324dfcSspeer break; 421958324dfcSspeer } 422058324dfcSspeer if (slot > mmac_info->num_factory_mmac) { 422158324dfcSspeer mutex_exit(nxgep->genlock); 422258324dfcSspeer return (ENOSPC); 422358324dfcSspeer } 422458324dfcSspeer } 422558324dfcSspeer if (slot < 1 || slot > mmac_info->num_factory_mmac) { 422658324dfcSspeer /* 422758324dfcSspeer * Do not support factory MAC at a slot greater than 422858324dfcSspeer * num_factory_mmac even when there are available factory 422958324dfcSspeer * MAC addresses because the alternate MACs are bundled with 423058324dfcSspeer * slot[1] through slot[num_factory_mmac] 423158324dfcSspeer */ 423258324dfcSspeer mutex_exit(nxgep->genlock); 423358324dfcSspeer return (EINVAL); 423458324dfcSspeer } 423558324dfcSspeer if (mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED) { 423658324dfcSspeer mutex_exit(nxgep->genlock); 423758324dfcSspeer return (EBUSY); 423858324dfcSspeer } 423958324dfcSspeer /* Verify the address to be reserved */ 424058324dfcSspeer if (!mac_unicst_verify(nxgep->mach, 42414045d941Ssowmini mmac_info->factory_mac_pool[slot], ETHERADDRL)) { 424258324dfcSspeer mutex_exit(nxgep->genlock); 424358324dfcSspeer return (EINVAL); 424458324dfcSspeer } 424558324dfcSspeer if (err = nxge_altmac_set(nxgep, 42464045d941Ssowmini mmac_info->factory_mac_pool[slot], slot)) { 424758324dfcSspeer mutex_exit(nxgep->genlock); 424858324dfcSspeer return (err); 424958324dfcSspeer } 425058324dfcSspeer bcopy(mmac_info->factory_mac_pool[slot], maddr->mma_addr, ETHERADDRL); 425158324dfcSspeer mmac_info->mac_pool[slot].flags |= MMAC_SLOT_USED | MMAC_VENDOR_ADDR; 425258324dfcSspeer mmac_info->naddrfree--; 425358324dfcSspeer 425458324dfcSspeer nxge_mmac_kstat_update(nxgep, slot, B_TRUE); 425558324dfcSspeer mutex_exit(nxgep->genlock); 425658324dfcSspeer 425758324dfcSspeer /* Pass info back to the caller */ 425858324dfcSspeer maddr->mma_slot = slot; 425958324dfcSspeer maddr->mma_addrlen = ETHERADDRL; 426058324dfcSspeer maddr->mma_flags = MMAC_SLOT_USED | MMAC_VENDOR_ADDR; 426158324dfcSspeer 426258324dfcSspeer return (0); 426358324dfcSspeer } 426458324dfcSspeer 426558324dfcSspeer /* 426658324dfcSspeer * Remove the specified mac address and update the HW not to filter 426758324dfcSspeer * the mac address anymore. 426858324dfcSspeer */ 4269678453a8Sspeer int 427058324dfcSspeer nxge_m_mmac_remove(void *arg, mac_addr_slot_t slot) 427158324dfcSspeer { 427258324dfcSspeer p_nxge_t nxgep = arg; 427358324dfcSspeer nxge_mmac_t *mmac_info; 427458324dfcSspeer uint8_t addrn; 427558324dfcSspeer uint8_t portn; 427658324dfcSspeer int err = 0; 427758324dfcSspeer nxge_status_t status; 427858324dfcSspeer 427958324dfcSspeer mutex_enter(nxgep->genlock); 428058324dfcSspeer 428158324dfcSspeer /* 428258324dfcSspeer * Make sure that nxge is initialized, if _start() has 428358324dfcSspeer * not been called. 428458324dfcSspeer */ 428558324dfcSspeer if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 428658324dfcSspeer status = nxge_init(nxgep); 428758324dfcSspeer if (status != NXGE_OK) { 428858324dfcSspeer mutex_exit(nxgep->genlock); 428958324dfcSspeer return (ENXIO); 429058324dfcSspeer } 429158324dfcSspeer } 429258324dfcSspeer 429358324dfcSspeer mmac_info = &nxgep->nxge_mmac_info; 429458324dfcSspeer if (slot < 1 || slot > mmac_info->num_mmac) { 429558324dfcSspeer mutex_exit(nxgep->genlock); 429658324dfcSspeer return (EINVAL); 429758324dfcSspeer } 429858324dfcSspeer 429958324dfcSspeer portn = nxgep->mac.portnum; 430058324dfcSspeer if (portn == XMAC_PORT_0 || portn == XMAC_PORT_1) 430158324dfcSspeer addrn = (uint8_t)slot - 1; 430258324dfcSspeer else 430358324dfcSspeer addrn = (uint8_t)slot; 430458324dfcSspeer 430558324dfcSspeer if (mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED) { 430658324dfcSspeer if (npi_mac_altaddr_disable(nxgep->npi_handle, portn, addrn) 43074045d941Ssowmini == NPI_SUCCESS) { 430858324dfcSspeer mmac_info->naddrfree++; 430958324dfcSspeer mmac_info->mac_pool[slot].flags &= ~MMAC_SLOT_USED; 431058324dfcSspeer /* 431158324dfcSspeer * Regardless if the MAC we just stopped filtering 431258324dfcSspeer * is a user addr or a facory addr, we must set 431358324dfcSspeer * the MMAC_VENDOR_ADDR flag if this slot has an 431458324dfcSspeer * associated factory MAC to indicate that a factory 431558324dfcSspeer * MAC is available. 431658324dfcSspeer */ 431758324dfcSspeer if (slot <= mmac_info->num_factory_mmac) { 431858324dfcSspeer mmac_info->mac_pool[slot].flags 43194045d941Ssowmini |= MMAC_VENDOR_ADDR; 432058324dfcSspeer } 432158324dfcSspeer /* 432258324dfcSspeer * Clear mac_pool[slot].addr so that kstat shows 0 432358324dfcSspeer * alternate MAC address if the slot is not used. 432458324dfcSspeer * (But nxge_m_mmac_get returns the factory MAC even 432558324dfcSspeer * when the slot is not used!) 432658324dfcSspeer */ 432758324dfcSspeer bzero(mmac_info->mac_pool[slot].addr, ETHERADDRL); 432858324dfcSspeer nxge_mmac_kstat_update(nxgep, slot, B_FALSE); 432958324dfcSspeer } else { 433058324dfcSspeer err = EIO; 433158324dfcSspeer } 433258324dfcSspeer } else { 433358324dfcSspeer err = EINVAL; 433458324dfcSspeer } 433558324dfcSspeer 433658324dfcSspeer mutex_exit(nxgep->genlock); 433758324dfcSspeer return (err); 433858324dfcSspeer } 433958324dfcSspeer 434058324dfcSspeer /* 434158324dfcSspeer * Modify a mac address added by nxge_m_mmac_add or nxge_m_mmac_reserve(). 434258324dfcSspeer */ 434358324dfcSspeer static int 434458324dfcSspeer nxge_m_mmac_modify(void *arg, mac_multi_addr_t *maddr) 434558324dfcSspeer { 434658324dfcSspeer p_nxge_t nxgep = arg; 434758324dfcSspeer mac_addr_slot_t slot; 434858324dfcSspeer nxge_mmac_t *mmac_info; 434958324dfcSspeer int err = 0; 435058324dfcSspeer nxge_status_t status; 435158324dfcSspeer 435258324dfcSspeer if (!mac_unicst_verify(nxgep->mach, maddr->mma_addr, 43534045d941Ssowmini maddr->mma_addrlen)) 435458324dfcSspeer return (EINVAL); 435558324dfcSspeer 435658324dfcSspeer slot = maddr->mma_slot; 435758324dfcSspeer 435858324dfcSspeer mutex_enter(nxgep->genlock); 435958324dfcSspeer 436058324dfcSspeer /* 436158324dfcSspeer * Make sure that nxge is initialized, if _start() has 436258324dfcSspeer * not been called. 436358324dfcSspeer */ 436458324dfcSspeer if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 436558324dfcSspeer status = nxge_init(nxgep); 436658324dfcSspeer if (status != NXGE_OK) { 436758324dfcSspeer mutex_exit(nxgep->genlock); 436858324dfcSspeer return (ENXIO); 436958324dfcSspeer } 437058324dfcSspeer } 437158324dfcSspeer 437258324dfcSspeer mmac_info = &nxgep->nxge_mmac_info; 437358324dfcSspeer if (slot < 1 || slot > mmac_info->num_mmac) { 437458324dfcSspeer mutex_exit(nxgep->genlock); 437558324dfcSspeer return (EINVAL); 437658324dfcSspeer } 437758324dfcSspeer if (mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED) { 437858324dfcSspeer if ((err = nxge_altmac_set(nxgep, maddr->mma_addr, slot)) 43794045d941Ssowmini != 0) { 438058324dfcSspeer bcopy(maddr->mma_addr, mmac_info->mac_pool[slot].addr, 43814045d941Ssowmini ETHERADDRL); 438258324dfcSspeer /* 438358324dfcSspeer * Assume that the MAC passed down from the caller 438458324dfcSspeer * is not a factory MAC address (The user should 438558324dfcSspeer * call mmac_remove followed by mmac_reserve if 438658324dfcSspeer * he wants to use the factory MAC for this slot). 438758324dfcSspeer */ 438858324dfcSspeer mmac_info->mac_pool[slot].flags &= ~MMAC_VENDOR_ADDR; 438958324dfcSspeer nxge_mmac_kstat_update(nxgep, slot, B_FALSE); 439058324dfcSspeer } 439158324dfcSspeer } else { 439258324dfcSspeer err = EINVAL; 439358324dfcSspeer } 439458324dfcSspeer mutex_exit(nxgep->genlock); 439558324dfcSspeer return (err); 439658324dfcSspeer } 439758324dfcSspeer 439858324dfcSspeer /* 439958324dfcSspeer * nxge_m_mmac_get() - Get the MAC address and other information 440058324dfcSspeer * related to the slot. mma_flags should be set to 0 in the call. 440158324dfcSspeer * Note: although kstat shows MAC address as zero when a slot is 440258324dfcSspeer * not used, Crossbow expects nxge_m_mmac_get to copy factory MAC 440358324dfcSspeer * to the caller as long as the slot is not using a user MAC address. 440458324dfcSspeer * The following table shows the rules, 440558324dfcSspeer * 440658324dfcSspeer * USED VENDOR mma_addr 440758324dfcSspeer * ------------------------------------------------------------ 440858324dfcSspeer * (1) Slot uses a user MAC: yes no user MAC 440958324dfcSspeer * (2) Slot uses a factory MAC: yes yes factory MAC 441058324dfcSspeer * (3) Slot is not used but is 441158324dfcSspeer * factory MAC capable: no yes factory MAC 441258324dfcSspeer * (4) Slot is not used and is 441358324dfcSspeer * not factory MAC capable: no no 0 441458324dfcSspeer * ------------------------------------------------------------ 441558324dfcSspeer */ 441658324dfcSspeer static int 441758324dfcSspeer nxge_m_mmac_get(void *arg, mac_multi_addr_t *maddr) 441858324dfcSspeer { 441958324dfcSspeer nxge_t *nxgep = arg; 442058324dfcSspeer mac_addr_slot_t slot; 442158324dfcSspeer nxge_mmac_t *mmac_info; 442258324dfcSspeer nxge_status_t status; 442358324dfcSspeer 442458324dfcSspeer slot = maddr->mma_slot; 442558324dfcSspeer 442658324dfcSspeer mutex_enter(nxgep->genlock); 442758324dfcSspeer 442858324dfcSspeer /* 442958324dfcSspeer * Make sure that nxge is initialized, if _start() has 443058324dfcSspeer * not been called. 443158324dfcSspeer */ 443258324dfcSspeer if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 443358324dfcSspeer status = nxge_init(nxgep); 443458324dfcSspeer if (status != NXGE_OK) { 443558324dfcSspeer mutex_exit(nxgep->genlock); 443658324dfcSspeer return (ENXIO); 443758324dfcSspeer } 443858324dfcSspeer } 443958324dfcSspeer 444058324dfcSspeer mmac_info = &nxgep->nxge_mmac_info; 444158324dfcSspeer 444258324dfcSspeer if (slot < 1 || slot > mmac_info->num_mmac) { 444358324dfcSspeer mutex_exit(nxgep->genlock); 444458324dfcSspeer return (EINVAL); 444558324dfcSspeer } 444658324dfcSspeer maddr->mma_flags = 0; 444758324dfcSspeer if (mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED) 444858324dfcSspeer maddr->mma_flags |= MMAC_SLOT_USED; 444958324dfcSspeer 445058324dfcSspeer if (mmac_info->mac_pool[slot].flags & MMAC_VENDOR_ADDR) { 445158324dfcSspeer maddr->mma_flags |= MMAC_VENDOR_ADDR; 445258324dfcSspeer bcopy(mmac_info->factory_mac_pool[slot], 44534045d941Ssowmini maddr->mma_addr, ETHERADDRL); 445458324dfcSspeer maddr->mma_addrlen = ETHERADDRL; 445558324dfcSspeer } else { 445658324dfcSspeer if (maddr->mma_flags & MMAC_SLOT_USED) { 445758324dfcSspeer bcopy(mmac_info->mac_pool[slot].addr, 44584045d941Ssowmini maddr->mma_addr, ETHERADDRL); 445958324dfcSspeer maddr->mma_addrlen = ETHERADDRL; 446058324dfcSspeer } else { 446158324dfcSspeer bzero(maddr->mma_addr, ETHERADDRL); 446258324dfcSspeer maddr->mma_addrlen = 0; 446358324dfcSspeer } 446458324dfcSspeer } 446558324dfcSspeer mutex_exit(nxgep->genlock); 446658324dfcSspeer return (0); 446758324dfcSspeer } 446858324dfcSspeer 446944961713Sgirish static boolean_t 447044961713Sgirish nxge_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 447144961713Sgirish { 447258324dfcSspeer nxge_t *nxgep = arg; 447358324dfcSspeer uint32_t *txflags = cap_data; 447458324dfcSspeer multiaddress_capab_t *mmacp = cap_data; 447544961713Sgirish 447658324dfcSspeer switch (cap) { 447758324dfcSspeer case MAC_CAPAB_HCKSUM: 4478678453a8Sspeer NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4479b4d05839Sml "==> nxge_m_getcapab: checksum %d", nxge_cksum_offload)); 4480b4d05839Sml if (nxge_cksum_offload <= 1) { 4481678453a8Sspeer *txflags = HCKSUM_INET_PARTIAL; 4482678453a8Sspeer } 448344961713Sgirish break; 4484678453a8Sspeer 448544961713Sgirish case MAC_CAPAB_POLL: 448644961713Sgirish /* 448744961713Sgirish * There's nothing for us to fill in, simply returning 448844961713Sgirish * B_TRUE stating that we support polling is sufficient. 448944961713Sgirish */ 449044961713Sgirish break; 449144961713Sgirish 449258324dfcSspeer case MAC_CAPAB_MULTIADDRESS: 4493678453a8Sspeer mmacp = (multiaddress_capab_t *)cap_data; 449458324dfcSspeer mutex_enter(nxgep->genlock); 449558324dfcSspeer 449658324dfcSspeer mmacp->maddr_naddr = nxgep->nxge_mmac_info.num_mmac; 449758324dfcSspeer mmacp->maddr_naddrfree = nxgep->nxge_mmac_info.naddrfree; 4498b4d05839Sml mmacp->maddr_flag = 0; /* 0 is required by PSARC2006/265 */ 449958324dfcSspeer /* 450058324dfcSspeer * maddr_handle is driver's private data, passed back to 450158324dfcSspeer * entry point functions as arg. 450258324dfcSspeer */ 450358324dfcSspeer mmacp->maddr_handle = nxgep; 450458324dfcSspeer mmacp->maddr_add = nxge_m_mmac_add; 450558324dfcSspeer mmacp->maddr_remove = nxge_m_mmac_remove; 450658324dfcSspeer mmacp->maddr_modify = nxge_m_mmac_modify; 450758324dfcSspeer mmacp->maddr_get = nxge_m_mmac_get; 450858324dfcSspeer mmacp->maddr_reserve = nxge_m_mmac_reserve; 450958324dfcSspeer 451058324dfcSspeer mutex_exit(nxgep->genlock); 451158324dfcSspeer break; 4512678453a8Sspeer 451330ac2e7bSml case MAC_CAPAB_LSO: { 451430ac2e7bSml mac_capab_lso_t *cap_lso = cap_data; 451530ac2e7bSml 45163d16f8e7Sml if (nxgep->soft_lso_enable) { 4517b4d05839Sml if (nxge_cksum_offload <= 1) { 4518b4d05839Sml cap_lso->lso_flags = LSO_TX_BASIC_TCP_IPV4; 4519b4d05839Sml if (nxge_lso_max > NXGE_LSO_MAXLEN) { 4520b4d05839Sml nxge_lso_max = NXGE_LSO_MAXLEN; 4521b4d05839Sml } 4522b4d05839Sml cap_lso->lso_basic_tcp_ipv4.lso_max = 4523b4d05839Sml nxge_lso_max; 452430ac2e7bSml } 452530ac2e7bSml break; 452630ac2e7bSml } else { 452730ac2e7bSml return (B_FALSE); 452830ac2e7bSml } 452930ac2e7bSml } 453030ac2e7bSml 4531678453a8Sspeer #if defined(sun4v) 4532678453a8Sspeer case MAC_CAPAB_RINGS: { 4533678453a8Sspeer mac_capab_rings_t *mrings = (mac_capab_rings_t *)cap_data; 4534678453a8Sspeer 4535678453a8Sspeer /* 4536678453a8Sspeer * Only the service domain driver responds to 4537678453a8Sspeer * this capability request. 4538678453a8Sspeer */ 4539678453a8Sspeer if (isLDOMservice(nxgep)) { 4540678453a8Sspeer mrings->mr_handle = (void *)nxgep; 4541678453a8Sspeer 4542678453a8Sspeer /* 4543678453a8Sspeer * No dynamic allocation of groups and 4544678453a8Sspeer * rings at this time. Shares dictate the 45456f157acbSml * configuration. 4546678453a8Sspeer */ 4547678453a8Sspeer mrings->mr_gadd_ring = NULL; 4548678453a8Sspeer mrings->mr_grem_ring = NULL; 4549678453a8Sspeer mrings->mr_rget = NULL; 4550678453a8Sspeer mrings->mr_gget = nxge_hio_group_get; 4551678453a8Sspeer 4552678453a8Sspeer if (mrings->mr_type == MAC_RING_TYPE_RX) { 4553678453a8Sspeer mrings->mr_rnum = 8; /* XXX */ 4554678453a8Sspeer mrings->mr_gnum = 6; /* XXX */ 4555678453a8Sspeer } else { 4556678453a8Sspeer mrings->mr_rnum = 8; /* XXX */ 4557678453a8Sspeer mrings->mr_gnum = 0; /* XXX */ 4558678453a8Sspeer } 4559678453a8Sspeer } else 4560678453a8Sspeer return (B_FALSE); 4561678453a8Sspeer break; 4562678453a8Sspeer } 4563678453a8Sspeer 4564678453a8Sspeer case MAC_CAPAB_SHARES: { 4565678453a8Sspeer mac_capab_share_t *mshares = (mac_capab_share_t *)cap_data; 4566678453a8Sspeer 4567678453a8Sspeer /* 4568678453a8Sspeer * Only the service domain driver responds to 4569678453a8Sspeer * this capability request. 4570678453a8Sspeer */ 4571678453a8Sspeer if (isLDOMservice(nxgep)) { 4572678453a8Sspeer mshares->ms_snum = 3; 4573678453a8Sspeer mshares->ms_handle = (void *)nxgep; 4574678453a8Sspeer mshares->ms_salloc = nxge_hio_share_alloc; 4575678453a8Sspeer mshares->ms_sfree = nxge_hio_share_free; 4576678453a8Sspeer mshares->ms_sadd = NULL; 4577678453a8Sspeer mshares->ms_sremove = NULL; 4578678453a8Sspeer mshares->ms_squery = nxge_hio_share_query; 4579678453a8Sspeer } else 4580678453a8Sspeer return (B_FALSE); 4581678453a8Sspeer break; 4582678453a8Sspeer } 4583678453a8Sspeer #endif 458444961713Sgirish default: 458544961713Sgirish return (B_FALSE); 458644961713Sgirish } 458744961713Sgirish return (B_TRUE); 458844961713Sgirish } 458944961713Sgirish 45901bd6825cSml static boolean_t 45911bd6825cSml nxge_param_locked(mac_prop_id_t pr_num) 45921bd6825cSml { 45931bd6825cSml /* 45941bd6825cSml * All adv_* parameters are locked (read-only) while 45951bd6825cSml * the device is in any sort of loopback mode ... 45961bd6825cSml */ 45971bd6825cSml switch (pr_num) { 45983fd94f8cSam case MAC_PROP_ADV_1000FDX_CAP: 45993fd94f8cSam case MAC_PROP_EN_1000FDX_CAP: 46003fd94f8cSam case MAC_PROP_ADV_1000HDX_CAP: 46013fd94f8cSam case MAC_PROP_EN_1000HDX_CAP: 46023fd94f8cSam case MAC_PROP_ADV_100FDX_CAP: 46033fd94f8cSam case MAC_PROP_EN_100FDX_CAP: 46043fd94f8cSam case MAC_PROP_ADV_100HDX_CAP: 46053fd94f8cSam case MAC_PROP_EN_100HDX_CAP: 46063fd94f8cSam case MAC_PROP_ADV_10FDX_CAP: 46073fd94f8cSam case MAC_PROP_EN_10FDX_CAP: 46083fd94f8cSam case MAC_PROP_ADV_10HDX_CAP: 46093fd94f8cSam case MAC_PROP_EN_10HDX_CAP: 46103fd94f8cSam case MAC_PROP_AUTONEG: 46113fd94f8cSam case MAC_PROP_FLOWCTRL: 46121bd6825cSml return (B_TRUE); 46131bd6825cSml } 46141bd6825cSml return (B_FALSE); 46151bd6825cSml } 46161bd6825cSml 46171bd6825cSml /* 46181bd6825cSml * callback functions for set/get of properties 46191bd6825cSml */ 46201bd6825cSml static int 46211bd6825cSml nxge_m_setprop(void *barg, const char *pr_name, mac_prop_id_t pr_num, 46221bd6825cSml uint_t pr_valsize, const void *pr_val) 46231bd6825cSml { 46241bd6825cSml nxge_t *nxgep = barg; 46251bd6825cSml p_nxge_param_t param_arr; 46261bd6825cSml p_nxge_stats_t statsp; 46271bd6825cSml int err = 0; 46281bd6825cSml uint8_t val; 46291bd6825cSml uint32_t cur_mtu, new_mtu, old_framesize; 46301bd6825cSml link_flowctrl_t fl; 46311bd6825cSml 46321bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_setprop")); 46331bd6825cSml param_arr = nxgep->param_arr; 46341bd6825cSml statsp = nxgep->statsp; 46351bd6825cSml mutex_enter(nxgep->genlock); 46361bd6825cSml if (statsp->port_stats.lb_mode != nxge_lb_normal && 46371bd6825cSml nxge_param_locked(pr_num)) { 46381bd6825cSml /* 46391bd6825cSml * All adv_* parameters are locked (read-only) 46401bd6825cSml * while the device is in any sort of loopback mode. 46411bd6825cSml */ 46421bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 46431bd6825cSml "==> nxge_m_setprop: loopback mode: read only")); 46441bd6825cSml mutex_exit(nxgep->genlock); 46451bd6825cSml return (EBUSY); 46461bd6825cSml } 46471bd6825cSml 46481bd6825cSml val = *(uint8_t *)pr_val; 46491bd6825cSml switch (pr_num) { 46503fd94f8cSam case MAC_PROP_EN_1000FDX_CAP: 46511bd6825cSml nxgep->param_en_1000fdx = val; 46521bd6825cSml param_arr[param_anar_1000fdx].value = val; 46531bd6825cSml 46541bd6825cSml goto reprogram; 46551bd6825cSml 46563fd94f8cSam case MAC_PROP_EN_100FDX_CAP: 46571bd6825cSml nxgep->param_en_100fdx = val; 46581bd6825cSml param_arr[param_anar_100fdx].value = val; 46591bd6825cSml 46601bd6825cSml goto reprogram; 46611bd6825cSml 46623fd94f8cSam case MAC_PROP_EN_10FDX_CAP: 46631bd6825cSml nxgep->param_en_10fdx = val; 46641bd6825cSml param_arr[param_anar_10fdx].value = val; 46651bd6825cSml 46661bd6825cSml goto reprogram; 46671bd6825cSml 46683fd94f8cSam case MAC_PROP_EN_1000HDX_CAP: 46693fd94f8cSam case MAC_PROP_EN_100HDX_CAP: 46703fd94f8cSam case MAC_PROP_EN_10HDX_CAP: 46713fd94f8cSam case MAC_PROP_ADV_1000FDX_CAP: 46723fd94f8cSam case MAC_PROP_ADV_1000HDX_CAP: 46733fd94f8cSam case MAC_PROP_ADV_100FDX_CAP: 46743fd94f8cSam case MAC_PROP_ADV_100HDX_CAP: 46753fd94f8cSam case MAC_PROP_ADV_10FDX_CAP: 46763fd94f8cSam case MAC_PROP_ADV_10HDX_CAP: 46773fd94f8cSam case MAC_PROP_STATUS: 46783fd94f8cSam case MAC_PROP_SPEED: 46793fd94f8cSam case MAC_PROP_DUPLEX: 46801bd6825cSml err = EINVAL; /* cannot set read-only properties */ 46811bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 46821bd6825cSml "==> nxge_m_setprop: read only property %d", 46831bd6825cSml pr_num)); 46841bd6825cSml break; 46851bd6825cSml 46863fd94f8cSam case MAC_PROP_AUTONEG: 46871bd6825cSml param_arr[param_autoneg].value = val; 46881bd6825cSml 46891bd6825cSml goto reprogram; 46901bd6825cSml 46913fd94f8cSam case MAC_PROP_MTU: 46921bd6825cSml if (nxgep->nxge_mac_state == NXGE_MAC_STARTED) { 46931bd6825cSml err = EBUSY; 46941bd6825cSml break; 46951bd6825cSml } 46961bd6825cSml 46971bd6825cSml cur_mtu = nxgep->mac.default_mtu; 46981bd6825cSml bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 46991bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 47001bd6825cSml "==> nxge_m_setprop: set MTU: %d is_jumbo %d", 47011bd6825cSml new_mtu, nxgep->mac.is_jumbo)); 47021bd6825cSml 47031bd6825cSml if (new_mtu == cur_mtu) { 47041bd6825cSml err = 0; 47051bd6825cSml break; 47061bd6825cSml } 47071bd6825cSml if (new_mtu < NXGE_DEFAULT_MTU || 47081bd6825cSml new_mtu > NXGE_MAXIMUM_MTU) { 47091bd6825cSml err = EINVAL; 47101bd6825cSml break; 47111bd6825cSml } 47121bd6825cSml 47131bd6825cSml if ((new_mtu > NXGE_DEFAULT_MTU) && 47141bd6825cSml !nxgep->mac.is_jumbo) { 47151bd6825cSml err = EINVAL; 47161bd6825cSml break; 47171bd6825cSml } 47181bd6825cSml 47191bd6825cSml old_framesize = (uint32_t)nxgep->mac.maxframesize; 47201bd6825cSml nxgep->mac.maxframesize = (uint16_t) 47211bd6825cSml (new_mtu + NXGE_EHEADER_VLAN_CRC); 47221bd6825cSml if (nxge_mac_set_framesize(nxgep)) { 4723c2d37b8bSml nxgep->mac.maxframesize = 4724c2d37b8bSml (uint16_t)old_framesize; 47251bd6825cSml err = EINVAL; 47261bd6825cSml break; 47271bd6825cSml } 47281bd6825cSml 47291bd6825cSml err = mac_maxsdu_update(nxgep->mach, new_mtu); 47301bd6825cSml if (err) { 4731c2d37b8bSml nxgep->mac.maxframesize = 4732c2d37b8bSml (uint16_t)old_framesize; 47331bd6825cSml err = EINVAL; 47341bd6825cSml break; 47351bd6825cSml } 47361bd6825cSml 47371bd6825cSml nxgep->mac.default_mtu = new_mtu; 47381bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 47391bd6825cSml "==> nxge_m_setprop: set MTU: %d maxframe %d", 47401bd6825cSml new_mtu, nxgep->mac.maxframesize)); 47411bd6825cSml break; 47421bd6825cSml 47433fd94f8cSam case MAC_PROP_FLOWCTRL: 47441bd6825cSml bcopy(pr_val, &fl, sizeof (fl)); 47451bd6825cSml switch (fl) { 47461bd6825cSml default: 47471bd6825cSml err = EINVAL; 47481bd6825cSml break; 47491bd6825cSml 47501bd6825cSml case LINK_FLOWCTRL_NONE: 47511bd6825cSml param_arr[param_anar_pause].value = 0; 47521bd6825cSml break; 47531bd6825cSml 47541bd6825cSml case LINK_FLOWCTRL_RX: 47551bd6825cSml param_arr[param_anar_pause].value = 1; 47561bd6825cSml break; 47571bd6825cSml 47581bd6825cSml case LINK_FLOWCTRL_TX: 47591bd6825cSml case LINK_FLOWCTRL_BI: 47601bd6825cSml err = EINVAL; 47611bd6825cSml break; 47621bd6825cSml } 47631bd6825cSml 47641bd6825cSml reprogram: 47651bd6825cSml if (err == 0) { 47661bd6825cSml if (!nxge_param_link_update(nxgep)) { 47671bd6825cSml err = EINVAL; 47681bd6825cSml } 47691bd6825cSml } 47701bd6825cSml break; 47713fd94f8cSam case MAC_PROP_PRIVATE: 47721bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 47731bd6825cSml "==> nxge_m_setprop: private property")); 47741bd6825cSml err = nxge_set_priv_prop(nxgep, pr_name, pr_valsize, 47751bd6825cSml pr_val); 47761bd6825cSml break; 47774045d941Ssowmini 47784045d941Ssowmini default: 47794045d941Ssowmini err = ENOTSUP; 47804045d941Ssowmini break; 47811bd6825cSml } 47821bd6825cSml 47831bd6825cSml mutex_exit(nxgep->genlock); 47841bd6825cSml 47851bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 47861bd6825cSml "<== nxge_m_setprop (return %d)", err)); 47871bd6825cSml return (err); 47881bd6825cSml } 47891bd6825cSml 47901bd6825cSml static int 47911bd6825cSml nxge_m_getprop(void *barg, const char *pr_name, mac_prop_id_t pr_num, 47924045d941Ssowmini uint_t pr_flags, uint_t pr_valsize, void *pr_val) 47931bd6825cSml { 47941bd6825cSml nxge_t *nxgep = barg; 47951bd6825cSml p_nxge_param_t param_arr = nxgep->param_arr; 47961bd6825cSml p_nxge_stats_t statsp = nxgep->statsp; 47971bd6825cSml int err = 0; 47981bd6825cSml link_flowctrl_t fl; 47991bd6825cSml uint64_t tmp = 0; 48004045d941Ssowmini link_state_t ls; 48013fd94f8cSam boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 48021bd6825cSml 48031bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 48041bd6825cSml "==> nxge_m_getprop: pr_num %d", pr_num)); 48054045d941Ssowmini 48064045d941Ssowmini if (pr_valsize == 0) 48074045d941Ssowmini return (EINVAL); 48084045d941Ssowmini 48093fd94f8cSam if ((is_default) && (pr_num != MAC_PROP_PRIVATE)) { 48104045d941Ssowmini err = nxge_get_def_val(nxgep, pr_num, pr_valsize, pr_val); 48114045d941Ssowmini return (err); 48124045d941Ssowmini } 48134045d941Ssowmini 48141bd6825cSml bzero(pr_val, pr_valsize); 48151bd6825cSml switch (pr_num) { 48163fd94f8cSam case MAC_PROP_DUPLEX: 48171bd6825cSml *(uint8_t *)pr_val = statsp->mac_stats.link_duplex; 48181bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 48191bd6825cSml "==> nxge_m_getprop: duplex mode %d", 48201bd6825cSml *(uint8_t *)pr_val)); 48211bd6825cSml break; 48221bd6825cSml 48233fd94f8cSam case MAC_PROP_SPEED: 48241bd6825cSml if (pr_valsize < sizeof (uint64_t)) 48251bd6825cSml return (EINVAL); 48261bd6825cSml tmp = statsp->mac_stats.link_speed * 1000000ull; 48271bd6825cSml bcopy(&tmp, pr_val, sizeof (tmp)); 48281bd6825cSml break; 48291bd6825cSml 48303fd94f8cSam case MAC_PROP_STATUS: 48314045d941Ssowmini if (pr_valsize < sizeof (link_state_t)) 48321bd6825cSml return (EINVAL); 48334045d941Ssowmini if (!statsp->mac_stats.link_up) 48344045d941Ssowmini ls = LINK_STATE_DOWN; 48354045d941Ssowmini else 48364045d941Ssowmini ls = LINK_STATE_UP; 48374045d941Ssowmini bcopy(&ls, pr_val, sizeof (ls)); 48381bd6825cSml break; 48391bd6825cSml 48403fd94f8cSam case MAC_PROP_AUTONEG: 48411bd6825cSml *(uint8_t *)pr_val = 48421bd6825cSml param_arr[param_autoneg].value; 48431bd6825cSml break; 48441bd6825cSml 48453fd94f8cSam case MAC_PROP_FLOWCTRL: 48461bd6825cSml if (pr_valsize < sizeof (link_flowctrl_t)) 48471bd6825cSml return (EINVAL); 48481bd6825cSml 48491bd6825cSml fl = LINK_FLOWCTRL_NONE; 48501bd6825cSml if (param_arr[param_anar_pause].value) { 48511bd6825cSml fl = LINK_FLOWCTRL_RX; 48521bd6825cSml } 48531bd6825cSml bcopy(&fl, pr_val, sizeof (fl)); 48541bd6825cSml break; 48551bd6825cSml 48563fd94f8cSam case MAC_PROP_ADV_1000FDX_CAP: 48571bd6825cSml *(uint8_t *)pr_val = 48581bd6825cSml param_arr[param_anar_1000fdx].value; 48591bd6825cSml break; 48601bd6825cSml 48613fd94f8cSam case MAC_PROP_EN_1000FDX_CAP: 48621bd6825cSml *(uint8_t *)pr_val = nxgep->param_en_1000fdx; 48631bd6825cSml break; 48641bd6825cSml 48653fd94f8cSam case MAC_PROP_ADV_100FDX_CAP: 48661bd6825cSml *(uint8_t *)pr_val = 48671bd6825cSml param_arr[param_anar_100fdx].value; 48681bd6825cSml break; 48691bd6825cSml 48703fd94f8cSam case MAC_PROP_EN_100FDX_CAP: 48711bd6825cSml *(uint8_t *)pr_val = nxgep->param_en_100fdx; 48721bd6825cSml break; 48731bd6825cSml 48743fd94f8cSam case MAC_PROP_ADV_10FDX_CAP: 48751bd6825cSml *(uint8_t *)pr_val = 48761bd6825cSml param_arr[param_anar_10fdx].value; 48771bd6825cSml break; 48781bd6825cSml 48793fd94f8cSam case MAC_PROP_EN_10FDX_CAP: 48801bd6825cSml *(uint8_t *)pr_val = nxgep->param_en_10fdx; 48811bd6825cSml break; 48821bd6825cSml 48833fd94f8cSam case MAC_PROP_EN_1000HDX_CAP: 48843fd94f8cSam case MAC_PROP_EN_100HDX_CAP: 48853fd94f8cSam case MAC_PROP_EN_10HDX_CAP: 48863fd94f8cSam case MAC_PROP_ADV_1000HDX_CAP: 48873fd94f8cSam case MAC_PROP_ADV_100HDX_CAP: 48883fd94f8cSam case MAC_PROP_ADV_10HDX_CAP: 48894045d941Ssowmini err = ENOTSUP; 48901bd6825cSml break; 48911bd6825cSml 48923fd94f8cSam case MAC_PROP_PRIVATE: 48934045d941Ssowmini err = nxge_get_priv_prop(nxgep, pr_name, pr_flags, 48944045d941Ssowmini pr_valsize, pr_val); 48954045d941Ssowmini break; 48961bd6825cSml default: 48974045d941Ssowmini err = EINVAL; 48984045d941Ssowmini break; 48991bd6825cSml } 49001bd6825cSml 49011bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_getprop")); 49021bd6825cSml 49031bd6825cSml return (err); 49041bd6825cSml } 49051bd6825cSml 49061bd6825cSml /* ARGSUSED */ 49071bd6825cSml static int 49081bd6825cSml nxge_set_priv_prop(p_nxge_t nxgep, const char *pr_name, uint_t pr_valsize, 49091bd6825cSml const void *pr_val) 49101bd6825cSml { 49111bd6825cSml p_nxge_param_t param_arr = nxgep->param_arr; 49121bd6825cSml int err = 0; 49131bd6825cSml long result; 49141bd6825cSml 49151bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 49161bd6825cSml "==> nxge_set_priv_prop: name %s", pr_name)); 49171bd6825cSml 49181bd6825cSml if (strcmp(pr_name, "_accept_jumbo") == 0) { 49191bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 49201bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 49211bd6825cSml "<== nxge_set_priv_prop: name %s " 49221bd6825cSml "pr_val %s result %d " 49231bd6825cSml "param %d is_jumbo %d", 49241bd6825cSml pr_name, pr_val, result, 49251bd6825cSml param_arr[param_accept_jumbo].value, 49261bd6825cSml nxgep->mac.is_jumbo)); 49271bd6825cSml 49281bd6825cSml if (result > 1 || result < 0) { 49291bd6825cSml err = EINVAL; 49301bd6825cSml } else { 49311bd6825cSml if (nxgep->mac.is_jumbo == 49321bd6825cSml (uint32_t)result) { 49331bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 49341bd6825cSml "no change (%d %d)", 49351bd6825cSml nxgep->mac.is_jumbo, 49361bd6825cSml result)); 49371bd6825cSml return (0); 49381bd6825cSml } 49391bd6825cSml } 49401bd6825cSml 49411bd6825cSml param_arr[param_accept_jumbo].value = result; 49421bd6825cSml nxgep->mac.is_jumbo = B_FALSE; 49431bd6825cSml if (result) { 49441bd6825cSml nxgep->mac.is_jumbo = B_TRUE; 49451bd6825cSml } 49461bd6825cSml 49471bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 49481bd6825cSml "<== nxge_set_priv_prop: name %s (value %d) is_jumbo %d", 49491bd6825cSml pr_name, result, nxgep->mac.is_jumbo)); 49501bd6825cSml 49511bd6825cSml return (err); 49521bd6825cSml } 49531bd6825cSml 49541bd6825cSml /* Blanking */ 49551bd6825cSml if (strcmp(pr_name, "_rxdma_intr_time") == 0) { 49561bd6825cSml err = nxge_param_rx_intr_time(nxgep, NULL, NULL, 49571bd6825cSml (char *)pr_val, 49581bd6825cSml (caddr_t)¶m_arr[param_rxdma_intr_time]); 49591bd6825cSml if (err) { 49601bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 49611bd6825cSml "<== nxge_set_priv_prop: " 49621bd6825cSml "unable to set (%s)", pr_name)); 49631bd6825cSml err = EINVAL; 49641bd6825cSml } else { 49651bd6825cSml err = 0; 49661bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 49671bd6825cSml "<== nxge_set_priv_prop: " 49681bd6825cSml "set (%s)", pr_name)); 49691bd6825cSml } 49701bd6825cSml 49711bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 49721bd6825cSml "<== nxge_set_priv_prop: name %s (value %d)", 49731bd6825cSml pr_name, result)); 49741bd6825cSml 49751bd6825cSml return (err); 49761bd6825cSml } 49771bd6825cSml 49781bd6825cSml if (strcmp(pr_name, "_rxdma_intr_pkts") == 0) { 49791bd6825cSml err = nxge_param_rx_intr_pkts(nxgep, NULL, NULL, 49801bd6825cSml (char *)pr_val, 49811bd6825cSml (caddr_t)¶m_arr[param_rxdma_intr_pkts]); 49821bd6825cSml if (err) { 49831bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 49841bd6825cSml "<== nxge_set_priv_prop: " 49851bd6825cSml "unable to set (%s)", pr_name)); 49861bd6825cSml err = EINVAL; 49871bd6825cSml } else { 49881bd6825cSml err = 0; 49891bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 49901bd6825cSml "<== nxge_set_priv_prop: " 49911bd6825cSml "set (%s)", pr_name)); 49921bd6825cSml } 49931bd6825cSml 49941bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 49951bd6825cSml "<== nxge_set_priv_prop: name %s (value %d)", 49961bd6825cSml pr_name, result)); 49971bd6825cSml 49981bd6825cSml return (err); 49991bd6825cSml } 50001bd6825cSml 50011bd6825cSml /* Classification */ 50021bd6825cSml if (strcmp(pr_name, "_class_opt_ipv4_tcp") == 0) { 50031bd6825cSml if (pr_val == NULL) { 50041bd6825cSml err = EINVAL; 50051bd6825cSml return (err); 50061bd6825cSml } 50071bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 50081bd6825cSml 50091bd6825cSml err = nxge_param_set_ip_opt(nxgep, NULL, 50101bd6825cSml NULL, (char *)pr_val, 50111bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv4_tcp]); 50121bd6825cSml 50131bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 50141bd6825cSml "<== nxge_set_priv_prop: name %s (value 0x%x)", 50151bd6825cSml pr_name, result)); 50161bd6825cSml 50171bd6825cSml return (err); 50181bd6825cSml } 50191bd6825cSml 50201bd6825cSml if (strcmp(pr_name, "_class_opt_ipv4_udp") == 0) { 50211bd6825cSml if (pr_val == NULL) { 50221bd6825cSml err = EINVAL; 50231bd6825cSml return (err); 50241bd6825cSml } 50251bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 50261bd6825cSml 50271bd6825cSml err = nxge_param_set_ip_opt(nxgep, NULL, 50281bd6825cSml NULL, (char *)pr_val, 50291bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv4_udp]); 50301bd6825cSml 50311bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 50321bd6825cSml "<== nxge_set_priv_prop: name %s (value 0x%x)", 50331bd6825cSml pr_name, result)); 50341bd6825cSml 50351bd6825cSml return (err); 50361bd6825cSml } 50371bd6825cSml if (strcmp(pr_name, "_class_opt_ipv4_ah") == 0) { 50381bd6825cSml if (pr_val == NULL) { 50391bd6825cSml err = EINVAL; 50401bd6825cSml return (err); 50411bd6825cSml } 50421bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 50431bd6825cSml 50441bd6825cSml err = nxge_param_set_ip_opt(nxgep, NULL, 50451bd6825cSml NULL, (char *)pr_val, 50461bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv4_ah]); 50471bd6825cSml 50481bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 50491bd6825cSml "<== nxge_set_priv_prop: name %s (value 0x%x)", 50501bd6825cSml pr_name, result)); 50511bd6825cSml 50521bd6825cSml return (err); 50531bd6825cSml } 50541bd6825cSml if (strcmp(pr_name, "_class_opt_ipv4_sctp") == 0) { 50551bd6825cSml if (pr_val == NULL) { 50561bd6825cSml err = EINVAL; 50571bd6825cSml return (err); 50581bd6825cSml } 50591bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 50601bd6825cSml 50611bd6825cSml err = nxge_param_set_ip_opt(nxgep, NULL, 50621bd6825cSml NULL, (char *)pr_val, 50631bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv4_sctp]); 50641bd6825cSml 50651bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 50661bd6825cSml "<== nxge_set_priv_prop: name %s (value 0x%x)", 50671bd6825cSml pr_name, result)); 50681bd6825cSml 50691bd6825cSml return (err); 50701bd6825cSml } 50711bd6825cSml 50721bd6825cSml if (strcmp(pr_name, "_class_opt_ipv6_tcp") == 0) { 50731bd6825cSml if (pr_val == NULL) { 50741bd6825cSml err = EINVAL; 50751bd6825cSml return (err); 50761bd6825cSml } 50771bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 50781bd6825cSml 50791bd6825cSml err = nxge_param_set_ip_opt(nxgep, NULL, 50801bd6825cSml NULL, (char *)pr_val, 50811bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv6_tcp]); 50821bd6825cSml 50831bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 50841bd6825cSml "<== nxge_set_priv_prop: name %s (value 0x%x)", 50851bd6825cSml pr_name, result)); 50861bd6825cSml 50871bd6825cSml return (err); 50881bd6825cSml } 50891bd6825cSml 50901bd6825cSml if (strcmp(pr_name, "_class_opt_ipv6_udp") == 0) { 50911bd6825cSml if (pr_val == NULL) { 50921bd6825cSml err = EINVAL; 50931bd6825cSml return (err); 50941bd6825cSml } 50951bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 50961bd6825cSml 50971bd6825cSml err = nxge_param_set_ip_opt(nxgep, NULL, 50981bd6825cSml NULL, (char *)pr_val, 50991bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv6_udp]); 51001bd6825cSml 51011bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 51021bd6825cSml "<== nxge_set_priv_prop: name %s (value 0x%x)", 51031bd6825cSml pr_name, result)); 51041bd6825cSml 51051bd6825cSml return (err); 51061bd6825cSml } 51071bd6825cSml if (strcmp(pr_name, "_class_opt_ipv6_ah") == 0) { 51081bd6825cSml if (pr_val == NULL) { 51091bd6825cSml err = EINVAL; 51101bd6825cSml return (err); 51111bd6825cSml } 51121bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 51131bd6825cSml 51141bd6825cSml err = nxge_param_set_ip_opt(nxgep, NULL, 51151bd6825cSml NULL, (char *)pr_val, 51161bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv6_ah]); 51171bd6825cSml 51181bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 51191bd6825cSml "<== nxge_set_priv_prop: name %s (value 0x%x)", 51201bd6825cSml pr_name, result)); 51211bd6825cSml 51221bd6825cSml return (err); 51231bd6825cSml } 51241bd6825cSml if (strcmp(pr_name, "_class_opt_ipv6_sctp") == 0) { 51251bd6825cSml if (pr_val == NULL) { 51261bd6825cSml err = EINVAL; 51271bd6825cSml return (err); 51281bd6825cSml } 51291bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 51301bd6825cSml 51311bd6825cSml err = nxge_param_set_ip_opt(nxgep, NULL, 51321bd6825cSml NULL, (char *)pr_val, 51331bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv6_sctp]); 51341bd6825cSml 51351bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 51361bd6825cSml "<== nxge_set_priv_prop: name %s (value 0x%x)", 51371bd6825cSml pr_name, result)); 51381bd6825cSml 51391bd6825cSml return (err); 51401bd6825cSml } 51411bd6825cSml 51421bd6825cSml if (strcmp(pr_name, "_soft_lso_enable") == 0) { 51431bd6825cSml if (nxgep->nxge_mac_state == NXGE_MAC_STARTED) { 51441bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 51451bd6825cSml "==> nxge_set_priv_prop: name %s (busy)", pr_name)); 51461bd6825cSml err = EBUSY; 51471bd6825cSml return (err); 51481bd6825cSml } 51491bd6825cSml if (pr_val == NULL) { 51501bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 51511bd6825cSml "==> nxge_set_priv_prop: name %s (null)", pr_name)); 51521bd6825cSml err = EINVAL; 51531bd6825cSml return (err); 51541bd6825cSml } 51551bd6825cSml 51561bd6825cSml (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 51571bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 51581bd6825cSml "<== nxge_set_priv_prop: name %s " 51591bd6825cSml "(lso %d pr_val %s value %d)", 51601bd6825cSml pr_name, nxgep->soft_lso_enable, pr_val, result)); 51611bd6825cSml 51621bd6825cSml if (result > 1 || result < 0) { 51631bd6825cSml err = EINVAL; 51641bd6825cSml } else { 51651bd6825cSml if (nxgep->soft_lso_enable == (uint32_t)result) { 51661bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 51671bd6825cSml "no change (%d %d)", 51681bd6825cSml nxgep->soft_lso_enable, result)); 51691bd6825cSml return (0); 51701bd6825cSml } 51711bd6825cSml } 51721bd6825cSml 51731bd6825cSml nxgep->soft_lso_enable = (int)result; 51741bd6825cSml 51751bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 51761bd6825cSml "<== nxge_set_priv_prop: name %s (value %d)", 51771bd6825cSml pr_name, result)); 51781bd6825cSml 51791bd6825cSml return (err); 51801bd6825cSml } 518100161856Syc /* 518200161856Syc * Commands like "ndd -set /dev/nxge0 adv_10gfdx_cap 1" cause the 518300161856Syc * following code to be executed. 518400161856Syc */ 51854045d941Ssowmini if (strcmp(pr_name, "_adv_10gfdx_cap") == 0) { 51864045d941Ssowmini err = nxge_param_set_mac(nxgep, NULL, NULL, (char *)pr_val, 51874045d941Ssowmini (caddr_t)¶m_arr[param_anar_10gfdx]); 51884045d941Ssowmini return (err); 51894045d941Ssowmini } 51904045d941Ssowmini if (strcmp(pr_name, "_adv_pause_cap") == 0) { 51914045d941Ssowmini err = nxge_param_set_mac(nxgep, NULL, NULL, (char *)pr_val, 51924045d941Ssowmini (caddr_t)¶m_arr[param_anar_pause]); 51934045d941Ssowmini return (err); 51944045d941Ssowmini } 51951bd6825cSml 51961bd6825cSml return (EINVAL); 51971bd6825cSml } 51981bd6825cSml 51991bd6825cSml static int 52004045d941Ssowmini nxge_get_priv_prop(p_nxge_t nxgep, const char *pr_name, uint_t pr_flags, 52014045d941Ssowmini uint_t pr_valsize, void *pr_val) 52021bd6825cSml { 52031bd6825cSml p_nxge_param_t param_arr = nxgep->param_arr; 52041bd6825cSml char valstr[MAXNAMELEN]; 52051bd6825cSml int err = EINVAL; 52061bd6825cSml uint_t strsize; 52073fd94f8cSam boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 52081bd6825cSml 52091bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 52101bd6825cSml "==> nxge_get_priv_prop: property %s", pr_name)); 52111bd6825cSml 52121bd6825cSml /* function number */ 52131bd6825cSml if (strcmp(pr_name, "_function_number") == 0) { 52144045d941Ssowmini if (is_default) 52154045d941Ssowmini return (ENOTSUP); 52164045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%d", 52174045d941Ssowmini nxgep->function_num); 52181bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 52191bd6825cSml "==> nxge_get_priv_prop: name %s " 52201bd6825cSml "(value %d valstr %s)", 52211bd6825cSml pr_name, nxgep->function_num, valstr)); 52221bd6825cSml 52231bd6825cSml err = 0; 52241bd6825cSml goto done; 52251bd6825cSml } 52261bd6825cSml 52271bd6825cSml /* Neptune firmware version */ 52281bd6825cSml if (strcmp(pr_name, "_fw_version") == 0) { 52294045d941Ssowmini if (is_default) 52304045d941Ssowmini return (ENOTSUP); 52314045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%s", 52324045d941Ssowmini nxgep->vpd_info.ver); 52331bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 52341bd6825cSml "==> nxge_get_priv_prop: name %s " 52351bd6825cSml "(value %d valstr %s)", 52361bd6825cSml pr_name, nxgep->vpd_info.ver, valstr)); 52371bd6825cSml 52381bd6825cSml err = 0; 52391bd6825cSml goto done; 52401bd6825cSml } 52411bd6825cSml 52421bd6825cSml /* port PHY mode */ 52431bd6825cSml if (strcmp(pr_name, "_port_mode") == 0) { 52444045d941Ssowmini if (is_default) 52454045d941Ssowmini return (ENOTSUP); 52461bd6825cSml switch (nxgep->mac.portmode) { 52471bd6825cSml case PORT_1G_COPPER: 52484045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "1G copper %s", 52491bd6825cSml nxgep->hot_swappable_phy ? 52501bd6825cSml "[Hot Swappable]" : ""); 52511bd6825cSml break; 52521bd6825cSml case PORT_1G_FIBER: 52534045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "1G fiber %s", 52541bd6825cSml nxgep->hot_swappable_phy ? 52551bd6825cSml "[hot swappable]" : ""); 52561bd6825cSml break; 52571bd6825cSml case PORT_10G_COPPER: 52584045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), 52594045d941Ssowmini "10G copper %s", 52601bd6825cSml nxgep->hot_swappable_phy ? 52611bd6825cSml "[hot swappable]" : ""); 52621bd6825cSml break; 52631bd6825cSml case PORT_10G_FIBER: 52644045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "10G fiber %s", 52651bd6825cSml nxgep->hot_swappable_phy ? 52661bd6825cSml "[hot swappable]" : ""); 52671bd6825cSml break; 52681bd6825cSml case PORT_10G_SERDES: 52694045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), 52704045d941Ssowmini "10G serdes %s", nxgep->hot_swappable_phy ? 52711bd6825cSml "[hot swappable]" : ""); 52721bd6825cSml break; 52731bd6825cSml case PORT_1G_SERDES: 52744045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "1G serdes %s", 52751bd6825cSml nxgep->hot_swappable_phy ? 52761bd6825cSml "[hot swappable]" : ""); 52771bd6825cSml break; 527800161856Syc case PORT_1G_TN1010: 527900161856Syc (void) snprintf(valstr, sizeof (valstr), 528000161856Syc "1G TN1010 copper %s", nxgep->hot_swappable_phy ? 528100161856Syc "[hot swappable]" : ""); 528200161856Syc break; 528300161856Syc case PORT_10G_TN1010: 528400161856Syc (void) snprintf(valstr, sizeof (valstr), 528500161856Syc "10G TN1010 copper %s", nxgep->hot_swappable_phy ? 528600161856Syc "[hot swappable]" : ""); 528700161856Syc break; 52881bd6825cSml case PORT_1G_RGMII_FIBER: 52894045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), 52904045d941Ssowmini "1G rgmii fiber %s", nxgep->hot_swappable_phy ? 52911bd6825cSml "[hot swappable]" : ""); 52921bd6825cSml break; 52931bd6825cSml case PORT_HSP_MODE: 52944045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), 5295c2d37b8bSml "phy not present[hot swappable]"); 52961bd6825cSml break; 52971bd6825cSml default: 52984045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "unknown %s", 52991bd6825cSml nxgep->hot_swappable_phy ? 53001bd6825cSml "[hot swappable]" : ""); 53011bd6825cSml break; 53021bd6825cSml } 53031bd6825cSml 53041bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 53051bd6825cSml "==> nxge_get_priv_prop: name %s (value %s)", 53061bd6825cSml pr_name, valstr)); 53071bd6825cSml 53081bd6825cSml err = 0; 53091bd6825cSml goto done; 53101bd6825cSml } 53111bd6825cSml 53121bd6825cSml /* Hot swappable PHY */ 53131bd6825cSml if (strcmp(pr_name, "_hot_swap_phy") == 0) { 53144045d941Ssowmini if (is_default) 53154045d941Ssowmini return (ENOTSUP); 53164045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%s", 53171bd6825cSml nxgep->hot_swappable_phy ? 53181bd6825cSml "yes" : "no"); 53191bd6825cSml 53201bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 53211bd6825cSml "==> nxge_get_priv_prop: name %s " 53221bd6825cSml "(value %d valstr %s)", 53231bd6825cSml pr_name, nxgep->hot_swappable_phy, valstr)); 53241bd6825cSml 53251bd6825cSml err = 0; 53261bd6825cSml goto done; 53271bd6825cSml } 53281bd6825cSml 53291bd6825cSml 53301bd6825cSml /* accept jumbo */ 53311bd6825cSml if (strcmp(pr_name, "_accept_jumbo") == 0) { 53324045d941Ssowmini if (is_default) 53334045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%d", 0); 53344045d941Ssowmini else 53354045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), 53364045d941Ssowmini "%d", nxgep->mac.is_jumbo); 53371bd6825cSml err = 0; 53381bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 53391bd6825cSml "==> nxge_get_priv_prop: name %s (value %d (%d, %d))", 53401bd6825cSml pr_name, 53411bd6825cSml (uint32_t)param_arr[param_accept_jumbo].value, 53421bd6825cSml nxgep->mac.is_jumbo, 53431bd6825cSml nxge_jumbo_enable)); 53441bd6825cSml 53451bd6825cSml goto done; 53461bd6825cSml } 53471bd6825cSml 53481bd6825cSml /* Receive Interrupt Blanking Parameters */ 53491bd6825cSml if (strcmp(pr_name, "_rxdma_intr_time") == 0) { 53504045d941Ssowmini err = 0; 53514045d941Ssowmini if (is_default) { 53524045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), 53534045d941Ssowmini "%d", RXDMA_RCR_TO_DEFAULT); 53544045d941Ssowmini goto done; 53554045d941Ssowmini } 53564045d941Ssowmini 53574045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%d", 53584045d941Ssowmini nxgep->intr_timeout); 53591bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 53601bd6825cSml "==> nxge_get_priv_prop: name %s (value %d)", 53611bd6825cSml pr_name, 53621bd6825cSml (uint32_t)nxgep->intr_timeout)); 53631bd6825cSml goto done; 53641bd6825cSml } 53651bd6825cSml 53661bd6825cSml if (strcmp(pr_name, "_rxdma_intr_pkts") == 0) { 53674045d941Ssowmini err = 0; 53684045d941Ssowmini if (is_default) { 53694045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), 53704045d941Ssowmini "%d", RXDMA_RCR_PTHRES_DEFAULT); 53714045d941Ssowmini goto done; 53724045d941Ssowmini } 53734045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%d", 53744045d941Ssowmini nxgep->intr_threshold); 53751bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 53761bd6825cSml "==> nxge_get_priv_prop: name %s (value %d)", 53771bd6825cSml pr_name, (uint32_t)nxgep->intr_threshold)); 53781bd6825cSml 53791bd6825cSml goto done; 53801bd6825cSml } 53811bd6825cSml 53821bd6825cSml /* Classification and Load Distribution Configuration */ 53831bd6825cSml if (strcmp(pr_name, "_class_opt_ipv4_tcp") == 0) { 53844045d941Ssowmini if (is_default) { 53854045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 53864045d941Ssowmini NXGE_CLASS_FLOW_GEN_SERVER); 53874045d941Ssowmini err = 0; 53884045d941Ssowmini goto done; 53894045d941Ssowmini } 53901bd6825cSml err = nxge_dld_get_ip_opt(nxgep, 53911bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv4_tcp]); 53921bd6825cSml 53934045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 53941bd6825cSml (int)param_arr[param_class_opt_ipv4_tcp].value); 53951bd6825cSml 53961bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 53971bd6825cSml "==> nxge_get_priv_prop: %s", valstr)); 53981bd6825cSml goto done; 53991bd6825cSml } 54001bd6825cSml 54011bd6825cSml if (strcmp(pr_name, "_class_opt_ipv4_udp") == 0) { 54024045d941Ssowmini if (is_default) { 54034045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 54044045d941Ssowmini NXGE_CLASS_FLOW_GEN_SERVER); 54054045d941Ssowmini err = 0; 54064045d941Ssowmini goto done; 54074045d941Ssowmini } 54081bd6825cSml err = nxge_dld_get_ip_opt(nxgep, 54091bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv4_udp]); 54101bd6825cSml 54114045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 54121bd6825cSml (int)param_arr[param_class_opt_ipv4_udp].value); 54131bd6825cSml 54141bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 54151bd6825cSml "==> nxge_get_priv_prop: %s", valstr)); 54161bd6825cSml goto done; 54171bd6825cSml } 54181bd6825cSml if (strcmp(pr_name, "_class_opt_ipv4_ah") == 0) { 54194045d941Ssowmini if (is_default) { 54204045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 54214045d941Ssowmini NXGE_CLASS_FLOW_GEN_SERVER); 54224045d941Ssowmini err = 0; 54234045d941Ssowmini goto done; 54244045d941Ssowmini } 54251bd6825cSml err = nxge_dld_get_ip_opt(nxgep, 54261bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv4_ah]); 54271bd6825cSml 54284045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 54291bd6825cSml (int)param_arr[param_class_opt_ipv4_ah].value); 54301bd6825cSml 54311bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 54321bd6825cSml "==> nxge_get_priv_prop: %s", valstr)); 54331bd6825cSml goto done; 54341bd6825cSml } 54351bd6825cSml 54361bd6825cSml if (strcmp(pr_name, "_class_opt_ipv4_sctp") == 0) { 54374045d941Ssowmini if (is_default) { 54384045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 54394045d941Ssowmini NXGE_CLASS_FLOW_GEN_SERVER); 54404045d941Ssowmini err = 0; 54414045d941Ssowmini goto done; 54424045d941Ssowmini } 54431bd6825cSml err = nxge_dld_get_ip_opt(nxgep, 54441bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv4_sctp]); 54451bd6825cSml 54464045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 54471bd6825cSml (int)param_arr[param_class_opt_ipv4_sctp].value); 54481bd6825cSml 54491bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 54501bd6825cSml "==> nxge_get_priv_prop: %s", valstr)); 54511bd6825cSml goto done; 54521bd6825cSml } 54531bd6825cSml 54541bd6825cSml if (strcmp(pr_name, "_class_opt_ipv6_tcp") == 0) { 54554045d941Ssowmini if (is_default) { 54564045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 54574045d941Ssowmini NXGE_CLASS_FLOW_GEN_SERVER); 54584045d941Ssowmini err = 0; 54594045d941Ssowmini goto done; 54604045d941Ssowmini } 54611bd6825cSml err = nxge_dld_get_ip_opt(nxgep, 54621bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv6_tcp]); 54631bd6825cSml 54644045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 54651bd6825cSml (int)param_arr[param_class_opt_ipv6_tcp].value); 54661bd6825cSml 54671bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 54681bd6825cSml "==> nxge_get_priv_prop: %s", valstr)); 54691bd6825cSml goto done; 54701bd6825cSml } 54711bd6825cSml 54721bd6825cSml if (strcmp(pr_name, "_class_opt_ipv6_udp") == 0) { 54734045d941Ssowmini if (is_default) { 54744045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 54754045d941Ssowmini NXGE_CLASS_FLOW_GEN_SERVER); 54764045d941Ssowmini err = 0; 54774045d941Ssowmini goto done; 54784045d941Ssowmini } 54791bd6825cSml err = nxge_dld_get_ip_opt(nxgep, 54801bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv6_udp]); 54811bd6825cSml 54824045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 54831bd6825cSml (int)param_arr[param_class_opt_ipv6_udp].value); 54841bd6825cSml 54851bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 54861bd6825cSml "==> nxge_get_priv_prop: %s", valstr)); 54871bd6825cSml goto done; 54881bd6825cSml } 54891bd6825cSml 54901bd6825cSml if (strcmp(pr_name, "_class_opt_ipv6_ah") == 0) { 54914045d941Ssowmini if (is_default) { 54924045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 54934045d941Ssowmini NXGE_CLASS_FLOW_GEN_SERVER); 54944045d941Ssowmini err = 0; 54954045d941Ssowmini goto done; 54964045d941Ssowmini } 54971bd6825cSml err = nxge_dld_get_ip_opt(nxgep, 54981bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv6_ah]); 54991bd6825cSml 55004045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 55011bd6825cSml (int)param_arr[param_class_opt_ipv6_ah].value); 55021bd6825cSml 55031bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 55041bd6825cSml "==> nxge_get_priv_prop: %s", valstr)); 55051bd6825cSml goto done; 55061bd6825cSml } 55071bd6825cSml 55081bd6825cSml if (strcmp(pr_name, "_class_opt_ipv6_sctp") == 0) { 55094045d941Ssowmini if (is_default) { 55104045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 55114045d941Ssowmini NXGE_CLASS_FLOW_GEN_SERVER); 55124045d941Ssowmini err = 0; 55134045d941Ssowmini goto done; 55144045d941Ssowmini } 55151bd6825cSml err = nxge_dld_get_ip_opt(nxgep, 55161bd6825cSml (caddr_t)¶m_arr[param_class_opt_ipv6_sctp]); 55171bd6825cSml 55184045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%x", 55191bd6825cSml (int)param_arr[param_class_opt_ipv6_sctp].value); 55201bd6825cSml 55211bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 55221bd6825cSml "==> nxge_get_priv_prop: %s", valstr)); 55231bd6825cSml goto done; 55241bd6825cSml } 55251bd6825cSml 55261bd6825cSml /* Software LSO */ 55271bd6825cSml if (strcmp(pr_name, "_soft_lso_enable") == 0) { 55284045d941Ssowmini if (is_default) { 55294045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%d", 0); 55304045d941Ssowmini err = 0; 55314045d941Ssowmini goto done; 55324045d941Ssowmini } 55334045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), 55344045d941Ssowmini "%d", nxgep->soft_lso_enable); 55351bd6825cSml err = 0; 55361bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 55371bd6825cSml "==> nxge_get_priv_prop: name %s (value %d)", 55381bd6825cSml pr_name, nxgep->soft_lso_enable)); 55391bd6825cSml 55401bd6825cSml goto done; 55411bd6825cSml } 55424045d941Ssowmini if (strcmp(pr_name, "_adv_10gfdx_cap") == 0) { 55434045d941Ssowmini err = 0; 55444045d941Ssowmini if (is_default || 55454045d941Ssowmini nxgep->param_arr[param_anar_10gfdx].value != 0) { 55464045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%d", 1); 55474045d941Ssowmini goto done; 55484045d941Ssowmini } else { 55494045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%d", 0); 55504045d941Ssowmini goto done; 55514045d941Ssowmini } 55524045d941Ssowmini } 55534045d941Ssowmini if (strcmp(pr_name, "_adv_pause_cap") == 0) { 55544045d941Ssowmini err = 0; 55554045d941Ssowmini if (is_default || 55564045d941Ssowmini nxgep->param_arr[param_anar_pause].value != 0) { 55574045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%d", 1); 55584045d941Ssowmini goto done; 55594045d941Ssowmini } else { 55604045d941Ssowmini (void) snprintf(valstr, sizeof (valstr), "%d", 0); 55614045d941Ssowmini goto done; 55624045d941Ssowmini } 55634045d941Ssowmini } 55641bd6825cSml 55651bd6825cSml done: 55661bd6825cSml if (err == 0) { 55671bd6825cSml strsize = (uint_t)strlen(valstr); 55681bd6825cSml if (pr_valsize < strsize) { 55691bd6825cSml err = ENOBUFS; 55701bd6825cSml } else { 55711bd6825cSml (void) strlcpy(pr_val, valstr, pr_valsize); 55721bd6825cSml } 55731bd6825cSml } 55741bd6825cSml 55751bd6825cSml NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 55761bd6825cSml "<== nxge_get_priv_prop: return %d", err)); 55771bd6825cSml return (err); 55781bd6825cSml } 55791bd6825cSml 558044961713Sgirish /* 558144961713Sgirish * Module loading and removing entry points. 558244961713Sgirish */ 558344961713Sgirish 55846f157acbSml DDI_DEFINE_STREAM_OPS(nxge_dev_ops, nulldev, nulldev, nxge_attach, nxge_detach, 5585*19397407SSherry Moore nodev, NULL, D_MP, NULL, nxge_quiesce); 558644961713Sgirish 55872e59129aSraghus #define NXGE_DESC_VER "Sun NIU 10Gb Ethernet" 558844961713Sgirish 558944961713Sgirish /* 559044961713Sgirish * Module linkage information for the kernel. 559144961713Sgirish */ 559244961713Sgirish static struct modldrv nxge_modldrv = { 559344961713Sgirish &mod_driverops, 559444961713Sgirish NXGE_DESC_VER, 559544961713Sgirish &nxge_dev_ops 559644961713Sgirish }; 559744961713Sgirish 559844961713Sgirish static struct modlinkage modlinkage = { 559944961713Sgirish MODREV_1, (void *) &nxge_modldrv, NULL 560044961713Sgirish }; 560144961713Sgirish 560244961713Sgirish int 560344961713Sgirish _init(void) 560444961713Sgirish { 560544961713Sgirish int status; 560644961713Sgirish 560744961713Sgirish NXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _init")); 560844961713Sgirish mac_init_ops(&nxge_dev_ops, "nxge"); 560944961713Sgirish status = ddi_soft_state_init(&nxge_list, sizeof (nxge_t), 0); 561044961713Sgirish if (status != 0) { 561144961713Sgirish NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 56124045d941Ssowmini "failed to init device soft state")); 561344961713Sgirish goto _init_exit; 561444961713Sgirish } 561544961713Sgirish status = mod_install(&modlinkage); 561644961713Sgirish if (status != 0) { 561744961713Sgirish ddi_soft_state_fini(&nxge_list); 561844961713Sgirish NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, "Mod install failed")); 561944961713Sgirish goto _init_exit; 562044961713Sgirish } 562144961713Sgirish 562244961713Sgirish MUTEX_INIT(&nxge_common_lock, NULL, MUTEX_DRIVER, NULL); 562344961713Sgirish 562444961713Sgirish _init_exit: 562544961713Sgirish NXGE_DEBUG_MSG((NULL, MOD_CTL, "_init status = 0x%X", status)); 562644961713Sgirish 562744961713Sgirish return (status); 562844961713Sgirish } 562944961713Sgirish 563044961713Sgirish int 563144961713Sgirish _fini(void) 563244961713Sgirish { 563344961713Sgirish int status; 563444961713Sgirish 563544961713Sgirish NXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _fini")); 563644961713Sgirish 563744961713Sgirish NXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _fini: mod_remove")); 5638a3c5bd6dSspeer 5639a3c5bd6dSspeer if (nxge_mblks_pending) 5640a3c5bd6dSspeer return (EBUSY); 5641a3c5bd6dSspeer 564244961713Sgirish status = mod_remove(&modlinkage); 564344961713Sgirish if (status != DDI_SUCCESS) { 564444961713Sgirish NXGE_DEBUG_MSG((NULL, MOD_CTL, 56454045d941Ssowmini "Module removal failed 0x%08x", 56464045d941Ssowmini status)); 564744961713Sgirish goto _fini_exit; 564844961713Sgirish } 564944961713Sgirish 565044961713Sgirish mac_fini_ops(&nxge_dev_ops); 565144961713Sgirish 565244961713Sgirish ddi_soft_state_fini(&nxge_list); 565344961713Sgirish 565444961713Sgirish MUTEX_DESTROY(&nxge_common_lock); 565544961713Sgirish _fini_exit: 565644961713Sgirish NXGE_DEBUG_MSG((NULL, MOD_CTL, "_fini status = 0x%08x", status)); 565744961713Sgirish 565844961713Sgirish return (status); 565944961713Sgirish } 566044961713Sgirish 566144961713Sgirish int 566244961713Sgirish _info(struct modinfo *modinfop) 566344961713Sgirish { 566444961713Sgirish int status; 566544961713Sgirish 566644961713Sgirish NXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _info")); 566744961713Sgirish status = mod_info(&modlinkage, modinfop); 566844961713Sgirish NXGE_DEBUG_MSG((NULL, MOD_CTL, " _info status = 0x%X", status)); 566944961713Sgirish 567044961713Sgirish return (status); 567144961713Sgirish } 567244961713Sgirish 567344961713Sgirish /*ARGSUSED*/ 567444961713Sgirish static nxge_status_t 567544961713Sgirish nxge_add_intrs(p_nxge_t nxgep) 567644961713Sgirish { 567744961713Sgirish 567844961713Sgirish int intr_types; 567944961713Sgirish int type = 0; 568044961713Sgirish int ddi_status = DDI_SUCCESS; 568144961713Sgirish nxge_status_t status = NXGE_OK; 568244961713Sgirish 568344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs")); 568444961713Sgirish 568544961713Sgirish nxgep->nxge_intr_type.intr_registered = B_FALSE; 568644961713Sgirish nxgep->nxge_intr_type.intr_enabled = B_FALSE; 568744961713Sgirish nxgep->nxge_intr_type.msi_intx_cnt = 0; 568844961713Sgirish nxgep->nxge_intr_type.intr_added = 0; 568944961713Sgirish nxgep->nxge_intr_type.niu_msi_enable = B_FALSE; 569044961713Sgirish nxgep->nxge_intr_type.intr_type = 0; 569144961713Sgirish 569244961713Sgirish if (nxgep->niu_type == N2_NIU) { 569344961713Sgirish nxgep->nxge_intr_type.niu_msi_enable = B_TRUE; 569444961713Sgirish } else if (nxge_msi_enable) { 569544961713Sgirish nxgep->nxge_intr_type.niu_msi_enable = B_TRUE; 569644961713Sgirish } 569744961713Sgirish 569844961713Sgirish /* Get the supported interrupt types */ 569944961713Sgirish if ((ddi_status = ddi_intr_get_supported_types(nxgep->dip, &intr_types)) 57004045d941Ssowmini != DDI_SUCCESS) { 570144961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_add_intrs: " 57024045d941Ssowmini "ddi_intr_get_supported_types failed: status 0x%08x", 57034045d941Ssowmini ddi_status)); 570444961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 570544961713Sgirish } 570644961713Sgirish nxgep->nxge_intr_type.intr_types = intr_types; 570744961713Sgirish 570844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 57094045d941Ssowmini "ddi_intr_get_supported_types: 0x%08x", intr_types)); 571044961713Sgirish 571144961713Sgirish /* 571244961713Sgirish * Solaris MSIX is not supported yet. use MSI for now. 571344961713Sgirish * nxge_msi_enable (1): 571444961713Sgirish * 1 - MSI 2 - MSI-X others - FIXED 571544961713Sgirish */ 571644961713Sgirish switch (nxge_msi_enable) { 571744961713Sgirish default: 571844961713Sgirish type = DDI_INTR_TYPE_FIXED; 571944961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: " 57204045d941Ssowmini "use fixed (intx emulation) type %08x", 57214045d941Ssowmini type)); 572244961713Sgirish break; 572344961713Sgirish 572444961713Sgirish case 2: 572544961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: " 57264045d941Ssowmini "ddi_intr_get_supported_types: 0x%08x", intr_types)); 572744961713Sgirish if (intr_types & DDI_INTR_TYPE_MSIX) { 572844961713Sgirish type = DDI_INTR_TYPE_MSIX; 572944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 57304045d941Ssowmini "ddi_intr_get_supported_types: MSIX 0x%08x", 57314045d941Ssowmini type)); 573244961713Sgirish } else if (intr_types & DDI_INTR_TYPE_MSI) { 573344961713Sgirish type = DDI_INTR_TYPE_MSI; 573444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 57354045d941Ssowmini "ddi_intr_get_supported_types: MSI 0x%08x", 57364045d941Ssowmini type)); 573744961713Sgirish } else if (intr_types & DDI_INTR_TYPE_FIXED) { 573844961713Sgirish type = DDI_INTR_TYPE_FIXED; 573944961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: " 57404045d941Ssowmini "ddi_intr_get_supported_types: MSXED0x%08x", 57414045d941Ssowmini type)); 574244961713Sgirish } 574344961713Sgirish break; 574444961713Sgirish 574544961713Sgirish case 1: 574644961713Sgirish if (intr_types & DDI_INTR_TYPE_MSI) { 574744961713Sgirish type = DDI_INTR_TYPE_MSI; 574844961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: " 57494045d941Ssowmini "ddi_intr_get_supported_types: MSI 0x%08x", 57504045d941Ssowmini type)); 575144961713Sgirish } else if (intr_types & DDI_INTR_TYPE_MSIX) { 575244961713Sgirish type = DDI_INTR_TYPE_MSIX; 575344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 57544045d941Ssowmini "ddi_intr_get_supported_types: MSIX 0x%08x", 57554045d941Ssowmini type)); 575644961713Sgirish } else if (intr_types & DDI_INTR_TYPE_FIXED) { 575744961713Sgirish type = DDI_INTR_TYPE_FIXED; 575844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 57594045d941Ssowmini "ddi_intr_get_supported_types: MSXED0x%08x", 57604045d941Ssowmini type)); 576144961713Sgirish } 576244961713Sgirish } 576344961713Sgirish 576444961713Sgirish nxgep->nxge_intr_type.intr_type = type; 576544961713Sgirish if ((type == DDI_INTR_TYPE_MSIX || type == DDI_INTR_TYPE_MSI || 57664045d941Ssowmini type == DDI_INTR_TYPE_FIXED) && 57674045d941Ssowmini nxgep->nxge_intr_type.niu_msi_enable) { 576844961713Sgirish if ((status = nxge_add_intrs_adv(nxgep)) != DDI_SUCCESS) { 576944961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 57704045d941Ssowmini " nxge_add_intrs: " 57714045d941Ssowmini " nxge_add_intrs_adv failed: status 0x%08x", 57724045d941Ssowmini status)); 577344961713Sgirish return (status); 577444961713Sgirish } else { 577544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 57764045d941Ssowmini "interrupts registered : type %d", type)); 577744961713Sgirish nxgep->nxge_intr_type.intr_registered = B_TRUE; 577844961713Sgirish 577944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 57804045d941Ssowmini "\nAdded advanced nxge add_intr_adv " 57814045d941Ssowmini "intr type 0x%x\n", type)); 578244961713Sgirish 578344961713Sgirish return (status); 578444961713Sgirish } 578544961713Sgirish } 578644961713Sgirish 578744961713Sgirish if (!nxgep->nxge_intr_type.intr_registered) { 578844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "==> nxge_add_intrs: " 57894045d941Ssowmini "failed to register interrupts")); 579044961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 579144961713Sgirish } 579244961713Sgirish 579344961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_add_intrs")); 579444961713Sgirish return (status); 579544961713Sgirish } 579644961713Sgirish 579744961713Sgirish /*ARGSUSED*/ 579844961713Sgirish static nxge_status_t 579944961713Sgirish nxge_add_soft_intrs(p_nxge_t nxgep) 580044961713Sgirish { 580144961713Sgirish 580244961713Sgirish int ddi_status = DDI_SUCCESS; 580344961713Sgirish nxge_status_t status = NXGE_OK; 580444961713Sgirish 580544961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_soft_intrs")); 580644961713Sgirish 580744961713Sgirish nxgep->resched_id = NULL; 580844961713Sgirish nxgep->resched_running = B_FALSE; 580944961713Sgirish ddi_status = ddi_add_softintr(nxgep->dip, DDI_SOFTINT_LOW, 58104045d941Ssowmini &nxgep->resched_id, 58114045d941Ssowmini NULL, NULL, nxge_reschedule, (caddr_t)nxgep); 581244961713Sgirish if (ddi_status != DDI_SUCCESS) { 581344961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_add_soft_intrs: " 58144045d941Ssowmini "ddi_add_softintrs failed: status 0x%08x", 58154045d941Ssowmini ddi_status)); 581644961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 581744961713Sgirish } 581844961713Sgirish 581944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_ddi_add_soft_intrs")); 582044961713Sgirish 582144961713Sgirish return (status); 582244961713Sgirish } 582344961713Sgirish 582444961713Sgirish static nxge_status_t 582544961713Sgirish nxge_add_intrs_adv(p_nxge_t nxgep) 582644961713Sgirish { 582744961713Sgirish int intr_type; 582844961713Sgirish p_nxge_intr_t intrp; 582944961713Sgirish 583044961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs_adv")); 583144961713Sgirish 583244961713Sgirish intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 583344961713Sgirish intr_type = intrp->intr_type; 583444961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs_adv: type 0x%x", 58354045d941Ssowmini intr_type)); 583644961713Sgirish 583744961713Sgirish switch (intr_type) { 583844961713Sgirish case DDI_INTR_TYPE_MSI: /* 0x2 */ 583944961713Sgirish case DDI_INTR_TYPE_MSIX: /* 0x4 */ 584044961713Sgirish return (nxge_add_intrs_adv_type(nxgep, intr_type)); 584144961713Sgirish 584244961713Sgirish case DDI_INTR_TYPE_FIXED: /* 0x1 */ 584344961713Sgirish return (nxge_add_intrs_adv_type_fix(nxgep, intr_type)); 584444961713Sgirish 584544961713Sgirish default: 584644961713Sgirish return (NXGE_ERROR); 584744961713Sgirish } 584844961713Sgirish } 584944961713Sgirish 585044961713Sgirish 585144961713Sgirish /*ARGSUSED*/ 585244961713Sgirish static nxge_status_t 585344961713Sgirish nxge_add_intrs_adv_type(p_nxge_t nxgep, uint32_t int_type) 585444961713Sgirish { 585544961713Sgirish dev_info_t *dip = nxgep->dip; 585644961713Sgirish p_nxge_ldg_t ldgp; 585744961713Sgirish p_nxge_intr_t intrp; 585844961713Sgirish uint_t *inthandler; 585944961713Sgirish void *arg1, *arg2; 586044961713Sgirish int behavior; 5861ec090658Sml int nintrs, navail, nrequest; 586244961713Sgirish int nactual, nrequired; 586344961713Sgirish int inum = 0; 586444961713Sgirish int x, y; 586544961713Sgirish int ddi_status = DDI_SUCCESS; 586644961713Sgirish nxge_status_t status = NXGE_OK; 586744961713Sgirish 586844961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs_adv_type")); 586944961713Sgirish intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 587044961713Sgirish intrp->start_inum = 0; 587144961713Sgirish 587244961713Sgirish ddi_status = ddi_intr_get_nintrs(dip, int_type, &nintrs); 587344961713Sgirish if ((ddi_status != DDI_SUCCESS) || (nintrs == 0)) { 587444961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 58754045d941Ssowmini "ddi_intr_get_nintrs() failed, status: 0x%x%, " 58764045d941Ssowmini "nintrs: %d", ddi_status, nintrs)); 587744961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 587844961713Sgirish } 587944961713Sgirish 588044961713Sgirish ddi_status = ddi_intr_get_navail(dip, int_type, &navail); 588144961713Sgirish if ((ddi_status != DDI_SUCCESS) || (navail == 0)) { 588244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 58834045d941Ssowmini "ddi_intr_get_navail() failed, status: 0x%x%, " 58844045d941Ssowmini "nintrs: %d", ddi_status, navail)); 588544961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 588644961713Sgirish } 588744961713Sgirish 588844961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 58894045d941Ssowmini "ddi_intr_get_navail() returned: nintrs %d, navail %d", 58904045d941Ssowmini nintrs, navail)); 589144961713Sgirish 5892ec090658Sml /* PSARC/2007/453 MSI-X interrupt limit override */ 5893ec090658Sml if (int_type == DDI_INTR_TYPE_MSIX) { 5894ec090658Sml nrequest = nxge_create_msi_property(nxgep); 5895ec090658Sml if (nrequest < navail) { 5896ec090658Sml navail = nrequest; 5897ec090658Sml NXGE_DEBUG_MSG((nxgep, INT_CTL, 5898ec090658Sml "nxge_add_intrs_adv_type: nintrs %d " 5899ec090658Sml "navail %d (nrequest %d)", 5900ec090658Sml nintrs, navail, nrequest)); 5901ec090658Sml } 5902ec090658Sml } 5903ec090658Sml 590444961713Sgirish if (int_type == DDI_INTR_TYPE_MSI && !ISP2(navail)) { 590544961713Sgirish /* MSI must be power of 2 */ 590644961713Sgirish if ((navail & 16) == 16) { 590744961713Sgirish navail = 16; 590844961713Sgirish } else if ((navail & 8) == 8) { 590944961713Sgirish navail = 8; 591044961713Sgirish } else if ((navail & 4) == 4) { 591144961713Sgirish navail = 4; 591244961713Sgirish } else if ((navail & 2) == 2) { 591344961713Sgirish navail = 2; 591444961713Sgirish } else { 591544961713Sgirish navail = 1; 591644961713Sgirish } 591744961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 59184045d941Ssowmini "ddi_intr_get_navail(): (msi power of 2) nintrs %d, " 59194045d941Ssowmini "navail %d", nintrs, navail)); 592044961713Sgirish } 592144961713Sgirish 592244961713Sgirish behavior = ((int_type == DDI_INTR_TYPE_FIXED) ? DDI_INTR_ALLOC_STRICT : 59234045d941Ssowmini DDI_INTR_ALLOC_NORMAL); 592444961713Sgirish intrp->intr_size = navail * sizeof (ddi_intr_handle_t); 592544961713Sgirish intrp->htable = kmem_alloc(intrp->intr_size, KM_SLEEP); 592644961713Sgirish ddi_status = ddi_intr_alloc(dip, intrp->htable, int_type, inum, 59274045d941Ssowmini navail, &nactual, behavior); 592844961713Sgirish if (ddi_status != DDI_SUCCESS || nactual == 0) { 592944961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 59304045d941Ssowmini " ddi_intr_alloc() failed: %d", 59314045d941Ssowmini ddi_status)); 593244961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 593344961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 593444961713Sgirish } 593544961713Sgirish 593644961713Sgirish if ((ddi_status = ddi_intr_get_pri(intrp->htable[0], 59374045d941Ssowmini (uint_t *)&intrp->pri)) != DDI_SUCCESS) { 593844961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 59394045d941Ssowmini " ddi_intr_get_pri() failed: %d", 59404045d941Ssowmini ddi_status)); 594144961713Sgirish /* Free already allocated interrupts */ 594244961713Sgirish for (y = 0; y < nactual; y++) { 594344961713Sgirish (void) ddi_intr_free(intrp->htable[y]); 594444961713Sgirish } 594544961713Sgirish 594644961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 594744961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 594844961713Sgirish } 594944961713Sgirish 595044961713Sgirish nrequired = 0; 595144961713Sgirish switch (nxgep->niu_type) { 595244961713Sgirish default: 595344961713Sgirish status = nxge_ldgv_init(nxgep, &nactual, &nrequired); 595444961713Sgirish break; 595544961713Sgirish 595644961713Sgirish case N2_NIU: 595744961713Sgirish status = nxge_ldgv_init_n2(nxgep, &nactual, &nrequired); 595844961713Sgirish break; 595944961713Sgirish } 596044961713Sgirish 596144961713Sgirish if (status != NXGE_OK) { 596244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 59634045d941Ssowmini "nxge_add_intrs_adv_typ:nxge_ldgv_init " 59644045d941Ssowmini "failed: 0x%x", status)); 596544961713Sgirish /* Free already allocated interrupts */ 596644961713Sgirish for (y = 0; y < nactual; y++) { 596744961713Sgirish (void) ddi_intr_free(intrp->htable[y]); 596844961713Sgirish } 596944961713Sgirish 597044961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 597144961713Sgirish return (status); 597244961713Sgirish } 597344961713Sgirish 597444961713Sgirish ldgp = nxgep->ldgvp->ldgp; 597544961713Sgirish for (x = 0; x < nrequired; x++, ldgp++) { 597644961713Sgirish ldgp->vector = (uint8_t)x; 597744961713Sgirish ldgp->intdata = SID_DATA(ldgp->func, x); 597844961713Sgirish arg1 = ldgp->ldvp; 597944961713Sgirish arg2 = nxgep; 598044961713Sgirish if (ldgp->nldvs == 1) { 598144961713Sgirish inthandler = (uint_t *)ldgp->ldvp->ldv_intr_handler; 598244961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 59834045d941Ssowmini "nxge_add_intrs_adv_type: " 59844045d941Ssowmini "arg1 0x%x arg2 0x%x: " 59854045d941Ssowmini "1-1 int handler (entry %d intdata 0x%x)\n", 59864045d941Ssowmini arg1, arg2, 59874045d941Ssowmini x, ldgp->intdata)); 598844961713Sgirish } else if (ldgp->nldvs > 1) { 598944961713Sgirish inthandler = (uint_t *)ldgp->sys_intr_handler; 599044961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 59914045d941Ssowmini "nxge_add_intrs_adv_type: " 59924045d941Ssowmini "arg1 0x%x arg2 0x%x: " 59934045d941Ssowmini "nldevs %d int handler " 59944045d941Ssowmini "(entry %d intdata 0x%x)\n", 59954045d941Ssowmini arg1, arg2, 59964045d941Ssowmini ldgp->nldvs, x, ldgp->intdata)); 599744961713Sgirish } 599844961713Sgirish 599944961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 60004045d941Ssowmini "==> nxge_add_intrs_adv_type: ddi_add_intr(inum) #%d " 60014045d941Ssowmini "htable 0x%llx", x, intrp->htable[x])); 600244961713Sgirish 600344961713Sgirish if ((ddi_status = ddi_intr_add_handler(intrp->htable[x], 60044045d941Ssowmini (ddi_intr_handler_t *)inthandler, arg1, arg2)) 60054045d941Ssowmini != DDI_SUCCESS) { 600644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 60074045d941Ssowmini "==> nxge_add_intrs_adv_type: failed #%d " 60084045d941Ssowmini "status 0x%x", x, ddi_status)); 600944961713Sgirish for (y = 0; y < intrp->intr_added; y++) { 601044961713Sgirish (void) ddi_intr_remove_handler( 60114045d941Ssowmini intrp->htable[y]); 601244961713Sgirish } 601344961713Sgirish /* Free already allocated intr */ 601444961713Sgirish for (y = 0; y < nactual; y++) { 601544961713Sgirish (void) ddi_intr_free(intrp->htable[y]); 601644961713Sgirish } 601744961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 601844961713Sgirish 601944961713Sgirish (void) nxge_ldgv_uninit(nxgep); 602044961713Sgirish 602144961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 602244961713Sgirish } 602344961713Sgirish intrp->intr_added++; 602444961713Sgirish } 602544961713Sgirish 602644961713Sgirish intrp->msi_intx_cnt = nactual; 602744961713Sgirish 602844961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 60294045d941Ssowmini "Requested: %d, Allowed: %d msi_intx_cnt %d intr_added %d", 60304045d941Ssowmini navail, nactual, 60314045d941Ssowmini intrp->msi_intx_cnt, 60324045d941Ssowmini intrp->intr_added)); 603344961713Sgirish 603444961713Sgirish (void) ddi_intr_get_cap(intrp->htable[0], &intrp->intr_cap); 603544961713Sgirish 603644961713Sgirish (void) nxge_intr_ldgv_init(nxgep); 603744961713Sgirish 603844961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_add_intrs_adv_type")); 603944961713Sgirish 604044961713Sgirish return (status); 604144961713Sgirish } 604244961713Sgirish 604344961713Sgirish /*ARGSUSED*/ 604444961713Sgirish static nxge_status_t 604544961713Sgirish nxge_add_intrs_adv_type_fix(p_nxge_t nxgep, uint32_t int_type) 604644961713Sgirish { 604744961713Sgirish dev_info_t *dip = nxgep->dip; 604844961713Sgirish p_nxge_ldg_t ldgp; 604944961713Sgirish p_nxge_intr_t intrp; 605044961713Sgirish uint_t *inthandler; 605144961713Sgirish void *arg1, *arg2; 605244961713Sgirish int behavior; 605344961713Sgirish int nintrs, navail; 605444961713Sgirish int nactual, nrequired; 605544961713Sgirish int inum = 0; 605644961713Sgirish int x, y; 605744961713Sgirish int ddi_status = DDI_SUCCESS; 605844961713Sgirish nxge_status_t status = NXGE_OK; 605944961713Sgirish 606044961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs_adv_type_fix")); 606144961713Sgirish intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 606244961713Sgirish intrp->start_inum = 0; 606344961713Sgirish 606444961713Sgirish ddi_status = ddi_intr_get_nintrs(dip, int_type, &nintrs); 606544961713Sgirish if ((ddi_status != DDI_SUCCESS) || (nintrs == 0)) { 606644961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 60674045d941Ssowmini "ddi_intr_get_nintrs() failed, status: 0x%x%, " 60684045d941Ssowmini "nintrs: %d", status, nintrs)); 606944961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 607044961713Sgirish } 607144961713Sgirish 607244961713Sgirish ddi_status = ddi_intr_get_navail(dip, int_type, &navail); 607344961713Sgirish if ((ddi_status != DDI_SUCCESS) || (navail == 0)) { 607444961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 60754045d941Ssowmini "ddi_intr_get_navail() failed, status: 0x%x%, " 60764045d941Ssowmini "nintrs: %d", ddi_status, navail)); 607744961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 607844961713Sgirish } 607944961713Sgirish 608044961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 60814045d941Ssowmini "ddi_intr_get_navail() returned: nintrs %d, naavail %d", 60824045d941Ssowmini nintrs, navail)); 608344961713Sgirish 608444961713Sgirish behavior = ((int_type == DDI_INTR_TYPE_FIXED) ? DDI_INTR_ALLOC_STRICT : 60854045d941Ssowmini DDI_INTR_ALLOC_NORMAL); 608644961713Sgirish intrp->intr_size = navail * sizeof (ddi_intr_handle_t); 608744961713Sgirish intrp->htable = kmem_alloc(intrp->intr_size, KM_SLEEP); 608844961713Sgirish ddi_status = ddi_intr_alloc(dip, intrp->htable, int_type, inum, 60894045d941Ssowmini navail, &nactual, behavior); 609044961713Sgirish if (ddi_status != DDI_SUCCESS || nactual == 0) { 609144961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 60924045d941Ssowmini " ddi_intr_alloc() failed: %d", 60934045d941Ssowmini ddi_status)); 609444961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 609544961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 609644961713Sgirish } 609744961713Sgirish 609844961713Sgirish if ((ddi_status = ddi_intr_get_pri(intrp->htable[0], 60994045d941Ssowmini (uint_t *)&intrp->pri)) != DDI_SUCCESS) { 610044961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 61014045d941Ssowmini " ddi_intr_get_pri() failed: %d", 61024045d941Ssowmini ddi_status)); 610344961713Sgirish /* Free already allocated interrupts */ 610444961713Sgirish for (y = 0; y < nactual; y++) { 610544961713Sgirish (void) ddi_intr_free(intrp->htable[y]); 610644961713Sgirish } 610744961713Sgirish 610844961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 610944961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 611044961713Sgirish } 611144961713Sgirish 611244961713Sgirish nrequired = 0; 611344961713Sgirish switch (nxgep->niu_type) { 611444961713Sgirish default: 611544961713Sgirish status = nxge_ldgv_init(nxgep, &nactual, &nrequired); 611644961713Sgirish break; 611744961713Sgirish 611844961713Sgirish case N2_NIU: 611944961713Sgirish status = nxge_ldgv_init_n2(nxgep, &nactual, &nrequired); 612044961713Sgirish break; 612144961713Sgirish } 612244961713Sgirish 612344961713Sgirish if (status != NXGE_OK) { 612444961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 61254045d941Ssowmini "nxge_add_intrs_adv_type_fix:nxge_ldgv_init " 61264045d941Ssowmini "failed: 0x%x", status)); 612744961713Sgirish /* Free already allocated interrupts */ 612844961713Sgirish for (y = 0; y < nactual; y++) { 612944961713Sgirish (void) ddi_intr_free(intrp->htable[y]); 613044961713Sgirish } 613144961713Sgirish 613244961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 613344961713Sgirish return (status); 613444961713Sgirish } 613544961713Sgirish 613644961713Sgirish ldgp = nxgep->ldgvp->ldgp; 613744961713Sgirish for (x = 0; x < nrequired; x++, ldgp++) { 613844961713Sgirish ldgp->vector = (uint8_t)x; 613944961713Sgirish if (nxgep->niu_type != N2_NIU) { 614044961713Sgirish ldgp->intdata = SID_DATA(ldgp->func, x); 614144961713Sgirish } 614244961713Sgirish 614344961713Sgirish arg1 = ldgp->ldvp; 614444961713Sgirish arg2 = nxgep; 614544961713Sgirish if (ldgp->nldvs == 1) { 614644961713Sgirish inthandler = (uint_t *)ldgp->ldvp->ldv_intr_handler; 614744961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 61484045d941Ssowmini "nxge_add_intrs_adv_type_fix: " 61494045d941Ssowmini "1-1 int handler(%d) ldg %d ldv %d " 61504045d941Ssowmini "arg1 $%p arg2 $%p\n", 61514045d941Ssowmini x, ldgp->ldg, ldgp->ldvp->ldv, 61524045d941Ssowmini arg1, arg2)); 615344961713Sgirish } else if (ldgp->nldvs > 1) { 615444961713Sgirish inthandler = (uint_t *)ldgp->sys_intr_handler; 615544961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 61564045d941Ssowmini "nxge_add_intrs_adv_type_fix: " 61574045d941Ssowmini "shared ldv %d int handler(%d) ldv %d ldg %d" 61584045d941Ssowmini "arg1 0x%016llx arg2 0x%016llx\n", 61594045d941Ssowmini x, ldgp->nldvs, ldgp->ldg, ldgp->ldvp->ldv, 61604045d941Ssowmini arg1, arg2)); 616144961713Sgirish } 616244961713Sgirish 616344961713Sgirish if ((ddi_status = ddi_intr_add_handler(intrp->htable[x], 61644045d941Ssowmini (ddi_intr_handler_t *)inthandler, arg1, arg2)) 61654045d941Ssowmini != DDI_SUCCESS) { 616644961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 61674045d941Ssowmini "==> nxge_add_intrs_adv_type_fix: failed #%d " 61684045d941Ssowmini "status 0x%x", x, ddi_status)); 616944961713Sgirish for (y = 0; y < intrp->intr_added; y++) { 617044961713Sgirish (void) ddi_intr_remove_handler( 61714045d941Ssowmini intrp->htable[y]); 617244961713Sgirish } 617344961713Sgirish for (y = 0; y < nactual; y++) { 617444961713Sgirish (void) ddi_intr_free(intrp->htable[y]); 617544961713Sgirish } 617644961713Sgirish /* Free already allocated intr */ 617744961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 617844961713Sgirish 617944961713Sgirish (void) nxge_ldgv_uninit(nxgep); 618044961713Sgirish 618144961713Sgirish return (NXGE_ERROR | NXGE_DDI_FAILED); 618244961713Sgirish } 618344961713Sgirish intrp->intr_added++; 618444961713Sgirish } 618544961713Sgirish 618644961713Sgirish intrp->msi_intx_cnt = nactual; 618744961713Sgirish 618844961713Sgirish (void) ddi_intr_get_cap(intrp->htable[0], &intrp->intr_cap); 618944961713Sgirish 619044961713Sgirish status = nxge_intr_ldgv_init(nxgep); 619144961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_add_intrs_adv_type_fix")); 619244961713Sgirish 619344961713Sgirish return (status); 619444961713Sgirish } 619544961713Sgirish 619644961713Sgirish static void 619744961713Sgirish nxge_remove_intrs(p_nxge_t nxgep) 619844961713Sgirish { 619944961713Sgirish int i, inum; 620044961713Sgirish p_nxge_intr_t intrp; 620144961713Sgirish 620244961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_remove_intrs")); 620344961713Sgirish intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 620444961713Sgirish if (!intrp->intr_registered) { 620544961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 62064045d941Ssowmini "<== nxge_remove_intrs: interrupts not registered")); 620744961713Sgirish return; 620844961713Sgirish } 620944961713Sgirish 621044961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_remove_intrs:advanced")); 621144961713Sgirish 621244961713Sgirish if (intrp->intr_cap & DDI_INTR_FLAG_BLOCK) { 621344961713Sgirish (void) ddi_intr_block_disable(intrp->htable, 62144045d941Ssowmini intrp->intr_added); 621544961713Sgirish } else { 621644961713Sgirish for (i = 0; i < intrp->intr_added; i++) { 621744961713Sgirish (void) ddi_intr_disable(intrp->htable[i]); 621844961713Sgirish } 621944961713Sgirish } 622044961713Sgirish 622144961713Sgirish for (inum = 0; inum < intrp->intr_added; inum++) { 622244961713Sgirish if (intrp->htable[inum]) { 622344961713Sgirish (void) ddi_intr_remove_handler(intrp->htable[inum]); 622444961713Sgirish } 622544961713Sgirish } 622644961713Sgirish 622744961713Sgirish for (inum = 0; inum < intrp->msi_intx_cnt; inum++) { 622844961713Sgirish if (intrp->htable[inum]) { 622944961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, 62304045d941Ssowmini "nxge_remove_intrs: ddi_intr_free inum %d " 62314045d941Ssowmini "msi_intx_cnt %d intr_added %d", 62324045d941Ssowmini inum, 62334045d941Ssowmini intrp->msi_intx_cnt, 62344045d941Ssowmini intrp->intr_added)); 623544961713Sgirish 623644961713Sgirish (void) ddi_intr_free(intrp->htable[inum]); 623744961713Sgirish } 623844961713Sgirish } 623944961713Sgirish 624044961713Sgirish kmem_free(intrp->htable, intrp->intr_size); 624144961713Sgirish intrp->intr_registered = B_FALSE; 624244961713Sgirish intrp->intr_enabled = B_FALSE; 624344961713Sgirish intrp->msi_intx_cnt = 0; 624444961713Sgirish intrp->intr_added = 0; 624544961713Sgirish 6246a3c5bd6dSspeer (void) nxge_ldgv_uninit(nxgep); 6247a3c5bd6dSspeer 6248ec090658Sml (void) ddi_prop_remove(DDI_DEV_T_NONE, nxgep->dip, 6249ec090658Sml "#msix-request"); 6250ec090658Sml 625144961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_remove_intrs")); 625244961713Sgirish } 625344961713Sgirish 625444961713Sgirish /*ARGSUSED*/ 625544961713Sgirish static void 625644961713Sgirish nxge_remove_soft_intrs(p_nxge_t nxgep) 625744961713Sgirish { 625844961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_remove_soft_intrs")); 625944961713Sgirish if (nxgep->resched_id) { 626044961713Sgirish ddi_remove_softintr(nxgep->resched_id); 626144961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 62624045d941Ssowmini "==> nxge_remove_soft_intrs: removed")); 626344961713Sgirish nxgep->resched_id = NULL; 626444961713Sgirish } 626544961713Sgirish 626644961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_remove_soft_intrs")); 626744961713Sgirish } 626844961713Sgirish 626944961713Sgirish /*ARGSUSED*/ 627044961713Sgirish static void 627144961713Sgirish nxge_intrs_enable(p_nxge_t nxgep) 627244961713Sgirish { 627344961713Sgirish p_nxge_intr_t intrp; 627444961713Sgirish int i; 627544961713Sgirish int status; 627644961713Sgirish 627744961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_enable")); 627844961713Sgirish 627944961713Sgirish intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 628044961713Sgirish 628144961713Sgirish if (!intrp->intr_registered) { 628244961713Sgirish NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_intrs_enable: " 62834045d941Ssowmini "interrupts are not registered")); 628444961713Sgirish return; 628544961713Sgirish } 628644961713Sgirish 628744961713Sgirish if (intrp->intr_enabled) { 628844961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, 62894045d941Ssowmini "<== nxge_intrs_enable: already enabled")); 629044961713Sgirish return; 629144961713Sgirish } 629244961713Sgirish 629344961713Sgirish if (intrp->intr_cap & DDI_INTR_FLAG_BLOCK) { 629444961713Sgirish status = ddi_intr_block_enable(intrp->htable, 62954045d941Ssowmini intrp->intr_added); 629644961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_enable " 62974045d941Ssowmini "block enable - status 0x%x total inums #%d\n", 62984045d941Ssowmini status, intrp->intr_added)); 629944961713Sgirish } else { 630044961713Sgirish for (i = 0; i < intrp->intr_added; i++) { 630144961713Sgirish status = ddi_intr_enable(intrp->htable[i]); 630244961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_enable " 63034045d941Ssowmini "ddi_intr_enable:enable - status 0x%x " 63044045d941Ssowmini "total inums %d enable inum #%d\n", 63054045d941Ssowmini status, intrp->intr_added, i)); 630644961713Sgirish if (status == DDI_SUCCESS) { 630744961713Sgirish intrp->intr_enabled = B_TRUE; 630844961713Sgirish } 630944961713Sgirish } 631044961713Sgirish } 631144961713Sgirish 631244961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intrs_enable")); 631344961713Sgirish } 631444961713Sgirish 631544961713Sgirish /*ARGSUSED*/ 631644961713Sgirish static void 631744961713Sgirish nxge_intrs_disable(p_nxge_t nxgep) 631844961713Sgirish { 631944961713Sgirish p_nxge_intr_t intrp; 632044961713Sgirish int i; 632144961713Sgirish 632244961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_disable")); 632344961713Sgirish 632444961713Sgirish intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 632544961713Sgirish 632644961713Sgirish if (!intrp->intr_registered) { 632744961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intrs_disable: " 63284045d941Ssowmini "interrupts are not registered")); 632944961713Sgirish return; 633044961713Sgirish } 633144961713Sgirish 633244961713Sgirish if (intrp->intr_cap & DDI_INTR_FLAG_BLOCK) { 633344961713Sgirish (void) ddi_intr_block_disable(intrp->htable, 63344045d941Ssowmini intrp->intr_added); 633544961713Sgirish } else { 633644961713Sgirish for (i = 0; i < intrp->intr_added; i++) { 633744961713Sgirish (void) ddi_intr_disable(intrp->htable[i]); 633844961713Sgirish } 633944961713Sgirish } 634044961713Sgirish 634144961713Sgirish intrp->intr_enabled = B_FALSE; 634244961713Sgirish NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intrs_disable")); 634344961713Sgirish } 634444961713Sgirish 634544961713Sgirish static nxge_status_t 634644961713Sgirish nxge_mac_register(p_nxge_t nxgep) 634744961713Sgirish { 634844961713Sgirish mac_register_t *macp; 634944961713Sgirish int status; 635044961713Sgirish 635144961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_mac_register")); 635244961713Sgirish 635344961713Sgirish if ((macp = mac_alloc(MAC_VERSION)) == NULL) 635444961713Sgirish return (NXGE_ERROR); 635544961713Sgirish 635644961713Sgirish macp->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 635744961713Sgirish macp->m_driver = nxgep; 635844961713Sgirish macp->m_dip = nxgep->dip; 635944961713Sgirish macp->m_src_addr = nxgep->ouraddr.ether_addr_octet; 636044961713Sgirish macp->m_callbacks = &nxge_m_callbacks; 636144961713Sgirish macp->m_min_sdu = 0; 63621bd6825cSml nxgep->mac.default_mtu = nxgep->mac.maxframesize - 63631bd6825cSml NXGE_EHEADER_VLAN_CRC; 63641bd6825cSml macp->m_max_sdu = nxgep->mac.default_mtu; 6365d62bc4baSyz macp->m_margin = VLAN_TAGSZ; 63664045d941Ssowmini macp->m_priv_props = nxge_priv_props; 63674045d941Ssowmini macp->m_priv_prop_count = NXGE_MAX_PRIV_PROPS; 636844961713Sgirish 63691bd6825cSml NXGE_DEBUG_MSG((nxgep, MAC_CTL, 63701bd6825cSml "==> nxge_mac_register: instance %d " 63711bd6825cSml "max_sdu %d margin %d maxframe %d (header %d)", 63721bd6825cSml nxgep->instance, 63731bd6825cSml macp->m_max_sdu, macp->m_margin, 63741bd6825cSml nxgep->mac.maxframesize, 63751bd6825cSml NXGE_EHEADER_VLAN_CRC)); 63761bd6825cSml 637744961713Sgirish status = mac_register(macp, &nxgep->mach); 637844961713Sgirish mac_free(macp); 637944961713Sgirish 638044961713Sgirish if (status != 0) { 638144961713Sgirish cmn_err(CE_WARN, 63824045d941Ssowmini "!nxge_mac_register failed (status %d instance %d)", 63834045d941Ssowmini status, nxgep->instance); 638444961713Sgirish return (NXGE_ERROR); 638544961713Sgirish } 638644961713Sgirish 638744961713Sgirish NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_mac_register success " 63884045d941Ssowmini "(instance %d)", nxgep->instance)); 638944961713Sgirish 639044961713Sgirish return (NXGE_OK); 639144961713Sgirish } 639244961713Sgirish 639344961713Sgirish void 639444961713Sgirish nxge_err_inject(p_nxge_t nxgep, queue_t *wq, mblk_t *mp) 639544961713Sgirish { 639644961713Sgirish ssize_t size; 639744961713Sgirish mblk_t *nmp; 639844961713Sgirish uint8_t blk_id; 639944961713Sgirish uint8_t chan; 640044961713Sgirish uint32_t err_id; 640144961713Sgirish err_inject_t *eip; 640244961713Sgirish 640344961713Sgirish NXGE_DEBUG_MSG((nxgep, STR_CTL, "==> nxge_err_inject")); 640444961713Sgirish 640544961713Sgirish size = 1024; 640644961713Sgirish nmp = mp->b_cont; 640744961713Sgirish eip = (err_inject_t *)nmp->b_rptr; 640844961713Sgirish blk_id = eip->blk_id; 640944961713Sgirish err_id = eip->err_id; 641044961713Sgirish chan = eip->chan; 641144961713Sgirish cmn_err(CE_NOTE, "!blk_id = 0x%x\n", blk_id); 641244961713Sgirish cmn_err(CE_NOTE, "!err_id = 0x%x\n", err_id); 641344961713Sgirish cmn_err(CE_NOTE, "!chan = 0x%x\n", chan); 641444961713Sgirish switch (blk_id) { 641544961713Sgirish case MAC_BLK_ID: 641644961713Sgirish break; 641744961713Sgirish case TXMAC_BLK_ID: 641844961713Sgirish break; 641944961713Sgirish case RXMAC_BLK_ID: 642044961713Sgirish break; 642144961713Sgirish case MIF_BLK_ID: 642244961713Sgirish break; 642344961713Sgirish case IPP_BLK_ID: 642444961713Sgirish nxge_ipp_inject_err(nxgep, err_id); 642544961713Sgirish break; 642644961713Sgirish case TXC_BLK_ID: 642744961713Sgirish nxge_txc_inject_err(nxgep, err_id); 642844961713Sgirish break; 642944961713Sgirish case TXDMA_BLK_ID: 643044961713Sgirish nxge_txdma_inject_err(nxgep, err_id, chan); 643144961713Sgirish break; 643244961713Sgirish case RXDMA_BLK_ID: 643344961713Sgirish nxge_rxdma_inject_err(nxgep, err_id, chan); 643444961713Sgirish break; 643544961713Sgirish case ZCP_BLK_ID: 643644961713Sgirish nxge_zcp_inject_err(nxgep, err_id); 643744961713Sgirish break; 643844961713Sgirish case ESPC_BLK_ID: 643944961713Sgirish break; 644044961713Sgirish case FFLP_BLK_ID: 644144961713Sgirish break; 644244961713Sgirish case PHY_BLK_ID: 644344961713Sgirish break; 644444961713Sgirish case ETHER_SERDES_BLK_ID: 644544961713Sgirish break; 644644961713Sgirish case PCIE_SERDES_BLK_ID: 644744961713Sgirish break; 644844961713Sgirish case VIR_BLK_ID: 644944961713Sgirish break; 645044961713Sgirish } 645144961713Sgirish 645244961713Sgirish nmp->b_wptr = nmp->b_rptr + size; 645344961713Sgirish NXGE_DEBUG_MSG((nxgep, STR_CTL, "<== nxge_err_inject")); 645444961713Sgirish 645544961713Sgirish miocack(wq, mp, (int)size, 0); 645644961713Sgirish } 645744961713Sgirish 645844961713Sgirish static int 645944961713Sgirish nxge_init_common_dev(p_nxge_t nxgep) 646044961713Sgirish { 646144961713Sgirish p_nxge_hw_list_t hw_p; 646244961713Sgirish dev_info_t *p_dip; 646344961713Sgirish 646444961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, "==> nxge_init_common_device")); 646544961713Sgirish 646644961713Sgirish p_dip = nxgep->p_dip; 646744961713Sgirish MUTEX_ENTER(&nxge_common_lock); 646844961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 64694045d941Ssowmini "==> nxge_init_common_dev:func # %d", 64704045d941Ssowmini nxgep->function_num)); 647144961713Sgirish /* 647244961713Sgirish * Loop through existing per neptune hardware list. 647344961713Sgirish */ 647444961713Sgirish for (hw_p = nxge_hw_list; hw_p; hw_p = hw_p->next) { 647544961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 64764045d941Ssowmini "==> nxge_init_common_device:func # %d " 64774045d941Ssowmini "hw_p $%p parent dip $%p", 64784045d941Ssowmini nxgep->function_num, 64794045d941Ssowmini hw_p, 64804045d941Ssowmini p_dip)); 648144961713Sgirish if (hw_p->parent_devp == p_dip) { 648244961713Sgirish nxgep->nxge_hw_p = hw_p; 648344961713Sgirish hw_p->ndevs++; 648444961713Sgirish hw_p->nxge_p[nxgep->function_num] = nxgep; 648544961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 64864045d941Ssowmini "==> nxge_init_common_device:func # %d " 64874045d941Ssowmini "hw_p $%p parent dip $%p " 64884045d941Ssowmini "ndevs %d (found)", 64894045d941Ssowmini nxgep->function_num, 64904045d941Ssowmini hw_p, 64914045d941Ssowmini p_dip, 64924045d941Ssowmini hw_p->ndevs)); 649344961713Sgirish break; 649444961713Sgirish } 649544961713Sgirish } 649644961713Sgirish 649744961713Sgirish if (hw_p == NULL) { 649844961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 64994045d941Ssowmini "==> nxge_init_common_device:func # %d " 65004045d941Ssowmini "parent dip $%p (new)", 65014045d941Ssowmini nxgep->function_num, 65024045d941Ssowmini p_dip)); 650344961713Sgirish hw_p = kmem_zalloc(sizeof (nxge_hw_list_t), KM_SLEEP); 650444961713Sgirish hw_p->parent_devp = p_dip; 650544961713Sgirish hw_p->magic = NXGE_NEPTUNE_MAGIC; 650644961713Sgirish nxgep->nxge_hw_p = hw_p; 650744961713Sgirish hw_p->ndevs++; 650844961713Sgirish hw_p->nxge_p[nxgep->function_num] = nxgep; 650944961713Sgirish hw_p->next = nxge_hw_list; 651059ac0c16Sdavemq if (nxgep->niu_type == N2_NIU) { 651159ac0c16Sdavemq hw_p->niu_type = N2_NIU; 651259ac0c16Sdavemq hw_p->platform_type = P_NEPTUNE_NIU; 651359ac0c16Sdavemq } else { 651459ac0c16Sdavemq hw_p->niu_type = NIU_TYPE_NONE; 65152e59129aSraghus hw_p->platform_type = P_NEPTUNE_NONE; 651659ac0c16Sdavemq } 651744961713Sgirish 651844961713Sgirish MUTEX_INIT(&hw_p->nxge_cfg_lock, NULL, MUTEX_DRIVER, NULL); 651944961713Sgirish MUTEX_INIT(&hw_p->nxge_tcam_lock, NULL, MUTEX_DRIVER, NULL); 652044961713Sgirish MUTEX_INIT(&hw_p->nxge_vlan_lock, NULL, MUTEX_DRIVER, NULL); 652144961713Sgirish MUTEX_INIT(&hw_p->nxge_mdio_lock, NULL, MUTEX_DRIVER, NULL); 652244961713Sgirish 652344961713Sgirish nxge_hw_list = hw_p; 652459ac0c16Sdavemq 652559ac0c16Sdavemq (void) nxge_scan_ports_phy(nxgep, nxge_hw_list); 652644961713Sgirish } 652744961713Sgirish 652844961713Sgirish MUTEX_EXIT(&nxge_common_lock); 652959ac0c16Sdavemq 65302e59129aSraghus nxgep->platform_type = hw_p->platform_type; 653159ac0c16Sdavemq if (nxgep->niu_type != N2_NIU) { 653259ac0c16Sdavemq nxgep->niu_type = hw_p->niu_type; 653359ac0c16Sdavemq } 653459ac0c16Sdavemq 653544961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 65364045d941Ssowmini "==> nxge_init_common_device (nxge_hw_list) $%p", 65374045d941Ssowmini nxge_hw_list)); 653844961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, "<== nxge_init_common_device")); 653944961713Sgirish 654044961713Sgirish return (NXGE_OK); 654144961713Sgirish } 654244961713Sgirish 654344961713Sgirish static void 654444961713Sgirish nxge_uninit_common_dev(p_nxge_t nxgep) 654544961713Sgirish { 654644961713Sgirish p_nxge_hw_list_t hw_p, h_hw_p; 65470b0beae0Sspeer p_nxge_dma_pt_cfg_t p_dma_cfgp; 65480b0beae0Sspeer p_nxge_hw_pt_cfg_t p_cfgp; 654944961713Sgirish dev_info_t *p_dip; 655044961713Sgirish 655144961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, "==> nxge_uninit_common_device")); 655244961713Sgirish if (nxgep->nxge_hw_p == NULL) { 655344961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 65544045d941Ssowmini "<== nxge_uninit_common_device (no common)")); 655544961713Sgirish return; 655644961713Sgirish } 655744961713Sgirish 655844961713Sgirish MUTEX_ENTER(&nxge_common_lock); 655944961713Sgirish h_hw_p = nxge_hw_list; 656044961713Sgirish for (hw_p = nxge_hw_list; hw_p; hw_p = hw_p->next) { 656144961713Sgirish p_dip = hw_p->parent_devp; 656244961713Sgirish if (nxgep->nxge_hw_p == hw_p && 65634045d941Ssowmini p_dip == nxgep->p_dip && 65644045d941Ssowmini nxgep->nxge_hw_p->magic == NXGE_NEPTUNE_MAGIC && 65654045d941Ssowmini hw_p->magic == NXGE_NEPTUNE_MAGIC) { 656644961713Sgirish 656744961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 65684045d941Ssowmini "==> nxge_uninit_common_device:func # %d " 65694045d941Ssowmini "hw_p $%p parent dip $%p " 65704045d941Ssowmini "ndevs %d (found)", 65714045d941Ssowmini nxgep->function_num, 65724045d941Ssowmini hw_p, 65734045d941Ssowmini p_dip, 65744045d941Ssowmini hw_p->ndevs)); 657544961713Sgirish 65760b0beae0Sspeer /* 65770b0beae0Sspeer * Release the RDC table, a shared resoruce 65780b0beae0Sspeer * of the nxge hardware. The RDC table was 65790b0beae0Sspeer * assigned to this instance of nxge in 65800b0beae0Sspeer * nxge_use_cfg_dma_config(). 65810b0beae0Sspeer */ 65829d5b8bc5SMichael Speer if (!isLDOMguest(nxgep)) { 65839d5b8bc5SMichael Speer p_dma_cfgp = 65849d5b8bc5SMichael Speer (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 65859d5b8bc5SMichael Speer p_cfgp = 65869d5b8bc5SMichael Speer (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 65879d5b8bc5SMichael Speer (void) nxge_fzc_rdc_tbl_unbind(nxgep, 65889d5b8bc5SMichael Speer p_cfgp->def_mac_rxdma_grpid); 65899d5b8bc5SMichael Speer } 65900b0beae0Sspeer 659144961713Sgirish if (hw_p->ndevs) { 659244961713Sgirish hw_p->ndevs--; 659344961713Sgirish } 659444961713Sgirish hw_p->nxge_p[nxgep->function_num] = NULL; 659544961713Sgirish if (!hw_p->ndevs) { 659644961713Sgirish MUTEX_DESTROY(&hw_p->nxge_vlan_lock); 659744961713Sgirish MUTEX_DESTROY(&hw_p->nxge_tcam_lock); 659844961713Sgirish MUTEX_DESTROY(&hw_p->nxge_cfg_lock); 659944961713Sgirish MUTEX_DESTROY(&hw_p->nxge_mdio_lock); 660044961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 66014045d941Ssowmini "==> nxge_uninit_common_device: " 66024045d941Ssowmini "func # %d " 66034045d941Ssowmini "hw_p $%p parent dip $%p " 66044045d941Ssowmini "ndevs %d (last)", 66054045d941Ssowmini nxgep->function_num, 66064045d941Ssowmini hw_p, 66074045d941Ssowmini p_dip, 66084045d941Ssowmini hw_p->ndevs)); 660944961713Sgirish 6610678453a8Sspeer nxge_hio_uninit(nxgep); 6611678453a8Sspeer 661244961713Sgirish if (hw_p == nxge_hw_list) { 661344961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 66144045d941Ssowmini "==> nxge_uninit_common_device:" 66154045d941Ssowmini "remove head func # %d " 66164045d941Ssowmini "hw_p $%p parent dip $%p " 66174045d941Ssowmini "ndevs %d (head)", 66184045d941Ssowmini nxgep->function_num, 66194045d941Ssowmini hw_p, 66204045d941Ssowmini p_dip, 66214045d941Ssowmini hw_p->ndevs)); 662244961713Sgirish nxge_hw_list = hw_p->next; 662344961713Sgirish } else { 662444961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 66254045d941Ssowmini "==> nxge_uninit_common_device:" 66264045d941Ssowmini "remove middle func # %d " 66274045d941Ssowmini "hw_p $%p parent dip $%p " 66284045d941Ssowmini "ndevs %d (middle)", 66294045d941Ssowmini nxgep->function_num, 66304045d941Ssowmini hw_p, 66314045d941Ssowmini p_dip, 66324045d941Ssowmini hw_p->ndevs)); 663344961713Sgirish h_hw_p->next = hw_p->next; 663444961713Sgirish } 663544961713Sgirish 6636678453a8Sspeer nxgep->nxge_hw_p = NULL; 663744961713Sgirish KMEM_FREE(hw_p, sizeof (nxge_hw_list_t)); 663844961713Sgirish } 663944961713Sgirish break; 664044961713Sgirish } else { 664144961713Sgirish h_hw_p = hw_p; 664244961713Sgirish } 664344961713Sgirish } 664444961713Sgirish 664544961713Sgirish MUTEX_EXIT(&nxge_common_lock); 664644961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, 66474045d941Ssowmini "==> nxge_uninit_common_device (nxge_hw_list) $%p", 66484045d941Ssowmini nxge_hw_list)); 664944961713Sgirish 665044961713Sgirish NXGE_DEBUG_MSG((nxgep, MOD_CTL, "<= nxge_uninit_common_device")); 665144961713Sgirish } 665259ac0c16Sdavemq 665359ac0c16Sdavemq /* 66542e59129aSraghus * Determines the number of ports from the niu_type or the platform type. 665559ac0c16Sdavemq * Returns the number of ports, or returns zero on failure. 665659ac0c16Sdavemq */ 665759ac0c16Sdavemq 665859ac0c16Sdavemq int 66592e59129aSraghus nxge_get_nports(p_nxge_t nxgep) 666059ac0c16Sdavemq { 666159ac0c16Sdavemq int nports = 0; 666259ac0c16Sdavemq 66632e59129aSraghus switch (nxgep->niu_type) { 666459ac0c16Sdavemq case N2_NIU: 666559ac0c16Sdavemq case NEPTUNE_2_10GF: 666659ac0c16Sdavemq nports = 2; 666759ac0c16Sdavemq break; 666859ac0c16Sdavemq case NEPTUNE_4_1GC: 666959ac0c16Sdavemq case NEPTUNE_2_10GF_2_1GC: 667059ac0c16Sdavemq case NEPTUNE_1_10GF_3_1GC: 667159ac0c16Sdavemq case NEPTUNE_1_1GC_1_10GF_2_1GC: 667259a835ddSjoycey case NEPTUNE_2_10GF_2_1GRF: 667359ac0c16Sdavemq nports = 4; 667459ac0c16Sdavemq break; 667559ac0c16Sdavemq default: 66762e59129aSraghus switch (nxgep->platform_type) { 66772e59129aSraghus case P_NEPTUNE_NIU: 66782e59129aSraghus case P_NEPTUNE_ATLAS_2PORT: 66792e59129aSraghus nports = 2; 66802e59129aSraghus break; 66812e59129aSraghus case P_NEPTUNE_ATLAS_4PORT: 66822e59129aSraghus case P_NEPTUNE_MARAMBA_P0: 66832e59129aSraghus case P_NEPTUNE_MARAMBA_P1: 6684d81011f0Ssbehera case P_NEPTUNE_ALONSO: 66852e59129aSraghus nports = 4; 66862e59129aSraghus break; 66872e59129aSraghus default: 66882e59129aSraghus break; 66892e59129aSraghus } 669059ac0c16Sdavemq break; 669159ac0c16Sdavemq } 669259ac0c16Sdavemq 669359ac0c16Sdavemq return (nports); 669459ac0c16Sdavemq } 6695ec090658Sml 6696ec090658Sml /* 6697ec090658Sml * The following two functions are to support 6698ec090658Sml * PSARC/2007/453 MSI-X interrupt limit override. 6699ec090658Sml */ 6700ec090658Sml static int 6701ec090658Sml nxge_create_msi_property(p_nxge_t nxgep) 6702ec090658Sml { 6703ec090658Sml int nmsi; 6704ec090658Sml extern int ncpus; 6705ec090658Sml 6706ec090658Sml NXGE_DEBUG_MSG((nxgep, MOD_CTL, "==>nxge_create_msi_property")); 6707ec090658Sml 6708ec090658Sml switch (nxgep->mac.portmode) { 6709ec090658Sml case PORT_10G_COPPER: 6710ec090658Sml case PORT_10G_FIBER: 671100161856Syc case PORT_10G_TN1010: 6712ec090658Sml (void) ddi_prop_create(DDI_DEV_T_NONE, nxgep->dip, 6713ec090658Sml DDI_PROP_CANSLEEP, "#msix-request", NULL, 0); 6714ec090658Sml /* 6715ec090658Sml * The maximum MSI-X requested will be 8. 6716ec090658Sml * If the # of CPUs is less than 8, we will reqeust 6717ec090658Sml * # MSI-X based on the # of CPUs. 6718ec090658Sml */ 6719ec090658Sml if (ncpus >= NXGE_MSIX_REQUEST_10G) { 6720ec090658Sml nmsi = NXGE_MSIX_REQUEST_10G; 6721ec090658Sml } else { 6722ec090658Sml nmsi = ncpus; 6723ec090658Sml } 6724ec090658Sml NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6725ec090658Sml "==>nxge_create_msi_property(10G): exists 0x%x (nmsi %d)", 6726ec090658Sml ddi_prop_exists(DDI_DEV_T_NONE, nxgep->dip, 6727ec090658Sml DDI_PROP_CANSLEEP, "#msix-request"), nmsi)); 6728ec090658Sml break; 6729ec090658Sml 6730ec090658Sml default: 6731ec090658Sml nmsi = NXGE_MSIX_REQUEST_1G; 6732ec090658Sml NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6733ec090658Sml "==>nxge_create_msi_property(1G): exists 0x%x (nmsi %d)", 6734ec090658Sml ddi_prop_exists(DDI_DEV_T_NONE, nxgep->dip, 6735ec090658Sml DDI_PROP_CANSLEEP, "#msix-request"), nmsi)); 6736ec090658Sml break; 6737ec090658Sml } 6738ec090658Sml 6739ec090658Sml NXGE_DEBUG_MSG((nxgep, MOD_CTL, "<==nxge_create_msi_property")); 6740ec090658Sml return (nmsi); 6741ec090658Sml } 67424045d941Ssowmini 67434045d941Ssowmini /* ARGSUSED */ 67444045d941Ssowmini static int 67454045d941Ssowmini nxge_get_def_val(nxge_t *nxgep, mac_prop_id_t pr_num, uint_t pr_valsize, 67464045d941Ssowmini void *pr_val) 67474045d941Ssowmini { 67484045d941Ssowmini int err = 0; 67494045d941Ssowmini link_flowctrl_t fl; 67504045d941Ssowmini 67514045d941Ssowmini switch (pr_num) { 67523fd94f8cSam case MAC_PROP_AUTONEG: 67534045d941Ssowmini *(uint8_t *)pr_val = 1; 67544045d941Ssowmini break; 67553fd94f8cSam case MAC_PROP_FLOWCTRL: 67564045d941Ssowmini if (pr_valsize < sizeof (link_flowctrl_t)) 67574045d941Ssowmini return (EINVAL); 67584045d941Ssowmini fl = LINK_FLOWCTRL_RX; 67594045d941Ssowmini bcopy(&fl, pr_val, sizeof (fl)); 67604045d941Ssowmini break; 67613fd94f8cSam case MAC_PROP_ADV_1000FDX_CAP: 67623fd94f8cSam case MAC_PROP_EN_1000FDX_CAP: 67634045d941Ssowmini *(uint8_t *)pr_val = 1; 67644045d941Ssowmini break; 67653fd94f8cSam case MAC_PROP_ADV_100FDX_CAP: 67663fd94f8cSam case MAC_PROP_EN_100FDX_CAP: 67674045d941Ssowmini *(uint8_t *)pr_val = 1; 67684045d941Ssowmini break; 67694045d941Ssowmini default: 67704045d941Ssowmini err = ENOTSUP; 67714045d941Ssowmini break; 67724045d941Ssowmini } 67734045d941Ssowmini return (err); 67744045d941Ssowmini } 67756f157acbSml 67766f157acbSml 67776f157acbSml /* 67786f157acbSml * The following is a software around for the Neptune hardware's 67796f157acbSml * interrupt bugs; The Neptune hardware may generate spurious interrupts when 67806f157acbSml * an interrupr handler is removed. 67816f157acbSml */ 67826f157acbSml #define NXGE_PCI_PORT_LOGIC_OFFSET 0x98 67836f157acbSml #define NXGE_PIM_RESET (1ULL << 29) 67846f157acbSml #define NXGE_GLU_RESET (1ULL << 30) 67856f157acbSml #define NXGE_NIU_RESET (1ULL << 31) 67866f157acbSml #define NXGE_PCI_RESET_ALL (NXGE_PIM_RESET | \ 67876f157acbSml NXGE_GLU_RESET | \ 67886f157acbSml NXGE_NIU_RESET) 67896f157acbSml 67906f157acbSml #define NXGE_WAIT_QUITE_TIME 200000 67916f157acbSml #define NXGE_WAIT_QUITE_RETRY 40 67926f157acbSml #define NXGE_PCI_RESET_WAIT 1000000 /* one second */ 67936f157acbSml 67946f157acbSml static void 67956f157acbSml nxge_niu_peu_reset(p_nxge_t nxgep) 67966f157acbSml { 67976f157acbSml uint32_t rvalue; 67986f157acbSml p_nxge_hw_list_t hw_p; 67996f157acbSml p_nxge_t fnxgep; 68006f157acbSml int i, j; 68016f157acbSml 68026f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, "==> nxge_niu_peu_reset")); 68036f157acbSml if ((hw_p = nxgep->nxge_hw_p) == NULL) { 68046f157acbSml NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 68056f157acbSml "==> nxge_niu_peu_reset: NULL hardware pointer")); 68066f157acbSml return; 68076f157acbSml } 68086f157acbSml 68096f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 68106f157acbSml "==> nxge_niu_peu_reset: flags 0x%x link timer id %d timer id %d", 68116f157acbSml hw_p->flags, nxgep->nxge_link_poll_timerid, 68126f157acbSml nxgep->nxge_timerid)); 68136f157acbSml 68146f157acbSml MUTEX_ENTER(&hw_p->nxge_cfg_lock); 68156f157acbSml /* 68166f157acbSml * Make sure other instances from the same hardware 68176f157acbSml * stop sending PIO and in quiescent state. 68186f157acbSml */ 68196f157acbSml for (i = 0; i < NXGE_MAX_PORTS; i++) { 68206f157acbSml fnxgep = hw_p->nxge_p[i]; 68216f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 68226f157acbSml "==> nxge_niu_peu_reset: checking entry %d " 68236f157acbSml "nxgep $%p", i, fnxgep)); 68246f157acbSml #ifdef NXGE_DEBUG 68256f157acbSml if (fnxgep) { 68266f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 68276f157acbSml "==> nxge_niu_peu_reset: entry %d (function %d) " 68286f157acbSml "link timer id %d hw timer id %d", 68296f157acbSml i, fnxgep->function_num, 68306f157acbSml fnxgep->nxge_link_poll_timerid, 68316f157acbSml fnxgep->nxge_timerid)); 68326f157acbSml } 68336f157acbSml #endif 68346f157acbSml if (fnxgep && fnxgep != nxgep && 68356f157acbSml (fnxgep->nxge_timerid || fnxgep->nxge_link_poll_timerid)) { 68366f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 68376f157acbSml "==> nxge_niu_peu_reset: checking $%p " 68386f157acbSml "(function %d) timer ids", 68396f157acbSml fnxgep, fnxgep->function_num)); 68406f157acbSml for (j = 0; j < NXGE_WAIT_QUITE_RETRY; j++) { 68416f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 68426f157acbSml "==> nxge_niu_peu_reset: waiting")); 68436f157acbSml NXGE_DELAY(NXGE_WAIT_QUITE_TIME); 68446f157acbSml if (!fnxgep->nxge_timerid && 68456f157acbSml !fnxgep->nxge_link_poll_timerid) { 68466f157acbSml break; 68476f157acbSml } 68486f157acbSml } 68496f157acbSml NXGE_DELAY(NXGE_WAIT_QUITE_TIME); 68506f157acbSml if (fnxgep->nxge_timerid || 68516f157acbSml fnxgep->nxge_link_poll_timerid) { 68526f157acbSml MUTEX_EXIT(&hw_p->nxge_cfg_lock); 68536f157acbSml NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 68546f157acbSml "<== nxge_niu_peu_reset: cannot reset " 68556f157acbSml "hardware (devices are still in use)")); 68566f157acbSml return; 68576f157acbSml } 68586f157acbSml } 68596f157acbSml } 68606f157acbSml 68616f157acbSml if ((hw_p->flags & COMMON_RESET_NIU_PCI) != COMMON_RESET_NIU_PCI) { 68626f157acbSml hw_p->flags |= COMMON_RESET_NIU_PCI; 68636f157acbSml rvalue = pci_config_get32(nxgep->dev_regs->nxge_pciregh, 68646f157acbSml NXGE_PCI_PORT_LOGIC_OFFSET); 68656f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 68666f157acbSml "nxge_niu_peu_reset: read offset 0x%x (%d) " 68676f157acbSml "(data 0x%x)", 68686f157acbSml NXGE_PCI_PORT_LOGIC_OFFSET, 68696f157acbSml NXGE_PCI_PORT_LOGIC_OFFSET, 68706f157acbSml rvalue)); 68716f157acbSml 68726f157acbSml rvalue |= NXGE_PCI_RESET_ALL; 68736f157acbSml pci_config_put32(nxgep->dev_regs->nxge_pciregh, 68746f157acbSml NXGE_PCI_PORT_LOGIC_OFFSET, rvalue); 68756f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 68766f157acbSml "nxge_niu_peu_reset: RESETTING NIU: write NIU reset 0x%x", 68776f157acbSml rvalue)); 68786f157acbSml 68796f157acbSml NXGE_DELAY(NXGE_PCI_RESET_WAIT); 68806f157acbSml } 68816f157acbSml 68826f157acbSml MUTEX_EXIT(&hw_p->nxge_cfg_lock); 68836f157acbSml NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_niu_peu_reset")); 68846f157acbSml } 6885d6d3405fSml 6886d6d3405fSml static void 6887d6d3405fSml nxge_set_pci_replay_timeout(p_nxge_t nxgep) 6888d6d3405fSml { 6889d6d3405fSml p_dev_regs_t dev_regs; 6890d6d3405fSml uint32_t value; 6891d6d3405fSml 6892d6d3405fSml NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_set_pci_replay_timeout")); 6893d6d3405fSml 6894d6d3405fSml if (!nxge_set_replay_timer) { 6895d6d3405fSml NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6896d6d3405fSml "==> nxge_set_pci_replay_timeout: will not change " 6897d6d3405fSml "the timeout")); 6898d6d3405fSml return; 6899d6d3405fSml } 6900d6d3405fSml 6901d6d3405fSml dev_regs = nxgep->dev_regs; 6902d6d3405fSml NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6903d6d3405fSml "==> nxge_set_pci_replay_timeout: dev_regs 0x%p pcireg 0x%p", 6904d6d3405fSml dev_regs, dev_regs->nxge_pciregh)); 6905d6d3405fSml 6906d6d3405fSml if (dev_regs == NULL || (dev_regs->nxge_pciregh == NULL)) { 6907f720bc57Syc NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6908d6d3405fSml "==> nxge_set_pci_replay_timeout: NULL dev_regs $%p or " 6909d6d3405fSml "no PCI handle", 6910d6d3405fSml dev_regs)); 6911d6d3405fSml return; 6912d6d3405fSml } 6913d6d3405fSml value = (pci_config_get32(dev_regs->nxge_pciregh, 6914d6d3405fSml PCI_REPLAY_TIMEOUT_CFG_OFFSET) | 6915d6d3405fSml (nxge_replay_timeout << PCI_REPLAY_TIMEOUT_SHIFT)); 6916d6d3405fSml 6917d6d3405fSml NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6918d6d3405fSml "nxge_set_pci_replay_timeout: replay timeout value before set 0x%x " 6919d6d3405fSml "(timeout value to set 0x%x at offset 0x%x) value 0x%x", 6920d6d3405fSml pci_config_get32(dev_regs->nxge_pciregh, 6921d6d3405fSml PCI_REPLAY_TIMEOUT_CFG_OFFSET), nxge_replay_timeout, 6922d6d3405fSml PCI_REPLAY_TIMEOUT_CFG_OFFSET, value)); 6923d6d3405fSml 6924d6d3405fSml pci_config_put32(dev_regs->nxge_pciregh, PCI_REPLAY_TIMEOUT_CFG_OFFSET, 6925d6d3405fSml value); 6926d6d3405fSml 6927d6d3405fSml NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6928d6d3405fSml "nxge_set_pci_replay_timeout: replay timeout value after set 0x%x", 6929d6d3405fSml pci_config_get32(dev_regs->nxge_pciregh, 6930d6d3405fSml PCI_REPLAY_TIMEOUT_CFG_OFFSET))); 6931d6d3405fSml 6932d6d3405fSml NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_set_pci_replay_timeout")); 6933d6d3405fSml } 6934*19397407SSherry Moore 6935*19397407SSherry Moore /* 6936*19397407SSherry Moore * quiesce(9E) entry point. 6937*19397407SSherry Moore * 6938*19397407SSherry Moore * This function is called when the system is single-threaded at high 6939*19397407SSherry Moore * PIL with preemption disabled. Therefore, this function must not be 6940*19397407SSherry Moore * blocked. 6941*19397407SSherry Moore * 6942*19397407SSherry Moore * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 6943*19397407SSherry Moore * DDI_FAILURE indicates an error condition and should almost never happen. 6944*19397407SSherry Moore */ 6945*19397407SSherry Moore static int 6946*19397407SSherry Moore nxge_quiesce(dev_info_t *dip) 6947*19397407SSherry Moore { 6948*19397407SSherry Moore int instance = ddi_get_instance(dip); 6949*19397407SSherry Moore p_nxge_t nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance); 6950*19397407SSherry Moore 6951*19397407SSherry Moore if (nxgep == NULL) 6952*19397407SSherry Moore return (DDI_FAILURE); 6953*19397407SSherry Moore 6954*19397407SSherry Moore /* Turn off debugging */ 6955*19397407SSherry Moore nxge_debug_level = NO_DEBUG; 6956*19397407SSherry Moore nxgep->nxge_debug_level = NO_DEBUG; 6957*19397407SSherry Moore npi_debug_level = NO_DEBUG; 6958*19397407SSherry Moore 6959*19397407SSherry Moore /* 6960*19397407SSherry Moore * Stop link monitor only when linkchkmod is interrupt based 6961*19397407SSherry Moore */ 6962*19397407SSherry Moore if (nxgep->mac.linkchkmode == LINKCHK_INTR) { 6963*19397407SSherry Moore (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 6964*19397407SSherry Moore } 6965*19397407SSherry Moore 6966*19397407SSherry Moore (void) nxge_intr_hw_disable(nxgep); 6967*19397407SSherry Moore 6968*19397407SSherry Moore /* 6969*19397407SSherry Moore * Reset the receive MAC side. 6970*19397407SSherry Moore */ 6971*19397407SSherry Moore (void) nxge_rx_mac_disable(nxgep); 6972*19397407SSherry Moore 6973*19397407SSherry Moore /* Disable and soft reset the IPP */ 6974*19397407SSherry Moore if (!isLDOMguest(nxgep)) 6975*19397407SSherry Moore (void) nxge_ipp_disable(nxgep); 6976*19397407SSherry Moore 6977*19397407SSherry Moore /* 6978*19397407SSherry Moore * Reset the transmit/receive DMA side. 6979*19397407SSherry Moore */ 6980*19397407SSherry Moore (void) nxge_txdma_hw_mode(nxgep, NXGE_DMA_STOP); 6981*19397407SSherry Moore (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_STOP); 6982*19397407SSherry Moore 6983*19397407SSherry Moore /* 6984*19397407SSherry Moore * Reset the transmit MAC side. 6985*19397407SSherry Moore */ 6986*19397407SSherry Moore (void) nxge_tx_mac_disable(nxgep); 6987*19397407SSherry Moore 6988*19397407SSherry Moore return (DDI_SUCCESS); 6989*19397407SSherry Moore } 6990