144961713Sgirish /*
244961713Sgirish * CDDL HEADER START
344961713Sgirish *
444961713Sgirish * The contents of this file are subject to the terms of the
544961713Sgirish * Common Development and Distribution License (the "License").
644961713Sgirish * You may not use this file except in compliance with the License.
744961713Sgirish *
844961713Sgirish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
944961713Sgirish * or http://www.opensolaris.org/os/licensing.
1044961713Sgirish * See the License for the specific language governing permissions
1144961713Sgirish * and limitations under the License.
1244961713Sgirish *
1344961713Sgirish * When distributing Covered Code, include this CDDL HEADER in each
1444961713Sgirish * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1544961713Sgirish * If applicable, add the following below this CDDL HEADER, with the
1644961713Sgirish * fields enclosed by brackets "[]" replaced with your own identifying
1744961713Sgirish * information: Portions Copyright [yyyy] [name of copyright owner]
1844961713Sgirish *
1944961713Sgirish * CDDL HEADER END
2044961713Sgirish */
2144961713Sgirish /*
22a3c5bd6dSspeer * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
2344961713Sgirish * Use is subject to license terms.
2444961713Sgirish */
2544961713Sgirish
2644961713Sgirish #include <npi_fflp.h>
2744961713Sgirish #include <nxge_defs.h>
2844961713Sgirish #include <nxge_fflp.h>
2944961713Sgirish #include <nxge_flow.h>
3044961713Sgirish #include <nxge_impl.h>
3144961713Sgirish #include <nxge_common.h>
3244961713Sgirish
3344961713Sgirish /*
3444961713Sgirish * Globals: tunable parameters (/etc/system or adb)
3544961713Sgirish *
3644961713Sgirish */
37a3c5bd6dSspeer int nxge_tcam_class_enable = 0;
38a3c5bd6dSspeer int nxge_tcam_lookup_enable = 0;
39a3c5bd6dSspeer int nxge_flow_dist_enable = NXGE_CLASS_FLOW_USE_DST_PORT |
40a3c5bd6dSspeer NXGE_CLASS_FLOW_USE_SRC_PORT | NXGE_CLASS_FLOW_USE_IPDST |
41a3c5bd6dSspeer NXGE_CLASS_FLOW_USE_IPSRC | NXGE_CLASS_FLOW_USE_PROTO |
42a3c5bd6dSspeer NXGE_CLASS_FLOW_USE_PORTNUM;
4344961713Sgirish
4444961713Sgirish /*
4544961713Sgirish * Bit mapped
4644961713Sgirish * 0x80000000: Drop
4744961713Sgirish * 0x0000: NO TCAM Lookup Needed
4844961713Sgirish * 0x0001: TCAM Lookup Needed with Dest Addr (IPv6)
4944961713Sgirish * 0x0003: TCAM Lookup Needed with SRC Addr (IPv6)
5044961713Sgirish * 0x0010: use MAC Port
5144961713Sgirish * 0x0020: use L2DA
5244961713Sgirish * 0x0040: use VLAN
5344961713Sgirish * 0x0080: use proto
5444961713Sgirish * 0x0100: use IP src addr
5544961713Sgirish * 0x0200: use IP dest addr
5644961713Sgirish * 0x0400: use Src Port
5744961713Sgirish * 0x0800: use Dest Port
5844961713Sgirish * 0x0fff: enable all options for IPv6 (with src addr)
5944961713Sgirish * 0x0ffd: enable all options for IPv6 (with dest addr)
6044961713Sgirish * 0x0fff: enable all options for IPv4
6144961713Sgirish * 0x0ffd: enable all options for IPv4
6244961713Sgirish *
6344961713Sgirish */
6444961713Sgirish
6544961713Sgirish /*
6644961713Sgirish * the default is to distribute as function of:
6744961713Sgirish * protocol
6844961713Sgirish * ip src address
6944961713Sgirish * ip dest address
7044961713Sgirish * src port
7144961713Sgirish * dest port
7244961713Sgirish *
7344961713Sgirish * 0x0f80
7444961713Sgirish *
7544961713Sgirish */
7644961713Sgirish
77a3c5bd6dSspeer int nxge_tcp4_class = NXGE_CLASS_FLOW_USE_DST_PORT |
78a3c5bd6dSspeer NXGE_CLASS_FLOW_USE_SRC_PORT | NXGE_CLASS_FLOW_USE_IPDST |
79a3c5bd6dSspeer NXGE_CLASS_FLOW_USE_IPSRC | NXGE_CLASS_FLOW_USE_PROTO |
80a3c5bd6dSspeer NXGE_CLASS_FLOW_USE_PORTNUM;
81a3c5bd6dSspeer
82a3c5bd6dSspeer int nxge_udp4_class = NXGE_CLASS_FLOW_USE_DST_PORT |
83a3c5bd6dSspeer NXGE_CLASS_FLOW_USE_SRC_PORT | NXGE_CLASS_FLOW_USE_IPDST |
84a3c5bd6dSspeer NXGE_CLASS_FLOW_USE_IPSRC | NXGE_CLASS_FLOW_USE_PROTO |
85a3c5bd6dSspeer NXGE_CLASS_FLOW_USE_PORTNUM;
86a3c5bd6dSspeer
87a3c5bd6dSspeer int nxge_ah4_class = NXGE_CLASS_FLOW_USE_DST_PORT |
88a3c5bd6dSspeer NXGE_CLASS_FLOW_USE_SRC_PORT | NXGE_CLASS_FLOW_USE_IPDST |
89a3c5bd6dSspeer NXGE_CLASS_FLOW_USE_IPSRC | NXGE_CLASS_FLOW_USE_PROTO |
90a3c5bd6dSspeer NXGE_CLASS_FLOW_USE_PORTNUM;
91a3c5bd6dSspeer int nxge_sctp4_class = NXGE_CLASS_FLOW_USE_DST_PORT |
9244961713Sgirish NXGE_CLASS_FLOW_USE_SRC_PORT | NXGE_CLASS_FLOW_USE_IPDST |
9344961713Sgirish NXGE_CLASS_FLOW_USE_IPSRC | NXGE_CLASS_FLOW_USE_PROTO |
9444961713Sgirish NXGE_CLASS_FLOW_USE_PORTNUM;
9544961713Sgirish
96a3c5bd6dSspeer int nxge_tcp6_class = NXGE_CLASS_FLOW_USE_DST_PORT |
9744961713Sgirish NXGE_CLASS_FLOW_USE_SRC_PORT | NXGE_CLASS_FLOW_USE_IPDST |
9844961713Sgirish NXGE_CLASS_FLOW_USE_IPSRC | NXGE_CLASS_FLOW_USE_PROTO |
9944961713Sgirish NXGE_CLASS_FLOW_USE_PORTNUM;
10044961713Sgirish
101a3c5bd6dSspeer int nxge_udp6_class = NXGE_CLASS_FLOW_USE_DST_PORT |
102a3c5bd6dSspeer NXGE_CLASS_FLOW_USE_SRC_PORT | NXGE_CLASS_FLOW_USE_IPDST |
103a3c5bd6dSspeer NXGE_CLASS_FLOW_USE_IPSRC | NXGE_CLASS_FLOW_USE_PROTO |
104a3c5bd6dSspeer NXGE_CLASS_FLOW_USE_PORTNUM;
105a3c5bd6dSspeer
106a3c5bd6dSspeer int nxge_ah6_class = NXGE_CLASS_FLOW_USE_DST_PORT |
107a3c5bd6dSspeer NXGE_CLASS_FLOW_USE_SRC_PORT | NXGE_CLASS_FLOW_USE_IPDST |
108a3c5bd6dSspeer NXGE_CLASS_FLOW_USE_IPSRC | NXGE_CLASS_FLOW_USE_PROTO |
109a3c5bd6dSspeer NXGE_CLASS_FLOW_USE_PORTNUM;
110a3c5bd6dSspeer
111a3c5bd6dSspeer int nxge_sctp6_class = NXGE_CLASS_FLOW_USE_DST_PORT |
112a3c5bd6dSspeer NXGE_CLASS_FLOW_USE_SRC_PORT | NXGE_CLASS_FLOW_USE_IPDST |
113a3c5bd6dSspeer NXGE_CLASS_FLOW_USE_IPSRC | NXGE_CLASS_FLOW_USE_PROTO |
114a3c5bd6dSspeer NXGE_CLASS_FLOW_USE_PORTNUM;
115a3c5bd6dSspeer
116a3c5bd6dSspeer uint32_t nxge_fflp_init_h1 = 0xffffffff;
117a3c5bd6dSspeer uint32_t nxge_fflp_init_h2 = 0xffff;
118a3c5bd6dSspeer
119a3c5bd6dSspeer uint64_t class_quick_config_distribute[NXGE_CLASS_CONFIG_PARAMS] = {
120a3c5bd6dSspeer 0xffffffffULL, /* h1_init */
121a3c5bd6dSspeer 0xffffULL, /* h2_init */
122a3c5bd6dSspeer 0x0, /* cfg_ether_usr1 */
123a3c5bd6dSspeer 0x0, /* cfg_ether_usr2 */
124a3c5bd6dSspeer 0x0, /* cfg_ip_usr4 */
125a3c5bd6dSspeer 0x0, /* cfg_ip_usr5 */
126a3c5bd6dSspeer 0x0, /* cfg_ip_usr6 */
127a3c5bd6dSspeer 0x0, /* cfg_ip_usr7 */
128a3c5bd6dSspeer 0x0, /* opt_ip_usr4 */
129a3c5bd6dSspeer 0x0, /* opt_ip_usr5 */
130a3c5bd6dSspeer 0x0, /* opt_ip_usr6 */
131a3c5bd6dSspeer 0x0, /* opt_ip_usr7 */
13244961713Sgirish NXGE_CLASS_FLOW_GEN_SERVER, /* opt_ipv4_tcp */
13344961713Sgirish NXGE_CLASS_FLOW_GEN_SERVER, /* opt_ipv4_udp */
13444961713Sgirish NXGE_CLASS_FLOW_GEN_SERVER, /* opt_ipv4_ah */
13544961713Sgirish NXGE_CLASS_FLOW_GEN_SERVER, /* opt_ipv4_sctp */
13644961713Sgirish NXGE_CLASS_FLOW_GEN_SERVER, /* opt_ipv6_tcp */
13744961713Sgirish NXGE_CLASS_FLOW_GEN_SERVER, /* opt_ipv6_udp */
13844961713Sgirish NXGE_CLASS_FLOW_GEN_SERVER, /* opt_ipv6_ah */
13944961713Sgirish NXGE_CLASS_FLOW_GEN_SERVER /* opt_ipv6_sctp */
14044961713Sgirish };
14144961713Sgirish
142a3c5bd6dSspeer uint64_t class_quick_config_web_server[NXGE_CLASS_CONFIG_PARAMS] = {
143a3c5bd6dSspeer 0xffffffffULL, /* h1_init */
144a3c5bd6dSspeer 0xffffULL, /* h2_init */
145a3c5bd6dSspeer 0x0, /* cfg_ether_usr1 */
146a3c5bd6dSspeer 0x0, /* cfg_ether_usr2 */
147a3c5bd6dSspeer 0x0, /* cfg_ip_usr4 */
148a3c5bd6dSspeer 0x0, /* cfg_ip_usr5 */
149a3c5bd6dSspeer 0x0, /* cfg_ip_usr6 */
150a3c5bd6dSspeer 0x0, /* cfg_ip_usr7 */
151a3c5bd6dSspeer 0x0, /* opt_ip_usr4 */
152a3c5bd6dSspeer 0x0, /* opt_ip_usr5 */
153a3c5bd6dSspeer 0x0, /* opt_ip_usr6 */
154a3c5bd6dSspeer 0x0, /* opt_ip_usr7 */
15544961713Sgirish NXGE_CLASS_FLOW_WEB_SERVER, /* opt_ipv4_tcp */
15644961713Sgirish NXGE_CLASS_FLOW_GEN_SERVER, /* opt_ipv4_udp */
15744961713Sgirish NXGE_CLASS_FLOW_GEN_SERVER, /* opt_ipv4_ah */
15844961713Sgirish NXGE_CLASS_FLOW_GEN_SERVER, /* opt_ipv4_sctp */
15944961713Sgirish NXGE_CLASS_FLOW_GEN_SERVER, /* opt_ipv6_tcp */
16044961713Sgirish NXGE_CLASS_FLOW_GEN_SERVER, /* opt_ipv6_udp */
16144961713Sgirish NXGE_CLASS_FLOW_GEN_SERVER, /* opt_ipv6_ah */
16244961713Sgirish NXGE_CLASS_FLOW_GEN_SERVER /* opt_ipv6_sctp */
16344961713Sgirish };
16444961713Sgirish
16544961713Sgirish nxge_status_t
nxge_classify_init(p_nxge_t nxgep)16644961713Sgirish nxge_classify_init(p_nxge_t nxgep)
16744961713Sgirish {
168a3c5bd6dSspeer nxge_status_t status = NXGE_OK;
16944961713Sgirish
17044961713Sgirish status = nxge_classify_init_sw(nxgep);
17144961713Sgirish if (status != NXGE_OK)
17244961713Sgirish return (status);
17344961713Sgirish status = nxge_set_hw_classify_config(nxgep);
17444961713Sgirish if (status != NXGE_OK)
17544961713Sgirish return (status);
17644961713Sgirish
17744961713Sgirish status = nxge_classify_init_hw(nxgep);
17844961713Sgirish if (status != NXGE_OK)
17944961713Sgirish return (status);
18044961713Sgirish
18144961713Sgirish return (NXGE_OK);
18244961713Sgirish }
18344961713Sgirish
18414ea4bb7Ssd nxge_status_t
nxge_classify_uninit(p_nxge_t nxgep)18514ea4bb7Ssd nxge_classify_uninit(p_nxge_t nxgep)
18614ea4bb7Ssd {
187a3c5bd6dSspeer nxge_status_t status = NXGE_OK;
18814ea4bb7Ssd
18914ea4bb7Ssd status = nxge_classify_exit_sw(nxgep);
19014ea4bb7Ssd if (status != NXGE_OK) {
19114ea4bb7Ssd return (status);
19214ea4bb7Ssd }
19314ea4bb7Ssd return (NXGE_OK);
19414ea4bb7Ssd }
19514ea4bb7Ssd
1960a8e077aSspeer /* ARGSUSED */
19744961713Sgirish uint64_t
nxge_classify_get_cfg_value(p_nxge_t nxgep,uint8_t cfg_type,uint8_t cfg_param)198a3c5bd6dSspeer nxge_classify_get_cfg_value(p_nxge_t nxgep, uint8_t cfg_type, uint8_t cfg_param)
19944961713Sgirish {
20044961713Sgirish uint64_t cfg_value;
201a3c5bd6dSspeer
20244961713Sgirish if (cfg_param >= NXGE_CLASS_CONFIG_PARAMS)
20344961713Sgirish return (-1);
20444961713Sgirish switch (cfg_type) {
205a3c5bd6dSspeer case CFG_L3_WEB:
206a3c5bd6dSspeer cfg_value = class_quick_config_web_server[cfg_param];
207a3c5bd6dSspeer break;
208a3c5bd6dSspeer case CFG_L3_DISTRIBUTE:
209a3c5bd6dSspeer default:
210a3c5bd6dSspeer cfg_value = class_quick_config_distribute[cfg_param];
211a3c5bd6dSspeer break;
21244961713Sgirish }
21344961713Sgirish return (cfg_value);
21444961713Sgirish }
21544961713Sgirish
21644961713Sgirish nxge_status_t
nxge_set_hw_classify_config(p_nxge_t nxgep)21744961713Sgirish nxge_set_hw_classify_config(p_nxge_t nxgep)
21844961713Sgirish {
219a3c5bd6dSspeer p_nxge_dma_pt_cfg_t p_all_cfgp;
220a3c5bd6dSspeer p_nxge_hw_pt_cfg_t p_cfgp;
22144961713Sgirish
22244961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_get_hw_classify_config"));
22344961713Sgirish
22444961713Sgirish /* Get mac rdc table info from HW/Prom/.conf etc ...... */
22544961713Sgirish /* for now, get it from dma configs */
22644961713Sgirish p_all_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
22744961713Sgirish p_cfgp = (p_nxge_hw_pt_cfg_t)&p_all_cfgp->hw_config;
22844961713Sgirish
22944961713Sgirish /*
23044961713Sgirish * classify_init needs to call first.
23144961713Sgirish */
23244961713Sgirish nxgep->class_config.mac_rdcgrp = p_cfgp->def_mac_rxdma_grpid;
23344961713Sgirish nxgep->class_config.mcast_rdcgrp = p_cfgp->def_mac_rxdma_grpid;
23444961713Sgirish NXGE_DEBUG_MSG((nxgep, OBP_CTL, "<== nxge_get_hw_classify_config"));
23544961713Sgirish
23644961713Sgirish return (NXGE_OK);
23744961713Sgirish }
238