1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _NPI_TXDMA_H 27 #define _NPI_TXDMA_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <npi.h> 36 #include <nxge_txdma_hw.h> 37 38 #define DMA_LOG_PAGE_FN_VALIDATE(cn, pn, fn, status) \ 39 { \ 40 status = NPI_SUCCESS; \ 41 if (!TXDMA_CHANNEL_VALID(channel)) { \ 42 status = (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(cn)); \ 43 } else if (!TXDMA_PAGE_VALID(pn)) { \ 44 status = (NPI_FAILURE | NPI_TXDMA_PAGE_INVALID(pn)); \ 45 } else if (!TXDMA_FUNC_VALID(fn)) { \ 46 status = (NPI_FAILURE | NPI_TXDMA_FUNC_INVALID(fn)); \ 47 } \ 48 } 49 50 #define DMA_LOG_PAGE_VALIDATE(cn, pn, status) \ 51 { \ 52 status = NPI_SUCCESS; \ 53 if (!TXDMA_CHANNEL_VALID(channel)) { \ 54 status = (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(cn)); \ 55 } else if (!TXDMA_PAGE_VALID(pn)) { \ 56 status = (NPI_FAILURE | NPI_TXDMA_PAGE_INVALID(pn)); \ 57 } \ 58 } 59 60 typedef enum _txdma_cs_cntl_e { 61 TXDMA_INIT_RESET = 0x1, 62 TXDMA_INIT_START = 0x2, 63 TXDMA_START = 0x3, 64 TXDMA_RESET = 0x4, 65 TXDMA_STOP = 0x5, 66 TXDMA_RESUME = 0x6, 67 TXDMA_CLEAR_MMK = 0x7, 68 TXDMA_MBOX_ENABLE = 0x8 69 } txdma_cs_cntl_t; 70 71 typedef enum _txdma_log_cfg_e { 72 TXDMA_LOG_PAGE_MASK = 0x01, 73 TXDMA_LOG_PAGE_VALUE = 0x02, 74 TXDMA_LOG_PAGE_RELOC = 0x04, 75 TXDMA_LOG_PAGE_VALID = 0x08, 76 TXDMA_LOG_PAGE_ALL = (TXDMA_LOG_PAGE_MASK | TXDMA_LOG_PAGE_VALUE | 77 TXDMA_LOG_PAGE_RELOC | TXDMA_LOG_PAGE_VALID) 78 } txdma_log_cfg_t; 79 80 typedef enum _txdma_ent_msk_cfg_e { 81 CFG_TXDMA_PKT_PRT_MASK = TX_ENT_MSK_PKT_PRT_ERR_MASK, 82 CFG_TXDMA_CONF_PART_MASK = TX_ENT_MSK_CONF_PART_ERR_MASK, 83 CFG_TXDMA_NACK_PKT_RD_MASK = TX_ENT_MSK_NACK_PKT_RD_MASK, 84 CFG_TXDMA_NACK_PREF_MASK = TX_ENT_MSK_NACK_PREF_MASK, 85 CFG_TXDMA_PREF_BUF_ECC_ERR_MASK = TX_ENT_MSK_PREF_BUF_ECC_ERR_MASK, 86 CFG_TXDMA_TX_RING_OFLOW_MASK = TX_ENT_MSK_TX_RING_OFLOW_MASK, 87 CFG_TXDMA_PKT_SIZE_ERR_MASK = TX_ENT_MSK_PKT_SIZE_ERR_MASK, 88 CFG_TXDMA_MBOX_ERR_MASK = TX_ENT_MSK_MBOX_ERR_MASK, 89 CFG_TXDMA_MK_MASK = TX_ENT_MSK_MK_MASK, 90 CFG_TXDMA_MASK_ALL = (TX_ENT_MSK_PKT_PRT_ERR_MASK | 91 TX_ENT_MSK_CONF_PART_ERR_MASK | 92 TX_ENT_MSK_NACK_PKT_RD_MASK | 93 TX_ENT_MSK_NACK_PREF_MASK | 94 TX_ENT_MSK_PREF_BUF_ECC_ERR_MASK | 95 TX_ENT_MSK_TX_RING_OFLOW_MASK | 96 TX_ENT_MSK_PKT_SIZE_ERR_MASK | 97 TX_ENT_MSK_MBOX_ERR_MASK | 98 TX_ENT_MSK_MK_MASK) 99 } txdma_ent_msk_cfg_t; 100 101 102 typedef struct _txdma_ring_errlog { 103 tx_rng_err_logl_t logl; 104 tx_rng_err_logh_t logh; 105 } txdma_ring_errlog_t, *p_txdma_ring_errlog_t; 106 107 /* 108 * Register offset (0x200 bytes for each channel) for logical pages registers. 109 */ 110 #define NXGE_TXLOG_OFFSET(x, channel) (x + TX_LOG_DMA_OFFSET(channel)) 111 112 /* 113 * Register offset (0x200 bytes for each channel) for transmit ring registers. 114 * (Ring configuration, kick register, event mask, control and status, 115 * mailbox, prefetch, ring errors). 116 */ 117 #define NXGE_TXDMA_OFFSET(x, v, channel) (x + \ 118 (!v ? DMC_OFFSET(channel) : TDMC_PIOVADDR_OFFSET(channel))) 119 /* 120 * Register offset (0x8 bytes for each port) for transmit mapping registers. 121 */ 122 #define NXGE_TXDMA_MAP_OFFSET(x, port) (x + TX_DMA_MAP_PORT_OFFSET(port)) 123 124 /* 125 * Register offset (0x10 bytes for each channel) for transmit DRR and ring 126 * usage registers. 127 */ 128 #define NXGE_TXDMA_DRR_OFFSET(x, channel) (x + \ 129 TXDMA_DRR_RNG_USE_OFFSET(channel)) 130 131 /* 132 * PIO macros to read and write the transmit registers. 133 */ 134 #define TX_LOG_REG_READ64(handle, reg, channel, val_p) \ 135 NXGE_REG_RD64(handle, NXGE_TXLOG_OFFSET(reg, channel), val_p) 136 137 #define TX_LOG_REG_WRITE64(handle, reg, channel, data) \ 138 NXGE_REG_WR64(handle, NXGE_TXLOG_OFFSET(reg, channel), data) 139 140 #define TXDMA_REG_READ64(handle, reg, channel, val_p) \ 141 NXGE_REG_RD64(handle, \ 142 (NXGE_TXDMA_OFFSET(reg, handle.is_vraddr, channel)), val_p) 143 144 #define TXDMA_REG_WRITE64(handle, reg, channel, data) \ 145 NXGE_REG_WR64(handle, \ 146 NXGE_TXDMA_OFFSET(reg, handle.is_vraddr, channel), data) 147 148 #define TX_DRR_RNGUSE_REG_READ64(handle, reg, channel, val_p) \ 149 NXGE_REG_RD64(handle, (NXGE_TXDMA_DRR_OFFSET(reg, channel)), val_p) 150 151 #define TX_DRR_RNGUSE_REG_WRITE64(handle, reg, channel, data) \ 152 NXGE_REG_WR64(handle, NXGE_TXDMA_DRR_OFFSET(reg, channel), data) 153 154 /* 155 * Transmit Descriptor Definitions. 156 */ 157 #define TXDMA_DESC_SIZE (sizeof (tx_desc_t)) 158 159 #define NPI_TXDMA_GATHER_INDEX(index) \ 160 ((index <= TX_MAX_GATHER_POINTERS)) ? NPI_SUCCESS : \ 161 (NPI_TXDMA_GATHER_INVALID) 162 163 /* 164 * Transmit NPI error codes 165 */ 166 #define TXDMA_ER_ST (TXDMA_BLK_ID << NPI_BLOCK_ID_SHIFT) 167 #define TXDMA_ID_SHIFT(n) (n << NPI_PORT_CHAN_SHIFT) 168 169 #define TXDMA_HW_STOP_FAILED (NPI_BK_HW_ER_START | 0x1) 170 #define TXDMA_HW_RESUME_FAILED (NPI_BK_HW_ER_START | 0x2) 171 172 #define TXDMA_GATHER_INVALID (NPI_BK_ERROR_START | 0x1) 173 #define TXDMA_XFER_LEN_INVALID (NPI_BK_ERROR_START | 0x2) 174 175 #define NPI_TXDMA_OPCODE_INVALID(n) (TXDMA_ID_SHIFT(n) | \ 176 TXDMA_ER_ST | OPCODE_INVALID) 177 178 #define NPI_TXDMA_FUNC_INVALID(n) (TXDMA_ID_SHIFT(n) | \ 179 TXDMA_ER_ST | PORT_INVALID) 180 #define NPI_TXDMA_CHANNEL_INVALID(n) (TXDMA_ID_SHIFT(n) | \ 181 TXDMA_ER_ST | CHANNEL_INVALID) 182 183 #define NPI_TXDMA_PAGE_INVALID(n) (TXDMA_ID_SHIFT(n) | \ 184 TXDMA_ER_ST | LOGICAL_PAGE_INVALID) 185 186 #define NPI_TXDMA_REGISTER_INVALID (TXDMA_ER_ST | REGISTER_INVALID) 187 #define NPI_TXDMA_COUNTER_INVALID (TXDMA_ER_ST | COUNTER_INVALID) 188 #define NPI_TXDMA_CONFIG_INVALID (TXDMA_ER_ST | CONFIG_INVALID) 189 190 191 #define NPI_TXDMA_GATHER_INVALID (TXDMA_ER_ST | TXDMA_GATHER_INVALID) 192 #define NPI_TXDMA_XFER_LEN_INVALID (TXDMA_ER_ST | TXDMA_XFER_LEN_INVALID) 193 194 #define NPI_TXDMA_RESET_FAILED (TXDMA_ER_ST | RESET_FAILED) 195 #define NPI_TXDMA_STOP_FAILED (TXDMA_ER_ST | TXDMA_HW_STOP_FAILED) 196 #define NPI_TXDMA_RESUME_FAILED (TXDMA_ER_ST | TXDMA_HW_RESUME_FAILED) 197 198 /* 199 * Transmit DMA Channel NPI Prototypes. 200 */ 201 npi_status_t npi_txdma_mode32_set(npi_handle_t, boolean_t); 202 npi_status_t npi_txdma_log_page_set(npi_handle_t, uint8_t, 203 p_dma_log_page_t); 204 npi_status_t npi_txdma_log_page_get(npi_handle_t, uint8_t, 205 p_dma_log_page_t); 206 npi_status_t npi_txdma_log_page_handle_set(npi_handle_t, uint8_t, 207 p_log_page_hdl_t); 208 npi_status_t npi_txdma_log_page_config(npi_handle_t, io_op_t, 209 txdma_log_cfg_t, uint8_t, p_dma_log_page_t); 210 npi_status_t npi_txdma_log_page_vld_config(npi_handle_t, io_op_t, 211 uint8_t, p_log_page_vld_t); 212 npi_status_t npi_txdma_drr_weight_set(npi_handle_t, uint8_t, 213 uint32_t); 214 npi_status_t npi_txdma_channel_reset(npi_handle_t, uint8_t); 215 npi_status_t npi_txdma_channel_init_enable(npi_handle_t, 216 uint8_t); 217 npi_status_t npi_txdma_channel_enable(npi_handle_t, uint8_t); 218 npi_status_t npi_txdma_channel_disable(npi_handle_t, uint8_t); 219 npi_status_t npi_txdma_channel_resume(npi_handle_t, uint8_t); 220 npi_status_t npi_txdma_channel_mmk_clear(npi_handle_t, uint8_t); 221 npi_status_t npi_txdma_channel_mbox_enable(npi_handle_t, uint8_t); 222 npi_status_t npi_txdma_channel_control(npi_handle_t, 223 txdma_cs_cntl_t, uint8_t); 224 npi_status_t npi_txdma_control_status(npi_handle_t, io_op_t, 225 uint8_t, p_tx_cs_t); 226 227 npi_status_t npi_txdma_event_mask(npi_handle_t, io_op_t, 228 uint8_t, p_tx_dma_ent_msk_t); 229 npi_status_t npi_txdma_event_mask_config(npi_handle_t, io_op_t, 230 uint8_t, txdma_ent_msk_cfg_t *); 231 npi_status_t npi_txdma_event_mask_mk_out(npi_handle_t, uint8_t); 232 npi_status_t npi_txdma_event_mask_mk_in(npi_handle_t, uint8_t); 233 234 npi_status_t npi_txdma_ring_addr_set(npi_handle_t, uint8_t, 235 uint64_t, uint32_t); 236 npi_status_t npi_txdma_ring_config(npi_handle_t, io_op_t, 237 uint8_t, uint64_t *); 238 npi_status_t npi_txdma_mbox_config(npi_handle_t, io_op_t, 239 uint8_t, uint64_t *); 240 npi_status_t npi_txdma_desc_gather_set(npi_handle_t, 241 p_tx_desc_t, uint8_t, 242 boolean_t, uint8_t, 243 uint64_t, uint32_t); 244 245 npi_status_t npi_txdma_desc_gather_sop_set(npi_handle_t, 246 p_tx_desc_t, boolean_t, uint8_t); 247 248 npi_status_t npi_txdma_desc_gather_sop_set_1(npi_handle_t, 249 p_tx_desc_t, boolean_t, uint8_t, 250 uint32_t); 251 252 npi_status_t npi_txdma_desc_set_xfer_len(npi_handle_t, 253 p_tx_desc_t, uint32_t); 254 255 npi_status_t npi_txdma_desc_set_zero(npi_handle_t, uint16_t); 256 npi_status_t npi_txdma_desc_mem_get(npi_handle_t, uint16_t, 257 p_tx_desc_t); 258 npi_status_t npi_txdma_desc_kick_reg_set(npi_handle_t, uint8_t, 259 uint16_t, boolean_t); 260 npi_status_t npi_txdma_desc_kick_reg_get(npi_handle_t, uint8_t, 261 p_tx_ring_kick_t); 262 npi_status_t npi_txdma_ring_head_get(npi_handle_t, uint8_t, 263 p_tx_ring_hdl_t); 264 npi_status_t npi_txdma_channel_mbox_get(npi_handle_t, uint8_t, 265 p_txdma_mailbox_t); 266 npi_status_t npi_txdma_channel_pre_state_get(npi_handle_t, 267 uint8_t, p_tx_dma_pre_st_t); 268 npi_status_t npi_txdma_ring_error_get(npi_handle_t, 269 uint8_t, p_txdma_ring_errlog_t); 270 npi_status_t npi_txdma_inj_par_error_clear(npi_handle_t); 271 npi_status_t npi_txdma_inj_par_error_set(npi_handle_t, 272 uint32_t); 273 npi_status_t npi_txdma_inj_par_error_update(npi_handle_t, 274 uint32_t); 275 npi_status_t npi_txdma_inj_par_error_get(npi_handle_t, 276 uint32_t *); 277 npi_status_t npi_txdma_dbg_sel_set(npi_handle_t, uint8_t); 278 npi_status_t npi_txdma_training_vector_set(npi_handle_t, 279 uint32_t); 280 void npi_txdma_dump_desc_one(npi_handle_t, p_tx_desc_t, 281 int); 282 npi_status_t npi_txdma_dump_tdc_regs(npi_handle_t, uint8_t); 283 npi_status_t npi_txdma_dump_fzc_regs(npi_handle_t); 284 npi_status_t npi_txdma_inj_int_error_set(npi_handle_t, uint8_t, 285 p_tdmc_intr_dbg_t); 286 #ifdef __cplusplus 287 } 288 #endif 289 290 #endif /* _NPI_TXDMA_H */ 291