14496171girish/*
24496171girish * CDDL HEADER START
34496171girish *
44496171girish * The contents of this file are subject to the terms of the
54496171girish * Common Development and Distribution License (the "License").
64496171girish * You may not use this file except in compliance with the License.
74496171girish *
84496171girish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
94496171girish * or http://www.opensolaris.org/os/licensing.
104496171girish * See the License for the specific language governing permissions
114496171girish * and limitations under the License.
124496171girish *
134496171girish * When distributing Covered Code, include this CDDL HEADER in each
144496171girish * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
154496171girish * If applicable, add the following below this CDDL HEADER, with the
164496171girish * fields enclosed by brackets "[]" replaced with your own identifying
174496171girish * information: Portions Copyright [yyyy] [name of copyright owner]
184496171girish *
194496171girish * CDDL HEADER END
204496171girish */
214496171girish/*
22678453aspeer * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
234496171girish * Use is subject to license terms.
244496171girish */
254496171girish
264496171girish#ifndef _NPI_TXDMA_H
274496171girish#define	_NPI_TXDMA_H
284496171girish
294496171girish#pragma ident	"%Z%%M%	%I%	%E% SMI"
304496171girish
314496171girish#ifdef	__cplusplus
324496171girishextern "C" {
334496171girish#endif
344496171girish
354496171girish#include <npi.h>
364496171girish#include <nxge_txdma_hw.h>
374496171girish
384496171girish#define	DMA_LOG_PAGE_FN_VALIDATE(cn, pn, fn, status)	\
394496171girish{									\
404496171girish	status = NPI_SUCCESS;						\
414496171girish	if (!TXDMA_CHANNEL_VALID(channel)) {				\
424496171girish		status = (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(cn));	\
434496171girish	} else if (!TXDMA_PAGE_VALID(pn)) {			\
444496171girish		status =  (NPI_FAILURE | NPI_TXDMA_PAGE_INVALID(pn));	\
454496171girish	} else if (!TXDMA_FUNC_VALID(fn)) {			\
464496171girish		status =  (NPI_FAILURE | NPI_TXDMA_FUNC_INVALID(fn));	\
474496171girish	} \
484496171girish}
494496171girish
504496171girish#define	DMA_LOG_PAGE_VALIDATE(cn, pn, status)	\
514496171girish{									\
524496171girish	status = NPI_SUCCESS;						\
534496171girish	if (!TXDMA_CHANNEL_VALID(channel)) {				\
544496171girish		status = (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(cn));	\
554496171girish	} else if (!TXDMA_PAGE_VALID(pn)) {			\
564496171girish		status =  (NPI_FAILURE | NPI_TXDMA_PAGE_INVALID(pn));	\
574496171girish	} \
584496171girish}
594496171girish
604496171girishtypedef	enum _txdma_cs_cntl_e {
614496171girish	TXDMA_INIT_RESET	= 0x1,
624496171girish	TXDMA_INIT_START	= 0x2,
634496171girish	TXDMA_START		= 0x3,
644496171girish	TXDMA_RESET		= 0x4,
654496171girish	TXDMA_STOP		= 0x5,
664496171girish	TXDMA_RESUME		= 0x6,
674496171girish	TXDMA_CLEAR_MMK		= 0x7,
684496171girish	TXDMA_MBOX_ENABLE	= 0x8
694496171girish} txdma_cs_cntl_t;
704496171girish
714496171girishtypedef	enum _txdma_log_cfg_e {
724496171girish	TXDMA_LOG_PAGE_MASK	= 0x01,
734496171girish	TXDMA_LOG_PAGE_VALUE	= 0x02,
744496171girish	TXDMA_LOG_PAGE_RELOC	= 0x04,
754496171girish	TXDMA_LOG_PAGE_VALID	= 0x08,
764496171girish	TXDMA_LOG_PAGE_ALL	= (TXDMA_LOG_PAGE_MASK | TXDMA_LOG_PAGE_VALUE |
774496171girish				TXDMA_LOG_PAGE_RELOC | TXDMA_LOG_PAGE_VALID)
784496171girish} txdma_log_cfg_t;
794496171girish
804496171girishtypedef	enum _txdma_ent_msk_cfg_e {
814496171girish	CFG_TXDMA_PKT_PRT_MASK		= TX_ENT_MSK_PKT_PRT_ERR_MASK,
824496171girish	CFG_TXDMA_CONF_PART_MASK	= TX_ENT_MSK_CONF_PART_ERR_MASK,
834496171girish	CFG_TXDMA_NACK_PKT_RD_MASK	= TX_ENT_MSK_NACK_PKT_RD_MASK,
844496171girish	CFG_TXDMA_NACK_PREF_MASK	= TX_ENT_MSK_NACK_PREF_MASK,
854496171girish	CFG_TXDMA_PREF_BUF_ECC_ERR_MASK	= TX_ENT_MSK_PREF_BUF_ECC_ERR_MASK,
864496171girish	CFG_TXDMA_TX_RING_OFLOW_MASK	= TX_ENT_MSK_TX_RING_OFLOW_MASK,
874496171girish	CFG_TXDMA_PKT_SIZE_ERR_MASK	= TX_ENT_MSK_PKT_SIZE_ERR_MASK,
884496171girish	CFG_TXDMA_MBOX_ERR_MASK		= TX_ENT_MSK_MBOX_ERR_MASK,
894496171girish	CFG_TXDMA_MK_MASK		= TX_ENT_MSK_MK_MASK,
904496171girish	CFG_TXDMA_MASK_ALL		= (TX_ENT_MSK_PKT_PRT_ERR_MASK |
914496171girish					TX_ENT_MSK_CONF_PART_ERR_MASK |
924496171girish					TX_ENT_MSK_NACK_PKT_RD_MASK |
934496171girish					TX_ENT_MSK_NACK_PREF_MASK |
944496171girish					TX_ENT_MSK_PREF_BUF_ECC_ERR_MASK |
954496171girish					TX_ENT_MSK_TX_RING_OFLOW_MASK |
964496171girish					TX_ENT_MSK_PKT_SIZE_ERR_MASK |
974496171girish					TX_ENT_MSK_MBOX_ERR_MASK |
984496171girish					TX_ENT_MSK_MK_MASK)
994496171girish} txdma_ent_msk_cfg_t;
1004496171girish
1014496171girish
1024496171girishtypedef	struct _txdma_ring_errlog {
1034496171girish	tx_rng_err_logl_t	logl;
1044496171girish	tx_rng_err_logh_t	logh;
1054496171girish} txdma_ring_errlog_t, *p_txdma_ring_errlog_t;
1064496171girish
1074496171girish/*
1084496171girish * Register offset (0x200 bytes for each channel) for logical pages registers.
1094496171girish */
1104496171girish#define	NXGE_TXLOG_OFFSET(x, channel) (x + TX_LOG_DMA_OFFSET(channel))
1114496171girish
1124496171girish/*
1134496171girish * Register offset (0x200 bytes for each channel) for transmit ring registers.
1144496171girish * (Ring configuration, kick register, event mask, control and status,
1154496171girish *  mailbox, prefetch, ring errors).
1164496171girish */
1174496171girish#define	NXGE_TXDMA_OFFSET(x, v, channel) (x + \
1184496171girish		(!v ? DMC_OFFSET(channel) : TDMC_PIOVADDR_OFFSET(channel)))
1194496171girish/*
1204496171girish * Register offset (0x8 bytes for each port) for transmit mapping registers.
1214496171girish */
1224496171girish#define	NXGE_TXDMA_MAP_OFFSET(x, port) (x + TX_DMA_MAP_PORT_OFFSET(port))
1234496171girish
1244496171girish/*
1254496171girish * Register offset (0x10 bytes for each channel) for transmit DRR and ring
1264496171girish * usage registers.
1274496171girish */
1284496171girish#define	NXGE_TXDMA_DRR_OFFSET(x, channel) (x + \
1294496171girish			TXDMA_DRR_RNG_USE_OFFSET(channel))
1304496171girish
1314496171girish/*
1324496171girish * PIO macros to read and write the transmit registers.
1334496171girish */
1344496171girish#define	TX_LOG_REG_READ64(handle, reg, channel, val_p)	\
1354496171girish	NXGE_REG_RD64(handle, NXGE_TXLOG_OFFSET(reg, channel), val_p)
1364496171girish
1374496171girish#define	TX_LOG_REG_WRITE64(handle, reg, channel, data)	\
1384496171girish	NXGE_REG_WR64(handle, NXGE_TXLOG_OFFSET(reg, channel), data)
1394496171girish
1404496171girish/*
1414496171girish * Transmit Descriptor Definitions.
1424496171girish */
1434496171girish#define	TXDMA_DESC_SIZE			(sizeof (tx_desc_t))
1444496171girish
1454496171girish#define	NPI_TXDMA_GATHER_INDEX(index)	\
1464496171girish	((index <= TX_MAX_GATHER_POINTERS)) ? NPI_SUCCESS : \
1474496171girish				(NPI_TXDMA_GATHER_INVALID)
1484496171girish
1494496171girish/*
1504496171girish * Transmit NPI error codes
1514496171girish */
1524496171girish#define	TXDMA_ER_ST			(TXDMA_BLK_ID << NPI_BLOCK_ID_SHIFT)
1534496171girish#define	TXDMA_ID_SHIFT(n)		(n << NPI_PORT_CHAN_SHIFT)
1544496171girish
1554496171girish#define	TXDMA_HW_STOP_FAILED		(NPI_BK_HW_ER_START | 0x1)
1564496171girish#define	TXDMA_HW_RESUME_FAILED		(NPI_BK_HW_ER_START | 0x2)
1574496171girish
1584496171girish#define	TXDMA_GATHER_INVALID		(NPI_BK_ERROR_START | 0x1)
1594496171girish#define	TXDMA_XFER_LEN_INVALID		(NPI_BK_ERROR_START | 0x2)
1604496171girish
1614496171girish#define	NPI_TXDMA_OPCODE_INVALID(n)	(TXDMA_ID_SHIFT(n) |	\
1624496171girish					TXDMA_ER_ST | OPCODE_INVALID)
1634496171girish
1644496171girish#define	NPI_TXDMA_FUNC_INVALID(n)	(TXDMA_ID_SHIFT(n) |	\
1654496171girish					TXDMA_ER_ST | PORT_INVALID)
1664496171girish#define	NPI_TXDMA_CHANNEL_INVALID(n)	(TXDMA_ID_SHIFT(n) |	\
1674496171girish					TXDMA_ER_ST | CHANNEL_INVALID)
1684496171girish
1694496171girish#define	NPI_TXDMA_PAGE_INVALID(n)	(TXDMA_ID_SHIFT(n) |	\
1704496171girish					TXDMA_ER_ST | LOGICAL_PAGE_INVALID)
1714496171girish
1724496171girish#define	NPI_TXDMA_REGISTER_INVALID	(TXDMA_ER_ST | REGISTER_INVALID)
1734496171girish#define	NPI_TXDMA_COUNTER_INVALID	(TXDMA_ER_ST | COUNTER_INVALID)
1744496171girish#define	NPI_TXDMA_CONFIG_INVALID	(TXDMA_ER_ST | CONFIG_INVALID)
1754496171girish
1764496171girish
1774496171girish#define	NPI_TXDMA_GATHER_INVALID	(TXDMA_ER_ST | TXDMA_GATHER_INVALID)
1784496171girish#define	NPI_TXDMA_XFER_LEN_INVALID	(TXDMA_ER_ST | TXDMA_XFER_LEN_INVALID)
1794496171girish
1804496171girish#define	NPI_TXDMA_RESET_FAILED		(TXDMA_ER_ST | RESET_FAILED)
1814496171girish#define	NPI_TXDMA_STOP_FAILED		(TXDMA_ER_ST | TXDMA_HW_STOP_FAILED)
1824496171girish#define	NPI_TXDMA_RESUME_FAILED		(TXDMA_ER_ST | TXDMA_HW_RESUME_FAILED)
1834496171girish
1844496171girish/*
1854496171girish * Transmit DMA Channel NPI Prototypes.
1864496171girish */
1874496171girishnpi_status_t npi_txdma_mode32_set(npi_handle_t, boolean_t);
1884496171girishnpi_status_t npi_txdma_log_page_set(npi_handle_t, uint8_t,
1894496171girish		p_dma_log_page_t);
1904496171girishnpi_status_t npi_txdma_log_page_get(npi_handle_t, uint8_t,
1914496171girish		p_dma_log_page_t);
1924496171girishnpi_status_t npi_txdma_log_page_handle_set(npi_handle_t, uint8_t,
1934496171girish		p_log_page_hdl_t);
1944496171girishnpi_status_t npi_txdma_log_page_config(npi_handle_t, io_op_t,
1954496171girish		txdma_log_cfg_t, uint8_t, p_dma_log_page_t);
1964496171girishnpi_status_t npi_txdma_log_page_vld_config(npi_handle_t, io_op_t,
1974496171girish		uint8_t, p_log_page_vld_t);
1984496171girishnpi_status_t npi_txdma_drr_weight_set(npi_handle_t, uint8_t,
1994496171girish		uint32_t);
2004496171girishnpi_status_t npi_txdma_channel_reset(npi_handle_t, uint8_t);
2014496171girishnpi_status_t npi_txdma_channel_init_enable(npi_handle_t,
2024496171girish		uint8_t);
2034496171girishnpi_status_t npi_txdma_channel_enable(npi_handle_t, uint8_t);
2044496171girishnpi_status_t npi_txdma_channel_disable(npi_handle_t, uint8_t);
2054496171girishnpi_status_t npi_txdma_channel_resume(npi_handle_t, uint8_t);
2064496171girishnpi_status_t npi_txdma_channel_mmk_clear(npi_handle_t, uint8_t);
2074496171girishnpi_status_t npi_txdma_channel_mbox_enable(npi_handle_t, uint8_t);
2084496171girishnpi_status_t npi_txdma_channel_control(npi_handle_t,
2094496171girish		txdma_cs_cntl_t, uint8_t);
2104496171girishnpi_status_t npi_txdma_control_status(npi_handle_t, io_op_t,
2114496171girish		uint8_t, p_tx_cs_t);
2124496171girish
2134496171girishnpi_status_t npi_txdma_event_mask(npi_handle_t, io_op_t,
2144496171girish		uint8_t, p_tx_dma_ent_msk_t);
2154496171girishnpi_status_t npi_txdma_event_mask_config(npi_handle_t, io_op_t,
2164496171girish		uint8_t, txdma_ent_msk_cfg_t *);
2174496171girishnpi_status_t npi_txdma_event_mask_mk_out(npi_handle_t, uint8_t);
2184496171girishnpi_status_t npi_txdma_event_mask_mk_in(npi_handle_t, uint8_t);
2194496171girish
2204496171girishnpi_status_t npi_txdma_ring_addr_set(npi_handle_t, uint8_t,
2214496171girish		uint64_t, uint32_t);
2224496171girishnpi_status_t npi_txdma_ring_config(npi_handle_t, io_op_t,
2234496171girish		uint8_t, uint64_t *);
2244496171girishnpi_status_t npi_txdma_mbox_config(npi_handle_t, io_op_t,
2254496171girish		uint8_t, uint64_t *);
2264496171girishnpi_status_t npi_txdma_desc_gather_set(npi_handle_t,
2274496171girish		p_tx_desc_t, uint8_t,
2284496171girish		boolean_t, uint8_t,
2294496171girish		uint64_t, uint32_t);
2304496171girish
2314496171girishnpi_status_t npi_txdma_desc_gather_sop_set(npi_handle_t,
2324496171girish		p_tx_desc_t, boolean_t, uint8_t);
2334496171girish
2344496171girishnpi_status_t npi_txdma_desc_gather_sop_set_1(npi_handle_t,
2354496171girish		p_tx_desc_t, boolean_t, uint8_t,
2364496171girish		uint32_t);
2374496171girish
2384496171girishnpi_status_t npi_txdma_desc_set_xfer_len(npi_handle_t,
2394496171girish		p_tx_desc_t, uint32_t);
2404496171girish
2414496171girishnpi_status_t npi_txdma_desc_set_zero(npi_handle_t, uint16_t);
2424496171girishnpi_status_t npi_txdma_desc_mem_get(npi_handle_t, uint16_t,
2434496171girish		p_tx_desc_t);
2444496171girishnpi_status_t npi_txdma_desc_kick_reg_set(npi_handle_t, uint8_t,
2454496171girish		uint16_t, boolean_t);
2464496171girishnpi_status_t npi_txdma_desc_kick_reg_get(npi_handle_t, uint8_t,
2474496171girish		p_tx_ring_kick_t);
2484496171girishnpi_status_t npi_txdma_ring_head_get(npi_handle_t, uint8_t,
2494496171girish		p_tx_ring_hdl_t);
2504496171girishnpi_status_t npi_txdma_channel_mbox_get(npi_handle_t, uint8_t,
2514496171girish		p_txdma_mailbox_t);
2524496171girishnpi_status_t npi_txdma_channel_pre_state_get(npi_handle_t,
2534496171girish		uint8_t, p_tx_dma_pre_st_t);
2544496171girishnpi_status_t npi_txdma_ring_error_get(npi_handle_t,
2554496171girish		uint8_t, p_txdma_ring_errlog_t);
2564496171girishnpi_status_t npi_txdma_inj_par_error_clear(npi_handle_t);
2574496171girishnpi_status_t npi_txdma_inj_par_error_set(npi_handle_t,
2584496171girish		uint32_t);
2594496171girishnpi_status_t npi_txdma_inj_par_error_update(npi_handle_t,
2604496171girish		uint32_t);
2614496171girishnpi_status_t npi_txdma_inj_par_error_get(npi_handle_t,
2624496171girish		uint32_t *);
2634496171girishnpi_status_t npi_txdma_dbg_sel_set(npi_handle_t, uint8_t);
2644496171girishnpi_status_t npi_txdma_training_vector_set(npi_handle_t,
2654496171girish		uint32_t);
2664496171girishvoid npi_txdma_dump_desc_one(npi_handle_t, p_tx_desc_t,
2674496171girish	int);
2684496171girishnpi_status_t npi_txdma_dump_tdc_regs(npi_handle_t, uint8_t);
2694496171girishnpi_status_t npi_txdma_dump_fzc_regs(npi_handle_t);
2704496171girishnpi_status_t npi_txdma_inj_int_error_set(npi_handle_t, uint8_t,
2714496171girish	p_tdmc_intr_dbg_t);
2724496171girish#ifdef	__cplusplus
2734496171girish}
2744496171girish#endif
2754496171girish
2764496171girish#endif	/* _NPI_TXDMA_H */
277