1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21/*
22 * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
23 * Use is subject to license terms.
24 */
25
26#ifndef _NPI_TXDMA_H
27#define	_NPI_TXDMA_H
28
29#pragma ident	"%Z%%M%	%I%	%E% SMI"
30
31#ifdef	__cplusplus
32extern "C" {
33#endif
34
35#include <npi.h>
36#include <nxge_txdma_hw.h>
37
38#define	DMA_LOG_PAGE_FN_VALIDATE(cn, pn, fn, status)	\
39{									\
40	status = NPI_SUCCESS;						\
41	if (!TXDMA_CHANNEL_VALID(channel)) {				\
42		status = (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(cn));	\
43	} else if (!TXDMA_PAGE_VALID(pn)) {			\
44		status =  (NPI_FAILURE | NPI_TXDMA_PAGE_INVALID(pn));	\
45	} else if (!TXDMA_FUNC_VALID(fn)) {			\
46		status =  (NPI_FAILURE | NPI_TXDMA_FUNC_INVALID(fn));	\
47	} \
48}
49
50#define	DMA_LOG_PAGE_VALIDATE(cn, pn, status)	\
51{									\
52	status = NPI_SUCCESS;						\
53	if (!TXDMA_CHANNEL_VALID(channel)) {				\
54		status = (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(cn));	\
55	} else if (!TXDMA_PAGE_VALID(pn)) {			\
56		status =  (NPI_FAILURE | NPI_TXDMA_PAGE_INVALID(pn));	\
57	} \
58}
59
60typedef	enum _txdma_cs_cntl_e {
61	TXDMA_INIT_RESET	= 0x1,
62	TXDMA_INIT_START	= 0x2,
63	TXDMA_START		= 0x3,
64	TXDMA_RESET		= 0x4,
65	TXDMA_STOP		= 0x5,
66	TXDMA_RESUME		= 0x6,
67	TXDMA_CLEAR_MMK		= 0x7,
68	TXDMA_MBOX_ENABLE	= 0x8
69} txdma_cs_cntl_t;
70
71typedef	enum _txdma_log_cfg_e {
72	TXDMA_LOG_PAGE_MASK	= 0x01,
73	TXDMA_LOG_PAGE_VALUE	= 0x02,
74	TXDMA_LOG_PAGE_RELOC	= 0x04,
75	TXDMA_LOG_PAGE_VALID	= 0x08,
76	TXDMA_LOG_PAGE_ALL	= (TXDMA_LOG_PAGE_MASK | TXDMA_LOG_PAGE_VALUE |
77				TXDMA_LOG_PAGE_RELOC | TXDMA_LOG_PAGE_VALID)
78} txdma_log_cfg_t;
79
80typedef	enum _txdma_ent_msk_cfg_e {
81	CFG_TXDMA_PKT_PRT_MASK		= TX_ENT_MSK_PKT_PRT_ERR_MASK,
82	CFG_TXDMA_CONF_PART_MASK	= TX_ENT_MSK_CONF_PART_ERR_MASK,
83	CFG_TXDMA_NACK_PKT_RD_MASK	= TX_ENT_MSK_NACK_PKT_RD_MASK,
84	CFG_TXDMA_NACK_PREF_MASK	= TX_ENT_MSK_NACK_PREF_MASK,
85	CFG_TXDMA_PREF_BUF_ECC_ERR_MASK	= TX_ENT_MSK_PREF_BUF_ECC_ERR_MASK,
86	CFG_TXDMA_TX_RING_OFLOW_MASK	= TX_ENT_MSK_TX_RING_OFLOW_MASK,
87	CFG_TXDMA_PKT_SIZE_ERR_MASK	= TX_ENT_MSK_PKT_SIZE_ERR_MASK,
88	CFG_TXDMA_MBOX_ERR_MASK		= TX_ENT_MSK_MBOX_ERR_MASK,
89	CFG_TXDMA_MK_MASK		= TX_ENT_MSK_MK_MASK,
90	CFG_TXDMA_MASK_ALL		= (TX_ENT_MSK_PKT_PRT_ERR_MASK |
91					TX_ENT_MSK_CONF_PART_ERR_MASK |
92					TX_ENT_MSK_NACK_PKT_RD_MASK |
93					TX_ENT_MSK_NACK_PREF_MASK |
94					TX_ENT_MSK_PREF_BUF_ECC_ERR_MASK |
95					TX_ENT_MSK_TX_RING_OFLOW_MASK |
96					TX_ENT_MSK_PKT_SIZE_ERR_MASK |
97					TX_ENT_MSK_MBOX_ERR_MASK |
98					TX_ENT_MSK_MK_MASK)
99} txdma_ent_msk_cfg_t;
100
101
102typedef	struct _txdma_ring_errlog {
103	tx_rng_err_logl_t	logl;
104	tx_rng_err_logh_t	logh;
105} txdma_ring_errlog_t, *p_txdma_ring_errlog_t;
106
107/*
108 * Register offset (0x200 bytes for each channel) for logical pages registers.
109 */
110#define	NXGE_TXLOG_OFFSET(x, channel) (x + TX_LOG_DMA_OFFSET(channel))
111
112/*
113 * Register offset (0x200 bytes for each channel) for transmit ring registers.
114 * (Ring configuration, kick register, event mask, control and status,
115 *  mailbox, prefetch, ring errors).
116 */
117#define	NXGE_TXDMA_OFFSET(x, v, channel) (x + \
118		(!v ? DMC_OFFSET(channel) : TDMC_PIOVADDR_OFFSET(channel)))
119/*
120 * Register offset (0x8 bytes for each port) for transmit mapping registers.
121 */
122#define	NXGE_TXDMA_MAP_OFFSET(x, port) (x + TX_DMA_MAP_PORT_OFFSET(port))
123
124/*
125 * Register offset (0x10 bytes for each channel) for transmit DRR and ring
126 * usage registers.
127 */
128#define	NXGE_TXDMA_DRR_OFFSET(x, channel) (x + \
129			TXDMA_DRR_RNG_USE_OFFSET(channel))
130
131/*
132 * PIO macros to read and write the transmit registers.
133 */
134#define	TX_LOG_REG_READ64(handle, reg, channel, val_p)	\
135	NXGE_REG_RD64(handle, NXGE_TXLOG_OFFSET(reg, channel), val_p)
136
137#define	TX_LOG_REG_WRITE64(handle, reg, channel, data)	\
138	NXGE_REG_WR64(handle, NXGE_TXLOG_OFFSET(reg, channel), data)
139
140/*
141 * Transmit Descriptor Definitions.
142 */
143#define	TXDMA_DESC_SIZE			(sizeof (tx_desc_t))
144
145#define	NPI_TXDMA_GATHER_INDEX(index)	\
146	((index <= TX_MAX_GATHER_POINTERS)) ? NPI_SUCCESS : \
147				(NPI_TXDMA_GATHER_INVALID)
148
149/*
150 * Transmit NPI error codes
151 */
152#define	TXDMA_ER_ST			(TXDMA_BLK_ID << NPI_BLOCK_ID_SHIFT)
153#define	TXDMA_ID_SHIFT(n)		(n << NPI_PORT_CHAN_SHIFT)
154
155#define	TXDMA_HW_STOP_FAILED		(NPI_BK_HW_ER_START | 0x1)
156#define	TXDMA_HW_RESUME_FAILED		(NPI_BK_HW_ER_START | 0x2)
157
158#define	TXDMA_GATHER_INVALID		(NPI_BK_ERROR_START | 0x1)
159#define	TXDMA_XFER_LEN_INVALID		(NPI_BK_ERROR_START | 0x2)
160
161#define	NPI_TXDMA_OPCODE_INVALID(n)	(TXDMA_ID_SHIFT(n) |	\
162					TXDMA_ER_ST | OPCODE_INVALID)
163
164#define	NPI_TXDMA_FUNC_INVALID(n)	(TXDMA_ID_SHIFT(n) |	\
165					TXDMA_ER_ST | PORT_INVALID)
166#define	NPI_TXDMA_CHANNEL_INVALID(n)	(TXDMA_ID_SHIFT(n) |	\
167					TXDMA_ER_ST | CHANNEL_INVALID)
168
169#define	NPI_TXDMA_PAGE_INVALID(n)	(TXDMA_ID_SHIFT(n) |	\
170					TXDMA_ER_ST | LOGICAL_PAGE_INVALID)
171
172#define	NPI_TXDMA_REGISTER_INVALID	(TXDMA_ER_ST | REGISTER_INVALID)
173#define	NPI_TXDMA_COUNTER_INVALID	(TXDMA_ER_ST | COUNTER_INVALID)
174#define	NPI_TXDMA_CONFIG_INVALID	(TXDMA_ER_ST | CONFIG_INVALID)
175
176
177#define	NPI_TXDMA_GATHER_INVALID	(TXDMA_ER_ST | TXDMA_GATHER_INVALID)
178#define	NPI_TXDMA_XFER_LEN_INVALID	(TXDMA_ER_ST | TXDMA_XFER_LEN_INVALID)
179
180#define	NPI_TXDMA_RESET_FAILED		(TXDMA_ER_ST | RESET_FAILED)
181#define	NPI_TXDMA_STOP_FAILED		(TXDMA_ER_ST | TXDMA_HW_STOP_FAILED)
182#define	NPI_TXDMA_RESUME_FAILED		(TXDMA_ER_ST | TXDMA_HW_RESUME_FAILED)
183
184/*
185 * Transmit DMA Channel NPI Prototypes.
186 */
187npi_status_t npi_txdma_mode32_set(npi_handle_t, boolean_t);
188npi_status_t npi_txdma_log_page_set(npi_handle_t, uint8_t,
189		p_dma_log_page_t);
190npi_status_t npi_txdma_log_page_get(npi_handle_t, uint8_t,
191		p_dma_log_page_t);
192npi_status_t npi_txdma_log_page_handle_set(npi_handle_t, uint8_t,
193		p_log_page_hdl_t);
194npi_status_t npi_txdma_log_page_config(npi_handle_t, io_op_t,
195		txdma_log_cfg_t, uint8_t, p_dma_log_page_t);
196npi_status_t npi_txdma_log_page_vld_config(npi_handle_t, io_op_t,
197		uint8_t, p_log_page_vld_t);
198npi_status_t npi_txdma_drr_weight_set(npi_handle_t, uint8_t,
199		uint32_t);
200npi_status_t npi_txdma_channel_reset(npi_handle_t, uint8_t);
201npi_status_t npi_txdma_channel_init_enable(npi_handle_t,
202		uint8_t);
203npi_status_t npi_txdma_channel_enable(npi_handle_t, uint8_t);
204npi_status_t npi_txdma_channel_disable(npi_handle_t, uint8_t);
205npi_status_t npi_txdma_channel_resume(npi_handle_t, uint8_t);
206npi_status_t npi_txdma_channel_mmk_clear(npi_handle_t, uint8_t);
207npi_status_t npi_txdma_channel_mbox_enable(npi_handle_t, uint8_t);
208npi_status_t npi_txdma_channel_control(npi_handle_t,
209		txdma_cs_cntl_t, uint8_t);
210npi_status_t npi_txdma_control_status(npi_handle_t, io_op_t,
211		uint8_t, p_tx_cs_t);
212
213npi_status_t npi_txdma_event_mask(npi_handle_t, io_op_t,
214		uint8_t, p_tx_dma_ent_msk_t);
215npi_status_t npi_txdma_event_mask_config(npi_handle_t, io_op_t,
216		uint8_t, txdma_ent_msk_cfg_t *);
217npi_status_t npi_txdma_event_mask_mk_out(npi_handle_t, uint8_t);
218npi_status_t npi_txdma_event_mask_mk_in(npi_handle_t, uint8_t);
219
220npi_status_t npi_txdma_ring_addr_set(npi_handle_t, uint8_t,
221		uint64_t, uint32_t);
222npi_status_t npi_txdma_ring_config(npi_handle_t, io_op_t,
223		uint8_t, uint64_t *);
224npi_status_t npi_txdma_mbox_config(npi_handle_t, io_op_t,
225		uint8_t, uint64_t *);
226npi_status_t npi_txdma_desc_gather_set(npi_handle_t,
227		p_tx_desc_t, uint8_t,
228		boolean_t, uint8_t,
229		uint64_t, uint32_t);
230
231npi_status_t npi_txdma_desc_gather_sop_set(npi_handle_t,
232		p_tx_desc_t, boolean_t, uint8_t);
233
234npi_status_t npi_txdma_desc_gather_sop_set_1(npi_handle_t,
235		p_tx_desc_t, boolean_t, uint8_t,
236		uint32_t);
237
238npi_status_t npi_txdma_desc_set_xfer_len(npi_handle_t,
239		p_tx_desc_t, uint32_t);
240
241npi_status_t npi_txdma_desc_set_zero(npi_handle_t, uint16_t);
242npi_status_t npi_txdma_desc_mem_get(npi_handle_t, uint16_t,
243		p_tx_desc_t);
244npi_status_t npi_txdma_desc_kick_reg_set(npi_handle_t, uint8_t,
245		uint16_t, boolean_t);
246npi_status_t npi_txdma_desc_kick_reg_get(npi_handle_t, uint8_t,
247		p_tx_ring_kick_t);
248npi_status_t npi_txdma_ring_head_get(npi_handle_t, uint8_t,
249		p_tx_ring_hdl_t);
250npi_status_t npi_txdma_channel_mbox_get(npi_handle_t, uint8_t,
251		p_txdma_mailbox_t);
252npi_status_t npi_txdma_channel_pre_state_get(npi_handle_t,
253		uint8_t, p_tx_dma_pre_st_t);
254npi_status_t npi_txdma_ring_error_get(npi_handle_t,
255		uint8_t, p_txdma_ring_errlog_t);
256npi_status_t npi_txdma_inj_par_error_clear(npi_handle_t);
257npi_status_t npi_txdma_inj_par_error_set(npi_handle_t,
258		uint32_t);
259npi_status_t npi_txdma_inj_par_error_update(npi_handle_t,
260		uint32_t);
261npi_status_t npi_txdma_inj_par_error_get(npi_handle_t,
262		uint32_t *);
263npi_status_t npi_txdma_dbg_sel_set(npi_handle_t, uint8_t);
264npi_status_t npi_txdma_training_vector_set(npi_handle_t,
265		uint32_t);
266void npi_txdma_dump_desc_one(npi_handle_t, p_tx_desc_t,
267	int);
268npi_status_t npi_txdma_dump_tdc_regs(npi_handle_t, uint8_t);
269npi_status_t npi_txdma_dump_fzc_regs(npi_handle_t);
270npi_status_t npi_txdma_inj_int_error_set(npi_handle_t, uint8_t,
271	p_tdmc_intr_dbg_t);
272#ifdef	__cplusplus
273}
274#endif
275
276#endif	/* _NPI_TXDMA_H */
277