144961713Sgirish /* 244961713Sgirish * CDDL HEADER START 344961713Sgirish * 444961713Sgirish * The contents of this file are subject to the terms of the 544961713Sgirish * Common Development and Distribution License (the "License"). 644961713Sgirish * You may not use this file except in compliance with the License. 744961713Sgirish * 844961713Sgirish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 944961713Sgirish * or http://www.opensolaris.org/os/licensing. 1044961713Sgirish * See the License for the specific language governing permissions 1144961713Sgirish * and limitations under the License. 1244961713Sgirish * 1344961713Sgirish * When distributing Covered Code, include this CDDL HEADER in each 1444961713Sgirish * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1544961713Sgirish * If applicable, add the following below this CDDL HEADER, with the 1644961713Sgirish * fields enclosed by brackets "[]" replaced with your own identifying 1744961713Sgirish * information: Portions Copyright [yyyy] [name of copyright owner] 1844961713Sgirish * 1944961713Sgirish * CDDL HEADER END 2044961713Sgirish */ 2144961713Sgirish /* 22*678453a8Sspeer * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 2344961713Sgirish * Use is subject to license terms. 2444961713Sgirish */ 2544961713Sgirish 2644961713Sgirish #pragma ident "%Z%%M% %I% %E% SMI" 2744961713Sgirish 28a3c5bd6dSspeer #include <npi_txdma.h> 29*678453a8Sspeer #include <npi_tx_rd64.h> 30*678453a8Sspeer #include <npi_tx_wr64.h> 3144961713Sgirish 3244961713Sgirish #define TXDMA_WAIT_LOOP 10000 3344961713Sgirish #define TXDMA_WAIT_MSEC 5 3444961713Sgirish 3544961713Sgirish static npi_status_t npi_txdma_control_reset_wait(npi_handle_t handle, 36a3c5bd6dSspeer uint8_t channel); 3744961713Sgirish static npi_status_t npi_txdma_control_stop_wait(npi_handle_t handle, 38a3c5bd6dSspeer uint8_t channel); 3944961713Sgirish static npi_status_t npi_txdma_control_resume_wait(npi_handle_t handle, 40a3c5bd6dSspeer uint8_t channel); 4144961713Sgirish 4244961713Sgirish uint64_t tdc_dmc_offset[] = { 4344961713Sgirish TX_RNG_CFIG_REG, 4444961713Sgirish TX_RING_HDL_REG, 4544961713Sgirish TX_RING_KICK_REG, 4644961713Sgirish TX_ENT_MSK_REG, 4744961713Sgirish TX_CS_REG, 4844961713Sgirish TXDMA_MBH_REG, 4944961713Sgirish TXDMA_MBL_REG, 5044961713Sgirish TX_DMA_PRE_ST_REG, 5144961713Sgirish TX_RNG_ERR_LOGH_REG, 5244961713Sgirish TX_RNG_ERR_LOGL_REG, 5344961713Sgirish TDMC_INTR_DBG_REG, 5444961713Sgirish TX_CS_DBG_REG 5544961713Sgirish }; 5644961713Sgirish 5744961713Sgirish const char *tdc_dmc_name[] = { 5844961713Sgirish "TX_RNG_CFIG_REG", 5944961713Sgirish "TX_RING_HDL_REG", 6044961713Sgirish "TX_RING_KICK_REG", 6144961713Sgirish "TX_ENT_MSK_REG", 6244961713Sgirish "TX_CS_REG", 6344961713Sgirish "TXDMA_MBH_REG", 6444961713Sgirish "TXDMA_MBL_REG", 6544961713Sgirish "TX_DMA_PRE_ST_REG", 6644961713Sgirish "TX_RNG_ERR_LOGH_REG", 6744961713Sgirish "TX_RNG_ERR_LOGL_REG", 6844961713Sgirish "TDMC_INTR_DBG_REG", 6944961713Sgirish "TX_CS_DBG_REG" 7044961713Sgirish }; 7144961713Sgirish 7244961713Sgirish uint64_t tdc_fzc_offset [] = { 7344961713Sgirish TX_LOG_PAGE_VLD_REG, 7444961713Sgirish TX_LOG_PAGE_MASK1_REG, 7544961713Sgirish TX_LOG_PAGE_VAL1_REG, 7644961713Sgirish TX_LOG_PAGE_MASK2_REG, 7744961713Sgirish TX_LOG_PAGE_VAL2_REG, 7844961713Sgirish TX_LOG_PAGE_RELO1_REG, 7944961713Sgirish TX_LOG_PAGE_RELO2_REG, 8044961713Sgirish TX_LOG_PAGE_HDL_REG 8144961713Sgirish }; 8244961713Sgirish 8344961713Sgirish const char *tdc_fzc_name [] = { 8444961713Sgirish "TX_LOG_PAGE_VLD_REG", 8544961713Sgirish "TX_LOG_PAGE_MASK1_REG", 8644961713Sgirish "TX_LOG_PAGE_VAL1_REG", 8744961713Sgirish "TX_LOG_PAGE_MASK2_REG", 8844961713Sgirish "TX_LOG_PAGE_VAL2_REG", 8944961713Sgirish "TX_LOG_PAGE_RELO1_REG", 9044961713Sgirish "TX_LOG_PAGE_RELO2_REG", 9144961713Sgirish "TX_LOG_PAGE_HDL_REG" 9244961713Sgirish }; 9344961713Sgirish 9444961713Sgirish uint64_t tx_fzc_offset[] = { 9544961713Sgirish TX_ADDR_MD_REG, 9644961713Sgirish TDMC_INJ_PAR_ERR_REG, 9744961713Sgirish TDMC_DBG_SEL_REG, 98*678453a8Sspeer TDMC_TRAINING_REG, 99*678453a8Sspeer TXC_PORT_DMA_ENABLE_REG, 100*678453a8Sspeer TXC_DMA_MAX_BURST_REG 10144961713Sgirish }; 10244961713Sgirish 10344961713Sgirish const char *tx_fzc_name[] = { 10444961713Sgirish "TX_ADDR_MD_REG", 10544961713Sgirish "TDMC_INJ_PAR_ERR_REG", 10644961713Sgirish "TDMC_DBG_SEL_REG", 107*678453a8Sspeer "TDMC_TRAINING_REG", 108*678453a8Sspeer "TXC_PORT_DMA_ENABLE_REG", 109*678453a8Sspeer "TXC_DMA_MAX_BURST_REG" 11044961713Sgirish }; 11144961713Sgirish 112a3c5bd6dSspeer #define NUM_TDC_DMC_REGS (sizeof (tdc_dmc_offset) / sizeof (uint64_t)) 113a3c5bd6dSspeer #define NUM_TX_FZC_REGS (sizeof (tx_fzc_offset) / sizeof (uint64_t)) 114a3c5bd6dSspeer 11544961713Sgirish /* 11644961713Sgirish * npi_txdma_dump_tdc_regs 11744961713Sgirish * Dumps the contents of tdc csrs and fzc registers 11844961713Sgirish * 11944961713Sgirish * Input: 12044961713Sgirish * tdc: TX DMA number 12144961713Sgirish * 12244961713Sgirish * return: 12344961713Sgirish * NPI_SUCCESS 12444961713Sgirish * NPI_FAILURE 12544961713Sgirish * NPI_TXDMA_CHANNEL_INVALID 12644961713Sgirish * 12744961713Sgirish */ 12844961713Sgirish npi_status_t 12944961713Sgirish npi_txdma_dump_tdc_regs(npi_handle_t handle, uint8_t tdc) 13044961713Sgirish { 13144961713Sgirish 13244961713Sgirish uint64_t value, offset; 13344961713Sgirish int num_regs, i; 13444961713Sgirish 135a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(tdc)); 13644961713Sgirish if (!TXDMA_CHANNEL_VALID(tdc)) { 13744961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 13844961713Sgirish "npi_txdma_dump_tdc_regs" 13944961713Sgirish " Invalid TDC number %d \n", 14044961713Sgirish tdc)); 14144961713Sgirish 14244961713Sgirish return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(tdc)); 14344961713Sgirish } 14444961713Sgirish 14544961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 14644961713Sgirish "\nTXDMA DMC Register Dump for Channel %d\n", 14744961713Sgirish tdc)); 14844961713Sgirish 149a3c5bd6dSspeer num_regs = NUM_TDC_DMC_REGS; 15044961713Sgirish for (i = 0; i < num_regs; i++) { 15144961713Sgirish TXDMA_REG_READ64(handle, tdc_dmc_offset[i], tdc, &value); 15244961713Sgirish offset = NXGE_TXDMA_OFFSET(tdc_dmc_offset[i], handle.is_vraddr, 15344961713Sgirish tdc); 15444961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, "0x%08llx " 15544961713Sgirish "%s\t 0x%016llx \n", 15644961713Sgirish offset, tdc_dmc_name[i], 15744961713Sgirish value)); 15844961713Sgirish } 15944961713Sgirish 16044961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 16144961713Sgirish "\n TXDMA Register Dump for Channel %d done\n", tdc)); 16244961713Sgirish 16344961713Sgirish return (NPI_SUCCESS); 16444961713Sgirish } 16544961713Sgirish 16644961713Sgirish /* 16744961713Sgirish * npi_txdma_dump_fzc_regs 16844961713Sgirish * Dumps the contents of tdc csrs and fzc registers 16944961713Sgirish * 17044961713Sgirish * Input: 17144961713Sgirish * tdc: TX DMA number 17244961713Sgirish * 17344961713Sgirish * return: 17444961713Sgirish * NPI_SUCCESS 17544961713Sgirish * NPI_FAILURE 17644961713Sgirish * NPI_TXDMA_CHANNEL_INVALID 17744961713Sgirish * 17844961713Sgirish */ 17944961713Sgirish npi_status_t 18044961713Sgirish npi_txdma_dump_fzc_regs(npi_handle_t handle) 18144961713Sgirish { 18244961713Sgirish 18344961713Sgirish uint64_t value; 18444961713Sgirish int num_regs, i; 18544961713Sgirish 18644961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 18744961713Sgirish "\nFZC_DMC Common Register Dump\n")); 18844961713Sgirish 189a3c5bd6dSspeer num_regs = NUM_TX_FZC_REGS; 19044961713Sgirish for (i = 0; i < num_regs; i++) { 191adfcba55Sjoycey #if defined(__i386) 192adfcba55Sjoycey NXGE_REG_RD64(handle, (uint32_t)tx_fzc_offset[i], &value); 193adfcba55Sjoycey #else 19444961713Sgirish NXGE_REG_RD64(handle, tx_fzc_offset[i], &value); 195adfcba55Sjoycey #endif 19644961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, "0x%08llx " 19744961713Sgirish "%s\t 0x%08llx \n", 19844961713Sgirish tx_fzc_offset[i], 19944961713Sgirish tx_fzc_name[i], value)); 20044961713Sgirish } 20144961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 20244961713Sgirish "\n TXDMA FZC_DMC Register Dump Done \n")); 20344961713Sgirish 20444961713Sgirish return (NPI_SUCCESS); 20544961713Sgirish } 20644961713Sgirish 20744961713Sgirish npi_status_t 20844961713Sgirish npi_txdma_tdc_regs_zero(npi_handle_t handle, uint8_t tdc) 20944961713Sgirish { 21044961713Sgirish uint64_t value; 21144961713Sgirish int num_regs, i; 21244961713Sgirish 213a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(tdc)); 21444961713Sgirish if (!TXDMA_CHANNEL_VALID(tdc)) { 21544961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 21644961713Sgirish "npi_txdma_tdc_regs_zero" 21744961713Sgirish " InvaliInvalid TDC number %d \n", 21844961713Sgirish tdc)); 21944961713Sgirish return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(tdc)); 22044961713Sgirish } 22144961713Sgirish 22244961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 22344961713Sgirish "\nTXDMA DMC Register (zero) for Channel %d\n", 22444961713Sgirish tdc)); 22544961713Sgirish 226a3c5bd6dSspeer num_regs = NUM_TDC_DMC_REGS; 22744961713Sgirish value = 0; 22844961713Sgirish for (i = 0; i < num_regs; i++) { 229adfcba55Sjoycey TXDMA_REG_WRITE64(handle, tdc_dmc_offset[i], tdc, value); 23044961713Sgirish } 23144961713Sgirish 23244961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 23344961713Sgirish "\nTXDMA FZC_DMC Register clear for Channel %d\n", 23444961713Sgirish tdc)); 23544961713Sgirish 23644961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 23744961713Sgirish "\n TXDMA Register Clear to 0s for Channel %d done\n", tdc)); 23844961713Sgirish 23944961713Sgirish return (NPI_SUCCESS); 24044961713Sgirish } 24144961713Sgirish 24244961713Sgirish /* 24344961713Sgirish * npi_txdma_address_mode32_set(): 24444961713Sgirish * This function is called to only support 32 bit addressing. 24544961713Sgirish * 24644961713Sgirish * Parameters: 24744961713Sgirish * handle - NPI handle 24844961713Sgirish * mode_enable - B_TRUE (enable 32 bit mode) 24944961713Sgirish * B_FALSE (disable 32 bit mode) 25044961713Sgirish * 25144961713Sgirish * Return: 25244961713Sgirish * NPI_SUCCESS - If set is complete successfully. 25344961713Sgirish * 25444961713Sgirish * Error: 25544961713Sgirish * NONE 25644961713Sgirish */ 25744961713Sgirish npi_status_t 25844961713Sgirish npi_txdma_mode32_set(npi_handle_t handle, boolean_t mode_enable) 25944961713Sgirish { 26044961713Sgirish tx_addr_md_t mode32; 26144961713Sgirish 26244961713Sgirish mode32.value = 0; 26344961713Sgirish if (mode_enable) { 26444961713Sgirish mode32.bits.ldw.mode32 = 1; 26544961713Sgirish } else { 26644961713Sgirish mode32.bits.ldw.mode32 = 0; 26744961713Sgirish } 26844961713Sgirish NXGE_REG_WR64(handle, TX_ADDR_MD_REG, mode32.value); 26944961713Sgirish 27044961713Sgirish return (NPI_SUCCESS); 27144961713Sgirish } 27244961713Sgirish 27344961713Sgirish /* 27444961713Sgirish * npi_txdma_log_page_set(): 27544961713Sgirish * This function is called to configure a logical page 27644961713Sgirish * (valid bit, mask, value, relocation). 27744961713Sgirish * 27844961713Sgirish * Parameters: 27944961713Sgirish * handle - NPI handle 28044961713Sgirish * cfgp - pointer to NPI defined data structure: 28144961713Sgirish * - page valid 28244961713Sgirish * - mask 28344961713Sgirish * - value 28444961713Sgirish * - relocation 28544961713Sgirish * channel - hardware TXDMA channel from 0 to 23. 28644961713Sgirish * 28744961713Sgirish * Return: 28844961713Sgirish * NPI_SUCCESS - If configurations are set successfully. 28944961713Sgirish * 29044961713Sgirish * Error: 29144961713Sgirish * NPI_FAILURE - 29244961713Sgirish * NPI_TXDMA_CHANNEL_INVALID - 29344961713Sgirish * NPI_TXDMA_FUNC_INVALID - 29444961713Sgirish * NPI_TXDMA_PAGE_INVALID - 29544961713Sgirish */ 29644961713Sgirish npi_status_t 29744961713Sgirish npi_txdma_log_page_set(npi_handle_t handle, uint8_t channel, 29844961713Sgirish p_dma_log_page_t cfgp) 29944961713Sgirish { 30044961713Sgirish log_page_vld_t vld; 30144961713Sgirish int status; 30244961713Sgirish uint64_t val; 30344961713Sgirish dma_log_page_t cfg; 30444961713Sgirish 30544961713Sgirish DMA_LOG_PAGE_FN_VALIDATE(channel, cfgp->page_num, cfgp->func_num, 30644961713Sgirish status); 30744961713Sgirish if (status) { 30844961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 30944961713Sgirish " npi_txdma_log_page_set" 31044961713Sgirish " npi_status <0x%x>", status)); 31144961713Sgirish return (status); 31244961713Sgirish } 31344961713Sgirish 31444961713Sgirish TX_LOG_REG_WRITE64(handle, TX_LOG_PAGE_VLD_REG, channel, 0); 31544961713Sgirish TX_LOG_REG_READ64(handle, TX_LOG_PAGE_VLD_REG, channel, &val); 31644961713Sgirish 31744961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_TDC_CTL, 31844961713Sgirish "\n==> npi_txdma_log_page_set: WRITE 0 and " 31944961713Sgirish " READ back 0x%llx\n ", val)); 32044961713Sgirish 32144961713Sgirish vld.value = 0; 32244961713Sgirish TX_LOG_REG_READ64(handle, TX_LOG_PAGE_VLD_REG, channel, &val); 32344961713Sgirish 32444961713Sgirish val &= 0x3; 32544961713Sgirish vld.value |= val; 32644961713Sgirish 32744961713Sgirish vld.value = 0; 32844961713Sgirish vld.bits.ldw.func = cfgp->func_num; 32944961713Sgirish 33044961713Sgirish if (!cfgp->page_num) { 33144961713Sgirish TX_LOG_REG_WRITE64(handle, TX_LOG_PAGE_MASK1_REG, 33244961713Sgirish channel, (cfgp->mask & DMA_LOG_PAGE_MASK_MASK)); 33344961713Sgirish TX_LOG_REG_WRITE64(handle, TX_LOG_PAGE_VAL1_REG, 33444961713Sgirish channel, (cfgp->value & DMA_LOG_PAGE_VALUE_MASK)); 33544961713Sgirish TX_LOG_REG_WRITE64(handle, TX_LOG_PAGE_RELO1_REG, 33644961713Sgirish channel, (cfgp->reloc & DMA_LOG_PAGE_RELO_MASK)); 33744961713Sgirish } else { 33844961713Sgirish TX_LOG_REG_WRITE64(handle, TX_LOG_PAGE_MASK2_REG, 33944961713Sgirish channel, (cfgp->mask & DMA_LOG_PAGE_MASK_MASK)); 34044961713Sgirish TX_LOG_REG_WRITE64(handle, TX_LOG_PAGE_VAL2_REG, 34144961713Sgirish channel, (cfgp->value & DMA_LOG_PAGE_VALUE_MASK)); 34244961713Sgirish TX_LOG_REG_WRITE64(handle, TX_LOG_PAGE_RELO2_REG, 34344961713Sgirish channel, (cfgp->reloc & DMA_LOG_PAGE_RELO_MASK)); 34444961713Sgirish } 34544961713Sgirish 34644961713Sgirish TX_LOG_REG_WRITE64(handle, TX_LOG_PAGE_VLD_REG, channel, 34744961713Sgirish vld.value | (cfgp->valid << cfgp->page_num)); 34844961713Sgirish 34944961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_REG_CTL, 35044961713Sgirish "\n==> npi_txdma_log_page_set: vld value " 35144961713Sgirish " 0x%llx function %d page_valid01 0x%x\n", 35244961713Sgirish vld.value, 35344961713Sgirish vld.bits.ldw.func, 35444961713Sgirish (cfgp->valid << cfgp->page_num))); 35544961713Sgirish 35644961713Sgirish 35744961713Sgirish cfg.page_num = 0; 35844961713Sgirish cfg.func_num = 0; 35944961713Sgirish (void) npi_txdma_log_page_get(handle, channel, &cfg); 36044961713Sgirish cfg.page_num = 1; 36144961713Sgirish (void) npi_txdma_log_page_get(handle, channel, &cfg); 36244961713Sgirish 36344961713Sgirish return (status); 36444961713Sgirish } 36544961713Sgirish 36644961713Sgirish /* 36744961713Sgirish * npi_txdma_log_page_get(): 36844961713Sgirish * This function is called to get a logical page 36944961713Sgirish * (valid bit, mask, value, relocation). 37044961713Sgirish * 37144961713Sgirish * Parameters: 37244961713Sgirish * handle - NPI handle 37344961713Sgirish * cfgp - Get the following values (NPI defined structure): 37444961713Sgirish * - page valid 37544961713Sgirish * - mask 37644961713Sgirish * - value 37744961713Sgirish * - relocation 37844961713Sgirish * channel - hardware TXDMA channel from 0 to 23. 37944961713Sgirish * 38044961713Sgirish * Return: 38144961713Sgirish * NPI_SUCCESS - If configurations are read successfully. 38244961713Sgirish * 38344961713Sgirish * Error: 38444961713Sgirish * NPI_FAILURE - 38544961713Sgirish * NPI_TXDMA_CHANNEL_INVALID - 38644961713Sgirish * NPI_TXDMA_FUNC_INVALID - 38744961713Sgirish * NPI_TXDMA_PAGE_INVALID - 38844961713Sgirish */ 38944961713Sgirish npi_status_t 39044961713Sgirish npi_txdma_log_page_get(npi_handle_t handle, uint8_t channel, 39144961713Sgirish p_dma_log_page_t cfgp) 39244961713Sgirish { 39344961713Sgirish log_page_vld_t vld; 39444961713Sgirish int status; 39544961713Sgirish uint64_t val; 39644961713Sgirish 39744961713Sgirish DMA_LOG_PAGE_VALIDATE(channel, cfgp->page_num, status); 39844961713Sgirish if (status) { 39944961713Sgirish NPI_ERROR_MSG((handle.function, NPI_REG_CTL, 40044961713Sgirish " npi_txdma_log_page_get" 40144961713Sgirish " npi_status <0x%x>", status)); 40244961713Sgirish return (status); 40344961713Sgirish } 40444961713Sgirish 40544961713Sgirish vld.value = 0; 40644961713Sgirish vld.bits.ldw.func = cfgp->func_num; 40744961713Sgirish TX_LOG_REG_READ64(handle, TX_LOG_PAGE_VLD_REG, channel, &val); 40844961713Sgirish 40944961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_TDC_CTL, 41044961713Sgirish "\n==> npi_txdma_log_page_get: read value " 41144961713Sgirish " function %d value 0x%llx\n", 41244961713Sgirish cfgp->func_num, val)); 41344961713Sgirish 41444961713Sgirish vld.value |= val; 41544961713Sgirish cfgp->func_num = vld.bits.ldw.func; 41644961713Sgirish 41744961713Sgirish if (!cfgp->page_num) { 41844961713Sgirish TX_LOG_REG_READ64(handle, TX_LOG_PAGE_MASK1_REG, channel, &val); 41944961713Sgirish cfgp->mask = val & DMA_LOG_PAGE_MASK_MASK; 42044961713Sgirish TX_LOG_REG_READ64(handle, TX_LOG_PAGE_VAL1_REG, channel, &val); 42144961713Sgirish cfgp->value = val & DMA_LOG_PAGE_VALUE_MASK; 42244961713Sgirish TX_LOG_REG_READ64(handle, TX_LOG_PAGE_RELO1_REG, channel, &val); 42344961713Sgirish cfgp->reloc = val & DMA_LOG_PAGE_RELO_MASK; 42444961713Sgirish cfgp->valid = vld.bits.ldw.page0; 42544961713Sgirish } else { 42644961713Sgirish TX_LOG_REG_READ64(handle, TX_LOG_PAGE_MASK2_REG, channel, &val); 42744961713Sgirish cfgp->mask = val & DMA_LOG_PAGE_MASK_MASK; 42844961713Sgirish TX_LOG_REG_READ64(handle, TX_LOG_PAGE_VAL2_REG, channel, &val); 42944961713Sgirish cfgp->value = val & DMA_LOG_PAGE_VALUE_MASK; 43044961713Sgirish TX_LOG_REG_READ64(handle, TX_LOG_PAGE_RELO2_REG, channel, &val); 43144961713Sgirish cfgp->reloc = val & DMA_LOG_PAGE_RELO_MASK; 43244961713Sgirish cfgp->valid = vld.bits.ldw.page1; 43344961713Sgirish } 43444961713Sgirish 43544961713Sgirish return (status); 43644961713Sgirish } 43744961713Sgirish 43844961713Sgirish /* 43944961713Sgirish * npi_txdma_log_page_handle_set(): 44044961713Sgirish * This function is called to program a page handle 44144961713Sgirish * (bits [63:44] of a 64-bit address to generate 44244961713Sgirish * a 64 bit address) 44344961713Sgirish * 44444961713Sgirish * Parameters: 44544961713Sgirish * handle - NPI handle 44644961713Sgirish * hdl_p - pointer to a logical page handle 44744961713Sgirish * hardware data structure (log_page_hdl_t). 44844961713Sgirish * channel - hardware TXDMA channel from 0 to 23. 44944961713Sgirish * 45044961713Sgirish * Return: 45144961713Sgirish * NPI_SUCCESS - If configurations are set successfully. 45244961713Sgirish * 45344961713Sgirish * Error: 45444961713Sgirish * NPI_FAILURE - 45544961713Sgirish * NPI_TXDMA_CHANNEL_INVALID - 45644961713Sgirish * NPI_TXDMA_FUNC_INVALID - 45744961713Sgirish * NPI_TXDMA_PAGE_INVALID - 45844961713Sgirish */ 45944961713Sgirish npi_status_t 46044961713Sgirish npi_txdma_log_page_handle_set(npi_handle_t handle, uint8_t channel, 46144961713Sgirish p_log_page_hdl_t hdl_p) 46244961713Sgirish { 46344961713Sgirish int status = NPI_SUCCESS; 46444961713Sgirish 465a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(channel)); 46644961713Sgirish if (!TXDMA_CHANNEL_VALID(channel)) { 46744961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 46844961713Sgirish " npi_txdma_log_page_handle_set" 46944961713Sgirish " Invalid Input: channel <0x%x>", 47044961713Sgirish channel)); 47144961713Sgirish return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel)); 47244961713Sgirish } 47344961713Sgirish 47444961713Sgirish TX_LOG_REG_WRITE64(handle, TX_LOG_PAGE_HDL_REG, 47544961713Sgirish channel, hdl_p->value); 47644961713Sgirish 47744961713Sgirish return (status); 47844961713Sgirish } 47944961713Sgirish 48044961713Sgirish /* 48144961713Sgirish * npi_txdma_log_page_config(): 48244961713Sgirish * This function is called to IO operations on 48344961713Sgirish * a logical page to set, get, clear 48444961713Sgirish * valid bit, mask, value, relocation). 48544961713Sgirish * 48644961713Sgirish * Parameters: 48744961713Sgirish * handle - NPI handle 48844961713Sgirish * op_mode - OP_GET, OP_SET, OP_CLEAR 48944961713Sgirish * type - NPI specific config type 49044961713Sgirish * TXDMA_LOG_PAGE_MASK 49144961713Sgirish * TXDMA_LOG_PAGE_VALUE 49244961713Sgirish * TXDMA_LOG_PAGE_RELOC 49344961713Sgirish * TXDMA_LOG_PAGE_VALID 49444961713Sgirish * TXDMA_LOG_PAGE_ALL 49544961713Sgirish * channel - hardware TXDMA channel from 0 to 23. 49644961713Sgirish * cfgp - pointer to the NPI config structure. 49744961713Sgirish * Return: 49844961713Sgirish * NPI_SUCCESS - If configurations are read successfully. 49944961713Sgirish * 50044961713Sgirish * Error: 50144961713Sgirish * NPI_FAILURE - 50244961713Sgirish * NPI_TXDMA_OPCODE_INVALID - 50344961713Sgirish * NPI_TXDMA_CHANNEL_INVALID - 50444961713Sgirish * NPI_TXDMA_FUNC_INVALID - 50544961713Sgirish * NPI_TXDMA_PAGE_INVALID - 50644961713Sgirish */ 50744961713Sgirish npi_status_t 50844961713Sgirish npi_txdma_log_page_config(npi_handle_t handle, io_op_t op_mode, 50944961713Sgirish txdma_log_cfg_t type, uint8_t channel, 51044961713Sgirish p_dma_log_page_t cfgp) 51144961713Sgirish { 51244961713Sgirish int status = NPI_SUCCESS; 51344961713Sgirish uint64_t val; 51444961713Sgirish 515a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(channel)); 51644961713Sgirish if (!TXDMA_CHANNEL_VALID(channel)) { 51744961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 51844961713Sgirish " npi_txdma_log_page_config" 51944961713Sgirish " Invalid Input: channel <0x%x>", 52044961713Sgirish channel)); 52144961713Sgirish return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel)); 52244961713Sgirish } 52344961713Sgirish 52444961713Sgirish switch (op_mode) { 52544961713Sgirish case OP_GET: 52644961713Sgirish switch (type) { 52744961713Sgirish case TXDMA_LOG_PAGE_ALL: 52844961713Sgirish return (npi_txdma_log_page_get(handle, channel, 52944961713Sgirish cfgp)); 53044961713Sgirish case TXDMA_LOG_PAGE_MASK: 53144961713Sgirish if (!cfgp->page_num) { 53244961713Sgirish TX_LOG_REG_READ64(handle, TX_LOG_PAGE_MASK1_REG, 53344961713Sgirish channel, &val); 53444961713Sgirish cfgp->mask = val & DMA_LOG_PAGE_MASK_MASK; 53544961713Sgirish } else { 53644961713Sgirish TX_LOG_REG_READ64(handle, TX_LOG_PAGE_MASK2_REG, 53744961713Sgirish channel, &val); 53844961713Sgirish cfgp->mask = val & DMA_LOG_PAGE_MASK_MASK; 53944961713Sgirish } 54044961713Sgirish break; 54144961713Sgirish 54244961713Sgirish case TXDMA_LOG_PAGE_VALUE: 54344961713Sgirish if (!cfgp->page_num) { 54444961713Sgirish TX_LOG_REG_READ64(handle, TX_LOG_PAGE_VAL1_REG, 54544961713Sgirish channel, &val); 54644961713Sgirish cfgp->value = val & DMA_LOG_PAGE_VALUE_MASK; 54744961713Sgirish } else { 54844961713Sgirish TX_LOG_REG_READ64(handle, TX_LOG_PAGE_VAL2_REG, 54944961713Sgirish channel, &val); 55044961713Sgirish cfgp->value = val & DMA_LOG_PAGE_VALUE_MASK; 55144961713Sgirish } 55244961713Sgirish break; 55344961713Sgirish 55444961713Sgirish case TXDMA_LOG_PAGE_RELOC: 55544961713Sgirish if (!cfgp->page_num) { 55644961713Sgirish TX_LOG_REG_READ64(handle, TX_LOG_PAGE_RELO1_REG, 55744961713Sgirish channel, &val); 55844961713Sgirish cfgp->reloc = val & DMA_LOG_PAGE_RELO_MASK; 55944961713Sgirish } else { 56044961713Sgirish TX_LOG_REG_READ64(handle, TX_LOG_PAGE_VAL2_REG, 56144961713Sgirish channel, &val); 56244961713Sgirish cfgp->reloc = val & DMA_LOG_PAGE_RELO_MASK; 56344961713Sgirish } 56444961713Sgirish break; 56544961713Sgirish 56644961713Sgirish default: 56744961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 56844961713Sgirish " npi_txdma_log_page_config" 56944961713Sgirish " Invalid Input: pageconfig <0x%x>", 57044961713Sgirish type)); 57144961713Sgirish return (NPI_FAILURE | 57244961713Sgirish NPI_TXDMA_OPCODE_INVALID(channel)); 57344961713Sgirish } 57444961713Sgirish 57544961713Sgirish break; 57644961713Sgirish 57744961713Sgirish case OP_SET: 57844961713Sgirish case OP_CLEAR: 57944961713Sgirish if (op_mode == OP_CLEAR) { 58044961713Sgirish cfgp->valid = 0; 58144961713Sgirish cfgp->mask = cfgp->func_num = 0; 58244961713Sgirish cfgp->value = cfgp->reloc = 0; 58344961713Sgirish } 58444961713Sgirish switch (type) { 58544961713Sgirish case TXDMA_LOG_PAGE_ALL: 58644961713Sgirish return (npi_txdma_log_page_set(handle, channel, 58744961713Sgirish cfgp)); 58844961713Sgirish case TXDMA_LOG_PAGE_MASK: 58944961713Sgirish if (!cfgp->page_num) { 59044961713Sgirish TX_LOG_REG_WRITE64(handle, 59144961713Sgirish TX_LOG_PAGE_MASK1_REG, channel, 59244961713Sgirish (cfgp->mask & DMA_LOG_PAGE_MASK_MASK)); 59344961713Sgirish } else { 59444961713Sgirish TX_LOG_REG_WRITE64(handle, 59544961713Sgirish TX_LOG_PAGE_MASK2_REG, 59644961713Sgirish channel, (cfgp->mask & DMA_LOG_PAGE_MASK_MASK)); 59744961713Sgirish } 59844961713Sgirish break; 59944961713Sgirish 60044961713Sgirish case TXDMA_LOG_PAGE_VALUE: 60144961713Sgirish if (!cfgp->page_num) { 60244961713Sgirish TX_LOG_REG_WRITE64(handle, 60344961713Sgirish TX_LOG_PAGE_VAL1_REG, channel, 60444961713Sgirish (cfgp->value & DMA_LOG_PAGE_VALUE_MASK)); 60544961713Sgirish } else { 60644961713Sgirish TX_LOG_REG_WRITE64(handle, 60744961713Sgirish TX_LOG_PAGE_VAL2_REG, channel, 60844961713Sgirish (cfgp->value & DMA_LOG_PAGE_VALUE_MASK)); 60944961713Sgirish } 61044961713Sgirish break; 61144961713Sgirish 61244961713Sgirish case TXDMA_LOG_PAGE_RELOC: 61344961713Sgirish if (!cfgp->page_num) { 61444961713Sgirish TX_LOG_REG_WRITE64(handle, 61544961713Sgirish TX_LOG_PAGE_RELO1_REG, channel, 61644961713Sgirish (cfgp->reloc & DMA_LOG_PAGE_RELO_MASK)); 61744961713Sgirish } else { 61844961713Sgirish TX_LOG_REG_WRITE64(handle, 61944961713Sgirish TX_LOG_PAGE_RELO2_REG, channel, 62044961713Sgirish (cfgp->reloc & DMA_LOG_PAGE_RELO_MASK)); 62144961713Sgirish } 62244961713Sgirish break; 62344961713Sgirish 62444961713Sgirish default: 62544961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 62644961713Sgirish " npi_txdma_log_page_config" 62744961713Sgirish " Invalid Input: pageconfig <0x%x>", 62844961713Sgirish type)); 62944961713Sgirish return (NPI_FAILURE | 63044961713Sgirish NPI_TXDMA_OPCODE_INVALID(channel)); 63144961713Sgirish } 63244961713Sgirish 63344961713Sgirish break; 63444961713Sgirish default: 63544961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 63644961713Sgirish " npi_txdma_log_page_config" 63744961713Sgirish " Invalid Input: op <0x%x>", 63844961713Sgirish op_mode)); 63944961713Sgirish return (NPI_FAILURE | NPI_TXDMA_OPCODE_INVALID(channel)); 64044961713Sgirish } 64144961713Sgirish 64244961713Sgirish return (status); 64344961713Sgirish } 64444961713Sgirish 64544961713Sgirish /* 64644961713Sgirish * npi_txdma_log_page_vld_config(): 64744961713Sgirish * This function is called to configure the logical 64844961713Sgirish * page valid register. 64944961713Sgirish * 65044961713Sgirish * Parameters: 65144961713Sgirish * handle - NPI handle 65244961713Sgirish * op_mode - OP_GET: get valid page configuration 65344961713Sgirish * OP_SET: set valid page configuration 65444961713Sgirish * OP_UPDATE: update valid page configuration 65544961713Sgirish * OP_CLEAR: reset both valid pages to 65644961713Sgirish * not defined (0). 65744961713Sgirish * channel - hardware TXDMA channel from 0 to 23. 65844961713Sgirish * vld_p - pointer to hardware defined log page valid register. 65944961713Sgirish * Return: 66044961713Sgirish * NPI_SUCCESS - If set is complete successfully. 66144961713Sgirish * 66244961713Sgirish * Error: 66344961713Sgirish * NPI_FAILURE - 66444961713Sgirish * NPI_TXDMA_CHANNEL_INVALID - 66544961713Sgirish * NPI_TXDMA_OPCODE_INVALID - 66644961713Sgirish */ 66744961713Sgirish npi_status_t 66844961713Sgirish npi_txdma_log_page_vld_config(npi_handle_t handle, io_op_t op_mode, 66944961713Sgirish uint8_t channel, p_log_page_vld_t vld_p) 67044961713Sgirish { 67144961713Sgirish int status = NPI_SUCCESS; 67244961713Sgirish log_page_vld_t vld; 67344961713Sgirish 674a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(channel)); 67544961713Sgirish if (!TXDMA_CHANNEL_VALID(channel)) { 67644961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 67744961713Sgirish " npi_txdma_log_page_vld_config" 67844961713Sgirish " Invalid Input: channel <0x%x>", 67944961713Sgirish channel)); 68044961713Sgirish return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel)); 68144961713Sgirish } 68244961713Sgirish 68344961713Sgirish switch (op_mode) { 68444961713Sgirish case OP_GET: 68544961713Sgirish TX_LOG_REG_READ64(handle, TX_LOG_PAGE_VLD_REG, channel, 68644961713Sgirish &vld_p->value); 68744961713Sgirish break; 68844961713Sgirish 68944961713Sgirish case OP_SET: 69044961713Sgirish TX_LOG_REG_WRITE64(handle, TX_LOG_PAGE_VLD_REG, 69144961713Sgirish channel, vld_p->value); 69244961713Sgirish break; 69344961713Sgirish 69444961713Sgirish case OP_UPDATE: 69544961713Sgirish TX_LOG_REG_READ64(handle, TX_LOG_PAGE_VLD_REG, channel, 69644961713Sgirish &vld.value); 69744961713Sgirish TX_LOG_REG_WRITE64(handle, TX_LOG_PAGE_VLD_REG, 69844961713Sgirish channel, vld.value | vld_p->value); 69944961713Sgirish break; 70044961713Sgirish 70144961713Sgirish case OP_CLEAR: 70244961713Sgirish TX_LOG_REG_WRITE64(handle, TX_LOG_PAGE_VLD_REG, 70344961713Sgirish channel, 0); 70444961713Sgirish break; 70544961713Sgirish 70644961713Sgirish default: 70744961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 70844961713Sgirish " npi_txdma_log_pag_vld_cofig" 70944961713Sgirish " Invalid Input: pagevld <0x%x>", 71044961713Sgirish op_mode)); 71144961713Sgirish return (NPI_FAILURE | NPI_TXDMA_OPCODE_INVALID(channel)); 71244961713Sgirish } 71344961713Sgirish 71444961713Sgirish return (status); 71544961713Sgirish } 71644961713Sgirish 71744961713Sgirish /* 71844961713Sgirish * npi_txdma_channel_reset(): 71944961713Sgirish * This function is called to reset a transmit DMA channel. 72044961713Sgirish * (This function is used to reset a channel and reinitialize 72144961713Sgirish * all other bits except RST_STATE). 72244961713Sgirish * 72344961713Sgirish * Parameters: 72444961713Sgirish * handle - NPI handle (virtualization flag must be defined). 72544961713Sgirish * channel - logical TXDMA channel from 0 to 23. 72644961713Sgirish * (If virtualization flag is not set, then 72744961713Sgirish * logical channel is the same as the hardware 72844961713Sgirish * channel number). 72944961713Sgirish * 73044961713Sgirish * Return: 73144961713Sgirish * NPI_SUCCESS - If reset is complete successfully. 73244961713Sgirish * 73344961713Sgirish * Error: 73444961713Sgirish * NPI_FAILURE - 73544961713Sgirish * NPI_TXDMA_CHANNEL_INVALID - 73644961713Sgirish * NPI_TXDMA_RESET_FAILED - 73744961713Sgirish */ 73844961713Sgirish npi_status_t 73944961713Sgirish npi_txdma_channel_reset(npi_handle_t handle, uint8_t channel) 74044961713Sgirish { 74144961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_TDC_CTL, 74244961713Sgirish " npi_txdma_channel_reset" 74344961713Sgirish " RESETTING", 74444961713Sgirish channel)); 74544961713Sgirish return (npi_txdma_channel_control(handle, TXDMA_RESET, channel)); 74644961713Sgirish } 74744961713Sgirish 74844961713Sgirish /* 74944961713Sgirish * npi_txdma_channel_init_enable(): 75044961713Sgirish * This function is called to start a transmit DMA channel after reset. 75144961713Sgirish * 75244961713Sgirish * Parameters: 75344961713Sgirish * handle - NPI handle (virtualization flag must be defined). 75444961713Sgirish * channel - logical TXDMA channel from 0 to 23. 75544961713Sgirish * (If virtualization flag is not set, then 75644961713Sgirish * logical channel is the same as the hardware 75744961713Sgirish * channel number). 75844961713Sgirish * Return: 75944961713Sgirish * NPI_SUCCESS - If DMA channel is started successfully. 76044961713Sgirish * 76144961713Sgirish * Error: 76244961713Sgirish * NPI_FAILURE - 76344961713Sgirish * NPI_TXDMA_CHANNEL_INVALID - 76444961713Sgirish */ 76544961713Sgirish npi_status_t 76644961713Sgirish npi_txdma_channel_init_enable(npi_handle_t handle, uint8_t channel) 76744961713Sgirish { 76844961713Sgirish return (npi_txdma_channel_control(handle, TXDMA_INIT_START, channel)); 76944961713Sgirish } 77044961713Sgirish 77144961713Sgirish /* 77244961713Sgirish * npi_txdma_channel_enable(): 77344961713Sgirish * This function is called to start a transmit DMA channel. 77444961713Sgirish * 77544961713Sgirish * Parameters: 77644961713Sgirish * handle - NPI handle (virtualization flag must be defined). 77744961713Sgirish * channel - logical TXDMA channel from 0 to 23. 77844961713Sgirish * (If virtualization flag is not set, then 77944961713Sgirish * logical channel is the same as the hardware 78044961713Sgirish * channel number). 78144961713Sgirish * Return: 78244961713Sgirish * NPI_SUCCESS - If DMA channel is stopped successfully. 78344961713Sgirish * 78444961713Sgirish * Error: 78544961713Sgirish * NPI_FAILURE - 78644961713Sgirish * NPI_TXDMA_CHANNEL_INVALID - 78744961713Sgirish */ 78844961713Sgirish 78944961713Sgirish npi_status_t 79044961713Sgirish npi_txdma_channel_enable(npi_handle_t handle, uint8_t channel) 79144961713Sgirish { 79244961713Sgirish return (npi_txdma_channel_control(handle, TXDMA_START, channel)); 79344961713Sgirish } 79444961713Sgirish 79544961713Sgirish /* 79644961713Sgirish * npi_txdma_channel_disable(): 79744961713Sgirish * This function is called to stop a transmit DMA channel. 79844961713Sgirish * 79944961713Sgirish * Parameters: 80044961713Sgirish * handle - NPI handle (virtualization flag must be defined). 80144961713Sgirish * channel - logical TXDMA channel from 0 to 23. 80244961713Sgirish * (If virtualization flag is not set, then 80344961713Sgirish * logical channel is the same as the hardware 80444961713Sgirish * channel number). 80544961713Sgirish * Return: 80644961713Sgirish * NPI_SUCCESS - If DMA channel is stopped successfully. 80744961713Sgirish * 80844961713Sgirish * Error: 80944961713Sgirish * NPI_FAILURE - 81044961713Sgirish * NPI_TXDMA_CHANNEL_INVALID - 81144961713Sgirish * NPI_TXDMA_STOP_FAILED - 81244961713Sgirish */ 81344961713Sgirish npi_status_t 81444961713Sgirish npi_txdma_channel_disable(npi_handle_t handle, uint8_t channel) 81544961713Sgirish { 81644961713Sgirish return (npi_txdma_channel_control(handle, TXDMA_STOP, channel)); 81744961713Sgirish } 81844961713Sgirish 81944961713Sgirish /* 82044961713Sgirish * npi_txdma_channel_resume(): 82144961713Sgirish * This function is called to restart a transmit DMA channel. 82244961713Sgirish * 82344961713Sgirish * Parameters: 82444961713Sgirish * handle - NPI handle (virtualization flag must be defined). 82544961713Sgirish * channel - logical TXDMA channel from 0 to 23. 82644961713Sgirish * (If virtualization flag is not set, then 82744961713Sgirish * logical channel is the same as the hardware 82844961713Sgirish * channel number). 82944961713Sgirish * Return: 83044961713Sgirish * NPI_SUCCESS - If DMA channel is stopped successfully. 83144961713Sgirish * 83244961713Sgirish * Error: 83344961713Sgirish * NPI_FAILURE - 83444961713Sgirish * NPI_TXDMA_CHANNEL_INVALID - 83544961713Sgirish * NPI_TXDMA_RESUME_FAILED - 83644961713Sgirish */ 83744961713Sgirish npi_status_t 83844961713Sgirish npi_txdma_channel_resume(npi_handle_t handle, uint8_t channel) 83944961713Sgirish { 84044961713Sgirish return (npi_txdma_channel_control(handle, TXDMA_RESUME, channel)); 84144961713Sgirish } 84244961713Sgirish 84344961713Sgirish /* 84444961713Sgirish * npi_txdma_channel_mmk_clear(): 84544961713Sgirish * This function is called to clear MMK bit. 84644961713Sgirish * 84744961713Sgirish * Parameters: 84844961713Sgirish * handle - NPI handle (virtualization flag must be defined). 84944961713Sgirish * channel - logical TXDMA channel from 0 to 23. 85044961713Sgirish * (If virtualization flag is not set, then 85144961713Sgirish * logical channel is the same as the hardware 85244961713Sgirish * channel number). 85344961713Sgirish * Return: 85444961713Sgirish * NPI_SUCCESS - If MMK is reset successfully. 85544961713Sgirish * 85644961713Sgirish * Error: 85744961713Sgirish * NPI_FAILURE - 85844961713Sgirish * NPI_TXDMA_CHANNEL_INVALID - 85944961713Sgirish */ 86044961713Sgirish npi_status_t 86144961713Sgirish npi_txdma_channel_mmk_clear(npi_handle_t handle, uint8_t channel) 86244961713Sgirish { 86344961713Sgirish return (npi_txdma_channel_control(handle, TXDMA_CLEAR_MMK, channel)); 86444961713Sgirish } 86544961713Sgirish 86644961713Sgirish /* 86744961713Sgirish * npi_txdma_channel_mbox_enable(): 86844961713Sgirish * This function is called to enable the mailbox update. 86944961713Sgirish * 87044961713Sgirish * Parameters: 87144961713Sgirish * handle - NPI handle (virtualization flag must be defined). 87244961713Sgirish * channel - logical TXDMA channel from 0 to 23. 87344961713Sgirish * (If virtualization flag is not set, then 87444961713Sgirish * logical channel is the same as the hardware 87544961713Sgirish * channel number). 87644961713Sgirish * Return: 87744961713Sgirish * NPI_SUCCESS - If mailbox is enabled successfully. 87844961713Sgirish * 87944961713Sgirish * Error: 88044961713Sgirish * NPI_HW_ERROR - 88144961713Sgirish * NPI_FAILURE - 88244961713Sgirish * NPI_TXDMA_CHANNEL_INVALID - 88344961713Sgirish */ 88444961713Sgirish npi_status_t 88544961713Sgirish npi_txdma_channel_mbox_enable(npi_handle_t handle, uint8_t channel) 88644961713Sgirish { 88744961713Sgirish return (npi_txdma_channel_control(handle, TXDMA_MBOX_ENABLE, channel)); 88844961713Sgirish } 88944961713Sgirish 89044961713Sgirish /* 89144961713Sgirish * npi_txdma_channel_control(): 89244961713Sgirish * This function is called to control a transmit DMA channel 89344961713Sgirish * for reset, start or stop. 89444961713Sgirish * 89544961713Sgirish * Parameters: 89644961713Sgirish * handle - NPI handle (virtualization flag must be defined). 89744961713Sgirish * control - NPI defined control type supported 89844961713Sgirish * - TXDMA_INIT_RESET 89944961713Sgirish * - TXDMA_INIT_START 90044961713Sgirish * - TXDMA_RESET 90144961713Sgirish * - TXDMA_START 90244961713Sgirish * - TXDMA_STOP 90344961713Sgirish * channel - logical TXDMA channel from 0 to 23. 90444961713Sgirish * (If virtualization flag is not set, then 90544961713Sgirish * logical channel is the same as the hardware 90644961713Sgirish * 90744961713Sgirish * Return: 90844961713Sgirish * NPI_SUCCESS - If reset is complete successfully. 90944961713Sgirish * 91044961713Sgirish * Error: 91144961713Sgirish * NPI_FAILURE - 91244961713Sgirish * NPI_TXDMA_OPCODE_INVALID - 91344961713Sgirish * NPI_TXDMA_CHANNEL_INVALID - 91444961713Sgirish * NPI_TXDMA_RESET_FAILED - 91544961713Sgirish * NPI_TXDMA_STOP_FAILED - 91644961713Sgirish * NPI_TXDMA_RESUME_FAILED - 91744961713Sgirish */ 91844961713Sgirish npi_status_t 91944961713Sgirish npi_txdma_channel_control(npi_handle_t handle, txdma_cs_cntl_t control, 92044961713Sgirish uint8_t channel) 92144961713Sgirish { 92244961713Sgirish int status = NPI_SUCCESS; 92344961713Sgirish tx_cs_t cs; 92444961713Sgirish 925a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(channel)); 92644961713Sgirish if (!TXDMA_CHANNEL_VALID(channel)) { 92744961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 92844961713Sgirish " npi_txdma_channel_control" 92944961713Sgirish " Invalid Input: channel <0x%x>", 93044961713Sgirish channel)); 93144961713Sgirish return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel)); 93244961713Sgirish } 93344961713Sgirish 93444961713Sgirish switch (control) { 93544961713Sgirish case TXDMA_INIT_RESET: 93644961713Sgirish cs.value = 0; 93744961713Sgirish TXDMA_REG_READ64(handle, TX_CS_REG, channel, &cs.value); 93844961713Sgirish cs.bits.ldw.rst = 1; 93944961713Sgirish TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs.value); 94044961713Sgirish return (npi_txdma_control_reset_wait(handle, channel)); 94144961713Sgirish 94244961713Sgirish case TXDMA_INIT_START: 94344961713Sgirish cs.value = 0; 94444961713Sgirish TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs.value); 94544961713Sgirish break; 94644961713Sgirish 94744961713Sgirish case TXDMA_RESET: 94844961713Sgirish /* 94944961713Sgirish * Sets reset bit only (Hardware will reset all 95044961713Sgirish * the RW bits but leave the RO bits alone. 95144961713Sgirish */ 95244961713Sgirish cs.value = 0; 95344961713Sgirish cs.bits.ldw.rst = 1; 95444961713Sgirish TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs.value); 95544961713Sgirish return (npi_txdma_control_reset_wait(handle, channel)); 95644961713Sgirish 95744961713Sgirish case TXDMA_START: 95844961713Sgirish /* Enable the DMA channel */ 95944961713Sgirish TXDMA_REG_READ64(handle, TX_CS_REG, channel, &cs.value); 96044961713Sgirish cs.bits.ldw.stop_n_go = 0; 96144961713Sgirish TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs.value); 96244961713Sgirish break; 96344961713Sgirish 96444961713Sgirish case TXDMA_STOP: 96544961713Sgirish /* Disable the DMA channel */ 96644961713Sgirish TXDMA_REG_READ64(handle, TX_CS_REG, channel, &cs.value); 96744961713Sgirish cs.bits.ldw.stop_n_go = 1; 96844961713Sgirish TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs.value); 96944961713Sgirish status = npi_txdma_control_stop_wait(handle, channel); 97044961713Sgirish if (status) { 97144961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 97244961713Sgirish "Cannot stop channel %d (TXC hung!)", 97344961713Sgirish channel)); 97444961713Sgirish } 97544961713Sgirish break; 97644961713Sgirish 97744961713Sgirish case TXDMA_RESUME: 97844961713Sgirish /* Resume the packet transmission after stopping */ 97944961713Sgirish TXDMA_REG_READ64(handle, TX_CS_REG, channel, &cs.value); 98044961713Sgirish cs.value |= ~TX_CS_STOP_N_GO_MASK; 98144961713Sgirish TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs.value); 98244961713Sgirish return (npi_txdma_control_resume_wait(handle, channel)); 98344961713Sgirish 98444961713Sgirish case TXDMA_CLEAR_MMK: 98544961713Sgirish /* Write 1 to MK bit to clear the MMK bit */ 98644961713Sgirish TXDMA_REG_READ64(handle, TX_CS_REG, channel, &cs.value); 98744961713Sgirish cs.bits.ldw.mk = 1; 98844961713Sgirish TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs.value); 98944961713Sgirish break; 99044961713Sgirish 99144961713Sgirish case TXDMA_MBOX_ENABLE: 99244961713Sgirish /* 99344961713Sgirish * Write 1 to MB bit to enable mailbox update 99444961713Sgirish * (cleared to 0 by hardware after update). 99544961713Sgirish */ 99644961713Sgirish TXDMA_REG_READ64(handle, TX_CS_REG, channel, &cs.value); 99744961713Sgirish cs.bits.ldw.mb = 1; 99844961713Sgirish TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs.value); 99944961713Sgirish break; 100044961713Sgirish 100144961713Sgirish default: 100244961713Sgirish status = (NPI_FAILURE | NPI_TXDMA_OPCODE_INVALID(channel)); 100344961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 100444961713Sgirish " npi_txdma_channel_control" 100544961713Sgirish " Invalid Input: control <0x%x>", 100644961713Sgirish control)); 100744961713Sgirish } 100844961713Sgirish 100944961713Sgirish return (status); 101044961713Sgirish } 101144961713Sgirish 101244961713Sgirish /* 101344961713Sgirish * npi_txdma_control_status(): 101444961713Sgirish * This function is called to operate on the control 101544961713Sgirish * and status register. 101644961713Sgirish * 101744961713Sgirish * Parameters: 101844961713Sgirish * handle - NPI handle 101944961713Sgirish * op_mode - OP_GET: get hardware control and status 102044961713Sgirish * OP_SET: set hardware control and status 102144961713Sgirish * OP_UPDATE: update hardware control and status. 102244961713Sgirish * OP_CLEAR: clear control and status register to 0s. 102344961713Sgirish * channel - hardware TXDMA channel from 0 to 23. 102444961713Sgirish * cs_p - pointer to hardware defined control and status 102544961713Sgirish * structure. 102644961713Sgirish * Return: 102744961713Sgirish * NPI_SUCCESS - If set is complete successfully. 102844961713Sgirish * 102944961713Sgirish * Error: 103044961713Sgirish * NPI_FAILURE - 103144961713Sgirish * NPI_TXDMA_OPCODE_INVALID - 103244961713Sgirish * NPI_TXDMA_CHANNEL_INVALID - 103344961713Sgirish * NPI_TXDMA_FUNC_INVALID - 103444961713Sgirish */ 103544961713Sgirish npi_status_t 103644961713Sgirish npi_txdma_control_status(npi_handle_t handle, io_op_t op_mode, 103744961713Sgirish uint8_t channel, p_tx_cs_t cs_p) 103844961713Sgirish { 103944961713Sgirish int status = NPI_SUCCESS; 104044961713Sgirish tx_cs_t txcs; 104144961713Sgirish 1042a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(channel)); 104344961713Sgirish if (!TXDMA_CHANNEL_VALID(channel)) { 104444961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 104544961713Sgirish " npi_txdma_control_status" 104644961713Sgirish " Invalid Input: channel <0x%x>", 104744961713Sgirish channel)); 104844961713Sgirish return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel)); 104944961713Sgirish } 105044961713Sgirish 105144961713Sgirish switch (op_mode) { 105244961713Sgirish case OP_GET: 105344961713Sgirish TXDMA_REG_READ64(handle, TX_CS_REG, channel, &cs_p->value); 105444961713Sgirish break; 105544961713Sgirish 105644961713Sgirish case OP_SET: 105744961713Sgirish TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs_p->value); 105844961713Sgirish break; 105944961713Sgirish 106044961713Sgirish case OP_UPDATE: 106144961713Sgirish TXDMA_REG_READ64(handle, TX_CS_REG, channel, &txcs.value); 106244961713Sgirish TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, 106344961713Sgirish cs_p->value | txcs.value); 106444961713Sgirish break; 106544961713Sgirish 106644961713Sgirish default: 106744961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 106844961713Sgirish " npi_txdma_control_status" 106944961713Sgirish " Invalid Input: control <0x%x>", 107044961713Sgirish op_mode)); 107144961713Sgirish return (NPI_FAILURE | NPI_TXDMA_OPCODE_INVALID(channel)); 107244961713Sgirish } 107344961713Sgirish 107444961713Sgirish return (status); 107544961713Sgirish 107644961713Sgirish } 107744961713Sgirish 107844961713Sgirish /* 107944961713Sgirish * npi_txdma_event_mask(): 108044961713Sgirish * This function is called to operate on the event mask 108144961713Sgirish * register which is used for generating interrupts.. 108244961713Sgirish * and status register. 108344961713Sgirish * 108444961713Sgirish * Parameters: 108544961713Sgirish * handle - NPI handle 108644961713Sgirish * op_mode - OP_GET: get hardware event mask 108744961713Sgirish * OP_SET: set hardware interrupt event masks 108844961713Sgirish * OP_CLEAR: clear control and status register to 0s. 108944961713Sgirish * channel - hardware TXDMA channel from 0 to 23. 109044961713Sgirish * mask_p - pointer to hardware defined event mask 109144961713Sgirish * structure. 109244961713Sgirish * Return: 109344961713Sgirish * NPI_SUCCESS - If set is complete successfully. 109444961713Sgirish * 109544961713Sgirish * Error: 109644961713Sgirish * NPI_FAILURE - 109744961713Sgirish * NPI_TXDMA_OPCODE_INVALID - 109844961713Sgirish * NPI_TXDMA_CHANNEL_INVALID - 109944961713Sgirish */ 110044961713Sgirish npi_status_t 110144961713Sgirish npi_txdma_event_mask(npi_handle_t handle, io_op_t op_mode, 110244961713Sgirish uint8_t channel, p_tx_dma_ent_msk_t mask_p) 110344961713Sgirish { 110444961713Sgirish int status = NPI_SUCCESS; 110544961713Sgirish tx_dma_ent_msk_t mask; 110644961713Sgirish 1107a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(channel)); 110844961713Sgirish if (!TXDMA_CHANNEL_VALID(channel)) { 110944961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 111044961713Sgirish " npi_txdma_event_mask" 111144961713Sgirish " Invalid Input: channel <0x%x>", 111244961713Sgirish channel)); 111344961713Sgirish return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel)); 111444961713Sgirish } 111544961713Sgirish 111644961713Sgirish switch (op_mode) { 111744961713Sgirish case OP_GET: 111844961713Sgirish TXDMA_REG_READ64(handle, TX_ENT_MSK_REG, channel, 111944961713Sgirish &mask_p->value); 112044961713Sgirish break; 112144961713Sgirish 112244961713Sgirish case OP_SET: 112344961713Sgirish TXDMA_REG_WRITE64(handle, TX_ENT_MSK_REG, channel, 112444961713Sgirish mask_p->value); 112544961713Sgirish break; 112644961713Sgirish 112744961713Sgirish case OP_UPDATE: 112844961713Sgirish TXDMA_REG_READ64(handle, TX_ENT_MSK_REG, channel, &mask.value); 112944961713Sgirish TXDMA_REG_WRITE64(handle, TX_ENT_MSK_REG, channel, 113044961713Sgirish mask_p->value | mask.value); 113144961713Sgirish break; 113244961713Sgirish 113344961713Sgirish default: 113444961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 113544961713Sgirish " npi_txdma_event_mask" 113644961713Sgirish " Invalid Input: eventmask <0x%x>", 113744961713Sgirish op_mode)); 113844961713Sgirish return (NPI_FAILURE | NPI_TXDMA_OPCODE_INVALID(channel)); 113944961713Sgirish } 114044961713Sgirish 114144961713Sgirish return (status); 114244961713Sgirish } 114344961713Sgirish 114444961713Sgirish /* 114544961713Sgirish * npi_txdma_event_mask_config(): 114644961713Sgirish * This function is called to operate on the event mask 114744961713Sgirish * register which is used for generating interrupts.. 114844961713Sgirish * and status register. 114944961713Sgirish * 115044961713Sgirish * Parameters: 115144961713Sgirish * handle - NPI handle 115244961713Sgirish * op_mode - OP_GET: get hardware event mask 115344961713Sgirish * OP_SET: set hardware interrupt event masks 115444961713Sgirish * OP_CLEAR: clear control and status register to 0s. 115544961713Sgirish * channel - hardware TXDMA channel from 0 to 23. 115644961713Sgirish * cfgp - pointer to NPI defined event mask 115744961713Sgirish * enum data type. 115844961713Sgirish * Return: 115944961713Sgirish * NPI_SUCCESS - If set is complete successfully. 116044961713Sgirish * 116144961713Sgirish * Error: 116244961713Sgirish * NPI_FAILURE - 116344961713Sgirish * NPI_TXDMA_OPCODE_INVALID - 116444961713Sgirish * NPI_TXDMA_CHANNEL_INVALID - 116544961713Sgirish */ 116644961713Sgirish npi_status_t 116744961713Sgirish npi_txdma_event_mask_config(npi_handle_t handle, io_op_t op_mode, 116844961713Sgirish uint8_t channel, txdma_ent_msk_cfg_t *mask_cfgp) 116944961713Sgirish { 117044961713Sgirish int status = NPI_SUCCESS; 1171*678453a8Sspeer uint64_t configuration = *mask_cfgp; 117244961713Sgirish uint64_t value; 117344961713Sgirish 1174a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(channel)); 117544961713Sgirish if (!TXDMA_CHANNEL_VALID(channel)) { 117644961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 117744961713Sgirish " npi_txdma_event_mask_config" 117844961713Sgirish " Invalid Input: channel <0x%x>", 117944961713Sgirish channel)); 118044961713Sgirish 118144961713Sgirish return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel)); 118244961713Sgirish } 118344961713Sgirish 118444961713Sgirish switch (op_mode) { 118544961713Sgirish case OP_GET: 1186*678453a8Sspeer TXDMA_REG_READ64(handle, TX_ENT_MSK_REG, channel, 1187*678453a8Sspeer (uint64_t *)mask_cfgp); 118844961713Sgirish break; 118944961713Sgirish 119044961713Sgirish case OP_SET: 119144961713Sgirish TXDMA_REG_WRITE64(handle, TX_ENT_MSK_REG, channel, 1192*678453a8Sspeer configuration); 119344961713Sgirish break; 119444961713Sgirish 119544961713Sgirish case OP_UPDATE: 119644961713Sgirish TXDMA_REG_READ64(handle, TX_ENT_MSK_REG, channel, &value); 119744961713Sgirish TXDMA_REG_WRITE64(handle, TX_ENT_MSK_REG, channel, 1198*678453a8Sspeer configuration | value); 119944961713Sgirish break; 120044961713Sgirish 120144961713Sgirish case OP_CLEAR: 120244961713Sgirish TXDMA_REG_WRITE64(handle, TX_ENT_MSK_REG, channel, 120344961713Sgirish CFG_TXDMA_MASK_ALL); 120444961713Sgirish break; 120544961713Sgirish default: 120644961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 120744961713Sgirish " npi_txdma_event_mask_config" 120844961713Sgirish " Invalid Input: eventmask <0x%x>", 120944961713Sgirish op_mode)); 121044961713Sgirish return (NPI_FAILURE | NPI_TXDMA_OPCODE_INVALID(channel)); 121144961713Sgirish } 121244961713Sgirish 121344961713Sgirish return (status); 121444961713Sgirish } 121544961713Sgirish 121644961713Sgirish /* 121744961713Sgirish * npi_txdma_event_mask_mk_out(): 121844961713Sgirish * This function is called to mask out the packet transmit marked event. 121944961713Sgirish * 122044961713Sgirish * Parameters: 122144961713Sgirish * handle - NPI handle 122244961713Sgirish * channel - hardware TXDMA channel from 0 to 23. 122344961713Sgirish * enum data type. 122444961713Sgirish * Return: 122544961713Sgirish * NPI_SUCCESS - If set is complete successfully. 122644961713Sgirish * 122744961713Sgirish * Error: 122844961713Sgirish * NPI_FAILURE - 122944961713Sgirish * NPI_TXDMA_CHANNEL_INVALID - 123044961713Sgirish */ 123144961713Sgirish npi_status_t 123244961713Sgirish npi_txdma_event_mask_mk_out(npi_handle_t handle, uint8_t channel) 123344961713Sgirish { 1234*678453a8Sspeer uint64_t event_mask; 1235*678453a8Sspeer int status = NPI_SUCCESS; 123644961713Sgirish 1237a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(channel)); 123844961713Sgirish if (!TXDMA_CHANNEL_VALID(channel)) { 123944961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 124044961713Sgirish " npi_txdma_event_mask_mk_out" 124144961713Sgirish " Invalid Input: channel <0x%x>", 124244961713Sgirish channel)); 124344961713Sgirish return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel)); 124444961713Sgirish } 124544961713Sgirish 124644961713Sgirish TXDMA_REG_READ64(handle, TX_ENT_MSK_REG, channel, &event_mask); 124744961713Sgirish TXDMA_REG_WRITE64(handle, TX_ENT_MSK_REG, channel, 124844961713Sgirish event_mask & (~TX_ENT_MSK_MK_MASK)); 124944961713Sgirish 125044961713Sgirish return (status); 125144961713Sgirish } 125244961713Sgirish 125344961713Sgirish /* 125444961713Sgirish * npi_txdma_event_mask_mk_in(): 125544961713Sgirish * This function is called to set the mask for the the packet marked event. 125644961713Sgirish * 125744961713Sgirish * Parameters: 125844961713Sgirish * handle - NPI handle 125944961713Sgirish * channel - hardware TXDMA channel from 0 to 23. 126044961713Sgirish * enum data type. 126144961713Sgirish * Return: 126244961713Sgirish * NPI_SUCCESS - If set is complete successfully. 126344961713Sgirish * 126444961713Sgirish * Error: 126544961713Sgirish * NPI_FAILURE - 126644961713Sgirish * NPI_TXDMA_CHANNEL_INVALID - 126744961713Sgirish */ 126844961713Sgirish npi_status_t 126944961713Sgirish npi_txdma_event_mask_mk_in(npi_handle_t handle, uint8_t channel) 127044961713Sgirish { 1271*678453a8Sspeer uint64_t event_mask; 1272*678453a8Sspeer int status = NPI_SUCCESS; 127344961713Sgirish 1274a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(channel)); 127544961713Sgirish if (!TXDMA_CHANNEL_VALID(channel)) { 127644961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 127744961713Sgirish " npi_txdma_event_mask_mk_in" 127844961713Sgirish " Invalid Input: channel <0x%x>", 127944961713Sgirish channel)); 128044961713Sgirish return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel)); 128144961713Sgirish } 128244961713Sgirish 128344961713Sgirish TXDMA_REG_READ64(handle, TX_ENT_MSK_REG, channel, &event_mask); 128444961713Sgirish TXDMA_REG_WRITE64(handle, TX_ENT_MSK_REG, channel, 128544961713Sgirish event_mask | TX_ENT_MSK_MK_MASK); 128644961713Sgirish 128744961713Sgirish return (status); 128844961713Sgirish } 128944961713Sgirish 129044961713Sgirish /* 129144961713Sgirish * npi_txdma_ring_addr_set(): 129244961713Sgirish * This function is called to configure the transmit descriptor 129344961713Sgirish * ring address and its size. 129444961713Sgirish * 129544961713Sgirish * Parameters: 129644961713Sgirish * handle - NPI handle (virtualization flag must be defined 129744961713Sgirish * if its register pointer is from the virtual region). 129844961713Sgirish * channel - logical TXDMA channel from 0 to 23. 129944961713Sgirish * (If virtualization flag is not set, then 130044961713Sgirish * logical channel is the same as the hardware 130144961713Sgirish * channel number). 130244961713Sgirish * start_addr - starting address of the descriptor 130344961713Sgirish * len - maximum length of the descriptor 130444961713Sgirish * (in number of 64 bytes block). 130544961713Sgirish * Return: 130644961713Sgirish * NPI_SUCCESS - If set is complete successfully. 130744961713Sgirish * 130844961713Sgirish * Error: 130944961713Sgirish * NPI_FAILURE - 131044961713Sgirish * NPI_TXDMA_OPCODE_INVALID - 131144961713Sgirish * NPI_TXDMA_CHANNEL_INVALID - 131244961713Sgirish */ 131344961713Sgirish npi_status_t 131444961713Sgirish npi_txdma_ring_addr_set(npi_handle_t handle, uint8_t channel, 131544961713Sgirish uint64_t start_addr, uint32_t len) 131644961713Sgirish { 131744961713Sgirish int status = NPI_SUCCESS; 131844961713Sgirish tx_rng_cfig_t cfg; 131944961713Sgirish 1320a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(channel)); 132144961713Sgirish if (!TXDMA_CHANNEL_VALID(channel)) { 132244961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 132344961713Sgirish " npi_txdma_ring_addr_set" 132444961713Sgirish " Invalid Input: channel <0x%x>", 132544961713Sgirish channel)); 132644961713Sgirish return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel)); 132744961713Sgirish } 132844961713Sgirish 132944961713Sgirish cfg.value = ((start_addr & TX_RNG_CFIG_ADDR_MASK) | 133044961713Sgirish (((uint64_t)len) << TX_RNG_CFIG_LEN_SHIFT)); 133144961713Sgirish TXDMA_REG_WRITE64(handle, TX_RNG_CFIG_REG, channel, cfg.value); 133244961713Sgirish 133344961713Sgirish return (status); 133444961713Sgirish } 133544961713Sgirish 133644961713Sgirish /* 133744961713Sgirish * npi_txdma_ring_config(): 133844961713Sgirish * This function is called to config a descriptor ring 133944961713Sgirish * by using the hardware defined data. 134044961713Sgirish * 134144961713Sgirish * Parameters: 134244961713Sgirish * handle - NPI handle (virtualization flag must be defined 134344961713Sgirish * if its register pointer is from the virtual region). 134444961713Sgirish * channel - logical TXDMA channel from 0 to 23. 134544961713Sgirish * (If virtualization flag is not set, then 134644961713Sgirish * logical channel is the same as the hardware 134744961713Sgirish * channel number). 134844961713Sgirish * op_mode - OP_GET: get transmit ring configuration 134944961713Sgirish * OP_SET: set transmit ring configuration 135044961713Sgirish * reg_data - pointer to hardware defined transmit ring 135144961713Sgirish * configuration data structure. 135244961713Sgirish * Return: 135344961713Sgirish * NPI_SUCCESS - If set/get is complete successfully. 135444961713Sgirish * 135544961713Sgirish * Error: 135644961713Sgirish * NPI_FAILURE - 135744961713Sgirish * NPI_TXDMA_CHANNEL_INVALID - 135844961713Sgirish */ 135944961713Sgirish npi_status_t 136044961713Sgirish npi_txdma_ring_config(npi_handle_t handle, io_op_t op_mode, 136144961713Sgirish uint8_t channel, uint64_t *reg_data) 136244961713Sgirish { 136344961713Sgirish int status = NPI_SUCCESS; 136444961713Sgirish 1365a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(channel)); 136644961713Sgirish if (!TXDMA_CHANNEL_VALID(channel)) { 136744961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 136844961713Sgirish " npi_txdma_ring_config" 136944961713Sgirish " Invalid Input: channel <0x%x>", 137044961713Sgirish channel)); 137144961713Sgirish return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel)); 137244961713Sgirish } 137344961713Sgirish 137444961713Sgirish switch (op_mode) { 137544961713Sgirish case OP_GET: 137644961713Sgirish TXDMA_REG_READ64(handle, TX_RNG_CFIG_REG, channel, reg_data); 137744961713Sgirish break; 137844961713Sgirish 137944961713Sgirish case OP_SET: 138044961713Sgirish TXDMA_REG_WRITE64(handle, TX_RNG_CFIG_REG, channel, 138144961713Sgirish *reg_data); 138244961713Sgirish break; 138344961713Sgirish 138444961713Sgirish default: 138544961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 138644961713Sgirish " npi_txdma_ring_config" 138744961713Sgirish " Invalid Input: ring_config <0x%x>", 138844961713Sgirish op_mode)); 138944961713Sgirish return (NPI_FAILURE | NPI_TXDMA_OPCODE_INVALID(channel)); 139044961713Sgirish } 139144961713Sgirish 139244961713Sgirish return (status); 139344961713Sgirish } 139444961713Sgirish 139544961713Sgirish /* 139644961713Sgirish * npi_txdma_mbox_config(): 139744961713Sgirish * This function is called to config the mailbox address 139844961713Sgirish * 139944961713Sgirish * Parameters: 140044961713Sgirish * handle - NPI handle (virtualization flag must be defined 140144961713Sgirish * if its register pointer is from the virtual region). 140244961713Sgirish * channel - logical TXDMA channel from 0 to 23. 140344961713Sgirish * (If virtualization flag is not set, then 140444961713Sgirish * logical channel is the same as the hardware 140544961713Sgirish * channel number). 140644961713Sgirish * op_mode - OP_GET: get the mailbox address 140744961713Sgirish * OP_SET: set the mailbox address 140844961713Sgirish * reg_data - pointer to the mailbox address. 140944961713Sgirish * Return: 141044961713Sgirish * NPI_SUCCESS - If set is complete successfully. 141144961713Sgirish * 141244961713Sgirish * Error: 141344961713Sgirish * NPI_FAILURE - 141444961713Sgirish * NPI_TXDMA_OPCODE_INVALID - 141544961713Sgirish * NPI_TXDMA_CHANNEL_INVALID - 141644961713Sgirish */ 141744961713Sgirish npi_status_t 141844961713Sgirish npi_txdma_mbox_config(npi_handle_t handle, io_op_t op_mode, 141944961713Sgirish uint8_t channel, uint64_t *mbox_addr) 142044961713Sgirish { 142144961713Sgirish int status = NPI_SUCCESS; 142244961713Sgirish txdma_mbh_t mh; 142344961713Sgirish txdma_mbl_t ml; 142444961713Sgirish 1425a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(channel)); 142644961713Sgirish if (!TXDMA_CHANNEL_VALID(channel)) { 142744961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 142844961713Sgirish " npi_txdma_mbox_config" 142944961713Sgirish " Invalid Input: channel <0x%x>", 143044961713Sgirish channel)); 143144961713Sgirish return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel)); 143244961713Sgirish } 143344961713Sgirish 143444961713Sgirish mh.value = ml.value = 0; 143544961713Sgirish 143644961713Sgirish switch (op_mode) { 143744961713Sgirish case OP_GET: 143844961713Sgirish TXDMA_REG_READ64(handle, TXDMA_MBH_REG, channel, &mh.value); 143944961713Sgirish TXDMA_REG_READ64(handle, TXDMA_MBL_REG, channel, &ml.value); 144044961713Sgirish *mbox_addr = ml.value; 144144961713Sgirish *mbox_addr |= (mh.value << TXDMA_MBH_ADDR_SHIFT); 144244961713Sgirish 144344961713Sgirish break; 144444961713Sgirish 144544961713Sgirish case OP_SET: 144644961713Sgirish ml.bits.ldw.mbaddr = ((*mbox_addr & TXDMA_MBL_MASK) >> 144744961713Sgirish TXDMA_MBL_SHIFT); 144844961713Sgirish TXDMA_REG_WRITE64(handle, TXDMA_MBL_REG, channel, ml.value); 144944961713Sgirish mh.bits.ldw.mbaddr = ((*mbox_addr >> TXDMA_MBH_ADDR_SHIFT) & 145044961713Sgirish TXDMA_MBH_MASK); 145144961713Sgirish TXDMA_REG_WRITE64(handle, TXDMA_MBH_REG, channel, mh.value); 145244961713Sgirish 145344961713Sgirish break; 145444961713Sgirish 145544961713Sgirish default: 145644961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 145744961713Sgirish " npi_txdma_mbox_config" 145844961713Sgirish " Invalid Input: mbox <0x%x>", 145944961713Sgirish op_mode)); 146044961713Sgirish return (NPI_FAILURE | NPI_TXDMA_OPCODE_INVALID(channel)); 146144961713Sgirish } 146244961713Sgirish 146344961713Sgirish return (status); 146444961713Sgirish 146544961713Sgirish } 146644961713Sgirish 146744961713Sgirish /* 146844961713Sgirish * npi_txdma_desc_gather_set(): 146944961713Sgirish * This function is called to set up a transmit descriptor entry. 147044961713Sgirish * 147144961713Sgirish * Parameters: 147244961713Sgirish * handle - NPI handle (register pointer is the 147344961713Sgirish * descriptor address in memory). 147444961713Sgirish * desc_p - pointer to a descriptor 147544961713Sgirish * gather_index - which entry (starts from index 0 to 15) 147644961713Sgirish * mark - mark bit (only valid if it is the first gather). 147744961713Sgirish * ngathers - number of gather pointers to set to the first gather. 147844961713Sgirish * dma_ioaddr - starting dma address of an IO buffer to write. 147944961713Sgirish * (SAD) 148044961713Sgirish * transfer_len - transfer len. 148144961713Sgirish * Return: 148244961713Sgirish * NPI_SUCCESS - If set is complete successfully. 148344961713Sgirish * 148444961713Sgirish * Error: 148544961713Sgirish * NPI_FAILURE - 148644961713Sgirish * NPI_TXDMA_OPCODE_INVALID - 148744961713Sgirish * NPI_TXDMA_CHANNEL_INVALID - 148844961713Sgirish * NPI_TXDMA_XFER_LEN_INVALID - 148944961713Sgirish */ 149044961713Sgirish npi_status_t 149144961713Sgirish npi_txdma_desc_gather_set(npi_handle_t handle, 149244961713Sgirish p_tx_desc_t desc_p, uint8_t gather_index, 149344961713Sgirish boolean_t mark, uint8_t ngathers, 149444961713Sgirish uint64_t dma_ioaddr, uint32_t transfer_len) 149544961713Sgirish { 149644961713Sgirish int status; 149744961713Sgirish 149844961713Sgirish status = NPI_TXDMA_GATHER_INDEX(gather_index); 149944961713Sgirish if (status) { 150044961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 150144961713Sgirish " npi_txdma_desc_gather_set" 150244961713Sgirish " Invalid Input: gather_index <0x%x>", 150344961713Sgirish gather_index)); 150444961713Sgirish return (status); 150544961713Sgirish } 150644961713Sgirish 150744961713Sgirish if (transfer_len > TX_MAX_TRANSFER_LENGTH) { 150844961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 150944961713Sgirish " npi_txdma_desc_gather_set" 151044961713Sgirish " Invalid Input: tr_len <0x%x>", 151144961713Sgirish transfer_len)); 151244961713Sgirish return (NPI_FAILURE | NPI_TXDMA_XFER_LEN_INVALID); 151344961713Sgirish } 151444961713Sgirish 151544961713Sgirish if (gather_index == 0) { 151644961713Sgirish desc_p->bits.hdw.sop = 1; 151744961713Sgirish desc_p->bits.hdw.mark = mark; 151844961713Sgirish desc_p->bits.hdw.num_ptr = ngathers; 151944961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_TDC_CTL, 152044961713Sgirish "npi_txdma_gather_set: SOP len %d (%d)", 152144961713Sgirish desc_p->bits.hdw.tr_len, transfer_len)); 152244961713Sgirish } 152344961713Sgirish 152444961713Sgirish desc_p->bits.hdw.tr_len = transfer_len; 152544961713Sgirish desc_p->bits.hdw.sad = dma_ioaddr >> 32; 152644961713Sgirish desc_p->bits.ldw.sad = dma_ioaddr & 0xffffffff; 152744961713Sgirish 152844961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_TDC_CTL, 152944961713Sgirish "npi_txdma_gather_set: xfer len %d to set (%d)", 153044961713Sgirish desc_p->bits.hdw.tr_len, transfer_len)); 153144961713Sgirish 153244961713Sgirish NXGE_MEM_PIO_WRITE64(handle, desc_p->value); 153344961713Sgirish 153444961713Sgirish return (status); 153544961713Sgirish } 153644961713Sgirish 153744961713Sgirish /* 153844961713Sgirish * npi_txdma_desc_sop_set(): 153944961713Sgirish * This function is called to set up the first gather entry. 154044961713Sgirish * 154144961713Sgirish * Parameters: 154244961713Sgirish * handle - NPI handle (register pointer is the 154344961713Sgirish * descriptor address in memory). 154444961713Sgirish * desc_p - pointer to a descriptor 154544961713Sgirish * mark - mark bit (only valid if it is the first gather). 154644961713Sgirish * ngathers - number of gather pointers to set to the first gather. 154744961713Sgirish * Return: 154844961713Sgirish * NPI_SUCCESS - If set is complete successfully. 154944961713Sgirish * 155044961713Sgirish * Error: 155144961713Sgirish */ 155244961713Sgirish npi_status_t 155344961713Sgirish npi_txdma_desc_gather_sop_set(npi_handle_t handle, 155444961713Sgirish p_tx_desc_t desc_p, 155544961713Sgirish boolean_t mark_mode, 155644961713Sgirish uint8_t ngathers) 155744961713Sgirish { 155844961713Sgirish int status = NPI_SUCCESS; 155944961713Sgirish 156044961713Sgirish desc_p->bits.hdw.sop = 1; 156144961713Sgirish desc_p->bits.hdw.mark = mark_mode; 156244961713Sgirish desc_p->bits.hdw.num_ptr = ngathers; 156344961713Sgirish 156444961713Sgirish NXGE_MEM_PIO_WRITE64(handle, desc_p->value); 156544961713Sgirish 156644961713Sgirish return (status); 156744961713Sgirish } 156844961713Sgirish npi_status_t 156944961713Sgirish npi_txdma_desc_gather_sop_set_1(npi_handle_t handle, 157044961713Sgirish p_tx_desc_t desc_p, 157144961713Sgirish boolean_t mark_mode, 157244961713Sgirish uint8_t ngathers, 157344961713Sgirish uint32_t extra) 157444961713Sgirish { 157544961713Sgirish int status = NPI_SUCCESS; 157644961713Sgirish 157744961713Sgirish desc_p->bits.hdw.sop = 1; 157844961713Sgirish desc_p->bits.hdw.mark = mark_mode; 157944961713Sgirish desc_p->bits.hdw.num_ptr = ngathers; 158044961713Sgirish desc_p->bits.hdw.tr_len += extra; 158144961713Sgirish 158244961713Sgirish NXGE_MEM_PIO_WRITE64(handle, desc_p->value); 158344961713Sgirish 158444961713Sgirish return (status); 158544961713Sgirish } 158644961713Sgirish 158744961713Sgirish npi_status_t 158844961713Sgirish npi_txdma_desc_set_xfer_len(npi_handle_t handle, 158944961713Sgirish p_tx_desc_t desc_p, 159044961713Sgirish uint32_t transfer_len) 159144961713Sgirish { 159244961713Sgirish int status = NPI_SUCCESS; 159344961713Sgirish 159444961713Sgirish desc_p->bits.hdw.tr_len = transfer_len; 159544961713Sgirish 159644961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_TDC_CTL, 159744961713Sgirish "npi_set_xfer_len: len %d (%d)", 159844961713Sgirish desc_p->bits.hdw.tr_len, transfer_len)); 159944961713Sgirish 160044961713Sgirish NXGE_MEM_PIO_WRITE64(handle, desc_p->value); 160144961713Sgirish 160244961713Sgirish return (status); 160344961713Sgirish } 160444961713Sgirish 160544961713Sgirish npi_status_t 160644961713Sgirish npi_txdma_desc_set_zero(npi_handle_t handle, uint16_t entries) 160744961713Sgirish { 160844961713Sgirish uint32_t offset; 160944961713Sgirish int i; 161044961713Sgirish 161144961713Sgirish /* 161244961713Sgirish * Assume no wrapped around. 161344961713Sgirish */ 161444961713Sgirish offset = 0; 161544961713Sgirish for (i = 0; i < entries; i++) { 161644961713Sgirish NXGE_REG_WR64(handle, offset, 0); 161744961713Sgirish offset += (i * TXDMA_DESC_SIZE); 161844961713Sgirish } 161944961713Sgirish 162044961713Sgirish return (NPI_SUCCESS); 162144961713Sgirish } 162244961713Sgirish 162344961713Sgirish npi_status_t 162444961713Sgirish npi_txdma_desc_mem_get(npi_handle_t handle, uint16_t index, 162544961713Sgirish p_tx_desc_t desc_p) 162644961713Sgirish { 162744961713Sgirish int status = NPI_SUCCESS; 162844961713Sgirish 162944961713Sgirish npi_txdma_dump_desc_one(handle, desc_p, index); 163044961713Sgirish 163144961713Sgirish return (status); 163244961713Sgirish 163344961713Sgirish } 163444961713Sgirish 163544961713Sgirish /* 163644961713Sgirish * npi_txdma_desc_kick_reg_set(): 163744961713Sgirish * This function is called to kick the transmit to start transmission. 163844961713Sgirish * 163944961713Sgirish * Parameters: 164044961713Sgirish * handle - NPI handle (virtualization flag must be defined). 164144961713Sgirish * channel - logical TXDMA channel from 0 to 23. 164244961713Sgirish * (If virtualization flag is not set, then 164344961713Sgirish * logical channel is the same as the hardware 164444961713Sgirish * channel number). 164544961713Sgirish * tail_index - index into the transmit descriptor 164644961713Sgirish * wrap - toggle bit to indicate if the tail index is 164744961713Sgirish * wrapped around. 164844961713Sgirish * 164944961713Sgirish * Return: 165044961713Sgirish * NPI_SUCCESS - If set is complete successfully. 165144961713Sgirish * 165244961713Sgirish * Error: 165344961713Sgirish * NPI_FAILURE - 165444961713Sgirish * NPI_TXDMA_CHANNEL_INVALID - 165544961713Sgirish */ 165644961713Sgirish npi_status_t 165744961713Sgirish npi_txdma_desc_kick_reg_set(npi_handle_t handle, uint8_t channel, 165844961713Sgirish uint16_t tail_index, boolean_t wrap) 165944961713Sgirish { 166044961713Sgirish int status = NPI_SUCCESS; 166144961713Sgirish tx_ring_kick_t kick; 166244961713Sgirish 1663a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(channel)); 166444961713Sgirish if (!TXDMA_CHANNEL_VALID(channel)) { 166544961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 166644961713Sgirish " npi_txdma_desc_kick_reg_set" 166744961713Sgirish " Invalid Input: channel <0x%x>", 166844961713Sgirish channel)); 166944961713Sgirish return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel)); 167044961713Sgirish } 167144961713Sgirish 167244961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_TDC_CTL, 167344961713Sgirish " npi_txdma_desc_kick_reg_set: " 167444961713Sgirish " KICKING channel %d", 167544961713Sgirish channel)); 167644961713Sgirish 167744961713Sgirish /* Toggle the wrap around bit */ 167844961713Sgirish kick.value = 0; 167944961713Sgirish kick.bits.ldw.wrap = wrap; 168044961713Sgirish kick.bits.ldw.tail = tail_index; 168144961713Sgirish 168244961713Sgirish /* Kick start the Transmit kick register */ 168344961713Sgirish TXDMA_REG_WRITE64(handle, TX_RING_KICK_REG, channel, kick.value); 168444961713Sgirish 168544961713Sgirish return (status); 168644961713Sgirish } 168744961713Sgirish 168844961713Sgirish /* 168944961713Sgirish * npi_txdma_desc_kick_reg_get(): 169044961713Sgirish * This function is called to kick the transmit to start transmission. 169144961713Sgirish * 169244961713Sgirish * Parameters: 169344961713Sgirish * handle - NPI handle (virtualization flag must be defined). 169444961713Sgirish * channel - logical TXDMA channel from 0 to 23. 169544961713Sgirish * (If virtualization flag is not set, then 169644961713Sgirish * logical channel is the same as the hardware 169744961713Sgirish * channel number). 169844961713Sgirish * tail_index - index into the transmit descriptor 169944961713Sgirish * wrap - toggle bit to indicate if the tail index is 170044961713Sgirish * wrapped around. 170144961713Sgirish * 170244961713Sgirish * Return: 170344961713Sgirish * NPI_SUCCESS - If get is complete successfully. 170444961713Sgirish * 170544961713Sgirish * Error: 170644961713Sgirish * NPI_FAILURE - 170744961713Sgirish * NPI_TXDMA_CHANNEL_INVALID - 170844961713Sgirish */ 170944961713Sgirish npi_status_t 171044961713Sgirish npi_txdma_desc_kick_reg_get(npi_handle_t handle, uint8_t channel, 171144961713Sgirish p_tx_ring_kick_t kick_p) 171244961713Sgirish { 171344961713Sgirish int status = NPI_SUCCESS; 171444961713Sgirish 1715a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(channel)); 171644961713Sgirish if (!TXDMA_CHANNEL_VALID(channel)) { 171744961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 171844961713Sgirish " npi_txdma_desc_kick_reg_get" 171944961713Sgirish " Invalid Input: channel <0x%x>", 172044961713Sgirish channel)); 172144961713Sgirish return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel)); 172244961713Sgirish } 172344961713Sgirish 172444961713Sgirish TXDMA_REG_READ64(handle, TX_RING_KICK_REG, channel, &kick_p->value); 172544961713Sgirish 172644961713Sgirish return (status); 172744961713Sgirish } 172844961713Sgirish 172944961713Sgirish /* 173044961713Sgirish * npi_txdma_ring_head_get(): 173144961713Sgirish * This function is called to get the transmit ring head index. 173244961713Sgirish * 173344961713Sgirish * Parameters: 173444961713Sgirish * handle - NPI handle (virtualization flag must be defined). 173544961713Sgirish * channel - logical TXDMA channel from 0 to 23. 173644961713Sgirish * (If virtualization flag is not set, then 173744961713Sgirish * logical channel is the same as the hardware 173844961713Sgirish * channel number). 173944961713Sgirish * hdl_p - pointer to the hardware defined transmit 174044961713Sgirish * ring header data (head index and wrap bit). 174144961713Sgirish * 174244961713Sgirish * Return: 174344961713Sgirish * NPI_SUCCESS - If get is complete successfully. 174444961713Sgirish * 174544961713Sgirish * Error: 174644961713Sgirish * NPI_FAILURE - 174744961713Sgirish * NPI_TXDMA_CHANNEL_INVALID - 174844961713Sgirish */ 174944961713Sgirish npi_status_t 175044961713Sgirish npi_txdma_ring_head_get(npi_handle_t handle, uint8_t channel, 175144961713Sgirish p_tx_ring_hdl_t hdl_p) 175244961713Sgirish { 175344961713Sgirish int status = NPI_SUCCESS; 175444961713Sgirish 1755a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(channel)); 175644961713Sgirish if (!TXDMA_CHANNEL_VALID(channel)) { 175744961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 175844961713Sgirish " npi_txdma_ring_head_get" 175944961713Sgirish " Invalid Input: channel <0x%x>", 176044961713Sgirish channel)); 176144961713Sgirish return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel)); 176244961713Sgirish } 176344961713Sgirish 176444961713Sgirish TXDMA_REG_READ64(handle, TX_RING_HDL_REG, channel, &hdl_p->value); 176544961713Sgirish 176644961713Sgirish return (status); 176744961713Sgirish } 176844961713Sgirish 176944961713Sgirish /*ARGSUSED*/ 177044961713Sgirish npi_status_t 177144961713Sgirish npi_txdma_channel_mbox_get(npi_handle_t handle, uint8_t channel, 177244961713Sgirish p_txdma_mailbox_t mbox_p) 177344961713Sgirish { 177444961713Sgirish int status = NPI_SUCCESS; 177544961713Sgirish 177644961713Sgirish return (status); 177744961713Sgirish 177844961713Sgirish } 177944961713Sgirish 178044961713Sgirish npi_status_t 178144961713Sgirish npi_txdma_channel_pre_state_get(npi_handle_t handle, uint8_t channel, 178244961713Sgirish p_tx_dma_pre_st_t prep) 178344961713Sgirish { 178444961713Sgirish int status = NPI_SUCCESS; 178544961713Sgirish 1786a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(channel)); 178744961713Sgirish if (!TXDMA_CHANNEL_VALID(channel)) { 178844961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 178944961713Sgirish " npi_txdma_channel_pre_state_get" 179044961713Sgirish " Invalid Input: channel <0x%x>", 179144961713Sgirish channel)); 179244961713Sgirish return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel)); 179344961713Sgirish } 179444961713Sgirish 179544961713Sgirish TXDMA_REG_READ64(handle, TX_DMA_PRE_ST_REG, channel, &prep->value); 179644961713Sgirish 179744961713Sgirish return (status); 179844961713Sgirish } 179944961713Sgirish 180044961713Sgirish npi_status_t 180144961713Sgirish npi_txdma_ring_error_get(npi_handle_t handle, uint8_t channel, 180244961713Sgirish p_txdma_ring_errlog_t ring_errlog_p) 180344961713Sgirish { 180444961713Sgirish tx_rng_err_logh_t logh; 180544961713Sgirish tx_rng_err_logl_t logl; 180644961713Sgirish int status = NPI_SUCCESS; 180744961713Sgirish 1808a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(channel)); 180944961713Sgirish if (!TXDMA_CHANNEL_VALID(channel)) { 181044961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 181144961713Sgirish " npi_txdma_ring_error_get" 181244961713Sgirish " Invalid Input: channel <0x%x>", 181344961713Sgirish channel)); 181444961713Sgirish return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel)); 181544961713Sgirish } 181644961713Sgirish 181744961713Sgirish logh.value = 0; 181844961713Sgirish TXDMA_REG_READ64(handle, TX_RNG_ERR_LOGH_REG, channel, &logh.value); 181944961713Sgirish TXDMA_REG_READ64(handle, TX_RNG_ERR_LOGL_REG, channel, &logl.value); 182044961713Sgirish ring_errlog_p->logh.bits.ldw.err = logh.bits.ldw.err; 182144961713Sgirish ring_errlog_p->logh.bits.ldw.merr = logh.bits.ldw.merr; 182244961713Sgirish ring_errlog_p->logh.bits.ldw.errcode = logh.bits.ldw.errcode; 182344961713Sgirish ring_errlog_p->logh.bits.ldw.err_addr = logh.bits.ldw.err_addr; 182444961713Sgirish ring_errlog_p->logl.bits.ldw.err_addr = logl.bits.ldw.err_addr; 182544961713Sgirish 182644961713Sgirish return (status); 182744961713Sgirish } 182844961713Sgirish 182944961713Sgirish npi_status_t 183044961713Sgirish npi_txdma_inj_par_error_clear(npi_handle_t handle) 183144961713Sgirish { 183244961713Sgirish NXGE_REG_WR64(handle, TDMC_INJ_PAR_ERR_REG, 0); 183344961713Sgirish 183444961713Sgirish return (NPI_SUCCESS); 183544961713Sgirish } 183644961713Sgirish 183744961713Sgirish npi_status_t 183844961713Sgirish npi_txdma_inj_par_error_set(npi_handle_t handle, uint32_t err_bits) 183944961713Sgirish { 184044961713Sgirish tdmc_inj_par_err_t inj; 184144961713Sgirish 184244961713Sgirish inj.value = 0; 184344961713Sgirish inj.bits.ldw.inject_parity_error = (err_bits & TDMC_INJ_PAR_ERR_MASK); 184444961713Sgirish NXGE_REG_WR64(handle, TDMC_INJ_PAR_ERR_REG, inj.value); 184544961713Sgirish 184644961713Sgirish return (NPI_SUCCESS); 184744961713Sgirish } 184844961713Sgirish 184944961713Sgirish npi_status_t 185044961713Sgirish npi_txdma_inj_par_error_update(npi_handle_t handle, uint32_t err_bits) 185144961713Sgirish { 185244961713Sgirish tdmc_inj_par_err_t inj; 185344961713Sgirish 185444961713Sgirish inj.value = 0; 185544961713Sgirish NXGE_REG_RD64(handle, TDMC_INJ_PAR_ERR_REG, &inj.value); 185644961713Sgirish inj.value |= (err_bits & TDMC_INJ_PAR_ERR_MASK); 185744961713Sgirish NXGE_REG_WR64(handle, TDMC_INJ_PAR_ERR_REG, inj.value); 185844961713Sgirish 185944961713Sgirish return (NPI_SUCCESS); 186044961713Sgirish } 186144961713Sgirish 186244961713Sgirish npi_status_t 186344961713Sgirish npi_txdma_inj_par_error_get(npi_handle_t handle, uint32_t *err_bits) 186444961713Sgirish { 186544961713Sgirish tdmc_inj_par_err_t inj; 186644961713Sgirish 186744961713Sgirish inj.value = 0; 186844961713Sgirish NXGE_REG_RD64(handle, TDMC_INJ_PAR_ERR_REG, &inj.value); 186944961713Sgirish *err_bits = (inj.value & TDMC_INJ_PAR_ERR_MASK); 187044961713Sgirish 187144961713Sgirish return (NPI_SUCCESS); 187244961713Sgirish } 187344961713Sgirish 187444961713Sgirish npi_status_t 187544961713Sgirish npi_txdma_dbg_sel_set(npi_handle_t handle, uint8_t dbg_sel) 187644961713Sgirish { 187744961713Sgirish tdmc_dbg_sel_t dbg; 187844961713Sgirish 187944961713Sgirish dbg.value = 0; 188044961713Sgirish dbg.bits.ldw.dbg_sel = (dbg_sel & TDMC_DBG_SEL_MASK); 188144961713Sgirish 188244961713Sgirish NXGE_REG_WR64(handle, TDMC_DBG_SEL_REG, dbg.value); 188344961713Sgirish 188444961713Sgirish return (NPI_SUCCESS); 188544961713Sgirish } 188644961713Sgirish 188744961713Sgirish npi_status_t 188844961713Sgirish npi_txdma_training_vector_set(npi_handle_t handle, uint32_t training_vector) 188944961713Sgirish { 189044961713Sgirish tdmc_training_t vec; 189144961713Sgirish 189244961713Sgirish vec.value = 0; 189344961713Sgirish vec.bits.ldw.vec = training_vector; 189444961713Sgirish 189544961713Sgirish NXGE_REG_WR64(handle, TDMC_TRAINING_REG, vec.value); 189644961713Sgirish 189744961713Sgirish return (NPI_SUCCESS); 189844961713Sgirish } 189944961713Sgirish 190044961713Sgirish /* 190144961713Sgirish * npi_txdma_dump_desc_one(npi_handle_t handle, p_tx_desc_t desc_p, 190244961713Sgirish * int desc_index) 190344961713Sgirish * 190444961713Sgirish * Dumps the contents of transmit descriptors. 190544961713Sgirish * 190644961713Sgirish * Parameters: 190744961713Sgirish * handle - NPI handle (register pointer is the 190844961713Sgirish * descriptor address in memory). 190944961713Sgirish * desc_p - pointer to place the descriptor contents 191044961713Sgirish * desc_index - descriptor index 191144961713Sgirish * 191244961713Sgirish */ 191344961713Sgirish /*ARGSUSED*/ 191444961713Sgirish void 191544961713Sgirish npi_txdma_dump_desc_one(npi_handle_t handle, p_tx_desc_t desc_p, int desc_index) 191644961713Sgirish { 191744961713Sgirish 191844961713Sgirish tx_desc_t desc, *desp; 191944961713Sgirish #ifdef NXGE_DEBUG 192044961713Sgirish uint64_t sad; 192144961713Sgirish int xfer_len; 192244961713Sgirish #endif 192344961713Sgirish 192444961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_TDC_CTL, 192544961713Sgirish "\n==> npi_txdma_dump_desc_one: dump " 192644961713Sgirish " desc_p $%p descriptor entry %d\n", 192744961713Sgirish desc_p, desc_index)); 192844961713Sgirish desc.value = 0; 192944961713Sgirish desp = ((desc_p != NULL) ? desc_p : (p_tx_desc_t)&desc); 193044961713Sgirish desp->value = NXGE_MEM_PIO_READ64(handle); 193144961713Sgirish #ifdef NXGE_DEBUG 193244961713Sgirish sad = (desp->value & TX_PKT_DESC_SAD_MASK); 193344961713Sgirish xfer_len = ((desp->value & TX_PKT_DESC_TR_LEN_MASK) >> 193444961713Sgirish TX_PKT_DESC_TR_LEN_SHIFT); 193544961713Sgirish #endif 193644961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_TDC_CTL, "\n\t: value 0x%llx\n" 193744961713Sgirish "\t\tsad $%p\ttr_len %d len %d\tnptrs %d\tmark %d sop %d\n", 193844961713Sgirish desp->value, 193944961713Sgirish sad, 194044961713Sgirish desp->bits.hdw.tr_len, 194144961713Sgirish xfer_len, 194244961713Sgirish desp->bits.hdw.num_ptr, 194344961713Sgirish desp->bits.hdw.mark, 194444961713Sgirish desp->bits.hdw.sop)); 194544961713Sgirish 194644961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_TDC_CTL, 194744961713Sgirish "\n<== npi_txdma_dump_desc_one: Done \n")); 194844961713Sgirish 194944961713Sgirish } 195044961713Sgirish 195144961713Sgirish /*ARGSUSED*/ 195244961713Sgirish void 195344961713Sgirish npi_txdma_dump_hdr(npi_handle_t handle, p_tx_pkt_header_t hdrp) 195444961713Sgirish { 195544961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_TDC_CTL, 195644961713Sgirish "\n==> npi_txdma_dump_hdr: dump\n")); 195744961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_TDC_CTL, 195844961713Sgirish "\n\t: value 0x%llx\n" 195944961713Sgirish "\t\tpkttype 0x%x\tip_ver %d\tllc %d\tvlan %d \tihl %d\n" 196044961713Sgirish "\t\tl3start %d\tl4start %d\tl4stuff %d\n" 196144961713Sgirish "\t\txferlen %d\tpad %d\n", 196244961713Sgirish hdrp->value, 196344961713Sgirish hdrp->bits.hdw.cksum_en_pkt_type, 196444961713Sgirish hdrp->bits.hdw.ip_ver, 196544961713Sgirish hdrp->bits.hdw.llc, 196644961713Sgirish hdrp->bits.hdw.vlan, 196744961713Sgirish hdrp->bits.hdw.ihl, 196844961713Sgirish hdrp->bits.hdw.l3start, 196944961713Sgirish hdrp->bits.hdw.l4start, 197044961713Sgirish hdrp->bits.hdw.l4stuff, 197144961713Sgirish hdrp->bits.ldw.tot_xfer_len, 197244961713Sgirish hdrp->bits.ldw.pad)); 197344961713Sgirish 197444961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_TDC_CTL, 197544961713Sgirish "\n<== npi_txdma_dump_hdr: Done \n")); 197644961713Sgirish } 197744961713Sgirish 197844961713Sgirish npi_status_t 197944961713Sgirish npi_txdma_inj_int_error_set(npi_handle_t handle, uint8_t channel, 198044961713Sgirish p_tdmc_intr_dbg_t erp) 198144961713Sgirish { 198244961713Sgirish int status = NPI_SUCCESS; 198344961713Sgirish 1984a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(channel)); 198544961713Sgirish if (!TXDMA_CHANNEL_VALID(channel)) { 198644961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 198744961713Sgirish " npi_txdma_inj_int_error_set" 198844961713Sgirish " Invalid Input: channel <0x%x>", 198944961713Sgirish channel)); 199044961713Sgirish return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel)); 199144961713Sgirish } 199244961713Sgirish 199344961713Sgirish TXDMA_REG_WRITE64(handle, TDMC_INTR_DBG_REG, channel, erp->value); 199444961713Sgirish 199544961713Sgirish return (status); 199644961713Sgirish } 199744961713Sgirish 199844961713Sgirish /* 199944961713Sgirish * Static functions start here. 200044961713Sgirish */ 200144961713Sgirish static npi_status_t 200244961713Sgirish npi_txdma_control_reset_wait(npi_handle_t handle, uint8_t channel) 200344961713Sgirish { 200444961713Sgirish 200544961713Sgirish tx_cs_t txcs; 200644961713Sgirish int loop = 0; 200744961713Sgirish 200844961713Sgirish do { 200944961713Sgirish NXGE_DELAY(TXDMA_WAIT_MSEC); 201044961713Sgirish TXDMA_REG_READ64(handle, TX_CS_REG, channel, &txcs.value); 201144961713Sgirish if (!txcs.bits.ldw.rst) { 201244961713Sgirish return (NPI_SUCCESS); 201344961713Sgirish } 201444961713Sgirish loop++; 201544961713Sgirish } while (loop < TXDMA_WAIT_LOOP); 201644961713Sgirish 201744961713Sgirish if (loop == TXDMA_WAIT_LOOP) { 201844961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 201944961713Sgirish "npi_txdma_control_reset_wait: RST bit not " 202044961713Sgirish "cleared to 0 txcs.bits 0x%llx", txcs.value)); 202144961713Sgirish return (NPI_FAILURE | NPI_TXDMA_RESET_FAILED); 202244961713Sgirish } 202344961713Sgirish return (NPI_SUCCESS); 202444961713Sgirish } 202544961713Sgirish 202644961713Sgirish static npi_status_t 202744961713Sgirish npi_txdma_control_stop_wait(npi_handle_t handle, uint8_t channel) 202844961713Sgirish { 202944961713Sgirish tx_cs_t txcs; 203044961713Sgirish int loop = 0; 203144961713Sgirish 203244961713Sgirish do { 203344961713Sgirish NXGE_DELAY(TXDMA_WAIT_MSEC); 203444961713Sgirish TXDMA_REG_READ64(handle, TX_CS_REG, channel, &txcs.value); 203544961713Sgirish if (txcs.bits.ldw.sng_state) { 203644961713Sgirish return (NPI_SUCCESS); 203744961713Sgirish } 203844961713Sgirish loop++; 203944961713Sgirish } while (loop < TXDMA_WAIT_LOOP); 204044961713Sgirish 204144961713Sgirish if (loop == TXDMA_WAIT_LOOP) { 204244961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 204344961713Sgirish "npi_txdma_control_stop_wait: SNG_STATE not " 204444961713Sgirish "set to 1 txcs.bits 0x%llx", txcs.value)); 204544961713Sgirish return (NPI_FAILURE | NPI_TXDMA_STOP_FAILED); 204644961713Sgirish } 204744961713Sgirish 204844961713Sgirish return (NPI_SUCCESS); 204944961713Sgirish } 205044961713Sgirish 205144961713Sgirish static npi_status_t 205244961713Sgirish npi_txdma_control_resume_wait(npi_handle_t handle, uint8_t channel) 205344961713Sgirish { 205444961713Sgirish tx_cs_t txcs; 205544961713Sgirish int loop = 0; 205644961713Sgirish 205744961713Sgirish do { 205844961713Sgirish NXGE_DELAY(TXDMA_WAIT_MSEC); 205944961713Sgirish TXDMA_REG_READ64(handle, TX_CS_REG, channel, &txcs.value); 206044961713Sgirish if (!txcs.bits.ldw.sng_state) { 206144961713Sgirish return (NPI_SUCCESS); 206244961713Sgirish } 206344961713Sgirish loop++; 206444961713Sgirish } while (loop < TXDMA_WAIT_LOOP); 206544961713Sgirish 206644961713Sgirish if (loop == TXDMA_WAIT_LOOP) { 206744961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 206844961713Sgirish "npi_txdma_control_resume_wait: sng_state not " 206944961713Sgirish "set to 0 txcs.bits 0x%llx", txcs.value)); 207044961713Sgirish return (NPI_FAILURE | NPI_TXDMA_RESUME_FAILED); 207144961713Sgirish } 207244961713Sgirish 207344961713Sgirish return (NPI_SUCCESS); 207444961713Sgirish } 2075