144961713Sgirish /*
244961713Sgirish * CDDL HEADER START
344961713Sgirish *
444961713Sgirish * The contents of this file are subject to the terms of the
544961713Sgirish * Common Development and Distribution License (the "License").
644961713Sgirish * You may not use this file except in compliance with the License.
744961713Sgirish *
844961713Sgirish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
944961713Sgirish * or http://www.opensolaris.org/os/licensing.
1044961713Sgirish * See the License for the specific language governing permissions
1144961713Sgirish * and limitations under the License.
1244961713Sgirish *
1344961713Sgirish * When distributing Covered Code, include this CDDL HEADER in each
1444961713Sgirish * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1544961713Sgirish * If applicable, add the following below this CDDL HEADER, with the
1644961713Sgirish * fields enclosed by brackets "[]" replaced with your own identifying
1744961713Sgirish * information: Portions Copyright [yyyy] [name of copyright owner]
1844961713Sgirish *
1944961713Sgirish * CDDL HEADER END
2044961713Sgirish */
2144961713Sgirish /*
22678453a8Sspeer * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
2344961713Sgirish * Use is subject to license terms.
2444961713Sgirish */
2544961713Sgirish
26a3c5bd6dSspeer #include <npi_txdma.h>
27678453a8Sspeer #include <npi_tx_rd64.h>
28678453a8Sspeer #include <npi_tx_wr64.h>
2944961713Sgirish
3044961713Sgirish #define TXDMA_WAIT_LOOP 10000
3144961713Sgirish #define TXDMA_WAIT_MSEC 5
3244961713Sgirish
3344961713Sgirish static npi_status_t npi_txdma_control_reset_wait(npi_handle_t handle,
34a3c5bd6dSspeer uint8_t channel);
3544961713Sgirish static npi_status_t npi_txdma_control_stop_wait(npi_handle_t handle,
36a3c5bd6dSspeer uint8_t channel);
3744961713Sgirish static npi_status_t npi_txdma_control_resume_wait(npi_handle_t handle,
38a3c5bd6dSspeer uint8_t channel);
3944961713Sgirish
4044961713Sgirish uint64_t tdc_dmc_offset[] = {
4144961713Sgirish TX_RNG_CFIG_REG,
4244961713Sgirish TX_RING_HDL_REG,
4344961713Sgirish TX_RING_KICK_REG,
4444961713Sgirish TX_ENT_MSK_REG,
4544961713Sgirish TX_CS_REG,
4644961713Sgirish TXDMA_MBH_REG,
4744961713Sgirish TXDMA_MBL_REG,
4844961713Sgirish TX_DMA_PRE_ST_REG,
4944961713Sgirish TX_RNG_ERR_LOGH_REG,
5044961713Sgirish TX_RNG_ERR_LOGL_REG,
5144961713Sgirish TDMC_INTR_DBG_REG,
5244961713Sgirish TX_CS_DBG_REG
5344961713Sgirish };
5444961713Sgirish
5544961713Sgirish const char *tdc_dmc_name[] = {
5644961713Sgirish "TX_RNG_CFIG_REG",
5744961713Sgirish "TX_RING_HDL_REG",
5844961713Sgirish "TX_RING_KICK_REG",
5944961713Sgirish "TX_ENT_MSK_REG",
6044961713Sgirish "TX_CS_REG",
6144961713Sgirish "TXDMA_MBH_REG",
6244961713Sgirish "TXDMA_MBL_REG",
6344961713Sgirish "TX_DMA_PRE_ST_REG",
6444961713Sgirish "TX_RNG_ERR_LOGH_REG",
6544961713Sgirish "TX_RNG_ERR_LOGL_REG",
6644961713Sgirish "TDMC_INTR_DBG_REG",
6744961713Sgirish "TX_CS_DBG_REG"
6844961713Sgirish };
6944961713Sgirish
7044961713Sgirish uint64_t tdc_fzc_offset [] = {
7144961713Sgirish TX_LOG_PAGE_VLD_REG,
7244961713Sgirish TX_LOG_PAGE_MASK1_REG,
7344961713Sgirish TX_LOG_PAGE_VAL1_REG,
7444961713Sgirish TX_LOG_PAGE_MASK2_REG,
7544961713Sgirish TX_LOG_PAGE_VAL2_REG,
7644961713Sgirish TX_LOG_PAGE_RELO1_REG,
7744961713Sgirish TX_LOG_PAGE_RELO2_REG,
7844961713Sgirish TX_LOG_PAGE_HDL_REG
7944961713Sgirish };
8044961713Sgirish
8144961713Sgirish const char *tdc_fzc_name [] = {
8244961713Sgirish "TX_LOG_PAGE_VLD_REG",
8344961713Sgirish "TX_LOG_PAGE_MASK1_REG",
8444961713Sgirish "TX_LOG_PAGE_VAL1_REG",
8544961713Sgirish "TX_LOG_PAGE_MASK2_REG",
8644961713Sgirish "TX_LOG_PAGE_VAL2_REG",
8744961713Sgirish "TX_LOG_PAGE_RELO1_REG",
8844961713Sgirish "TX_LOG_PAGE_RELO2_REG",
8944961713Sgirish "TX_LOG_PAGE_HDL_REG"
9044961713Sgirish };
9144961713Sgirish
9244961713Sgirish uint64_t tx_fzc_offset[] = {
9344961713Sgirish TX_ADDR_MD_REG,
9444961713Sgirish TDMC_INJ_PAR_ERR_REG,
9544961713Sgirish TDMC_DBG_SEL_REG,
96678453a8Sspeer TDMC_TRAINING_REG,
97678453a8Sspeer TXC_PORT_DMA_ENABLE_REG,
98678453a8Sspeer TXC_DMA_MAX_BURST_REG
9944961713Sgirish };
10044961713Sgirish
10144961713Sgirish const char *tx_fzc_name[] = {
10244961713Sgirish "TX_ADDR_MD_REG",
10344961713Sgirish "TDMC_INJ_PAR_ERR_REG",
10444961713Sgirish "TDMC_DBG_SEL_REG",
105678453a8Sspeer "TDMC_TRAINING_REG",
106678453a8Sspeer "TXC_PORT_DMA_ENABLE_REG",
107678453a8Sspeer "TXC_DMA_MAX_BURST_REG"
10844961713Sgirish };
10944961713Sgirish
110a3c5bd6dSspeer #define NUM_TDC_DMC_REGS (sizeof (tdc_dmc_offset) / sizeof (uint64_t))
111a3c5bd6dSspeer #define NUM_TX_FZC_REGS (sizeof (tx_fzc_offset) / sizeof (uint64_t))
112a3c5bd6dSspeer
11344961713Sgirish /*
11444961713Sgirish * npi_txdma_dump_tdc_regs
11544961713Sgirish * Dumps the contents of tdc csrs and fzc registers
11644961713Sgirish *
11744961713Sgirish * Input:
11844961713Sgirish * tdc: TX DMA number
11944961713Sgirish *
12044961713Sgirish * return:
12144961713Sgirish * NPI_SUCCESS
12244961713Sgirish * NPI_FAILURE
12344961713Sgirish * NPI_TXDMA_CHANNEL_INVALID
12444961713Sgirish *
12544961713Sgirish */
12644961713Sgirish npi_status_t
npi_txdma_dump_tdc_regs(npi_handle_t handle,uint8_t tdc)12744961713Sgirish npi_txdma_dump_tdc_regs(npi_handle_t handle, uint8_t tdc)
12844961713Sgirish {
12944961713Sgirish
13044961713Sgirish uint64_t value, offset;
131*86ef0a63SRichard Lowe int num_regs, i;
13244961713Sgirish
133a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(tdc));
13444961713Sgirish if (!TXDMA_CHANNEL_VALID(tdc)) {
13544961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
13652ccf843Smisaki "npi_txdma_dump_tdc_regs"
13752ccf843Smisaki " Invalid TDC number %d \n",
13852ccf843Smisaki tdc));
13944961713Sgirish
14044961713Sgirish return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(tdc));
14144961713Sgirish }
14244961713Sgirish
14344961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
14452ccf843Smisaki "\nTXDMA DMC Register Dump for Channel %d\n",
14552ccf843Smisaki tdc));
14644961713Sgirish
147a3c5bd6dSspeer num_regs = NUM_TDC_DMC_REGS;
14844961713Sgirish for (i = 0; i < num_regs; i++) {
14944961713Sgirish TXDMA_REG_READ64(handle, tdc_dmc_offset[i], tdc, &value);
15044961713Sgirish offset = NXGE_TXDMA_OFFSET(tdc_dmc_offset[i], handle.is_vraddr,
15152ccf843Smisaki tdc);
15244961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, "0x%08llx "
15352ccf843Smisaki "%s\t 0x%016llx \n",
15452ccf843Smisaki offset, tdc_dmc_name[i],
15552ccf843Smisaki value));
15644961713Sgirish }
15744961713Sgirish
15844961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
15952ccf843Smisaki "\n TXDMA Register Dump for Channel %d done\n", tdc));
16044961713Sgirish
16144961713Sgirish return (NPI_SUCCESS);
16244961713Sgirish }
16344961713Sgirish
16444961713Sgirish /*
16544961713Sgirish * npi_txdma_dump_fzc_regs
16644961713Sgirish * Dumps the contents of tdc csrs and fzc registers
16744961713Sgirish *
16844961713Sgirish * Input:
16944961713Sgirish * tdc: TX DMA number
17044961713Sgirish *
17144961713Sgirish * return:
17244961713Sgirish * NPI_SUCCESS
17344961713Sgirish * NPI_FAILURE
17444961713Sgirish * NPI_TXDMA_CHANNEL_INVALID
17544961713Sgirish *
17644961713Sgirish */
17744961713Sgirish npi_status_t
npi_txdma_dump_fzc_regs(npi_handle_t handle)17844961713Sgirish npi_txdma_dump_fzc_regs(npi_handle_t handle)
17944961713Sgirish {
18044961713Sgirish
18144961713Sgirish uint64_t value;
18244961713Sgirish int num_regs, i;
18344961713Sgirish
18444961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
18552ccf843Smisaki "\nFZC_DMC Common Register Dump\n"));
18644961713Sgirish
187a3c5bd6dSspeer num_regs = NUM_TX_FZC_REGS;
18844961713Sgirish for (i = 0; i < num_regs; i++) {
18944961713Sgirish NXGE_REG_RD64(handle, tx_fzc_offset[i], &value);
19044961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, "0x%08llx "
19152ccf843Smisaki "%s\t 0x%08llx \n",
19252ccf843Smisaki tx_fzc_offset[i],
19352ccf843Smisaki tx_fzc_name[i], value));
19444961713Sgirish }
19544961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
19652ccf843Smisaki "\n TXDMA FZC_DMC Register Dump Done \n"));
19744961713Sgirish
19844961713Sgirish return (NPI_SUCCESS);
19944961713Sgirish }
20044961713Sgirish
20144961713Sgirish npi_status_t
npi_txdma_tdc_regs_zero(npi_handle_t handle,uint8_t tdc)20244961713Sgirish npi_txdma_tdc_regs_zero(npi_handle_t handle, uint8_t tdc)
20344961713Sgirish {
20444961713Sgirish uint64_t value;
205*86ef0a63SRichard Lowe int num_regs, i;
20644961713Sgirish
207a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(tdc));
20844961713Sgirish if (!TXDMA_CHANNEL_VALID(tdc)) {
20944961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
21052ccf843Smisaki "npi_txdma_tdc_regs_zero"
21152ccf843Smisaki " InvaliInvalid TDC number %d \n",
21252ccf843Smisaki tdc));
21344961713Sgirish return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(tdc));
21444961713Sgirish }
21544961713Sgirish
21644961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
21752ccf843Smisaki "\nTXDMA DMC Register (zero) for Channel %d\n",
21852ccf843Smisaki tdc));
21944961713Sgirish
220a3c5bd6dSspeer num_regs = NUM_TDC_DMC_REGS;
22144961713Sgirish value = 0;
22244961713Sgirish for (i = 0; i < num_regs; i++) {
223adfcba55Sjoycey TXDMA_REG_WRITE64(handle, tdc_dmc_offset[i], tdc, value);
22444961713Sgirish }
22544961713Sgirish
22644961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
22752ccf843Smisaki "\nTXDMA FZC_DMC Register clear for Channel %d\n",
22852ccf843Smisaki tdc));
22944961713Sgirish
23044961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
23152ccf843Smisaki "\n TXDMA Register Clear to 0s for Channel %d done\n", tdc));
23244961713Sgirish
23344961713Sgirish return (NPI_SUCCESS);
23444961713Sgirish }
23544961713Sgirish
23644961713Sgirish /*
23744961713Sgirish * npi_txdma_address_mode32_set():
23844961713Sgirish * This function is called to only support 32 bit addressing.
23944961713Sgirish *
24044961713Sgirish * Parameters:
24144961713Sgirish * handle - NPI handle
24244961713Sgirish * mode_enable - B_TRUE (enable 32 bit mode)
24344961713Sgirish * B_FALSE (disable 32 bit mode)
24444961713Sgirish *
24544961713Sgirish * Return:
24644961713Sgirish * NPI_SUCCESS - If set is complete successfully.
24744961713Sgirish *
24844961713Sgirish * Error:
24944961713Sgirish * NONE
25044961713Sgirish */
25144961713Sgirish npi_status_t
npi_txdma_mode32_set(npi_handle_t handle,boolean_t mode_enable)25244961713Sgirish npi_txdma_mode32_set(npi_handle_t handle, boolean_t mode_enable)
25344961713Sgirish {
25444961713Sgirish tx_addr_md_t mode32;
25544961713Sgirish
25644961713Sgirish mode32.value = 0;
25744961713Sgirish if (mode_enable) {
25844961713Sgirish mode32.bits.ldw.mode32 = 1;
25944961713Sgirish } else {
26044961713Sgirish mode32.bits.ldw.mode32 = 0;
26144961713Sgirish }
26244961713Sgirish NXGE_REG_WR64(handle, TX_ADDR_MD_REG, mode32.value);
26344961713Sgirish
26444961713Sgirish return (NPI_SUCCESS);
26544961713Sgirish }
26644961713Sgirish
26744961713Sgirish /*
26844961713Sgirish * npi_txdma_log_page_set():
26944961713Sgirish * This function is called to configure a logical page
27044961713Sgirish * (valid bit, mask, value, relocation).
27144961713Sgirish *
27244961713Sgirish * Parameters:
27344961713Sgirish * handle - NPI handle
27444961713Sgirish * cfgp - pointer to NPI defined data structure:
27544961713Sgirish * - page valid
276*86ef0a63SRichard Lowe * - mask
27744961713Sgirish * - value
27844961713Sgirish * - relocation
27944961713Sgirish * channel - hardware TXDMA channel from 0 to 23.
28044961713Sgirish *
28144961713Sgirish * Return:
28244961713Sgirish * NPI_SUCCESS - If configurations are set successfully.
28344961713Sgirish *
28444961713Sgirish * Error:
28544961713Sgirish * NPI_FAILURE -
28644961713Sgirish * NPI_TXDMA_CHANNEL_INVALID -
28744961713Sgirish * NPI_TXDMA_FUNC_INVALID -
28844961713Sgirish * NPI_TXDMA_PAGE_INVALID -
28944961713Sgirish */
29044961713Sgirish npi_status_t
npi_txdma_log_page_set(npi_handle_t handle,uint8_t channel,p_dma_log_page_t cfgp)29144961713Sgirish npi_txdma_log_page_set(npi_handle_t handle, uint8_t channel,
292*86ef0a63SRichard Lowe p_dma_log_page_t cfgp)
29344961713Sgirish {
29444961713Sgirish log_page_vld_t vld;
29544961713Sgirish int status;
29644961713Sgirish uint64_t val;
29744961713Sgirish dma_log_page_t cfg;
29844961713Sgirish
29944961713Sgirish DMA_LOG_PAGE_FN_VALIDATE(channel, cfgp->page_num, cfgp->func_num,
30052ccf843Smisaki status);
30144961713Sgirish if (status) {
30244961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
30352ccf843Smisaki " npi_txdma_log_page_set"
30452ccf843Smisaki " npi_status <0x%x>", status));
30544961713Sgirish return (status);
30644961713Sgirish }
30744961713Sgirish
30844961713Sgirish TX_LOG_REG_WRITE64(handle, TX_LOG_PAGE_VLD_REG, channel, 0);
30944961713Sgirish TX_LOG_REG_READ64(handle, TX_LOG_PAGE_VLD_REG, channel, &val);
31044961713Sgirish
31144961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_TDC_CTL,
31252ccf843Smisaki "\n==> npi_txdma_log_page_set: WRITE 0 and "
31352ccf843Smisaki " READ back 0x%llx\n ", val));
31444961713Sgirish
31544961713Sgirish vld.value = 0;
31644961713Sgirish TX_LOG_REG_READ64(handle, TX_LOG_PAGE_VLD_REG, channel, &val);
31744961713Sgirish
31844961713Sgirish val &= 0x3;
31944961713Sgirish vld.value |= val;
32044961713Sgirish
32144961713Sgirish vld.value = 0;
32244961713Sgirish vld.bits.ldw.func = cfgp->func_num;
32344961713Sgirish
32444961713Sgirish if (!cfgp->page_num) {
32544961713Sgirish TX_LOG_REG_WRITE64(handle, TX_LOG_PAGE_MASK1_REG,
32652ccf843Smisaki channel, (cfgp->mask & DMA_LOG_PAGE_MASK_MASK));
32744961713Sgirish TX_LOG_REG_WRITE64(handle, TX_LOG_PAGE_VAL1_REG,
32852ccf843Smisaki channel, (cfgp->value & DMA_LOG_PAGE_VALUE_MASK));
32944961713Sgirish TX_LOG_REG_WRITE64(handle, TX_LOG_PAGE_RELO1_REG,
33052ccf843Smisaki channel, (cfgp->reloc & DMA_LOG_PAGE_RELO_MASK));
33144961713Sgirish } else {
33244961713Sgirish TX_LOG_REG_WRITE64(handle, TX_LOG_PAGE_MASK2_REG,
33352ccf843Smisaki channel, (cfgp->mask & DMA_LOG_PAGE_MASK_MASK));
33444961713Sgirish TX_LOG_REG_WRITE64(handle, TX_LOG_PAGE_VAL2_REG,
33552ccf843Smisaki channel, (cfgp->value & DMA_LOG_PAGE_VALUE_MASK));
33644961713Sgirish TX_LOG_REG_WRITE64(handle, TX_LOG_PAGE_RELO2_REG,
33752ccf843Smisaki channel, (cfgp->reloc & DMA_LOG_PAGE_RELO_MASK));
33844961713Sgirish }
33944961713Sgirish
34044961713Sgirish TX_LOG_REG_WRITE64(handle, TX_LOG_PAGE_VLD_REG, channel,
34152ccf843Smisaki vld.value | (cfgp->valid << cfgp->page_num));
34244961713Sgirish
34344961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_REG_CTL,
34452ccf843Smisaki "\n==> npi_txdma_log_page_set: vld value "
34552ccf843Smisaki " 0x%llx function %d page_valid01 0x%x\n",
34652ccf843Smisaki vld.value,
34752ccf843Smisaki vld.bits.ldw.func,
34852ccf843Smisaki (cfgp->valid << cfgp->page_num)));
34944961713Sgirish
35044961713Sgirish
35144961713Sgirish cfg.page_num = 0;
35244961713Sgirish cfg.func_num = 0;
35344961713Sgirish (void) npi_txdma_log_page_get(handle, channel, &cfg);
35444961713Sgirish cfg.page_num = 1;
35544961713Sgirish (void) npi_txdma_log_page_get(handle, channel, &cfg);
35644961713Sgirish
35744961713Sgirish return (status);
35844961713Sgirish }
35944961713Sgirish
36044961713Sgirish /*
36144961713Sgirish * npi_txdma_log_page_get():
36244961713Sgirish * This function is called to get a logical page
36344961713Sgirish * (valid bit, mask, value, relocation).
36444961713Sgirish *
36544961713Sgirish * Parameters:
36644961713Sgirish * handle - NPI handle
36744961713Sgirish * cfgp - Get the following values (NPI defined structure):
36844961713Sgirish * - page valid
369*86ef0a63SRichard Lowe * - mask
37044961713Sgirish * - value
37144961713Sgirish * - relocation
37244961713Sgirish * channel - hardware TXDMA channel from 0 to 23.
37344961713Sgirish *
37444961713Sgirish * Return:
37544961713Sgirish * NPI_SUCCESS - If configurations are read successfully.
37644961713Sgirish *
37744961713Sgirish * Error:
37844961713Sgirish * NPI_FAILURE -
37944961713Sgirish * NPI_TXDMA_CHANNEL_INVALID -
38044961713Sgirish * NPI_TXDMA_FUNC_INVALID -
38144961713Sgirish * NPI_TXDMA_PAGE_INVALID -
38244961713Sgirish */
38344961713Sgirish npi_status_t
npi_txdma_log_page_get(npi_handle_t handle,uint8_t channel,p_dma_log_page_t cfgp)38444961713Sgirish npi_txdma_log_page_get(npi_handle_t handle, uint8_t channel,
385*86ef0a63SRichard Lowe p_dma_log_page_t cfgp)
38644961713Sgirish {
38744961713Sgirish log_page_vld_t vld;
38844961713Sgirish int status;
38944961713Sgirish uint64_t val;
39044961713Sgirish
39144961713Sgirish DMA_LOG_PAGE_VALIDATE(channel, cfgp->page_num, status);
39244961713Sgirish if (status) {
39344961713Sgirish NPI_ERROR_MSG((handle.function, NPI_REG_CTL,
39452ccf843Smisaki " npi_txdma_log_page_get"
39552ccf843Smisaki " npi_status <0x%x>", status));
39644961713Sgirish return (status);
39744961713Sgirish }
39844961713Sgirish
39944961713Sgirish vld.value = 0;
40044961713Sgirish vld.bits.ldw.func = cfgp->func_num;
40144961713Sgirish TX_LOG_REG_READ64(handle, TX_LOG_PAGE_VLD_REG, channel, &val);
40244961713Sgirish
40344961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_TDC_CTL,
40452ccf843Smisaki "\n==> npi_txdma_log_page_get: read value "
40552ccf843Smisaki " function %d value 0x%llx\n",
40652ccf843Smisaki cfgp->func_num, val));
40744961713Sgirish
40844961713Sgirish vld.value |= val;
40944961713Sgirish cfgp->func_num = vld.bits.ldw.func;
41044961713Sgirish
41144961713Sgirish if (!cfgp->page_num) {
41244961713Sgirish TX_LOG_REG_READ64(handle, TX_LOG_PAGE_MASK1_REG, channel, &val);
41344961713Sgirish cfgp->mask = val & DMA_LOG_PAGE_MASK_MASK;
41444961713Sgirish TX_LOG_REG_READ64(handle, TX_LOG_PAGE_VAL1_REG, channel, &val);
41544961713Sgirish cfgp->value = val & DMA_LOG_PAGE_VALUE_MASK;
41644961713Sgirish TX_LOG_REG_READ64(handle, TX_LOG_PAGE_RELO1_REG, channel, &val);
41744961713Sgirish cfgp->reloc = val & DMA_LOG_PAGE_RELO_MASK;
41844961713Sgirish cfgp->valid = vld.bits.ldw.page0;
41944961713Sgirish } else {
42044961713Sgirish TX_LOG_REG_READ64(handle, TX_LOG_PAGE_MASK2_REG, channel, &val);
42144961713Sgirish cfgp->mask = val & DMA_LOG_PAGE_MASK_MASK;
42244961713Sgirish TX_LOG_REG_READ64(handle, TX_LOG_PAGE_VAL2_REG, channel, &val);
42344961713Sgirish cfgp->value = val & DMA_LOG_PAGE_VALUE_MASK;
42444961713Sgirish TX_LOG_REG_READ64(handle, TX_LOG_PAGE_RELO2_REG, channel, &val);
42544961713Sgirish cfgp->reloc = val & DMA_LOG_PAGE_RELO_MASK;
42644961713Sgirish cfgp->valid = vld.bits.ldw.page1;
42744961713Sgirish }
42844961713Sgirish
42944961713Sgirish return (status);
43044961713Sgirish }
43144961713Sgirish
43244961713Sgirish /*
43344961713Sgirish * npi_txdma_log_page_handle_set():
43444961713Sgirish * This function is called to program a page handle
43544961713Sgirish * (bits [63:44] of a 64-bit address to generate
43644961713Sgirish * a 64 bit address)
43744961713Sgirish *
43844961713Sgirish * Parameters:
43944961713Sgirish * handle - NPI handle
44044961713Sgirish * hdl_p - pointer to a logical page handle
44144961713Sgirish * hardware data structure (log_page_hdl_t).
44244961713Sgirish * channel - hardware TXDMA channel from 0 to 23.
44344961713Sgirish *
44444961713Sgirish * Return:
44544961713Sgirish * NPI_SUCCESS - If configurations are set successfully.
44644961713Sgirish *
44744961713Sgirish * Error:
44844961713Sgirish * NPI_FAILURE -
44944961713Sgirish * NPI_TXDMA_CHANNEL_INVALID -
45044961713Sgirish * NPI_TXDMA_FUNC_INVALID -
45144961713Sgirish * NPI_TXDMA_PAGE_INVALID -
45244961713Sgirish */
45344961713Sgirish npi_status_t
npi_txdma_log_page_handle_set(npi_handle_t handle,uint8_t channel,p_log_page_hdl_t hdl_p)45444961713Sgirish npi_txdma_log_page_handle_set(npi_handle_t handle, uint8_t channel,
455*86ef0a63SRichard Lowe p_log_page_hdl_t hdl_p)
45644961713Sgirish {
45744961713Sgirish int status = NPI_SUCCESS;
45844961713Sgirish
459a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(channel));
46044961713Sgirish if (!TXDMA_CHANNEL_VALID(channel)) {
46144961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
46252ccf843Smisaki " npi_txdma_log_page_handle_set"
46352ccf843Smisaki " Invalid Input: channel <0x%x>",
46452ccf843Smisaki channel));
46544961713Sgirish return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel));
46644961713Sgirish }
46744961713Sgirish
46844961713Sgirish TX_LOG_REG_WRITE64(handle, TX_LOG_PAGE_HDL_REG,
46952ccf843Smisaki channel, hdl_p->value);
47044961713Sgirish
47144961713Sgirish return (status);
47244961713Sgirish }
47344961713Sgirish
47444961713Sgirish /*
47544961713Sgirish * npi_txdma_log_page_config():
47644961713Sgirish * This function is called to IO operations on
47744961713Sgirish * a logical page to set, get, clear
47844961713Sgirish * valid bit, mask, value, relocation).
47944961713Sgirish *
48044961713Sgirish * Parameters:
48144961713Sgirish * handle - NPI handle
48244961713Sgirish * op_mode - OP_GET, OP_SET, OP_CLEAR
48344961713Sgirish * type - NPI specific config type
48444961713Sgirish * TXDMA_LOG_PAGE_MASK
48544961713Sgirish * TXDMA_LOG_PAGE_VALUE
48644961713Sgirish * TXDMA_LOG_PAGE_RELOC
48744961713Sgirish * TXDMA_LOG_PAGE_VALID
48844961713Sgirish * TXDMA_LOG_PAGE_ALL
48944961713Sgirish * channel - hardware TXDMA channel from 0 to 23.
49044961713Sgirish * cfgp - pointer to the NPI config structure.
49144961713Sgirish * Return:
49244961713Sgirish * NPI_SUCCESS - If configurations are read successfully.
49344961713Sgirish *
49444961713Sgirish * Error:
49544961713Sgirish * NPI_FAILURE -
49644961713Sgirish * NPI_TXDMA_OPCODE_INVALID -
49744961713Sgirish * NPI_TXDMA_CHANNEL_INVALID -
49844961713Sgirish * NPI_TXDMA_FUNC_INVALID -
49944961713Sgirish * NPI_TXDMA_PAGE_INVALID -
50044961713Sgirish */
50144961713Sgirish npi_status_t
npi_txdma_log_page_config(npi_handle_t handle,io_op_t op_mode,txdma_log_cfg_t type,uint8_t channel,p_dma_log_page_t cfgp)50244961713Sgirish npi_txdma_log_page_config(npi_handle_t handle, io_op_t op_mode,
503*86ef0a63SRichard Lowe txdma_log_cfg_t type, uint8_t channel,
504*86ef0a63SRichard Lowe p_dma_log_page_t cfgp)
50544961713Sgirish {
50644961713Sgirish int status = NPI_SUCCESS;
50744961713Sgirish uint64_t val;
50844961713Sgirish
509a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(channel));
51044961713Sgirish if (!TXDMA_CHANNEL_VALID(channel)) {
51144961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
51252ccf843Smisaki " npi_txdma_log_page_config"
51352ccf843Smisaki " Invalid Input: channel <0x%x>",
51452ccf843Smisaki channel));
51544961713Sgirish return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel));
51644961713Sgirish }
51744961713Sgirish
51844961713Sgirish switch (op_mode) {
51944961713Sgirish case OP_GET:
52044961713Sgirish switch (type) {
52144961713Sgirish case TXDMA_LOG_PAGE_ALL:
52244961713Sgirish return (npi_txdma_log_page_get(handle, channel,
52352ccf843Smisaki cfgp));
52444961713Sgirish case TXDMA_LOG_PAGE_MASK:
52544961713Sgirish if (!cfgp->page_num) {
52644961713Sgirish TX_LOG_REG_READ64(handle, TX_LOG_PAGE_MASK1_REG,
52752ccf843Smisaki channel, &val);
52844961713Sgirish cfgp->mask = val & DMA_LOG_PAGE_MASK_MASK;
52944961713Sgirish } else {
53044961713Sgirish TX_LOG_REG_READ64(handle, TX_LOG_PAGE_MASK2_REG,
53152ccf843Smisaki channel, &val);
53244961713Sgirish cfgp->mask = val & DMA_LOG_PAGE_MASK_MASK;
53344961713Sgirish }
53444961713Sgirish break;
53544961713Sgirish
53644961713Sgirish case TXDMA_LOG_PAGE_VALUE:
53744961713Sgirish if (!cfgp->page_num) {
53844961713Sgirish TX_LOG_REG_READ64(handle, TX_LOG_PAGE_VAL1_REG,
53952ccf843Smisaki channel, &val);
54044961713Sgirish cfgp->value = val & DMA_LOG_PAGE_VALUE_MASK;
54144961713Sgirish } else {
54244961713Sgirish TX_LOG_REG_READ64(handle, TX_LOG_PAGE_VAL2_REG,
54352ccf843Smisaki channel, &val);
54444961713Sgirish cfgp->value = val & DMA_LOG_PAGE_VALUE_MASK;
54544961713Sgirish }
54644961713Sgirish break;
54744961713Sgirish
54844961713Sgirish case TXDMA_LOG_PAGE_RELOC:
54944961713Sgirish if (!cfgp->page_num) {
55044961713Sgirish TX_LOG_REG_READ64(handle, TX_LOG_PAGE_RELO1_REG,
55152ccf843Smisaki channel, &val);
55244961713Sgirish cfgp->reloc = val & DMA_LOG_PAGE_RELO_MASK;
55344961713Sgirish } else {
55444961713Sgirish TX_LOG_REG_READ64(handle, TX_LOG_PAGE_VAL2_REG,
55552ccf843Smisaki channel, &val);
55644961713Sgirish cfgp->reloc = val & DMA_LOG_PAGE_RELO_MASK;
55744961713Sgirish }
55844961713Sgirish break;
55944961713Sgirish
56044961713Sgirish default:
56144961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
56252ccf843Smisaki " npi_txdma_log_page_config"
56352ccf843Smisaki " Invalid Input: pageconfig <0x%x>",
56452ccf843Smisaki type));
56544961713Sgirish return (NPI_FAILURE |
56652ccf843Smisaki NPI_TXDMA_OPCODE_INVALID(channel));
56744961713Sgirish }
56844961713Sgirish
56944961713Sgirish break;
57044961713Sgirish
57144961713Sgirish case OP_SET:
57244961713Sgirish case OP_CLEAR:
57344961713Sgirish if (op_mode == OP_CLEAR) {
57444961713Sgirish cfgp->valid = 0;
57544961713Sgirish cfgp->mask = cfgp->func_num = 0;
57644961713Sgirish cfgp->value = cfgp->reloc = 0;
57744961713Sgirish }
57844961713Sgirish switch (type) {
57944961713Sgirish case TXDMA_LOG_PAGE_ALL:
58044961713Sgirish return (npi_txdma_log_page_set(handle, channel,
58152ccf843Smisaki cfgp));
58244961713Sgirish case TXDMA_LOG_PAGE_MASK:
58344961713Sgirish if (!cfgp->page_num) {
58444961713Sgirish TX_LOG_REG_WRITE64(handle,
58552ccf843Smisaki TX_LOG_PAGE_MASK1_REG, channel,
58652ccf843Smisaki (cfgp->mask & DMA_LOG_PAGE_MASK_MASK));
58744961713Sgirish } else {
58844961713Sgirish TX_LOG_REG_WRITE64(handle,
58952ccf843Smisaki TX_LOG_PAGE_MASK2_REG, channel,
59052ccf843Smisaki (cfgp->mask & DMA_LOG_PAGE_MASK_MASK));
59144961713Sgirish }
59244961713Sgirish break;
59344961713Sgirish
59444961713Sgirish case TXDMA_LOG_PAGE_VALUE:
59544961713Sgirish if (!cfgp->page_num) {
59644961713Sgirish TX_LOG_REG_WRITE64(handle,
59752ccf843Smisaki TX_LOG_PAGE_VAL1_REG, channel,
59852ccf843Smisaki (cfgp->value & DMA_LOG_PAGE_VALUE_MASK));
59944961713Sgirish } else {
60044961713Sgirish TX_LOG_REG_WRITE64(handle,
60152ccf843Smisaki TX_LOG_PAGE_VAL2_REG, channel,
60252ccf843Smisaki (cfgp->value & DMA_LOG_PAGE_VALUE_MASK));
60344961713Sgirish }
60444961713Sgirish break;
60544961713Sgirish
60644961713Sgirish case TXDMA_LOG_PAGE_RELOC:
60744961713Sgirish if (!cfgp->page_num) {
60844961713Sgirish TX_LOG_REG_WRITE64(handle,
60952ccf843Smisaki TX_LOG_PAGE_RELO1_REG, channel,
61052ccf843Smisaki (cfgp->reloc & DMA_LOG_PAGE_RELO_MASK));
61144961713Sgirish } else {
61244961713Sgirish TX_LOG_REG_WRITE64(handle,
61352ccf843Smisaki TX_LOG_PAGE_RELO2_REG, channel,
61452ccf843Smisaki (cfgp->reloc & DMA_LOG_PAGE_RELO_MASK));
61544961713Sgirish }
61644961713Sgirish break;
61744961713Sgirish
61844961713Sgirish default:
61944961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
62052ccf843Smisaki " npi_txdma_log_page_config"
62152ccf843Smisaki " Invalid Input: pageconfig <0x%x>",
62252ccf843Smisaki type));
62344961713Sgirish return (NPI_FAILURE |
62452ccf843Smisaki NPI_TXDMA_OPCODE_INVALID(channel));
62544961713Sgirish }
62644961713Sgirish
62744961713Sgirish break;
62844961713Sgirish default:
62944961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
63052ccf843Smisaki " npi_txdma_log_page_config"
63152ccf843Smisaki " Invalid Input: op <0x%x>",
63252ccf843Smisaki op_mode));
63344961713Sgirish return (NPI_FAILURE | NPI_TXDMA_OPCODE_INVALID(channel));
63444961713Sgirish }
63544961713Sgirish
63644961713Sgirish return (status);
63744961713Sgirish }
63844961713Sgirish
63944961713Sgirish /*
64044961713Sgirish * npi_txdma_log_page_vld_config():
64144961713Sgirish * This function is called to configure the logical
64244961713Sgirish * page valid register.
64344961713Sgirish *
64444961713Sgirish * Parameters:
64544961713Sgirish * handle - NPI handle
64644961713Sgirish * op_mode - OP_GET: get valid page configuration
64744961713Sgirish * OP_SET: set valid page configuration
64844961713Sgirish * OP_UPDATE: update valid page configuration
64944961713Sgirish * OP_CLEAR: reset both valid pages to
65044961713Sgirish * not defined (0).
65144961713Sgirish * channel - hardware TXDMA channel from 0 to 23.
65244961713Sgirish * vld_p - pointer to hardware defined log page valid register.
65344961713Sgirish * Return:
65444961713Sgirish * NPI_SUCCESS - If set is complete successfully.
65544961713Sgirish *
65644961713Sgirish * Error:
65744961713Sgirish * NPI_FAILURE -
65844961713Sgirish * NPI_TXDMA_CHANNEL_INVALID -
65944961713Sgirish * NPI_TXDMA_OPCODE_INVALID -
66044961713Sgirish */
66144961713Sgirish npi_status_t
npi_txdma_log_page_vld_config(npi_handle_t handle,io_op_t op_mode,uint8_t channel,p_log_page_vld_t vld_p)66244961713Sgirish npi_txdma_log_page_vld_config(npi_handle_t handle, io_op_t op_mode,
663*86ef0a63SRichard Lowe uint8_t channel, p_log_page_vld_t vld_p)
66444961713Sgirish {
66544961713Sgirish int status = NPI_SUCCESS;
66644961713Sgirish log_page_vld_t vld;
66744961713Sgirish
668a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(channel));
66944961713Sgirish if (!TXDMA_CHANNEL_VALID(channel)) {
67044961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
67152ccf843Smisaki " npi_txdma_log_page_vld_config"
67252ccf843Smisaki " Invalid Input: channel <0x%x>",
67352ccf843Smisaki channel));
67444961713Sgirish return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel));
67544961713Sgirish }
67644961713Sgirish
67744961713Sgirish switch (op_mode) {
67844961713Sgirish case OP_GET:
67944961713Sgirish TX_LOG_REG_READ64(handle, TX_LOG_PAGE_VLD_REG, channel,
68052ccf843Smisaki &vld_p->value);
68144961713Sgirish break;
68244961713Sgirish
68344961713Sgirish case OP_SET:
68444961713Sgirish TX_LOG_REG_WRITE64(handle, TX_LOG_PAGE_VLD_REG,
68552ccf843Smisaki channel, vld_p->value);
68644961713Sgirish break;
68744961713Sgirish
68844961713Sgirish case OP_UPDATE:
68944961713Sgirish TX_LOG_REG_READ64(handle, TX_LOG_PAGE_VLD_REG, channel,
69052ccf843Smisaki &vld.value);
69144961713Sgirish TX_LOG_REG_WRITE64(handle, TX_LOG_PAGE_VLD_REG,
69252ccf843Smisaki channel, vld.value | vld_p->value);
69344961713Sgirish break;
69444961713Sgirish
69544961713Sgirish case OP_CLEAR:
69644961713Sgirish TX_LOG_REG_WRITE64(handle, TX_LOG_PAGE_VLD_REG,
69752ccf843Smisaki channel, 0);
69844961713Sgirish break;
69944961713Sgirish
70044961713Sgirish default:
70144961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
70252ccf843Smisaki " npi_txdma_log_pag_vld_cofig"
70352ccf843Smisaki " Invalid Input: pagevld <0x%x>",
70452ccf843Smisaki op_mode));
70544961713Sgirish return (NPI_FAILURE | NPI_TXDMA_OPCODE_INVALID(channel));
70644961713Sgirish }
70744961713Sgirish
70844961713Sgirish return (status);
70944961713Sgirish }
71044961713Sgirish
71144961713Sgirish /*
71244961713Sgirish * npi_txdma_channel_reset():
71344961713Sgirish * This function is called to reset a transmit DMA channel.
71444961713Sgirish * (This function is used to reset a channel and reinitialize
71544961713Sgirish * all other bits except RST_STATE).
71644961713Sgirish *
71744961713Sgirish * Parameters:
71844961713Sgirish * handle - NPI handle (virtualization flag must be defined).
71944961713Sgirish * channel - logical TXDMA channel from 0 to 23.
72044961713Sgirish * (If virtualization flag is not set, then
72144961713Sgirish * logical channel is the same as the hardware
72244961713Sgirish * channel number).
72344961713Sgirish *
72444961713Sgirish * Return:
72544961713Sgirish * NPI_SUCCESS - If reset is complete successfully.
72644961713Sgirish *
72744961713Sgirish * Error:
72844961713Sgirish * NPI_FAILURE -
72944961713Sgirish * NPI_TXDMA_CHANNEL_INVALID -
73044961713Sgirish * NPI_TXDMA_RESET_FAILED -
73144961713Sgirish */
73244961713Sgirish npi_status_t
npi_txdma_channel_reset(npi_handle_t handle,uint8_t channel)73344961713Sgirish npi_txdma_channel_reset(npi_handle_t handle, uint8_t channel)
73444961713Sgirish {
73544961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_TDC_CTL,
73652ccf843Smisaki " npi_txdma_channel_reset"
73752ccf843Smisaki " RESETTING",
73852ccf843Smisaki channel));
73944961713Sgirish return (npi_txdma_channel_control(handle, TXDMA_RESET, channel));
74044961713Sgirish }
74144961713Sgirish
74244961713Sgirish /*
74344961713Sgirish * npi_txdma_channel_init_enable():
74444961713Sgirish * This function is called to start a transmit DMA channel after reset.
74544961713Sgirish *
74644961713Sgirish * Parameters:
74744961713Sgirish * handle - NPI handle (virtualization flag must be defined).
74844961713Sgirish * channel - logical TXDMA channel from 0 to 23.
74944961713Sgirish * (If virtualization flag is not set, then
75044961713Sgirish * logical channel is the same as the hardware
75144961713Sgirish * channel number).
75244961713Sgirish * Return:
75344961713Sgirish * NPI_SUCCESS - If DMA channel is started successfully.
75444961713Sgirish *
75544961713Sgirish * Error:
75644961713Sgirish * NPI_FAILURE -
75744961713Sgirish * NPI_TXDMA_CHANNEL_INVALID -
75844961713Sgirish */
75944961713Sgirish npi_status_t
npi_txdma_channel_init_enable(npi_handle_t handle,uint8_t channel)76044961713Sgirish npi_txdma_channel_init_enable(npi_handle_t handle, uint8_t channel)
76144961713Sgirish {
76244961713Sgirish return (npi_txdma_channel_control(handle, TXDMA_INIT_START, channel));
76344961713Sgirish }
76444961713Sgirish
76544961713Sgirish /*
76644961713Sgirish * npi_txdma_channel_enable():
76744961713Sgirish * This function is called to start a transmit DMA channel.
76844961713Sgirish *
76944961713Sgirish * Parameters:
77044961713Sgirish * handle - NPI handle (virtualization flag must be defined).
77144961713Sgirish * channel - logical TXDMA channel from 0 to 23.
77244961713Sgirish * (If virtualization flag is not set, then
77344961713Sgirish * logical channel is the same as the hardware
77444961713Sgirish * channel number).
77544961713Sgirish * Return:
77644961713Sgirish * NPI_SUCCESS - If DMA channel is stopped successfully.
77744961713Sgirish *
77844961713Sgirish * Error:
77944961713Sgirish * NPI_FAILURE -
78044961713Sgirish * NPI_TXDMA_CHANNEL_INVALID -
78144961713Sgirish */
78244961713Sgirish
78344961713Sgirish npi_status_t
npi_txdma_channel_enable(npi_handle_t handle,uint8_t channel)78444961713Sgirish npi_txdma_channel_enable(npi_handle_t handle, uint8_t channel)
78544961713Sgirish {
78644961713Sgirish return (npi_txdma_channel_control(handle, TXDMA_START, channel));
78744961713Sgirish }
78844961713Sgirish
78944961713Sgirish /*
79044961713Sgirish * npi_txdma_channel_disable():
79144961713Sgirish * This function is called to stop a transmit DMA channel.
79244961713Sgirish *
79344961713Sgirish * Parameters:
79444961713Sgirish * handle - NPI handle (virtualization flag must be defined).
79544961713Sgirish * channel - logical TXDMA channel from 0 to 23.
79644961713Sgirish * (If virtualization flag is not set, then
79744961713Sgirish * logical channel is the same as the hardware
79844961713Sgirish * channel number).
79944961713Sgirish * Return:
80044961713Sgirish * NPI_SUCCESS - If DMA channel is stopped successfully.
80144961713Sgirish *
80244961713Sgirish * Error:
80344961713Sgirish * NPI_FAILURE -
80444961713Sgirish * NPI_TXDMA_CHANNEL_INVALID -
80544961713Sgirish * NPI_TXDMA_STOP_FAILED -
80644961713Sgirish */
80744961713Sgirish npi_status_t
npi_txdma_channel_disable(npi_handle_t handle,uint8_t channel)80844961713Sgirish npi_txdma_channel_disable(npi_handle_t handle, uint8_t channel)
80944961713Sgirish {
81044961713Sgirish return (npi_txdma_channel_control(handle, TXDMA_STOP, channel));
81144961713Sgirish }
81244961713Sgirish
81344961713Sgirish /*
81444961713Sgirish * npi_txdma_channel_resume():
81544961713Sgirish * This function is called to restart a transmit DMA channel.
81644961713Sgirish *
81744961713Sgirish * Parameters:
81844961713Sgirish * handle - NPI handle (virtualization flag must be defined).
81944961713Sgirish * channel - logical TXDMA channel from 0 to 23.
82044961713Sgirish * (If virtualization flag is not set, then
82144961713Sgirish * logical channel is the same as the hardware
82244961713Sgirish * channel number).
82344961713Sgirish * Return:
82444961713Sgirish * NPI_SUCCESS - If DMA channel is stopped successfully.
82544961713Sgirish *
82644961713Sgirish * Error:
82744961713Sgirish * NPI_FAILURE -
82844961713Sgirish * NPI_TXDMA_CHANNEL_INVALID -
82944961713Sgirish * NPI_TXDMA_RESUME_FAILED -
83044961713Sgirish */
83144961713Sgirish npi_status_t
npi_txdma_channel_resume(npi_handle_t handle,uint8_t channel)83244961713Sgirish npi_txdma_channel_resume(npi_handle_t handle, uint8_t channel)
83344961713Sgirish {
83444961713Sgirish return (npi_txdma_channel_control(handle, TXDMA_RESUME, channel));
83544961713Sgirish }
83644961713Sgirish
83744961713Sgirish /*
83844961713Sgirish * npi_txdma_channel_mmk_clear():
83944961713Sgirish * This function is called to clear MMK bit.
84044961713Sgirish *
84144961713Sgirish * Parameters:
84244961713Sgirish * handle - NPI handle (virtualization flag must be defined).
84344961713Sgirish * channel - logical TXDMA channel from 0 to 23.
84444961713Sgirish * (If virtualization flag is not set, then
84544961713Sgirish * logical channel is the same as the hardware
84644961713Sgirish * channel number).
84744961713Sgirish * Return:
84844961713Sgirish * NPI_SUCCESS - If MMK is reset successfully.
84944961713Sgirish *
85044961713Sgirish * Error:
85144961713Sgirish * NPI_FAILURE -
85244961713Sgirish * NPI_TXDMA_CHANNEL_INVALID -
85344961713Sgirish */
85444961713Sgirish npi_status_t
npi_txdma_channel_mmk_clear(npi_handle_t handle,uint8_t channel)85544961713Sgirish npi_txdma_channel_mmk_clear(npi_handle_t handle, uint8_t channel)
85644961713Sgirish {
85744961713Sgirish return (npi_txdma_channel_control(handle, TXDMA_CLEAR_MMK, channel));
85844961713Sgirish }
85944961713Sgirish
86044961713Sgirish /*
86144961713Sgirish * npi_txdma_channel_mbox_enable():
86244961713Sgirish * This function is called to enable the mailbox update.
86344961713Sgirish *
86444961713Sgirish * Parameters:
86544961713Sgirish * handle - NPI handle (virtualization flag must be defined).
86644961713Sgirish * channel - logical TXDMA channel from 0 to 23.
86744961713Sgirish * (If virtualization flag is not set, then
86844961713Sgirish * logical channel is the same as the hardware
86944961713Sgirish * channel number).
87044961713Sgirish * Return:
87144961713Sgirish * NPI_SUCCESS - If mailbox is enabled successfully.
87244961713Sgirish *
87344961713Sgirish * Error:
87444961713Sgirish * NPI_HW_ERROR -
87544961713Sgirish * NPI_FAILURE -
87644961713Sgirish * NPI_TXDMA_CHANNEL_INVALID -
87744961713Sgirish */
87844961713Sgirish npi_status_t
npi_txdma_channel_mbox_enable(npi_handle_t handle,uint8_t channel)87944961713Sgirish npi_txdma_channel_mbox_enable(npi_handle_t handle, uint8_t channel)
88044961713Sgirish {
88144961713Sgirish return (npi_txdma_channel_control(handle, TXDMA_MBOX_ENABLE, channel));
88244961713Sgirish }
88344961713Sgirish
88444961713Sgirish /*
88544961713Sgirish * npi_txdma_channel_control():
88644961713Sgirish * This function is called to control a transmit DMA channel
88744961713Sgirish * for reset, start or stop.
88844961713Sgirish *
88944961713Sgirish * Parameters:
89044961713Sgirish * handle - NPI handle (virtualization flag must be defined).
89144961713Sgirish * control - NPI defined control type supported
89244961713Sgirish * - TXDMA_INIT_RESET
893*86ef0a63SRichard Lowe * - TXDMA_INIT_START
89444961713Sgirish * - TXDMA_RESET
89544961713Sgirish * - TXDMA_START
89644961713Sgirish * - TXDMA_STOP
89744961713Sgirish * channel - logical TXDMA channel from 0 to 23.
89844961713Sgirish * (If virtualization flag is not set, then
89944961713Sgirish * logical channel is the same as the hardware
90044961713Sgirish *
90144961713Sgirish * Return:
90244961713Sgirish * NPI_SUCCESS - If reset is complete successfully.
90344961713Sgirish *
90444961713Sgirish * Error:
90544961713Sgirish * NPI_FAILURE -
90644961713Sgirish * NPI_TXDMA_OPCODE_INVALID -
90744961713Sgirish * NPI_TXDMA_CHANNEL_INVALID -
90844961713Sgirish * NPI_TXDMA_RESET_FAILED -
90944961713Sgirish * NPI_TXDMA_STOP_FAILED -
91044961713Sgirish * NPI_TXDMA_RESUME_FAILED -
91144961713Sgirish */
91244961713Sgirish npi_status_t
npi_txdma_channel_control(npi_handle_t handle,txdma_cs_cntl_t control,uint8_t channel)91344961713Sgirish npi_txdma_channel_control(npi_handle_t handle, txdma_cs_cntl_t control,
914*86ef0a63SRichard Lowe uint8_t channel)
91544961713Sgirish {
91644961713Sgirish int status = NPI_SUCCESS;
91744961713Sgirish tx_cs_t cs;
91844961713Sgirish
919a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(channel));
92044961713Sgirish if (!TXDMA_CHANNEL_VALID(channel)) {
92144961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
92252ccf843Smisaki " npi_txdma_channel_control"
92352ccf843Smisaki " Invalid Input: channel <0x%x>",
92452ccf843Smisaki channel));
92544961713Sgirish return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel));
92644961713Sgirish }
92744961713Sgirish
92844961713Sgirish switch (control) {
92944961713Sgirish case TXDMA_INIT_RESET:
93044961713Sgirish cs.value = 0;
93144961713Sgirish TXDMA_REG_READ64(handle, TX_CS_REG, channel, &cs.value);
93244961713Sgirish cs.bits.ldw.rst = 1;
93344961713Sgirish TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs.value);
93444961713Sgirish return (npi_txdma_control_reset_wait(handle, channel));
93544961713Sgirish
93644961713Sgirish case TXDMA_INIT_START:
93744961713Sgirish cs.value = 0;
93844961713Sgirish TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs.value);
93944961713Sgirish break;
94044961713Sgirish
94144961713Sgirish case TXDMA_RESET:
94244961713Sgirish /*
94344961713Sgirish * Sets reset bit only (Hardware will reset all
94444961713Sgirish * the RW bits but leave the RO bits alone.
94544961713Sgirish */
94644961713Sgirish cs.value = 0;
94744961713Sgirish cs.bits.ldw.rst = 1;
94844961713Sgirish TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs.value);
94944961713Sgirish return (npi_txdma_control_reset_wait(handle, channel));
95044961713Sgirish
95144961713Sgirish case TXDMA_START:
95244961713Sgirish /* Enable the DMA channel */
95344961713Sgirish TXDMA_REG_READ64(handle, TX_CS_REG, channel, &cs.value);
95444961713Sgirish cs.bits.ldw.stop_n_go = 0;
95544961713Sgirish TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs.value);
95644961713Sgirish break;
95744961713Sgirish
95844961713Sgirish case TXDMA_STOP:
95944961713Sgirish /* Disable the DMA channel */
96044961713Sgirish TXDMA_REG_READ64(handle, TX_CS_REG, channel, &cs.value);
96144961713Sgirish cs.bits.ldw.stop_n_go = 1;
96244961713Sgirish TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs.value);
96344961713Sgirish status = npi_txdma_control_stop_wait(handle, channel);
96444961713Sgirish if (status) {
96544961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
96652ccf843Smisaki "Cannot stop channel %d (TXC hung!)",
96752ccf843Smisaki channel));
96844961713Sgirish }
96944961713Sgirish break;
97044961713Sgirish
97144961713Sgirish case TXDMA_RESUME:
97244961713Sgirish /* Resume the packet transmission after stopping */
97344961713Sgirish TXDMA_REG_READ64(handle, TX_CS_REG, channel, &cs.value);
97444961713Sgirish cs.value |= ~TX_CS_STOP_N_GO_MASK;
97544961713Sgirish TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs.value);
97644961713Sgirish return (npi_txdma_control_resume_wait(handle, channel));
97744961713Sgirish
97844961713Sgirish case TXDMA_CLEAR_MMK:
97944961713Sgirish /* Write 1 to MK bit to clear the MMK bit */
98044961713Sgirish TXDMA_REG_READ64(handle, TX_CS_REG, channel, &cs.value);
98144961713Sgirish cs.bits.ldw.mk = 1;
98244961713Sgirish TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs.value);
98344961713Sgirish break;
98444961713Sgirish
98544961713Sgirish case TXDMA_MBOX_ENABLE:
98644961713Sgirish /*
98744961713Sgirish * Write 1 to MB bit to enable mailbox update
98844961713Sgirish * (cleared to 0 by hardware after update).
98944961713Sgirish */
99044961713Sgirish TXDMA_REG_READ64(handle, TX_CS_REG, channel, &cs.value);
99144961713Sgirish cs.bits.ldw.mb = 1;
99244961713Sgirish TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs.value);
99344961713Sgirish break;
99444961713Sgirish
99544961713Sgirish default:
99644961713Sgirish status = (NPI_FAILURE | NPI_TXDMA_OPCODE_INVALID(channel));
99744961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
99852ccf843Smisaki " npi_txdma_channel_control"
99952ccf843Smisaki " Invalid Input: control <0x%x>",
100052ccf843Smisaki control));
100144961713Sgirish }
100244961713Sgirish
100344961713Sgirish return (status);
100444961713Sgirish }
100544961713Sgirish
100644961713Sgirish /*
100744961713Sgirish * npi_txdma_control_status():
100844961713Sgirish * This function is called to operate on the control
100944961713Sgirish * and status register.
101044961713Sgirish *
101144961713Sgirish * Parameters:
101244961713Sgirish * handle - NPI handle
101344961713Sgirish * op_mode - OP_GET: get hardware control and status
101444961713Sgirish * OP_SET: set hardware control and status
101544961713Sgirish * OP_UPDATE: update hardware control and status.
101644961713Sgirish * OP_CLEAR: clear control and status register to 0s.
101744961713Sgirish * channel - hardware TXDMA channel from 0 to 23.
101844961713Sgirish * cs_p - pointer to hardware defined control and status
101944961713Sgirish * structure.
102044961713Sgirish * Return:
102144961713Sgirish * NPI_SUCCESS - If set is complete successfully.
102244961713Sgirish *
102344961713Sgirish * Error:
102444961713Sgirish * NPI_FAILURE -
102544961713Sgirish * NPI_TXDMA_OPCODE_INVALID -
102644961713Sgirish * NPI_TXDMA_CHANNEL_INVALID -
102744961713Sgirish * NPI_TXDMA_FUNC_INVALID -
102844961713Sgirish */
102944961713Sgirish npi_status_t
npi_txdma_control_status(npi_handle_t handle,io_op_t op_mode,uint8_t channel,p_tx_cs_t cs_p)103044961713Sgirish npi_txdma_control_status(npi_handle_t handle, io_op_t op_mode,
1031*86ef0a63SRichard Lowe uint8_t channel, p_tx_cs_t cs_p)
103244961713Sgirish {
103344961713Sgirish int status = NPI_SUCCESS;
103444961713Sgirish tx_cs_t txcs;
103544961713Sgirish
1036a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(channel));
103744961713Sgirish if (!TXDMA_CHANNEL_VALID(channel)) {
103844961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
103952ccf843Smisaki " npi_txdma_control_status"
104052ccf843Smisaki " Invalid Input: channel <0x%x>",
104152ccf843Smisaki channel));
104244961713Sgirish return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel));
104344961713Sgirish }
104444961713Sgirish
104544961713Sgirish switch (op_mode) {
104644961713Sgirish case OP_GET:
104744961713Sgirish TXDMA_REG_READ64(handle, TX_CS_REG, channel, &cs_p->value);
104844961713Sgirish break;
104944961713Sgirish
105044961713Sgirish case OP_SET:
105144961713Sgirish TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs_p->value);
105244961713Sgirish break;
105344961713Sgirish
105444961713Sgirish case OP_UPDATE:
105544961713Sgirish TXDMA_REG_READ64(handle, TX_CS_REG, channel, &txcs.value);
105644961713Sgirish TXDMA_REG_WRITE64(handle, TX_CS_REG, channel,
105752ccf843Smisaki cs_p->value | txcs.value);
105844961713Sgirish break;
105944961713Sgirish
106044961713Sgirish default:
106144961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
106252ccf843Smisaki " npi_txdma_control_status"
106352ccf843Smisaki " Invalid Input: control <0x%x>",
106452ccf843Smisaki op_mode));
106544961713Sgirish return (NPI_FAILURE | NPI_TXDMA_OPCODE_INVALID(channel));
106644961713Sgirish }
106744961713Sgirish
106844961713Sgirish return (status);
106944961713Sgirish
107044961713Sgirish }
107144961713Sgirish
107244961713Sgirish /*
107344961713Sgirish * npi_txdma_event_mask():
107444961713Sgirish * This function is called to operate on the event mask
107544961713Sgirish * register which is used for generating interrupts..
107644961713Sgirish * and status register.
107744961713Sgirish *
107844961713Sgirish * Parameters:
107944961713Sgirish * handle - NPI handle
108044961713Sgirish * op_mode - OP_GET: get hardware event mask
108144961713Sgirish * OP_SET: set hardware interrupt event masks
108244961713Sgirish * OP_CLEAR: clear control and status register to 0s.
108344961713Sgirish * channel - hardware TXDMA channel from 0 to 23.
108444961713Sgirish * mask_p - pointer to hardware defined event mask
108544961713Sgirish * structure.
108644961713Sgirish * Return:
108744961713Sgirish * NPI_SUCCESS - If set is complete successfully.
108844961713Sgirish *
108944961713Sgirish * Error:
109044961713Sgirish * NPI_FAILURE -
109144961713Sgirish * NPI_TXDMA_OPCODE_INVALID -
109244961713Sgirish * NPI_TXDMA_CHANNEL_INVALID -
109344961713Sgirish */
109444961713Sgirish npi_status_t
npi_txdma_event_mask(npi_handle_t handle,io_op_t op_mode,uint8_t channel,p_tx_dma_ent_msk_t mask_p)109544961713Sgirish npi_txdma_event_mask(npi_handle_t handle, io_op_t op_mode,
1096*86ef0a63SRichard Lowe uint8_t channel, p_tx_dma_ent_msk_t mask_p)
109744961713Sgirish {
109844961713Sgirish int status = NPI_SUCCESS;
109944961713Sgirish tx_dma_ent_msk_t mask;
110044961713Sgirish
1101a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(channel));
110244961713Sgirish if (!TXDMA_CHANNEL_VALID(channel)) {
110344961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
110452ccf843Smisaki " npi_txdma_event_mask"
110552ccf843Smisaki " Invalid Input: channel <0x%x>",
110652ccf843Smisaki channel));
110744961713Sgirish return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel));
110844961713Sgirish }
110944961713Sgirish
111044961713Sgirish switch (op_mode) {
111144961713Sgirish case OP_GET:
111244961713Sgirish TXDMA_REG_READ64(handle, TX_ENT_MSK_REG, channel,
111352ccf843Smisaki &mask_p->value);
111444961713Sgirish break;
111544961713Sgirish
111644961713Sgirish case OP_SET:
111744961713Sgirish TXDMA_REG_WRITE64(handle, TX_ENT_MSK_REG, channel,
111852ccf843Smisaki mask_p->value);
111944961713Sgirish break;
112044961713Sgirish
112144961713Sgirish case OP_UPDATE:
112244961713Sgirish TXDMA_REG_READ64(handle, TX_ENT_MSK_REG, channel, &mask.value);
112344961713Sgirish TXDMA_REG_WRITE64(handle, TX_ENT_MSK_REG, channel,
112452ccf843Smisaki mask_p->value | mask.value);
112544961713Sgirish break;
112644961713Sgirish
112744961713Sgirish default:
112844961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
112952ccf843Smisaki " npi_txdma_event_mask"
113052ccf843Smisaki " Invalid Input: eventmask <0x%x>",
113152ccf843Smisaki op_mode));
113244961713Sgirish return (NPI_FAILURE | NPI_TXDMA_OPCODE_INVALID(channel));
113344961713Sgirish }
113444961713Sgirish
113544961713Sgirish return (status);
113644961713Sgirish }
113744961713Sgirish
113844961713Sgirish /*
113944961713Sgirish * npi_txdma_event_mask_config():
114044961713Sgirish * This function is called to operate on the event mask
114144961713Sgirish * register which is used for generating interrupts..
114244961713Sgirish * and status register.
114344961713Sgirish *
114444961713Sgirish * Parameters:
114544961713Sgirish * handle - NPI handle
114644961713Sgirish * op_mode - OP_GET: get hardware event mask
114744961713Sgirish * OP_SET: set hardware interrupt event masks
114844961713Sgirish * OP_CLEAR: clear control and status register to 0s.
114944961713Sgirish * channel - hardware TXDMA channel from 0 to 23.
115044961713Sgirish * cfgp - pointer to NPI defined event mask
115144961713Sgirish * enum data type.
115244961713Sgirish * Return:
115344961713Sgirish * NPI_SUCCESS - If set is complete successfully.
115444961713Sgirish *
115544961713Sgirish * Error:
115644961713Sgirish * NPI_FAILURE -
115744961713Sgirish * NPI_TXDMA_OPCODE_INVALID -
115844961713Sgirish * NPI_TXDMA_CHANNEL_INVALID -
115944961713Sgirish */
116044961713Sgirish npi_status_t
npi_txdma_event_mask_config(npi_handle_t handle,io_op_t op_mode,uint8_t channel,txdma_ent_msk_cfg_t * mask_cfgp)116144961713Sgirish npi_txdma_event_mask_config(npi_handle_t handle, io_op_t op_mode,
1162*86ef0a63SRichard Lowe uint8_t channel, txdma_ent_msk_cfg_t *mask_cfgp)
116344961713Sgirish {
116444961713Sgirish int status = NPI_SUCCESS;
1165678453a8Sspeer uint64_t configuration = *mask_cfgp;
116644961713Sgirish uint64_t value;
116744961713Sgirish
1168a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(channel));
116944961713Sgirish if (!TXDMA_CHANNEL_VALID(channel)) {
117044961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
117152ccf843Smisaki " npi_txdma_event_mask_config"
117252ccf843Smisaki " Invalid Input: channel <0x%x>",
117352ccf843Smisaki channel));
117444961713Sgirish
117544961713Sgirish return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel));
117644961713Sgirish }
117744961713Sgirish
117844961713Sgirish switch (op_mode) {
117944961713Sgirish case OP_GET:
1180678453a8Sspeer TXDMA_REG_READ64(handle, TX_ENT_MSK_REG, channel,
1181678453a8Sspeer (uint64_t *)mask_cfgp);
118244961713Sgirish break;
118344961713Sgirish
118444961713Sgirish case OP_SET:
118544961713Sgirish TXDMA_REG_WRITE64(handle, TX_ENT_MSK_REG, channel,
1186678453a8Sspeer configuration);
118744961713Sgirish break;
118844961713Sgirish
118944961713Sgirish case OP_UPDATE:
119044961713Sgirish TXDMA_REG_READ64(handle, TX_ENT_MSK_REG, channel, &value);
119144961713Sgirish TXDMA_REG_WRITE64(handle, TX_ENT_MSK_REG, channel,
1192678453a8Sspeer configuration | value);
119344961713Sgirish break;
119444961713Sgirish
119544961713Sgirish case OP_CLEAR:
119644961713Sgirish TXDMA_REG_WRITE64(handle, TX_ENT_MSK_REG, channel,
119752ccf843Smisaki CFG_TXDMA_MASK_ALL);
119844961713Sgirish break;
119944961713Sgirish default:
120044961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
120152ccf843Smisaki " npi_txdma_event_mask_config"
120252ccf843Smisaki " Invalid Input: eventmask <0x%x>",
120352ccf843Smisaki op_mode));
120444961713Sgirish return (NPI_FAILURE | NPI_TXDMA_OPCODE_INVALID(channel));
120544961713Sgirish }
120644961713Sgirish
120744961713Sgirish return (status);
120844961713Sgirish }
120944961713Sgirish
121044961713Sgirish /*
121144961713Sgirish * npi_txdma_event_mask_mk_out():
121244961713Sgirish * This function is called to mask out the packet transmit marked event.
121344961713Sgirish *
121444961713Sgirish * Parameters:
121544961713Sgirish * handle - NPI handle
121644961713Sgirish * channel - hardware TXDMA channel from 0 to 23.
121744961713Sgirish * enum data type.
121844961713Sgirish * Return:
121944961713Sgirish * NPI_SUCCESS - If set is complete successfully.
122044961713Sgirish *
122144961713Sgirish * Error:
122244961713Sgirish * NPI_FAILURE -
122344961713Sgirish * NPI_TXDMA_CHANNEL_INVALID -
122444961713Sgirish */
122544961713Sgirish npi_status_t
npi_txdma_event_mask_mk_out(npi_handle_t handle,uint8_t channel)122644961713Sgirish npi_txdma_event_mask_mk_out(npi_handle_t handle, uint8_t channel)
122744961713Sgirish {
1228678453a8Sspeer uint64_t event_mask;
1229678453a8Sspeer int status = NPI_SUCCESS;
123044961713Sgirish
1231a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(channel));
123244961713Sgirish if (!TXDMA_CHANNEL_VALID(channel)) {
123344961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
123452ccf843Smisaki " npi_txdma_event_mask_mk_out"
123552ccf843Smisaki " Invalid Input: channel <0x%x>",
123652ccf843Smisaki channel));
123744961713Sgirish return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel));
123844961713Sgirish }
123944961713Sgirish
124044961713Sgirish TXDMA_REG_READ64(handle, TX_ENT_MSK_REG, channel, &event_mask);
124144961713Sgirish TXDMA_REG_WRITE64(handle, TX_ENT_MSK_REG, channel,
124252ccf843Smisaki event_mask & (~TX_ENT_MSK_MK_MASK));
124344961713Sgirish
124444961713Sgirish return (status);
124544961713Sgirish }
124644961713Sgirish
124744961713Sgirish /*
124844961713Sgirish * npi_txdma_event_mask_mk_in():
124944961713Sgirish * This function is called to set the mask for the the packet marked event.
125044961713Sgirish *
125144961713Sgirish * Parameters:
125244961713Sgirish * handle - NPI handle
125344961713Sgirish * channel - hardware TXDMA channel from 0 to 23.
125444961713Sgirish * enum data type.
125544961713Sgirish * Return:
125644961713Sgirish * NPI_SUCCESS - If set is complete successfully.
125744961713Sgirish *
125844961713Sgirish * Error:
125944961713Sgirish * NPI_FAILURE -
126044961713Sgirish * NPI_TXDMA_CHANNEL_INVALID -
126144961713Sgirish */
126244961713Sgirish npi_status_t
npi_txdma_event_mask_mk_in(npi_handle_t handle,uint8_t channel)126344961713Sgirish npi_txdma_event_mask_mk_in(npi_handle_t handle, uint8_t channel)
126444961713Sgirish {
1265678453a8Sspeer uint64_t event_mask;
1266678453a8Sspeer int status = NPI_SUCCESS;
126744961713Sgirish
1268a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(channel));
126944961713Sgirish if (!TXDMA_CHANNEL_VALID(channel)) {
127044961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
127152ccf843Smisaki " npi_txdma_event_mask_mk_in"
127252ccf843Smisaki " Invalid Input: channel <0x%x>",
127352ccf843Smisaki channel));
127444961713Sgirish return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel));
127544961713Sgirish }
127644961713Sgirish
127744961713Sgirish TXDMA_REG_READ64(handle, TX_ENT_MSK_REG, channel, &event_mask);
127844961713Sgirish TXDMA_REG_WRITE64(handle, TX_ENT_MSK_REG, channel,
127952ccf843Smisaki event_mask | TX_ENT_MSK_MK_MASK);
128044961713Sgirish
128144961713Sgirish return (status);
128244961713Sgirish }
128344961713Sgirish
128444961713Sgirish /*
128544961713Sgirish * npi_txdma_ring_addr_set():
128644961713Sgirish * This function is called to configure the transmit descriptor
128744961713Sgirish * ring address and its size.
128844961713Sgirish *
128944961713Sgirish * Parameters:
129044961713Sgirish * handle - NPI handle (virtualization flag must be defined
129144961713Sgirish * if its register pointer is from the virtual region).
129244961713Sgirish * channel - logical TXDMA channel from 0 to 23.
129344961713Sgirish * (If virtualization flag is not set, then
129444961713Sgirish * logical channel is the same as the hardware
129544961713Sgirish * channel number).
129644961713Sgirish * start_addr - starting address of the descriptor
129744961713Sgirish * len - maximum length of the descriptor
129844961713Sgirish * (in number of 64 bytes block).
129944961713Sgirish * Return:
130044961713Sgirish * NPI_SUCCESS - If set is complete successfully.
130144961713Sgirish *
130244961713Sgirish * Error:
130344961713Sgirish * NPI_FAILURE -
130444961713Sgirish * NPI_TXDMA_OPCODE_INVALID -
130544961713Sgirish * NPI_TXDMA_CHANNEL_INVALID -
130644961713Sgirish */
130744961713Sgirish npi_status_t
npi_txdma_ring_addr_set(npi_handle_t handle,uint8_t channel,uint64_t start_addr,uint32_t len)130844961713Sgirish npi_txdma_ring_addr_set(npi_handle_t handle, uint8_t channel,
1309*86ef0a63SRichard Lowe uint64_t start_addr, uint32_t len)
131044961713Sgirish {
131144961713Sgirish int status = NPI_SUCCESS;
131244961713Sgirish tx_rng_cfig_t cfg;
131344961713Sgirish
1314a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(channel));
131544961713Sgirish if (!TXDMA_CHANNEL_VALID(channel)) {
131644961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
131752ccf843Smisaki " npi_txdma_ring_addr_set"
131852ccf843Smisaki " Invalid Input: channel <0x%x>",
131952ccf843Smisaki channel));
132044961713Sgirish return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel));
132144961713Sgirish }
132244961713Sgirish
132344961713Sgirish cfg.value = ((start_addr & TX_RNG_CFIG_ADDR_MASK) |
132452ccf843Smisaki (((uint64_t)len) << TX_RNG_CFIG_LEN_SHIFT));
132544961713Sgirish TXDMA_REG_WRITE64(handle, TX_RNG_CFIG_REG, channel, cfg.value);
132644961713Sgirish
132744961713Sgirish return (status);
132844961713Sgirish }
132944961713Sgirish
133044961713Sgirish /*
133144961713Sgirish * npi_txdma_ring_config():
133244961713Sgirish * This function is called to config a descriptor ring
133344961713Sgirish * by using the hardware defined data.
133444961713Sgirish *
133544961713Sgirish * Parameters:
133644961713Sgirish * handle - NPI handle (virtualization flag must be defined
133744961713Sgirish * if its register pointer is from the virtual region).
133844961713Sgirish * channel - logical TXDMA channel from 0 to 23.
133944961713Sgirish * (If virtualization flag is not set, then
134044961713Sgirish * logical channel is the same as the hardware
134144961713Sgirish * channel number).
134244961713Sgirish * op_mode - OP_GET: get transmit ring configuration
134344961713Sgirish * OP_SET: set transmit ring configuration
134444961713Sgirish * reg_data - pointer to hardware defined transmit ring
134544961713Sgirish * configuration data structure.
134644961713Sgirish * Return:
134744961713Sgirish * NPI_SUCCESS - If set/get is complete successfully.
134844961713Sgirish *
134944961713Sgirish * Error:
135044961713Sgirish * NPI_FAILURE -
135144961713Sgirish * NPI_TXDMA_CHANNEL_INVALID -
135244961713Sgirish */
135344961713Sgirish npi_status_t
npi_txdma_ring_config(npi_handle_t handle,io_op_t op_mode,uint8_t channel,uint64_t * reg_data)135444961713Sgirish npi_txdma_ring_config(npi_handle_t handle, io_op_t op_mode,
1355*86ef0a63SRichard Lowe uint8_t channel, uint64_t *reg_data)
135644961713Sgirish {
135744961713Sgirish int status = NPI_SUCCESS;
135844961713Sgirish
1359a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(channel));
136044961713Sgirish if (!TXDMA_CHANNEL_VALID(channel)) {
136144961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
136252ccf843Smisaki " npi_txdma_ring_config"
136352ccf843Smisaki " Invalid Input: channel <0x%x>",
136452ccf843Smisaki channel));
136544961713Sgirish return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel));
136644961713Sgirish }
136744961713Sgirish
136844961713Sgirish switch (op_mode) {
136944961713Sgirish case OP_GET:
137044961713Sgirish TXDMA_REG_READ64(handle, TX_RNG_CFIG_REG, channel, reg_data);
137144961713Sgirish break;
137244961713Sgirish
137344961713Sgirish case OP_SET:
137444961713Sgirish TXDMA_REG_WRITE64(handle, TX_RNG_CFIG_REG, channel,
137552ccf843Smisaki *reg_data);
137644961713Sgirish break;
137744961713Sgirish
137844961713Sgirish default:
137944961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
138052ccf843Smisaki " npi_txdma_ring_config"
138152ccf843Smisaki " Invalid Input: ring_config <0x%x>",
138252ccf843Smisaki op_mode));
138344961713Sgirish return (NPI_FAILURE | NPI_TXDMA_OPCODE_INVALID(channel));
138444961713Sgirish }
138544961713Sgirish
138644961713Sgirish return (status);
138744961713Sgirish }
138844961713Sgirish
138944961713Sgirish /*
139044961713Sgirish * npi_txdma_mbox_config():
139144961713Sgirish * This function is called to config the mailbox address
139244961713Sgirish *
139344961713Sgirish * Parameters:
139444961713Sgirish * handle - NPI handle (virtualization flag must be defined
139544961713Sgirish * if its register pointer is from the virtual region).
139644961713Sgirish * channel - logical TXDMA channel from 0 to 23.
139744961713Sgirish * (If virtualization flag is not set, then
139844961713Sgirish * logical channel is the same as the hardware
139944961713Sgirish * channel number).
140044961713Sgirish * op_mode - OP_GET: get the mailbox address
140144961713Sgirish * OP_SET: set the mailbox address
140244961713Sgirish * reg_data - pointer to the mailbox address.
140344961713Sgirish * Return:
140444961713Sgirish * NPI_SUCCESS - If set is complete successfully.
140544961713Sgirish *
140644961713Sgirish * Error:
140744961713Sgirish * NPI_FAILURE -
140844961713Sgirish * NPI_TXDMA_OPCODE_INVALID -
140944961713Sgirish * NPI_TXDMA_CHANNEL_INVALID -
141044961713Sgirish */
141144961713Sgirish npi_status_t
npi_txdma_mbox_config(npi_handle_t handle,io_op_t op_mode,uint8_t channel,uint64_t * mbox_addr)141244961713Sgirish npi_txdma_mbox_config(npi_handle_t handle, io_op_t op_mode,
1413*86ef0a63SRichard Lowe uint8_t channel, uint64_t *mbox_addr)
141444961713Sgirish {
141544961713Sgirish int status = NPI_SUCCESS;
141644961713Sgirish txdma_mbh_t mh;
141744961713Sgirish txdma_mbl_t ml;
141844961713Sgirish
1419a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(channel));
142044961713Sgirish if (!TXDMA_CHANNEL_VALID(channel)) {
142144961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
142252ccf843Smisaki " npi_txdma_mbox_config"
142352ccf843Smisaki " Invalid Input: channel <0x%x>",
142452ccf843Smisaki channel));
142544961713Sgirish return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel));
142644961713Sgirish }
142744961713Sgirish
142844961713Sgirish mh.value = ml.value = 0;
142944961713Sgirish
143044961713Sgirish switch (op_mode) {
143144961713Sgirish case OP_GET:
143244961713Sgirish TXDMA_REG_READ64(handle, TXDMA_MBH_REG, channel, &mh.value);
143344961713Sgirish TXDMA_REG_READ64(handle, TXDMA_MBL_REG, channel, &ml.value);
143444961713Sgirish *mbox_addr = ml.value;
143544961713Sgirish *mbox_addr |= (mh.value << TXDMA_MBH_ADDR_SHIFT);
143644961713Sgirish
143744961713Sgirish break;
143844961713Sgirish
143944961713Sgirish case OP_SET:
144044961713Sgirish ml.bits.ldw.mbaddr = ((*mbox_addr & TXDMA_MBL_MASK) >>
144152ccf843Smisaki TXDMA_MBL_SHIFT);
144244961713Sgirish TXDMA_REG_WRITE64(handle, TXDMA_MBL_REG, channel, ml.value);
144344961713Sgirish mh.bits.ldw.mbaddr = ((*mbox_addr >> TXDMA_MBH_ADDR_SHIFT) &
144452ccf843Smisaki TXDMA_MBH_MASK);
144544961713Sgirish TXDMA_REG_WRITE64(handle, TXDMA_MBH_REG, channel, mh.value);
144644961713Sgirish
144744961713Sgirish break;
144844961713Sgirish
144944961713Sgirish default:
145044961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
145152ccf843Smisaki " npi_txdma_mbox_config"
145252ccf843Smisaki " Invalid Input: mbox <0x%x>",
145352ccf843Smisaki op_mode));
145444961713Sgirish return (NPI_FAILURE | NPI_TXDMA_OPCODE_INVALID(channel));
145544961713Sgirish }
145644961713Sgirish
145744961713Sgirish return (status);
145844961713Sgirish
145944961713Sgirish }
146044961713Sgirish
146144961713Sgirish /*
146244961713Sgirish * npi_txdma_desc_gather_set():
146344961713Sgirish * This function is called to set up a transmit descriptor entry.
146444961713Sgirish *
146544961713Sgirish * Parameters:
146644961713Sgirish * handle - NPI handle (register pointer is the
146744961713Sgirish * descriptor address in memory).
146844961713Sgirish * desc_p - pointer to a descriptor
146944961713Sgirish * gather_index - which entry (starts from index 0 to 15)
147044961713Sgirish * mark - mark bit (only valid if it is the first gather).
147144961713Sgirish * ngathers - number of gather pointers to set to the first gather.
147244961713Sgirish * dma_ioaddr - starting dma address of an IO buffer to write.
147344961713Sgirish * (SAD)
147444961713Sgirish * transfer_len - transfer len.
147544961713Sgirish * Return:
147644961713Sgirish * NPI_SUCCESS - If set is complete successfully.
147744961713Sgirish *
147844961713Sgirish * Error:
147944961713Sgirish * NPI_FAILURE -
148044961713Sgirish * NPI_TXDMA_OPCODE_INVALID -
148144961713Sgirish * NPI_TXDMA_CHANNEL_INVALID -
148244961713Sgirish * NPI_TXDMA_XFER_LEN_INVALID -
148344961713Sgirish */
148444961713Sgirish npi_status_t
npi_txdma_desc_gather_set(npi_handle_t handle,p_tx_desc_t desc_p,uint8_t gather_index,boolean_t mark,uint8_t ngathers,uint64_t dma_ioaddr,uint32_t transfer_len)148544961713Sgirish npi_txdma_desc_gather_set(npi_handle_t handle,
1486*86ef0a63SRichard Lowe p_tx_desc_t desc_p, uint8_t gather_index,
1487*86ef0a63SRichard Lowe boolean_t mark, uint8_t ngathers,
1488*86ef0a63SRichard Lowe uint64_t dma_ioaddr, uint32_t transfer_len)
148944961713Sgirish {
149044961713Sgirish int status;
149144961713Sgirish
149244961713Sgirish status = NPI_TXDMA_GATHER_INDEX(gather_index);
149344961713Sgirish if (status) {
149444961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
149552ccf843Smisaki " npi_txdma_desc_gather_set"
149652ccf843Smisaki " Invalid Input: gather_index <0x%x>",
149752ccf843Smisaki gather_index));
149844961713Sgirish return (status);
149944961713Sgirish }
150044961713Sgirish
150144961713Sgirish if (transfer_len > TX_MAX_TRANSFER_LENGTH) {
150244961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
150352ccf843Smisaki " npi_txdma_desc_gather_set"
150452ccf843Smisaki " Invalid Input: tr_len <0x%x>",
150552ccf843Smisaki transfer_len));
150644961713Sgirish return (NPI_FAILURE | NPI_TXDMA_XFER_LEN_INVALID);
150744961713Sgirish }
150844961713Sgirish
150944961713Sgirish if (gather_index == 0) {
151044961713Sgirish desc_p->bits.hdw.sop = 1;
151144961713Sgirish desc_p->bits.hdw.mark = mark;
151244961713Sgirish desc_p->bits.hdw.num_ptr = ngathers;
151344961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_TDC_CTL,
151452ccf843Smisaki "npi_txdma_gather_set: SOP len %d (%d)",
151552ccf843Smisaki desc_p->bits.hdw.tr_len, transfer_len));
151644961713Sgirish }
151744961713Sgirish
151844961713Sgirish desc_p->bits.hdw.tr_len = transfer_len;
151944961713Sgirish desc_p->bits.hdw.sad = dma_ioaddr >> 32;
152044961713Sgirish desc_p->bits.ldw.sad = dma_ioaddr & 0xffffffff;
152144961713Sgirish
152244961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_TDC_CTL,
152352ccf843Smisaki "npi_txdma_gather_set: xfer len %d to set (%d)",
152452ccf843Smisaki desc_p->bits.hdw.tr_len, transfer_len));
152544961713Sgirish
152644961713Sgirish NXGE_MEM_PIO_WRITE64(handle, desc_p->value);
152744961713Sgirish
152844961713Sgirish return (status);
152944961713Sgirish }
153044961713Sgirish
153144961713Sgirish /*
153244961713Sgirish * npi_txdma_desc_sop_set():
153344961713Sgirish * This function is called to set up the first gather entry.
153444961713Sgirish *
153544961713Sgirish * Parameters:
153644961713Sgirish * handle - NPI handle (register pointer is the
153744961713Sgirish * descriptor address in memory).
153844961713Sgirish * desc_p - pointer to a descriptor
153944961713Sgirish * mark - mark bit (only valid if it is the first gather).
154044961713Sgirish * ngathers - number of gather pointers to set to the first gather.
154144961713Sgirish * Return:
154244961713Sgirish * NPI_SUCCESS - If set is complete successfully.
154344961713Sgirish *
154444961713Sgirish * Error:
154544961713Sgirish */
154644961713Sgirish npi_status_t
npi_txdma_desc_gather_sop_set(npi_handle_t handle,p_tx_desc_t desc_p,boolean_t mark_mode,uint8_t ngathers)154744961713Sgirish npi_txdma_desc_gather_sop_set(npi_handle_t handle,
1548*86ef0a63SRichard Lowe p_tx_desc_t desc_p,
1549*86ef0a63SRichard Lowe boolean_t mark_mode,
1550*86ef0a63SRichard Lowe uint8_t ngathers)
155144961713Sgirish {
155244961713Sgirish int status = NPI_SUCCESS;
155344961713Sgirish
155444961713Sgirish desc_p->bits.hdw.sop = 1;
155544961713Sgirish desc_p->bits.hdw.mark = mark_mode;
155644961713Sgirish desc_p->bits.hdw.num_ptr = ngathers;
155744961713Sgirish
155844961713Sgirish NXGE_MEM_PIO_WRITE64(handle, desc_p->value);
155944961713Sgirish
156044961713Sgirish return (status);
156144961713Sgirish }
156244961713Sgirish npi_status_t
npi_txdma_desc_gather_sop_set_1(npi_handle_t handle,p_tx_desc_t desc_p,boolean_t mark_mode,uint8_t ngathers,uint32_t extra)156344961713Sgirish npi_txdma_desc_gather_sop_set_1(npi_handle_t handle,
1564*86ef0a63SRichard Lowe p_tx_desc_t desc_p,
1565*86ef0a63SRichard Lowe boolean_t mark_mode,
1566*86ef0a63SRichard Lowe uint8_t ngathers,
1567*86ef0a63SRichard Lowe uint32_t extra)
156844961713Sgirish {
156944961713Sgirish int status = NPI_SUCCESS;
157044961713Sgirish
157144961713Sgirish desc_p->bits.hdw.sop = 1;
157244961713Sgirish desc_p->bits.hdw.mark = mark_mode;
157344961713Sgirish desc_p->bits.hdw.num_ptr = ngathers;
157444961713Sgirish desc_p->bits.hdw.tr_len += extra;
157544961713Sgirish
157644961713Sgirish NXGE_MEM_PIO_WRITE64(handle, desc_p->value);
157744961713Sgirish
157844961713Sgirish return (status);
157944961713Sgirish }
158044961713Sgirish
158144961713Sgirish npi_status_t
npi_txdma_desc_set_xfer_len(npi_handle_t handle,p_tx_desc_t desc_p,uint32_t transfer_len)158244961713Sgirish npi_txdma_desc_set_xfer_len(npi_handle_t handle,
1583*86ef0a63SRichard Lowe p_tx_desc_t desc_p,
1584*86ef0a63SRichard Lowe uint32_t transfer_len)
158544961713Sgirish {
158644961713Sgirish int status = NPI_SUCCESS;
158744961713Sgirish
158844961713Sgirish desc_p->bits.hdw.tr_len = transfer_len;
158944961713Sgirish
159044961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_TDC_CTL,
159152ccf843Smisaki "npi_set_xfer_len: len %d (%d)",
159252ccf843Smisaki desc_p->bits.hdw.tr_len, transfer_len));
159344961713Sgirish
159444961713Sgirish NXGE_MEM_PIO_WRITE64(handle, desc_p->value);
159544961713Sgirish
159644961713Sgirish return (status);
159744961713Sgirish }
159844961713Sgirish
159944961713Sgirish npi_status_t
npi_txdma_desc_set_zero(npi_handle_t handle,uint16_t entries)160044961713Sgirish npi_txdma_desc_set_zero(npi_handle_t handle, uint16_t entries)
160144961713Sgirish {
160244961713Sgirish uint32_t offset;
160344961713Sgirish int i;
160444961713Sgirish
160544961713Sgirish /*
160644961713Sgirish * Assume no wrapped around.
160744961713Sgirish */
160844961713Sgirish offset = 0;
160944961713Sgirish for (i = 0; i < entries; i++) {
161044961713Sgirish NXGE_REG_WR64(handle, offset, 0);
161144961713Sgirish offset += (i * TXDMA_DESC_SIZE);
161244961713Sgirish }
161344961713Sgirish
161444961713Sgirish return (NPI_SUCCESS);
161544961713Sgirish }
161644961713Sgirish
161744961713Sgirish npi_status_t
npi_txdma_desc_mem_get(npi_handle_t handle,uint16_t index,p_tx_desc_t desc_p)161844961713Sgirish npi_txdma_desc_mem_get(npi_handle_t handle, uint16_t index,
1619*86ef0a63SRichard Lowe p_tx_desc_t desc_p)
162044961713Sgirish {
162144961713Sgirish int status = NPI_SUCCESS;
162244961713Sgirish
162344961713Sgirish npi_txdma_dump_desc_one(handle, desc_p, index);
162444961713Sgirish
162544961713Sgirish return (status);
162644961713Sgirish
162744961713Sgirish }
162844961713Sgirish
162944961713Sgirish /*
163044961713Sgirish * npi_txdma_desc_kick_reg_set():
163144961713Sgirish * This function is called to kick the transmit to start transmission.
163244961713Sgirish *
163344961713Sgirish * Parameters:
163444961713Sgirish * handle - NPI handle (virtualization flag must be defined).
163544961713Sgirish * channel - logical TXDMA channel from 0 to 23.
163644961713Sgirish * (If virtualization flag is not set, then
163744961713Sgirish * logical channel is the same as the hardware
163844961713Sgirish * channel number).
163944961713Sgirish * tail_index - index into the transmit descriptor
164044961713Sgirish * wrap - toggle bit to indicate if the tail index is
164144961713Sgirish * wrapped around.
164244961713Sgirish *
164344961713Sgirish * Return:
164444961713Sgirish * NPI_SUCCESS - If set is complete successfully.
164544961713Sgirish *
164644961713Sgirish * Error:
164744961713Sgirish * NPI_FAILURE -
164844961713Sgirish * NPI_TXDMA_CHANNEL_INVALID -
164944961713Sgirish */
165044961713Sgirish npi_status_t
npi_txdma_desc_kick_reg_set(npi_handle_t handle,uint8_t channel,uint16_t tail_index,boolean_t wrap)165144961713Sgirish npi_txdma_desc_kick_reg_set(npi_handle_t handle, uint8_t channel,
1652*86ef0a63SRichard Lowe uint16_t tail_index, boolean_t wrap)
165344961713Sgirish {
165444961713Sgirish int status = NPI_SUCCESS;
165544961713Sgirish tx_ring_kick_t kick;
165644961713Sgirish
1657a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(channel));
165844961713Sgirish if (!TXDMA_CHANNEL_VALID(channel)) {
165944961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
166052ccf843Smisaki " npi_txdma_desc_kick_reg_set"
166152ccf843Smisaki " Invalid Input: channel <0x%x>",
166252ccf843Smisaki channel));
166344961713Sgirish return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel));
166444961713Sgirish }
166544961713Sgirish
166644961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_TDC_CTL,
166752ccf843Smisaki " npi_txdma_desc_kick_reg_set: "
166852ccf843Smisaki " KICKING channel %d",
166952ccf843Smisaki channel));
167044961713Sgirish
167144961713Sgirish /* Toggle the wrap around bit */
167244961713Sgirish kick.value = 0;
167344961713Sgirish kick.bits.ldw.wrap = wrap;
167444961713Sgirish kick.bits.ldw.tail = tail_index;
167544961713Sgirish
167644961713Sgirish /* Kick start the Transmit kick register */
167744961713Sgirish TXDMA_REG_WRITE64(handle, TX_RING_KICK_REG, channel, kick.value);
167844961713Sgirish
167944961713Sgirish return (status);
168044961713Sgirish }
168144961713Sgirish
168244961713Sgirish /*
168344961713Sgirish * npi_txdma_desc_kick_reg_get():
168444961713Sgirish * This function is called to kick the transmit to start transmission.
168544961713Sgirish *
168644961713Sgirish * Parameters:
168744961713Sgirish * handle - NPI handle (virtualization flag must be defined).
168844961713Sgirish * channel - logical TXDMA channel from 0 to 23.
168944961713Sgirish * (If virtualization flag is not set, then
169044961713Sgirish * logical channel is the same as the hardware
169144961713Sgirish * channel number).
169244961713Sgirish * tail_index - index into the transmit descriptor
169344961713Sgirish * wrap - toggle bit to indicate if the tail index is
169444961713Sgirish * wrapped around.
169544961713Sgirish *
169644961713Sgirish * Return:
169744961713Sgirish * NPI_SUCCESS - If get is complete successfully.
169844961713Sgirish *
169944961713Sgirish * Error:
170044961713Sgirish * NPI_FAILURE -
170144961713Sgirish * NPI_TXDMA_CHANNEL_INVALID -
170244961713Sgirish */
170344961713Sgirish npi_status_t
npi_txdma_desc_kick_reg_get(npi_handle_t handle,uint8_t channel,p_tx_ring_kick_t kick_p)170444961713Sgirish npi_txdma_desc_kick_reg_get(npi_handle_t handle, uint8_t channel,
1705*86ef0a63SRichard Lowe p_tx_ring_kick_t kick_p)
170644961713Sgirish {
170744961713Sgirish int status = NPI_SUCCESS;
170844961713Sgirish
1709a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(channel));
171044961713Sgirish if (!TXDMA_CHANNEL_VALID(channel)) {
171144961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
171252ccf843Smisaki " npi_txdma_desc_kick_reg_get"
171352ccf843Smisaki " Invalid Input: channel <0x%x>",
171452ccf843Smisaki channel));
171544961713Sgirish return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel));
171644961713Sgirish }
171744961713Sgirish
171844961713Sgirish TXDMA_REG_READ64(handle, TX_RING_KICK_REG, channel, &kick_p->value);
171944961713Sgirish
172044961713Sgirish return (status);
172144961713Sgirish }
172244961713Sgirish
172344961713Sgirish /*
172444961713Sgirish * npi_txdma_ring_head_get():
172544961713Sgirish * This function is called to get the transmit ring head index.
172644961713Sgirish *
172744961713Sgirish * Parameters:
172844961713Sgirish * handle - NPI handle (virtualization flag must be defined).
172944961713Sgirish * channel - logical TXDMA channel from 0 to 23.
173044961713Sgirish * (If virtualization flag is not set, then
173144961713Sgirish * logical channel is the same as the hardware
173244961713Sgirish * channel number).
173344961713Sgirish * hdl_p - pointer to the hardware defined transmit
173444961713Sgirish * ring header data (head index and wrap bit).
173544961713Sgirish *
173644961713Sgirish * Return:
173744961713Sgirish * NPI_SUCCESS - If get is complete successfully.
173844961713Sgirish *
173944961713Sgirish * Error:
174044961713Sgirish * NPI_FAILURE -
174144961713Sgirish * NPI_TXDMA_CHANNEL_INVALID -
174244961713Sgirish */
174344961713Sgirish npi_status_t
npi_txdma_ring_head_get(npi_handle_t handle,uint8_t channel,p_tx_ring_hdl_t hdl_p)174444961713Sgirish npi_txdma_ring_head_get(npi_handle_t handle, uint8_t channel,
1745*86ef0a63SRichard Lowe p_tx_ring_hdl_t hdl_p)
174644961713Sgirish {
174744961713Sgirish int status = NPI_SUCCESS;
174844961713Sgirish
1749a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(channel));
175044961713Sgirish if (!TXDMA_CHANNEL_VALID(channel)) {
175144961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
175252ccf843Smisaki " npi_txdma_ring_head_get"
175352ccf843Smisaki " Invalid Input: channel <0x%x>",
175452ccf843Smisaki channel));
175544961713Sgirish return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel));
175644961713Sgirish }
175744961713Sgirish
175844961713Sgirish TXDMA_REG_READ64(handle, TX_RING_HDL_REG, channel, &hdl_p->value);
175944961713Sgirish
176044961713Sgirish return (status);
176144961713Sgirish }
176244961713Sgirish
176344961713Sgirish /*ARGSUSED*/
176444961713Sgirish npi_status_t
npi_txdma_channel_mbox_get(npi_handle_t handle,uint8_t channel,p_txdma_mailbox_t mbox_p)176544961713Sgirish npi_txdma_channel_mbox_get(npi_handle_t handle, uint8_t channel,
1766*86ef0a63SRichard Lowe p_txdma_mailbox_t mbox_p)
176744961713Sgirish {
176844961713Sgirish int status = NPI_SUCCESS;
176944961713Sgirish
177044961713Sgirish return (status);
177144961713Sgirish
177244961713Sgirish }
177344961713Sgirish
177444961713Sgirish npi_status_t
npi_txdma_channel_pre_state_get(npi_handle_t handle,uint8_t channel,p_tx_dma_pre_st_t prep)177544961713Sgirish npi_txdma_channel_pre_state_get(npi_handle_t handle, uint8_t channel,
1776*86ef0a63SRichard Lowe p_tx_dma_pre_st_t prep)
177744961713Sgirish {
177844961713Sgirish int status = NPI_SUCCESS;
177944961713Sgirish
1780a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(channel));
178144961713Sgirish if (!TXDMA_CHANNEL_VALID(channel)) {
178244961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
178352ccf843Smisaki " npi_txdma_channel_pre_state_get"
178452ccf843Smisaki " Invalid Input: channel <0x%x>",
178552ccf843Smisaki channel));
178644961713Sgirish return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel));
178744961713Sgirish }
178844961713Sgirish
178944961713Sgirish TXDMA_REG_READ64(handle, TX_DMA_PRE_ST_REG, channel, &prep->value);
179044961713Sgirish
179144961713Sgirish return (status);
179244961713Sgirish }
179344961713Sgirish
179444961713Sgirish npi_status_t
npi_txdma_ring_error_get(npi_handle_t handle,uint8_t channel,p_txdma_ring_errlog_t ring_errlog_p)179544961713Sgirish npi_txdma_ring_error_get(npi_handle_t handle, uint8_t channel,
1796*86ef0a63SRichard Lowe p_txdma_ring_errlog_t ring_errlog_p)
179744961713Sgirish {
179844961713Sgirish tx_rng_err_logh_t logh;
179944961713Sgirish tx_rng_err_logl_t logl;
180044961713Sgirish int status = NPI_SUCCESS;
180144961713Sgirish
1802a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(channel));
180344961713Sgirish if (!TXDMA_CHANNEL_VALID(channel)) {
180444961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
180552ccf843Smisaki " npi_txdma_ring_error_get"
180652ccf843Smisaki " Invalid Input: channel <0x%x>",
180752ccf843Smisaki channel));
180844961713Sgirish return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel));
180944961713Sgirish }
181044961713Sgirish
181144961713Sgirish logh.value = 0;
181244961713Sgirish TXDMA_REG_READ64(handle, TX_RNG_ERR_LOGH_REG, channel, &logh.value);
181344961713Sgirish TXDMA_REG_READ64(handle, TX_RNG_ERR_LOGL_REG, channel, &logl.value);
181444961713Sgirish ring_errlog_p->logh.bits.ldw.err = logh.bits.ldw.err;
181544961713Sgirish ring_errlog_p->logh.bits.ldw.merr = logh.bits.ldw.merr;
181644961713Sgirish ring_errlog_p->logh.bits.ldw.errcode = logh.bits.ldw.errcode;
181744961713Sgirish ring_errlog_p->logh.bits.ldw.err_addr = logh.bits.ldw.err_addr;
181844961713Sgirish ring_errlog_p->logl.bits.ldw.err_addr = logl.bits.ldw.err_addr;
181944961713Sgirish
182044961713Sgirish return (status);
182144961713Sgirish }
182244961713Sgirish
182344961713Sgirish npi_status_t
npi_txdma_inj_par_error_clear(npi_handle_t handle)182444961713Sgirish npi_txdma_inj_par_error_clear(npi_handle_t handle)
182544961713Sgirish {
182644961713Sgirish NXGE_REG_WR64(handle, TDMC_INJ_PAR_ERR_REG, 0);
182744961713Sgirish
182844961713Sgirish return (NPI_SUCCESS);
182944961713Sgirish }
183044961713Sgirish
183144961713Sgirish npi_status_t
npi_txdma_inj_par_error_set(npi_handle_t handle,uint32_t err_bits)183244961713Sgirish npi_txdma_inj_par_error_set(npi_handle_t handle, uint32_t err_bits)
183344961713Sgirish {
183444961713Sgirish tdmc_inj_par_err_t inj;
183544961713Sgirish
183644961713Sgirish inj.value = 0;
183744961713Sgirish inj.bits.ldw.inject_parity_error = (err_bits & TDMC_INJ_PAR_ERR_MASK);
183844961713Sgirish NXGE_REG_WR64(handle, TDMC_INJ_PAR_ERR_REG, inj.value);
183944961713Sgirish
184044961713Sgirish return (NPI_SUCCESS);
184144961713Sgirish }
184244961713Sgirish
184344961713Sgirish npi_status_t
npi_txdma_inj_par_error_update(npi_handle_t handle,uint32_t err_bits)184444961713Sgirish npi_txdma_inj_par_error_update(npi_handle_t handle, uint32_t err_bits)
184544961713Sgirish {
184644961713Sgirish tdmc_inj_par_err_t inj;
184744961713Sgirish
184844961713Sgirish inj.value = 0;
184944961713Sgirish NXGE_REG_RD64(handle, TDMC_INJ_PAR_ERR_REG, &inj.value);
185044961713Sgirish inj.value |= (err_bits & TDMC_INJ_PAR_ERR_MASK);
185144961713Sgirish NXGE_REG_WR64(handle, TDMC_INJ_PAR_ERR_REG, inj.value);
185244961713Sgirish
185344961713Sgirish return (NPI_SUCCESS);
185444961713Sgirish }
185544961713Sgirish
185644961713Sgirish npi_status_t
npi_txdma_inj_par_error_get(npi_handle_t handle,uint32_t * err_bits)185744961713Sgirish npi_txdma_inj_par_error_get(npi_handle_t handle, uint32_t *err_bits)
185844961713Sgirish {
185944961713Sgirish tdmc_inj_par_err_t inj;
186044961713Sgirish
186144961713Sgirish inj.value = 0;
186244961713Sgirish NXGE_REG_RD64(handle, TDMC_INJ_PAR_ERR_REG, &inj.value);
186344961713Sgirish *err_bits = (inj.value & TDMC_INJ_PAR_ERR_MASK);
186444961713Sgirish
186544961713Sgirish return (NPI_SUCCESS);
186644961713Sgirish }
186744961713Sgirish
186844961713Sgirish npi_status_t
npi_txdma_dbg_sel_set(npi_handle_t handle,uint8_t dbg_sel)186944961713Sgirish npi_txdma_dbg_sel_set(npi_handle_t handle, uint8_t dbg_sel)
187044961713Sgirish {
187144961713Sgirish tdmc_dbg_sel_t dbg;
187244961713Sgirish
187344961713Sgirish dbg.value = 0;
187444961713Sgirish dbg.bits.ldw.dbg_sel = (dbg_sel & TDMC_DBG_SEL_MASK);
187544961713Sgirish
187644961713Sgirish NXGE_REG_WR64(handle, TDMC_DBG_SEL_REG, dbg.value);
187744961713Sgirish
187844961713Sgirish return (NPI_SUCCESS);
187944961713Sgirish }
188044961713Sgirish
188144961713Sgirish npi_status_t
npi_txdma_training_vector_set(npi_handle_t handle,uint32_t training_vector)188244961713Sgirish npi_txdma_training_vector_set(npi_handle_t handle, uint32_t training_vector)
188344961713Sgirish {
188444961713Sgirish tdmc_training_t vec;
188544961713Sgirish
188644961713Sgirish vec.value = 0;
188744961713Sgirish vec.bits.ldw.vec = training_vector;
188844961713Sgirish
188944961713Sgirish NXGE_REG_WR64(handle, TDMC_TRAINING_REG, vec.value);
189044961713Sgirish
189144961713Sgirish return (NPI_SUCCESS);
189244961713Sgirish }
189344961713Sgirish
189444961713Sgirish /*
189544961713Sgirish * npi_txdma_dump_desc_one(npi_handle_t handle, p_tx_desc_t desc_p,
189644961713Sgirish * int desc_index)
189744961713Sgirish *
189844961713Sgirish * Dumps the contents of transmit descriptors.
189944961713Sgirish *
190044961713Sgirish * Parameters:
190144961713Sgirish * handle - NPI handle (register pointer is the
190244961713Sgirish * descriptor address in memory).
190344961713Sgirish * desc_p - pointer to place the descriptor contents
190444961713Sgirish * desc_index - descriptor index
190544961713Sgirish *
190644961713Sgirish */
190744961713Sgirish /*ARGSUSED*/
190844961713Sgirish void
npi_txdma_dump_desc_one(npi_handle_t handle,p_tx_desc_t desc_p,int desc_index)190944961713Sgirish npi_txdma_dump_desc_one(npi_handle_t handle, p_tx_desc_t desc_p, int desc_index)
191044961713Sgirish {
191144961713Sgirish
1912*86ef0a63SRichard Lowe tx_desc_t desc, *desp;
191344961713Sgirish #ifdef NXGE_DEBUG
191444961713Sgirish uint64_t sad;
191544961713Sgirish int xfer_len;
191644961713Sgirish #endif
191744961713Sgirish
191844961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_TDC_CTL,
191952ccf843Smisaki "\n==> npi_txdma_dump_desc_one: dump "
192052ccf843Smisaki " desc_p $%p descriptor entry %d\n",
192152ccf843Smisaki desc_p, desc_index));
192244961713Sgirish desc.value = 0;
192344961713Sgirish desp = ((desc_p != NULL) ? desc_p : (p_tx_desc_t)&desc);
192444961713Sgirish desp->value = NXGE_MEM_PIO_READ64(handle);
192544961713Sgirish #ifdef NXGE_DEBUG
192644961713Sgirish sad = (desp->value & TX_PKT_DESC_SAD_MASK);
192744961713Sgirish xfer_len = ((desp->value & TX_PKT_DESC_TR_LEN_MASK) >>
192852ccf843Smisaki TX_PKT_DESC_TR_LEN_SHIFT);
192944961713Sgirish #endif
193044961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_TDC_CTL, "\n\t: value 0x%llx\n"
193152ccf843Smisaki "\t\tsad $%p\ttr_len %d len %d\tnptrs %d\tmark %d sop %d\n",
193252ccf843Smisaki desp->value,
193352ccf843Smisaki sad,
193452ccf843Smisaki desp->bits.hdw.tr_len,
193552ccf843Smisaki xfer_len,
193652ccf843Smisaki desp->bits.hdw.num_ptr,
193752ccf843Smisaki desp->bits.hdw.mark,
193852ccf843Smisaki desp->bits.hdw.sop));
193944961713Sgirish
194044961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_TDC_CTL,
194152ccf843Smisaki "\n<== npi_txdma_dump_desc_one: Done \n"));
194244961713Sgirish
194344961713Sgirish }
194444961713Sgirish
194544961713Sgirish /*ARGSUSED*/
194644961713Sgirish void
npi_txdma_dump_hdr(npi_handle_t handle,p_tx_pkt_header_t hdrp)194744961713Sgirish npi_txdma_dump_hdr(npi_handle_t handle, p_tx_pkt_header_t hdrp)
194844961713Sgirish {
194944961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_TDC_CTL,
195052ccf843Smisaki "\n==> npi_txdma_dump_hdr: dump\n"));
195144961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_TDC_CTL,
195252ccf843Smisaki "\n\t: value 0x%llx\n"
195352ccf843Smisaki "\t\tpkttype 0x%x\tip_ver %d\tllc %d\tvlan %d \tihl %d\n"
195452ccf843Smisaki "\t\tl3start %d\tl4start %d\tl4stuff %d\n"
195552ccf843Smisaki "\t\txferlen %d\tpad %d\n",
195652ccf843Smisaki hdrp->value,
195752ccf843Smisaki hdrp->bits.hdw.cksum_en_pkt_type,
195852ccf843Smisaki hdrp->bits.hdw.ip_ver,
195952ccf843Smisaki hdrp->bits.hdw.llc,
196052ccf843Smisaki hdrp->bits.hdw.vlan,
196152ccf843Smisaki hdrp->bits.hdw.ihl,
196252ccf843Smisaki hdrp->bits.hdw.l3start,
196352ccf843Smisaki hdrp->bits.hdw.l4start,
196452ccf843Smisaki hdrp->bits.hdw.l4stuff,
196552ccf843Smisaki hdrp->bits.ldw.tot_xfer_len,
196652ccf843Smisaki hdrp->bits.ldw.pad));
196744961713Sgirish
196844961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_TDC_CTL,
196952ccf843Smisaki "\n<== npi_txdma_dump_hdr: Done \n"));
197044961713Sgirish }
197144961713Sgirish
197244961713Sgirish npi_status_t
npi_txdma_inj_int_error_set(npi_handle_t handle,uint8_t channel,p_tdmc_intr_dbg_t erp)197344961713Sgirish npi_txdma_inj_int_error_set(npi_handle_t handle, uint8_t channel,
1974*86ef0a63SRichard Lowe p_tdmc_intr_dbg_t erp)
197544961713Sgirish {
197644961713Sgirish int status = NPI_SUCCESS;
197744961713Sgirish
1978a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(channel));
197944961713Sgirish if (!TXDMA_CHANNEL_VALID(channel)) {
198044961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
198152ccf843Smisaki " npi_txdma_inj_int_error_set"
198252ccf843Smisaki " Invalid Input: channel <0x%x>",
198352ccf843Smisaki channel));
198444961713Sgirish return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel));
198544961713Sgirish }
198644961713Sgirish
198744961713Sgirish TXDMA_REG_WRITE64(handle, TDMC_INTR_DBG_REG, channel, erp->value);
198844961713Sgirish
198944961713Sgirish return (status);
199044961713Sgirish }
199144961713Sgirish
199244961713Sgirish /*
199344961713Sgirish * Static functions start here.
199444961713Sgirish */
199544961713Sgirish static npi_status_t
npi_txdma_control_reset_wait(npi_handle_t handle,uint8_t channel)199644961713Sgirish npi_txdma_control_reset_wait(npi_handle_t handle, uint8_t channel)
199744961713Sgirish {
199844961713Sgirish
199944961713Sgirish tx_cs_t txcs;
200044961713Sgirish int loop = 0;
200144961713Sgirish
200244961713Sgirish do {
200344961713Sgirish NXGE_DELAY(TXDMA_WAIT_MSEC);
200444961713Sgirish TXDMA_REG_READ64(handle, TX_CS_REG, channel, &txcs.value);
200544961713Sgirish if (!txcs.bits.ldw.rst) {
200644961713Sgirish return (NPI_SUCCESS);
200744961713Sgirish }
200844961713Sgirish loop++;
200944961713Sgirish } while (loop < TXDMA_WAIT_LOOP);
201044961713Sgirish
201144961713Sgirish if (loop == TXDMA_WAIT_LOOP) {
201244961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
201352ccf843Smisaki "npi_txdma_control_reset_wait: RST bit not "
201452ccf843Smisaki "cleared to 0 txcs.bits 0x%llx", txcs.value));
201544961713Sgirish return (NPI_FAILURE | NPI_TXDMA_RESET_FAILED);
201644961713Sgirish }
201744961713Sgirish return (NPI_SUCCESS);
201844961713Sgirish }
201944961713Sgirish
202044961713Sgirish static npi_status_t
npi_txdma_control_stop_wait(npi_handle_t handle,uint8_t channel)202144961713Sgirish npi_txdma_control_stop_wait(npi_handle_t handle, uint8_t channel)
202244961713Sgirish {
202344961713Sgirish tx_cs_t txcs;
202444961713Sgirish int loop = 0;
202544961713Sgirish
202644961713Sgirish do {
202744961713Sgirish NXGE_DELAY(TXDMA_WAIT_MSEC);
202844961713Sgirish TXDMA_REG_READ64(handle, TX_CS_REG, channel, &txcs.value);
202944961713Sgirish if (txcs.bits.ldw.sng_state) {
203044961713Sgirish return (NPI_SUCCESS);
203144961713Sgirish }
203244961713Sgirish loop++;
203344961713Sgirish } while (loop < TXDMA_WAIT_LOOP);
203444961713Sgirish
203544961713Sgirish if (loop == TXDMA_WAIT_LOOP) {
203644961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
203752ccf843Smisaki "npi_txdma_control_stop_wait: SNG_STATE not "
203852ccf843Smisaki "set to 1 txcs.bits 0x%llx", txcs.value));
203944961713Sgirish return (NPI_FAILURE | NPI_TXDMA_STOP_FAILED);
204044961713Sgirish }
204144961713Sgirish
204244961713Sgirish return (NPI_SUCCESS);
204344961713Sgirish }
204444961713Sgirish
204544961713Sgirish static npi_status_t
npi_txdma_control_resume_wait(npi_handle_t handle,uint8_t channel)204644961713Sgirish npi_txdma_control_resume_wait(npi_handle_t handle, uint8_t channel)
204744961713Sgirish {
204844961713Sgirish tx_cs_t txcs;
204944961713Sgirish int loop = 0;
205044961713Sgirish
205144961713Sgirish do {
205244961713Sgirish NXGE_DELAY(TXDMA_WAIT_MSEC);
205344961713Sgirish TXDMA_REG_READ64(handle, TX_CS_REG, channel, &txcs.value);
205444961713Sgirish if (!txcs.bits.ldw.sng_state) {
205544961713Sgirish return (NPI_SUCCESS);
205644961713Sgirish }
205744961713Sgirish loop++;
205844961713Sgirish } while (loop < TXDMA_WAIT_LOOP);
205944961713Sgirish
206044961713Sgirish if (loop == TXDMA_WAIT_LOOP) {
206144961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
206252ccf843Smisaki "npi_txdma_control_resume_wait: sng_state not "
206352ccf843Smisaki "set to 0 txcs.bits 0x%llx", txcs.value));
206444961713Sgirish return (NPI_FAILURE | NPI_TXDMA_RESUME_FAILED);
206544961713Sgirish }
206644961713Sgirish
206744961713Sgirish return (NPI_SUCCESS);
206844961713Sgirish }
2069