14496171girish/*
24496171girish * CDDL HEADER START
34496171girish *
44496171girish * The contents of this file are subject to the terms of the
54496171girish * Common Development and Distribution License (the "License").
64496171girish * You may not use this file except in compliance with the License.
74496171girish *
84496171girish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
94496171girish * or http://www.opensolaris.org/os/licensing.
104496171girish * See the License for the specific language governing permissions
114496171girish * and limitations under the License.
124496171girish *
134496171girish * When distributing Covered Code, include this CDDL HEADER in each
144496171girish * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
154496171girish * If applicable, add the following below this CDDL HEADER, with the
164496171girish * fields enclosed by brackets "[]" replaced with your own identifying
174496171girish * information: Portions Copyright [yyyy] [name of copyright owner]
184496171girish *
194496171girish * CDDL HEADER END
204496171girish */
214496171girish/*
22678453aspeer * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
234496171girish * Use is subject to license terms.
244496171girish */
254496171girish
264496171girish#pragma ident	"%Z%%M%	%I%	%E% SMI"
274496171girish
28a3c5bd6speer#include <npi_txdma.h>
29678453aspeer#include <npi_tx_rd64.h>
30678453aspeer#include <npi_tx_wr64.h>
314496171girish
324496171girish#define	TXDMA_WAIT_LOOP		10000
334496171girish#define	TXDMA_WAIT_MSEC		5
344496171girish
354496171girishstatic npi_status_t npi_txdma_control_reset_wait(npi_handle_t handle,
36a3c5bd6speer	uint8_t channel);
374496171girishstatic npi_status_t npi_txdma_control_stop_wait(npi_handle_t handle,
38a3c5bd6speer	uint8_t channel);
394496171girishstatic npi_status_t npi_txdma_control_resume_wait(npi_handle_t handle,
40a3c5bd6speer	uint8_t channel);
414496171girish
424496171girishuint64_t tdc_dmc_offset[] = {
434496171girish	TX_RNG_CFIG_REG,
444496171girish	TX_RING_HDL_REG,
454496171girish	TX_RING_KICK_REG,
464496171girish	TX_ENT_MSK_REG,
474496171girish	TX_CS_REG,
484496171girish	TXDMA_MBH_REG,
494496171girish	TXDMA_MBL_REG,
504496171girish	TX_DMA_PRE_ST_REG,
514496171girish	TX_RNG_ERR_LOGH_REG,
524496171girish	TX_RNG_ERR_LOGL_REG,
534496171girish	TDMC_INTR_DBG_REG,
544496171girish	TX_CS_DBG_REG
554496171girish};
564496171girish
574496171girishconst char *tdc_dmc_name[] = {
584496171girish	"TX_RNG_CFIG_REG",
594496171girish	"TX_RING_HDL_REG",
604496171girish	"TX_RING_KICK_REG",
614496171girish	"TX_ENT_MSK_REG",
624496171girish	"TX_CS_REG",
634496171girish	"TXDMA_MBH_REG",
644496171girish	"TXDMA_MBL_REG",
654496171girish	"TX_DMA_PRE_ST_REG",
664496171girish	"TX_RNG_ERR_LOGH_REG",
674496171girish	"TX_RNG_ERR_LOGL_REG",
684496171girish	"TDMC_INTR_DBG_REG",
694496171girish	"TX_CS_DBG_REG"
704496171girish};
714496171girish
724496171girishuint64_t tdc_fzc_offset [] = {
734496171girish	TX_LOG_PAGE_VLD_REG,
744496171girish	TX_LOG_PAGE_MASK1_REG,
754496171girish	TX_LOG_PAGE_VAL1_REG,
764496171girish	TX_LOG_PAGE_MASK2_REG,
774496171girish	TX_LOG_PAGE_VAL2_REG,
784496171girish	TX_LOG_PAGE_RELO1_REG,
794496171girish	TX_LOG_PAGE_RELO2_REG,
804496171girish	TX_LOG_PAGE_HDL_REG
814496171girish};
824496171girish
834496171girishconst char *tdc_fzc_name [] = {
844496171girish	"TX_LOG_PAGE_VLD_REG",
854496171girish	"TX_LOG_PAGE_MASK1_REG",
864496171girish	"TX_LOG_PAGE_VAL1_REG",
874496171girish	"TX_LOG_PAGE_MASK2_REG",
884496171girish	"TX_LOG_PAGE_VAL2_REG",
894496171girish	"TX_LOG_PAGE_RELO1_REG",
904496171girish	"TX_LOG_PAGE_RELO2_REG",
914496171girish	"TX_LOG_PAGE_HDL_REG"
924496171girish};
934496171girish
944496171girishuint64_t tx_fzc_offset[] = {
954496171girish	TX_ADDR_MD_REG,
964496171girish	TDMC_INJ_PAR_ERR_REG,
974496171girish	TDMC_DBG_SEL_REG,
98678453aspeer	TDMC_TRAINING_REG,
99678453aspeer	TXC_PORT_DMA_ENABLE_REG,
100678453aspeer	TXC_DMA_MAX_BURST_REG
1014496171girish};
1024496171girish
1034496171girishconst char *tx_fzc_name[] = {
1044496171girish	"TX_ADDR_MD_REG",
1054496171girish	"TDMC_INJ_PAR_ERR_REG",
1064496171girish	"TDMC_DBG_SEL_REG",
107678453aspeer	"TDMC_TRAINING_REG",
108678453aspeer	"TXC_PORT_DMA_ENABLE_REG",
109678453aspeer	"TXC_DMA_MAX_BURST_REG"
1104496171girish};
1114496171girish
112a3c5bd6speer#define	NUM_TDC_DMC_REGS	(sizeof (tdc_dmc_offset) / sizeof (uint64_t))
113a3c5bd6speer#define	NUM_TX_FZC_REGS	(sizeof (tx_fzc_offset) / sizeof (uint64_t))
114a3c5bd6speer
1154496171girish/*
1164496171girish * npi_txdma_dump_tdc_regs
1174496171girish * Dumps the contents of tdc csrs and fzc registers
1184496171girish *
1194496171girish * Input:
1204496171girish *         tdc:      TX DMA number
1214496171girish *
1224496171girish * return:
1234496171girish *     NPI_SUCCESS
1244496171girish *     NPI_FAILURE
1254496171girish *     NPI_TXDMA_CHANNEL_INVALID
1264496171girish *
1274496171girish */
1284496171girishnpi_status_t
1294496171girishnpi_txdma_dump_tdc_regs(npi_handle_t handle, uint8_t tdc)
1304496171girish{
1314496171girish
1324496171girish	uint64_t		value, offset;
1334496171girish	int 			num_regs, i;
1344496171girish
135a3c5bd6speer	ASSERT(TXDMA_CHANNEL_VALID(tdc));
1364496171girish	if (!TXDMA_CHANNEL_VALID(tdc)) {
1374496171girish		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
13852ccf84misaki		    "npi_txdma_dump_tdc_regs"
13952ccf84misaki		    " Invalid TDC number %d \n",
14052ccf84misaki		    tdc));
1414496171girish
1424496171girish		return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(tdc));
1434496171girish	}
1444496171girish
1454496171girish	NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
14652ccf84misaki	    "\nTXDMA DMC Register Dump for Channel %d\n",
14752ccf84misaki	    tdc));
1484496171girish
149a3c5bd6speer	num_regs = NUM_TDC_DMC_REGS;
1504496171girish	for (i = 0; i < num_regs; i++) {
1514496171girish		TXDMA_REG_READ64(handle, tdc_dmc_offset[i], tdc, &value);
1524496171girish		offset = NXGE_TXDMA_OFFSET(tdc_dmc_offset[i], handle.is_vraddr,
15352ccf84misaki		    tdc);
1544496171girish		NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, "0x%08llx "
15552ccf84misaki		    "%s\t 0x%016llx \n",
15652ccf84misaki		    offset, tdc_dmc_name[i],
15752ccf84misaki		    value));
1584496171girish	}
1594496171girish
1604496171girish	NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
16152ccf84misaki	    "\n TXDMA Register Dump for Channel %d done\n", tdc));
1624496171girish
1634496171girish	return (NPI_SUCCESS);
1644496171girish}
1654496171girish
1664496171girish/*
1674496171girish * npi_txdma_dump_fzc_regs
1684496171girish * Dumps the contents of tdc csrs and fzc registers
1694496171girish *
1704496171girish * Input:
1714496171girish *         tdc:      TX DMA number
1724496171girish *
1734496171girish * return:
1744496171girish *     NPI_SUCCESS
1754496171girish *     NPI_FAILURE
1764496171girish *     NPI_TXDMA_CHANNEL_INVALID
1774496171girish *
1784496171girish */
1794496171girishnpi_status_t
1804496171girishnpi_txdma_dump_fzc_regs(npi_handle_t handle)
1814496171girish{
1824496171girish
1834496171girish	uint64_t value;
1844496171girish	int num_regs, i;
1854496171girish
1864496171girish	NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
18752ccf84misaki	    "\nFZC_DMC Common Register Dump\n"));
1884496171girish
189a3c5bd6speer	num_regs = NUM_TX_FZC_REGS;
1904496171girish	for (i = 0; i < num_regs; i++) {
191adfcba5joycey#if defined(__i386)
192adfcba5joycey		NXGE_REG_RD64(handle, (uint32_t)tx_fzc_offset[i], &value);
193adfcba5joycey#else
1944496171girish		NXGE_REG_RD64(handle, tx_fzc_offset[i], &value);
195adfcba5joycey#endif
1964496171girish		NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, "0x%08llx "
19752ccf84misaki		    "%s\t 0x%08llx \n",
19852ccf84misaki		    tx_fzc_offset[i],
19952ccf84misaki		    tx_fzc_name[i], value));
2004496171girish	}
2014496171girish	NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
20252ccf84misaki	    "\n TXDMA FZC_DMC Register Dump Done \n"));
2034496171girish
2044496171girish	return (NPI_SUCCESS);
2054496171girish}
2064496171girish
2074496171girishnpi_status_t
2084496171girishnpi_txdma_tdc_regs_zero(npi_handle_t handle, uint8_t tdc)
2094496171girish{
2104496171girish	uint64_t		value;
2114496171girish	int 			num_regs, i;
2124496171girish
213a3c5bd6speer	ASSERT(TXDMA_CHANNEL_VALID(tdc));
2144496171girish	if (!TXDMA_CHANNEL_VALID(tdc)) {
2154496171girish		NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
21652ccf84misaki		    "npi_txdma_tdc_regs_zero"
21752ccf84misaki		    " InvaliInvalid TDC number %d \n",
21852ccf84misaki		    tdc));
2194496171girish		return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(tdc));
2204496171girish	}
2214496171girish
2224496171girish	NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
22352ccf84misaki	    "\nTXDMA DMC Register (zero) for Channel %d\n",
22452ccf84misaki	    tdc));
2254496171girish
226a3c5bd6speer	num_regs = NUM_TDC_DMC_REGS;
2274496171girish	value = 0;
2284496171girish	for (i = 0; i < num_regs; i++) {
229adfcba5joycey		TXDMA_REG_WRITE64(handle, tdc_dmc_offset[i], tdc, value);
2304496171girish	}
2314496171girish
2324496171girish	NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
23352ccf84misaki	    "\nTXDMA FZC_DMC Register clear for Channel %d\n",
23452ccf84misaki	    tdc));
2354496171girish
2364496171girish	NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
23752ccf84misaki	    "\n TXDMA Register Clear to 0s for Channel %d done\n", tdc));
2384496171girish
2394496171girish	return (NPI_SUCCESS);
2404496171girish}
2414496171girish
2424496171girish/*
2434496171girish * npi_txdma_address_mode32_set():
2444496171girish *	This function is called to only support 32 bit addressing.
2454496171girish *
2464496171girish * Parameters:
2474496171girish *	handle		- NPI handle
2484496171girish *	mode_enable	- B_TRUE  (enable 32 bit mode)
2494496171girish *			  B_FALSE (disable 32 bit mode)
2504496171girish *
2514496171girish * Return:
2524496171girish *	NPI_SUCCESS		- If set is complete successfully.
2534496171girish *
2544496171girish *	Error:
2554496171girish *	NONE
2564496171girish */
2574496171girishnpi_status_t
2584496171girishnpi_txdma_mode32_set(npi_handle_t handle, boolean_t mode_enable)
2594496171girish{
2604496171girish	tx_addr_md_t		mode32;
2614496171girish
2624496171girish	mode32.value = 0;
2634496171girish	if (mode_enable) {
2644496171girish		mode32.bits.ldw.mode32 = 1;
2654496171girish	} else {
2664496171girish		mode32.bits.ldw.mode32 = 0;
2674496171girish	}
2684496171girish	NXGE_REG_WR64(handle, TX_ADDR_MD_REG, mode32.value);
2694496171girish
2704496171girish	return (NPI_SUCCESS);
2714496171girish}
2724496171girish
2734496171girish/*
2744496171girish * npi_txdma_log_page_set():
2754496171girish *	This function is called to configure a logical page
2764496171girish *	(valid bit, mask, value, relocation).
2774496171girish *
2784496171girish * Parameters:
2794496171girish *	handle		- NPI handle
2804496171girish *	cfgp		- pointer to NPI defined data structure:
2814496171girish *				- page valid
2824496171girish * 				- mask
2834496171girish *				- value
2844496171girish *				- relocation
2854496171girish *	channel		- hardware TXDMA channel from 0 to 23.
2864496171girish *
2874496171girish * Return:
2884496171girish *	NPI_SUCCESS		- If configurations are set successfully.
2894496171girish *
2904496171girish *	Error:
2914496171girish *	NPI_FAILURE -
2924496171girish *		NPI_TXDMA_CHANNEL_INVALID	-
2934496171girish *		NPI_TXDMA_FUNC_INVALID	-
2944496171girish *		NPI_TXDMA_PAGE_INVALID	-
2954496171girish */
2964496171girishnpi_status_t
2974496171girishnpi_txdma_log_page_set(npi_handle_t handle, uint8_t channel,
2984496171girish		p_dma_log_page_t cfgp)
2994496171girish{
3004496171girish	log_page_vld_t		vld;
3014496171girish	int			status;
3024496171girish	uint64_t		val;
3034496171girish	dma_log_page_t		cfg;
3044496171girish
3054496171girish	DMA_LOG_PAGE_FN_VALIDATE(channel, cfgp->page_num, cfgp->func_num,
30652ccf84misaki	    status);
3074496171girish	if (status) {
3084496171girish		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
30952ccf84misaki		    " npi_txdma_log_page_set"
31052ccf84misaki		    " npi_status <0x%x>", status));
3114496171girish		return (status);
3124496171girish	}
3134496171girish
3144496171girish	TX_LOG_REG_WRITE64(handle, TX_LOG_PAGE_VLD_REG, channel, 0);
3154496171girish	TX_LOG_REG_READ64(handle, TX_LOG_PAGE_VLD_REG, channel, &val);
3164496171girish
3174496171girish	NPI_DEBUG_MSG((handle.function, NPI_TDC_CTL,
31852ccf84misaki	    "\n==> npi_txdma_log_page_set: WRITE 0 and "
31952ccf84misaki	    " READ back 0x%llx\n ", val));
3204496171girish
3214496171girish	vld.value = 0;
3224496171girish	TX_LOG_REG_READ64(handle, TX_LOG_PAGE_VLD_REG, channel, &val);
3234496171girish
3244496171girish	val &= 0x3;
3254496171girish	vld.value |= val;
3264496171girish
3274496171girish	vld.value = 0;
3284496171girish	vld.bits.ldw.func = cfgp->func_num;
3294496171girish
3304496171girish	if (!cfgp->page_num) {
3314496171girish		TX_LOG_REG_WRITE64(handle, TX_LOG_PAGE_MASK1_REG,
33252ccf84misaki		    channel, (cfgp->mask & DMA_LOG_PAGE_MASK_MASK));
3334496171girish		TX_LOG_REG_WRITE64(handle, TX_LOG_PAGE_VAL1_REG,
33452ccf84misaki		    channel, (cfgp->value & DMA_LOG_PAGE_VALUE_MASK));
3354496171girish		TX_LOG_REG_WRITE64(handle, TX_LOG_PAGE_RELO1_REG,
33652ccf84misaki		    channel, (cfgp->reloc & DMA_LOG_PAGE_RELO_MASK));
3374496171girish	} else {
3384496171girish		TX_LOG_REG_WRITE64(handle, TX_LOG_PAGE_MASK2_REG,
33952ccf84misaki		    channel, (cfgp->mask & DMA_LOG_PAGE_MASK_MASK));
3404496171girish		TX_LOG_REG_WRITE64(handle, TX_LOG_PAGE_VAL2_REG,
34152ccf84misaki		    channel, (cfgp->value & DMA_LOG_PAGE_VALUE_MASK));
3424496171girish		TX_LOG_REG_WRITE64(handle, TX_LOG_PAGE_RELO2_REG,
34352ccf84misaki		    channel, (cfgp->reloc & DMA_LOG_PAGE_RELO_MASK));
3444496171girish	}
3454496171girish
3464496171girish	TX_LOG_REG_WRITE64(handle, TX_LOG_PAGE_VLD_REG, channel,
34752ccf84misaki	    vld.value | (cfgp->valid << cfgp->page_num));
3484496171girish
3494496171girish	NPI_DEBUG_MSG((handle.function, NPI_REG_CTL,
35052ccf84misaki	    "\n==> npi_txdma_log_page_set: vld value "
35152ccf84misaki	    " 0x%llx function %d page_valid01 0x%x\n",
35252ccf84misaki	    vld.value,
35352ccf84misaki	    vld.bits.ldw.func,
35452ccf84misaki	    (cfgp->valid << cfgp->page_num)));
3554496171girish
3564496171girish
3574496171girish	cfg.page_num = 0;
3584496171girish	cfg.func_num = 0;
3594496171girish	(void) npi_txdma_log_page_get(handle, channel, &cfg);
3604496171girish	cfg.page_num = 1;
3614496171girish	(void) npi_txdma_log_page_get(handle, channel, &cfg);
3624496171girish
3634496171girish	return (status);
3644496171girish}
3654496171girish
3664496171girish/*
3674496171girish * npi_txdma_log_page_get():
3684496171girish *	This function is called to get a logical page
3694496171girish *	(valid bit, mask, value, relocation).
3704496171girish *
3714496171girish * Parameters:
3724496171girish *	handle		- NPI handle
3734496171girish *	cfgp		- Get the following values (NPI defined structure):
3744496171girish *				- page valid
3754496171girish * 				- mask
3764496171girish *				- value
3774496171girish *				- relocation
3784496171girish *	channel		- hardware TXDMA channel from 0 to 23.
3794496171girish *
3804496171girish * Return:
3814496171girish *	NPI_SUCCESS		- If configurations are read successfully.
3824496171girish *
3834496171girish *	Error:
3844496171girish *	NPI_FAILURE -
3854496171girish *		NPI_TXDMA_CHANNEL_INVALID	-
3864496171girish *		NPI_TXDMA_FUNC_INVALID	-
3874496171girish *		NPI_TXDMA_PAGE_INVALID	-
3884496171girish */
3894496171girishnpi_status_t
3904496171girishnpi_txdma_log_page_get(npi_handle_t handle, uint8_t channel,
3914496171girish		p_dma_log_page_t cfgp)
3924496171girish{
3934496171girish	log_page_vld_t		vld;
3944496171girish	int			status;
3954496171girish	uint64_t		val;
3964496171girish
3974496171girish	DMA_LOG_PAGE_VALIDATE(channel, cfgp->page_num, status);
3984496171girish	if (status) {
3994496171girish		NPI_ERROR_MSG((handle.function, NPI_REG_CTL,
40052ccf84misaki		    " npi_txdma_log_page_get"
40152ccf84misaki		    " npi_status <0x%x>", status));
4024496171girish		return (status);
4034496171girish	}
4044496171girish
4054496171girish	vld.value = 0;
4064496171girish	vld.bits.ldw.func = cfgp->func_num;
4074496171girish	TX_LOG_REG_READ64(handle, TX_LOG_PAGE_VLD_REG, channel, &val);
4084496171girish
4094496171girish	NPI_DEBUG_MSG((handle.function, NPI_TDC_CTL,
41052ccf84misaki	    "\n==> npi_txdma_log_page_get: read value "
41152ccf84misaki	    " function %d  value 0x%llx\n",
41252ccf84misaki	    cfgp->func_num, val));
4134496171girish
4144496171girish	vld.value |= val;
4154496171girish	cfgp->func_num = vld.bits.ldw.func;
4164496171girish
4174496171girish	if (!cfgp->page_num) {
4184496171girish		TX_LOG_REG_READ64(handle, TX_LOG_PAGE_MASK1_REG, channel, &val);
4194496171girish		cfgp->mask = val & DMA_LOG_PAGE_MASK_MASK;
4204496171girish		TX_LOG_REG_READ64(handle, TX_LOG_PAGE_VAL1_REG, channel, &val);
4214496171girish		cfgp->value = val & DMA_LOG_PAGE_VALUE_MASK;
4224496171girish		TX_LOG_REG_READ64(handle, TX_LOG_PAGE_RELO1_REG, channel, &val);
4234496171girish		cfgp->reloc = val & DMA_LOG_PAGE_RELO_MASK;
4244496171girish		cfgp->valid = vld.bits.ldw.page0;
4254496171girish	} else {
4264496171girish		TX_LOG_REG_READ64(handle, TX_LOG_PAGE_MASK2_REG, channel, &val);
4274496171girish		cfgp->mask = val & DMA_LOG_PAGE_MASK_MASK;
4284496171girish		TX_LOG_REG_READ64(handle, TX_LOG_PAGE_VAL2_REG, channel, &val);
4294496171girish		cfgp->value = val & DMA_LOG_PAGE_VALUE_MASK;
4304496171girish		TX_LOG_REG_READ64(handle, TX_LOG_PAGE_RELO2_REG, channel, &val);
4314496171girish		cfgp->reloc = val & DMA_LOG_PAGE_RELO_MASK;
4324496171girish		cfgp->valid = vld.bits.ldw.page1;
4334496171girish	}
4344496171girish
4354496171girish	return (status);
4364496171girish}
4374496171girish
4384496171girish/*
4394496171girish * npi_txdma_log_page_handle_set():
4404496171girish *	This function is called to program a page handle
4414496171girish *	(bits [63:44] of a 64-bit address to generate
4424496171girish *	a 64 bit address)
4434496171girish *
4444496171girish * Parameters:
4454496171girish *	handle		- NPI handle
4464496171girish *	hdl_p		- pointer to a logical page handle
4474496171girish *			  hardware data structure (log_page_hdl_t).
4484496171girish *	channel		- hardware TXDMA channel from 0 to 23.
4494496171girish *
4504496171girish * Return:
4514496171girish *	NPI_SUCCESS		- If configurations are set successfully.
4524496171girish *
4534496171girish *	Error:
4544496171girish *	NPI_FAILURE -
4554496171girish *		NPI_TXDMA_CHANNEL_INVALID	-
4564496171girish *		NPI_TXDMA_FUNC_INVALID	-
4574496171girish *		NPI_TXDMA_PAGE_INVALID	-
4584496171girish */
4594496171girishnpi_status_t
4604496171girishnpi_txdma_log_page_handle_set(npi_handle_t handle, uint8_t channel,
4614496171girish		p_log_page_hdl_t hdl_p)
4624496171girish{
4634496171girish	int			status = NPI_SUCCESS;
4644496171girish
465a3c5bd6speer	ASSERT(TXDMA_CHANNEL_VALID(channel));
4664496171girish	if (!TXDMA_CHANNEL_VALID(channel)) {
4674496171girish		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
46852ccf84misaki		    " npi_txdma_log_page_handle_set"
46952ccf84misaki		    " Invalid Input: channel <0x%x>",
47052ccf84misaki		    channel));
4714496171girish		return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel));
4724496171girish	}
4734496171girish
4744496171girish	TX_LOG_REG_WRITE64(handle, TX_LOG_PAGE_HDL_REG,
47552ccf84misaki	    channel, hdl_p->value);
4764496171girish
4774496171girish	return (status);
4784496171girish}
4794496171girish
4804496171girish/*
4814496171girish * npi_txdma_log_page_config():
4824496171girish *	This function is called to IO operations on
4834496171girish *	 a logical page to set, get, clear
4844496171girish *	valid bit, mask, value, relocation).
4854496171girish *
4864496171girish * Parameters:
4874496171girish *	handle		- NPI handle
4884496171girish *	op_mode		- OP_GET, OP_SET, OP_CLEAR
4894496171girish *	type		- NPI specific config type
4904496171girish *			   TXDMA_LOG_PAGE_MASK
4914496171girish *			   TXDMA_LOG_PAGE_VALUE
4924496171girish *			   TXDMA_LOG_PAGE_RELOC
4934496171girish *			   TXDMA_LOG_PAGE_VALID
4944496171girish *			   TXDMA_LOG_PAGE_ALL
4954496171girish *	channel		- hardware TXDMA channel from 0 to 23.
4964496171girish *	cfgp		- pointer to the NPI config structure.
4974496171girish * Return:
4984496171girish *	NPI_SUCCESS		- If configurations are read successfully.
4994496171girish *
5004496171girish *	Error:
5014496171girish *	NPI_FAILURE		-
5024496171girish *		NPI_TXDMA_OPCODE_INVALID	-
5034496171girish *		NPI_TXDMA_CHANNEL_INVALID	-
5044496171girish *		NPI_TXDMA_FUNC_INVALID	-
5054496171girish *		NPI_TXDMA_PAGE_INVALID	-
5064496171girish */
5074496171girishnpi_status_t
5084496171girishnpi_txdma_log_page_config(npi_handle_t handle, io_op_t op_mode,
5094496171girish		txdma_log_cfg_t type, uint8_t channel,
5104496171girish		p_dma_log_page_t cfgp)
5114496171girish{
5124496171girish	int			status = NPI_SUCCESS;
5134496171girish	uint64_t		val;
5144496171girish
515a3c5bd6speer	ASSERT(TXDMA_CHANNEL_VALID(channel));
5164496171girish	if (!TXDMA_CHANNEL_VALID(channel)) {
5174496171girish		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
51852ccf84misaki		    " npi_txdma_log_page_config"
51952ccf84misaki		    " Invalid Input: channel <0x%x>",
52052ccf84misaki		    channel));
5214496171girish		return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel));
5224496171girish	}
5234496171girish
5244496171girish	switch (op_mode) {
5254496171girish	case OP_GET:
5264496171girish		switch (type) {
5274496171girish		case TXDMA_LOG_PAGE_ALL:
5284496171girish			return (npi_txdma_log_page_get(handle, channel,
52952ccf84misaki			    cfgp));
5304496171girish		case TXDMA_LOG_PAGE_MASK:
5314496171girish			if (!cfgp->page_num) {
5324496171girish				TX_LOG_REG_READ64(handle, TX_LOG_PAGE_MASK1_REG,
53352ccf84misaki				    channel, &val);
5344496171girish				cfgp->mask = val & DMA_LOG_PAGE_MASK_MASK;
5354496171girish			} else {
5364496171girish				TX_LOG_REG_READ64(handle, TX_LOG_PAGE_MASK2_REG,
53752ccf84misaki				    channel, &val);
5384496171girish				cfgp->mask = val & DMA_LOG_PAGE_MASK_MASK;
5394496171girish			}
5404496171girish			break;
5414496171girish
5424496171girish		case TXDMA_LOG_PAGE_VALUE:
5434496171girish			if (!cfgp->page_num) {
5444496171girish				TX_LOG_REG_READ64(handle, TX_LOG_PAGE_VAL1_REG,
54552ccf84misaki				    channel, &val);
5464496171girish				cfgp->value = val & DMA_LOG_PAGE_VALUE_MASK;
5474496171girish			} else {
5484496171girish				TX_LOG_REG_READ64(handle, TX_LOG_PAGE_VAL2_REG,
54952ccf84misaki				    channel, &val);
5504496171girish				cfgp->value = val & DMA_LOG_PAGE_VALUE_MASK;
5514496171girish			}
5524496171girish			break;
5534496171girish
5544496171girish		case TXDMA_LOG_PAGE_RELOC:
5554496171girish			if (!cfgp->page_num) {
5564496171girish				TX_LOG_REG_READ64(handle, TX_LOG_PAGE_RELO1_REG,
55752ccf84misaki				    channel, &val);
5584496171girish				cfgp->reloc = val & DMA_LOG_PAGE_RELO_MASK;
5594496171girish			} else {
5604496171girish				TX_LOG_REG_READ64(handle, TX_LOG_PAGE_VAL2_REG,
56152ccf84misaki				    channel, &val);
5624496171girish				cfgp->reloc = val & DMA_LOG_PAGE_RELO_MASK;
5634496171girish			}
5644496171girish			break;
5654496171girish
5664496171girish		default:
5674496171girish			NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
56852ccf84misaki			    " npi_txdma_log_page_config"
56952ccf84misaki			    " Invalid Input: pageconfig <0x%x>",
57052ccf84misaki			    type));
5714496171girish			return (NPI_FAILURE |
57252ccf84misaki			    NPI_TXDMA_OPCODE_INVALID(channel));
5734496171girish		}
5744496171girish
5754496171girish		break;
5764496171girish
5774496171girish	case OP_SET:
5784496171girish	case OP_CLEAR:
5794496171girish		if (op_mode == OP_CLEAR) {
5804496171girish			cfgp->valid = 0;
5814496171girish			cfgp->mask = cfgp->func_num = 0;
5824496171girish			cfgp->value = cfgp->reloc = 0;
5834496171girish		}
5844496171girish		switch (type) {
5854496171girish		case TXDMA_LOG_PAGE_ALL:
5864496171girish			return (npi_txdma_log_page_set(handle, channel,
58752ccf84misaki			    cfgp));
5884496171girish		case TXDMA_LOG_PAGE_MASK:
5894496171girish			if (!cfgp->page_num) {
5904496171girish				TX_LOG_REG_WRITE64(handle,
59152ccf84misaki				    TX_LOG_PAGE_MASK1_REG, channel,
59252ccf84misaki				    (cfgp->mask & DMA_LOG_PAGE_MASK_MASK));
5934496171girish			} else {
5944496171girish				TX_LOG_REG_WRITE64(handle,
59552ccf84misaki				    TX_LOG_PAGE_MASK2_REG, channel,
59652ccf84misaki				    (cfgp->mask & DMA_LOG_PAGE_MASK_MASK));
5974496171girish			}
5984496171girish			break;
5994496171girish
6004496171girish		case TXDMA_LOG_PAGE_VALUE:
6014496171girish			if (!cfgp->page_num) {
6024496171girish				TX_LOG_REG_WRITE64(handle,
60352ccf84misaki				    TX_LOG_PAGE_VAL1_REG, channel,
60452ccf84misaki				    (cfgp->value & DMA_LOG_PAGE_VALUE_MASK));
6054496171girish			} else {
6064496171girish				TX_LOG_REG_WRITE64(handle,
60752ccf84misaki				    TX_LOG_PAGE_VAL2_REG, channel,
60852ccf84misaki				    (cfgp->value & DMA_LOG_PAGE_VALUE_MASK));
6094496171girish			}
6104496171girish			break;
6114496171girish
6124496171girish		case TXDMA_LOG_PAGE_RELOC:
6134496171girish			if (!cfgp->page_num) {
6144496171girish				TX_LOG_REG_WRITE64(handle,
61552ccf84misaki				    TX_LOG_PAGE_RELO1_REG, channel,
61652ccf84misaki				    (cfgp->reloc & DMA_LOG_PAGE_RELO_MASK));
6174496171girish			} else {
6184496171girish				TX_LOG_REG_WRITE64(handle,
61952ccf84misaki				    TX_LOG_PAGE_RELO2_REG, channel,
62052ccf84misaki				    (cfgp->reloc & DMA_LOG_PAGE_RELO_MASK));
6214496171girish			}
6224496171girish			break;
6234496171girish
6244496171girish		default:
6254496171girish			NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
62652ccf84misaki			    " npi_txdma_log_page_config"
62752ccf84misaki			    " Invalid Input: pageconfig <0x%x>",
62852ccf84misaki			    type));
6294496171girish			return (NPI_FAILURE |
63052ccf84misaki			    NPI_TXDMA_OPCODE_INVALID(channel));
6314496171girish		}
6324496171girish
6334496171girish		break;
6344496171girish	default:
6354496171girish		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
63652ccf84misaki		    " npi_txdma_log_page_config"
63752ccf84misaki		    " Invalid Input: op <0x%x>",
63852ccf84misaki		    op_mode));
6394496171girish		return (NPI_FAILURE | NPI_TXDMA_OPCODE_INVALID(channel));
6404496171girish	}
6414496171girish
6424496171girish	return (status);
6434496171girish}
6444496171girish
6454496171girish/*
6464496171girish * npi_txdma_log_page_vld_config():
6474496171girish *	This function is called to configure the logical
6484496171girish *	page valid register.
6494496171girish *
6504496171girish * Parameters:
6514496171girish *	handle		- NPI handle
6524496171girish *	op_mode		- OP_GET: get valid page configuration
6534496171girish *			  OP_SET: set valid page configuration
6544496171girish *			  OP_UPDATE: update valid page configuration
6554496171girish *			  OP_CLEAR: reset both valid pages to
6564496171girish *			  not defined (0).
6574496171girish *	channel		- hardware TXDMA channel from 0 to 23.
6584496171girish *	vld_p		- pointer to hardware defined log page valid register.
6594496171girish * Return:
6604496171girish *	NPI_SUCCESS		- If set is complete successfully.
6614496171girish *
6624496171girish *	Error:
6634496171girish *	NPI_FAILURE -
6644496171girish *		NPI_TXDMA_CHANNEL_INVALID -
6654496171girish *		NPI_TXDMA_OPCODE_INVALID -
6664496171girish */
6674496171girishnpi_status_t
6684496171girishnpi_txdma_log_page_vld_config(npi_handle_t handle, io_op_t op_mode,
6694496171girish		uint8_t channel, p_log_page_vld_t vld_p)
6704496171girish{
6714496171girish	int			status = NPI_SUCCESS;
6724496171girish	log_page_vld_t		vld;
6734496171girish
674a3c5bd6speer	ASSERT(TXDMA_CHANNEL_VALID(channel));
6754496171girish	if (!TXDMA_CHANNEL_VALID(channel)) {
6764496171girish		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
67752ccf84misaki		    " npi_txdma_log_page_vld_config"
67852ccf84misaki		    " Invalid Input: channel <0x%x>",
67952ccf84misaki		    channel));
6804496171girish		return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel));
6814496171girish	}
6824496171girish
6834496171girish	switch (op_mode) {
6844496171girish	case OP_GET:
6854496171girish		TX_LOG_REG_READ64(handle, TX_LOG_PAGE_VLD_REG, channel,
68652ccf84misaki		    &vld_p->value);
6874496171girish		break;
6884496171girish
6894496171girish	case OP_SET:
6904496171girish		TX_LOG_REG_WRITE64(handle, TX_LOG_PAGE_VLD_REG,
69152ccf84misaki		    channel, vld_p->value);
6924496171girish		break;
6934496171girish
6944496171girish	case OP_UPDATE:
6954496171girish		TX_LOG_REG_READ64(handle, TX_LOG_PAGE_VLD_REG, channel,
69652ccf84misaki		    &vld.value);
6974496171girish		TX_LOG_REG_WRITE64(handle, TX_LOG_PAGE_VLD_REG,
69852ccf84misaki		    channel, vld.value | vld_p->value);
6994496171girish		break;
7004496171girish
7014496171girish	case OP_CLEAR:
7024496171girish		TX_LOG_REG_WRITE64(handle, TX_LOG_PAGE_VLD_REG,
70352ccf84misaki		    channel, 0);
7044496171girish		break;
7054496171girish
7064496171girish	default:
7074496171girish		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
70852ccf84misaki		    " npi_txdma_log_pag_vld_cofig"
70952ccf84misaki		    " Invalid Input: pagevld <0x%x>",
71052ccf84misaki		    op_mode));
7114496171girish		return (NPI_FAILURE | NPI_TXDMA_OPCODE_INVALID(channel));
7124496171girish	}
7134496171girish
7144496171girish	return (status);
7154496171girish}
7164496171girish
7174496171girish/*
7184496171girish * npi_txdma_channel_reset():
7194496171girish *	This function is called to reset a transmit DMA channel.
7204496171girish *	(This function is used to reset a channel and reinitialize
7214496171girish *	 all other bits except RST_STATE).
7224496171girish *
7234496171girish * Parameters:
7244496171girish *	handle		- NPI handle (virtualization flag must be defined).
7254496171girish *	channel		- logical TXDMA channel from 0 to 23.
7264496171girish *			  (If virtualization flag is not set, then
7274496171girish *			   logical channel is the same as the hardware
7284496171girish *			   channel number).
7294496171girish *
7304496171girish * Return:
7314496171girish *	NPI_SUCCESS		- If reset is complete successfully.
7324496171girish *
7334496171girish *	Error:
7344496171girish *	NPI_FAILURE	-
7354496171girish *		NPI_TXDMA_CHANNEL_INVALID -
7364496171girish *		NPI_TXDMA_RESET_FAILED -
7374496171girish */
7384496171girishnpi_status_t
7394496171girishnpi_txdma_channel_reset(npi_handle_t handle, uint8_t channel)
7404496171girish{
7414496171girish	NPI_DEBUG_MSG((handle.function, NPI_TDC_CTL,
74252ccf84misaki	    " npi_txdma_channel_reset"
74352ccf84misaki	    " RESETTING",
74452ccf84misaki	    channel));
7454496171girish	return (npi_txdma_channel_control(handle, TXDMA_RESET, channel));
7464496171girish}
7474496171girish
7484496171girish/*
7494496171girish * npi_txdma_channel_init_enable():
7504496171girish *	This function is called to start a transmit DMA channel after reset.
7514496171girish *
7524496171girish * Parameters:
7534496171girish *	handle		- NPI handle (virtualization flag must be defined).
7544496171girish *	channel		- logical TXDMA channel from 0 to 23.
7554496171girish *			  (If virtualization flag is not set, then
7564496171girish *			   logical channel is the same as the hardware
7574496171girish *			   channel number).
7584496171girish * Return:
7594496171girish *	NPI_SUCCESS		- If DMA channel is started successfully.
7604496171girish *
7614496171girish *	Error:
7624496171girish *	NPI_FAILURE	-
7634496171girish *		NPI_TXDMA_CHANNEL_INVALID -
7644496171girish */
7654496171girishnpi_status_t
7664496171girishnpi_txdma_channel_init_enable(npi_handle_t handle, uint8_t channel)
7674496171girish{
7684496171girish	return (npi_txdma_channel_control(handle, TXDMA_INIT_START, channel));
7694496171girish}
7704496171girish
7714496171girish/*
7724496171girish * npi_txdma_channel_enable():
7734496171girish *	This function is called to start a transmit DMA channel.
7744496171girish *
7754496171girish * Parameters:
7764496171girish *	handle		- NPI handle (virtualization flag must be defined).
7774496171girish *	channel		- logical TXDMA channel from 0 to 23.
7784496171girish *			  (If virtualization flag is not set, then
7794496171girish *			   logical channel is the same as the hardware
7804496171girish *			   channel number).
7814496171girish * Return:
7824496171girish *	NPI_SUCCESS		- If DMA channel is stopped successfully.
7834496171girish *
7844496171girish *	Error:
7854496171girish *	NPI_FAILURE	-
7864496171girish *		NPI_TXDMA_CHANNEL_INVALID -
7874496171girish */
7884496171girish
7894496171girishnpi_status_t
7904496171girishnpi_txdma_channel_enable(npi_handle_t handle, uint8_t channel)
7914496171girish{
7924496171girish	return (npi_txdma_channel_control(handle, TXDMA_START, channel));
7934496171girish}
7944496171girish
7954496171girish/*
7964496171girish * npi_txdma_channel_disable():
7974496171girish *	This function is called to stop a transmit DMA channel.
7984496171girish *
7994496171girish * Parameters:
8004496171girish *	handle		- NPI handle (virtualization flag must be defined).
8014496171girish *	channel		- logical TXDMA channel from 0 to 23.
8024496171girish *			  (If virtualization flag is not set, then
8034496171girish *			   logical channel is the same as the hardware
8044496171girish *			   channel number).
8054496171girish * Return:
8064496171girish *	NPI_SUCCESS		- If DMA channel is stopped successfully.
8074496171girish *
8084496171girish *	Error:
8094496171girish *	NPI_FAILURE	-
8104496171girish *		NPI_TXDMA_CHANNEL_INVALID -
8114496171girish *		NPI_TXDMA_STOP_FAILED -
8124496171girish */
8134496171girishnpi_status_t
8144496171girishnpi_txdma_channel_disable(npi_handle_t handle, uint8_t channel)
8154496171girish{
8164496171girish	return (npi_txdma_channel_control(handle, TXDMA_STOP, channel));
8174496171girish}
8184496171girish
8194496171girish/*
8204496171girish * npi_txdma_channel_resume():
8214496171girish *	This function is called to restart a transmit DMA channel.
8224496171girish *
8234496171girish * Parameters:
8244496171girish *	handle		- NPI handle (virtualization flag must be defined).
8254496171girish *	channel		- logical TXDMA channel from 0 to 23.
8264496171girish *			  (If virtualization flag is not set, then
8274496171girish *			   logical channel is the same as the hardware
8284496171girish *			   channel number).
8294496171girish * Return:
8304496171girish *	NPI_SUCCESS		- If DMA channel is stopped successfully.
8314496171girish *
8324496171girish *	Error:
8334496171girish *	NPI_FAILURE	-
8344496171girish *		NPI_TXDMA_CHANNEL_INVALID -
8354496171girish *		NPI_TXDMA_RESUME_FAILED -
8364496171girish */
8374496171girishnpi_status_t
8384496171girishnpi_txdma_channel_resume(npi_handle_t handle, uint8_t channel)
8394496171girish{
8404496171girish	return (npi_txdma_channel_control(handle, TXDMA_RESUME, channel));
8414496171girish}
8424496171girish
8434496171girish/*
8444496171girish * npi_txdma_channel_mmk_clear():
8454496171girish *	This function is called to clear MMK bit.
8464496171girish *
8474496171girish * Parameters:
8484496171girish *	handle		- NPI handle (virtualization flag must be defined).
8494496171girish *	channel		- logical TXDMA channel from 0 to 23.
8504496171girish *			  (If virtualization flag is not set, then
8514496171girish *			   logical channel is the same as the hardware
8524496171girish *			   channel number).
8534496171girish * Return:
8544496171girish *	NPI_SUCCESS		- If MMK is reset successfully.
8554496171girish *
8564496171girish *	Error:
8574496171girish *	NPI_FAILURE	-
8584496171girish *		NPI_TXDMA_CHANNEL_INVALID -
8594496171girish */
8604496171girishnpi_status_t
8614496171girishnpi_txdma_channel_mmk_clear(npi_handle_t handle, uint8_t channel)
8624496171girish{
8634496171girish	return (npi_txdma_channel_control(handle, TXDMA_CLEAR_MMK, channel));
8644496171girish}
8654496171girish
8664496171girish/*
8674496171girish * npi_txdma_channel_mbox_enable():
8684496171girish *	This function is called to enable the mailbox update.
8694496171girish *
8704496171girish * Parameters:
8714496171girish *	handle		- NPI handle (virtualization flag must be defined).
8724496171girish *	channel		- logical TXDMA channel from 0 to 23.
8734496171girish *			  (If virtualization flag is not set, then
8744496171girish *			   logical channel is the same as the hardware
8754496171girish *			   channel number).
8764496171girish * Return:
8774496171girish *	NPI_SUCCESS		- If mailbox is enabled successfully.
8784496171girish *
8794496171girish *	Error:
8804496171girish *	NPI_HW_ERROR		-
8814496171girish *	NPI_FAILURE	-
8824496171girish *		NPI_TXDMA_CHANNEL_INVALID -
8834496171girish */
8844496171girishnpi_status_t
8854496171girishnpi_txdma_channel_mbox_enable(npi_handle_t handle, uint8_t channel)
8864496171girish{
8874496171girish	return (npi_txdma_channel_control(handle, TXDMA_MBOX_ENABLE, channel));
8884496171girish}
8894496171girish
8904496171girish/*
8914496171girish * npi_txdma_channel_control():
8924496171girish *	This function is called to control a transmit DMA channel
8934496171girish *	for reset, start or stop.
8944496171girish *
8954496171girish * Parameters:
8964496171girish *	handle		- NPI handle (virtualization flag must be defined).
8974496171girish *	control		- NPI defined control type supported
8984496171girish *				- TXDMA_INIT_RESET
8994496171girish * 				- TXDMA_INIT_START
9004496171girish *				- TXDMA_RESET
9014496171girish *				- TXDMA_START
9024496171girish *				- TXDMA_STOP
9034496171girish *	channel		- logical TXDMA channel from 0 to 23.
9044496171girish *			  (If virtualization flag is not set, then
9054496171girish *			   logical channel is the same as the hardware
9064496171girish *
9074496171girish * Return:
9084496171girish *	NPI_SUCCESS		- If reset is complete successfully.
9094496171girish *
9104496171girish *	Error:
9114496171girish *	NPI_FAILURE		-
9124496171girish *		NPI_TXDMA_OPCODE_INVALID	-
9134496171girish *		NPI_TXDMA_CHANNEL_INVALID	-
9144496171girish *		NPI_TXDMA_RESET_FAILED	-
9154496171girish *		NPI_TXDMA_STOP_FAILED	-
9164496171girish *		NPI_TXDMA_RESUME_FAILED	-
9174496171girish */
9184496171girishnpi_status_t
9194496171girishnpi_txdma_channel_control(npi_handle_t handle, txdma_cs_cntl_t control,
9204496171girish		uint8_t channel)
9214496171girish{
9224496171girish	int		status = NPI_SUCCESS;
9234496171girish	tx_cs_t		cs;
9244496171girish
925a3c5bd6speer	ASSERT(TXDMA_CHANNEL_VALID(channel));
9264496171girish	if (!TXDMA_CHANNEL_VALID(channel)) {
9274496171girish		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
92852ccf84misaki		    " npi_txdma_channel_control"
92952ccf84misaki		    " Invalid Input: channel <0x%x>",
93052ccf84misaki		    channel));
9314496171girish		return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel));
9324496171girish	}
9334496171girish
9344496171girish	switch (control) {
9354496171girish	case TXDMA_INIT_RESET:
9364496171girish		cs.value = 0;
9374496171girish		TXDMA_REG_READ64(handle, TX_CS_REG, channel, &cs.value);
9384496171girish		cs.bits.ldw.rst = 1;
9394496171girish		TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs.value);
9404496171girish		return (npi_txdma_control_reset_wait(handle, channel));
9414496171girish
9424496171girish	case TXDMA_INIT_START:
9434496171girish		cs.value = 0;
9444496171girish		TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs.value);
9454496171girish		break;
9464496171girish
9474496171girish	case TXDMA_RESET:
9484496171girish		/*
9494496171girish		 * Sets reset bit only (Hardware will reset all
9504496171girish		 * the RW bits but leave the RO bits alone.
9514496171girish		 */
9524496171girish		cs.value = 0;
9534496171girish		cs.bits.ldw.rst = 1;
9544496171girish		TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs.value);
9554496171girish		return (npi_txdma_control_reset_wait(handle, channel));
9564496171girish
9574496171girish	case TXDMA_START:
9584496171girish		/* Enable the DMA channel */
9594496171girish		TXDMA_REG_READ64(handle, TX_CS_REG, channel, &cs.value);
9604496171girish		cs.bits.ldw.stop_n_go = 0;
9614496171girish		TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs.value);
9624496171girish		break;
9634496171girish
9644496171girish	case TXDMA_STOP:
9654496171girish		/* Disable the DMA channel */
9664496171girish		TXDMA_REG_READ64(handle, TX_CS_REG, channel, &cs.value);
9674496171girish		cs.bits.ldw.stop_n_go = 1;
9684496171girish		TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs.value);
9694496171girish		status = npi_txdma_control_stop_wait(handle, channel);
9704496171girish		if (status) {
9714496171girish			NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
97252ccf84misaki			    "Cannot stop channel %d (TXC hung!)",
97352ccf84misaki			    channel));
9744496171girish		}
9754496171girish		break;
9764496171girish
9774496171girish	case TXDMA_RESUME:
9784496171girish		/* Resume the packet transmission after stopping */
9794496171girish		TXDMA_REG_READ64(handle, TX_CS_REG, channel, &cs.value);
9804496171girish		cs.value |= ~TX_CS_STOP_N_GO_MASK;
9814496171girish		TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs.value);
9824496171girish		return (npi_txdma_control_resume_wait(handle, channel));
9834496171girish
9844496171girish	case TXDMA_CLEAR_MMK:
9854496171girish		/* Write 1 to MK bit to clear the MMK bit */
9864496171girish		TXDMA_REG_READ64(handle, TX_CS_REG, channel, &cs.value);
9874496171girish		cs.bits.ldw.mk = 1;
9884496171girish		TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs.value);
9894496171girish		break;
9904496171girish
9914496171girish	case TXDMA_MBOX_ENABLE:
9924496171girish		/*
9934496171girish		 * Write 1 to MB bit to enable mailbox update
9944496171girish		 * (cleared to 0 by hardware after update).
9954496171girish		 */
9964496171girish		TXDMA_REG_READ64(handle, TX_CS_REG, channel, &cs.value);
9974496171girish		cs.bits.ldw.mb = 1;
9984496171girish		TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs.value);
9994496171girish		break;
10004496171girish
10014496171girish	default:
10024496171girish		status =  (NPI_FAILURE | NPI_TXDMA_OPCODE_INVALID(channel));
10034496171girish		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
100452ccf84misaki		    " npi_txdma_channel_control"
100552ccf84misaki		    " Invalid Input: control <0x%x>",
100652ccf84misaki		    control));
10074496171girish	}
10084496171girish
10094496171girish	return (status);
10104496171girish}
10114496171girish
10124496171girish/*
10134496171girish * npi_txdma_control_status():
10144496171girish *	This function is called to operate on the control
10154496171girish *	and status register.
10164496171girish *
10174496171girish * Parameters:
10184496171girish *	handle		- NPI handle
10194496171girish *	op_mode		- OP_GET: get hardware control and status
10204496171girish *			  OP_SET: set hardware control and status
10214496171girish *			  OP_UPDATE: update hardware control and status.
10224496171girish *			  OP_CLEAR: clear control and status register to 0s.
10234496171girish *	channel		- hardware TXDMA channel from 0 to 23.
10244496171girish *	cs_p		- pointer to hardware defined control and status
10254496171girish *			  structure.
10264496171girish * Return:
10274496171girish *	NPI_SUCCESS		- If set is complete successfully.
10284496171girish *
10294496171girish *	Error:
10304496171girish *	NPI_FAILURE		-
10314496171girish *		NPI_TXDMA_OPCODE_INVALID	-
10324496171girish *		NPI_TXDMA_CHANNEL_INVALID	-
10334496171girish *		NPI_TXDMA_FUNC_INVALID	-
10344496171girish */
10354496171girishnpi_status_t
10364496171girishnpi_txdma_control_status(npi_handle_t handle, io_op_t op_mode,
10374496171girish		uint8_t channel, p_tx_cs_t cs_p)
10384496171girish{
10394496171girish	int		status = NPI_SUCCESS;
10404496171girish	tx_cs_t		txcs;
10414496171girish
1042a3c5bd6speer	ASSERT(TXDMA_CHANNEL_VALID(channel));
10434496171girish	if (!TXDMA_CHANNEL_VALID(channel)) {
10444496171girish		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
104552ccf84misaki		    " npi_txdma_control_status"
104652ccf84misaki		    " Invalid Input: channel <0x%x>",
104752ccf84misaki		    channel));
10484496171girish		return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel));
10494496171girish	}
10504496171girish
10514496171girish	switch (op_mode) {
10524496171girish	case OP_GET:
10534496171girish		TXDMA_REG_READ64(handle, TX_CS_REG, channel, &cs_p->value);
10544496171girish		break;
10554496171girish
10564496171girish	case OP_SET:
10574496171girish		TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs_p->value);
10584496171girish		break;
10594496171girish
10604496171girish	case OP_UPDATE:
10614496171girish		TXDMA_REG_READ64(handle, TX_CS_REG, channel, &txcs.value);
10624496171girish		TXDMA_REG_WRITE64(handle, TX_CS_REG, channel,
106352ccf84misaki		    cs_p->value | txcs.value);
10644496171girish		break;
10654496171girish
10664496171girish	default:
10674496171girish		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
106852ccf84misaki		    " npi_txdma_control_status"
106952ccf84misaki		    " Invalid Input: control <0x%x>",
107052ccf84misaki		    op_mode));
10714496171girish		return (NPI_FAILURE | NPI_TXDMA_OPCODE_INVALID(channel));
10724496171girish	}
10734496171girish
10744496171girish	return (status);
10754496171girish
10764496171girish}
10774496171girish
10784496171girish/*
10794496171girish * npi_txdma_event_mask():
10804496171girish *	This function is called to operate on the event mask
10814496171girish *	register which is used for generating interrupts..
10824496171girish *	and status register.
10834496171girish *
10844496171girish * Parameters:
10854496171girish *	handle		- NPI handle
10864496171girish *	op_mode		- OP_GET: get hardware event mask
10874496171girish *			  OP_SET: set hardware interrupt event masks
10884496171girish *			  OP_CLEAR: clear control and status register to 0s.
10894496171girish *	channel		- hardware TXDMA channel from 0 to 23.
10904496171girish *	mask_p		- pointer to hardware defined event mask
10914496171girish *			  structure.
10924496171girish * Return:
10934496171girish *	NPI_SUCCESS		- If set is complete successfully.
10944496171girish *
10954496171girish *	Error:
10964496171girish *	NPI_FAILURE		-
10974496171girish *		NPI_TXDMA_OPCODE_INVALID	-
10984496171girish *		NPI_TXDMA_CHANNEL_INVALID	-
10994496171girish */
11004496171girishnpi_status_t
11014496171girishnpi_txdma_event_mask(npi_handle_t handle, io_op_t op_mode,
11024496171girish		uint8_t channel, p_tx_dma_ent_msk_t mask_p)
11034496171girish{
11044496171girish	int			status = NPI_SUCCESS;
11054496171girish	tx_dma_ent_msk_t	mask;
11064496171girish
1107a3c5bd6speer	ASSERT(TXDMA_CHANNEL_VALID(channel));
11084496171girish	if (!TXDMA_CHANNEL_VALID(channel)) {
11094496171girish		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
111052ccf84misaki		    " npi_txdma_event_mask"
111152ccf84misaki		    " Invalid Input: channel <0x%x>",
111252ccf84misaki		    channel));
11134496171girish		return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel));
11144496171girish	}
11154496171girish
11164496171girish	switch (op_mode) {
11174496171girish	case OP_GET:
11184496171girish		TXDMA_REG_READ64(handle, TX_ENT_MSK_REG, channel,
111952ccf84misaki		    &mask_p->value);
11204496171girish		break;
11214496171girish
11224496171girish	case OP_SET:
11234496171girish		TXDMA_REG_WRITE64(handle, TX_ENT_MSK_REG, channel,
112452ccf84misaki		    mask_p->value);
11254496171girish		break;
11264496171girish
11274496171girish	case OP_UPDATE:
11284496171girish		TXDMA_REG_READ64(handle, TX_ENT_MSK_REG, channel, &mask.value);
11294496171girish		TXDMA_REG_WRITE64(handle, TX_ENT_MSK_REG, channel,
113052ccf84misaki		    mask_p->value | mask.value);
11314496171girish		break;
11324496171girish
11334496171girish	default:
11344496171girish		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
113552ccf84misaki		    " npi_txdma_event_mask"
113652ccf84misaki		    " Invalid Input: eventmask <0x%x>",
113752ccf84misaki		    op_mode));
11384496171girish		return (NPI_FAILURE | NPI_TXDMA_OPCODE_INVALID(channel));
11394496171girish	}
11404496171girish
11414496171girish	return (status);
11424496171girish}
11434496171girish
11444496171girish/*
11454496171girish * npi_txdma_event_mask_config():
11464496171girish *	This function is called to operate on the event mask
11474496171girish *	register which is used for generating interrupts..
11484496171girish *	and status register.
11494496171girish *
11504496171girish * Parameters:
11514496171girish *	handle		- NPI handle
11524496171girish *	op_mode		- OP_GET: get hardware event mask
11534496171girish *			  OP_SET: set hardware interrupt event masks
11544496171girish *			  OP_CLEAR: clear control and status register to 0s.
11554496171girish *	channel		- hardware TXDMA channel from 0 to 23.
11564496171girish *	cfgp		- pointer to NPI defined event mask
11574496171girish *			  enum data type.
11584496171girish * Return:
11594496171girish *	NPI_SUCCESS		- If set is complete successfully.
11604496171girish *
11614496171girish *	Error:
11624496171girish *	NPI_FAILURE		-
11634496171girish *		NPI_TXDMA_OPCODE_INVALID	-
11644496171girish *		NPI_TXDMA_CHANNEL_INVALID	-
11654496171girish */
11664496171girishnpi_status_t
11674496171girishnpi_txdma_event_mask_config(npi_handle_t handle, io_op_t op_mode,
11684496171girish		uint8_t channel, txdma_ent_msk_cfg_t *mask_cfgp)
11694496171girish{
11704496171girish	int		status = NPI_SUCCESS;
1171678453aspeer	uint64_t	configuration = *mask_cfgp;
11724496171girish	uint64_t	value;
11734496171girish
1174a3c5bd6speer	ASSERT(TXDMA_CHANNEL_VALID(channel));
11754496171girish	if (!TXDMA_CHANNEL_VALID(channel)) {
11764496171girish		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
117752ccf84misaki		    " npi_txdma_event_mask_config"
117852ccf84misaki		    " Invalid Input: channel <0x%x>",
117952ccf84misaki		    channel));
11804496171girish
11814496171girish		return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel));
11824496171girish	}
11834496171girish
11844496171girish	switch (op_mode) {
11854496171girish	case OP_GET:
1186678453aspeer		TXDMA_REG_READ64(handle, TX_ENT_MSK_REG, channel,
1187678453aspeer		    (uint64_t *)mask_cfgp);
11884496171girish		break;
11894496171girish
11904496171girish	case OP_SET:
11914496171girish		TXDMA_REG_WRITE64(handle, TX_ENT_MSK_REG, channel,
1192678453aspeer		    configuration);
11934496171girish		break;
11944496171girish
11954496171girish	case OP_UPDATE:
11964496171girish		TXDMA_REG_READ64(handle, TX_ENT_MSK_REG, channel, &value);
11974496171girish		TXDMA_REG_WRITE64(handle, TX_ENT_MSK_REG, channel,
1198678453aspeer		    configuration | value);
11994496171girish		break;
12004496171girish
12014496171girish	case OP_CLEAR:
12024496171girish		TXDMA_REG_WRITE64(handle, TX_ENT_MSK_REG, channel,
120352ccf84misaki		    CFG_TXDMA_MASK_ALL);
12044496171girish		break;
12054496171girish	default:
12064496171girish		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
120752ccf84misaki		    " npi_txdma_event_mask_config"
120852ccf84misaki		    " Invalid Input: eventmask <0x%x>",
120952ccf84misaki		    op_mode));
12104496171girish		return (NPI_FAILURE | NPI_TXDMA_OPCODE_INVALID(channel));
12114496171girish	}
12124496171girish
12134496171girish	return (status);
12144496171girish}
12154496171girish
12164496171girish/*
12174496171girish * npi_txdma_event_mask_mk_out():
12184496171girish *	This function is called to mask out the packet transmit marked event.
12194496171girish *
12204496171girish * Parameters:
12214496171girish *	handle		- NPI handle
12224496171girish *	channel		- hardware TXDMA channel from 0 to 23.
12234496171girish *			  enum data type.
12244496171girish * Return:
12254496171girish *	NPI_SUCCESS		- If set is complete successfully.
12264496171girish *
12274496171girish *	Error:
12284496171girish *	NPI_FAILURE		-
12294496171girish *		NPI_TXDMA_CHANNEL_INVALID	-
12304496171girish */
12314496171girishnpi_status_t
12324496171girishnpi_txdma_event_mask_mk_out(npi_handle_t handle, uint8_t channel)
12334496171girish{
1234678453aspeer	uint64_t event_mask;
1235678453aspeer	int	status = NPI_SUCCESS;
12364496171girish
1237a3c5bd6speer	ASSERT(TXDMA_CHANNEL_VALID(channel));
12384496171girish	if (!TXDMA_CHANNEL_VALID(channel)) {
12394496171girish		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
124052ccf84misaki		    " npi_txdma_event_mask_mk_out"
124152ccf84misaki		    " Invalid Input: channel <0x%x>",
124252ccf84misaki		    channel));
12434496171girish		return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel));
12444496171girish	}
12454496171girish
12464496171girish	TXDMA_REG_READ64(handle, TX_ENT_MSK_REG, channel, &event_mask);
12474496171girish	TXDMA_REG_WRITE64(handle, TX_ENT_MSK_REG, channel,
124852ccf84misaki	    event_mask & (~TX_ENT_MSK_MK_MASK));
12494496171girish
12504496171girish	return (status);
12514496171girish}
12524496171girish
12534496171girish/*
12544496171girish * npi_txdma_event_mask_mk_in():
12554496171girish *	This function is called to set the mask for the the packet marked event.
12564496171girish *
12574496171girish * Parameters:
12584496171girish *	handle		- NPI handle
12594496171girish *	channel		- hardware TXDMA channel from 0 to 23.
12604496171girish *			  enum data type.
12614496171girish * Return:
12624496171girish *	NPI_SUCCESS		- If set is complete successfully.
12634496171girish *
12644496171girish *	Error:
12654496171girish *	NPI_FAILURE		-
12664496171girish *		NPI_TXDMA_CHANNEL_INVALID	-
12674496171girish */
12684496171girishnpi_status_t
12694496171girishnpi_txdma_event_mask_mk_in(npi_handle_t handle, uint8_t channel)
12704496171girish{
1271678453aspeer	uint64_t event_mask;
1272678453aspeer	int	status = NPI_SUCCESS;
12734496171girish
1274a3c5bd6speer	ASSERT(TXDMA_CHANNEL_VALID(channel));
12754496171girish	if (!TXDMA_CHANNEL_VALID(channel)) {
12764496171girish		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
127752ccf84misaki		    " npi_txdma_event_mask_mk_in"
127852ccf84misaki		    " Invalid Input: channel <0x%x>",
127952ccf84misaki		    channel));
12804496171girish		return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel));
12814496171girish	}
12824496171girish
12834496171girish	TXDMA_REG_READ64(handle, TX_ENT_MSK_REG, channel, &event_mask);
12844496171girish	TXDMA_REG_WRITE64(handle, TX_ENT_MSK_REG, channel,
128552ccf84misaki	    event_mask | TX_ENT_MSK_MK_MASK);
12864496171girish
12874496171girish	return (status);
12884496171girish}
12894496171girish
12904496171girish/*
12914496171girish * npi_txdma_ring_addr_set():
12924496171girish *	This function is called to configure the transmit descriptor
12934496171girish *	ring address and its size.
12944496171girish *
12954496171girish * Parameters:
12964496171girish *	handle		- NPI handle (virtualization flag must be defined
12974496171girish *			  if its register pointer is from the virtual region).
12984496171girish *	channel		- logical TXDMA channel from 0 to 23.
12994496171girish *			  (If virtualization flag is not set, then
13004496171girish *			   logical channel is the same as the hardware
13014496171girish *			   channel number).
13024496171girish *	start_addr	- starting address of the descriptor
13034496171girish *	len		- maximum length of the descriptor
13044496171girish *			  (in number of 64 bytes block).
13054496171girish * Return:
13064496171girish *	NPI_SUCCESS		- If set is complete successfully.
13074496171girish *
13084496171girish *	Error:
13094496171girish *	NPI_FAILURE		-
13104496171girish *		NPI_TXDMA_OPCODE_INVALID	-
13114496171girish *		NPI_TXDMA_CHANNEL_INVALID	-
13124496171girish */
13134496171girishnpi_status_t
13144496171girishnpi_txdma_ring_addr_set(npi_handle_t handle, uint8_t channel,
13154496171girish		uint64_t start_addr, uint32_t len)
13164496171girish{
13174496171girish	int		status = NPI_SUCCESS;
13184496171girish	tx_rng_cfig_t	cfg;
13194496171girish
1320a3c5bd6speer	ASSERT(TXDMA_CHANNEL_VALID(channel));
13214496171girish	if (!TXDMA_CHANNEL_VALID(channel)) {
13224496171girish		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
132352ccf84misaki		    " npi_txdma_ring_addr_set"
132452ccf84misaki		    " Invalid Input: channel <0x%x>",
132552ccf84misaki		    channel));
13264496171girish		return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel));
13274496171girish	}
13284496171girish
13294496171girish	cfg.value = ((start_addr & TX_RNG_CFIG_ADDR_MASK) |
133052ccf84misaki	    (((uint64_t)len) << TX_RNG_CFIG_LEN_SHIFT));
13314496171girish	TXDMA_REG_WRITE64(handle, TX_RNG_CFIG_REG, channel, cfg.value);
13324496171girish
13334496171girish	return (status);
13344496171girish}
13354496171girish
13364496171girish/*
13374496171girish * npi_txdma_ring_config():
13384496171girish *	This function is called to config a descriptor ring
13394496171girish *	by using the hardware defined data.
13404496171girish *
13414496171girish * Parameters:
13424496171girish *	handle		- NPI handle (virtualization flag must be defined
13434496171girish *			  if its register pointer is from the virtual region).
13444496171girish *	channel		- logical TXDMA channel from 0 to 23.
13454496171girish *			  (If virtualization flag is not set, then
13464496171girish *			   logical channel is the same as the hardware
13474496171girish *			   channel number).
13484496171girish *	op_mode		- OP_GET: get transmit ring configuration
13494496171girish *			  OP_SET: set transmit ring configuration
13504496171girish *	reg_data	- pointer to hardware defined transmit ring
13514496171girish *			  configuration data structure.
13524496171girish * Return:
13534496171girish *	NPI_SUCCESS		- If set/get is complete successfully.
13544496171girish *
13554496171girish *	Error:
13564496171girish *	NPI_FAILURE		-
13574496171girish *		NPI_TXDMA_CHANNEL_INVALID	-
13584496171girish */
13594496171girishnpi_status_t
13604496171girishnpi_txdma_ring_config(npi_handle_t handle, io_op_t op_mode,
13614496171girish		uint8_t channel, uint64_t *reg_data)
13624496171girish{
13634496171girish	int		status = NPI_SUCCESS;
13644496171girish
1365a3c5bd6speer	ASSERT(TXDMA_CHANNEL_VALID(channel));
13664496171girish	if (!TXDMA_CHANNEL_VALID(channel)) {
13674496171girish		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
136852ccf84misaki		    " npi_txdma_ring_config"
136952ccf84misaki		    " Invalid Input: channel <0x%x>",
137052ccf84misaki		    channel));
13714496171girish		return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel));
13724496171girish	}
13734496171girish
13744496171girish	switch (op_mode) {
13754496171girish	case OP_GET:
13764496171girish		TXDMA_REG_READ64(handle, TX_RNG_CFIG_REG, channel, reg_data);
13774496171girish		break;
13784496171girish
13794496171girish	case OP_SET:
13804496171girish		TXDMA_REG_WRITE64(handle, TX_RNG_CFIG_REG, channel,
138152ccf84misaki		    *reg_data);
13824496171girish		break;
13834496171girish
13844496171girish	default:
13854496171girish		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
138652ccf84misaki		    " npi_txdma_ring_config"
138752ccf84misaki		    " Invalid Input: ring_config <0x%x>",
138852ccf84misaki		    op_mode));
13894496171girish		return (NPI_FAILURE | NPI_TXDMA_OPCODE_INVALID(channel));
13904496171girish	}
13914496171girish
13924496171girish	return (status);
13934496171girish}
13944496171girish
13954496171girish/*
13964496171girish * npi_txdma_mbox_config():
13974496171girish *	This function is called to config the mailbox address
13984496171girish *
13994496171girish * Parameters:
14004496171girish *	handle		- NPI handle (virtualization flag must be defined
14014496171girish *			  if its register pointer is from the virtual region).
14024496171girish *	channel		- logical TXDMA channel from 0 to 23.
14034496171girish *			  (If virtualization flag is not set, then
14044496171girish *			   logical channel is the same as the hardware
14054496171girish *			   channel number).
14064496171girish *	op_mode		- OP_GET: get the mailbox address
14074496171girish *			  OP_SET: set the mailbox address
14084496171girish *	reg_data	- pointer to the mailbox address.
14094496171girish * Return:
14104496171girish *	NPI_SUCCESS		- If set is complete successfully.
14114496171girish *
14124496171girish *	Error:
14134496171girish *	NPI_FAILURE		-
14144496171girish *		NPI_TXDMA_OPCODE_INVALID	-
14154496171girish *		NPI_TXDMA_CHANNEL_INVALID	-
14164496171girish */
14174496171girishnpi_status_t
14184496171girishnpi_txdma_mbox_config(npi_handle_t handle, io_op_t op_mode,
14194496171girish		uint8_t channel, uint64_t *mbox_addr)
14204496171girish{
14214496171girish	int		status = NPI_SUCCESS;
14224496171girish	txdma_mbh_t	mh;
14234496171girish	txdma_mbl_t	ml;
14244496171girish
1425a3c5bd6speer	ASSERT(TXDMA_CHANNEL_VALID(channel));
14264496171girish	if (!TXDMA_CHANNEL_VALID(channel)) {
14274496171girish		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
142852ccf84misaki		    " npi_txdma_mbox_config"
142952ccf84misaki		    " Invalid Input: channel <0x%x>",
143052ccf84misaki		    channel));
14314496171girish		return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel));
14324496171girish	}
14334496171girish
14344496171girish	mh.value = ml.value = 0;
14354496171girish
14364496171girish	switch (op_mode) {
14374496171girish	case OP_GET:
14384496171girish		TXDMA_REG_READ64(handle, TXDMA_MBH_REG, channel, &mh.value);
14394496171girish		TXDMA_REG_READ64(handle, TXDMA_MBL_REG, channel, &ml.value);
14404496171girish		*mbox_addr = ml.value;
14414496171girish		*mbox_addr |= (mh.value << TXDMA_MBH_ADDR_SHIFT);
14424496171girish
14434496171girish		break;
14444496171girish
14454496171girish	case OP_SET:
14464496171girish		ml.bits.ldw.mbaddr = ((*mbox_addr & TXDMA_MBL_MASK) >>
144752ccf84misaki		    TXDMA_MBL_SHIFT);
14484496171girish		TXDMA_REG_WRITE64(handle, TXDMA_MBL_REG, channel, ml.value);
14494496171girish		mh.bits.ldw.mbaddr = ((*mbox_addr >> TXDMA_MBH_ADDR_SHIFT) &
145052ccf84misaki		    TXDMA_MBH_MASK);
14514496171girish		TXDMA_REG_WRITE64(handle, TXDMA_MBH_REG, channel, mh.value);
14524496171girish
14534496171girish		break;
14544496171girish
14554496171girish	default:
14564496171girish		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
145752ccf84misaki		    " npi_txdma_mbox_config"
145852ccf84misaki		    " Invalid Input: mbox <0x%x>",
145952ccf84misaki		    op_mode));
14604496171girish		return (NPI_FAILURE | NPI_TXDMA_OPCODE_INVALID(channel));
14614496171girish	}
14624496171girish
14634496171girish	return (status);
14644496171girish
14654496171girish}
14664496171girish
14674496171girish/*
14684496171girish * npi_txdma_desc_gather_set():
14694496171girish *	This function is called to set up a transmit descriptor entry.
14704496171girish *
14714496171girish * Parameters:
14724496171girish *	handle		- NPI handle (register pointer is the
14734496171girish *			  descriptor address in memory).
14744496171girish *	desc_p		- pointer to a descriptor
14754496171girish *	gather_index	- which entry (starts from index 0 to 15)
14764496171girish *	mark		- mark bit (only valid if it is the first gather).
14774496171girish *	ngathers	- number of gather pointers to set to the first gather.
14784496171girish *	dma_ioaddr	- starting dma address of an IO buffer to write.
14794496171girish *			  (SAD)
14804496171girish *	transfer_len	- transfer len.
14814496171girish * Return:
14824496171girish *	NPI_SUCCESS		- If set is complete successfully.
14834496171girish *
14844496171girish *	Error:
14854496171girish *	NPI_FAILURE		-
14864496171girish *		NPI_TXDMA_OPCODE_INVALID	-
14874496171girish *		NPI_TXDMA_CHANNEL_INVALID	-
14884496171girish *		NPI_TXDMA_XFER_LEN_INVALID	-
14894496171girish */
14904496171girishnpi_status_t
14914496171girishnpi_txdma_desc_gather_set(npi_handle_t handle,
14924496171girish		p_tx_desc_t desc_p, uint8_t gather_index,
14934496171girish		boolean_t mark, uint8_t ngathers,
14944496171girish		uint64_t dma_ioaddr, uint32_t transfer_len)
14954496171girish{
14964496171girish	int		status;
14974496171girish
14984496171girish	status = NPI_TXDMA_GATHER_INDEX(gather_index);
14994496171girish	if (status) {
15004496171girish		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
150152ccf84misaki		    " npi_txdma_desc_gather_set"
150252ccf84misaki		    " Invalid Input: gather_index <0x%x>",
150352ccf84misaki		    gather_index));
15044496171girish		return (status);
15054496171girish	}
15064496171girish
15074496171girish	if (transfer_len > TX_MAX_TRANSFER_LENGTH) {
15084496171girish		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
150952ccf84misaki		    " npi_txdma_desc_gather_set"
151052ccf84misaki		    " Invalid Input: tr_len <0x%x>",
151152ccf84misaki		    transfer_len));
15124496171girish		return (NPI_FAILURE | NPI_TXDMA_XFER_LEN_INVALID);
15134496171girish	}
15144496171girish
15154496171girish	if (gather_index == 0) {
15164496171girish		desc_p->bits.hdw.sop = 1;
15174496171girish		desc_p->bits.hdw.mark = mark;
15184496171girish		desc_p->bits.hdw.num_ptr = ngathers;
15194496171girish		NPI_DEBUG_MSG((handle.function, NPI_TDC_CTL,
152052ccf84misaki		    "npi_txdma_gather_set: SOP len %d (%d)",
152152ccf84misaki		    desc_p->bits.hdw.tr_len, transfer_len));
15224496171girish	}
15234496171girish
15244496171girish	desc_p->bits.hdw.tr_len = transfer_len;
15254496171girish	desc_p->bits.hdw.sad = dma_ioaddr >> 32;
15264496171girish	desc_p->bits.ldw.sad = dma_ioaddr & 0xffffffff;
15274496171girish
15284496171girish	NPI_DEBUG_MSG((handle.function, NPI_TDC_CTL,
152952ccf84misaki	    "npi_txdma_gather_set: xfer len %d to set (%d)",
153052ccf84misaki	    desc_p->bits.hdw.tr_len, transfer_len));
15314496171girish
15324496171girish	NXGE_MEM_PIO_WRITE64(handle, desc_p->value);
15334496171girish
15344496171girish	return (status);
15354496171girish}
15364496171girish
15374496171girish/*
15384496171girish * npi_txdma_desc_sop_set():
15394496171girish *	This function is called to set up the first gather entry.
15404496171girish *
15414496171girish * Parameters:
15424496171girish *	handle		- NPI handle (register pointer is the
15434496171girish *			  descriptor address in memory).
15444496171girish *	desc_p		- pointer to a descriptor
15454496171girish *	mark		- mark bit (only valid if it is the first gather).
15464496171girish *	ngathers	- number of gather pointers to set to the first gather.
15474496171girish * Return:
15484496171girish *	NPI_SUCCESS		- If set is complete successfully.
15494496171girish *
15504496171girish *	Error:
15514496171girish */
15524496171girishnpi_status_t
15534496171girishnpi_txdma_desc_gather_sop_set(npi_handle_t handle,
15544496171girish		p_tx_desc_t desc_p,
15554496171girish		boolean_t mark_mode,
15564496171girish		uint8_t ngathers)
15574496171girish{
15584496171girish	int		status = NPI_SUCCESS;
15594496171girish
15604496171girish	desc_p->bits.hdw.sop = 1;
15614496171girish	desc_p->bits.hdw.mark = mark_mode;
15624496171girish	desc_p->bits.hdw.num_ptr = ngathers;
15634496171girish
15644496171girish	NXGE_MEM_PIO_WRITE64(handle, desc_p->value);
15654496171girish
15664496171girish	return (status);
15674496171girish}
15684496171girishnpi_status_t
15694496171girishnpi_txdma_desc_gather_sop_set_1(npi_handle_t handle,
15704496171girish		p_tx_desc_t desc_p,
15714496171girish		boolean_t mark_mode,
15724496171girish		uint8_t ngathers,
15734496171girish		uint32_t extra)
15744496171girish{
15754496171girish	int		status = NPI_SUCCESS;
15764496171girish
15774496171girish	desc_p->bits.hdw.sop = 1;
15784496171girish	desc_p->bits.hdw.mark = mark_mode;
15794496171girish	desc_p->bits.hdw.num_ptr = ngathers;
15804496171girish	desc_p->bits.hdw.tr_len += extra;
15814496171girish
15824496171girish	NXGE_MEM_PIO_WRITE64(handle, desc_p->value);
15834496171girish
15844496171girish	return (status);
15854496171girish}
15864496171girish
15874496171girishnpi_status_t
15884496171girishnpi_txdma_desc_set_xfer_len(npi_handle_t handle,
15894496171girish		p_tx_desc_t desc_p,
15904496171girish		uint32_t transfer_len)
15914496171girish{
15924496171girish	int		status = NPI_SUCCESS;
15934496171girish
15944496171girish	desc_p->bits.hdw.tr_len = transfer_len;
15954496171girish
15964496171girish	NPI_DEBUG_MSG((handle.function, NPI_TDC_CTL,
159752ccf84misaki	    "npi_set_xfer_len: len %d (%d)",
159852ccf84misaki	    desc_p->bits.hdw.tr_len, transfer_len));
15994496171girish
16004496171girish	NXGE_MEM_PIO_WRITE64(handle, desc_p->value);
16014496171girish
16024496171girish	return (status);
16034496171girish}
16044496171girish
16054496171girishnpi_status_t
16064496171girishnpi_txdma_desc_set_zero(npi_handle_t handle, uint16_t entries)
16074496171girish{
16084496171girish	uint32_t	offset;
16094496171girish	int		i;
16104496171girish
16114496171girish	/*
16124496171girish	 * Assume no wrapped around.
16134496171girish	 */
16144496171girish	offset = 0;
16154496171girish	for (i = 0; i < entries; i++) {
16164496171girish		NXGE_REG_WR64(handle, offset, 0);
16174496171girish		offset += (i * TXDMA_DESC_SIZE);
16184496171girish	}
16194496171girish
16204496171girish	return (NPI_SUCCESS);
16214496171girish}
16224496171girish
16234496171girishnpi_status_t
16244496171girishnpi_txdma_desc_mem_get(npi_handle_t handle, uint16_t index,
16254496171girish		p_tx_desc_t desc_p)
16264496171girish{
16274496171girish	int		status = NPI_SUCCESS;
16284496171girish
16294496171girish	npi_txdma_dump_desc_one(handle, desc_p, index);
16304496171girish
16314496171girish	return (status);
16324496171girish
16334496171girish}
16344496171girish
16354496171girish/*
16364496171girish * npi_txdma_desc_kick_reg_set():
16374496171girish *	This function is called to kick the transmit  to start transmission.
16384496171girish *
16394496171girish * Parameters:
16404496171girish *	handle		- NPI handle (virtualization flag must be defined).
16414496171girish *	channel		- logical TXDMA channel from 0 to 23.
16424496171girish *			  (If virtualization flag is not set, then
16434496171girish *			   logical channel is the same as the hardware
16444496171girish *			   channel number).
16454496171girish *	tail_index	- index into the transmit descriptor
16464496171girish *	wrap		- toggle bit to indicate if the tail index is
16474496171girish *			  wrapped around.
16484496171girish *
16494496171girish * Return:
16504496171girish *	NPI_SUCCESS		- If set is complete successfully.
16514496171girish *
16524496171girish *	Error:
16534496171girish *	NPI_FAILURE		-
16544496171girish *		NPI_TXDMA_CHANNEL_INVALID	-
16554496171girish */
16564496171girishnpi_status_t
16574496171girishnpi_txdma_desc_kick_reg_set(npi_handle_t handle, uint8_t channel,
16584496171girish		uint16_t tail_index, boolean_t wrap)
16594496171girish{
16604496171girish	int			status = NPI_SUCCESS;
16614496171girish	tx_ring_kick_t		kick;
16624496171girish
1663a3c5bd6speer	ASSERT(TXDMA_CHANNEL_VALID(channel));
16644496171girish	if (!TXDMA_CHANNEL_VALID(channel)) {
16654496171girish		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
166652ccf84misaki		    " npi_txdma_desc_kick_reg_set"
166752ccf84misaki		    " Invalid Input: channel <0x%x>",
166852ccf84misaki		    channel));
16694496171girish		return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel));
16704496171girish	}
16714496171girish
16724496171girish	NPI_DEBUG_MSG((handle.function, NPI_TDC_CTL,
167352ccf84misaki	    " npi_txdma_desc_kick_reg_set: "
167452ccf84misaki	    " KICKING channel %d",
167552ccf84misaki	    channel));
16764496171girish
16774496171girish	/* Toggle the wrap around bit */
16784496171girish	kick.value = 0;
16794496171girish	kick.bits.ldw.wrap = wrap;
16804496171girish	kick.bits.ldw.tail = tail_index;
16814496171girish
16824496171girish	/* Kick start the Transmit kick register */
16834496171girish	TXDMA_REG_WRITE64(handle, TX_RING_KICK_REG, channel, kick.value);
16844496171girish
16854496171girish	return (status);
16864496171girish}
16874496171girish
16884496171girish/*
16894496171girish * npi_txdma_desc_kick_reg_get():
16904496171girish *	This function is called to kick the transmit  to start transmission.
16914496171girish *
16924496171girish * Parameters:
16934496171girish *	handle		- NPI handle (virtualization flag must be defined).
16944496171girish *	channel		- logical TXDMA channel from 0 to 23.
16954496171girish *			  (If virtualization flag is not set, then
16964496171girish *			   logical channel is the same as the hardware
16974496171girish *			   channel number).
16984496171girish *	tail_index	- index into the transmit descriptor
16994496171girish *	wrap		- toggle bit to indicate if the tail index is
17004496171girish *			  wrapped around.
17014496171girish *
17024496171girish * Return:
17034496171girish *	NPI_SUCCESS		- If get is complete successfully.
17044496171girish *
17054496171girish *	Error:
17064496171girish *	NPI_FAILURE		-
17074496171girish *		NPI_TXDMA_CHANNEL_INVALID	-
17084496171girish */
17094496171girishnpi_status_t
17104496171girishnpi_txdma_desc_kick_reg_get(npi_handle_t handle, uint8_t channel,
17114496171girish		p_tx_ring_kick_t kick_p)
17124496171girish{
17134496171girish	int		status = NPI_SUCCESS;
17144496171girish
1715a3c5bd6speer	ASSERT(TXDMA_CHANNEL_VALID(channel));
17164496171girish	if (!TXDMA_CHANNEL_VALID(channel)) {
17174496171girish		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
171852ccf84misaki		    " npi_txdma_desc_kick_reg_get"
171952ccf84misaki		    " Invalid Input: channel <0x%x>",
172052ccf84misaki		    channel));
17214496171girish		return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel));
17224496171girish	}
17234496171girish
17244496171girish	TXDMA_REG_READ64(handle, TX_RING_KICK_REG, channel, &kick_p->value);
17254496171girish
17264496171girish	return (status);
17274496171girish}
17284496171girish
17294496171girish/*
17304496171girish * npi_txdma_ring_head_get():
17314496171girish *	This function is called to get the transmit ring head index.
17324496171girish *
17334496171girish * Parameters:
17344496171girish *	handle		- NPI handle (virtualization flag must be defined).
17354496171girish *	channel		- logical TXDMA channel from 0 to 23.
17364496171girish *			  (If virtualization flag is not set, then
17374496171girish *			   logical channel is the same as the hardware
17384496171girish *			   channel number).
17394496171girish *	hdl_p		- pointer to the hardware defined transmit
17404496171girish *			  ring header data (head index and wrap bit).
17414496171girish *
17424496171girish * Return:
17434496171girish *	NPI_SUCCESS		- If get is complete successfully.
17444496171girish *
17454496171girish *	Error:
17464496171girish *	NPI_FAILURE		-
17474496171girish *		NPI_TXDMA_CHANNEL_INVALID	-
17484496171girish */
17494496171girishnpi_status_t
17504496171girishnpi_txdma_ring_head_get(npi_handle_t handle, uint8_t channel,
17514496171girish		p_tx_ring_hdl_t hdl_p)
17524496171girish{
17534496171girish	int		status = NPI_SUCCESS;
17544496171girish
1755a3c5bd6speer	ASSERT(TXDMA_CHANNEL_VALID(channel));
17564496171girish	if (!TXDMA_CHANNEL_VALID(channel)) {
17574496171girish		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
175852ccf84misaki		    " npi_txdma_ring_head_get"
175952ccf84misaki		    " Invalid Input: channel <0x%x>",
176052ccf84misaki		    channel));
17614496171girish		return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel));
17624496171girish	}
17634496171girish
17644496171girish	TXDMA_REG_READ64(handle, TX_RING_HDL_REG, channel, &hdl_p->value);
17654496171girish
17664496171girish	return (status);
17674496171girish}
17684496171girish
17694496171girish/*ARGSUSED*/
17704496171girishnpi_status_t
17714496171girishnpi_txdma_channel_mbox_get(npi_handle_t handle, uint8_t channel,
17724496171girish		p_txdma_mailbox_t mbox_p)
17734496171girish{
17744496171girish	int		status = NPI_SUCCESS;
17754496171girish
17764496171girish	return (status);
17774496171girish
17784496171girish}
17794496171girish
17804496171girishnpi_status_t
17814496171girishnpi_txdma_channel_pre_state_get(npi_handle_t handle, uint8_t channel,
17824496171girish		p_tx_dma_pre_st_t prep)
17834496171girish{
17844496171girish	int		status = NPI_SUCCESS;
17854496171girish
1786a3c5bd6speer	ASSERT(TXDMA_CHANNEL_VALID(channel));
17874496171girish	if (!TXDMA_CHANNEL_VALID(channel)) {
17884496171girish		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
178952ccf84misaki		    " npi_txdma_channel_pre_state_get"
179052ccf84misaki		    " Invalid Input: channel <0x%x>",
179152ccf84misaki		    channel));
17924496171girish		return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel));
17934496171girish	}
17944496171girish
17954496171girish	TXDMA_REG_READ64(handle, TX_DMA_PRE_ST_REG, channel, &prep->value);
17964496171girish
17974496171girish	return (status);
17984496171girish}
17994496171girish
18004496171girishnpi_status_t
18014496171girishnpi_txdma_ring_error_get(npi_handle_t handle, uint8_t channel,
18024496171girish		p_txdma_ring_errlog_t ring_errlog_p)
18034496171girish{
18044496171girish	tx_rng_err_logh_t	logh;
18054496171girish	tx_rng_err_logl_t	logl;
18064496171girish	int			status = NPI_SUCCESS;
18074496171girish
1808a3c5bd6speer	ASSERT(TXDMA_CHANNEL_VALID(channel));
18094496171girish	if (!TXDMA_CHANNEL_VALID(channel)) {
18104496171girish		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
181152ccf84misaki		    " npi_txdma_ring_error_get"
181252ccf84misaki		    " Invalid Input: channel <0x%x>",
181352ccf84misaki		    channel));
18144496171girish		return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel));
18154496171girish	}
18164496171girish
18174496171girish	logh.value = 0;
18184496171girish	TXDMA_REG_READ64(handle, TX_RNG_ERR_LOGH_REG, channel, &logh.value);
18194496171girish	TXDMA_REG_READ64(handle, TX_RNG_ERR_LOGL_REG, channel, &logl.value);
18204496171girish	ring_errlog_p->logh.bits.ldw.err = logh.bits.ldw.err;
18214496171girish	ring_errlog_p->logh.bits.ldw.merr = logh.bits.ldw.merr;
18224496171girish	ring_errlog_p->logh.bits.ldw.errcode = logh.bits.ldw.errcode;
18234496171girish	ring_errlog_p->logh.bits.ldw.err_addr = logh.bits.ldw.err_addr;
18244496171girish	ring_errlog_p->logl.bits.ldw.err_addr = logl.bits.ldw.err_addr;
18254496171girish
18264496171girish	return (status);
18274496171girish}
18284496171girish
18294496171girishnpi_status_t
18304496171girishnpi_txdma_inj_par_error_clear(npi_handle_t handle)
18314496171girish{
18324496171girish	NXGE_REG_WR64(handle, TDMC_INJ_PAR_ERR_REG, 0);
18334496171girish
18344496171girish	return (NPI_SUCCESS);
18354496171girish}
18364496171girish
18374496171girishnpi_status_t
18384496171girishnpi_txdma_inj_par_error_set(npi_handle_t handle, uint32_t err_bits)
18394496171girish{
18404496171girish	tdmc_inj_par_err_t	inj;
18414496171girish
18424496171girish	inj.value = 0;
18434496171girish	inj.bits.ldw.inject_parity_error = (err_bits & TDMC_INJ_PAR_ERR_MASK);
18444496171girish	NXGE_REG_WR64(handle, TDMC_INJ_PAR_ERR_REG, inj.value);
18454496171girish
18464496171girish	return (NPI_SUCCESS);
18474496171girish}
18484496171girish
18494496171girishnpi_status_t
18504496171girishnpi_txdma_inj_par_error_update(npi_handle_t handle, uint32_t err_bits)
18514496171girish{
18524496171girish	tdmc_inj_par_err_t	inj;
18534496171girish
18544496171girish	inj.value = 0;
18554496171girish	NXGE_REG_RD64(handle, TDMC_INJ_PAR_ERR_REG, &inj.value);
18564496171girish	inj.value |= (err_bits & TDMC_INJ_PAR_ERR_MASK);
18574496171girish	NXGE_REG_WR64(handle, TDMC_INJ_PAR_ERR_REG, inj.value);
18584496171girish
18594496171girish	return (NPI_SUCCESS);
18604496171girish}
18614496171girish
18624496171girishnpi_status_t
18634496171girishnpi_txdma_inj_par_error_get(npi_handle_t handle, uint32_t *err_bits)
18644496171girish{
18654496171girish	tdmc_inj_par_err_t	inj;
18664496171girish
18674496171girish	inj.value = 0;
18684496171girish	NXGE_REG_RD64(handle, TDMC_INJ_PAR_ERR_REG, &inj.value);
18694496171girish	*err_bits = (inj.value & TDMC_INJ_PAR_ERR_MASK);
18704496171girish
18714496171girish	return (NPI_SUCCESS);
18724496171girish}
18734496171girish
18744496171girishnpi_status_t
18754496171girishnpi_txdma_dbg_sel_set(npi_handle_t handle, uint8_t dbg_sel)
18764496171girish{
18774496171girish	tdmc_dbg_sel_t		dbg;
18784496171girish
18794496171girish	dbg.value = 0;
18804496171girish	dbg.bits.ldw.dbg_sel = (dbg_sel & TDMC_DBG_SEL_MASK);
18814496171girish
18824496171girish	NXGE_REG_WR64(handle, TDMC_DBG_SEL_REG, dbg.value);
18834496171girish
18844496171girish	return (NPI_SUCCESS);
18854496171girish}
18864496171girish
18874496171girishnpi_status_t
18884496171girishnpi_txdma_training_vector_set(npi_handle_t handle, uint32_t training_vector)
18894496171girish{
18904496171girish	tdmc_training_t		vec;
18914496171girish
18924496171girish	vec.value = 0;
18934496171girish	vec.bits.ldw.vec = training_vector;
18944496171girish
18954496171girish	NXGE_REG_WR64(handle, TDMC_TRAINING_REG, vec.value);
18964496171girish
18974496171girish	return (NPI_SUCCESS);
18984496171girish}
18994496171girish
19004496171girish/*
19014496171girish * npi_txdma_dump_desc_one(npi_handle_t handle, p_tx_desc_t desc_p,
19024496171girish *	int desc_index)
19034496171girish *
19044496171girish *	Dumps the contents of transmit descriptors.
19054496171girish *
19064496171girish * Parameters:
19074496171girish *	handle		- NPI handle (register pointer is the
19084496171girish *			  descriptor address in memory).
19094496171girish *	desc_p		- pointer to place the descriptor contents
19104496171girish *	desc_index	- descriptor index
19114496171girish *
19124496171girish */
19134496171girish/*ARGSUSED*/
19144496171girishvoid
19154496171girishnpi_txdma_dump_desc_one(npi_handle_t handle, p_tx_desc_t desc_p, int desc_index)
19164496171girish{
19174496171girish
19184496171girish	tx_desc_t 		desc, *desp;
19194496171girish#ifdef NXGE_DEBUG
19204496171girish	uint64_t		sad;
19214496171girish	int			xfer_len;
19224496171girish#endif
19234496171girish
19244496171girish	NPI_DEBUG_MSG((handle.function, NPI_TDC_CTL,
192552ccf84misaki	    "\n==> npi_txdma_dump_desc_one: dump "
192652ccf84misaki	    " desc_p $%p descriptor entry %d\n",
192752ccf84misaki	    desc_p, desc_index));
19284496171girish	desc.value = 0;
19294496171girish	desp = ((desc_p != NULL) ? desc_p : (p_tx_desc_t)&desc);
19304496171girish	desp->value = NXGE_MEM_PIO_READ64(handle);
19314496171girish#ifdef NXGE_DEBUG
19324496171girish	sad = (desp->value & TX_PKT_DESC_SAD_MASK);
19334496171girish	xfer_len = ((desp->value & TX_PKT_DESC_TR_LEN_MASK) >>
193452ccf84misaki	    TX_PKT_DESC_TR_LEN_SHIFT);
19354496171girish#endif
19364496171girish	NPI_DEBUG_MSG((handle.function, NPI_TDC_CTL, "\n\t: value 0x%llx\n"
193752ccf84misaki	    "\t\tsad $%p\ttr_len %d len %d\tnptrs %d\tmark %d sop %d\n",
193852ccf84misaki	    desp->value,
193952ccf84misaki	    sad,
194052ccf84misaki	    desp->bits.hdw.tr_len,
194152ccf84misaki	    xfer_len,
194252ccf84misaki	    desp->bits.hdw.num_ptr,
194352ccf84misaki	    desp->bits.hdw.mark,
194452ccf84misaki	    desp->bits.hdw.sop));
19454496171girish
19464496171girish	NPI_DEBUG_MSG((handle.function, NPI_TDC_CTL,
194752ccf84misaki	    "\n<== npi_txdma_dump_desc_one: Done \n"));
19484496171girish
19494496171girish}
19504496171girish
19514496171girish/*ARGSUSED*/
19524496171girishvoid
19534496171girishnpi_txdma_dump_hdr(npi_handle_t handle, p_tx_pkt_header_t hdrp)
19544496171girish{
19554496171girish	NPI_DEBUG_MSG((handle.function, NPI_TDC_CTL,
195652ccf84misaki	    "\n==> npi_txdma_dump_hdr: dump\n"));
19574496171girish	NPI_DEBUG_MSG((handle.function, NPI_TDC_CTL,
195852ccf84misaki	    "\n\t: value 0x%llx\n"
195952ccf84misaki	    "\t\tpkttype 0x%x\tip_ver %d\tllc %d\tvlan %d \tihl %d\n"
196052ccf84misaki	    "\t\tl3start %d\tl4start %d\tl4stuff %d\n"
196152ccf84misaki	    "\t\txferlen %d\tpad %d\n",
196252ccf84misaki	    hdrp->value,
196352ccf84misaki	    hdrp->bits.hdw.cksum_en_pkt_type,
196452ccf84misaki	    hdrp->bits.hdw.ip_ver,
196552ccf84misaki	    hdrp->bits.hdw.llc,
196652ccf84misaki	    hdrp->bits.hdw.vlan,
196752ccf84misaki	    hdrp->bits.hdw.ihl,
196852ccf84misaki	    hdrp->bits.hdw.l3start,
196952ccf84misaki	    hdrp->bits.hdw.l4start,
197052ccf84misaki	    hdrp->bits.hdw.l4stuff,
197152ccf84misaki	    hdrp->bits.ldw.tot_xfer_len,
197252ccf84misaki	    hdrp->bits.ldw.pad));
19734496171girish
19744496171girish	NPI_DEBUG_MSG((handle.function, NPI_TDC_CTL,
197552ccf84misaki	    "\n<== npi_txdma_dump_hdr: Done \n"));
19764496171girish}
19774496171girish
19784496171girishnpi_status_t
19794496171girishnpi_txdma_inj_int_error_set(npi_handle_t handle, uint8_t channel,
19804496171girish	p_tdmc_intr_dbg_t erp)
19814496171girish{
19824496171girish	int		status = NPI_SUCCESS;
19834496171girish
1984a3c5bd6speer	ASSERT(TXDMA_CHANNEL_VALID(channel));
19854496171girish	if (!TXDMA_CHANNEL_VALID(channel)) {
19864496171girish		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
198752ccf84misaki		    " npi_txdma_inj_int_error_set"
198852ccf84misaki		    " Invalid Input: channel <0x%x>",
198952ccf84misaki		    channel));
19904496171girish		return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(channel));
19914496171girish	}
19924496171girish
19934496171girish	TXDMA_REG_WRITE64(handle, TDMC_INTR_DBG_REG, channel, erp->value);
19944496171girish
19954496171girish	return (status);
19964496171girish}
19974496171girish
19984496171girish/*
19994496171girish * Static functions start here.
20004496171girish */
20014496171girishstatic npi_status_t
20024496171girishnpi_txdma_control_reset_wait(npi_handle_t handle, uint8_t channel)
20034496171girish{
20044496171girish
20054496171girish	tx_cs_t		txcs;
20064496171girish	int		loop = 0;
20074496171girish
20084496171girish	do {
20094496171girish		NXGE_DELAY(TXDMA_WAIT_MSEC);
20104496171girish		TXDMA_REG_READ64(handle, TX_CS_REG, channel, &txcs.value);
20114496171girish		if (!txcs.bits.ldw.rst) {
20124496171girish			return (NPI_SUCCESS);
20134496171girish		}
20144496171girish		loop++;
20154496171girish	} while (loop < TXDMA_WAIT_LOOP);
20164496171girish
20174496171girish	if (loop == TXDMA_WAIT_LOOP) {
20184496171girish		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
201952ccf84misaki		    "npi_txdma_control_reset_wait: RST bit not "
202052ccf84misaki		    "cleared to 0 txcs.bits 0x%llx", txcs.value));
20214496171girish		return (NPI_FAILURE | NPI_TXDMA_RESET_FAILED);
20224496171girish	}
20234496171girish	return (NPI_SUCCESS);
20244496171girish}
20254496171girish
20264496171girishstatic npi_status_t
20274496171girishnpi_txdma_control_stop_wait(npi_handle_t handle, uint8_t channel)
20284496171girish{
20294496171girish	tx_cs_t		txcs;
20304496171girish	int		loop = 0;
20314496171girish
20324496171girish	do {
20334496171girish		NXGE_DELAY(TXDMA_WAIT_MSEC);
20344496171girish		TXDMA_REG_READ64(handle, TX_CS_REG, channel, &txcs.value);
20354496171girish		if (txcs.bits.ldw.sng_state) {
20364496171girish			return (NPI_SUCCESS);
20374496171girish		}
20384496171girish		loop++;
20394496171girish	} while (loop < TXDMA_WAIT_LOOP);
20404496171girish
20414496171girish	if (loop == TXDMA_WAIT_LOOP) {
20424496171girish		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
204352ccf84misaki		    "npi_txdma_control_stop_wait: SNG_STATE not "
204452ccf84misaki		    "set to 1 txcs.bits 0x%llx", txcs.value));
20454496171girish		return (NPI_FAILURE | NPI_TXDMA_STOP_FAILED);
20464496171girish	}
20474496171girish
20484496171girish	return (NPI_SUCCESS);
20494496171girish}
20504496171girish
20514496171girishstatic npi_status_t
20524496171girishnpi_txdma_control_resume_wait(npi_handle_t handle, uint8_t channel)
20534496171girish{
20544496171girish	tx_cs_t		txcs;
20554496171girish	int		loop = 0;
20564496171girish
20574496171girish	do {
20584496171girish		NXGE_DELAY(TXDMA_WAIT_MSEC);
20594496171girish		TXDMA_REG_READ64(handle, TX_CS_REG, channel, &txcs.value);
20604496171girish		if (!txcs.bits.ldw.sng_state) {
20614496171girish			return (NPI_SUCCESS);
20624496171girish		}
20634496171girish		loop++;
20644496171girish	} while (loop < TXDMA_WAIT_LOOP);
20654496171girish
20664496171girish	if (loop == TXDMA_WAIT_LOOP) {
20674496171girish		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
206852ccf84misaki		    "npi_txdma_control_resume_wait: sng_state not "
206952ccf84misaki		    "set to 0 txcs.bits 0x%llx", txcs.value));
20704496171girish		return (NPI_FAILURE | NPI_TXDMA_RESUME_FAILED);
20714496171girish	}
20724496171girish
20734496171girish	return (NPI_SUCCESS);
20744496171girish}
2075