144961713Sgirish /*
244961713Sgirish * CDDL HEADER START
344961713Sgirish *
444961713Sgirish * The contents of this file are subject to the terms of the
544961713Sgirish * Common Development and Distribution License (the "License").
644961713Sgirish * You may not use this file except in compliance with the License.
744961713Sgirish *
844961713Sgirish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
944961713Sgirish * or http://www.opensolaris.org/os/licensing.
1044961713Sgirish * See the License for the specific language governing permissions
1144961713Sgirish * and limitations under the License.
1244961713Sgirish *
1344961713Sgirish * When distributing Covered Code, include this CDDL HEADER in each
1444961713Sgirish * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1544961713Sgirish * If applicable, add the following below this CDDL HEADER, with the
1644961713Sgirish * fields enclosed by brackets "[]" replaced with your own identifying
1744961713Sgirish * information: Portions Copyright [yyyy] [name of copyright owner]
1844961713Sgirish *
1944961713Sgirish * CDDL HEADER END
2044961713Sgirish */
2144961713Sgirish /*
2252ccf843Smisaki * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
2344961713Sgirish * Use is subject to license terms.
2444961713Sgirish */
2544961713Sgirish
2644961713Sgirish #include <npi_txc.h>
2744961713Sgirish
2844961713Sgirish /*
2944961713Sgirish * Transmit Controller (TXC) Functions.
3044961713Sgirish */
3144961713Sgirish
3244961713Sgirish uint64_t txc_fzc_dmc_offset[] = {
3344961713Sgirish TXC_DMA_MAX_BURST_REG,
3444961713Sgirish TXC_DMA_MAX_LENGTH_REG
3544961713Sgirish };
3644961713Sgirish
3744961713Sgirish const char *txc_fzc_dmc_name[] = {
3844961713Sgirish "TXC_DMA_MAX_BURST_REG",
3944961713Sgirish "TXC_DMA_MAX_LENGTH_REG"
4044961713Sgirish };
4144961713Sgirish
4244961713Sgirish uint64_t txc_fzc_offset [] = {
4344961713Sgirish TXC_CONTROL_REG,
4444961713Sgirish TXC_TRAINING_REG,
4544961713Sgirish TXC_DEBUG_SELECT_REG,
4644961713Sgirish TXC_MAX_REORDER_REG,
4744961713Sgirish TXC_INT_STAT_DBG_REG,
4844961713Sgirish TXC_INT_STAT_REG,
4944961713Sgirish TXC_INT_MASK_REG
5044961713Sgirish };
5144961713Sgirish
5244961713Sgirish const char *txc_fzc_name [] = {
5344961713Sgirish "TXC_CONTROL_REG",
5444961713Sgirish "TXC_TRAINING_REG",
5544961713Sgirish "TXC_DEBUG_SELECT_REG",
5644961713Sgirish "TXC_MAX_REORDER_REG",
5744961713Sgirish "TXC_INT_STAT_DBG_REG",
5844961713Sgirish "TXC_INT_STAT_REG",
5944961713Sgirish "TXC_INT_MASK_REG"
6044961713Sgirish };
6144961713Sgirish
6244961713Sgirish uint64_t txc_fzc_port_offset[] = {
6344961713Sgirish TXC_PORT_CTL_REG,
6444961713Sgirish TXC_PORT_DMA_ENABLE_REG,
6544961713Sgirish TXC_PKT_STUFFED_REG,
6644961713Sgirish TXC_PKT_XMIT_REG,
6744961713Sgirish TXC_ROECC_CTL_REG,
6844961713Sgirish TXC_ROECC_ST_REG,
6944961713Sgirish TXC_RO_DATA0_REG,
7044961713Sgirish TXC_RO_DATA1_REG,
7144961713Sgirish TXC_RO_DATA2_REG,
7244961713Sgirish TXC_RO_DATA3_REG,
7344961713Sgirish TXC_RO_DATA4_REG,
7444961713Sgirish TXC_SFECC_CTL_REG,
7544961713Sgirish TXC_SFECC_ST_REG,
7644961713Sgirish TXC_SF_DATA0_REG,
7744961713Sgirish TXC_SF_DATA1_REG,
7844961713Sgirish TXC_SF_DATA2_REG,
7944961713Sgirish TXC_SF_DATA3_REG,
8044961713Sgirish TXC_SF_DATA4_REG,
8144961713Sgirish TXC_RO_TIDS_REG,
8244961713Sgirish TXC_RO_STATE0_REG,
8344961713Sgirish TXC_RO_STATE1_REG,
8444961713Sgirish TXC_RO_STATE2_REG,
8544961713Sgirish TXC_RO_STATE3_REG,
8644961713Sgirish TXC_RO_CTL_REG,
8744961713Sgirish TXC_RO_ST_DATA0_REG,
8844961713Sgirish TXC_RO_ST_DATA1_REG,
8944961713Sgirish TXC_RO_ST_DATA2_REG,
9044961713Sgirish TXC_RO_ST_DATA3_REG,
9144961713Sgirish TXC_PORT_PACKET_REQ_REG
9244961713Sgirish };
9344961713Sgirish
9444961713Sgirish const char *txc_fzc_port_name[] = {
9544961713Sgirish "TXC_PORT_CTL_REG",
9644961713Sgirish "TXC_PORT_DMA_ENABLE_REG",
9744961713Sgirish "TXC_PKT_STUFFED_REG",
9844961713Sgirish "TXC_PKT_XMIT_REG",
9944961713Sgirish "TXC_ROECC_CTL_REG",
10044961713Sgirish "TXC_ROECC_ST_REG",
10144961713Sgirish "TXC_RO_DATA0_REG",
10244961713Sgirish "TXC_RO_DATA1_REG",
10344961713Sgirish "TXC_RO_DATA2_REG",
10444961713Sgirish "TXC_RO_DATA3_REG",
10544961713Sgirish "TXC_RO_DATA4_REG",
10644961713Sgirish "TXC_SFECC_CTL_REG",
10744961713Sgirish "TXC_SFECC_ST_REG",
10844961713Sgirish "TXC_SF_DATA0_REG",
10944961713Sgirish "TXC_SF_DATA1_REG",
11044961713Sgirish "TXC_SF_DATA2_REG",
11144961713Sgirish "TXC_SF_DATA3_REG",
11244961713Sgirish "TXC_SF_DATA4_REG",
11344961713Sgirish "TXC_RO_TIDS_REG",
11444961713Sgirish "TXC_RO_STATE0_REG",
11544961713Sgirish "TXC_RO_STATE1_REG",
11644961713Sgirish "TXC_RO_STATE2_REG",
11744961713Sgirish "TXC_RO_STATE3_REG",
11844961713Sgirish "TXC_RO_CTL_REG",
11944961713Sgirish "TXC_RO_ST_DATA0_REG",
12044961713Sgirish "TXC_RO_ST_DATA1_REG",
12144961713Sgirish "TXC_RO_ST_DATA2_REG",
12244961713Sgirish "TXC_RO_ST_DATA3_REG",
12344961713Sgirish "TXC_PORT_PACKET_REQ_REG"
12444961713Sgirish };
12544961713Sgirish
12644961713Sgirish /*
12744961713Sgirish * npi_txc_dump_tdc_fzc_regs
12844961713Sgirish * Dumps the contents of TXC csrs and fzc registers
12944961713Sgirish *
13044961713Sgirish * Input:
131a3c5bd6dSspeer * handle - NPI handle
13244961713Sgirish * tdc: TX DMA number
13344961713Sgirish *
13444961713Sgirish * return:
13544961713Sgirish * NPI_SUCCESS
13644961713Sgirish * NPI_FAILURE
13744961713Sgirish * NPI_TXC_CHANNEL_INVALID
13844961713Sgirish *
13944961713Sgirish */
14044961713Sgirish npi_status_t
npi_txc_dump_tdc_fzc_regs(npi_handle_t handle,uint8_t tdc)14144961713Sgirish npi_txc_dump_tdc_fzc_regs(npi_handle_t handle, uint8_t tdc)
14244961713Sgirish {
14344961713Sgirish uint64_t value, offset;
14444961713Sgirish int num_regs, i;
14544961713Sgirish
146a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(tdc));
14744961713Sgirish if (!TXDMA_CHANNEL_VALID(tdc)) {
14844961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
14952ccf843Smisaki "npi_txc_dump_tdc_fzc_regs"
15052ccf843Smisaki " Invalid TDC number %d \n",
15152ccf843Smisaki tdc));
15244961713Sgirish return (NPI_FAILURE | NPI_TXC_CHANNEL_INVALID(tdc));
15344961713Sgirish }
15444961713Sgirish
15544961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
15652ccf843Smisaki "\nTXC FZC DMC Register Dump for Channel %d\n",
15752ccf843Smisaki tdc));
15844961713Sgirish
15944961713Sgirish num_regs = sizeof (txc_fzc_dmc_offset) / sizeof (uint64_t);
16044961713Sgirish for (i = 0; i < num_regs; i++) {
16144961713Sgirish offset = TXC_FZC_REG_CN_OFFSET(txc_fzc_dmc_offset[i], tdc);
16244961713Sgirish NXGE_REG_RD64(handle, offset, &value);
16344961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, "0x%08llx "
16452ccf843Smisaki "%s\t 0x%08llx \n",
16552ccf843Smisaki offset, txc_fzc_dmc_name[i], value));
16644961713Sgirish }
16744961713Sgirish
16844961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
16952ccf843Smisaki "\n TXC FZC Register Dump for Channel %d done\n", tdc));
17044961713Sgirish
17144961713Sgirish return (NPI_SUCCESS);
17244961713Sgirish }
17344961713Sgirish
17444961713Sgirish /*
17544961713Sgirish * npi_txc_dump_fzc_regs
17644961713Sgirish * Dumps the contents of txc csrs and fzc registers
17744961713Sgirish *
17844961713Sgirish *
17944961713Sgirish * return:
18044961713Sgirish * NPI_SUCCESS
18144961713Sgirish * NPI_FAILURE
18244961713Sgirish *
18344961713Sgirish */
18444961713Sgirish npi_status_t
npi_txc_dump_fzc_regs(npi_handle_t handle)18544961713Sgirish npi_txc_dump_fzc_regs(npi_handle_t handle)
18644961713Sgirish {
18744961713Sgirish
18844961713Sgirish uint64_t value;
18944961713Sgirish int num_regs, i;
19044961713Sgirish
19144961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
19252ccf843Smisaki "\nTXC FZC Common Register Dump\n"));
19344961713Sgirish
19444961713Sgirish num_regs = sizeof (txc_fzc_offset) / sizeof (uint64_t);
19544961713Sgirish for (i = 0; i < num_regs; i++) {
19644961713Sgirish NXGE_REG_RD64(handle, txc_fzc_offset[i], &value);
19744961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, "0x%08llx "
19852ccf843Smisaki "%s\t 0x%08llx \n",
19952ccf843Smisaki txc_fzc_offset[i], txc_fzc_name[i], value));
20044961713Sgirish }
20144961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
20252ccf843Smisaki "\n TXC FZC Common Register Dump Done \n"));
20344961713Sgirish
20444961713Sgirish return (NPI_SUCCESS);
20544961713Sgirish }
20644961713Sgirish
20744961713Sgirish /*
20844961713Sgirish * npi_txc_dump_port_fzc_regs
20944961713Sgirish * Dumps the contents of TXC csrs and fzc registers
21044961713Sgirish *
21144961713Sgirish * Input:
212a3c5bd6dSspeer * handle - NPI handle
21344961713Sgirish * port: port number
21444961713Sgirish *
21544961713Sgirish * return:
21644961713Sgirish * NPI_SUCCESS
21744961713Sgirish * NPI_FAILURE
21844961713Sgirish *
21944961713Sgirish */
22044961713Sgirish npi_status_t
npi_txc_dump_port_fzc_regs(npi_handle_t handle,uint8_t port)22144961713Sgirish npi_txc_dump_port_fzc_regs(npi_handle_t handle, uint8_t port)
22244961713Sgirish {
22344961713Sgirish uint64_t value, offset;
22444961713Sgirish int num_regs, i;
22544961713Sgirish
226a3c5bd6dSspeer ASSERT(IS_PORT_NUM_VALID(port));
22744961713Sgirish
22844961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
22952ccf843Smisaki "\nTXC FZC PORT Register Dump for port %d\n", port));
23044961713Sgirish
23144961713Sgirish num_regs = sizeof (txc_fzc_port_offset) / sizeof (uint64_t);
23244961713Sgirish for (i = 0; i < num_regs; i++) {
23344961713Sgirish offset = TXC_FZC_REG_PT_OFFSET(txc_fzc_port_offset[i], port);
23444961713Sgirish NXGE_REG_RD64(handle, offset, &value);
23544961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, "0x%08llx "
23652ccf843Smisaki "%s\t 0x%08llx \n",
23752ccf843Smisaki offset, txc_fzc_port_name[i], value));
23844961713Sgirish }
23944961713Sgirish
24044961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
24152ccf843Smisaki "\n TXC FZC Register Dump for port %d done\n", port));
24244961713Sgirish
24344961713Sgirish return (NPI_SUCCESS);
24444961713Sgirish }
24544961713Sgirish
24644961713Sgirish /*
24744961713Sgirish * npi_txc_dma_max_burst():
24844961713Sgirish * This function is called to configure the max burst bytes.
24944961713Sgirish *
25044961713Sgirish * Parameters:
25144961713Sgirish * handle - NPI handle
25244961713Sgirish * op_mode - OP_GET: get max burst value
25344961713Sgirish * - OP_SET: set max burst value
25444961713Sgirish * channel - channel number (0 - 23)
25544961713Sgirish * dma_max_burst_p - pointer to store or used for max burst value.
25644961713Sgirish * Return:
25744961713Sgirish * NPI_SUCCESS - If operation is complete successfully.
25844961713Sgirish *
25944961713Sgirish * Error:
26044961713Sgirish * NPI_FAILURE -
26144961713Sgirish * NPI_TXC_OPCODE_INVALID
26244961713Sgirish * NPI_TXC_CHANNEL_INVALID
26344961713Sgirish */
26444961713Sgirish npi_status_t
npi_txc_dma_max_burst(npi_handle_t handle,io_op_t op_mode,uint8_t channel,uint32_t * dma_max_burst_p)26544961713Sgirish npi_txc_dma_max_burst(npi_handle_t handle, io_op_t op_mode, uint8_t channel,
26644961713Sgirish uint32_t *dma_max_burst_p)
26744961713Sgirish {
26844961713Sgirish uint64_t val;
26944961713Sgirish
270a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(channel));
27144961713Sgirish if (!TXDMA_CHANNEL_VALID(channel)) {
27244961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
27352ccf843Smisaki " npi_txc_dma_max_burst"
27452ccf843Smisaki " Invalid Input: channel <0x%x>",
27552ccf843Smisaki channel));
27644961713Sgirish return (NPI_FAILURE | NPI_TXC_CHANNEL_INVALID(channel));
27744961713Sgirish }
27844961713Sgirish
27944961713Sgirish switch (op_mode) {
28044961713Sgirish case OP_GET:
28144961713Sgirish TXC_FZC_REG_READ64(handle, TXC_DMA_MAX_BURST_REG, channel,
28252ccf843Smisaki &val);
28344961713Sgirish *dma_max_burst_p = (uint32_t)val;
28444961713Sgirish break;
28544961713Sgirish
28644961713Sgirish case OP_SET:
28744961713Sgirish TXC_FZC_REG_WRITE64(handle,
28852ccf843Smisaki TXC_DMA_MAX_BURST_REG, channel, *dma_max_burst_p);
28944961713Sgirish break;
29044961713Sgirish
29144961713Sgirish default:
29244961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
29352ccf843Smisaki " npi_txc_dma_max_burst"
29452ccf843Smisaki " Invalid Input: burst <0x%x>",
29552ccf843Smisaki op_mode));
29644961713Sgirish return (NPI_FAILURE | NPI_TXC_OPCODE_INVALID(channel));
29744961713Sgirish }
29844961713Sgirish
29944961713Sgirish return (NPI_SUCCESS);
30044961713Sgirish }
30144961713Sgirish
30244961713Sgirish /*
30344961713Sgirish * npi_txc_dma_max_burst_set():
30444961713Sgirish * This function is called to set the max burst bytes.
30544961713Sgirish *
30644961713Sgirish * Parameters:
30744961713Sgirish * handle - NPI handle
30844961713Sgirish * channel - channel number (0 - 23)
30944961713Sgirish * max_burst - max burst to set
31044961713Sgirish * Return:
31144961713Sgirish * NPI_SUCCESS - If operation is complete successfully.
31244961713Sgirish *
31344961713Sgirish * Error:
31444961713Sgirish * NPI_FAILURE -
31544961713Sgirish */
31644961713Sgirish npi_status_t
npi_txc_dma_max_burst_set(npi_handle_t handle,uint8_t channel,uint32_t max_burst)31744961713Sgirish npi_txc_dma_max_burst_set(npi_handle_t handle, uint8_t channel,
31844961713Sgirish uint32_t max_burst)
31944961713Sgirish {
320a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(channel));
32144961713Sgirish if (!TXDMA_CHANNEL_VALID(channel)) {
32244961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
32352ccf843Smisaki " npi_txc_dma_max_burst_set"
32452ccf843Smisaki " Invalid Input: channel <0x%x>",
32552ccf843Smisaki channel));
32644961713Sgirish return (NPI_FAILURE | NPI_TXC_CHANNEL_INVALID(channel));
32744961713Sgirish }
32844961713Sgirish
32944961713Sgirish TXC_FZC_REG_WRITE64(handle, TXC_DMA_MAX_BURST_REG,
33052ccf843Smisaki channel, (uint64_t)max_burst);
33144961713Sgirish
33244961713Sgirish return (NPI_SUCCESS);
33344961713Sgirish }
33444961713Sgirish
33544961713Sgirish /*
33644961713Sgirish * npi_txc_dma_bytes_transmitted():
33744961713Sgirish * This function is called to get # of bytes transmitted by
33844961713Sgirish * DMA (hardware register is cleared on read).
33944961713Sgirish *
34044961713Sgirish * Parameters:
34144961713Sgirish * handle - NPI handle
34244961713Sgirish * channel - channel number (0 - 23)
34344961713Sgirish * dma_bytes_p - pointer to store bytes transmitted.
34444961713Sgirish * Return:
34544961713Sgirish * NPI_SUCCESS - If get is complete successfully.
34644961713Sgirish *
34744961713Sgirish * Error:
34844961713Sgirish * NPI_FAILURE -
34944961713Sgirish * NPI_TXC_PORT_INVALID
35044961713Sgirish */
35144961713Sgirish npi_status_t
npi_txc_dma_bytes_transmitted(npi_handle_t handle,uint8_t channel,uint32_t * dma_bytes_p)35244961713Sgirish npi_txc_dma_bytes_transmitted(npi_handle_t handle, uint8_t channel,
35344961713Sgirish uint32_t *dma_bytes_p)
35444961713Sgirish {
35544961713Sgirish uint64_t val;
35644961713Sgirish
357a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(channel));
35844961713Sgirish if (!TXDMA_CHANNEL_VALID(channel)) {
35944961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
36052ccf843Smisaki " npi_txc_dma_bytes_transmitted"
36152ccf843Smisaki " Invalid Input: channel %d",
36252ccf843Smisaki channel));
36344961713Sgirish return (NPI_FAILURE | NPI_TXC_CHANNEL_INVALID(channel));
36444961713Sgirish }
36544961713Sgirish
36644961713Sgirish TXC_FZC_REG_READ64(handle, TXC_DMA_MAX_LENGTH_REG, channel, &val);
36744961713Sgirish *dma_bytes_p = (uint32_t)val;
36844961713Sgirish
36944961713Sgirish return (NPI_SUCCESS);
37044961713Sgirish }
37144961713Sgirish
37244961713Sgirish /*
37344961713Sgirish * npi_txc_control():
37444961713Sgirish * This function is called to get or set the control register.
37544961713Sgirish *
37644961713Sgirish * Parameters:
37744961713Sgirish * handle - NPI handle
37844961713Sgirish * op_mode - OP_GET: get control register value
37944961713Sgirish * OP_SET: set control register value
38044961713Sgirish * txc_control_p - pointer to hardware defined data structure.
38144961713Sgirish * Return:
38244961713Sgirish * NPI_SUCCESS - If operation is complete successfully.
38344961713Sgirish *
38444961713Sgirish * Error:
38544961713Sgirish * NPI_FAILURE -
38644961713Sgirish * NPI_TXC_OPCODE_INVALID
38744961713Sgirish * NPI_TXC_PORT_INVALID
38844961713Sgirish */
38944961713Sgirish npi_status_t
npi_txc_control(npi_handle_t handle,io_op_t op_mode,p_txc_control_t txc_control_p)39044961713Sgirish npi_txc_control(npi_handle_t handle, io_op_t op_mode,
39144961713Sgirish p_txc_control_t txc_control_p)
39244961713Sgirish {
39344961713Sgirish switch (op_mode) {
39444961713Sgirish case OP_GET:
39544961713Sgirish NXGE_REG_RD64(handle, TXC_CONTROL_REG, &txc_control_p->value);
39644961713Sgirish break;
39744961713Sgirish
39844961713Sgirish case OP_SET:
39944961713Sgirish NXGE_REG_WR64(handle, TXC_CONTROL_REG,
40052ccf843Smisaki txc_control_p->value);
40144961713Sgirish break;
40244961713Sgirish
40344961713Sgirish default:
40444961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
40552ccf843Smisaki " npi_txc_control"
40652ccf843Smisaki " Invalid Input: control 0x%x",
40752ccf843Smisaki op_mode));
40844961713Sgirish return (NPI_FAILURE | NPI_TXC_OPCODE_INVALID(op_mode));
40944961713Sgirish }
41044961713Sgirish
41144961713Sgirish return (NPI_SUCCESS);
41244961713Sgirish }
41344961713Sgirish
41444961713Sgirish /*
41544961713Sgirish * npi_txc_global_enable():
41644961713Sgirish * This function is called to globally enable TXC.
41744961713Sgirish *
41844961713Sgirish * Parameters:
41944961713Sgirish * handle - NPI handle
42044961713Sgirish * Return:
42144961713Sgirish * NPI_SUCCESS - If enable is complete successfully.
42244961713Sgirish *
42344961713Sgirish * Error:
42444961713Sgirish */
42544961713Sgirish npi_status_t
npi_txc_global_enable(npi_handle_t handle)42644961713Sgirish npi_txc_global_enable(npi_handle_t handle)
42744961713Sgirish {
42844961713Sgirish txc_control_t cntl;
42944961713Sgirish uint64_t val;
43044961713Sgirish
43144961713Sgirish cntl.value = 0;
43244961713Sgirish cntl.bits.ldw.txc_enabled = 1;
43344961713Sgirish
43444961713Sgirish NXGE_REG_RD64(handle, TXC_CONTROL_REG, &val);
43544961713Sgirish NXGE_REG_WR64(handle, TXC_CONTROL_REG, val | cntl.value);
43644961713Sgirish
43744961713Sgirish return (NPI_SUCCESS);
43844961713Sgirish }
43944961713Sgirish
44044961713Sgirish /*
44144961713Sgirish * npi_txc_global_disable():
44244961713Sgirish * This function is called to globally disable TXC.
44344961713Sgirish *
44444961713Sgirish * Parameters:
44544961713Sgirish * handle - NPI handle
44644961713Sgirish * Return:
44744961713Sgirish * NPI_SUCCESS - If disable is complete successfully.
44844961713Sgirish *
44944961713Sgirish * Error:
45044961713Sgirish */
45144961713Sgirish npi_status_t
npi_txc_global_disable(npi_handle_t handle)45244961713Sgirish npi_txc_global_disable(npi_handle_t handle)
45344961713Sgirish {
45444961713Sgirish txc_control_t cntl;
45544961713Sgirish uint64_t val;
45644961713Sgirish
45744961713Sgirish
45844961713Sgirish cntl.value = 0;
45944961713Sgirish cntl.bits.ldw.txc_enabled = 0;
46044961713Sgirish
46144961713Sgirish NXGE_REG_RD64(handle, TXC_CONTROL_REG, &val);
46244961713Sgirish NXGE_REG_WR64(handle, TXC_CONTROL_REG, val | cntl.value);
46344961713Sgirish
46444961713Sgirish return (NPI_SUCCESS);
46544961713Sgirish }
46644961713Sgirish
46744961713Sgirish /*
46844961713Sgirish * npi_txc_control_clear():
46944961713Sgirish * This function is called to clear all bits.
47044961713Sgirish *
47144961713Sgirish * Parameters:
47244961713Sgirish * handle - NPI handle
47344961713Sgirish * Return:
47444961713Sgirish * NPI_SUCCESS - If reset all bits to 0s is complete successfully.
47544961713Sgirish *
47644961713Sgirish * Error:
47744961713Sgirish */
47844961713Sgirish npi_status_t
npi_txc_control_clear(npi_handle_t handle,uint8_t port)47944961713Sgirish npi_txc_control_clear(npi_handle_t handle, uint8_t port)
48044961713Sgirish {
481a3c5bd6dSspeer ASSERT(IS_PORT_NUM_VALID(port));
48244961713Sgirish
48344961713Sgirish NXGE_REG_WR64(handle, TXC_PORT_CTL_REG, TXC_PORT_CNTL_CLEAR);
48444961713Sgirish
48544961713Sgirish return (NPI_SUCCESS);
48644961713Sgirish }
48744961713Sgirish
48844961713Sgirish /*
48944961713Sgirish * npi_txc_training_set():
49044961713Sgirish * This function is called to set the debug training vector.
49144961713Sgirish *
49244961713Sgirish * Parameters:
49344961713Sgirish * handle - NPI handle
49444961713Sgirish * vector - training vector to set.
49544961713Sgirish * Return:
49644961713Sgirish * NPI_SUCCESS
49744961713Sgirish *
49844961713Sgirish * Error:
49944961713Sgirish * NPI_FAILURE -
50044961713Sgirish */
50144961713Sgirish npi_status_t
npi_txc_training_set(npi_handle_t handle,uint32_t vector)50244961713Sgirish npi_txc_training_set(npi_handle_t handle, uint32_t vector)
50344961713Sgirish {
50444961713Sgirish NXGE_REG_WR64(handle, TXC_TRAINING_REG, (uint64_t)vector);
50544961713Sgirish
50644961713Sgirish return (NPI_SUCCESS);
50744961713Sgirish }
50844961713Sgirish
50944961713Sgirish /*
51044961713Sgirish * npi_txc_training_get():
51144961713Sgirish * This function is called to get the debug training vector.
51244961713Sgirish *
51344961713Sgirish * Parameters:
51444961713Sgirish * handle - NPI handle
51544961713Sgirish * vector_p - pointer to store training vector.
51644961713Sgirish * Return:
51744961713Sgirish * NPI_SUCCESS
51844961713Sgirish *
51944961713Sgirish * Error:
52044961713Sgirish * NPI_FAILURE -
52144961713Sgirish */
52244961713Sgirish npi_status_t
npi_txc_training_get(npi_handle_t handle,uint32_t * vector_p)52344961713Sgirish npi_txc_training_get(npi_handle_t handle, uint32_t *vector_p)
52444961713Sgirish {
52544961713Sgirish uint64_t val;
52644961713Sgirish
52744961713Sgirish NXGE_REG_RD64(handle, (TXC_TRAINING_REG & TXC_TRAINING_VECTOR_MASK),
52852ccf843Smisaki &val);
52944961713Sgirish *vector_p = (uint32_t)val;
53044961713Sgirish
53144961713Sgirish return (NPI_SUCCESS);
53244961713Sgirish }
53344961713Sgirish
53444961713Sgirish /*
53544961713Sgirish * npi_txc_port_enable():
53644961713Sgirish * This function is called to enable a particular port.
53744961713Sgirish *
53844961713Sgirish * Parameters:
53944961713Sgirish * handle - NPI handle
54044961713Sgirish * port - port number (0 - 3)
54144961713Sgirish * Return:
54244961713Sgirish * NPI_SUCCESS - If port is enabled successfully.
54344961713Sgirish *
54444961713Sgirish * Error:
54544961713Sgirish * NPI_FAILURE -
54644961713Sgirish * NPI_TXC_PORT_INVALID
54744961713Sgirish */
54844961713Sgirish npi_status_t
npi_txc_port_enable(npi_handle_t handle,uint8_t port)54944961713Sgirish npi_txc_port_enable(npi_handle_t handle, uint8_t port)
55044961713Sgirish {
55144961713Sgirish uint64_t val;
55244961713Sgirish
553a3c5bd6dSspeer ASSERT(IS_PORT_NUM_VALID(port));
55444961713Sgirish
55544961713Sgirish NXGE_REG_RD64(handle, TXC_CONTROL_REG, &val);
55644961713Sgirish NXGE_REG_WR64(handle, TXC_CONTROL_REG, val | (1 << port));
55744961713Sgirish
55844961713Sgirish return (NPI_SUCCESS);
55944961713Sgirish }
56044961713Sgirish
56144961713Sgirish /*
56244961713Sgirish * npi_txc_port_disable():
56344961713Sgirish * This function is called to disable a particular port.
56444961713Sgirish *
56544961713Sgirish * Parameters:
56644961713Sgirish * handle - NPI handle
56744961713Sgirish * port - port number (0 - 3)
56844961713Sgirish * Return:
56944961713Sgirish * NPI_SUCCESS - If port is disabled successfully.
57044961713Sgirish *
57144961713Sgirish * Error:
57244961713Sgirish * NPI_FAILURE -
57344961713Sgirish * NPI_TXC_PORT_INVALID
57444961713Sgirish */
57544961713Sgirish npi_status_t
npi_txc_port_disable(npi_handle_t handle,uint8_t port)57644961713Sgirish npi_txc_port_disable(npi_handle_t handle, uint8_t port)
57744961713Sgirish {
57844961713Sgirish uint64_t val;
57944961713Sgirish
580a3c5bd6dSspeer ASSERT(IS_PORT_NUM_VALID(port));
58144961713Sgirish
58244961713Sgirish NXGE_REG_RD64(handle, TXC_CONTROL_REG, &val);
58344961713Sgirish NXGE_REG_WR64(handle, TXC_CONTROL_REG, (val & ~(1 << port)));
58444961713Sgirish
58544961713Sgirish return (NPI_SUCCESS);
58644961713Sgirish }
58744961713Sgirish
58844961713Sgirish /*
58944961713Sgirish * npi_txc_port_dma_enable():
59044961713Sgirish * This function is called to bind DMA channels (bitmap) to a port.
59144961713Sgirish *
59244961713Sgirish * Parameters:
59344961713Sgirish * handle - NPI handle
59444961713Sgirish * port - port number (0 - 3)
59544961713Sgirish * port_dma_list_bitmap - channels bitmap
59644961713Sgirish * (1 to bind, 0 - 23 bits one bit/channel)
59744961713Sgirish * Return:
59844961713Sgirish * NPI_SUCCESS - If channels are bound successfully.
59944961713Sgirish *
60044961713Sgirish * Error:
60144961713Sgirish * NPI_FAILURE -
60244961713Sgirish * NPI_TXC_PORT_INVALID
60344961713Sgirish */
60444961713Sgirish npi_status_t
npi_txc_port_dma_enable(npi_handle_t handle,uint8_t port,uint32_t port_dma_list_bitmap)60544961713Sgirish npi_txc_port_dma_enable(npi_handle_t handle, uint8_t port,
60644961713Sgirish uint32_t port_dma_list_bitmap)
60744961713Sgirish {
60844961713Sgirish
609a3c5bd6dSspeer ASSERT(IS_PORT_NUM_VALID(port));
61044961713Sgirish
61144961713Sgirish TXC_FZC_CNTL_REG_WRITE64(handle, TXC_PORT_DMA_ENABLE_REG, port,
61252ccf843Smisaki port_dma_list_bitmap);
61344961713Sgirish return (NPI_SUCCESS);
61444961713Sgirish }
61544961713Sgirish
61644961713Sgirish npi_status_t
npi_txc_port_dma_list_get(npi_handle_t handle,uint8_t port,uint32_t * port_dma_list_bitmap)61744961713Sgirish npi_txc_port_dma_list_get(npi_handle_t handle, uint8_t port,
61844961713Sgirish uint32_t *port_dma_list_bitmap)
61944961713Sgirish {
62044961713Sgirish uint64_t val;
62144961713Sgirish
622a3c5bd6dSspeer ASSERT(IS_PORT_NUM_VALID(port));
62344961713Sgirish
62444961713Sgirish TXC_FZC_CNTL_REG_READ64(handle, TXC_PORT_DMA_ENABLE_REG, port, &val);
62544961713Sgirish *port_dma_list_bitmap = (uint32_t)(val & TXC_DMA_DMA_LIST_MASK);
62644961713Sgirish
62744961713Sgirish return (NPI_SUCCESS);
62844961713Sgirish }
62944961713Sgirish
63044961713Sgirish /*
63144961713Sgirish * npi_txc_port_dma_channel_enable():
63244961713Sgirish * This function is called to bind a channel to a port.
63344961713Sgirish *
63444961713Sgirish * Parameters:
63544961713Sgirish * handle - NPI handle
63644961713Sgirish * port - port number (0 - 3)
63744961713Sgirish * channel - channel number (0 - 23)
63844961713Sgirish * Return:
63944961713Sgirish * NPI_SUCCESS - If channel is bound successfully.
64044961713Sgirish *
64144961713Sgirish * Error:
64244961713Sgirish * NPI_FAILURE -
64344961713Sgirish * NPI_TXC_PORT_INVALID -
64444961713Sgirish */
64544961713Sgirish npi_status_t
npi_txc_port_dma_channel_enable(npi_handle_t handle,uint8_t port,uint8_t channel)64644961713Sgirish npi_txc_port_dma_channel_enable(npi_handle_t handle, uint8_t port,
64744961713Sgirish uint8_t channel)
64844961713Sgirish {
64944961713Sgirish uint64_t val;
65044961713Sgirish
651a3c5bd6dSspeer ASSERT(IS_PORT_NUM_VALID(port));
652a3c5bd6dSspeer
653a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(channel));
65444961713Sgirish if (!TXDMA_CHANNEL_VALID(channel)) {
65544961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
65652ccf843Smisaki " npi_txc_port_dma_channel_enable"
65752ccf843Smisaki " Invalid Input: channel <0x%x>", channel));
65844961713Sgirish return (NPI_FAILURE | NPI_TXC_CHANNEL_INVALID(channel));
65944961713Sgirish }
66044961713Sgirish
66144961713Sgirish TXC_FZC_CNTL_REG_READ64(handle, TXC_PORT_DMA_ENABLE_REG, port, &val);
66244961713Sgirish TXC_FZC_CNTL_REG_WRITE64(handle, TXC_PORT_DMA_ENABLE_REG, port,
66352ccf843Smisaki (val | (1 << channel)));
66444961713Sgirish
66544961713Sgirish return (NPI_SUCCESS);
66644961713Sgirish }
66744961713Sgirish
66844961713Sgirish /*
66944961713Sgirish * npi_txc_port_dma_channel_disable():
67044961713Sgirish * This function is called to unbind a channel to a port.
67144961713Sgirish *
67244961713Sgirish * Parameters:
67344961713Sgirish * handle - NPI handle
67444961713Sgirish * port - port number (0 - 3)
67544961713Sgirish * channel - channel number (0 - 23)
67644961713Sgirish * Return:
67744961713Sgirish * NPI_SUCCESS - If channel is unbound successfully.
67844961713Sgirish *
67944961713Sgirish * Error:
68044961713Sgirish * NPI_FAILURE -
68144961713Sgirish * NPI_TXC_PORT_INVALID -
68244961713Sgirish */
68344961713Sgirish npi_status_t
npi_txc_port_dma_channel_disable(npi_handle_t handle,uint8_t port,uint8_t channel)68444961713Sgirish npi_txc_port_dma_channel_disable(npi_handle_t handle, uint8_t port,
68544961713Sgirish uint8_t channel)
68644961713Sgirish {
68744961713Sgirish uint64_t val;
68844961713Sgirish
689a3c5bd6dSspeer ASSERT(IS_PORT_NUM_VALID(port));
69044961713Sgirish
691a3c5bd6dSspeer ASSERT(TXDMA_CHANNEL_VALID(channel));
69244961713Sgirish if (!TXDMA_CHANNEL_VALID(channel)) {
69344961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
69452ccf843Smisaki " npi_txc_port_dma_channel_disable"
69552ccf843Smisaki " Invalid Input: channel <0x%x>", channel));
69644961713Sgirish return (NPI_FAILURE | NPI_TXC_CHANNEL_INVALID(channel));
69744961713Sgirish }
69844961713Sgirish
69944961713Sgirish TXC_FZC_CNTL_REG_READ64(handle, TXC_PORT_DMA_ENABLE_REG, port, &val)
70044961713Sgirish TXC_FZC_CNTL_REG_WRITE64(handle, TXC_PORT_DMA_ENABLE_REG, port,
70152ccf843Smisaki val & ~(1 << channel));
70244961713Sgirish
70344961713Sgirish return (NPI_SUCCESS);
70444961713Sgirish }
70544961713Sgirish
70644961713Sgirish /*
70744961713Sgirish * npi_txc_max_reorder_set():
70844961713Sgirish * This function is called to set the per port reorder resources
70944961713Sgirish *
71044961713Sgirish * Parameters:
71144961713Sgirish * handle - NPI handle
71244961713Sgirish * port - port to set
71344961713Sgirish * reorder - reorder resources (4 bits)
71444961713Sgirish * Return:
71544961713Sgirish * NPI_SUCCESS
71644961713Sgirish *
71744961713Sgirish * Error:
71844961713Sgirish * NPI_FAILURE -
71944961713Sgirish */
72044961713Sgirish npi_status_t
npi_txc_reorder_set(npi_handle_t handle,uint8_t port,uint8_t * reorder)72144961713Sgirish npi_txc_reorder_set(npi_handle_t handle, uint8_t port, uint8_t *reorder)
72244961713Sgirish {
72344961713Sgirish uint64_t val;
72444961713Sgirish
725a3c5bd6dSspeer ASSERT(IS_PORT_NUM_VALID(port));
72644961713Sgirish
72744961713Sgirish NXGE_REG_RD64(handle, TXC_MAX_REORDER_REG, &val);
72844961713Sgirish
72944961713Sgirish val |= (*reorder << TXC_MAX_REORDER_SHIFT(port));
73044961713Sgirish
73144961713Sgirish NXGE_REG_WR64(handle, TXC_MAX_REORDER_REG, val);
73244961713Sgirish
73344961713Sgirish return (NPI_SUCCESS);
73444961713Sgirish }
73544961713Sgirish
73644961713Sgirish /*
73744961713Sgirish * npi_txc_reorder_get():
73844961713Sgirish * This function is called to get the txc reorder resources.
73944961713Sgirish *
74044961713Sgirish * Parameters:
74144961713Sgirish * handle - NPI handle
74244961713Sgirish * port - port to get
74344961713Sgirish * reorder - data to be stored at
74444961713Sgirish * Return:
74544961713Sgirish * NPI_SUCCESS
74644961713Sgirish *
74744961713Sgirish * Error:
74844961713Sgirish * NPI_FAILURE -
74944961713Sgirish */
75044961713Sgirish npi_status_t
npi_txc_reorder_get(npi_handle_t handle,uint8_t port,uint32_t * reorder)75144961713Sgirish npi_txc_reorder_get(npi_handle_t handle, uint8_t port, uint32_t *reorder)
75244961713Sgirish {
75344961713Sgirish uint64_t val;
75444961713Sgirish
755a3c5bd6dSspeer ASSERT(IS_PORT_NUM_VALID(port));
75644961713Sgirish
75744961713Sgirish NXGE_REG_RD64(handle, TXC_MAX_REORDER_REG, &val);
75844961713Sgirish
75944961713Sgirish *reorder = (uint8_t)(val >> TXC_MAX_REORDER_SHIFT(port));
76044961713Sgirish
76144961713Sgirish return (NPI_SUCCESS);
76244961713Sgirish }
76344961713Sgirish
76444961713Sgirish /*
76544961713Sgirish * npi_txc_pkt_stuffed_get():
76644961713Sgirish * This function is called to get total # of packets processed
76744961713Sgirish * by reorder engine and packetAssy engine.
76844961713Sgirish *
76944961713Sgirish * Parameters:
77044961713Sgirish * handle - NPI handle
77144961713Sgirish * port - port number (0 - 3)
77244961713Sgirish * pkt_assy_p - packets processed by Assy engine.
77344961713Sgirish * pkt_reorder_p - packets processed by reorder engine.
77444961713Sgirish *
77544961713Sgirish * Return:
77644961713Sgirish * NPI_SUCCESS - If get is complete successfully.
77744961713Sgirish *
77844961713Sgirish * Error:
77944961713Sgirish * NPI_FAILURE -
78044961713Sgirish * NPI_TXC_PORT_INVALID
78144961713Sgirish */
78244961713Sgirish npi_status_t
npi_txc_pkt_stuffed_get(npi_handle_t handle,uint8_t port,uint32_t * pkt_assy_p,uint32_t * pkt_reorder_p)78344961713Sgirish npi_txc_pkt_stuffed_get(npi_handle_t handle, uint8_t port,
78444961713Sgirish uint32_t *pkt_assy_p, uint32_t *pkt_reorder_p)
78544961713Sgirish {
78644961713Sgirish uint64_t value;
78744961713Sgirish
788a3c5bd6dSspeer ASSERT(IS_PORT_NUM_VALID(port));
78944961713Sgirish
79044961713Sgirish TXC_FZC_CNTL_REG_READ64(handle, TXC_PKT_STUFFED_REG, port, &value);
79144961713Sgirish *pkt_assy_p = ((uint32_t)((value & TXC_PKT_STUFF_PKTASY_MASK) >>
79252ccf843Smisaki TXC_PKT_STUFF_PKTASY_SHIFT));
79344961713Sgirish *pkt_reorder_p = ((uint32_t)((value & TXC_PKT_STUFF_REORDER_MASK) >>
79452ccf843Smisaki TXC_PKT_STUFF_REORDER_SHIFT));
79544961713Sgirish
79644961713Sgirish return (NPI_SUCCESS);
79744961713Sgirish }
79844961713Sgirish
79944961713Sgirish /*
80044961713Sgirish * npi_txc_pkt_xmt_to_mac_get():
80144961713Sgirish * This function is called to get total # of packets transmitted
80244961713Sgirish * to the MAC.
80344961713Sgirish *
80444961713Sgirish * Parameters:
80544961713Sgirish * handle - NPI handle
80644961713Sgirish * port - port number (0 - 3)
80744961713Sgirish * mac_bytes_p - bytes transmitted to the MAC.
80844961713Sgirish * mac_pkts_p - packets transmitted to the MAC.
80944961713Sgirish *
81044961713Sgirish * Return:
81144961713Sgirish * NPI_SUCCESS - If get is complete successfully.
81244961713Sgirish *
81344961713Sgirish * Error:
81444961713Sgirish * NPI_FAILURE -
81544961713Sgirish * NPI_TXC_PORT_INVALID
81644961713Sgirish */
81744961713Sgirish npi_status_t
npi_txc_pkt_xmt_to_mac_get(npi_handle_t handle,uint8_t port,uint32_t * mac_bytes_p,uint32_t * mac_pkts_p)81844961713Sgirish npi_txc_pkt_xmt_to_mac_get(npi_handle_t handle, uint8_t port,
81944961713Sgirish uint32_t *mac_bytes_p, uint32_t *mac_pkts_p)
82044961713Sgirish {
82144961713Sgirish uint64_t value;
82244961713Sgirish
823a3c5bd6dSspeer ASSERT(IS_PORT_NUM_VALID(port));
82444961713Sgirish
82544961713Sgirish TXC_FZC_CNTL_REG_READ64(handle, TXC_PKT_XMIT_REG, port, &value);
82644961713Sgirish *mac_pkts_p = ((uint32_t)((value & TXC_PKTS_XMIT_MASK) >>
82752ccf843Smisaki TXC_PKTS_XMIT_SHIFT));
82844961713Sgirish *mac_bytes_p = ((uint32_t)((value & TXC_BYTES_XMIT_MASK) >>
82952ccf843Smisaki TXC_BYTES_XMIT_SHIFT));
83044961713Sgirish
83144961713Sgirish return (NPI_SUCCESS);
83244961713Sgirish }
83344961713Sgirish
83444961713Sgirish /*
83544961713Sgirish * npi_txc_get_ro_states():
83644961713Sgirish * This function is called to get TXC's reorder state-machine states.
83744961713Sgirish *
83844961713Sgirish * Parameters:
83944961713Sgirish * handle - NPI handle
84044961713Sgirish * port - port number
84144961713Sgirish * *states - TXC Re-order states.
84244961713Sgirish *
84344961713Sgirish * Return:
84444961713Sgirish * NPI_SUCCESS - If get is complete successfully.
84544961713Sgirish *
84644961713Sgirish * Error:
84744961713Sgirish * NPI_FAILURE -
84844961713Sgirish * NPI_TXC_PORT_INVALID
84944961713Sgirish */
85044961713Sgirish npi_status_t
npi_txc_ro_states_get(npi_handle_t handle,uint8_t port,txc_ro_states_t * states)85144961713Sgirish npi_txc_ro_states_get(npi_handle_t handle, uint8_t port,
85244961713Sgirish txc_ro_states_t *states)
85344961713Sgirish {
85444961713Sgirish txc_ro_ctl_t ctl;
85544961713Sgirish txc_ro_tids_t tids;
85644961713Sgirish txc_ro_state0_t s0;
85744961713Sgirish txc_ro_state1_t s1;
85844961713Sgirish txc_ro_state2_t s2;
85944961713Sgirish txc_ro_state3_t s3;
86044961713Sgirish txc_roecc_st_t ecc;
86144961713Sgirish txc_ro_data0_t d0;
86244961713Sgirish txc_ro_data1_t d1;
86344961713Sgirish txc_ro_data2_t d2;
86444961713Sgirish txc_ro_data3_t d3;
86544961713Sgirish txc_ro_data4_t d4;
86644961713Sgirish
867a3c5bd6dSspeer ASSERT(IS_PORT_NUM_VALID(port));
86844961713Sgirish
86944961713Sgirish TXC_FZC_CNTL_REG_READ64(handle, TXC_ROECC_ST_REG, port, &ecc.value);
87044961713Sgirish if ((ecc.bits.ldw.correct_error) || (ecc.bits.ldw.uncorrect_error)) {
87144961713Sgirish TXC_FZC_CNTL_REG_READ64(handle, TXC_RO_DATA0_REG, port,
87252ccf843Smisaki &d0.value);
87344961713Sgirish TXC_FZC_CNTL_REG_READ64(handle, TXC_RO_DATA1_REG, port,
87452ccf843Smisaki &d1.value);
87544961713Sgirish TXC_FZC_CNTL_REG_READ64(handle, TXC_RO_DATA2_REG, port,
87652ccf843Smisaki &d2.value);
87744961713Sgirish TXC_FZC_CNTL_REG_READ64(handle, TXC_RO_DATA3_REG, port,
87852ccf843Smisaki &d3.value);
87944961713Sgirish TXC_FZC_CNTL_REG_READ64(handle, TXC_RO_DATA4_REG, port,
88052ccf843Smisaki &d4.value);
88144961713Sgirish states->d0.value = d0.value;
88244961713Sgirish states->d1.value = d1.value;
88344961713Sgirish states->d2.value = d2.value;
88444961713Sgirish states->d3.value = d3.value;
88544961713Sgirish states->d4.value = d4.value;
88644961713Sgirish
88744961713Sgirish ecc.bits.ldw.ecc_address = 0;
88844961713Sgirish ecc.bits.ldw.correct_error = 0;
88944961713Sgirish ecc.bits.ldw.uncorrect_error = 0;
89044961713Sgirish ecc.bits.ldw.clr_st = 1;
89144961713Sgirish TXC_FZC_CNTL_REG_WRITE64(handle, TXC_ROECC_ST_REG, port,
89252ccf843Smisaki ecc.value);
89344961713Sgirish }
89444961713Sgirish
89544961713Sgirish TXC_FZC_CNTL_REG_READ64(handle, TXC_RO_CTL_REG, port, &ctl.value);
89644961713Sgirish TXC_FZC_CNTL_REG_READ64(handle, TXC_RO_STATE0_REG, port, &s0.value);
89744961713Sgirish TXC_FZC_CNTL_REG_READ64(handle, TXC_RO_STATE1_REG, port, &s1.value);
89844961713Sgirish TXC_FZC_CNTL_REG_READ64(handle, TXC_RO_STATE2_REG, port, &s2.value);
89944961713Sgirish TXC_FZC_CNTL_REG_READ64(handle, TXC_RO_STATE3_REG, port, &s3.value);
90044961713Sgirish TXC_FZC_CNTL_REG_READ64(handle, TXC_RO_TIDS_REG, port, &tids.value);
90144961713Sgirish
90244961713Sgirish states->roecc.value = ctl.value;
90344961713Sgirish states->st0.value = s0.value;
90444961713Sgirish states->st1.value = s1.value;
90544961713Sgirish states->st2.value = s2.value;
90644961713Sgirish states->st3.value = s3.value;
90744961713Sgirish states->ctl.value = ctl.value;
90844961713Sgirish states->tids.value = tids.value;
90944961713Sgirish
91044961713Sgirish ctl.bits.ldw.clr_fail_state = 1;
91144961713Sgirish TXC_FZC_CNTL_REG_WRITE64(handle, TXC_RO_CTL_REG, port, ctl.value);
91244961713Sgirish
91344961713Sgirish return (NPI_SUCCESS);
91444961713Sgirish }
91544961713Sgirish
91644961713Sgirish npi_status_t
npi_txc_ro_ecc_state_clr(npi_handle_t handle,uint8_t port)91744961713Sgirish npi_txc_ro_ecc_state_clr(npi_handle_t handle, uint8_t port)
91844961713Sgirish {
919a3c5bd6dSspeer ASSERT(IS_PORT_NUM_VALID(port));
92044961713Sgirish
92144961713Sgirish TXC_FZC_CNTL_REG_WRITE64(handle, TXC_ROECC_ST_REG, port, 0);
92244961713Sgirish
92344961713Sgirish return (NPI_SUCCESS);
92444961713Sgirish }
92544961713Sgirish
92644961713Sgirish /*
92744961713Sgirish * npi_txc_sf_states_get():
92844961713Sgirish * This function is called to get TXC's store-forward state-machine states.
92944961713Sgirish *
93044961713Sgirish * Parameters:
93144961713Sgirish * handle - NPI handle
93244961713Sgirish * port - port number
93344961713Sgirish * states - TXC Store-forward states
93444961713Sgirish *
93544961713Sgirish * Return:
93644961713Sgirish * NPI_SUCCESS - If get is complete successfully.
93744961713Sgirish *
93844961713Sgirish * Error:
93944961713Sgirish * NPI_FAILURE -
94044961713Sgirish * NPI_TXC_PORT_INVALID
94144961713Sgirish */
94244961713Sgirish npi_status_t
npi_txc_sf_states_get(npi_handle_t handle,uint8_t port,txc_sf_states_t * states)94344961713Sgirish npi_txc_sf_states_get(npi_handle_t handle, uint8_t port,
944*e3d11eeeSToomas Soome txc_sf_states_t *states)
94544961713Sgirish {
94644961713Sgirish txc_sfecc_st_t ecc;
94744961713Sgirish txc_sf_data0_t d0;
94844961713Sgirish txc_sf_data1_t d1;
94944961713Sgirish txc_sf_data2_t d2;
95044961713Sgirish txc_sf_data3_t d3;
95144961713Sgirish txc_sf_data4_t d4;
95244961713Sgirish
953*e3d11eeeSToomas Soome d0.value = 0;
954*e3d11eeeSToomas Soome d1.value = 0;
955*e3d11eeeSToomas Soome d2.value = 0;
956*e3d11eeeSToomas Soome d3.value = 0;
957*e3d11eeeSToomas Soome d4.value = 0;
958*e3d11eeeSToomas Soome
959a3c5bd6dSspeer ASSERT(IS_PORT_NUM_VALID(port));
96044961713Sgirish
96144961713Sgirish TXC_FZC_CNTL_REG_READ64(handle, TXC_SFECC_ST_REG, port, &ecc.value);
96244961713Sgirish if ((ecc.bits.ldw.correct_error) || (ecc.bits.ldw.uncorrect_error)) {
96344961713Sgirish TXC_FZC_CNTL_REG_READ64(handle, TXC_SF_DATA0_REG, port,
96452ccf843Smisaki &d0.value);
96544961713Sgirish TXC_FZC_CNTL_REG_READ64(handle, TXC_SF_DATA1_REG, port,
96652ccf843Smisaki &d1.value);
96744961713Sgirish TXC_FZC_CNTL_REG_READ64(handle, TXC_SF_DATA2_REG, port,
96852ccf843Smisaki &d2.value);
96944961713Sgirish TXC_FZC_CNTL_REG_READ64(handle, TXC_SF_DATA3_REG, port,
97052ccf843Smisaki &d3.value);
97144961713Sgirish TXC_FZC_CNTL_REG_READ64(handle, TXC_SF_DATA4_REG, port,
97252ccf843Smisaki &d4.value);
97344961713Sgirish ecc.bits.ldw.ecc_address = 0;
97444961713Sgirish ecc.bits.ldw.correct_error = 0;
97544961713Sgirish ecc.bits.ldw.uncorrect_error = 0;
97644961713Sgirish ecc.bits.ldw.clr_st = 1;
97744961713Sgirish TXC_FZC_CNTL_REG_WRITE64(handle, TXC_SFECC_ST_REG, port,
97852ccf843Smisaki ecc.value);
97944961713Sgirish }
98044961713Sgirish
98144961713Sgirish states->sfecc.value = ecc.value;
98244961713Sgirish states->d0.value = d0.value;
98344961713Sgirish states->d1.value = d1.value;
98444961713Sgirish states->d2.value = d2.value;
98544961713Sgirish states->d3.value = d3.value;
98644961713Sgirish states->d4.value = d4.value;
98744961713Sgirish
98844961713Sgirish return (NPI_SUCCESS);
98944961713Sgirish }
99044961713Sgirish
99144961713Sgirish npi_status_t
npi_txc_sf_ecc_state_clr(npi_handle_t handle,uint8_t port)99244961713Sgirish npi_txc_sf_ecc_state_clr(npi_handle_t handle, uint8_t port)
99344961713Sgirish {
994a3c5bd6dSspeer ASSERT(IS_PORT_NUM_VALID(port));
99544961713Sgirish
99644961713Sgirish TXC_FZC_CNTL_REG_WRITE64(handle, TXC_SFECC_ST_REG, port, 0);
99744961713Sgirish
99844961713Sgirish return (NPI_SUCCESS);
99944961713Sgirish }
100044961713Sgirish
100144961713Sgirish /*
100244961713Sgirish * npi_txc_global_istatus_get():
100344961713Sgirish * This function is called to get TXC's global interrupt status.
100444961713Sgirish *
100544961713Sgirish * Parameters:
100644961713Sgirish * handle - NPI handle
100744961713Sgirish * istatus - TXC global interrupt status
100844961713Sgirish *
100944961713Sgirish * Return:
101044961713Sgirish */
101144961713Sgirish void
npi_txc_global_istatus_get(npi_handle_t handle,txc_int_stat_t * istatus)101244961713Sgirish npi_txc_global_istatus_get(npi_handle_t handle, txc_int_stat_t *istatus)
101344961713Sgirish {
101444961713Sgirish txc_int_stat_t status;
101544961713Sgirish
101644961713Sgirish NXGE_REG_RD64(handle, TXC_INT_STAT_REG, &status.value);
101744961713Sgirish
101844961713Sgirish istatus->value = status.value;
101944961713Sgirish }
102044961713Sgirish
102144961713Sgirish /*
102244961713Sgirish * npi_txc_global_istatus_clear():
102344961713Sgirish * This function is called to clear TXC's global interrupt status.
102444961713Sgirish *
102544961713Sgirish * Parameters:
102644961713Sgirish * handle - NPI handle
102744961713Sgirish * istatus - TXC global interrupt status
102844961713Sgirish *
102944961713Sgirish * Return:
103044961713Sgirish */
103144961713Sgirish void
npi_txc_global_istatus_clear(npi_handle_t handle,uint64_t istatus)103244961713Sgirish npi_txc_global_istatus_clear(npi_handle_t handle, uint64_t istatus)
103344961713Sgirish {
103444961713Sgirish NXGE_REG_WR64(handle, TXC_INT_STAT_REG, istatus);
103544961713Sgirish }
103644961713Sgirish
103744961713Sgirish void
npi_txc_global_imask_set(npi_handle_t handle,uint8_t portn,uint8_t istatus)103844961713Sgirish npi_txc_global_imask_set(npi_handle_t handle, uint8_t portn, uint8_t istatus)
103944961713Sgirish {
104044961713Sgirish uint64_t val;
104144961713Sgirish
104244961713Sgirish NXGE_REG_RD64(handle, TXC_INT_MASK_REG, &val);
104344961713Sgirish switch (portn) {
104444961713Sgirish case 0:
104544961713Sgirish val &= 0xFFFFFF00;
104644961713Sgirish val |= istatus & 0x3F;
104744961713Sgirish break;
104844961713Sgirish case 1:
104944961713Sgirish val &= 0xFFFF00FF;
105044961713Sgirish val |= (istatus << 8) & 0x3F00;
105144961713Sgirish break;
105244961713Sgirish case 2:
105344961713Sgirish val &= 0xFF00FFFF;
105444961713Sgirish val |= (istatus << 16) & 0x3F0000;
105544961713Sgirish break;
105644961713Sgirish case 3:
105744961713Sgirish val &= 0x00FFFFFF;
105844961713Sgirish val |= (istatus << 24) & 0x3F000000;
105944961713Sgirish break;
106044961713Sgirish default:
106144961713Sgirish ;
106244961713Sgirish }
106344961713Sgirish NXGE_REG_WR64(handle, TXC_INT_MASK_REG, val);
106444961713Sgirish }
1065