1*678453a8Sspeer /*
2*678453a8Sspeer * CDDL HEADER START
3*678453a8Sspeer *
4*678453a8Sspeer * The contents of this file are subject to the terms of the
5*678453a8Sspeer * Common Development and Distribution License (the "License").
6*678453a8Sspeer * You may not use this file except in compliance with the License.
7*678453a8Sspeer *
8*678453a8Sspeer * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9*678453a8Sspeer * or http://www.opensolaris.org/os/licensing.
10*678453a8Sspeer * See the License for the specific language governing permissions
11*678453a8Sspeer * and limitations under the License.
12*678453a8Sspeer *
13*678453a8Sspeer * When distributing Covered Code, include this CDDL HEADER in each
14*678453a8Sspeer * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15*678453a8Sspeer * If applicable, add the following below this CDDL HEADER, with the
16*678453a8Sspeer * fields enclosed by brackets "[]" replaced with your own identifying
17*678453a8Sspeer * information: Portions Copyright [yyyy] [name of copyright owner]
18*678453a8Sspeer *
19*678453a8Sspeer * CDDL HEADER END
20*678453a8Sspeer */
21*678453a8Sspeer /*
22*678453a8Sspeer * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
23*678453a8Sspeer * Use is subject to license terms.
24*678453a8Sspeer */
25*678453a8Sspeer
26*678453a8Sspeer #ifndef _NPI_TX_RD64_H
27*678453a8Sspeer #define _NPI_TX_RD64_H
28*678453a8Sspeer
29*678453a8Sspeer #ifdef __cplusplus
30*678453a8Sspeer extern "C" {
31*678453a8Sspeer #endif
32*678453a8Sspeer
33*678453a8Sspeer #include <npi.h>
34*678453a8Sspeer
35*678453a8Sspeer static void TXDMA_REG_READ64(npi_handle_t, uint64_t, int, uint64_t *);
36*678453a8Sspeer #pragma inline(TXDMA_REG_READ64)
37*678453a8Sspeer
38*678453a8Sspeer /*
39*678453a8Sspeer * TXDMA_REG_READ64
40*678453a8Sspeer *
41*678453a8Sspeer * Read a 64-bit value from a DMC register.
42*678453a8Sspeer *
43*678453a8Sspeer * Arguments:
44*678453a8Sspeer * handle The NPI handle to use.
45*678453a8Sspeer * offset The offset into the DMA CSR (the register).
46*678453a8Sspeer * channel The channel, which is used as a multiplicand.
47*678453a8Sspeer * value Where to put the 64-bit value to be read.
48*678453a8Sspeer *
49*678453a8Sspeer * Notes:
50*678453a8Sspeer * For reference, here is the old macro:
51*678453a8Sspeer *
52*678453a8Sspeer * #define TXDMA_REG_READ64(handle, reg, channel, val_p) \
53*678453a8Sspeer * NXGE_REG_RD64(handle, \
54*678453a8Sspeer * (NXGE_TXDMA_OFFSET(reg, handle.is_vraddr, channel)), val_p)
55*678453a8Sspeer *
56*678453a8Sspeer * If handle.regp is a virtual address (the address of a VR),
57*678453a8Sspeer * we have to subtract the value DMC right off the bat. DMC
58*678453a8Sspeer * is defined as 0x600000, which works in a non-virtual address
59*678453a8Sspeer * space, but not in a VR. In a VR, a DMA CSR's space begins
60*678453a8Sspeer * at zero (0). So, since every call to RXMDA_REG_READ64 uses
61*678453a8Sspeer * a register macro which adds in DMC, we have to subtract it.
62*678453a8Sspeer *
63*678453a8Sspeer * The rest of it is pretty straighforward. In a VR, a channel is
64*678453a8Sspeer * logical, not absolute; and every DMA CSR is 512 bytes big;
65*678453a8Sspeer * furthermore, a subpage of a VR is always ordered with the
66*678453a8Sspeer * transmit CSRs first, followed by the receive CSRs. That is,
67*678453a8Sspeer * a 512 byte space of Tx CSRs, followed by a 512 byte space of
68*678453a8Sspeer * Rx CSRs. Hence this calculation:
69*678453a8Sspeer *
70*678453a8Sspeer * offset += ((channel << 1) << DMA_CSR_SLL);
71*678453a8Sspeer *
72*678453a8Sspeer * Here's an example:
73*678453a8Sspeer *
74*678453a8Sspeer * TXDMA_REG_READ64(handle, TX_CS_REG, channel, &value);
75*678453a8Sspeer * Let's say channel is 3
76*678453a8Sspeer * #define TX_CS_REG (DMC + 0x40028)
77*678453a8Sspeer * offset = 0x640028
78*678453a8Sspeer * offset &= 0xff = 0x28
79*678453a8Sspeer * offset += ((3 << 1) << 9)
80*678453a8Sspeer * 3 << 1 = 6
81*678453a8Sspeer * 6 << 9 = 0xc00
82*678453a8Sspeer * offset += 0xc00 = 0xc28
83*678453a8Sspeer *
84*678453a8Sspeer * Therefore, our register's (virtual) PIO address is 0xc28.
85*678453a8Sspeer *
86*678453a8Sspeer * cf. Table 10-6 on page 181 of the Neptune PRM, v 1.4:
87*678453a8Sspeer *
88*678453a8Sspeer * C00 - dFF CSRs for bound logical transmit DMA channel 3.
89*678453a8Sspeer *
90*678453a8Sspeer * In a non-virtual environment, you simply multiply the absolute
91*678453a8Sspeer * channel number by 512 bytes, and get the correct offset to
92*678453a8Sspeer * the register you're looking for. That is, the RX_DMA_CTL_STAT CSR,
93*678453a8Sspeer * is, as are all of these registers, in a table where each channel
94*678453a8Sspeer * is offset 512 bytes from the previous channel (count 16 step 512).
95*678453a8Sspeer *
96*678453a8Sspeer * offset += (channel << DMA_CSR_SLL); // channel<<9 = channel*512
97*678453a8Sspeer *
98*678453a8Sspeer * Here's an example:
99*678453a8Sspeer *
100*678453a8Sspeer * TXDMA_REG_READ64(handle, TX_CS_REG, channel, &value);
101*678453a8Sspeer * Let's say channel is 3
102*678453a8Sspeer * #define TX_CS_REG (DMC + 0x40028)
103*678453a8Sspeer * offset = 0x640028
104*678453a8Sspeer * offset += (3 << 9)
105*678453a8Sspeer * 3 << 9 = 0x600
106*678453a8Sspeer * offset += 0x600 = 0x640628
107*678453a8Sspeer *
108*678453a8Sspeer * Therefore, our register's PIO address is 0x640628.
109*678453a8Sspeer *
110*678453a8Sspeer * cf. Table 13-15 on page 265 of the Neptune PRM, v 1.4:
111*678453a8Sspeer * TX_CS (DMC + 4002816) (count 24 step 0x200)
112*678453a8Sspeer *
113*678453a8Sspeer * Context:
114*678453a8Sspeer * Any domain
115*678453a8Sspeer *
116*678453a8Sspeer */
117*678453a8Sspeer extern const char *nxge_tx2str(int);
118*678453a8Sspeer
119*678453a8Sspeer void
TXDMA_REG_READ64(npi_handle_t handle,uint64_t offset,int channel,uint64_t * value)120*678453a8Sspeer TXDMA_REG_READ64(
121*678453a8Sspeer npi_handle_t handle,
122*678453a8Sspeer uint64_t offset,
123*678453a8Sspeer int channel,
124*678453a8Sspeer uint64_t *value)
125*678453a8Sspeer {
126*678453a8Sspeer #if defined(NPI_REG_TRACE)
127*678453a8Sspeer const char *name = nxge_tx2str((int)offset);
128*678453a8Sspeer #endif
129*678453a8Sspeer if (handle.is_vraddr) {
130*678453a8Sspeer offset &= DMA_CSR_MASK;
131*678453a8Sspeer offset += ((channel << 1) << DMA_CSR_SLL);
132*678453a8Sspeer } else {
133*678453a8Sspeer offset += (channel << DMA_CSR_SLL);
134*678453a8Sspeer }
135*678453a8Sspeer
136*678453a8Sspeer #if defined(__i386)
137*678453a8Sspeer *value = ddi_get64(handle.regh,
138*678453a8Sspeer (uint64_t *)(handle.regp + (uint32_t)offset));
139*678453a8Sspeer #else
140*678453a8Sspeer *value = ddi_get64(handle.regh, (uint64_t *)(handle.regp + offset));
141*678453a8Sspeer #endif
142*678453a8Sspeer
143*678453a8Sspeer #if defined(NPI_REG_TRACE)
144*678453a8Sspeer npi_trace_update(handle, B_FALSE, &npi_rtracebuf,
145*678453a8Sspeer name, (uint32_t)offset, *value);
146*678453a8Sspeer #elif defined(REG_SHOW)
147*678453a8Sspeer /*
148*678453a8Sspeer * Since we don't have a valid RTBUF index to show, send 0xBADBAD.
149*678453a8Sspeer */
150*678453a8Sspeer rt_show_reg(0xbadbad, B_FALSE, (uint32_t)offset, *value);
151*678453a8Sspeer #endif
152*678453a8Sspeer }
153*678453a8Sspeer
154*678453a8Sspeer #ifdef __cplusplus
155*678453a8Sspeer }
156*678453a8Sspeer #endif
157*678453a8Sspeer
158*678453a8Sspeer #endif /* _NPI_TX_RD64_H */
159