144961713Sgirish /* 244961713Sgirish * CDDL HEADER START 344961713Sgirish * 444961713Sgirish * The contents of this file are subject to the terms of the 544961713Sgirish * Common Development and Distribution License (the "License"). 644961713Sgirish * You may not use this file except in compliance with the License. 744961713Sgirish * 844961713Sgirish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 944961713Sgirish * or http://www.opensolaris.org/os/licensing. 1044961713Sgirish * See the License for the specific language governing permissions 1144961713Sgirish * and limitations under the License. 1244961713Sgirish * 1344961713Sgirish * When distributing Covered Code, include this CDDL HEADER in each 1444961713Sgirish * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1544961713Sgirish * If applicable, add the following below this CDDL HEADER, with the 1644961713Sgirish * fields enclosed by brackets "[]" replaced with your own identifying 1744961713Sgirish * information: Portions Copyright [yyyy] [name of copyright owner] 1844961713Sgirish * 1944961713Sgirish * CDDL HEADER END 2044961713Sgirish */ 2144961713Sgirish /* 22a3c5bd6dSspeer * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 2344961713Sgirish * Use is subject to license terms. 2444961713Sgirish */ 2544961713Sgirish 2644961713Sgirish #pragma ident "%Z%%M% %I% %E% SMI" 2744961713Sgirish 2844961713Sgirish #include <npi_ipp.h> 2944961713Sgirish 3044961713Sgirish uint64_t ipp_fzc_offset[] = { 3144961713Sgirish IPP_CONFIG_REG, 3244961713Sgirish IPP_DISCARD_PKT_CNT_REG, 33*f6485eecSyc IPP_BAD_CKSUM_ERR_CNT_REG, 3444961713Sgirish IPP_ECC_ERR_COUNTER_REG, 3544961713Sgirish IPP_INT_STATUS_REG, 3644961713Sgirish IPP_INT_MASK_REG, 3744961713Sgirish IPP_PFIFO_RD_DATA0_REG, 3844961713Sgirish IPP_PFIFO_RD_DATA1_REG, 3944961713Sgirish IPP_PFIFO_RD_DATA2_REG, 4044961713Sgirish IPP_PFIFO_RD_DATA3_REG, 4144961713Sgirish IPP_PFIFO_RD_DATA4_REG, 4244961713Sgirish IPP_PFIFO_WR_DATA0_REG, 4344961713Sgirish IPP_PFIFO_WR_DATA1_REG, 4444961713Sgirish IPP_PFIFO_WR_DATA2_REG, 4544961713Sgirish IPP_PFIFO_WR_DATA3_REG, 4644961713Sgirish IPP_PFIFO_WR_DATA4_REG, 4744961713Sgirish IPP_PFIFO_RD_PTR_REG, 4844961713Sgirish IPP_PFIFO_WR_PTR_REG, 4944961713Sgirish IPP_DFIFO_RD_DATA0_REG, 5044961713Sgirish IPP_DFIFO_RD_DATA1_REG, 5144961713Sgirish IPP_DFIFO_RD_DATA2_REG, 5244961713Sgirish IPP_DFIFO_RD_DATA3_REG, 5344961713Sgirish IPP_DFIFO_RD_DATA4_REG, 5444961713Sgirish IPP_DFIFO_WR_DATA0_REG, 5544961713Sgirish IPP_DFIFO_WR_DATA1_REG, 5644961713Sgirish IPP_DFIFO_WR_DATA2_REG, 5744961713Sgirish IPP_DFIFO_WR_DATA3_REG, 5844961713Sgirish IPP_DFIFO_WR_DATA4_REG, 5944961713Sgirish IPP_DFIFO_RD_PTR_REG, 6044961713Sgirish IPP_DFIFO_WR_PTR_REG, 6144961713Sgirish IPP_STATE_MACHINE_REG, 6244961713Sgirish IPP_CKSUM_STATUS_REG, 6344961713Sgirish IPP_FFLP_CKSUM_INFO_REG, 6444961713Sgirish IPP_DEBUG_SELECT_REG, 6544961713Sgirish IPP_DFIFO_ECC_SYNDROME_REG, 6644961713Sgirish IPP_DFIFO_EOPM_RD_PTR_REG, 6744961713Sgirish IPP_ECC_CTRL_REG 6844961713Sgirish }; 6944961713Sgirish 7044961713Sgirish const char *ipp_fzc_name[] = { 7144961713Sgirish "IPP_CONFIG_REG", 7244961713Sgirish "IPP_DISCARD_PKT_CNT_REG", 73*f6485eecSyc "IPP_BAD_CKSUM_ERR_CNT_REG", 7444961713Sgirish "IPP_ECC_ERR_COUNTER_REG", 7544961713Sgirish "IPP_INT_STATUS_REG", 7644961713Sgirish "IPP_INT_MASK_REG", 7744961713Sgirish "IPP_PFIFO_RD_DATA0_REG", 7844961713Sgirish "IPP_PFIFO_RD_DATA1_REG", 7944961713Sgirish "IPP_PFIFO_RD_DATA2_REG", 8044961713Sgirish "IPP_PFIFO_RD_DATA3_REG", 8144961713Sgirish "IPP_PFIFO_RD_DATA4_REG", 8244961713Sgirish "IPP_PFIFO_WR_DATA0_REG", 8344961713Sgirish "IPP_PFIFO_WR_DATA1_REG", 8444961713Sgirish "IPP_PFIFO_WR_DATA2_REG", 8544961713Sgirish "IPP_PFIFO_WR_DATA3_REG", 8644961713Sgirish "IPP_PFIFO_WR_DATA4_REG", 8744961713Sgirish "IPP_PFIFO_RD_PTR_REG", 8844961713Sgirish "IPP_PFIFO_WR_PTR_REG", 8944961713Sgirish "IPP_DFIFO_RD_DATA0_REG", 9044961713Sgirish "IPP_DFIFO_RD_DATA1_REG", 9144961713Sgirish "IPP_DFIFO_RD_DATA2_REG", 9244961713Sgirish "IPP_DFIFO_RD_DATA3_REG", 9344961713Sgirish "IPP_DFIFO_RD_DATA4_REG", 9444961713Sgirish "IPP_DFIFO_WR_DATA0_REG", 9544961713Sgirish "IPP_DFIFO_WR_DATA1_REG", 9644961713Sgirish "IPP_DFIFO_WR_DATA2_REG", 9744961713Sgirish "IPP_DFIFO_WR_DATA3_REG", 9844961713Sgirish "IPP_DFIFO_WR_DATA4_REG", 9944961713Sgirish "IPP_DFIFO_RD_PTR_REG", 10044961713Sgirish "IPP_DFIFO_WR_PTR_REG", 10144961713Sgirish "IPP_STATE_MACHINE_REG", 10244961713Sgirish "IPP_CKSUM_STATUS_REG", 10344961713Sgirish "IPP_FFLP_CKSUM_INFO_REG", 10444961713Sgirish "IPP_DEBUG_SELECT_REG", 10544961713Sgirish "IPP_DFIFO_ECC_SYNDROME_REG", 10644961713Sgirish "IPP_DFIFO_EOPM_RD_PTR_REG", 10744961713Sgirish "IPP_ECC_CTRL_REG", 10844961713Sgirish }; 10944961713Sgirish 11044961713Sgirish npi_status_t 11144961713Sgirish npi_ipp_dump_regs(npi_handle_t handle, uint8_t port) 11244961713Sgirish { 11344961713Sgirish uint64_t value, offset; 11444961713Sgirish int num_regs, i; 11544961713Sgirish 116a3c5bd6dSspeer ASSERT(IS_PORT_NUM_VALID(port)); 11744961713Sgirish 11844961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 11944961713Sgirish "\nIPP PORT Register Dump for port %d\n", port)); 12044961713Sgirish 12144961713Sgirish num_regs = sizeof (ipp_fzc_offset) / sizeof (uint64_t); 12244961713Sgirish for (i = 0; i < num_regs; i++) { 12344961713Sgirish offset = IPP_REG_ADDR(port, ipp_fzc_offset[i]); 124adfcba55Sjoycey #if defined(__i386) 125adfcba55Sjoycey NXGE_REG_RD64(handle, (uint32_t)offset, &value); 126adfcba55Sjoycey #else 12744961713Sgirish NXGE_REG_RD64(handle, offset, &value); 128adfcba55Sjoycey #endif 12944961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, "0x%08llx " 13044961713Sgirish "%s\t 0x%08llx \n", 13144961713Sgirish offset, ipp_fzc_name[i], value)); 13244961713Sgirish } 13344961713Sgirish 13444961713Sgirish NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 13544961713Sgirish "\n IPP FZC Register Dump for port %d done\n", port)); 13644961713Sgirish 13744961713Sgirish return (NPI_SUCCESS); 13844961713Sgirish } 13944961713Sgirish 14044961713Sgirish void 14144961713Sgirish npi_ipp_read_regs(npi_handle_t handle, uint8_t port) 14244961713Sgirish { 14344961713Sgirish uint64_t value, offset; 14444961713Sgirish int num_regs, i; 14544961713Sgirish 146a3c5bd6dSspeer ASSERT(IS_PORT_NUM_VALID(port)); 14744961713Sgirish 14844961713Sgirish NPI_DEBUG_MSG((handle.function, NPI_IPP_CTL, 14944961713Sgirish "\nIPP PORT Register read (to clear) for port %d\n", port)); 15044961713Sgirish 15144961713Sgirish num_regs = sizeof (ipp_fzc_offset) / sizeof (uint64_t); 15244961713Sgirish for (i = 0; i < num_regs; i++) { 15344961713Sgirish offset = IPP_REG_ADDR(port, ipp_fzc_offset[i]); 154adfcba55Sjoycey #if defined(__i386) 155adfcba55Sjoycey NXGE_REG_RD64(handle, (uint32_t)offset, &value); 156adfcba55Sjoycey #else 15744961713Sgirish NXGE_REG_RD64(handle, offset, &value); 158adfcba55Sjoycey #endif 15944961713Sgirish } 16044961713Sgirish 16144961713Sgirish } 16244961713Sgirish 163a3c5bd6dSspeer /* 164a3c5bd6dSspeer * IPP Reset Routine 165a3c5bd6dSspeer */ 16644961713Sgirish npi_status_t 16744961713Sgirish npi_ipp_reset(npi_handle_t handle, uint8_t portn) 16844961713Sgirish { 16944961713Sgirish uint64_t val = 0; 17044961713Sgirish uint32_t cnt = MAX_PIO_RETRIES; 17144961713Sgirish 172a3c5bd6dSspeer ASSERT(IS_PORT_NUM_VALID(portn)); 17344961713Sgirish 17444961713Sgirish IPP_REG_RD(handle, portn, IPP_CONFIG_REG, &val); 17544961713Sgirish val |= IPP_SOFT_RESET; 17644961713Sgirish IPP_REG_WR(handle, portn, IPP_CONFIG_REG, val); 17744961713Sgirish 17844961713Sgirish do { 17944961713Sgirish NXGE_DELAY(IPP_RESET_WAIT); 18044961713Sgirish IPP_REG_RD(handle, portn, IPP_CONFIG_REG, &val); 18144961713Sgirish cnt--; 18244961713Sgirish } while (((val & IPP_SOFT_RESET) != 0) && (cnt > 0)); 18344961713Sgirish 18444961713Sgirish if (cnt == 0) { 18544961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 18644961713Sgirish " npi_ipp_reset" 18744961713Sgirish " HW Error: IPP_RESET <0x%x>", val)); 18844961713Sgirish return (NPI_FAILURE | NPI_IPP_RESET_FAILED(portn)); 18944961713Sgirish } 19044961713Sgirish 19144961713Sgirish return (NPI_SUCCESS); 19244961713Sgirish } 19344961713Sgirish 19444961713Sgirish 195a3c5bd6dSspeer /* 196a3c5bd6dSspeer * IPP Configuration Routine 197a3c5bd6dSspeer */ 19844961713Sgirish npi_status_t 19944961713Sgirish npi_ipp_config(npi_handle_t handle, config_op_t op, uint8_t portn, 20044961713Sgirish ipp_config_t config) 20144961713Sgirish { 20244961713Sgirish uint64_t val = 0; 20344961713Sgirish 204a3c5bd6dSspeer ASSERT(IS_PORT_NUM_VALID(portn)); 20544961713Sgirish 20644961713Sgirish switch (op) { 20744961713Sgirish 20844961713Sgirish case ENABLE: 20944961713Sgirish case DISABLE: 21044961713Sgirish if ((config == 0) || ((config & ~CFG_IPP_ALL) != 0)) { 21144961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 21244961713Sgirish " npi_ipp_config", 21344961713Sgirish " Invalid Input config <0x%x>", 21444961713Sgirish config)); 21544961713Sgirish return (NPI_FAILURE | NPI_IPP_CONFIG_INVALID(portn)); 21644961713Sgirish } 21744961713Sgirish 21844961713Sgirish IPP_REG_RD(handle, portn, IPP_CONFIG_REG, &val); 21944961713Sgirish 22044961713Sgirish if (op == ENABLE) 22144961713Sgirish val |= config; 22244961713Sgirish else 22344961713Sgirish val &= ~config; 22444961713Sgirish break; 22544961713Sgirish 22644961713Sgirish case INIT: 22744961713Sgirish if ((config & ~CFG_IPP_ALL) != 0) { 22844961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 22944961713Sgirish " npi_ipp_config" 23044961713Sgirish " Invalid Input config <0x%x>", 23144961713Sgirish config)); 23244961713Sgirish return (NPI_FAILURE | NPI_IPP_CONFIG_INVALID(portn)); 23344961713Sgirish } 23444961713Sgirish IPP_REG_RD(handle, portn, IPP_CONFIG_REG, &val); 23544961713Sgirish 23644961713Sgirish 23744961713Sgirish val &= (IPP_IP_MAX_PKT_BYTES_MASK); 23844961713Sgirish val |= config; 23944961713Sgirish break; 24044961713Sgirish 24144961713Sgirish default: 24244961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 24344961713Sgirish " npi_ipp_config" 24444961713Sgirish " Invalid Input op <0x%x>", op)); 24544961713Sgirish return (NPI_FAILURE | NPI_IPP_OPCODE_INVALID(portn)); 24644961713Sgirish } 24744961713Sgirish 24844961713Sgirish IPP_REG_WR(handle, portn, IPP_CONFIG_REG, val); 24944961713Sgirish return (NPI_SUCCESS); 25044961713Sgirish } 25144961713Sgirish 25244961713Sgirish npi_status_t 25344961713Sgirish npi_ipp_set_max_pktsize(npi_handle_t handle, uint8_t portn, uint32_t bytes) 25444961713Sgirish { 25544961713Sgirish uint64_t val = 0; 25644961713Sgirish 257a3c5bd6dSspeer ASSERT(IS_PORT_NUM_VALID(portn)); 25844961713Sgirish 25944961713Sgirish if (bytes > IPP_IP_MAX_PKT_BYTES_MASK) { 26044961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 26144961713Sgirish " npi_ipp_set_max_pktsize" 26244961713Sgirish " Invalid Input Max bytes <0x%x>", 26344961713Sgirish bytes)); 26444961713Sgirish return (NPI_FAILURE | NPI_IPP_MAX_PKT_BYTES_INVALID(portn)); 26544961713Sgirish } 26644961713Sgirish 26744961713Sgirish IPP_REG_RD(handle, portn, IPP_CONFIG_REG, &val); 26844961713Sgirish val &= ~(IPP_IP_MAX_PKT_BYTES_MASK << IPP_IP_MAX_PKT_BYTES_SHIFT); 26944961713Sgirish 27044961713Sgirish val |= (bytes << IPP_IP_MAX_PKT_BYTES_SHIFT); 27144961713Sgirish IPP_REG_WR(handle, portn, IPP_CONFIG_REG, val); 27244961713Sgirish 27344961713Sgirish return (NPI_SUCCESS); 27444961713Sgirish } 27544961713Sgirish 276a3c5bd6dSspeer /* 277a3c5bd6dSspeer * IPP Interrupt Configuration Routine 278a3c5bd6dSspeer */ 27944961713Sgirish npi_status_t 28044961713Sgirish npi_ipp_iconfig(npi_handle_t handle, config_op_t op, uint8_t portn, 28144961713Sgirish ipp_iconfig_t iconfig) 28244961713Sgirish { 28344961713Sgirish uint64_t val = 0; 28444961713Sgirish 285a3c5bd6dSspeer ASSERT(IS_PORT_NUM_VALID(portn)); 28644961713Sgirish 28744961713Sgirish switch (op) { 28844961713Sgirish case ENABLE: 28944961713Sgirish case DISABLE: 29044961713Sgirish 29144961713Sgirish if ((iconfig == 0) || ((iconfig & ~ICFG_IPP_ALL) != 0)) { 29244961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 29344961713Sgirish " npi_ipp_iconfig" 29444961713Sgirish " Invalid Input iconfig <0x%x>", 29544961713Sgirish iconfig)); 29644961713Sgirish return (NPI_FAILURE | NPI_IPP_CONFIG_INVALID(portn)); 29744961713Sgirish } 29844961713Sgirish 29944961713Sgirish IPP_REG_RD(handle, portn, IPP_INT_MASK_REG, &val); 30044961713Sgirish if (op == ENABLE) 30144961713Sgirish val &= ~iconfig; 30244961713Sgirish else 30344961713Sgirish val |= iconfig; 30444961713Sgirish IPP_REG_WR(handle, portn, IPP_INT_MASK_REG, val); 30544961713Sgirish 30644961713Sgirish break; 30744961713Sgirish case INIT: 30844961713Sgirish 30944961713Sgirish if ((iconfig & ~ICFG_IPP_ALL) != 0) { 31044961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 31144961713Sgirish " npi_ipp_iconfig" 31244961713Sgirish " Invalid Input iconfig <0x%x>", 31344961713Sgirish iconfig)); 31444961713Sgirish return (NPI_FAILURE | NPI_IPP_CONFIG_INVALID(portn)); 31544961713Sgirish } 31644961713Sgirish IPP_REG_WR(handle, portn, IPP_INT_MASK_REG, ~iconfig); 31744961713Sgirish 31844961713Sgirish break; 31944961713Sgirish default: 32044961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 32144961713Sgirish " npi_ipp_iconfig" 32244961713Sgirish " Invalid Input iconfig <0x%x>", 32344961713Sgirish iconfig)); 32444961713Sgirish return (NPI_FAILURE | NPI_IPP_OPCODE_INVALID(portn)); 32544961713Sgirish } 32644961713Sgirish 32744961713Sgirish return (NPI_SUCCESS); 32844961713Sgirish } 32944961713Sgirish 33044961713Sgirish npi_status_t 33144961713Sgirish npi_ipp_get_status(npi_handle_t handle, uint8_t portn, ipp_status_t *status) 33244961713Sgirish { 33344961713Sgirish uint64_t val; 33444961713Sgirish 335a3c5bd6dSspeer ASSERT(IS_PORT_NUM_VALID(portn)); 33644961713Sgirish 33744961713Sgirish IPP_REG_RD(handle, portn, IPP_INT_STATUS_REG, &val); 33844961713Sgirish 33944961713Sgirish status->value = val; 34044961713Sgirish return (NPI_SUCCESS); 34144961713Sgirish } 34244961713Sgirish 34344961713Sgirish npi_status_t 34444961713Sgirish npi_ipp_get_pfifo_rd_ptr(npi_handle_t handle, uint8_t portn, uint16_t *rd_ptr) 34544961713Sgirish { 34644961713Sgirish uint64_t value; 347a3c5bd6dSspeer 348a3c5bd6dSspeer ASSERT(IS_PORT_NUM_VALID(portn)); 34944961713Sgirish 35044961713Sgirish IPP_REG_RD(handle, portn, IPP_PFIFO_RD_PTR_REG, &value); 35144961713Sgirish *rd_ptr = value & 0xfff; 35244961713Sgirish return (NPI_SUCCESS); 35344961713Sgirish } 35444961713Sgirish 35544961713Sgirish npi_status_t 35644961713Sgirish npi_ipp_get_pfifo_wr_ptr(npi_handle_t handle, uint8_t portn, uint16_t *wr_ptr) 35744961713Sgirish { 35844961713Sgirish uint64_t value; 359a3c5bd6dSspeer 360a3c5bd6dSspeer ASSERT(IS_PORT_NUM_VALID(portn)); 36144961713Sgirish 36244961713Sgirish IPP_REG_RD(handle, portn, IPP_PFIFO_WR_PTR_REG, &value); 36344961713Sgirish *wr_ptr = value & 0xfff; 36444961713Sgirish return (NPI_SUCCESS); 36544961713Sgirish } 36644961713Sgirish 36744961713Sgirish npi_status_t 36844961713Sgirish npi_ipp_get_dfifo_rd_ptr(npi_handle_t handle, uint8_t portn, uint16_t *rd_ptr) 36944961713Sgirish { 37044961713Sgirish uint64_t value; 371a3c5bd6dSspeer 372a3c5bd6dSspeer ASSERT(IS_PORT_NUM_VALID(portn)); 37344961713Sgirish 37444961713Sgirish IPP_REG_RD(handle, portn, IPP_DFIFO_RD_PTR_REG, &value); 37544961713Sgirish *rd_ptr = (uint16_t)(value & ((portn < 2) ? IPP_XMAC_DFIFO_PTR_MASK : 37644961713Sgirish IPP_BMAC_DFIFO_PTR_MASK)); 37744961713Sgirish return (NPI_SUCCESS); 37844961713Sgirish } 37944961713Sgirish 38044961713Sgirish npi_status_t 38144961713Sgirish npi_ipp_get_dfifo_wr_ptr(npi_handle_t handle, uint8_t portn, uint16_t *wr_ptr) 38244961713Sgirish { 38344961713Sgirish uint64_t value; 384a3c5bd6dSspeer 385a3c5bd6dSspeer ASSERT(IS_PORT_NUM_VALID(portn)); 38644961713Sgirish 38744961713Sgirish IPP_REG_RD(handle, portn, IPP_DFIFO_WR_PTR_REG, &value); 38844961713Sgirish *wr_ptr = (uint16_t)(value & ((portn < 2) ? IPP_XMAC_DFIFO_PTR_MASK : 38944961713Sgirish IPP_BMAC_DFIFO_PTR_MASK)); 39044961713Sgirish return (NPI_SUCCESS); 39144961713Sgirish } 39244961713Sgirish 39344961713Sgirish npi_status_t 39444961713Sgirish npi_ipp_write_pfifo(npi_handle_t handle, uint8_t portn, uint8_t addr, 39544961713Sgirish uint32_t d0, uint32_t d1, uint32_t d2, uint32_t d3, uint32_t d4) 39644961713Sgirish { 39744961713Sgirish uint64_t val; 39844961713Sgirish 399a3c5bd6dSspeer ASSERT(IS_PORT_NUM_VALID(portn)); 40044961713Sgirish 40144961713Sgirish if (addr >= 64) { 40244961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 40344961713Sgirish " npi_ipp_write_pfifo" 40444961713Sgirish " Invalid PFIFO address <0x%x>", addr)); 40544961713Sgirish return (NPI_FAILURE | NPI_IPP_FIFO_ADDR_INVALID(portn)); 40644961713Sgirish } 40744961713Sgirish 40844961713Sgirish IPP_REG_RD(handle, portn, IPP_CONFIG_REG, &val); 40944961713Sgirish val |= IPP_PRE_FIFO_PIO_WR_EN; 41044961713Sgirish IPP_REG_WR(handle, portn, IPP_CONFIG_REG, val); 41144961713Sgirish 41244961713Sgirish IPP_REG_WR(handle, portn, IPP_PFIFO_WR_PTR_REG, addr); 41344961713Sgirish IPP_REG_WR(handle, portn, IPP_PFIFO_WR_DATA0_REG, d0); 41444961713Sgirish IPP_REG_WR(handle, portn, IPP_PFIFO_WR_DATA1_REG, d1); 41544961713Sgirish IPP_REG_WR(handle, portn, IPP_PFIFO_WR_DATA2_REG, d2); 41644961713Sgirish IPP_REG_WR(handle, portn, IPP_PFIFO_WR_DATA3_REG, d3); 41744961713Sgirish IPP_REG_WR(handle, portn, IPP_PFIFO_WR_DATA4_REG, d4); 41844961713Sgirish 41944961713Sgirish val &= ~IPP_PRE_FIFO_PIO_WR_EN; 42044961713Sgirish IPP_REG_WR(handle, portn, IPP_CONFIG_REG, val); 42144961713Sgirish 42244961713Sgirish return (NPI_SUCCESS); 42344961713Sgirish } 42444961713Sgirish 42544961713Sgirish npi_status_t 42644961713Sgirish npi_ipp_read_pfifo(npi_handle_t handle, uint8_t portn, uint8_t addr, 42744961713Sgirish uint32_t *d0, uint32_t *d1, uint32_t *d2, uint32_t *d3, 42844961713Sgirish uint32_t *d4) 42944961713Sgirish { 430a3c5bd6dSspeer ASSERT(IS_PORT_NUM_VALID(portn)); 43144961713Sgirish 43244961713Sgirish if (addr >= 64) { 43344961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 43444961713Sgirish " npi_ipp_read_pfifo" 43544961713Sgirish " Invalid PFIFO address <0x%x>", addr)); 43644961713Sgirish return (NPI_FAILURE | NPI_IPP_FIFO_ADDR_INVALID(portn)); 43744961713Sgirish } 43844961713Sgirish 43944961713Sgirish IPP_REG_WR(handle, portn, IPP_PFIFO_RD_PTR_REG, addr); 44044961713Sgirish IPP_REG_RD(handle, portn, IPP_PFIFO_RD_DATA0_REG, d0); 44144961713Sgirish IPP_REG_RD(handle, portn, IPP_PFIFO_RD_DATA1_REG, d1); 44244961713Sgirish IPP_REG_RD(handle, portn, IPP_PFIFO_RD_DATA2_REG, d2); 44344961713Sgirish IPP_REG_RD(handle, portn, IPP_PFIFO_RD_DATA3_REG, d3); 44444961713Sgirish IPP_REG_RD(handle, portn, IPP_PFIFO_RD_DATA4_REG, d4); 44544961713Sgirish 44644961713Sgirish return (NPI_SUCCESS); 44744961713Sgirish } 44844961713Sgirish 44944961713Sgirish npi_status_t 45044961713Sgirish npi_ipp_write_dfifo(npi_handle_t handle, uint8_t portn, uint16_t addr, 45144961713Sgirish uint32_t d0, uint32_t d1, uint32_t d2, uint32_t d3, uint32_t d4) 45244961713Sgirish { 45344961713Sgirish uint64_t val; 45444961713Sgirish 455a3c5bd6dSspeer ASSERT(IS_PORT_NUM_VALID(portn)); 45644961713Sgirish 45744961713Sgirish if (addr >= 2048) { 45844961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 45944961713Sgirish " npi_ipp_write_dfifo" 46044961713Sgirish " Invalid DFIFO address <0x%x>", addr)); 46144961713Sgirish return (NPI_FAILURE | NPI_IPP_FIFO_ADDR_INVALID(portn)); 46244961713Sgirish } 46344961713Sgirish 46444961713Sgirish IPP_REG_RD(handle, portn, IPP_CONFIG_REG, &val); 46544961713Sgirish val |= IPP_DFIFO_PIO_WR_EN; 46644961713Sgirish IPP_REG_WR(handle, portn, IPP_CONFIG_REG, val); 46744961713Sgirish 46844961713Sgirish IPP_REG_WR(handle, portn, IPP_DFIFO_WR_PTR_REG, addr); 46944961713Sgirish IPP_REG_WR(handle, portn, IPP_DFIFO_WR_DATA0_REG, d0); 47044961713Sgirish IPP_REG_WR(handle, portn, IPP_DFIFO_WR_DATA1_REG, d1); 47144961713Sgirish IPP_REG_WR(handle, portn, IPP_DFIFO_WR_DATA2_REG, d2); 47244961713Sgirish IPP_REG_WR(handle, portn, IPP_DFIFO_WR_DATA3_REG, d3); 47344961713Sgirish IPP_REG_WR(handle, portn, IPP_DFIFO_WR_DATA4_REG, d4); 47444961713Sgirish 47544961713Sgirish val &= ~IPP_DFIFO_PIO_WR_EN; 47644961713Sgirish IPP_REG_WR(handle, portn, IPP_CONFIG_REG, val); 47744961713Sgirish 47844961713Sgirish return (NPI_SUCCESS); 47944961713Sgirish } 48044961713Sgirish 48144961713Sgirish npi_status_t 48244961713Sgirish npi_ipp_read_dfifo(npi_handle_t handle, uint8_t portn, uint16_t addr, 48344961713Sgirish uint32_t *d0, uint32_t *d1, uint32_t *d2, uint32_t *d3, 48444961713Sgirish uint32_t *d4) 48544961713Sgirish { 486a3c5bd6dSspeer ASSERT(IS_PORT_NUM_VALID(portn)); 48744961713Sgirish 48844961713Sgirish if (addr >= 2048) { 48944961713Sgirish NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 49044961713Sgirish " npi_ipp_read_dfifo" 49144961713Sgirish " Invalid DFIFO address <0x%x>", addr)); 49244961713Sgirish return (NPI_FAILURE | NPI_IPP_FIFO_ADDR_INVALID(portn)); 49344961713Sgirish } 49444961713Sgirish 49544961713Sgirish IPP_REG_WR(handle, portn, IPP_DFIFO_RD_PTR_REG, addr); 49644961713Sgirish IPP_REG_RD(handle, portn, IPP_DFIFO_RD_DATA0_REG, d0); 49744961713Sgirish IPP_REG_RD(handle, portn, IPP_DFIFO_RD_DATA1_REG, d1); 49844961713Sgirish IPP_REG_RD(handle, portn, IPP_DFIFO_RD_DATA2_REG, d2); 49944961713Sgirish IPP_REG_RD(handle, portn, IPP_DFIFO_RD_DATA3_REG, d3); 50044961713Sgirish IPP_REG_RD(handle, portn, IPP_DFIFO_RD_DATA4_REG, d4); 50144961713Sgirish 50244961713Sgirish return (NPI_SUCCESS); 50344961713Sgirish } 50444961713Sgirish 50544961713Sgirish npi_status_t 50644961713Sgirish npi_ipp_get_ecc_syndrome(npi_handle_t handle, uint8_t portn, uint16_t *syndrome) 50744961713Sgirish { 50844961713Sgirish uint64_t val; 50944961713Sgirish 510a3c5bd6dSspeer ASSERT(IS_PORT_NUM_VALID(portn)); 51144961713Sgirish 51244961713Sgirish IPP_REG_RD(handle, portn, IPP_DFIFO_ECC_SYNDROME_REG, &val); 51344961713Sgirish 51444961713Sgirish *syndrome = (uint16_t)val; 51544961713Sgirish return (NPI_SUCCESS); 51644961713Sgirish } 51744961713Sgirish 51844961713Sgirish npi_status_t 51944961713Sgirish npi_ipp_get_dfifo_eopm_rdptr(npi_handle_t handle, uint8_t portn, 52044961713Sgirish uint16_t *rdptr) 52144961713Sgirish { 52244961713Sgirish uint64_t val; 52344961713Sgirish 524a3c5bd6dSspeer ASSERT(IS_PORT_NUM_VALID(portn)); 52544961713Sgirish 52644961713Sgirish IPP_REG_RD(handle, portn, IPP_DFIFO_EOPM_RD_PTR_REG, &val); 52744961713Sgirish 52844961713Sgirish *rdptr = (uint16_t)val; 52944961713Sgirish return (NPI_SUCCESS); 53044961713Sgirish } 53144961713Sgirish 53244961713Sgirish npi_status_t 53344961713Sgirish npi_ipp_get_state_mach(npi_handle_t handle, uint8_t portn, uint32_t *sm) 53444961713Sgirish { 53544961713Sgirish uint64_t val; 53644961713Sgirish 537a3c5bd6dSspeer ASSERT(IS_PORT_NUM_VALID(portn)); 53844961713Sgirish 53944961713Sgirish IPP_REG_RD(handle, portn, IPP_STATE_MACHINE_REG, &val); 54044961713Sgirish 54144961713Sgirish *sm = (uint32_t)val; 54244961713Sgirish return (NPI_SUCCESS); 54344961713Sgirish } 54444961713Sgirish 54544961713Sgirish npi_status_t 54644961713Sgirish npi_ipp_get_ecc_err_count(npi_handle_t handle, uint8_t portn, uint8_t *err_cnt) 54744961713Sgirish { 548a3c5bd6dSspeer ASSERT(IS_PORT_NUM_VALID(portn)); 54944961713Sgirish 55044961713Sgirish IPP_REG_RD(handle, portn, IPP_ECC_ERR_COUNTER_REG, err_cnt); 55144961713Sgirish 55244961713Sgirish return (NPI_SUCCESS); 55344961713Sgirish } 55444961713Sgirish 55544961713Sgirish npi_status_t 55644961713Sgirish npi_ipp_get_pkt_dis_count(npi_handle_t handle, uint8_t portn, uint16_t *dis_cnt) 55744961713Sgirish { 558a3c5bd6dSspeer ASSERT(IS_PORT_NUM_VALID(portn)); 55944961713Sgirish 56044961713Sgirish IPP_REG_RD(handle, portn, IPP_DISCARD_PKT_CNT_REG, dis_cnt); 56144961713Sgirish 56244961713Sgirish return (NPI_SUCCESS); 56344961713Sgirish } 56444961713Sgirish 56544961713Sgirish npi_status_t 56644961713Sgirish npi_ipp_get_cs_err_count(npi_handle_t handle, uint8_t portn, uint16_t *err_cnt) 56744961713Sgirish { 568a3c5bd6dSspeer ASSERT(IS_PORT_NUM_VALID(portn)); 56944961713Sgirish 570*f6485eecSyc IPP_REG_RD(handle, portn, IPP_BAD_CKSUM_ERR_CNT_REG, err_cnt); 57144961713Sgirish 57244961713Sgirish return (NPI_SUCCESS); 57344961713Sgirish } 574