1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <npi_ipp.h> 29 30 uint64_t ipp_fzc_offset[] = { 31 IPP_CONFIG_REG, 32 IPP_DISCARD_PKT_CNT_REG, 33 IPP_TCP_CKSUM_ERR_CNT_REG, 34 IPP_ECC_ERR_COUNTER_REG, 35 IPP_INT_STATUS_REG, 36 IPP_INT_MASK_REG, 37 IPP_PFIFO_RD_DATA0_REG, 38 IPP_PFIFO_RD_DATA1_REG, 39 IPP_PFIFO_RD_DATA2_REG, 40 IPP_PFIFO_RD_DATA3_REG, 41 IPP_PFIFO_RD_DATA4_REG, 42 IPP_PFIFO_WR_DATA0_REG, 43 IPP_PFIFO_WR_DATA1_REG, 44 IPP_PFIFO_WR_DATA2_REG, 45 IPP_PFIFO_WR_DATA3_REG, 46 IPP_PFIFO_WR_DATA4_REG, 47 IPP_PFIFO_RD_PTR_REG, 48 IPP_PFIFO_WR_PTR_REG, 49 IPP_DFIFO_RD_DATA0_REG, 50 IPP_DFIFO_RD_DATA1_REG, 51 IPP_DFIFO_RD_DATA2_REG, 52 IPP_DFIFO_RD_DATA3_REG, 53 IPP_DFIFO_RD_DATA4_REG, 54 IPP_DFIFO_WR_DATA0_REG, 55 IPP_DFIFO_WR_DATA1_REG, 56 IPP_DFIFO_WR_DATA2_REG, 57 IPP_DFIFO_WR_DATA3_REG, 58 IPP_DFIFO_WR_DATA4_REG, 59 IPP_DFIFO_RD_PTR_REG, 60 IPP_DFIFO_WR_PTR_REG, 61 IPP_STATE_MACHINE_REG, 62 IPP_CKSUM_STATUS_REG, 63 IPP_FFLP_CKSUM_INFO_REG, 64 IPP_DEBUG_SELECT_REG, 65 IPP_DFIFO_ECC_SYNDROME_REG, 66 IPP_DFIFO_EOPM_RD_PTR_REG, 67 IPP_ECC_CTRL_REG 68 }; 69 70 const char *ipp_fzc_name[] = { 71 "IPP_CONFIG_REG", 72 "IPP_DISCARD_PKT_CNT_REG", 73 "IPP_TCP_CKSUM_ERR_CNT_REG", 74 "IPP_ECC_ERR_COUNTER_REG", 75 "IPP_INT_STATUS_REG", 76 "IPP_INT_MASK_REG", 77 "IPP_PFIFO_RD_DATA0_REG", 78 "IPP_PFIFO_RD_DATA1_REG", 79 "IPP_PFIFO_RD_DATA2_REG", 80 "IPP_PFIFO_RD_DATA3_REG", 81 "IPP_PFIFO_RD_DATA4_REG", 82 "IPP_PFIFO_WR_DATA0_REG", 83 "IPP_PFIFO_WR_DATA1_REG", 84 "IPP_PFIFO_WR_DATA2_REG", 85 "IPP_PFIFO_WR_DATA3_REG", 86 "IPP_PFIFO_WR_DATA4_REG", 87 "IPP_PFIFO_RD_PTR_REG", 88 "IPP_PFIFO_WR_PTR_REG", 89 "IPP_DFIFO_RD_DATA0_REG", 90 "IPP_DFIFO_RD_DATA1_REG", 91 "IPP_DFIFO_RD_DATA2_REG", 92 "IPP_DFIFO_RD_DATA3_REG", 93 "IPP_DFIFO_RD_DATA4_REG", 94 "IPP_DFIFO_WR_DATA0_REG", 95 "IPP_DFIFO_WR_DATA1_REG", 96 "IPP_DFIFO_WR_DATA2_REG", 97 "IPP_DFIFO_WR_DATA3_REG", 98 "IPP_DFIFO_WR_DATA4_REG", 99 "IPP_DFIFO_RD_PTR_REG", 100 "IPP_DFIFO_WR_PTR_REG", 101 "IPP_STATE_MACHINE_REG", 102 "IPP_CKSUM_STATUS_REG", 103 "IPP_FFLP_CKSUM_INFO_REG", 104 "IPP_DEBUG_SELECT_REG", 105 "IPP_DFIFO_ECC_SYNDROME_REG", 106 "IPP_DFIFO_EOPM_RD_PTR_REG", 107 "IPP_ECC_CTRL_REG", 108 }; 109 110 npi_status_t 111 npi_ipp_dump_regs(npi_handle_t handle, uint8_t port) 112 { 113 uint64_t value, offset; 114 int num_regs, i; 115 116 if (!IS_PORT_NUM_VALID(port)) { 117 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 118 " npi_ipp_dump_regs" 119 " Invalid Input: port <%d>", port)); 120 return (NPI_FAILURE); 121 } 122 123 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 124 "\nIPP PORT Register Dump for port %d\n", port)); 125 126 num_regs = sizeof (ipp_fzc_offset) / sizeof (uint64_t); 127 for (i = 0; i < num_regs; i++) { 128 offset = IPP_REG_ADDR(port, ipp_fzc_offset[i]); 129 NXGE_REG_RD64(handle, offset, &value); 130 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, "0x%08llx " 131 "%s\t 0x%08llx \n", 132 offset, ipp_fzc_name[i], value)); 133 } 134 135 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 136 "\n IPP FZC Register Dump for port %d done\n", port)); 137 138 return (NPI_SUCCESS); 139 } 140 141 void 142 npi_ipp_read_regs(npi_handle_t handle, uint8_t port) 143 { 144 uint64_t value, offset; 145 int num_regs, i; 146 147 if (!IS_PORT_NUM_VALID(port)) { 148 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 149 " npi_ipp_dump_regs" 150 " Invalid Input: port <%d>", port)); 151 return; 152 } 153 154 NPI_DEBUG_MSG((handle.function, NPI_IPP_CTL, 155 "\nIPP PORT Register read (to clear) for port %d\n", port)); 156 157 num_regs = sizeof (ipp_fzc_offset) / sizeof (uint64_t); 158 for (i = 0; i < num_regs; i++) { 159 offset = IPP_REG_ADDR(port, ipp_fzc_offset[i]); 160 NXGE_REG_RD64(handle, offset, &value); 161 } 162 163 } 164 165 /* IPP Reset Routine */ 166 167 npi_status_t 168 npi_ipp_reset(npi_handle_t handle, uint8_t portn) 169 { 170 uint64_t val = 0; 171 uint32_t cnt = MAX_PIO_RETRIES; 172 173 if (!IS_PORT_NUM_VALID(portn)) { 174 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 175 " npi_ipp_reset" 176 " Invalid Input portn <0x%x>", 177 portn)); 178 return (NPI_FAILURE | NPI_IPP_PORT_INVALID(portn)); 179 } 180 181 IPP_REG_RD(handle, portn, IPP_CONFIG_REG, &val); 182 val |= IPP_SOFT_RESET; 183 IPP_REG_WR(handle, portn, IPP_CONFIG_REG, val); 184 185 do { 186 NXGE_DELAY(IPP_RESET_WAIT); 187 IPP_REG_RD(handle, portn, IPP_CONFIG_REG, &val); 188 cnt--; 189 } while (((val & IPP_SOFT_RESET) != 0) && (cnt > 0)); 190 191 if (cnt == 0) { 192 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 193 " npi_ipp_reset" 194 " HW Error: IPP_RESET <0x%x>", val)); 195 return (NPI_FAILURE | NPI_IPP_RESET_FAILED(portn)); 196 } 197 198 return (NPI_SUCCESS); 199 } 200 201 202 /* IPP Configuration Routine */ 203 204 npi_status_t 205 npi_ipp_config(npi_handle_t handle, config_op_t op, uint8_t portn, 206 ipp_config_t config) 207 { 208 uint64_t val = 0; 209 210 if (!IS_PORT_NUM_VALID(portn)) { 211 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 212 " npi_ipp_config" 213 " Invalid Input portn <0x%x>", portn)); 214 return (NPI_FAILURE | NPI_IPP_PORT_INVALID(portn)); 215 } 216 217 switch (op) { 218 219 case ENABLE: 220 case DISABLE: 221 if ((config == 0) || ((config & ~CFG_IPP_ALL) != 0)) { 222 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 223 " npi_ipp_config", 224 " Invalid Input config <0x%x>", 225 config)); 226 return (NPI_FAILURE | NPI_IPP_CONFIG_INVALID(portn)); 227 } 228 229 IPP_REG_RD(handle, portn, IPP_CONFIG_REG, &val); 230 231 if (op == ENABLE) 232 val |= config; 233 else 234 val &= ~config; 235 break; 236 237 case INIT: 238 if ((config & ~CFG_IPP_ALL) != 0) { 239 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 240 " npi_ipp_config" 241 " Invalid Input config <0x%x>", 242 config)); 243 return (NPI_FAILURE | NPI_IPP_CONFIG_INVALID(portn)); 244 } 245 IPP_REG_RD(handle, portn, IPP_CONFIG_REG, &val); 246 247 248 val &= (IPP_IP_MAX_PKT_BYTES_MASK); 249 val |= config; 250 break; 251 252 default: 253 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 254 " npi_ipp_config" 255 " Invalid Input op <0x%x>", op)); 256 return (NPI_FAILURE | NPI_IPP_OPCODE_INVALID(portn)); 257 } 258 259 IPP_REG_WR(handle, portn, IPP_CONFIG_REG, val); 260 return (NPI_SUCCESS); 261 } 262 263 264 npi_status_t 265 npi_ipp_set_max_pktsize(npi_handle_t handle, uint8_t portn, uint32_t bytes) 266 { 267 uint64_t val = 0; 268 269 if (!IS_PORT_NUM_VALID(portn)) { 270 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 271 " npi_ipp_set_max_pktsize" 272 " Invalid Input portn <0x%x>", 273 portn)); 274 return (NPI_FAILURE | NPI_IPP_PORT_INVALID(portn)); 275 } 276 277 if (bytes > IPP_IP_MAX_PKT_BYTES_MASK) { 278 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 279 " npi_ipp_set_max_pktsize" 280 " Invalid Input Max bytes <0x%x>", 281 bytes)); 282 return (NPI_FAILURE | NPI_IPP_MAX_PKT_BYTES_INVALID(portn)); 283 } 284 285 IPP_REG_RD(handle, portn, IPP_CONFIG_REG, &val); 286 val &= ~(IPP_IP_MAX_PKT_BYTES_MASK << IPP_IP_MAX_PKT_BYTES_SHIFT); 287 288 val |= (bytes << IPP_IP_MAX_PKT_BYTES_SHIFT); 289 IPP_REG_WR(handle, portn, IPP_CONFIG_REG, val); 290 291 return (NPI_SUCCESS); 292 } 293 294 295 296 /* IPP Interrupt Configuration Routine */ 297 298 npi_status_t 299 npi_ipp_iconfig(npi_handle_t handle, config_op_t op, uint8_t portn, 300 ipp_iconfig_t iconfig) 301 { 302 uint64_t val = 0; 303 304 if (!IS_PORT_NUM_VALID(portn)) { 305 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 306 " npi_ipp_config" 307 " Invalid Input portn <0x%x>", 308 portn)); 309 return (NPI_FAILURE | NPI_IPP_PORT_INVALID(portn)); 310 } 311 312 switch (op) { 313 case ENABLE: 314 case DISABLE: 315 316 if ((iconfig == 0) || ((iconfig & ~ICFG_IPP_ALL) != 0)) { 317 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 318 " npi_ipp_iconfig" 319 " Invalid Input iconfig <0x%x>", 320 iconfig)); 321 return (NPI_FAILURE | NPI_IPP_CONFIG_INVALID(portn)); 322 } 323 324 IPP_REG_RD(handle, portn, IPP_INT_MASK_REG, &val); 325 if (op == ENABLE) 326 val &= ~iconfig; 327 else 328 val |= iconfig; 329 IPP_REG_WR(handle, portn, IPP_INT_MASK_REG, val); 330 331 break; 332 case INIT: 333 334 if ((iconfig & ~ICFG_IPP_ALL) != 0) { 335 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 336 " npi_ipp_iconfig" 337 " Invalid Input iconfig <0x%x>", 338 iconfig)); 339 return (NPI_FAILURE | NPI_IPP_CONFIG_INVALID(portn)); 340 } 341 IPP_REG_WR(handle, portn, IPP_INT_MASK_REG, ~iconfig); 342 343 break; 344 default: 345 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 346 " npi_ipp_iconfig" 347 " Invalid Input iconfig <0x%x>", 348 iconfig)); 349 return (NPI_FAILURE | NPI_IPP_OPCODE_INVALID(portn)); 350 } 351 352 return (NPI_SUCCESS); 353 } 354 355 npi_status_t 356 npi_ipp_get_status(npi_handle_t handle, uint8_t portn, ipp_status_t *status) 357 { 358 uint64_t val; 359 360 if (!IS_PORT_NUM_VALID(portn)) { 361 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 362 " npi_ipp_get_status" 363 " Invalid Input portn <0x%x>", 364 portn)); 365 return (NPI_FAILURE | NPI_IPP_PORT_INVALID(portn)); 366 } 367 368 IPP_REG_RD(handle, portn, IPP_INT_STATUS_REG, &val); 369 370 status->value = val; 371 return (NPI_SUCCESS); 372 } 373 374 npi_status_t 375 npi_ipp_get_pfifo_rd_ptr(npi_handle_t handle, uint8_t portn, uint16_t *rd_ptr) 376 { 377 uint64_t value; 378 if (!IS_PORT_NUM_VALID(portn)) { 379 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 380 " npi_ipp_get_pfifo_rd_ptr" 381 " Invalid Input portn <0x%x>", 382 portn)); 383 return (NPI_FAILURE | NPI_IPP_PORT_INVALID(portn)); 384 } 385 386 IPP_REG_RD(handle, portn, IPP_PFIFO_RD_PTR_REG, &value); 387 *rd_ptr = value & 0xfff; 388 return (NPI_SUCCESS); 389 } 390 391 npi_status_t 392 npi_ipp_get_pfifo_wr_ptr(npi_handle_t handle, uint8_t portn, uint16_t *wr_ptr) 393 { 394 uint64_t value; 395 if (!IS_PORT_NUM_VALID(portn)) { 396 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 397 " npi_ipp_get_pfifo_wr_ptr" 398 " Invalid Input portn <0x%x>", 399 portn)); 400 return (NPI_FAILURE | NPI_IPP_PORT_INVALID(portn)); 401 } 402 403 IPP_REG_RD(handle, portn, IPP_PFIFO_WR_PTR_REG, &value); 404 *wr_ptr = value & 0xfff; 405 return (NPI_SUCCESS); 406 } 407 408 npi_status_t 409 npi_ipp_get_dfifo_rd_ptr(npi_handle_t handle, uint8_t portn, uint16_t *rd_ptr) 410 { 411 uint64_t value; 412 if (!IS_PORT_NUM_VALID(portn)) { 413 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 414 " npi_ipp_get_dfifo_rd_ptr" 415 " Invalid Input portn <0x%x>", 416 portn)); 417 return (NPI_FAILURE | NPI_IPP_PORT_INVALID(portn)); 418 } 419 420 IPP_REG_RD(handle, portn, IPP_DFIFO_RD_PTR_REG, &value); 421 *rd_ptr = (uint16_t)(value & ((portn < 2) ? IPP_XMAC_DFIFO_PTR_MASK : 422 IPP_BMAC_DFIFO_PTR_MASK)); 423 return (NPI_SUCCESS); 424 } 425 426 npi_status_t 427 npi_ipp_get_dfifo_wr_ptr(npi_handle_t handle, uint8_t portn, uint16_t *wr_ptr) 428 { 429 uint64_t value; 430 if (!IS_PORT_NUM_VALID(portn)) { 431 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 432 " npi_ipp_get_dfifo_wr_ptr" 433 " Invalid Input portn <0x%x>", 434 portn)); 435 return (NPI_FAILURE | NPI_IPP_PORT_INVALID(portn)); 436 } 437 438 IPP_REG_RD(handle, portn, IPP_DFIFO_WR_PTR_REG, &value); 439 *wr_ptr = (uint16_t)(value & ((portn < 2) ? IPP_XMAC_DFIFO_PTR_MASK : 440 IPP_BMAC_DFIFO_PTR_MASK)); 441 return (NPI_SUCCESS); 442 } 443 444 445 npi_status_t 446 npi_ipp_write_pfifo(npi_handle_t handle, uint8_t portn, uint8_t addr, 447 uint32_t d0, uint32_t d1, uint32_t d2, uint32_t d3, uint32_t d4) 448 { 449 uint64_t val; 450 451 if (!IS_PORT_NUM_VALID(portn)) { 452 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 453 " npi_ipp_write_pfifo" 454 " Invalid Input portn <0x%x>", 455 portn)); 456 return (NPI_FAILURE | NPI_IPP_PORT_INVALID(portn)); 457 } 458 459 if (addr >= 64) { 460 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 461 " npi_ipp_write_pfifo" 462 " Invalid PFIFO address <0x%x>", addr)); 463 return (NPI_FAILURE | NPI_IPP_FIFO_ADDR_INVALID(portn)); 464 } 465 466 IPP_REG_RD(handle, portn, IPP_CONFIG_REG, &val); 467 val |= IPP_PRE_FIFO_PIO_WR_EN; 468 IPP_REG_WR(handle, portn, IPP_CONFIG_REG, val); 469 470 IPP_REG_WR(handle, portn, IPP_PFIFO_WR_PTR_REG, addr); 471 IPP_REG_WR(handle, portn, IPP_PFIFO_WR_DATA0_REG, d0); 472 IPP_REG_WR(handle, portn, IPP_PFIFO_WR_DATA1_REG, d1); 473 IPP_REG_WR(handle, portn, IPP_PFIFO_WR_DATA2_REG, d2); 474 IPP_REG_WR(handle, portn, IPP_PFIFO_WR_DATA3_REG, d3); 475 IPP_REG_WR(handle, portn, IPP_PFIFO_WR_DATA4_REG, d4); 476 477 val &= ~IPP_PRE_FIFO_PIO_WR_EN; 478 IPP_REG_WR(handle, portn, IPP_CONFIG_REG, val); 479 480 return (NPI_SUCCESS); 481 } 482 483 npi_status_t 484 npi_ipp_read_pfifo(npi_handle_t handle, uint8_t portn, uint8_t addr, 485 uint32_t *d0, uint32_t *d1, uint32_t *d2, uint32_t *d3, 486 uint32_t *d4) 487 { 488 if (!IS_PORT_NUM_VALID(portn)) { 489 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 490 " npi_ipp_read_pfifo" 491 " Invalid Input portn <0x%x>", 492 portn)); 493 return (NPI_FAILURE | NPI_IPP_PORT_INVALID(portn)); 494 } 495 496 if (addr >= 64) { 497 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 498 " npi_ipp_read_pfifo" 499 " Invalid PFIFO address <0x%x>", addr)); 500 return (NPI_FAILURE | NPI_IPP_FIFO_ADDR_INVALID(portn)); 501 } 502 503 IPP_REG_WR(handle, portn, IPP_PFIFO_RD_PTR_REG, addr); 504 IPP_REG_RD(handle, portn, IPP_PFIFO_RD_DATA0_REG, d0); 505 IPP_REG_RD(handle, portn, IPP_PFIFO_RD_DATA1_REG, d1); 506 IPP_REG_RD(handle, portn, IPP_PFIFO_RD_DATA2_REG, d2); 507 IPP_REG_RD(handle, portn, IPP_PFIFO_RD_DATA3_REG, d3); 508 IPP_REG_RD(handle, portn, IPP_PFIFO_RD_DATA4_REG, d4); 509 510 return (NPI_SUCCESS); 511 } 512 513 npi_status_t 514 npi_ipp_write_dfifo(npi_handle_t handle, uint8_t portn, uint16_t addr, 515 uint32_t d0, uint32_t d1, uint32_t d2, uint32_t d3, uint32_t d4) 516 { 517 uint64_t val; 518 519 if (!IS_PORT_NUM_VALID(portn)) { 520 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 521 " npi_ipp_write_dfifo" 522 " Invalid Input portn <0x%x>", 523 portn)); 524 return (NPI_FAILURE | NPI_IPP_PORT_INVALID(portn)); 525 } 526 527 if (addr >= 2048) { 528 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 529 " npi_ipp_write_dfifo" 530 " Invalid DFIFO address <0x%x>", addr)); 531 return (NPI_FAILURE | NPI_IPP_FIFO_ADDR_INVALID(portn)); 532 } 533 534 IPP_REG_RD(handle, portn, IPP_CONFIG_REG, &val); 535 val |= IPP_DFIFO_PIO_WR_EN; 536 IPP_REG_WR(handle, portn, IPP_CONFIG_REG, val); 537 538 IPP_REG_WR(handle, portn, IPP_DFIFO_WR_PTR_REG, addr); 539 IPP_REG_WR(handle, portn, IPP_DFIFO_WR_DATA0_REG, d0); 540 IPP_REG_WR(handle, portn, IPP_DFIFO_WR_DATA1_REG, d1); 541 IPP_REG_WR(handle, portn, IPP_DFIFO_WR_DATA2_REG, d2); 542 IPP_REG_WR(handle, portn, IPP_DFIFO_WR_DATA3_REG, d3); 543 IPP_REG_WR(handle, portn, IPP_DFIFO_WR_DATA4_REG, d4); 544 545 val &= ~IPP_DFIFO_PIO_WR_EN; 546 IPP_REG_WR(handle, portn, IPP_CONFIG_REG, val); 547 548 return (NPI_SUCCESS); 549 } 550 551 npi_status_t 552 npi_ipp_read_dfifo(npi_handle_t handle, uint8_t portn, uint16_t addr, 553 uint32_t *d0, uint32_t *d1, uint32_t *d2, uint32_t *d3, 554 uint32_t *d4) 555 { 556 if (!IS_PORT_NUM_VALID(portn)) { 557 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 558 " npi_ipp_read_dfifo" 559 " Invalid Input portn <0x%x>", 560 portn)); 561 return (NPI_FAILURE | NPI_IPP_PORT_INVALID(portn)); 562 } 563 564 if (addr >= 2048) { 565 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 566 " npi_ipp_read_dfifo" 567 " Invalid DFIFO address <0x%x>", addr)); 568 return (NPI_FAILURE | NPI_IPP_FIFO_ADDR_INVALID(portn)); 569 } 570 571 IPP_REG_WR(handle, portn, IPP_DFIFO_RD_PTR_REG, addr); 572 IPP_REG_RD(handle, portn, IPP_DFIFO_RD_DATA0_REG, d0); 573 IPP_REG_RD(handle, portn, IPP_DFIFO_RD_DATA1_REG, d1); 574 IPP_REG_RD(handle, portn, IPP_DFIFO_RD_DATA2_REG, d2); 575 IPP_REG_RD(handle, portn, IPP_DFIFO_RD_DATA3_REG, d3); 576 IPP_REG_RD(handle, portn, IPP_DFIFO_RD_DATA4_REG, d4); 577 578 return (NPI_SUCCESS); 579 } 580 581 582 npi_status_t 583 npi_ipp_get_ecc_syndrome(npi_handle_t handle, uint8_t portn, uint16_t *syndrome) 584 { 585 uint64_t val; 586 587 if (!IS_PORT_NUM_VALID(portn)) { 588 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 589 " npi_ipp_get_ecc_syndrome" 590 " Invalid Input portn <0x%x>", 591 portn)); 592 return (NPI_FAILURE | NPI_IPP_PORT_INVALID(portn)); 593 } 594 595 IPP_REG_RD(handle, portn, IPP_DFIFO_ECC_SYNDROME_REG, &val); 596 597 *syndrome = (uint16_t)val; 598 return (NPI_SUCCESS); 599 } 600 601 npi_status_t 602 npi_ipp_get_dfifo_eopm_rdptr(npi_handle_t handle, uint8_t portn, 603 uint16_t *rdptr) 604 { 605 uint64_t val; 606 607 if (!IS_PORT_NUM_VALID(portn)) { 608 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 609 " npi_ipp_get_dfifo_rdptr" 610 " Invalid Input portn <0x%x>", 611 portn)); 612 return (NPI_FAILURE | NPI_IPP_PORT_INVALID(portn)); 613 } 614 615 IPP_REG_RD(handle, portn, IPP_DFIFO_EOPM_RD_PTR_REG, &val); 616 617 *rdptr = (uint16_t)val; 618 return (NPI_SUCCESS); 619 } 620 621 npi_status_t 622 npi_ipp_get_state_mach(npi_handle_t handle, uint8_t portn, uint32_t *sm) 623 { 624 uint64_t val; 625 626 if (!IS_PORT_NUM_VALID(portn)) { 627 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 628 " npi_ipp_get_state_mach" 629 " Invalid Input portn <0x%x>", 630 portn)); 631 return (NPI_FAILURE | NPI_IPP_PORT_INVALID(portn)); 632 } 633 634 IPP_REG_RD(handle, portn, IPP_STATE_MACHINE_REG, &val); 635 636 *sm = (uint32_t)val; 637 return (NPI_SUCCESS); 638 } 639 640 npi_status_t 641 npi_ipp_get_ecc_err_count(npi_handle_t handle, uint8_t portn, uint8_t *err_cnt) 642 { 643 if (!IS_PORT_NUM_VALID(portn)) { 644 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 645 " npi_ipp_get_ecc_err_count" 646 " Invalid Input portn <0x%x>", 647 portn)); 648 return (NPI_FAILURE | NPI_IPP_PORT_INVALID(portn)); 649 } 650 651 IPP_REG_RD(handle, portn, IPP_ECC_ERR_COUNTER_REG, err_cnt); 652 653 return (NPI_SUCCESS); 654 } 655 656 npi_status_t 657 npi_ipp_get_pkt_dis_count(npi_handle_t handle, uint8_t portn, uint16_t *dis_cnt) 658 { 659 if (!IS_PORT_NUM_VALID(portn)) { 660 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 661 " npi_ipp_get_pkt_dis_count" 662 " Invalid Input portn <0x%x>", 663 portn)); 664 return (NPI_FAILURE | NPI_IPP_PORT_INVALID(portn)); 665 } 666 667 IPP_REG_RD(handle, portn, IPP_DISCARD_PKT_CNT_REG, dis_cnt); 668 669 return (NPI_SUCCESS); 670 } 671 672 npi_status_t 673 npi_ipp_get_cs_err_count(npi_handle_t handle, uint8_t portn, uint16_t *err_cnt) 674 { 675 if (!IS_PORT_NUM_VALID(portn)) { 676 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 677 " npi_ipp_get_cs_err_count" 678 " Invalid Input portn <0x%x>", 679 portn)); 680 return (NPI_FAILURE | NPI_IPP_PORT_INVALID(portn)); 681 } 682 683 IPP_REG_RD(handle, portn, IPP_ECC_ERR_COUNTER_REG, err_cnt); 684 685 return (NPI_SUCCESS); 686 } 687