14496171girish/*
24496171girish * CDDL HEADER START
34496171girish *
44496171girish * The contents of this file are subject to the terms of the
54496171girish * Common Development and Distribution License (the "License").
64496171girish * You may not use this file except in compliance with the License.
74496171girish *
84496171girish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
94496171girish * or http://www.opensolaris.org/os/licensing.
104496171girish * See the License for the specific language governing permissions
114496171girish * and limitations under the License.
124496171girish *
134496171girish * When distributing Covered Code, include this CDDL HEADER in each
144496171girish * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
154496171girish * If applicable, add the following below this CDDL HEADER, with the
164496171girish * fields enclosed by brackets "[]" replaced with your own identifying
174496171girish * information: Portions Copyright [yyyy] [name of copyright owner]
184496171girish *
194496171girish * CDDL HEADER END
204496171girish */
214496171girish/*
2252ccf84misaki * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
234496171girish * Use is subject to license terms.
244496171girish */
254496171girish
264496171girish#pragma ident	"%Z%%M%	%I%	%E% SMI"
274496171girish
284496171girish#include <npi_ipp.h>
294496171girish
304496171girishuint64_t ipp_fzc_offset[] = {
314496171girish		IPP_CONFIG_REG,
324496171girish		IPP_DISCARD_PKT_CNT_REG,
33f6485eeyc		IPP_BAD_CKSUM_ERR_CNT_REG,
344496171girish		IPP_ECC_ERR_COUNTER_REG,
354496171girish		IPP_INT_STATUS_REG,
364496171girish		IPP_INT_MASK_REG,
374496171girish		IPP_PFIFO_RD_DATA0_REG,
384496171girish		IPP_PFIFO_RD_DATA1_REG,
394496171girish		IPP_PFIFO_RD_DATA2_REG,
404496171girish		IPP_PFIFO_RD_DATA3_REG,
414496171girish		IPP_PFIFO_RD_DATA4_REG,
424496171girish		IPP_PFIFO_WR_DATA0_REG,
434496171girish		IPP_PFIFO_WR_DATA1_REG,
444496171girish		IPP_PFIFO_WR_DATA2_REG,
454496171girish		IPP_PFIFO_WR_DATA3_REG,
464496171girish		IPP_PFIFO_WR_DATA4_REG,
474496171girish		IPP_PFIFO_RD_PTR_REG,
484496171girish		IPP_PFIFO_WR_PTR_REG,
494496171girish		IPP_DFIFO_RD_DATA0_REG,
504496171girish		IPP_DFIFO_RD_DATA1_REG,
514496171girish		IPP_DFIFO_RD_DATA2_REG,
524496171girish		IPP_DFIFO_RD_DATA3_REG,
534496171girish		IPP_DFIFO_RD_DATA4_REG,
544496171girish		IPP_DFIFO_WR_DATA0_REG,
554496171girish		IPP_DFIFO_WR_DATA1_REG,
564496171girish		IPP_DFIFO_WR_DATA2_REG,
574496171girish		IPP_DFIFO_WR_DATA3_REG,
584496171girish		IPP_DFIFO_WR_DATA4_REG,
594496171girish		IPP_DFIFO_RD_PTR_REG,
604496171girish		IPP_DFIFO_WR_PTR_REG,
614496171girish		IPP_STATE_MACHINE_REG,
624496171girish		IPP_CKSUM_STATUS_REG,
634496171girish		IPP_FFLP_CKSUM_INFO_REG,
644496171girish		IPP_DEBUG_SELECT_REG,
654496171girish		IPP_DFIFO_ECC_SYNDROME_REG,
664496171girish		IPP_DFIFO_EOPM_RD_PTR_REG,
674496171girish		IPP_ECC_CTRL_REG
684496171girish};
694496171girish
704496171girishconst char *ipp_fzc_name[] = {
714496171girish		"IPP_CONFIG_REG",
724496171girish		"IPP_DISCARD_PKT_CNT_REG",
73f6485eeyc		"IPP_BAD_CKSUM_ERR_CNT_REG",
744496171girish		"IPP_ECC_ERR_COUNTER_REG",
754496171girish		"IPP_INT_STATUS_REG",
764496171girish		"IPP_INT_MASK_REG",
774496171girish		"IPP_PFIFO_RD_DATA0_REG",
784496171girish		"IPP_PFIFO_RD_DATA1_REG",
794496171girish		"IPP_PFIFO_RD_DATA2_REG",
804496171girish		"IPP_PFIFO_RD_DATA3_REG",
814496171girish		"IPP_PFIFO_RD_DATA4_REG",
824496171girish		"IPP_PFIFO_WR_DATA0_REG",
834496171girish		"IPP_PFIFO_WR_DATA1_REG",
844496171girish		"IPP_PFIFO_WR_DATA2_REG",
854496171girish		"IPP_PFIFO_WR_DATA3_REG",
864496171girish		"IPP_PFIFO_WR_DATA4_REG",
874496171girish		"IPP_PFIFO_RD_PTR_REG",
884496171girish		"IPP_PFIFO_WR_PTR_REG",
894496171girish		"IPP_DFIFO_RD_DATA0_REG",
904496171girish		"IPP_DFIFO_RD_DATA1_REG",
914496171girish		"IPP_DFIFO_RD_DATA2_REG",
924496171girish		"IPP_DFIFO_RD_DATA3_REG",
934496171girish		"IPP_DFIFO_RD_DATA4_REG",
944496171girish		"IPP_DFIFO_WR_DATA0_REG",
954496171girish		"IPP_DFIFO_WR_DATA1_REG",
964496171girish		"IPP_DFIFO_WR_DATA2_REG",
974496171girish		"IPP_DFIFO_WR_DATA3_REG",
984496171girish		"IPP_DFIFO_WR_DATA4_REG",
994496171girish		"IPP_DFIFO_RD_PTR_REG",
1004496171girish		"IPP_DFIFO_WR_PTR_REG",
1014496171girish		"IPP_STATE_MACHINE_REG",
1024496171girish		"IPP_CKSUM_STATUS_REG",
1034496171girish		"IPP_FFLP_CKSUM_INFO_REG",
1044496171girish		"IPP_DEBUG_SELECT_REG",
1054496171girish		"IPP_DFIFO_ECC_SYNDROME_REG",
1064496171girish		"IPP_DFIFO_EOPM_RD_PTR_REG",
1074496171girish		"IPP_ECC_CTRL_REG",
1084496171girish};
1094496171girish
1104496171girishnpi_status_t
1114496171girishnpi_ipp_dump_regs(npi_handle_t handle, uint8_t port)
1124496171girish{
1134496171girish	uint64_t		value, offset;
1144496171girish	int 			num_regs, i;
1154496171girish
116a3c5bd6speer	ASSERT(IS_PORT_NUM_VALID(port));
1174496171girish
1184496171girish	NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
11952ccf84misaki	    "\nIPP PORT Register Dump for port %d\n", port));
1204496171girish
1214496171girish	num_regs = sizeof (ipp_fzc_offset) / sizeof (uint64_t);
1224496171girish	for (i = 0; i < num_regs; i++) {
1234496171girish		offset = IPP_REG_ADDR(port, ipp_fzc_offset[i]);
124adfcba5joycey#if defined(__i386)
125adfcba5joycey		NXGE_REG_RD64(handle, (uint32_t)offset, &value);
126adfcba5joycey#else
1274496171girish		NXGE_REG_RD64(handle, offset, &value);
128adfcba5joycey#endif
1294496171girish		NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, "0x%08llx "
13052ccf84misaki		    "%s\t 0x%08llx \n",
13152ccf84misaki		    offset, ipp_fzc_name[i], value));
1324496171girish	}
1334496171girish
1344496171girish	NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
13552ccf84misaki	    "\n IPP FZC Register Dump for port %d done\n", port));
1364496171girish
1374496171girish	return (NPI_SUCCESS);
1384496171girish}
1394496171girish
1404496171girishvoid
1414496171girishnpi_ipp_read_regs(npi_handle_t handle, uint8_t port)
1424496171girish{
1434496171girish	uint64_t		value, offset;
1444496171girish	int 			num_regs, i;
1454496171girish
146a3c5bd6speer	ASSERT(IS_PORT_NUM_VALID(port));
1474496171girish
1484496171girish	NPI_DEBUG_MSG((handle.function, NPI_IPP_CTL,
14952ccf84misaki	    "\nIPP PORT Register read (to clear) for port %d\n", port));
1504496171girish
1514496171girish	num_regs = sizeof (ipp_fzc_offset) / sizeof (uint64_t);
1524496171girish	for (i = 0; i < num_regs; i++) {
1534496171girish		offset = IPP_REG_ADDR(port, ipp_fzc_offset[i]);
154adfcba5joycey#if defined(__i386)
155adfcba5joycey		NXGE_REG_RD64(handle, (uint32_t)offset, &value);
156adfcba5joycey#else
1574496171girish		NXGE_REG_RD64(handle, offset, &value);
158adfcba5joycey#endif
1594496171girish	}
1604496171girish
1614496171girish}
1624496171girish
163a3c5bd6speer/*
164a3c5bd6speer * IPP Reset Routine
165a3c5bd6speer */
1664496171girishnpi_status_t
1674496171girishnpi_ipp_reset(npi_handle_t handle, uint8_t portn)
1684496171girish{
1694496171girish	uint64_t val = 0;
1704496171girish	uint32_t cnt = MAX_PIO_RETRIES;
1714496171girish
172a3c5bd6speer	ASSERT(IS_PORT_NUM_VALID(portn));
1734496171girish
1744496171girish	IPP_REG_RD(handle, portn, IPP_CONFIG_REG, &val);
1754496171girish	val |= IPP_SOFT_RESET;
1764496171girish	IPP_REG_WR(handle, portn, IPP_CONFIG_REG, val);
1774496171girish
1784496171girish	do {
1794496171girish		NXGE_DELAY(IPP_RESET_WAIT);
1804496171girish		IPP_REG_RD(handle, portn, IPP_CONFIG_REG, &val);
1814496171girish		cnt--;
1824496171girish	} while (((val & IPP_SOFT_RESET) != 0) && (cnt > 0));
1834496171girish
1844496171girish	if (cnt == 0) {
1854496171girish		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
18652ccf84misaki		    " npi_ipp_reset"
18752ccf84misaki		    " HW Error: IPP_RESET  <0x%x>", val));
1884496171girish		return (NPI_FAILURE | NPI_IPP_RESET_FAILED(portn));
1894496171girish	}
1904496171girish
1914496171girish	return (NPI_SUCCESS);
1924496171girish}
1934496171girish
1944496171girish
195a3c5bd6speer/*
196a3c5bd6speer * IPP Configuration Routine
197a3c5bd6speer */
1984496171girishnpi_status_t
1994496171girishnpi_ipp_config(npi_handle_t handle, config_op_t op, uint8_t portn,
2004496171girish		ipp_config_t config)
2014496171girish{
2024496171girish	uint64_t val = 0;
2034496171girish
204a3c5bd6speer	ASSERT(IS_PORT_NUM_VALID(portn));
2054496171girish
2064496171girish	switch (op) {
2074496171girish
2084496171girish	case ENABLE:
2094496171girish	case DISABLE:
2104496171girish		if ((config == 0) || ((config & ~CFG_IPP_ALL) != 0)) {
2114496171girish			NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
21252ccf84misaki			    " npi_ipp_config",
21352ccf84misaki			    " Invalid Input config <0x%x>",
21452ccf84misaki			    config));
2154496171girish			return (NPI_FAILURE | NPI_IPP_CONFIG_INVALID(portn));
2164496171girish		}
2174496171girish
2184496171girish		IPP_REG_RD(handle, portn, IPP_CONFIG_REG, &val);
2194496171girish
2204496171girish		if (op == ENABLE)
2214496171girish			val |= config;
2224496171girish		else
2234496171girish			val &= ~config;
2244496171girish		break;
2254496171girish
2264496171girish	case INIT:
2274496171girish		if ((config & ~CFG_IPP_ALL) != 0) {
2284496171girish			NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
22952ccf84misaki			    " npi_ipp_config"
23052ccf84misaki			    " Invalid Input config <0x%x>",
23152ccf84misaki			    config));
2324496171girish			return (NPI_FAILURE | NPI_IPP_CONFIG_INVALID(portn));
2334496171girish		}
2344496171girish		IPP_REG_RD(handle, portn, IPP_CONFIG_REG, &val);
2354496171girish
2364496171girish
2374496171girish		val &= (IPP_IP_MAX_PKT_BYTES_MASK);
2384496171girish		val |= config;
2394496171girish		break;
2404496171girish
2414496171girish	default:
2424496171girish		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
24352ccf84misaki		    " npi_ipp_config"
24452ccf84misaki		    " Invalid Input op <0x%x>", op));
2454496171girish		return (NPI_FAILURE | NPI_IPP_OPCODE_INVALID(portn));
2464496171girish	}
2474496171girish
2484496171girish	IPP_REG_WR(handle, portn, IPP_CONFIG_REG, val);
2494496171girish	return (NPI_SUCCESS);
2504496171girish}
2514496171girish
2524496171girishnpi_status_t
2534496171girishnpi_ipp_set_max_pktsize(npi_handle_t handle, uint8_t portn, uint32_t bytes)
2544496171girish{
2554496171girish	uint64_t val = 0;
2564496171girish
257a3c5bd6speer	ASSERT(IS_PORT_NUM_VALID(portn));
2584496171girish
2594496171girish	if (bytes > IPP_IP_MAX_PKT_BYTES_MASK) {
2604496171girish		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
26152ccf84misaki		    " npi_ipp_set_max_pktsize"
26252ccf84misaki		    " Invalid Input Max bytes <0x%x>",
26352ccf84misaki		    bytes));
2644496171girish		return (NPI_FAILURE | NPI_IPP_MAX_PKT_BYTES_INVALID(portn));
2654496171girish	}
2664496171girish
2674496171girish	IPP_REG_RD(handle, portn, IPP_CONFIG_REG, &val);
2684496171girish	val &= ~(IPP_IP_MAX_PKT_BYTES_MASK << IPP_IP_MAX_PKT_BYTES_SHIFT);
2694496171girish
2704496171girish	val |= (bytes << IPP_IP_MAX_PKT_BYTES_SHIFT);
2714496171girish	IPP_REG_WR(handle, portn, IPP_CONFIG_REG, val);
2724496171girish
2734496171girish	return (NPI_SUCCESS);
2744496171girish}
2754496171girish
276a3c5bd6speer/*
277a3c5bd6speer * IPP Interrupt Configuration Routine
278a3c5bd6speer */
2794496171girishnpi_status_t
2804496171girishnpi_ipp_iconfig(npi_handle_t handle, config_op_t op, uint8_t portn,
2814496171girish		ipp_iconfig_t iconfig)
2824496171girish{
2834496171girish	uint64_t val = 0;
2844496171girish
285a3c5bd6speer	ASSERT(IS_PORT_NUM_VALID(portn));
2864496171girish
2874496171girish	switch (op) {
2884496171girish	case ENABLE:
2894496171girish	case DISABLE:
2904496171girish
2914496171girish		if ((iconfig == 0) || ((iconfig & ~ICFG_IPP_ALL) != 0)) {
2924496171girish			NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
29352ccf84misaki			    " npi_ipp_iconfig"
29452ccf84misaki			    " Invalid Input iconfig <0x%x>",
29552ccf84misaki			    iconfig));
2964496171girish			return (NPI_FAILURE | NPI_IPP_CONFIG_INVALID(portn));
2974496171girish		}
2984496171girish
2994496171girish		IPP_REG_RD(handle, portn, IPP_INT_MASK_REG, &val);
3004496171girish		if (op == ENABLE)
3014496171girish			val &= ~iconfig;
3024496171girish		else
3034496171girish			val |= iconfig;
3044496171girish		IPP_REG_WR(handle, portn, IPP_INT_MASK_REG, val);
3054496171girish
3064496171girish		break;
3074496171girish	case INIT:
3084496171girish
3094496171girish		if ((iconfig & ~ICFG_IPP_ALL) != 0) {
3104496171girish			NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
31152ccf84misaki			    " npi_ipp_iconfig"
31252ccf84misaki			    " Invalid Input iconfig <0x%x>",
31352ccf84misaki			    iconfig));
3144496171girish			return (NPI_FAILURE | NPI_IPP_CONFIG_INVALID(portn));
3154496171girish		}
3164496171girish		IPP_REG_WR(handle, portn, IPP_INT_MASK_REG, ~iconfig);
3174496171girish
3184496171girish		break;
3194496171girish	default:
3204496171girish		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
32152ccf84misaki		    " npi_ipp_iconfig"
32252ccf84misaki		    " Invalid Input iconfig <0x%x>",
32352ccf84misaki		    iconfig));
3244496171girish		return (NPI_FAILURE | NPI_IPP_OPCODE_INVALID(portn));
3254496171girish	}
3264496171girish
3274496171girish	return (NPI_SUCCESS);
3284496171girish}
3294496171girish
3304496171girishnpi_status_t
3314496171girishnpi_ipp_get_status(npi_handle_t handle, uint8_t portn, ipp_status_t *status)
3324496171girish{
3334496171girish	uint64_t val;
3344496171girish
335a3c5bd6speer	ASSERT(IS_PORT_NUM_VALID(portn));
3364496171girish
3374496171girish	IPP_REG_RD(handle, portn, IPP_INT_STATUS_REG, &val);
3384496171girish
3394496171girish	status->value = val;
3404496171girish	return (NPI_SUCCESS);
3414496171girish}
3424496171girish
3434496171girishnpi_status_t
3444496171girishnpi_ipp_get_pfifo_rd_ptr(npi_handle_t handle, uint8_t portn, uint16_t *rd_ptr)
3454496171girish{
3464496171girish	uint64_t value;
347a3c5bd6speer
348a3c5bd6speer	ASSERT(IS_PORT_NUM_VALID(portn));
3494496171girish
3504496171girish	IPP_REG_RD(handle, portn, IPP_PFIFO_RD_PTR_REG, &value);
3514496171girish	*rd_ptr = value & 0xfff;
3524496171girish	return (NPI_SUCCESS);
3534496171girish}
3544496171girish
3554496171girishnpi_status_t
3564496171girishnpi_ipp_get_pfifo_wr_ptr(npi_handle_t handle, uint8_t portn, uint16_t *wr_ptr)
3574496171girish{
3584496171girish	uint64_t value;
359a3c5bd6speer
360a3c5bd6speer	ASSERT(IS_PORT_NUM_VALID(portn));
3614496171girish
3624496171girish	IPP_REG_RD(handle, portn, IPP_PFIFO_WR_PTR_REG, &value);
3634496171girish	*wr_ptr = value & 0xfff;
3644496171girish	return (NPI_SUCCESS);
3654496171girish}
3664496171girish
3674496171girishnpi_status_t
3684496171girishnpi_ipp_get_dfifo_rd_ptr(npi_handle_t handle, uint8_t portn, uint16_t *rd_ptr)
3694496171girish{
3704496171girish	uint64_t value;
371a3c5bd6speer
372a3c5bd6speer	ASSERT(IS_PORT_NUM_VALID(portn));
3734496171girish
3744496171girish	IPP_REG_RD(handle, portn, IPP_DFIFO_RD_PTR_REG, &value);
3754496171girish	*rd_ptr = (uint16_t)(value & ((portn < 2) ? IPP_XMAC_DFIFO_PTR_MASK :
37652ccf84misaki	    IPP_BMAC_DFIFO_PTR_MASK));
3774496171girish	return (NPI_SUCCESS);
3784496171girish}
3794496171girish
3804496171girishnpi_status_t
3814496171girishnpi_ipp_get_dfifo_wr_ptr(npi_handle_t handle, uint8_t portn, uint16_t *wr_ptr)
3824496171girish{
3834496171girish	uint64_t value;
384a3c5bd6speer
385a3c5bd6speer	ASSERT(IS_PORT_NUM_VALID(portn));
3864496171girish
3874496171girish	IPP_REG_RD(handle, portn, IPP_DFIFO_WR_PTR_REG, &value);
3884496171girish	*wr_ptr = (uint16_t)(value & ((portn < 2) ? IPP_XMAC_DFIFO_PTR_MASK :
38952ccf84misaki	    IPP_BMAC_DFIFO_PTR_MASK));
3904496171girish	return (NPI_SUCCESS);
3914496171girish}
3924496171girish
3934496171girishnpi_status_t
3944496171girishnpi_ipp_write_pfifo(npi_handle_t handle, uint8_t portn, uint8_t addr,
3954496171girish		uint32_t d0, uint32_t d1, uint32_t d2, uint32_t d3, uint32_t d4)
3964496171girish{
3974496171girish	uint64_t val;
3984496171girish
399a3c5bd6speer	ASSERT(IS_PORT_NUM_VALID(portn));
4004496171girish
4014496171girish	if (addr >= 64) {
4024496171girish		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
40352ccf84misaki		    " npi_ipp_write_pfifo"
40452ccf84misaki		    " Invalid PFIFO address <0x%x>", addr));
4054496171girish		return (NPI_FAILURE | NPI_IPP_FIFO_ADDR_INVALID(portn));
4064496171girish	}
4074496171girish
4084496171girish	IPP_REG_RD(handle, portn, IPP_CONFIG_REG, &val);
4094496171girish	val |= IPP_PRE_FIFO_PIO_WR_EN;
4104496171girish	IPP_REG_WR(handle, portn, IPP_CONFIG_REG, val);
4114496171girish
4124496171girish	IPP_REG_WR(handle, portn, IPP_PFIFO_WR_PTR_REG, addr);
4134496171girish	IPP_REG_WR(handle, portn, IPP_PFIFO_WR_DATA0_REG, d0);
4144496171girish	IPP_REG_WR(handle, portn, IPP_PFIFO_WR_DATA1_REG, d1);
4154496171girish	IPP_REG_WR(handle, portn, IPP_PFIFO_WR_DATA2_REG, d2);
4164496171girish	IPP_REG_WR(handle, portn, IPP_PFIFO_WR_DATA3_REG, d3);
4174496171girish	IPP_REG_WR(handle, portn, IPP_PFIFO_WR_DATA4_REG, d4);
4184496171girish
4194496171girish	val &= ~IPP_PRE_FIFO_PIO_WR_EN;
4204496171girish	IPP_REG_WR(handle, portn, IPP_CONFIG_REG, val);
4214496171girish
4224496171girish	return (NPI_SUCCESS);
4234496171girish}
4244496171girish
4254496171girishnpi_status_t
4264496171girishnpi_ipp_read_pfifo(npi_handle_t handle, uint8_t portn, uint8_t addr,
4274496171girish		uint32_t *d0, uint32_t *d1, uint32_t *d2, uint32_t *d3,
4284496171girish		uint32_t *d4)
4294496171girish{
430a3c5bd6speer	ASSERT(IS_PORT_NUM_VALID(portn));
4314496171girish
4324496171girish	if (addr >= 64) {
4334496171girish		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
43452ccf84misaki		    " npi_ipp_read_pfifo"
43552ccf84misaki		    " Invalid PFIFO address <0x%x>", addr));
4364496171girish		return (NPI_FAILURE | NPI_IPP_FIFO_ADDR_INVALID(portn));
4374496171girish	}
4384496171girish
4394496171girish	IPP_REG_WR(handle, portn, IPP_PFIFO_RD_PTR_REG, addr);
4404496171girish	IPP_REG_RD(handle, portn, IPP_PFIFO_RD_DATA0_REG, d0);
4414496171girish	IPP_REG_RD(handle, portn, IPP_PFIFO_RD_DATA1_REG, d1);
4424496171girish	IPP_REG_RD(handle, portn, IPP_PFIFO_RD_DATA2_REG, d2);
4434496171girish	IPP_REG_RD(handle, portn, IPP_PFIFO_RD_DATA3_REG, d3);
4444496171girish	IPP_REG_RD(handle, portn, IPP_PFIFO_RD_DATA4_REG, d4);
4454496171girish
4464496171girish	return (NPI_SUCCESS);
4474496171girish}
4484496171girish
4494496171girishnpi_status_t
4504496171girishnpi_ipp_write_dfifo(npi_handle_t handle, uint8_t portn, uint16_t addr,
4514496171girish		uint32_t d0, uint32_t d1, uint32_t d2, uint32_t d3, uint32_t d4)
4524496171girish{
4534496171girish	uint64_t val;
4544496171girish
455a3c5bd6speer	ASSERT(IS_PORT_NUM_VALID(portn));
4564496171girish
4574496171girish	if (addr >= 2048) {
4584496171girish		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
45952ccf84misaki		    " npi_ipp_write_dfifo"
46052ccf84misaki		    " Invalid DFIFO address <0x%x>", addr));
4614496171girish		return (NPI_FAILURE | NPI_IPP_FIFO_ADDR_INVALID(portn));
4624496171girish	}
4634496171girish
4644496171girish	IPP_REG_RD(handle, portn, IPP_CONFIG_REG, &val);
4654496171girish	val |= IPP_DFIFO_PIO_WR_EN;
4664496171girish	IPP_REG_WR(handle, portn, IPP_CONFIG_REG, val);
4674496171girish
4684496171girish	IPP_REG_WR(handle, portn, IPP_DFIFO_WR_PTR_REG, addr);
4694496171girish	IPP_REG_WR(handle, portn, IPP_DFIFO_WR_DATA0_REG, d0);
4704496171girish	IPP_REG_WR(handle, portn, IPP_DFIFO_WR_DATA1_REG, d1);
4714496171girish	IPP_REG_WR(handle, portn, IPP_DFIFO_WR_DATA2_REG, d2);
4724496171girish	IPP_REG_WR(handle, portn, IPP_DFIFO_WR_DATA3_REG, d3);
4734496171girish	IPP_REG_WR(handle, portn, IPP_DFIFO_WR_DATA4_REG, d4);
4744496171girish
4754496171girish	val &= ~IPP_DFIFO_PIO_WR_EN;
4764496171girish	IPP_REG_WR(handle, portn, IPP_CONFIG_REG, val);
4774496171girish
4784496171girish	return (NPI_SUCCESS);
4794496171girish}
4804496171girish
4814496171girishnpi_status_t
4824496171girishnpi_ipp_read_dfifo(npi_handle_t handle, uint8_t portn, uint16_t addr,
4834496171girish		uint32_t *d0, uint32_t *d1, uint32_t *d2, uint32_t *d3,
4844496171girish		uint32_t *d4)
4854496171girish{
486a3c5bd6speer	ASSERT(IS_PORT_NUM_VALID(portn));
4874496171girish
4884496171girish	if (addr >= 2048) {
4894496171girish		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
49052ccf84misaki		    " npi_ipp_read_dfifo"
49152ccf84misaki		    " Invalid DFIFO address <0x%x>", addr));
4924496171girish		return (NPI_FAILURE | NPI_IPP_FIFO_ADDR_INVALID(portn));
4934496171girish	}
4944496171girish
4954496171girish	IPP_REG_WR(handle, portn, IPP_DFIFO_RD_PTR_REG, addr);
4964496171girish	IPP_REG_RD(handle, portn, IPP_DFIFO_RD_DATA0_REG, d0);
4974496171girish	IPP_REG_RD(handle, portn, IPP_DFIFO_RD_DATA1_REG, d1);
4984496171girish	IPP_REG_RD(handle, portn, IPP_DFIFO_RD_DATA2_REG, d2);
4994496171girish	IPP_REG_RD(handle, portn, IPP_DFIFO_RD_DATA3_REG, d3);
5004496171girish	IPP_REG_RD(handle, portn, IPP_DFIFO_RD_DATA4_REG, d4);
5014496171girish
5024496171girish	return (NPI_SUCCESS);
5034496171girish}
5044496171girish
5054496171girishnpi_status_t
5064496171girishnpi_ipp_get_ecc_syndrome(npi_handle_t handle, uint8_t portn, uint16_t *syndrome)
5074496171girish{
5084496171girish	uint64_t val;
5094496171girish
510a3c5bd6speer	ASSERT(IS_PORT_NUM_VALID(portn));
5114496171girish
5124496171girish	IPP_REG_RD(handle, portn, IPP_DFIFO_ECC_SYNDROME_REG, &val);
5134496171girish
5144496171girish	*syndrome = (uint16_t)val;
5154496171girish	return (NPI_SUCCESS);
5164496171girish}
5174496171girish
5184496171girishnpi_status_t
5194496171girishnpi_ipp_get_dfifo_eopm_rdptr(npi_handle_t handle, uint8_t portn,
5204496171girish							uint16_t *rdptr)
5214496171girish{
5224496171girish	uint64_t val;
5234496171girish
524a3c5bd6speer	ASSERT(IS_PORT_NUM_VALID(portn));
5254496171girish
5264496171girish	IPP_REG_RD(handle, portn, IPP_DFIFO_EOPM_RD_PTR_REG, &val);
5274496171girish
5284496171girish	*rdptr = (uint16_t)val;
5294496171girish	return (NPI_SUCCESS);
5304496171girish}
5314496171girish
5324496171girishnpi_status_t
5334496171girishnpi_ipp_get_state_mach(npi_handle_t handle, uint8_t portn, uint32_t *sm)
5344496171girish{
5354496171girish	uint64_t val;
5364496171girish
537a3c5bd6speer	ASSERT(IS_PORT_NUM_VALID(portn));
5384496171girish
5394496171girish	IPP_REG_RD(handle, portn, IPP_STATE_MACHINE_REG, &val);
5404496171girish
5414496171girish	*sm = (uint32_t)val;
5424496171girish	return (NPI_SUCCESS);
5434496171girish}
5444496171girish
5454496171girishnpi_status_t
5464496171girishnpi_ipp_get_ecc_err_count(npi_handle_t handle, uint8_t portn, uint8_t *err_cnt)
5474496171girish{
548a3c5bd6speer	ASSERT(IS_PORT_NUM_VALID(portn));
5494496171girish
5504496171girish	IPP_REG_RD(handle, portn, IPP_ECC_ERR_COUNTER_REG, err_cnt);
5514496171girish
5524496171girish	return (NPI_SUCCESS);
5534496171girish}
5544496171girish
5554496171girishnpi_status_t
5564496171girishnpi_ipp_get_pkt_dis_count(npi_handle_t handle, uint8_t portn, uint16_t *dis_cnt)
5574496171girish{
558a3c5bd6speer	ASSERT(IS_PORT_NUM_VALID(portn));
5594496171girish
5604496171girish	IPP_REG_RD(handle, portn, IPP_DISCARD_PKT_CNT_REG, dis_cnt);
5614496171girish
5624496171girish	return (NPI_SUCCESS);
5634496171girish}
5644496171girish
5654496171girishnpi_status_t
5664496171girishnpi_ipp_get_cs_err_count(npi_handle_t handle, uint8_t portn, uint16_t *err_cnt)
5674496171girish{
568a3c5bd6speer	ASSERT(IS_PORT_NUM_VALID(portn));
5694496171girish
570f6485eeyc	IPP_REG_RD(handle, portn, IPP_BAD_CKSUM_ERR_CNT_REG, err_cnt);
5714496171girish
5724496171girish	return (NPI_SUCCESS);
5734496171girish}
574