xref: /illumos-gate/usr/src/uts/common/io/nxge/npi/npi_ipp.c (revision 86ef0a63)
144961713Sgirish /*
244961713Sgirish  * CDDL HEADER START
344961713Sgirish  *
444961713Sgirish  * The contents of this file are subject to the terms of the
544961713Sgirish  * Common Development and Distribution License (the "License").
644961713Sgirish  * You may not use this file except in compliance with the License.
744961713Sgirish  *
844961713Sgirish  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
944961713Sgirish  * or http://www.opensolaris.org/os/licensing.
1044961713Sgirish  * See the License for the specific language governing permissions
1144961713Sgirish  * and limitations under the License.
1244961713Sgirish  *
1344961713Sgirish  * When distributing Covered Code, include this CDDL HEADER in each
1444961713Sgirish  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1544961713Sgirish  * If applicable, add the following below this CDDL HEADER, with the
1644961713Sgirish  * fields enclosed by brackets "[]" replaced with your own identifying
1744961713Sgirish  * information: Portions Copyright [yyyy] [name of copyright owner]
1844961713Sgirish  *
1944961713Sgirish  * CDDL HEADER END
2044961713Sgirish  */
2144961713Sgirish /*
2252ccf843Smisaki  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
2344961713Sgirish  * Use is subject to license terms.
2444961713Sgirish  */
2544961713Sgirish 
2644961713Sgirish #include <npi_ipp.h>
2744961713Sgirish 
2844961713Sgirish uint64_t ipp_fzc_offset[] = {
2944961713Sgirish 		IPP_CONFIG_REG,
3044961713Sgirish 		IPP_DISCARD_PKT_CNT_REG,
31f6485eecSyc 		IPP_BAD_CKSUM_ERR_CNT_REG,
3244961713Sgirish 		IPP_ECC_ERR_COUNTER_REG,
3344961713Sgirish 		IPP_INT_STATUS_REG,
3444961713Sgirish 		IPP_INT_MASK_REG,
3544961713Sgirish 		IPP_PFIFO_RD_DATA0_REG,
3644961713Sgirish 		IPP_PFIFO_RD_DATA1_REG,
3744961713Sgirish 		IPP_PFIFO_RD_DATA2_REG,
3844961713Sgirish 		IPP_PFIFO_RD_DATA3_REG,
3944961713Sgirish 		IPP_PFIFO_RD_DATA4_REG,
4044961713Sgirish 		IPP_PFIFO_WR_DATA0_REG,
4144961713Sgirish 		IPP_PFIFO_WR_DATA1_REG,
4244961713Sgirish 		IPP_PFIFO_WR_DATA2_REG,
4344961713Sgirish 		IPP_PFIFO_WR_DATA3_REG,
4444961713Sgirish 		IPP_PFIFO_WR_DATA4_REG,
4544961713Sgirish 		IPP_PFIFO_RD_PTR_REG,
4644961713Sgirish 		IPP_PFIFO_WR_PTR_REG,
4744961713Sgirish 		IPP_DFIFO_RD_DATA0_REG,
4844961713Sgirish 		IPP_DFIFO_RD_DATA1_REG,
4944961713Sgirish 		IPP_DFIFO_RD_DATA2_REG,
5044961713Sgirish 		IPP_DFIFO_RD_DATA3_REG,
5144961713Sgirish 		IPP_DFIFO_RD_DATA4_REG,
5244961713Sgirish 		IPP_DFIFO_WR_DATA0_REG,
5344961713Sgirish 		IPP_DFIFO_WR_DATA1_REG,
5444961713Sgirish 		IPP_DFIFO_WR_DATA2_REG,
5544961713Sgirish 		IPP_DFIFO_WR_DATA3_REG,
5644961713Sgirish 		IPP_DFIFO_WR_DATA4_REG,
5744961713Sgirish 		IPP_DFIFO_RD_PTR_REG,
5844961713Sgirish 		IPP_DFIFO_WR_PTR_REG,
5944961713Sgirish 		IPP_STATE_MACHINE_REG,
6044961713Sgirish 		IPP_CKSUM_STATUS_REG,
6144961713Sgirish 		IPP_FFLP_CKSUM_INFO_REG,
6244961713Sgirish 		IPP_DEBUG_SELECT_REG,
6344961713Sgirish 		IPP_DFIFO_ECC_SYNDROME_REG,
6444961713Sgirish 		IPP_DFIFO_EOPM_RD_PTR_REG,
6544961713Sgirish 		IPP_ECC_CTRL_REG
6644961713Sgirish };
6744961713Sgirish 
6844961713Sgirish const char *ipp_fzc_name[] = {
6944961713Sgirish 		"IPP_CONFIG_REG",
7044961713Sgirish 		"IPP_DISCARD_PKT_CNT_REG",
71f6485eecSyc 		"IPP_BAD_CKSUM_ERR_CNT_REG",
7244961713Sgirish 		"IPP_ECC_ERR_COUNTER_REG",
7344961713Sgirish 		"IPP_INT_STATUS_REG",
7444961713Sgirish 		"IPP_INT_MASK_REG",
7544961713Sgirish 		"IPP_PFIFO_RD_DATA0_REG",
7644961713Sgirish 		"IPP_PFIFO_RD_DATA1_REG",
7744961713Sgirish 		"IPP_PFIFO_RD_DATA2_REG",
7844961713Sgirish 		"IPP_PFIFO_RD_DATA3_REG",
7944961713Sgirish 		"IPP_PFIFO_RD_DATA4_REG",
8044961713Sgirish 		"IPP_PFIFO_WR_DATA0_REG",
8144961713Sgirish 		"IPP_PFIFO_WR_DATA1_REG",
8244961713Sgirish 		"IPP_PFIFO_WR_DATA2_REG",
8344961713Sgirish 		"IPP_PFIFO_WR_DATA3_REG",
8444961713Sgirish 		"IPP_PFIFO_WR_DATA4_REG",
8544961713Sgirish 		"IPP_PFIFO_RD_PTR_REG",
8644961713Sgirish 		"IPP_PFIFO_WR_PTR_REG",
8744961713Sgirish 		"IPP_DFIFO_RD_DATA0_REG",
8844961713Sgirish 		"IPP_DFIFO_RD_DATA1_REG",
8944961713Sgirish 		"IPP_DFIFO_RD_DATA2_REG",
9044961713Sgirish 		"IPP_DFIFO_RD_DATA3_REG",
9144961713Sgirish 		"IPP_DFIFO_RD_DATA4_REG",
9244961713Sgirish 		"IPP_DFIFO_WR_DATA0_REG",
9344961713Sgirish 		"IPP_DFIFO_WR_DATA1_REG",
9444961713Sgirish 		"IPP_DFIFO_WR_DATA2_REG",
9544961713Sgirish 		"IPP_DFIFO_WR_DATA3_REG",
9644961713Sgirish 		"IPP_DFIFO_WR_DATA4_REG",
9744961713Sgirish 		"IPP_DFIFO_RD_PTR_REG",
9844961713Sgirish 		"IPP_DFIFO_WR_PTR_REG",
9944961713Sgirish 		"IPP_STATE_MACHINE_REG",
10044961713Sgirish 		"IPP_CKSUM_STATUS_REG",
10144961713Sgirish 		"IPP_FFLP_CKSUM_INFO_REG",
10244961713Sgirish 		"IPP_DEBUG_SELECT_REG",
10344961713Sgirish 		"IPP_DFIFO_ECC_SYNDROME_REG",
10444961713Sgirish 		"IPP_DFIFO_EOPM_RD_PTR_REG",
10544961713Sgirish 		"IPP_ECC_CTRL_REG",
10644961713Sgirish };
10744961713Sgirish 
10844961713Sgirish npi_status_t
npi_ipp_dump_regs(npi_handle_t handle,uint8_t port)10944961713Sgirish npi_ipp_dump_regs(npi_handle_t handle, uint8_t port)
11044961713Sgirish {
11144961713Sgirish 	uint64_t		value, offset;
112*86ef0a63SRichard Lowe 	int			num_regs, i;
11344961713Sgirish 
114a3c5bd6dSspeer 	ASSERT(IS_PORT_NUM_VALID(port));
11544961713Sgirish 
11644961713Sgirish 	NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
11752ccf843Smisaki 	    "\nIPP PORT Register Dump for port %d\n", port));
11844961713Sgirish 
11944961713Sgirish 	num_regs = sizeof (ipp_fzc_offset) / sizeof (uint64_t);
12044961713Sgirish 	for (i = 0; i < num_regs; i++) {
12144961713Sgirish 		offset = IPP_REG_ADDR(port, ipp_fzc_offset[i]);
12244961713Sgirish 		NXGE_REG_RD64(handle, offset, &value);
12344961713Sgirish 		NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, "0x%08llx "
12452ccf843Smisaki 		    "%s\t 0x%08llx \n",
12552ccf843Smisaki 		    offset, ipp_fzc_name[i], value));
12644961713Sgirish 	}
12744961713Sgirish 
12844961713Sgirish 	NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL,
12952ccf843Smisaki 	    "\n IPP FZC Register Dump for port %d done\n", port));
13044961713Sgirish 
13144961713Sgirish 	return (NPI_SUCCESS);
13244961713Sgirish }
13344961713Sgirish 
13444961713Sgirish void
npi_ipp_read_regs(npi_handle_t handle,uint8_t port)13544961713Sgirish npi_ipp_read_regs(npi_handle_t handle, uint8_t port)
13644961713Sgirish {
13744961713Sgirish 	uint64_t		value, offset;
138*86ef0a63SRichard Lowe 	int			num_regs, i;
13944961713Sgirish 
140a3c5bd6dSspeer 	ASSERT(IS_PORT_NUM_VALID(port));
14144961713Sgirish 
14244961713Sgirish 	NPI_DEBUG_MSG((handle.function, NPI_IPP_CTL,
14352ccf843Smisaki 	    "\nIPP PORT Register read (to clear) for port %d\n", port));
14444961713Sgirish 
14544961713Sgirish 	num_regs = sizeof (ipp_fzc_offset) / sizeof (uint64_t);
14644961713Sgirish 	for (i = 0; i < num_regs; i++) {
14744961713Sgirish 		offset = IPP_REG_ADDR(port, ipp_fzc_offset[i]);
14844961713Sgirish 		NXGE_REG_RD64(handle, offset, &value);
14944961713Sgirish 	}
15044961713Sgirish 
15144961713Sgirish }
15244961713Sgirish 
153a3c5bd6dSspeer /*
154a3c5bd6dSspeer  * IPP Reset Routine
155a3c5bd6dSspeer  */
15644961713Sgirish npi_status_t
npi_ipp_reset(npi_handle_t handle,uint8_t portn)15744961713Sgirish npi_ipp_reset(npi_handle_t handle, uint8_t portn)
15844961713Sgirish {
15944961713Sgirish 	uint64_t val = 0;
16044961713Sgirish 	uint32_t cnt = MAX_PIO_RETRIES;
16144961713Sgirish 
162a3c5bd6dSspeer 	ASSERT(IS_PORT_NUM_VALID(portn));
16344961713Sgirish 
16444961713Sgirish 	IPP_REG_RD(handle, portn, IPP_CONFIG_REG, &val);
16544961713Sgirish 	val |= IPP_SOFT_RESET;
16644961713Sgirish 	IPP_REG_WR(handle, portn, IPP_CONFIG_REG, val);
16744961713Sgirish 
16844961713Sgirish 	do {
16944961713Sgirish 		NXGE_DELAY(IPP_RESET_WAIT);
17044961713Sgirish 		IPP_REG_RD(handle, portn, IPP_CONFIG_REG, &val);
17144961713Sgirish 		cnt--;
17244961713Sgirish 	} while (((val & IPP_SOFT_RESET) != 0) && (cnt > 0));
17344961713Sgirish 
17444961713Sgirish 	if (cnt == 0) {
17544961713Sgirish 		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
17652ccf843Smisaki 		    " npi_ipp_reset"
17752ccf843Smisaki 		    " HW Error: IPP_RESET  <0x%x>", val));
17844961713Sgirish 		return (NPI_FAILURE | NPI_IPP_RESET_FAILED(portn));
17944961713Sgirish 	}
18044961713Sgirish 
18144961713Sgirish 	return (NPI_SUCCESS);
18244961713Sgirish }
18344961713Sgirish 
18444961713Sgirish 
185a3c5bd6dSspeer /*
186a3c5bd6dSspeer  * IPP Configuration Routine
187a3c5bd6dSspeer  */
18844961713Sgirish npi_status_t
npi_ipp_config(npi_handle_t handle,config_op_t op,uint8_t portn,ipp_config_t config)18944961713Sgirish npi_ipp_config(npi_handle_t handle, config_op_t op, uint8_t portn,
190*86ef0a63SRichard Lowe     ipp_config_t config)
19144961713Sgirish {
19244961713Sgirish 	uint64_t val = 0;
19344961713Sgirish 
194a3c5bd6dSspeer 	ASSERT(IS_PORT_NUM_VALID(portn));
19544961713Sgirish 
19644961713Sgirish 	switch (op) {
19744961713Sgirish 
19844961713Sgirish 	case ENABLE:
19944961713Sgirish 	case DISABLE:
20044961713Sgirish 		if ((config == 0) || ((config & ~CFG_IPP_ALL) != 0)) {
20144961713Sgirish 			NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
20252ccf843Smisaki 			    " npi_ipp_config",
20352ccf843Smisaki 			    " Invalid Input config <0x%x>",
20452ccf843Smisaki 			    config));
20544961713Sgirish 			return (NPI_FAILURE | NPI_IPP_CONFIG_INVALID(portn));
20644961713Sgirish 		}
20744961713Sgirish 
20844961713Sgirish 		IPP_REG_RD(handle, portn, IPP_CONFIG_REG, &val);
20944961713Sgirish 
21044961713Sgirish 		if (op == ENABLE)
21144961713Sgirish 			val |= config;
21244961713Sgirish 		else
21344961713Sgirish 			val &= ~config;
21444961713Sgirish 		break;
21544961713Sgirish 
21644961713Sgirish 	case INIT:
21744961713Sgirish 		if ((config & ~CFG_IPP_ALL) != 0) {
21844961713Sgirish 			NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
21952ccf843Smisaki 			    " npi_ipp_config"
22052ccf843Smisaki 			    " Invalid Input config <0x%x>",
22152ccf843Smisaki 			    config));
22244961713Sgirish 			return (NPI_FAILURE | NPI_IPP_CONFIG_INVALID(portn));
22344961713Sgirish 		}
22444961713Sgirish 		IPP_REG_RD(handle, portn, IPP_CONFIG_REG, &val);
22544961713Sgirish 
22644961713Sgirish 
22744961713Sgirish 		val &= (IPP_IP_MAX_PKT_BYTES_MASK);
22844961713Sgirish 		val |= config;
22944961713Sgirish 		break;
23044961713Sgirish 
23144961713Sgirish 	default:
23244961713Sgirish 		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
23352ccf843Smisaki 		    " npi_ipp_config"
23452ccf843Smisaki 		    " Invalid Input op <0x%x>", op));
23544961713Sgirish 		return (NPI_FAILURE | NPI_IPP_OPCODE_INVALID(portn));
23644961713Sgirish 	}
23744961713Sgirish 
23844961713Sgirish 	IPP_REG_WR(handle, portn, IPP_CONFIG_REG, val);
23944961713Sgirish 	return (NPI_SUCCESS);
24044961713Sgirish }
24144961713Sgirish 
24244961713Sgirish npi_status_t
npi_ipp_set_max_pktsize(npi_handle_t handle,uint8_t portn,uint32_t bytes)24344961713Sgirish npi_ipp_set_max_pktsize(npi_handle_t handle, uint8_t portn, uint32_t bytes)
24444961713Sgirish {
24544961713Sgirish 	uint64_t val = 0;
24644961713Sgirish 
247a3c5bd6dSspeer 	ASSERT(IS_PORT_NUM_VALID(portn));
24844961713Sgirish 
24944961713Sgirish 	if (bytes > IPP_IP_MAX_PKT_BYTES_MASK) {
25044961713Sgirish 		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
25152ccf843Smisaki 		    " npi_ipp_set_max_pktsize"
25252ccf843Smisaki 		    " Invalid Input Max bytes <0x%x>",
25352ccf843Smisaki 		    bytes));
25444961713Sgirish 		return (NPI_FAILURE | NPI_IPP_MAX_PKT_BYTES_INVALID(portn));
25544961713Sgirish 	}
25644961713Sgirish 
25744961713Sgirish 	IPP_REG_RD(handle, portn, IPP_CONFIG_REG, &val);
25844961713Sgirish 	val &= ~(IPP_IP_MAX_PKT_BYTES_MASK << IPP_IP_MAX_PKT_BYTES_SHIFT);
25944961713Sgirish 
26044961713Sgirish 	val |= (bytes << IPP_IP_MAX_PKT_BYTES_SHIFT);
26144961713Sgirish 	IPP_REG_WR(handle, portn, IPP_CONFIG_REG, val);
26244961713Sgirish 
26344961713Sgirish 	return (NPI_SUCCESS);
26444961713Sgirish }
26544961713Sgirish 
266a3c5bd6dSspeer /*
267a3c5bd6dSspeer  * IPP Interrupt Configuration Routine
268a3c5bd6dSspeer  */
26944961713Sgirish npi_status_t
npi_ipp_iconfig(npi_handle_t handle,config_op_t op,uint8_t portn,ipp_iconfig_t iconfig)27044961713Sgirish npi_ipp_iconfig(npi_handle_t handle, config_op_t op, uint8_t portn,
271*86ef0a63SRichard Lowe     ipp_iconfig_t iconfig)
27244961713Sgirish {
27344961713Sgirish 	uint64_t val = 0;
27444961713Sgirish 
275a3c5bd6dSspeer 	ASSERT(IS_PORT_NUM_VALID(portn));
27644961713Sgirish 
27744961713Sgirish 	switch (op) {
27844961713Sgirish 	case ENABLE:
27944961713Sgirish 	case DISABLE:
28044961713Sgirish 
28144961713Sgirish 		if ((iconfig == 0) || ((iconfig & ~ICFG_IPP_ALL) != 0)) {
28244961713Sgirish 			NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
28352ccf843Smisaki 			    " npi_ipp_iconfig"
28452ccf843Smisaki 			    " Invalid Input iconfig <0x%x>",
28552ccf843Smisaki 			    iconfig));
28644961713Sgirish 			return (NPI_FAILURE | NPI_IPP_CONFIG_INVALID(portn));
28744961713Sgirish 		}
28844961713Sgirish 
28944961713Sgirish 		IPP_REG_RD(handle, portn, IPP_INT_MASK_REG, &val);
29044961713Sgirish 		if (op == ENABLE)
29144961713Sgirish 			val &= ~iconfig;
29244961713Sgirish 		else
29344961713Sgirish 			val |= iconfig;
29444961713Sgirish 		IPP_REG_WR(handle, portn, IPP_INT_MASK_REG, val);
29544961713Sgirish 
29644961713Sgirish 		break;
29744961713Sgirish 	case INIT:
29844961713Sgirish 
29944961713Sgirish 		if ((iconfig & ~ICFG_IPP_ALL) != 0) {
30044961713Sgirish 			NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
30152ccf843Smisaki 			    " npi_ipp_iconfig"
30252ccf843Smisaki 			    " Invalid Input iconfig <0x%x>",
30352ccf843Smisaki 			    iconfig));
30444961713Sgirish 			return (NPI_FAILURE | NPI_IPP_CONFIG_INVALID(portn));
30544961713Sgirish 		}
30644961713Sgirish 		IPP_REG_WR(handle, portn, IPP_INT_MASK_REG, ~iconfig);
30744961713Sgirish 
30844961713Sgirish 		break;
30944961713Sgirish 	default:
31044961713Sgirish 		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
31152ccf843Smisaki 		    " npi_ipp_iconfig"
31252ccf843Smisaki 		    " Invalid Input iconfig <0x%x>",
31352ccf843Smisaki 		    iconfig));
31444961713Sgirish 		return (NPI_FAILURE | NPI_IPP_OPCODE_INVALID(portn));
31544961713Sgirish 	}
31644961713Sgirish 
31744961713Sgirish 	return (NPI_SUCCESS);
31844961713Sgirish }
31944961713Sgirish 
32044961713Sgirish npi_status_t
npi_ipp_get_status(npi_handle_t handle,uint8_t portn,ipp_status_t * status)32144961713Sgirish npi_ipp_get_status(npi_handle_t handle, uint8_t portn, ipp_status_t *status)
32244961713Sgirish {
32344961713Sgirish 	uint64_t val;
32444961713Sgirish 
325a3c5bd6dSspeer 	ASSERT(IS_PORT_NUM_VALID(portn));
32644961713Sgirish 
32744961713Sgirish 	IPP_REG_RD(handle, portn, IPP_INT_STATUS_REG, &val);
32844961713Sgirish 
32944961713Sgirish 	status->value = val;
33044961713Sgirish 	return (NPI_SUCCESS);
33144961713Sgirish }
33244961713Sgirish 
33344961713Sgirish npi_status_t
npi_ipp_get_pfifo_rd_ptr(npi_handle_t handle,uint8_t portn,uint16_t * rd_ptr)33444961713Sgirish npi_ipp_get_pfifo_rd_ptr(npi_handle_t handle, uint8_t portn, uint16_t *rd_ptr)
33544961713Sgirish {
33644961713Sgirish 	uint64_t value;
337a3c5bd6dSspeer 
338a3c5bd6dSspeer 	ASSERT(IS_PORT_NUM_VALID(portn));
33944961713Sgirish 
34044961713Sgirish 	IPP_REG_RD(handle, portn, IPP_PFIFO_RD_PTR_REG, &value);
34144961713Sgirish 	*rd_ptr = value & 0xfff;
34244961713Sgirish 	return (NPI_SUCCESS);
34344961713Sgirish }
34444961713Sgirish 
34544961713Sgirish npi_status_t
npi_ipp_get_pfifo_wr_ptr(npi_handle_t handle,uint8_t portn,uint16_t * wr_ptr)34644961713Sgirish npi_ipp_get_pfifo_wr_ptr(npi_handle_t handle, uint8_t portn, uint16_t *wr_ptr)
34744961713Sgirish {
34844961713Sgirish 	uint64_t value;
349a3c5bd6dSspeer 
350a3c5bd6dSspeer 	ASSERT(IS_PORT_NUM_VALID(portn));
35144961713Sgirish 
35244961713Sgirish 	IPP_REG_RD(handle, portn, IPP_PFIFO_WR_PTR_REG, &value);
35344961713Sgirish 	*wr_ptr = value & 0xfff;
35444961713Sgirish 	return (NPI_SUCCESS);
35544961713Sgirish }
35644961713Sgirish 
35744961713Sgirish npi_status_t
npi_ipp_get_dfifo_rd_ptr(npi_handle_t handle,uint8_t portn,uint16_t * rd_ptr)35844961713Sgirish npi_ipp_get_dfifo_rd_ptr(npi_handle_t handle, uint8_t portn, uint16_t *rd_ptr)
35944961713Sgirish {
36044961713Sgirish 	uint64_t value;
361a3c5bd6dSspeer 
362a3c5bd6dSspeer 	ASSERT(IS_PORT_NUM_VALID(portn));
36344961713Sgirish 
36444961713Sgirish 	IPP_REG_RD(handle, portn, IPP_DFIFO_RD_PTR_REG, &value);
36544961713Sgirish 	*rd_ptr = (uint16_t)(value & ((portn < 2) ? IPP_XMAC_DFIFO_PTR_MASK :
36652ccf843Smisaki 	    IPP_BMAC_DFIFO_PTR_MASK));
36744961713Sgirish 	return (NPI_SUCCESS);
36844961713Sgirish }
36944961713Sgirish 
37044961713Sgirish npi_status_t
npi_ipp_get_dfifo_wr_ptr(npi_handle_t handle,uint8_t portn,uint16_t * wr_ptr)37144961713Sgirish npi_ipp_get_dfifo_wr_ptr(npi_handle_t handle, uint8_t portn, uint16_t *wr_ptr)
37244961713Sgirish {
37344961713Sgirish 	uint64_t value;
374a3c5bd6dSspeer 
375a3c5bd6dSspeer 	ASSERT(IS_PORT_NUM_VALID(portn));
37644961713Sgirish 
37744961713Sgirish 	IPP_REG_RD(handle, portn, IPP_DFIFO_WR_PTR_REG, &value);
37844961713Sgirish 	*wr_ptr = (uint16_t)(value & ((portn < 2) ? IPP_XMAC_DFIFO_PTR_MASK :
37952ccf843Smisaki 	    IPP_BMAC_DFIFO_PTR_MASK));
38044961713Sgirish 	return (NPI_SUCCESS);
38144961713Sgirish }
38244961713Sgirish 
38344961713Sgirish npi_status_t
npi_ipp_write_pfifo(npi_handle_t handle,uint8_t portn,uint8_t addr,uint32_t d0,uint32_t d1,uint32_t d2,uint32_t d3,uint32_t d4)38444961713Sgirish npi_ipp_write_pfifo(npi_handle_t handle, uint8_t portn, uint8_t addr,
385*86ef0a63SRichard Lowe     uint32_t d0, uint32_t d1, uint32_t d2, uint32_t d3, uint32_t d4)
38644961713Sgirish {
38744961713Sgirish 	uint64_t val;
38844961713Sgirish 
389a3c5bd6dSspeer 	ASSERT(IS_PORT_NUM_VALID(portn));
39044961713Sgirish 
39144961713Sgirish 	if (addr >= 64) {
39244961713Sgirish 		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
39352ccf843Smisaki 		    " npi_ipp_write_pfifo"
39452ccf843Smisaki 		    " Invalid PFIFO address <0x%x>", addr));
39544961713Sgirish 		return (NPI_FAILURE | NPI_IPP_FIFO_ADDR_INVALID(portn));
39644961713Sgirish 	}
39744961713Sgirish 
39844961713Sgirish 	IPP_REG_RD(handle, portn, IPP_CONFIG_REG, &val);
39944961713Sgirish 	val |= IPP_PRE_FIFO_PIO_WR_EN;
40044961713Sgirish 	IPP_REG_WR(handle, portn, IPP_CONFIG_REG, val);
40144961713Sgirish 
40244961713Sgirish 	IPP_REG_WR(handle, portn, IPP_PFIFO_WR_PTR_REG, addr);
40344961713Sgirish 	IPP_REG_WR(handle, portn, IPP_PFIFO_WR_DATA0_REG, d0);
40444961713Sgirish 	IPP_REG_WR(handle, portn, IPP_PFIFO_WR_DATA1_REG, d1);
40544961713Sgirish 	IPP_REG_WR(handle, portn, IPP_PFIFO_WR_DATA2_REG, d2);
40644961713Sgirish 	IPP_REG_WR(handle, portn, IPP_PFIFO_WR_DATA3_REG, d3);
40744961713Sgirish 	IPP_REG_WR(handle, portn, IPP_PFIFO_WR_DATA4_REG, d4);
40844961713Sgirish 
40944961713Sgirish 	val &= ~IPP_PRE_FIFO_PIO_WR_EN;
41044961713Sgirish 	IPP_REG_WR(handle, portn, IPP_CONFIG_REG, val);
41144961713Sgirish 
41244961713Sgirish 	return (NPI_SUCCESS);
41344961713Sgirish }
41444961713Sgirish 
41544961713Sgirish npi_status_t
npi_ipp_read_pfifo(npi_handle_t handle,uint8_t portn,uint8_t addr,uint32_t * d0,uint32_t * d1,uint32_t * d2,uint32_t * d3,uint32_t * d4)41644961713Sgirish npi_ipp_read_pfifo(npi_handle_t handle, uint8_t portn, uint8_t addr,
417*86ef0a63SRichard Lowe     uint32_t *d0, uint32_t *d1, uint32_t *d2, uint32_t *d3,
418*86ef0a63SRichard Lowe     uint32_t *d4)
41944961713Sgirish {
420a3c5bd6dSspeer 	ASSERT(IS_PORT_NUM_VALID(portn));
42144961713Sgirish 
42244961713Sgirish 	if (addr >= 64) {
42344961713Sgirish 		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
42452ccf843Smisaki 		    " npi_ipp_read_pfifo"
42552ccf843Smisaki 		    " Invalid PFIFO address <0x%x>", addr));
42644961713Sgirish 		return (NPI_FAILURE | NPI_IPP_FIFO_ADDR_INVALID(portn));
42744961713Sgirish 	}
42844961713Sgirish 
42944961713Sgirish 	IPP_REG_WR(handle, portn, IPP_PFIFO_RD_PTR_REG, addr);
43044961713Sgirish 	IPP_REG_RD(handle, portn, IPP_PFIFO_RD_DATA0_REG, d0);
43144961713Sgirish 	IPP_REG_RD(handle, portn, IPP_PFIFO_RD_DATA1_REG, d1);
43244961713Sgirish 	IPP_REG_RD(handle, portn, IPP_PFIFO_RD_DATA2_REG, d2);
43344961713Sgirish 	IPP_REG_RD(handle, portn, IPP_PFIFO_RD_DATA3_REG, d3);
43444961713Sgirish 	IPP_REG_RD(handle, portn, IPP_PFIFO_RD_DATA4_REG, d4);
43544961713Sgirish 
43644961713Sgirish 	return (NPI_SUCCESS);
43744961713Sgirish }
43844961713Sgirish 
43944961713Sgirish npi_status_t
npi_ipp_write_dfifo(npi_handle_t handle,uint8_t portn,uint16_t addr,uint32_t d0,uint32_t d1,uint32_t d2,uint32_t d3,uint32_t d4)44044961713Sgirish npi_ipp_write_dfifo(npi_handle_t handle, uint8_t portn, uint16_t addr,
441*86ef0a63SRichard Lowe     uint32_t d0, uint32_t d1, uint32_t d2, uint32_t d3, uint32_t d4)
44244961713Sgirish {
44344961713Sgirish 	uint64_t val;
44444961713Sgirish 
445a3c5bd6dSspeer 	ASSERT(IS_PORT_NUM_VALID(portn));
44644961713Sgirish 
44744961713Sgirish 	if (addr >= 2048) {
44844961713Sgirish 		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
44952ccf843Smisaki 		    " npi_ipp_write_dfifo"
45052ccf843Smisaki 		    " Invalid DFIFO address <0x%x>", addr));
45144961713Sgirish 		return (NPI_FAILURE | NPI_IPP_FIFO_ADDR_INVALID(portn));
45244961713Sgirish 	}
45344961713Sgirish 
45444961713Sgirish 	IPP_REG_RD(handle, portn, IPP_CONFIG_REG, &val);
45544961713Sgirish 	val |= IPP_DFIFO_PIO_WR_EN;
45644961713Sgirish 	IPP_REG_WR(handle, portn, IPP_CONFIG_REG, val);
45744961713Sgirish 
45844961713Sgirish 	IPP_REG_WR(handle, portn, IPP_DFIFO_WR_PTR_REG, addr);
45944961713Sgirish 	IPP_REG_WR(handle, portn, IPP_DFIFO_WR_DATA0_REG, d0);
46044961713Sgirish 	IPP_REG_WR(handle, portn, IPP_DFIFO_WR_DATA1_REG, d1);
46144961713Sgirish 	IPP_REG_WR(handle, portn, IPP_DFIFO_WR_DATA2_REG, d2);
46244961713Sgirish 	IPP_REG_WR(handle, portn, IPP_DFIFO_WR_DATA3_REG, d3);
46344961713Sgirish 	IPP_REG_WR(handle, portn, IPP_DFIFO_WR_DATA4_REG, d4);
46444961713Sgirish 
46544961713Sgirish 	val &= ~IPP_DFIFO_PIO_WR_EN;
46644961713Sgirish 	IPP_REG_WR(handle, portn, IPP_CONFIG_REG, val);
46744961713Sgirish 
46844961713Sgirish 	return (NPI_SUCCESS);
46944961713Sgirish }
47044961713Sgirish 
47144961713Sgirish npi_status_t
npi_ipp_read_dfifo(npi_handle_t handle,uint8_t portn,uint16_t addr,uint32_t * d0,uint32_t * d1,uint32_t * d2,uint32_t * d3,uint32_t * d4)47244961713Sgirish npi_ipp_read_dfifo(npi_handle_t handle, uint8_t portn, uint16_t addr,
473*86ef0a63SRichard Lowe     uint32_t *d0, uint32_t *d1, uint32_t *d2, uint32_t *d3,
474*86ef0a63SRichard Lowe     uint32_t *d4)
47544961713Sgirish {
476a3c5bd6dSspeer 	ASSERT(IS_PORT_NUM_VALID(portn));
47744961713Sgirish 
47844961713Sgirish 	if (addr >= 2048) {
47944961713Sgirish 		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
48052ccf843Smisaki 		    " npi_ipp_read_dfifo"
48152ccf843Smisaki 		    " Invalid DFIFO address <0x%x>", addr));
48244961713Sgirish 		return (NPI_FAILURE | NPI_IPP_FIFO_ADDR_INVALID(portn));
48344961713Sgirish 	}
48444961713Sgirish 
48544961713Sgirish 	IPP_REG_WR(handle, portn, IPP_DFIFO_RD_PTR_REG, addr);
48644961713Sgirish 	IPP_REG_RD(handle, portn, IPP_DFIFO_RD_DATA0_REG, d0);
48744961713Sgirish 	IPP_REG_RD(handle, portn, IPP_DFIFO_RD_DATA1_REG, d1);
48844961713Sgirish 	IPP_REG_RD(handle, portn, IPP_DFIFO_RD_DATA2_REG, d2);
48944961713Sgirish 	IPP_REG_RD(handle, portn, IPP_DFIFO_RD_DATA3_REG, d3);
49044961713Sgirish 	IPP_REG_RD(handle, portn, IPP_DFIFO_RD_DATA4_REG, d4);
49144961713Sgirish 
49244961713Sgirish 	return (NPI_SUCCESS);
49344961713Sgirish }
49444961713Sgirish 
49544961713Sgirish npi_status_t
npi_ipp_get_ecc_syndrome(npi_handle_t handle,uint8_t portn,uint16_t * syndrome)49644961713Sgirish npi_ipp_get_ecc_syndrome(npi_handle_t handle, uint8_t portn, uint16_t *syndrome)
49744961713Sgirish {
49844961713Sgirish 	uint64_t val;
49944961713Sgirish 
500a3c5bd6dSspeer 	ASSERT(IS_PORT_NUM_VALID(portn));
50144961713Sgirish 
50244961713Sgirish 	IPP_REG_RD(handle, portn, IPP_DFIFO_ECC_SYNDROME_REG, &val);
50344961713Sgirish 
50444961713Sgirish 	*syndrome = (uint16_t)val;
50544961713Sgirish 	return (NPI_SUCCESS);
50644961713Sgirish }
50744961713Sgirish 
50844961713Sgirish npi_status_t
npi_ipp_get_dfifo_eopm_rdptr(npi_handle_t handle,uint8_t portn,uint16_t * rdptr)50944961713Sgirish npi_ipp_get_dfifo_eopm_rdptr(npi_handle_t handle, uint8_t portn,
510*86ef0a63SRichard Lowe     uint16_t *rdptr)
51144961713Sgirish {
51244961713Sgirish 	uint64_t val;
51344961713Sgirish 
514a3c5bd6dSspeer 	ASSERT(IS_PORT_NUM_VALID(portn));
51544961713Sgirish 
51644961713Sgirish 	IPP_REG_RD(handle, portn, IPP_DFIFO_EOPM_RD_PTR_REG, &val);
51744961713Sgirish 
51844961713Sgirish 	*rdptr = (uint16_t)val;
51944961713Sgirish 	return (NPI_SUCCESS);
52044961713Sgirish }
52144961713Sgirish 
52244961713Sgirish npi_status_t
npi_ipp_get_state_mach(npi_handle_t handle,uint8_t portn,uint32_t * sm)52344961713Sgirish npi_ipp_get_state_mach(npi_handle_t handle, uint8_t portn, uint32_t *sm)
52444961713Sgirish {
52544961713Sgirish 	uint64_t val;
52644961713Sgirish 
527a3c5bd6dSspeer 	ASSERT(IS_PORT_NUM_VALID(portn));
52844961713Sgirish 
52944961713Sgirish 	IPP_REG_RD(handle, portn, IPP_STATE_MACHINE_REG, &val);
53044961713Sgirish 
53144961713Sgirish 	*sm = (uint32_t)val;
53244961713Sgirish 	return (NPI_SUCCESS);
53344961713Sgirish }
53444961713Sgirish 
53544961713Sgirish npi_status_t
npi_ipp_get_ecc_err_count(npi_handle_t handle,uint8_t portn,uint8_t * err_cnt)53644961713Sgirish npi_ipp_get_ecc_err_count(npi_handle_t handle, uint8_t portn, uint8_t *err_cnt)
53744961713Sgirish {
538a3c5bd6dSspeer 	ASSERT(IS_PORT_NUM_VALID(portn));
53944961713Sgirish 
54044961713Sgirish 	IPP_REG_RD(handle, portn, IPP_ECC_ERR_COUNTER_REG, err_cnt);
54144961713Sgirish 
54244961713Sgirish 	return (NPI_SUCCESS);
54344961713Sgirish }
54444961713Sgirish 
54544961713Sgirish npi_status_t
npi_ipp_get_pkt_dis_count(npi_handle_t handle,uint8_t portn,uint16_t * dis_cnt)54644961713Sgirish npi_ipp_get_pkt_dis_count(npi_handle_t handle, uint8_t portn, uint16_t *dis_cnt)
54744961713Sgirish {
548a3c5bd6dSspeer 	ASSERT(IS_PORT_NUM_VALID(portn));
54944961713Sgirish 
55044961713Sgirish 	IPP_REG_RD(handle, portn, IPP_DISCARD_PKT_CNT_REG, dis_cnt);
55144961713Sgirish 
55244961713Sgirish 	return (NPI_SUCCESS);
55344961713Sgirish }
55444961713Sgirish 
55544961713Sgirish npi_status_t
npi_ipp_get_cs_err_count(npi_handle_t handle,uint8_t portn,uint16_t * err_cnt)55644961713Sgirish npi_ipp_get_cs_err_count(npi_handle_t handle, uint8_t portn, uint16_t *err_cnt)
55744961713Sgirish {
558a3c5bd6dSspeer 	ASSERT(IS_PORT_NUM_VALID(portn));
55944961713Sgirish 
560f6485eecSyc 	IPP_REG_RD(handle, portn, IPP_BAD_CKSUM_ERR_CNT_REG, err_cnt);
56144961713Sgirish 
56244961713Sgirish 	return (NPI_SUCCESS);
56344961713Sgirish }
564