16f3e57acSmx /*
247693af9Smx * CDDL HEADER START
347693af9Smx *
447693af9Smx * The contents of this file are subject to the terms of the
547693af9Smx * Common Development and Distribution License (the "License").
647693af9Smx * You may not use this file except in compliance with the License.
747693af9Smx *
847693af9Smx * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
947693af9Smx * or http://www.opensolaris.org/os/licensing.
1047693af9Smx * See the License for the specific language governing permissions
1147693af9Smx * and limitations under the License.
1247693af9Smx *
1347693af9Smx * When distributing Covered Code, include this CDDL HEADER in each
1447693af9Smx * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1547693af9Smx * If applicable, add the following below this CDDL HEADER, with the
1647693af9Smx * fields enclosed by brackets "[]" replaced with your own identifying
1747693af9Smx * information: Portions Copyright [yyyy] [name of copyright owner]
1847693af9Smx *
1947693af9Smx * CDDL HEADER END
206f3e57acSmx */
216f3e57acSmx
226f3e57acSmx /*
23d635b452SWinson Wang - Sun Microsystems - Beijing China * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
2447693af9Smx * Use is subject to license terms.
256f3e57acSmx */
266f3e57acSmx
2715c07adcSJohn Levon /*
2815c07adcSJohn Levon * Copyright (c) 2018, Joyent, Inc.
2915c07adcSJohn Levon */
3015c07adcSJohn Levon
316f3e57acSmx #include "nge.h"
3251fc88a8SWinson Wang - Sun Microsystems - Beijing China static uint32_t nge_watchdog_count = 1 << 5;
3351fc88a8SWinson Wang - Sun Microsystems - Beijing China static uint32_t nge_watchdog_check = 1 << 3;
346f3e57acSmx extern boolean_t nge_enable_msi;
356f3e57acSmx static void nge_sync_mac_modes(nge_t *);
366f3e57acSmx
376f3e57acSmx #undef NGE_DBG
386f3e57acSmx #define NGE_DBG NGE_DBG_CHIP
396f3e57acSmx
406f3e57acSmx /*
416f3e57acSmx * Operating register get/set access routines
426f3e57acSmx */
436f3e57acSmx uint8_t nge_reg_get8(nge_t *ngep, nge_regno_t regno);
446f3e57acSmx #pragma inline(nge_reg_get8)
456f3e57acSmx
466f3e57acSmx uint8_t
nge_reg_get8(nge_t * ngep,nge_regno_t regno)476f3e57acSmx nge_reg_get8(nge_t *ngep, nge_regno_t regno)
486f3e57acSmx {
496f3e57acSmx NGE_TRACE(("nge_reg_get8($%p, 0x%lx)", (void *)ngep, regno));
506f3e57acSmx
516f3e57acSmx return (ddi_get8(ngep->io_handle, PIO_ADDR(ngep, regno)));
526f3e57acSmx }
536f3e57acSmx
546f3e57acSmx void nge_reg_put8(nge_t *ngep, nge_regno_t regno, uint8_t data);
556f3e57acSmx #pragma inline(nge_reg_put8)
566f3e57acSmx
576f3e57acSmx void
nge_reg_put8(nge_t * ngep,nge_regno_t regno,uint8_t data)586f3e57acSmx nge_reg_put8(nge_t *ngep, nge_regno_t regno, uint8_t data)
596f3e57acSmx {
606f3e57acSmx NGE_TRACE(("nge_reg_put8($%p, 0x%lx, 0x%x)",
616f3e57acSmx (void *)ngep, regno, data));
626f3e57acSmx ddi_put8(ngep->io_handle, PIO_ADDR(ngep, regno), data);
636f3e57acSmx
646f3e57acSmx }
656f3e57acSmx
666f3e57acSmx uint16_t nge_reg_get16(nge_t *ngep, nge_regno_t regno);
676f3e57acSmx #pragma inline(nge_reg_get16)
686f3e57acSmx
696f3e57acSmx uint16_t
nge_reg_get16(nge_t * ngep,nge_regno_t regno)706f3e57acSmx nge_reg_get16(nge_t *ngep, nge_regno_t regno)
716f3e57acSmx {
726f3e57acSmx NGE_TRACE(("nge_reg_get16($%p, 0x%lx)", (void *)ngep, regno));
736f3e57acSmx return (ddi_get16(ngep->io_handle, PIO_ADDR(ngep, regno)));
746f3e57acSmx }
756f3e57acSmx
766f3e57acSmx void nge_reg_put16(nge_t *ngep, nge_regno_t regno, uint16_t data);
776f3e57acSmx #pragma inline(nge_reg_put16)
786f3e57acSmx
796f3e57acSmx void
nge_reg_put16(nge_t * ngep,nge_regno_t regno,uint16_t data)806f3e57acSmx nge_reg_put16(nge_t *ngep, nge_regno_t regno, uint16_t data)
816f3e57acSmx {
826f3e57acSmx NGE_TRACE(("nge_reg_put16($%p, 0x%lx, 0x%x)",
836f3e57acSmx (void *)ngep, regno, data));
846f3e57acSmx ddi_put16(ngep->io_handle, PIO_ADDR(ngep, regno), data);
856f3e57acSmx
866f3e57acSmx }
876f3e57acSmx
886f3e57acSmx uint32_t nge_reg_get32(nge_t *ngep, nge_regno_t regno);
896f3e57acSmx #pragma inline(nge_reg_get32)
906f3e57acSmx
916f3e57acSmx uint32_t
nge_reg_get32(nge_t * ngep,nge_regno_t regno)926f3e57acSmx nge_reg_get32(nge_t *ngep, nge_regno_t regno)
936f3e57acSmx {
946f3e57acSmx NGE_TRACE(("nge_reg_get32($%p, 0x%lx)", (void *)ngep, regno));
956f3e57acSmx return (ddi_get32(ngep->io_handle, PIO_ADDR(ngep, regno)));
966f3e57acSmx }
976f3e57acSmx
986f3e57acSmx void nge_reg_put32(nge_t *ngep, nge_regno_t regno, uint32_t data);
996f3e57acSmx #pragma inline(nge_reg_put32)
1006f3e57acSmx
1016f3e57acSmx void
nge_reg_put32(nge_t * ngep,nge_regno_t regno,uint32_t data)1026f3e57acSmx nge_reg_put32(nge_t *ngep, nge_regno_t regno, uint32_t data)
1036f3e57acSmx {
1046f3e57acSmx NGE_TRACE(("nge_reg_put32($%p, 0x%lx, 0x%x)",
1056f3e57acSmx (void *)ngep, regno, data));
1066f3e57acSmx ddi_put32(ngep->io_handle, PIO_ADDR(ngep, regno), data);
1076f3e57acSmx
1086f3e57acSmx }
1096f3e57acSmx
110*ae5a8bedSAndy Fiddaman #if NGE_DEBUGGING
1116f3e57acSmx static int nge_chip_peek_cfg(nge_t *ngep, nge_peekpoke_t *ppd);
1126f3e57acSmx #pragma no_inline(nge_chip_peek_cfg)
1136f3e57acSmx
1146f3e57acSmx static int
nge_chip_peek_cfg(nge_t * ngep,nge_peekpoke_t * ppd)1156f3e57acSmx nge_chip_peek_cfg(nge_t *ngep, nge_peekpoke_t *ppd)
1166f3e57acSmx {
1176f3e57acSmx int err;
1186f3e57acSmx uint64_t regval;
1196f3e57acSmx uint64_t regno;
1206f3e57acSmx
1216f3e57acSmx NGE_TRACE(("nge_chip_peek_cfg($%p, $%p)",
1226f3e57acSmx (void *)ngep, (void *)ppd));
1236f3e57acSmx
1246f3e57acSmx err = DDI_SUCCESS;
1256f3e57acSmx regno = ppd->pp_acc_offset;
1266f3e57acSmx
1276f3e57acSmx switch (ppd->pp_acc_size) {
1286f3e57acSmx case 1:
1296f3e57acSmx regval = pci_config_get8(ngep->cfg_handle, regno);
1306f3e57acSmx break;
1316f3e57acSmx
1326f3e57acSmx case 2:
1336f3e57acSmx regval = pci_config_get16(ngep->cfg_handle, regno);
1346f3e57acSmx break;
1356f3e57acSmx
1366f3e57acSmx case 4:
1376f3e57acSmx regval = pci_config_get32(ngep->cfg_handle, regno);
1386f3e57acSmx break;
1396f3e57acSmx
1406f3e57acSmx case 8:
1416f3e57acSmx regval = pci_config_get64(ngep->cfg_handle, regno);
1426f3e57acSmx break;
1436f3e57acSmx }
1446f3e57acSmx ppd->pp_acc_data = regval;
1456f3e57acSmx return (err);
1466f3e57acSmx }
1476f3e57acSmx
1486f3e57acSmx static int nge_chip_poke_cfg(nge_t *ngep, nge_peekpoke_t *ppd);
1496f3e57acSmx
1506f3e57acSmx static int
nge_chip_poke_cfg(nge_t * ngep,nge_peekpoke_t * ppd)1516f3e57acSmx nge_chip_poke_cfg(nge_t *ngep, nge_peekpoke_t *ppd)
1526f3e57acSmx {
1536f3e57acSmx int err;
1546f3e57acSmx uint64_t regval;
1556f3e57acSmx uint64_t regno;
1566f3e57acSmx
1576f3e57acSmx NGE_TRACE(("nge_chip_poke_cfg($%p, $%p)",
1586f3e57acSmx (void *)ngep, (void *)ppd));
1596f3e57acSmx
1606f3e57acSmx err = DDI_SUCCESS;
1616f3e57acSmx regno = ppd->pp_acc_offset;
1626f3e57acSmx regval = ppd->pp_acc_data;
1636f3e57acSmx
1646f3e57acSmx switch (ppd->pp_acc_size) {
1656f3e57acSmx case 1:
1666f3e57acSmx pci_config_put8(ngep->cfg_handle, regno, regval);
1676f3e57acSmx break;
1686f3e57acSmx
1696f3e57acSmx case 2:
1706f3e57acSmx pci_config_put16(ngep->cfg_handle, regno, regval);
1716f3e57acSmx break;
1726f3e57acSmx
1736f3e57acSmx case 4:
1746f3e57acSmx pci_config_put32(ngep->cfg_handle, regno, regval);
1756f3e57acSmx break;
1766f3e57acSmx
1776f3e57acSmx case 8:
1786f3e57acSmx pci_config_put64(ngep->cfg_handle, regno, regval);
1796f3e57acSmx break;
1806f3e57acSmx }
1816f3e57acSmx
1826f3e57acSmx return (err);
1836f3e57acSmx
1846f3e57acSmx }
1856f3e57acSmx
1866f3e57acSmx static int nge_chip_peek_reg(nge_t *ngep, nge_peekpoke_t *ppd);
1876f3e57acSmx
1886f3e57acSmx static int
nge_chip_peek_reg(nge_t * ngep,nge_peekpoke_t * ppd)1896f3e57acSmx nge_chip_peek_reg(nge_t *ngep, nge_peekpoke_t *ppd)
1906f3e57acSmx {
1916f3e57acSmx int err;
1926f3e57acSmx uint64_t regval;
1936f3e57acSmx void *regaddr;
1946f3e57acSmx
1956f3e57acSmx NGE_TRACE(("nge_chip_peek_reg($%p, $%p)",
1966f3e57acSmx (void *)ngep, (void *)ppd));
1976f3e57acSmx
1986f3e57acSmx err = DDI_SUCCESS;
1996f3e57acSmx regaddr = PIO_ADDR(ngep, ppd->pp_acc_offset);
2006f3e57acSmx
2016f3e57acSmx switch (ppd->pp_acc_size) {
2026f3e57acSmx case 1:
2036f3e57acSmx regval = ddi_get8(ngep->io_handle, regaddr);
2046f3e57acSmx break;
2056f3e57acSmx
2066f3e57acSmx case 2:
2076f3e57acSmx regval = ddi_get16(ngep->io_handle, regaddr);
2086f3e57acSmx break;
2096f3e57acSmx
2106f3e57acSmx case 4:
2116f3e57acSmx regval = ddi_get32(ngep->io_handle, regaddr);
2126f3e57acSmx break;
2136f3e57acSmx
2146f3e57acSmx case 8:
2156f3e57acSmx regval = ddi_get64(ngep->io_handle, regaddr);
2166f3e57acSmx break;
2176f3e57acSmx
2186f3e57acSmx default:
2196f3e57acSmx regval = 0x0ull;
2206f3e57acSmx break;
2216f3e57acSmx }
2226f3e57acSmx ppd->pp_acc_data = regval;
2236f3e57acSmx return (err);
2246f3e57acSmx }
2256f3e57acSmx
2266f3e57acSmx static int nge_chip_poke_reg(nge_t *ngep, nge_peekpoke_t *ppd);
2276f3e57acSmx
2286f3e57acSmx static int
nge_chip_poke_reg(nge_t * ngep,nge_peekpoke_t * ppd)2296f3e57acSmx nge_chip_poke_reg(nge_t *ngep, nge_peekpoke_t *ppd)
2306f3e57acSmx {
2316f3e57acSmx int err;
2326f3e57acSmx uint64_t regval;
2336f3e57acSmx void *regaddr;
2346f3e57acSmx
2356f3e57acSmx NGE_TRACE(("nge_chip_poke_reg($%p, $%p)",
2366f3e57acSmx (void *)ngep, (void *)ppd));
2376f3e57acSmx
2386f3e57acSmx err = DDI_SUCCESS;
2396f3e57acSmx regaddr = PIO_ADDR(ngep, ppd->pp_acc_offset);
2406f3e57acSmx regval = ppd->pp_acc_data;
2416f3e57acSmx
2426f3e57acSmx switch (ppd->pp_acc_size) {
2436f3e57acSmx case 1:
2446f3e57acSmx ddi_put8(ngep->io_handle, regaddr, regval);
2456f3e57acSmx break;
2466f3e57acSmx
2476f3e57acSmx case 2:
2486f3e57acSmx ddi_put16(ngep->io_handle, regaddr, regval);
2496f3e57acSmx break;
2506f3e57acSmx
2516f3e57acSmx case 4:
2526f3e57acSmx ddi_put32(ngep->io_handle, regaddr, regval);
2536f3e57acSmx break;
2546f3e57acSmx
2556f3e57acSmx case 8:
2566f3e57acSmx ddi_put64(ngep->io_handle, regaddr, regval);
2576f3e57acSmx break;
2586f3e57acSmx }
2596f3e57acSmx return (err);
2606f3e57acSmx }
2616f3e57acSmx
2626f3e57acSmx static int nge_chip_peek_mii(nge_t *ngep, nge_peekpoke_t *ppd);
2636f3e57acSmx #pragma no_inline(nge_chip_peek_mii)
2646f3e57acSmx
2656f3e57acSmx static int
nge_chip_peek_mii(nge_t * ngep,nge_peekpoke_t * ppd)2666f3e57acSmx nge_chip_peek_mii(nge_t *ngep, nge_peekpoke_t *ppd)
2676f3e57acSmx {
2686f3e57acSmx int err;
2696f3e57acSmx
2706f3e57acSmx err = DDI_SUCCESS;
2716f3e57acSmx ppd->pp_acc_data = nge_mii_get16(ngep, ppd->pp_acc_offset/2);
2726f3e57acSmx return (err);
2736f3e57acSmx }
2746f3e57acSmx
2756f3e57acSmx static int nge_chip_poke_mii(nge_t *ngep, nge_peekpoke_t *ppd);
2766f3e57acSmx #pragma no_inline(nge_chip_poke_mii)
2776f3e57acSmx
2786f3e57acSmx static int
nge_chip_poke_mii(nge_t * ngep,nge_peekpoke_t * ppd)2796f3e57acSmx nge_chip_poke_mii(nge_t *ngep, nge_peekpoke_t *ppd)
2806f3e57acSmx {
2816f3e57acSmx int err;
2826f3e57acSmx err = DDI_SUCCESS;
2836f3e57acSmx nge_mii_put16(ngep, ppd->pp_acc_offset/2, ppd->pp_acc_data);
2846f3e57acSmx return (err);
2856f3e57acSmx }
2866f3e57acSmx
2876f3e57acSmx /*
2886f3e57acSmx * Basic SEEPROM get/set access routine
2896f3e57acSmx *
2906f3e57acSmx * This uses the chip's SEEPROM auto-access method, controlled by the
2916f3e57acSmx * Serial EEPROM Address/Data Registers at 0x504h, so the CPU
2926f3e57acSmx * doesn't have to fiddle with the individual bits.
2936f3e57acSmx *
2946f3e57acSmx * The caller should hold <genlock> and *also* have already acquired
2956f3e57acSmx * the right to access the SEEPROM.
2966f3e57acSmx *
2976f3e57acSmx * Return value:
2986f3e57acSmx * 0 on success,
2996f3e57acSmx * ENODATA on access timeout (maybe retryable: device may just be busy)
3006f3e57acSmx * EPROTO on other h/w or s/w errors.
3016f3e57acSmx *
3026f3e57acSmx * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output
3036f3e57acSmx * from a (successful) SEEPROM_ACCESS_READ.
3046f3e57acSmx */
3056f3e57acSmx
3066f3e57acSmx static int
nge_seeprom_access(nge_t * ngep,uint32_t cmd,nge_regno_t addr,uint16_t * dp)3076f3e57acSmx nge_seeprom_access(nge_t *ngep, uint32_t cmd, nge_regno_t addr, uint16_t *dp)
3086f3e57acSmx {
3096f3e57acSmx uint32_t tries;
3106f3e57acSmx nge_ep_cmd cmd_reg;
3116f3e57acSmx nge_ep_data data_reg;
3126f3e57acSmx
3136f3e57acSmx NGE_TRACE(("nge_seeprom_access($%p, %d, %x, $%p)",
3146f3e57acSmx (void *)ngep, cmd, addr, (void *)dp));
3156f3e57acSmx
3166f3e57acSmx ASSERT(mutex_owned(ngep->genlock));
3176f3e57acSmx
3186f3e57acSmx /*
3196f3e57acSmx * Check there's no command in progress.
3206f3e57acSmx *
3216f3e57acSmx * Note: this *shouldn't* ever find that there is a command
3226f3e57acSmx * in progress, because we already hold the <genlock> mutex.
3236f3e57acSmx * Also, to ensure we don't have a conflict with the chip's
3246f3e57acSmx * internal firmware or a process accessing the same (shared)
3256f3e57acSmx * So this is just a final consistency check: we shouldn't
3266f3e57acSmx * see EITHER the START bit (command started but not complete)
3276f3e57acSmx * OR the COMPLETE bit (command completed but not cleared).
3286f3e57acSmx */
3296f3e57acSmx cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD);
3306f3e57acSmx for (tries = 0; tries < 30; tries++) {
3316f3e57acSmx if (cmd_reg.cmd_bits.sts == SEEPROM_READY)
3326f3e57acSmx break;
3336f3e57acSmx drv_usecwait(10);
3346f3e57acSmx cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD);
3356f3e57acSmx }
3366f3e57acSmx
3376f3e57acSmx /*
3386f3e57acSmx * This should not happen. If so, we have to restart eeprom
3396f3e57acSmx * state machine
3406f3e57acSmx */
3416f3e57acSmx if (tries == 30) {
3426f3e57acSmx cmd_reg.cmd_bits.sts = SEEPROM_READY;
3436f3e57acSmx nge_reg_put32(ngep, NGE_EP_CMD, cmd_reg.cmd_val);
3446f3e57acSmx drv_usecwait(10);
3456f3e57acSmx /*
3466f3e57acSmx * Polling the status bit to make assure the eeprom is ready
3476f3e57acSmx */
3486f3e57acSmx cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD);
3496f3e57acSmx for (tries = 0; tries < 30; tries++) {
3506f3e57acSmx if (cmd_reg.cmd_bits.sts == SEEPROM_READY)
3516f3e57acSmx break;
3526f3e57acSmx drv_usecwait(10);
3536f3e57acSmx cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD);
3546f3e57acSmx }
3556f3e57acSmx }
3566f3e57acSmx
3576f3e57acSmx /*
3586f3e57acSmx * Assemble the command ...
3596f3e57acSmx */
360a55f7119SMiles Xu, Sun Microsystems cmd_reg.cmd_bits.addr = (uint32_t)addr;
3616f3e57acSmx cmd_reg.cmd_bits.cmd = cmd;
3626f3e57acSmx cmd_reg.cmd_bits.sts = 0;
3636f3e57acSmx
3646f3e57acSmx nge_reg_put32(ngep, NGE_EP_CMD, cmd_reg.cmd_val);
3656f3e57acSmx
3666f3e57acSmx /*
3676f3e57acSmx * Polling whether the access is successful.
3686f3e57acSmx *
3696f3e57acSmx */
3706f3e57acSmx cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD);
3716f3e57acSmx for (tries = 0; tries < 30; tries++) {
3726f3e57acSmx if (cmd_reg.cmd_bits.sts == SEEPROM_READY)
3736f3e57acSmx break;
3746f3e57acSmx drv_usecwait(10);
3756f3e57acSmx cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD);
3766f3e57acSmx }
3776f3e57acSmx
3786f3e57acSmx if (tries == 30) {
3796f3e57acSmx nge_report(ngep, NGE_HW_ROM);
3806f3e57acSmx return (DDI_FAILURE);
3816f3e57acSmx }
3826f3e57acSmx switch (cmd) {
3836f3e57acSmx default:
3846f3e57acSmx case SEEPROM_CMD_WRITE_ENABLE:
3856f3e57acSmx case SEEPROM_CMD_ERASE:
3866f3e57acSmx case SEEPROM_CMD_ERALSE_ALL:
3876f3e57acSmx case SEEPROM_CMD_WRITE_DIS:
3886f3e57acSmx break;
3896f3e57acSmx
3906f3e57acSmx case SEEPROM_CMD_READ:
3916f3e57acSmx data_reg.data_val = nge_reg_get32(ngep, NGE_EP_DATA);
3926f3e57acSmx *dp = data_reg.data_bits.data;
3936f3e57acSmx break;
3946f3e57acSmx
3956f3e57acSmx case SEEPROM_CMD_WRITE:
3966f3e57acSmx data_reg.data_val = nge_reg_get32(ngep, NGE_EP_DATA);
3976f3e57acSmx data_reg.data_bits.data = *dp;
3986f3e57acSmx nge_reg_put32(ngep, NGE_EP_DATA, data_reg.data_val);
3996f3e57acSmx break;
4006f3e57acSmx }
4016f3e57acSmx
4026f3e57acSmx return (DDI_SUCCESS);
4036f3e57acSmx }
4046f3e57acSmx
4056f3e57acSmx
4066f3e57acSmx static int
nge_chip_peek_seeprom(nge_t * ngep,nge_peekpoke_t * ppd)4076f3e57acSmx nge_chip_peek_seeprom(nge_t *ngep, nge_peekpoke_t *ppd)
4086f3e57acSmx {
4096f3e57acSmx uint16_t data;
4106f3e57acSmx int err;
4116f3e57acSmx
4126f3e57acSmx err = nge_seeprom_access(ngep, SEEPROM_CMD_READ,
4136f3e57acSmx ppd->pp_acc_offset, &data);
4146f3e57acSmx ppd->pp_acc_data = data;
4156f3e57acSmx return (err);
4166f3e57acSmx }
4176f3e57acSmx
4186f3e57acSmx static int
nge_chip_poke_seeprom(nge_t * ngep,nge_peekpoke_t * ppd)4196f3e57acSmx nge_chip_poke_seeprom(nge_t *ngep, nge_peekpoke_t *ppd)
4206f3e57acSmx {
4216f3e57acSmx uint16_t data;
4226f3e57acSmx int err;
4236f3e57acSmx
4246f3e57acSmx data = ppd->pp_acc_data;
4256f3e57acSmx err = nge_seeprom_access(ngep, SEEPROM_CMD_WRITE,
4266f3e57acSmx ppd->pp_acc_offset, &data);
4276f3e57acSmx return (err);
4286f3e57acSmx }
429*ae5a8bedSAndy Fiddaman #endif /* NGE_DEBUGGING */
4306f3e57acSmx
4316f3e57acSmx void
nge_init_dev_spec_param(nge_t * ngep)4326f3e57acSmx nge_init_dev_spec_param(nge_t *ngep)
4336f3e57acSmx {
4346f3e57acSmx nge_dev_spec_param_t *dev_param_p;
4356f3e57acSmx chip_info_t *infop;
4366f3e57acSmx
4376f3e57acSmx dev_param_p = &ngep->dev_spec_param;
4386f3e57acSmx infop = (chip_info_t *)&ngep->chipinfo;
4396f3e57acSmx
4406f3e57acSmx switch (infop->device) {
4416f3e57acSmx case DEVICE_ID_NF3_E6:
4426f3e57acSmx case DEVICE_ID_NF3_DF:
4436f3e57acSmx case DEVICE_ID_MCP04_37:
4446f3e57acSmx case DEVICE_ID_MCP04_38:
4456f3e57acSmx dev_param_p->msi = B_FALSE;
4466f3e57acSmx dev_param_p->msi_x = B_FALSE;
4476f3e57acSmx dev_param_p->vlan = B_FALSE;
4489ae6bcf1Sjj dev_param_p->advanced_pm = B_FALSE;
449d27d4a13SMiles Xu, Sun Microsystems dev_param_p->mac_addr_order = B_FALSE;
4506f3e57acSmx dev_param_p->tx_pause_frame = B_FALSE;
4516f3e57acSmx dev_param_p->rx_pause_frame = B_FALSE;
4526f3e57acSmx dev_param_p->jumbo = B_FALSE;
4536f3e57acSmx dev_param_p->tx_rx_64byte = B_FALSE;
4546f3e57acSmx dev_param_p->rx_hw_checksum = B_FALSE;
4556f3e57acSmx dev_param_p->tx_hw_checksum = 0;
4566f3e57acSmx dev_param_p->desc_type = DESC_OFFLOAD;
4576f3e57acSmx dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_1024;
4586f3e57acSmx dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_1024;
4596f3e57acSmx dev_param_p->nge_split = NGE_SPLIT_32;
4606f3e57acSmx break;
4616f3e57acSmx
4626f3e57acSmx case DEVICE_ID_CK804_56:
4636f3e57acSmx case DEVICE_ID_CK804_57:
4646f3e57acSmx dev_param_p->msi = B_TRUE;
4656f3e57acSmx dev_param_p->msi_x = B_TRUE;
4666f3e57acSmx dev_param_p->vlan = B_FALSE;
4679ae6bcf1Sjj dev_param_p->advanced_pm = B_FALSE;
468d27d4a13SMiles Xu, Sun Microsystems dev_param_p->mac_addr_order = B_FALSE;
4696f3e57acSmx dev_param_p->tx_pause_frame = B_FALSE;
4706f3e57acSmx dev_param_p->rx_pause_frame = B_TRUE;
4716f3e57acSmx dev_param_p->jumbo = B_TRUE;
4726f3e57acSmx dev_param_p->tx_rx_64byte = B_FALSE;
4736f3e57acSmx dev_param_p->rx_hw_checksum = B_TRUE;
4746f3e57acSmx dev_param_p->tx_hw_checksum = HCKSUM_IPHDRCKSUM;
4756f3e57acSmx dev_param_p->desc_type = DESC_HOT;
4766f3e57acSmx dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_3072;
4776f3e57acSmx dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_3072;
4786f3e57acSmx dev_param_p->nge_split = NGE_SPLIT_96;
4796f3e57acSmx break;
4806f3e57acSmx
4816f3e57acSmx case DEVICE_ID_MCP51_268:
4826f3e57acSmx case DEVICE_ID_MCP51_269:
4836f3e57acSmx dev_param_p->msi = B_FALSE;
4846f3e57acSmx dev_param_p->msi_x = B_FALSE;
4856f3e57acSmx dev_param_p->vlan = B_FALSE;
4869ae6bcf1Sjj dev_param_p->advanced_pm = B_TRUE;
487d27d4a13SMiles Xu, Sun Microsystems dev_param_p->mac_addr_order = B_FALSE;
4886f3e57acSmx dev_param_p->tx_pause_frame = B_FALSE;
4896f3e57acSmx dev_param_p->rx_pause_frame = B_FALSE;
4906f3e57acSmx dev_param_p->jumbo = B_FALSE;
4916f3e57acSmx dev_param_p->tx_rx_64byte = B_TRUE;
4926f3e57acSmx dev_param_p->rx_hw_checksum = B_FALSE;
4936f3e57acSmx dev_param_p->tx_hw_checksum = 0;
4946f3e57acSmx dev_param_p->desc_type = DESC_OFFLOAD;
4956f3e57acSmx dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_1024;
4966f3e57acSmx dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_1024;
4976f3e57acSmx dev_param_p->nge_split = NGE_SPLIT_32;
4986f3e57acSmx break;
4996f3e57acSmx
5006f3e57acSmx case DEVICE_ID_MCP55_372:
5016f3e57acSmx case DEVICE_ID_MCP55_373:
5026f3e57acSmx dev_param_p->msi = B_TRUE;
5036f3e57acSmx dev_param_p->msi_x = B_TRUE;
5046f3e57acSmx dev_param_p->vlan = B_TRUE;
5059ae6bcf1Sjj dev_param_p->advanced_pm = B_TRUE;
506d27d4a13SMiles Xu, Sun Microsystems dev_param_p->mac_addr_order = B_FALSE;
5076f3e57acSmx dev_param_p->tx_pause_frame = B_TRUE;
5086f3e57acSmx dev_param_p->rx_pause_frame = B_TRUE;
5096f3e57acSmx dev_param_p->jumbo = B_TRUE;
5106f3e57acSmx dev_param_p->tx_rx_64byte = B_TRUE;
5116f3e57acSmx dev_param_p->rx_hw_checksum = B_TRUE;
5126f3e57acSmx dev_param_p->tx_hw_checksum = HCKSUM_IPHDRCKSUM;
5136f3e57acSmx dev_param_p->desc_type = DESC_HOT;
5146f3e57acSmx dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_3072;
5156f3e57acSmx dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_3072;
5166f3e57acSmx dev_param_p->nge_split = NGE_SPLIT_96;
5176f3e57acSmx break;
5186f3e57acSmx
519d27d4a13SMiles Xu, Sun Microsystems case DEVICE_ID_MCP61_3EE:
520d27d4a13SMiles Xu, Sun Microsystems case DEVICE_ID_MCP61_3EF:
521d27d4a13SMiles Xu, Sun Microsystems dev_param_p->msi = B_FALSE;
522d27d4a13SMiles Xu, Sun Microsystems dev_param_p->msi_x = B_FALSE;
523d27d4a13SMiles Xu, Sun Microsystems dev_param_p->vlan = B_FALSE;
524d27d4a13SMiles Xu, Sun Microsystems dev_param_p->advanced_pm = B_TRUE;
525d27d4a13SMiles Xu, Sun Microsystems dev_param_p->mac_addr_order = B_TRUE;
526d27d4a13SMiles Xu, Sun Microsystems dev_param_p->tx_pause_frame = B_FALSE;
527d27d4a13SMiles Xu, Sun Microsystems dev_param_p->rx_pause_frame = B_FALSE;
528d27d4a13SMiles Xu, Sun Microsystems dev_param_p->jumbo = B_FALSE;
529d27d4a13SMiles Xu, Sun Microsystems dev_param_p->tx_rx_64byte = B_TRUE;
530d27d4a13SMiles Xu, Sun Microsystems dev_param_p->rx_hw_checksum = B_FALSE;
531d27d4a13SMiles Xu, Sun Microsystems dev_param_p->tx_hw_checksum = 0;
532d27d4a13SMiles Xu, Sun Microsystems dev_param_p->desc_type = DESC_OFFLOAD;
533d27d4a13SMiles Xu, Sun Microsystems dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_1024;
534d27d4a13SMiles Xu, Sun Microsystems dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_1024;
535d27d4a13SMiles Xu, Sun Microsystems dev_param_p->nge_split = NGE_SPLIT_32;
536d27d4a13SMiles Xu, Sun Microsystems break;
537d27d4a13SMiles Xu, Sun Microsystems
538a01a4735SWinson Wang - Sun Microsystems - Beijing China case DEVICE_ID_MCP77_760:
5399fa05d92SWinson Wang - Sun Microsystems - Beijing China case DEVICE_ID_MCP79_AB0:
540a01a4735SWinson Wang - Sun Microsystems - Beijing China dev_param_p->msi = B_FALSE;
541a01a4735SWinson Wang - Sun Microsystems - Beijing China dev_param_p->msi_x = B_FALSE;
542a01a4735SWinson Wang - Sun Microsystems - Beijing China dev_param_p->vlan = B_FALSE;
543a01a4735SWinson Wang - Sun Microsystems - Beijing China dev_param_p->advanced_pm = B_TRUE;
544a01a4735SWinson Wang - Sun Microsystems - Beijing China dev_param_p->mac_addr_order = B_TRUE;
545a01a4735SWinson Wang - Sun Microsystems - Beijing China dev_param_p->tx_pause_frame = B_FALSE;
546a01a4735SWinson Wang - Sun Microsystems - Beijing China dev_param_p->rx_pause_frame = B_FALSE;
547a01a4735SWinson Wang - Sun Microsystems - Beijing China dev_param_p->jumbo = B_FALSE;
548a01a4735SWinson Wang - Sun Microsystems - Beijing China dev_param_p->tx_rx_64byte = B_TRUE;
549a01a4735SWinson Wang - Sun Microsystems - Beijing China dev_param_p->rx_hw_checksum = B_FALSE;
550a01a4735SWinson Wang - Sun Microsystems - Beijing China dev_param_p->tx_hw_checksum = 0;
551a01a4735SWinson Wang - Sun Microsystems - Beijing China dev_param_p->desc_type = DESC_HOT;
552a01a4735SWinson Wang - Sun Microsystems - Beijing China dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_1024;
553a01a4735SWinson Wang - Sun Microsystems - Beijing China dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_1024;
554a01a4735SWinson Wang - Sun Microsystems - Beijing China dev_param_p->nge_split = NGE_SPLIT_32;
555a01a4735SWinson Wang - Sun Microsystems - Beijing China break;
556a01a4735SWinson Wang - Sun Microsystems - Beijing China
5576f3e57acSmx default:
5586f3e57acSmx dev_param_p->msi = B_FALSE;
5596f3e57acSmx dev_param_p->msi_x = B_FALSE;
5606f3e57acSmx dev_param_p->vlan = B_FALSE;
5619ae6bcf1Sjj dev_param_p->advanced_pm = B_FALSE;
562d27d4a13SMiles Xu, Sun Microsystems dev_param_p->mac_addr_order = B_FALSE;
5636f3e57acSmx dev_param_p->tx_pause_frame = B_FALSE;
5646f3e57acSmx dev_param_p->rx_pause_frame = B_FALSE;
5656f3e57acSmx dev_param_p->jumbo = B_FALSE;
5666f3e57acSmx dev_param_p->tx_rx_64byte = B_FALSE;
5676f3e57acSmx dev_param_p->rx_hw_checksum = B_FALSE;
5686f3e57acSmx dev_param_p->tx_hw_checksum = 0;
5696f3e57acSmx dev_param_p->desc_type = DESC_OFFLOAD;
5706f3e57acSmx dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_1024;
5716f3e57acSmx dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_1024;
5726f3e57acSmx dev_param_p->nge_split = NGE_SPLIT_32;
5736f3e57acSmx return;
5746f3e57acSmx }
5756f3e57acSmx }
5766f3e57acSmx /*
5776f3e57acSmx * Perform first-stage chip (re-)initialisation, using only config-space
5786f3e57acSmx * accesses:
5796f3e57acSmx *
5806f3e57acSmx * + Read the vendor/device/revision/subsystem/cache-line-size registers,
5816f3e57acSmx * returning the data in the structure pointed to by <infop>.
5826f3e57acSmx */
5836f3e57acSmx void nge_chip_cfg_init(nge_t *ngep, chip_info_t *infop, boolean_t reset);
5846f3e57acSmx #pragma no_inline(nge_chip_cfg_init)
5856f3e57acSmx
5866f3e57acSmx void
nge_chip_cfg_init(nge_t * ngep,chip_info_t * infop,boolean_t reset)5876f3e57acSmx nge_chip_cfg_init(nge_t *ngep, chip_info_t *infop, boolean_t reset)
5886f3e57acSmx {
5896f3e57acSmx uint16_t command;
5906f3e57acSmx ddi_acc_handle_t handle;
5916f3e57acSmx nge_interbus_conf interbus_conf;
5926f3e57acSmx nge_msi_mask_conf msi_mask_conf;
5936f3e57acSmx nge_msi_map_cap_conf cap_conf;
5946f3e57acSmx
5956f3e57acSmx NGE_TRACE(("nge_chip_cfg_init($%p, $%p, %d)",
5966f3e57acSmx (void *)ngep, (void *)infop, reset));
5976f3e57acSmx
5986f3e57acSmx /*
5996f3e57acSmx * save PCI cache line size and subsystem vendor ID
6006f3e57acSmx *
6016f3e57acSmx * Read all the config-space registers that characterise the
6026f3e57acSmx * chip, specifically vendor/device/revision/subsystem vendor
6036f3e57acSmx * and subsystem device id. We expect (but don't check) that
6046f3e57acSmx */
6056f3e57acSmx handle = ngep->cfg_handle;
6066f3e57acSmx /* reading the vendor information once */
6076f3e57acSmx if (reset == B_FALSE) {
6086f3e57acSmx infop->command = pci_config_get16(handle,
6096f3e57acSmx PCI_CONF_COMM);
6106f3e57acSmx infop->vendor = pci_config_get16(handle,
6116f3e57acSmx PCI_CONF_VENID);
6126f3e57acSmx infop->device = pci_config_get16(handle,
6136f3e57acSmx PCI_CONF_DEVID);
6146f3e57acSmx infop->subven = pci_config_get16(handle,
6156f3e57acSmx PCI_CONF_SUBVENID);
6166f3e57acSmx infop->subdev = pci_config_get16(handle,
6176f3e57acSmx PCI_CONF_SUBSYSID);
6186f3e57acSmx infop->class_code = pci_config_get8(handle,
6196f3e57acSmx PCI_CONF_BASCLASS);
6206f3e57acSmx infop->revision = pci_config_get8(handle,
6216f3e57acSmx PCI_CONF_REVID);
6226f3e57acSmx infop->clsize = pci_config_get8(handle,
6236f3e57acSmx PCI_CONF_CACHE_LINESZ);
6246f3e57acSmx infop->latency = pci_config_get8(handle,
6256f3e57acSmx PCI_CONF_LATENCY_TIMER);
6266f3e57acSmx }
6276f3e57acSmx if (nge_enable_msi) {
6286f3e57acSmx /* Disable the hidden for MSI support */
6296f3e57acSmx interbus_conf.conf_val = pci_config_get32(handle,
6306f3e57acSmx PCI_CONF_HT_INTERNAL);
6316f3e57acSmx if ((infop->device == DEVICE_ID_MCP55_373) ||
6326f3e57acSmx (infop->device == DEVICE_ID_MCP55_372))
6336f3e57acSmx interbus_conf.conf_bits.msix_off = NGE_SET;
6346f3e57acSmx interbus_conf.conf_bits.msi_off = NGE_CLEAR;
6356f3e57acSmx pci_config_put32(handle, PCI_CONF_HT_INTERNAL,
6366f3e57acSmx interbus_conf.conf_val);
6376f3e57acSmx
6386f3e57acSmx if ((infop->device == DEVICE_ID_MCP55_373) ||
6396f3e57acSmx (infop->device == DEVICE_ID_MCP55_372)) {
6406f3e57acSmx
6416f3e57acSmx /* Disable the vector off for mcp55 */
6426f3e57acSmx msi_mask_conf.msi_mask_conf_val =
6436f3e57acSmx pci_config_get32(handle, PCI_CONF_HT_MSI_MASK);
6446f3e57acSmx msi_mask_conf.msi_mask_bits.vec0_off = NGE_CLEAR;
6456f3e57acSmx msi_mask_conf.msi_mask_bits.vec1_off = NGE_CLEAR;
6466f3e57acSmx msi_mask_conf.msi_mask_bits.vec2_off = NGE_CLEAR;
6476f3e57acSmx msi_mask_conf.msi_mask_bits.vec3_off = NGE_CLEAR;
6486f3e57acSmx msi_mask_conf.msi_mask_bits.vec4_off = NGE_CLEAR;
6496f3e57acSmx msi_mask_conf.msi_mask_bits.vec5_off = NGE_CLEAR;
6506f3e57acSmx msi_mask_conf.msi_mask_bits.vec6_off = NGE_CLEAR;
6516f3e57acSmx msi_mask_conf.msi_mask_bits.vec7_off = NGE_CLEAR;
6526f3e57acSmx pci_config_put32(handle, PCI_CONF_HT_MSI_MASK,
6536f3e57acSmx msi_mask_conf.msi_mask_conf_val);
6546f3e57acSmx
6556f3e57acSmx /* Enable the MSI mapping */
6566f3e57acSmx cap_conf.msi_map_cap_conf_val =
6576f3e57acSmx pci_config_get32(handle, PCI_CONF_HT_MSI_MAP_CAP);
6586f3e57acSmx cap_conf.map_cap_conf_bits.map_en = NGE_SET;
6596f3e57acSmx pci_config_put32(handle, PCI_CONF_HT_MSI_MAP_CAP,
6606f3e57acSmx cap_conf.msi_map_cap_conf_val);
6616f3e57acSmx }
6626f3e57acSmx } else {
6636f3e57acSmx interbus_conf.conf_val = pci_config_get32(handle,
6646f3e57acSmx PCI_CONF_HT_INTERNAL);
6656f3e57acSmx interbus_conf.conf_bits.msi_off = NGE_SET;
6666f3e57acSmx pci_config_put32(handle, PCI_CONF_HT_INTERNAL,
6676f3e57acSmx interbus_conf.conf_val);
6686f3e57acSmx }
6696f3e57acSmx command = infop->command | PCI_COMM_MAE;
6706f3e57acSmx command &= ~PCI_COMM_MEMWR_INVAL;
6716f3e57acSmx command |= PCI_COMM_ME;
6726f3e57acSmx pci_config_put16(handle, PCI_CONF_COMM, command);
6736f3e57acSmx pci_config_put16(handle, PCI_CONF_STAT, ~0);
6746f3e57acSmx
6756f3e57acSmx }
6766f3e57acSmx
6776f3e57acSmx int
nge_chip_stop(nge_t * ngep,boolean_t fault)6786f3e57acSmx nge_chip_stop(nge_t *ngep, boolean_t fault)
6796f3e57acSmx {
6806f3e57acSmx int err;
6816f3e57acSmx uint32_t reg_val;
6826f3e57acSmx uint32_t tries;
6836f3e57acSmx nge_mintr_src mintr_src;
6846f3e57acSmx nge_mii_cs mii_cs;
6856f3e57acSmx nge_rx_poll rx_poll;
6866f3e57acSmx nge_tx_poll tx_poll;
6876f3e57acSmx nge_rx_en rx_en;
6886f3e57acSmx nge_tx_en tx_en;
6896f3e57acSmx nge_tx_sta tx_sta;
6906f3e57acSmx nge_rx_sta rx_sta;
6916f3e57acSmx nge_mode_cntl mode;
6926f3e57acSmx nge_pmu_cntl2 pmu_cntl2;
6936f3e57acSmx
6946f3e57acSmx NGE_TRACE(("nge_chip_stop($%p, %d)", (void *)ngep, fault));
6956f3e57acSmx
6966f3e57acSmx err = DDI_SUCCESS;
6979ae6bcf1Sjj
6989ae6bcf1Sjj /* Clear any pending PHY interrupt */
6996f3e57acSmx mintr_src.src_val = nge_reg_get8(ngep, NGE_MINTR_SRC);
7006f3e57acSmx nge_reg_put8(ngep, NGE_MINTR_SRC, mintr_src.src_val);
7016f3e57acSmx
7026f3e57acSmx /* Mask all interrupts */
7036f3e57acSmx reg_val = nge_reg_get32(ngep, NGE_INTR_MASK);
7046f3e57acSmx reg_val &= ~NGE_INTR_ALL_EN;
7056f3e57acSmx nge_reg_put32(ngep, NGE_INTR_MASK, reg_val);
7066f3e57acSmx
7076f3e57acSmx /* Disable auto-polling of phy */
7086f3e57acSmx mii_cs.cs_val = nge_reg_get32(ngep, NGE_MII_CS);
7096f3e57acSmx mii_cs.cs_bits.ap_en = NGE_CLEAR;
7106f3e57acSmx nge_reg_put32(ngep, NGE_MII_CS, mii_cs.cs_val);
7116f3e57acSmx
7126f3e57acSmx /* Reset buffer management & DMA */
7136f3e57acSmx mode.mode_val = nge_reg_get32(ngep, NGE_MODE_CNTL);
7146f3e57acSmx mode.mode_bits.dma_dis = NGE_SET;
7156f3e57acSmx mode.mode_bits.desc_type = ngep->desc_mode;
7166f3e57acSmx nge_reg_put32(ngep, NGE_MODE_CNTL, mode.mode_val);
7176f3e57acSmx
7186de4f663Smx for (tries = 0; tries < 10000; tries++) {
7196f3e57acSmx drv_usecwait(10);
7206f3e57acSmx mode.mode_val = nge_reg_get32(ngep, NGE_MODE_CNTL);
7216f3e57acSmx if (mode.mode_bits.dma_status == NGE_SET)
7226f3e57acSmx break;
7236f3e57acSmx }
7246de4f663Smx if (tries == 10000) {
725a01a4735SWinson Wang - Sun Microsystems - Beijing China ngep->nge_chip_state = NGE_CHIP_ERROR;
7266f3e57acSmx return (DDI_FAILURE);
7276f3e57acSmx }
7286f3e57acSmx
729d635b452SWinson Wang - Sun Microsystems - Beijing China /* Disable rx's machine */
730d635b452SWinson Wang - Sun Microsystems - Beijing China rx_en.val = nge_reg_get8(ngep, NGE_RX_EN);
731d635b452SWinson Wang - Sun Microsystems - Beijing China rx_en.bits.rx_en = NGE_CLEAR;
732d635b452SWinson Wang - Sun Microsystems - Beijing China nge_reg_put8(ngep, NGE_RX_EN, rx_en.val);
7336f3e57acSmx
734d635b452SWinson Wang - Sun Microsystems - Beijing China /* Disable tx's machine */
735d635b452SWinson Wang - Sun Microsystems - Beijing China tx_en.val = nge_reg_get8(ngep, NGE_TX_EN);
736d635b452SWinson Wang - Sun Microsystems - Beijing China tx_en.bits.tx_en = NGE_CLEAR;
737d635b452SWinson Wang - Sun Microsystems - Beijing China nge_reg_put8(ngep, NGE_TX_EN, tx_en.val);
7386f3e57acSmx
7396f3e57acSmx /*
7406f3e57acSmx * Clean the status of tx's state machine
7416f3e57acSmx * and Make assure the tx's channel is idle
7426f3e57acSmx */
7436f3e57acSmx tx_sta.sta_val = nge_reg_get32(ngep, NGE_TX_STA);
7446f3e57acSmx for (tries = 0; tries < 1000; tries++) {
7456f3e57acSmx if (tx_sta.sta_bits.tx_chan_sta == NGE_CLEAR)
7466f3e57acSmx break;
7476f3e57acSmx drv_usecwait(10);
7486f3e57acSmx tx_sta.sta_val = nge_reg_get32(ngep, NGE_TX_STA);
7496f3e57acSmx }
7506f3e57acSmx if (tries == 1000) {
751a01a4735SWinson Wang - Sun Microsystems - Beijing China ngep->nge_chip_state = NGE_CHIP_ERROR;
7526f3e57acSmx return (DDI_FAILURE);
7536f3e57acSmx }
7546f3e57acSmx nge_reg_put32(ngep, NGE_TX_STA, tx_sta.sta_val);
7556f3e57acSmx
7566f3e57acSmx /*
7576f3e57acSmx * Clean the status of rx's state machine
7586f3e57acSmx * and Make assure the tx's channel is idle
7596f3e57acSmx */
7606f3e57acSmx rx_sta.sta_val = nge_reg_get32(ngep, NGE_RX_STA);
7616f3e57acSmx for (tries = 0; tries < 1000; tries++) {
7626f3e57acSmx if (rx_sta.sta_bits.rx_chan_sta == NGE_CLEAR)
7636f3e57acSmx break;
7646f3e57acSmx drv_usecwait(10);
7656f3e57acSmx rx_sta.sta_val = nge_reg_get32(ngep, NGE_RX_STA);
7666f3e57acSmx }
7676f3e57acSmx if (tries == 1000) {
768a01a4735SWinson Wang - Sun Microsystems - Beijing China ngep->nge_chip_state = NGE_CHIP_ERROR;
7696f3e57acSmx return (DDI_FAILURE);
7706f3e57acSmx }
7716f3e57acSmx nge_reg_put32(ngep, NGE_RX_STA, rx_sta.sta_val);
7726f3e57acSmx
7739ae6bcf1Sjj /* Disable auto-poll of rx's state machine */
7749ae6bcf1Sjj rx_poll.poll_val = nge_reg_get32(ngep, NGE_RX_POLL);
7759ae6bcf1Sjj rx_poll.poll_bits.rpen = NGE_CLEAR;
7769ae6bcf1Sjj rx_poll.poll_bits.rpi = NGE_CLEAR;
7779ae6bcf1Sjj nge_reg_put32(ngep, NGE_RX_POLL, rx_poll.poll_val);
7789ae6bcf1Sjj
7799ae6bcf1Sjj /* Disable auto-polling of tx's state machine */
7809ae6bcf1Sjj tx_poll.poll_val = nge_reg_get32(ngep, NGE_TX_POLL);
7819ae6bcf1Sjj tx_poll.poll_bits.tpen = NGE_CLEAR;
7829ae6bcf1Sjj tx_poll.poll_bits.tpi = NGE_CLEAR;
7839ae6bcf1Sjj nge_reg_put32(ngep, NGE_TX_POLL, tx_poll.poll_val);
7849ae6bcf1Sjj
7859ae6bcf1Sjj /* Restore buffer management */
7869ae6bcf1Sjj mode.mode_val = nge_reg_get32(ngep, NGE_MODE_CNTL);
7879ae6bcf1Sjj mode.mode_bits.bm_reset = NGE_SET;
7889ae6bcf1Sjj mode.mode_bits.tx_rcom_en = NGE_SET;
7899ae6bcf1Sjj nge_reg_put32(ngep, NGE_MODE_CNTL, mode.mode_val);
7909ae6bcf1Sjj
7919ae6bcf1Sjj if (ngep->dev_spec_param.advanced_pm) {
7926f3e57acSmx
7936f3e57acSmx nge_reg_put32(ngep, NGE_PMU_CIDLE_LIMIT, 0);
7946f3e57acSmx nge_reg_put32(ngep, NGE_PMU_DIDLE_LIMIT, 0);
7956f3e57acSmx
7966f3e57acSmx pmu_cntl2.cntl2_val = nge_reg_get32(ngep, NGE_PMU_CNTL2);
7976f3e57acSmx pmu_cntl2.cntl2_bits.cidle_timer = NGE_CLEAR;
7986f3e57acSmx pmu_cntl2.cntl2_bits.didle_timer = NGE_CLEAR;
7996f3e57acSmx nge_reg_put32(ngep, NGE_PMU_CNTL2, pmu_cntl2.cntl2_val);
8006f3e57acSmx }
8016f3e57acSmx if (fault)
8026f3e57acSmx ngep->nge_chip_state = NGE_CHIP_FAULT;
8036f3e57acSmx else
8046f3e57acSmx ngep->nge_chip_state = NGE_CHIP_STOPPED;
8056f3e57acSmx
8066f3e57acSmx return (err);
8076f3e57acSmx }
8086f3e57acSmx
8096f3e57acSmx static void
nge_rx_setup(nge_t * ngep)8106f3e57acSmx nge_rx_setup(nge_t *ngep)
8116f3e57acSmx {
8126f3e57acSmx uint64_t desc_addr;
8136f3e57acSmx nge_rxtx_dlen dlen;
8146f3e57acSmx nge_rx_poll rx_poll;
8156f3e57acSmx
8166f3e57acSmx /*
8176f3e57acSmx * Filling the address and length of rx's descriptors
8186f3e57acSmx */
8196f3e57acSmx desc_addr = ngep->recv->desc.cookie.dmac_laddress;
8206f3e57acSmx nge_reg_put32(ngep, NGE_RX_DADR, desc_addr);
8216f3e57acSmx nge_reg_put32(ngep, NGE_RX_DADR_HI, desc_addr >> 32);
8226f3e57acSmx dlen.dlen_val = nge_reg_get32(ngep, NGE_RXTX_DLEN);
8236f3e57acSmx dlen.dlen_bits.rdlen = ngep->recv->desc.nslots - 1;
8246f3e57acSmx nge_reg_put32(ngep, NGE_RXTX_DLEN, dlen.dlen_val);
8256f3e57acSmx
8266f3e57acSmx rx_poll.poll_val = nge_reg_get32(ngep, NGE_RX_POLL);
8276f3e57acSmx rx_poll.poll_bits.rpi = RX_POLL_INTV_1G;
8286f3e57acSmx rx_poll.poll_bits.rpen = NGE_SET;
8296f3e57acSmx nge_reg_put32(ngep, NGE_RX_POLL, rx_poll.poll_val);
8306f3e57acSmx }
8316f3e57acSmx
8326f3e57acSmx static void
nge_tx_setup(nge_t * ngep)8336f3e57acSmx nge_tx_setup(nge_t *ngep)
8346f3e57acSmx {
8356f3e57acSmx uint64_t desc_addr;
8366f3e57acSmx nge_rxtx_dlen dlen;
8376f3e57acSmx
8386f3e57acSmx /*
8396f3e57acSmx * Filling the address and length of tx's descriptors
8406f3e57acSmx */
8416f3e57acSmx desc_addr = ngep->send->desc.cookie.dmac_laddress;
8426f3e57acSmx nge_reg_put32(ngep, NGE_TX_DADR, desc_addr);
8436f3e57acSmx nge_reg_put32(ngep, NGE_TX_DADR_HI, desc_addr >> 32);
8446f3e57acSmx dlen.dlen_val = nge_reg_get32(ngep, NGE_RXTX_DLEN);
8456f3e57acSmx dlen.dlen_bits.tdlen = ngep->send->desc.nslots - 1;
8466f3e57acSmx nge_reg_put32(ngep, NGE_RXTX_DLEN, dlen.dlen_val);
8476f3e57acSmx }
8486f3e57acSmx
8496f3e57acSmx static int
nge_buff_setup(nge_t * ngep)8506f3e57acSmx nge_buff_setup(nge_t *ngep)
8516f3e57acSmx {
8526f3e57acSmx nge_mode_cntl mode_cntl;
8536f3e57acSmx nge_dev_spec_param_t *dev_param_p;
8546f3e57acSmx
8556f3e57acSmx dev_param_p = &ngep->dev_spec_param;
8566f3e57acSmx
8576f3e57acSmx /*
8586f3e57acSmx * Configure Rx&Tx's buffer
8596f3e57acSmx */
8606f3e57acSmx nge_rx_setup(ngep);
8616f3e57acSmx nge_tx_setup(ngep);
8626f3e57acSmx
8636f3e57acSmx /*
8646f3e57acSmx * Configure buffer attribute
8656f3e57acSmx */
8666f3e57acSmx mode_cntl.mode_val = nge_reg_get32(ngep, NGE_MODE_CNTL);
8676f3e57acSmx
8686f3e57acSmx /*
8696f3e57acSmx * Enable Dma access request
8706f3e57acSmx */
8716f3e57acSmx mode_cntl.mode_bits.dma_dis = NGE_CLEAR;
8726f3e57acSmx
8736f3e57acSmx /*
8746f3e57acSmx * Enbale Buffer management
8756f3e57acSmx */
8766f3e57acSmx mode_cntl.mode_bits.bm_reset = NGE_CLEAR;
8776f3e57acSmx
8786f3e57acSmx /*
8796f3e57acSmx * Support Standoffload Descriptor
8806f3e57acSmx */
8816f3e57acSmx mode_cntl.mode_bits.desc_type = ngep->desc_mode;
8826f3e57acSmx
8836f3e57acSmx /*
8846f3e57acSmx * Support receive hardware checksum
8856f3e57acSmx */
8866f3e57acSmx if (dev_param_p->rx_hw_checksum) {
8876f3e57acSmx mode_cntl.mode_bits.rx_sum_en = NGE_SET;
8886f3e57acSmx } else
8896f3e57acSmx mode_cntl.mode_bits.rx_sum_en = NGE_CLEAR;
8906f3e57acSmx
8916f3e57acSmx /*
8926f3e57acSmx * Disable Tx PRD coarse update
8936f3e57acSmx */
8946f3e57acSmx mode_cntl.mode_bits.tx_prd_cu_en = NGE_CLEAR;
8956f3e57acSmx
8966f3e57acSmx /*
8976f3e57acSmx * Disable 64-byte access
8986f3e57acSmx */
8996f3e57acSmx mode_cntl.mode_bits.w64_dis = NGE_SET;
9006f3e57acSmx
9016f3e57acSmx /*
9026f3e57acSmx * Skip Rx Error Frame is not supported and if
9036f3e57acSmx * enable it, jumbo frame does not work any more.
9046f3e57acSmx */
9056f3e57acSmx mode_cntl.mode_bits.rx_filter_en = NGE_CLEAR;
9066f3e57acSmx
9076f3e57acSmx /*
9086f3e57acSmx * Can not support hot mode now
9096f3e57acSmx */
9106f3e57acSmx mode_cntl.mode_bits.resv15 = NGE_CLEAR;
9116f3e57acSmx
9126f3e57acSmx if (dev_param_p->vlan) {
9136f3e57acSmx /* Disable the vlan strip for devices which support vlan */
9146f3e57acSmx mode_cntl.mode_bits.vlan_strip = NGE_CLEAR;
9156f3e57acSmx
9166f3e57acSmx /* Disable the vlan insert for devices which supprot vlan */
9176f3e57acSmx mode_cntl.mode_bits.vlan_ins = NGE_CLEAR;
9186f3e57acSmx }
9196f3e57acSmx
9206f3e57acSmx if (dev_param_p->tx_rx_64byte) {
9216f3e57acSmx
9226f3e57acSmx /* Set the maximum TX PRD fetch size to 64 bytes */
9236f3e57acSmx mode_cntl.mode_bits.tx_fetch_prd = NGE_SET;
9246f3e57acSmx
9256f3e57acSmx /* Set the maximum RX PRD fetch size to 64 bytes */
9266f3e57acSmx mode_cntl.mode_bits.rx_fetch_prd = NGE_SET;
9276f3e57acSmx }
9286f3e57acSmx /*
9296f3e57acSmx * Upload Rx data as it arrives, rather than waiting for full frame
9306f3e57acSmx */
9316f3e57acSmx mode_cntl.mode_bits.resv16 = NGE_CLEAR;
9326f3e57acSmx
9336f3e57acSmx /*
9346f3e57acSmx * Normal HOT table accesses
9356f3e57acSmx */
9366f3e57acSmx mode_cntl.mode_bits.resv17 = NGE_CLEAR;
9376f3e57acSmx
9386f3e57acSmx /*
9396f3e57acSmx * Normal HOT buffer requesting
9406f3e57acSmx */
9416f3e57acSmx mode_cntl.mode_bits.resv18 = NGE_CLEAR;
9426f3e57acSmx nge_reg_put32(ngep, NGE_MODE_CNTL, mode_cntl.mode_val);
9436f3e57acSmx
9446f3e57acSmx /*
9456f3e57acSmx * Signal controller to check for new Rx descriptors
9466f3e57acSmx */
9476f3e57acSmx mode_cntl.mode_val = nge_reg_get32(ngep, NGE_MODE_CNTL);
9486f3e57acSmx mode_cntl.mode_bits.rxdm = NGE_SET;
9496f3e57acSmx mode_cntl.mode_bits.tx_rcom_en = NGE_SET;
9506f3e57acSmx nge_reg_put32(ngep, NGE_MODE_CNTL, mode_cntl.mode_val);
9516f3e57acSmx
9526f3e57acSmx
9536f3e57acSmx return (DDI_SUCCESS);
9546f3e57acSmx }
9556f3e57acSmx
9566f3e57acSmx /*
9576f3e57acSmx * When chipset resets, the chipset can not restore the orignial
9586f3e57acSmx * mac address to the mac address registers.
9596f3e57acSmx *
9606f3e57acSmx * When the driver is dettached, the function will write the orignial
9616f3e57acSmx * mac address to the mac address registers.
9626f3e57acSmx */
9636f3e57acSmx
9646f3e57acSmx void
nge_restore_mac_addr(nge_t * ngep)9656f3e57acSmx nge_restore_mac_addr(nge_t *ngep)
9666f3e57acSmx {
9676f3e57acSmx uint32_t mac_addr;
9686f3e57acSmx
9696f3e57acSmx mac_addr = (uint32_t)ngep->chipinfo.hw_mac_addr;
9706f3e57acSmx nge_reg_put32(ngep, NGE_UNI_ADDR0, mac_addr);
9716f3e57acSmx mac_addr = (uint32_t)(ngep->chipinfo.hw_mac_addr >> 32);
9726f3e57acSmx nge_reg_put32(ngep, NGE_UNI_ADDR1, mac_addr);
9736f3e57acSmx }
9746f3e57acSmx
9756f3e57acSmx int
nge_chip_reset(nge_t * ngep)9766f3e57acSmx nge_chip_reset(nge_t *ngep)
9776f3e57acSmx {
9786f3e57acSmx int err;
9796f3e57acSmx uint8_t i;
9806f3e57acSmx uint32_t regno;
981d27d4a13SMiles Xu, Sun Microsystems uint64_t mac = 0;
9826f3e57acSmx nge_uni_addr1 uaddr1;
9836f3e57acSmx nge_cp_cntl ee_cntl;
9846f3e57acSmx nge_soft_misc soft_misc;
9856f3e57acSmx nge_pmu_cntl0 pmu_cntl0;
9866f3e57acSmx nge_pmu_cntl2 pmu_cntl2;
9876f3e57acSmx nge_pm_cntl2 pm_cntl2;
9886f3e57acSmx const nge_ksindex_t *ksip;
9896f3e57acSmx
9906f3e57acSmx NGE_TRACE(("nge_chip_reset($%p)", (void *)ngep));
9916f3e57acSmx
9926f3e57acSmx /*
9936f3e57acSmx * Clear the statistics by reading the statistics register
9946f3e57acSmx */
9956f3e57acSmx for (ksip = nge_statistics; ksip->name != NULL; ++ksip) {
9966f3e57acSmx regno = KS_BASE + ksip->index * sizeof (uint32_t);
9976f3e57acSmx (void) nge_reg_get32(ngep, regno);
9986f3e57acSmx }
9996f3e57acSmx
10006f3e57acSmx /*
10016f3e57acSmx * Setup seeprom control
10026f3e57acSmx */
10036f3e57acSmx ee_cntl.cntl_val = nge_reg_get32(ngep, NGE_EP_CNTL);
10046f3e57acSmx ee_cntl.cntl_bits.clkdiv = EEPROM_CLKDIV;
10056f3e57acSmx ee_cntl.cntl_bits.rom_size = EEPROM_32K;
10066f3e57acSmx ee_cntl.cntl_bits.word_wid = ACCESS_16BIT;
10076f3e57acSmx ee_cntl.cntl_bits.wait_slots = EEPROM_WAITCLK;
10086f3e57acSmx nge_reg_put32(ngep, NGE_EP_CNTL, ee_cntl.cntl_val);
10096f3e57acSmx
10106f3e57acSmx /*
10116f3e57acSmx * Reading the unicast mac address table
10126f3e57acSmx */
10136f3e57acSmx if (ngep->nge_chip_state == NGE_CHIP_INITIAL) {
10146f3e57acSmx uaddr1.addr_val = nge_reg_get32(ngep, NGE_UNI_ADDR1);
10156f3e57acSmx mac = uaddr1.addr_bits.addr;
10166f3e57acSmx mac <<= 32;
10176f3e57acSmx mac |= nge_reg_get32(ngep, NGE_UNI_ADDR0);
101815c07adcSJohn Levon ngep->chipinfo.hw_mac_addr = mac;
101915c07adcSJohn Levon if (ngep->dev_spec_param.mac_addr_order) {
102015c07adcSJohn Levon for (i = 0; i < ETHERADDRL; i++) {
102115c07adcSJohn Levon ngep->chipinfo.vendor_addr.addr[i] =
102215c07adcSJohn Levon (uchar_t)mac;
102315c07adcSJohn Levon ngep->cur_uni_addr.addr[i] =
102415c07adcSJohn Levon (uchar_t)mac;
102515c07adcSJohn Levon mac >>= 8;
10266f3e57acSmx }
102715c07adcSJohn Levon } else {
102815c07adcSJohn Levon for (i = ETHERADDRL; i-- != 0; ) {
102915c07adcSJohn Levon ngep->chipinfo.vendor_addr.addr[i] =
103015c07adcSJohn Levon (uchar_t)mac;
103115c07adcSJohn Levon ngep->cur_uni_addr.addr[i] =
103215c07adcSJohn Levon (uchar_t)mac;
103315c07adcSJohn Levon mac >>= 8;
103415c07adcSJohn Levon }
103515c07adcSJohn Levon }
103615c07adcSJohn Levon ngep->chipinfo.vendor_addr.set = 1;
10376f3e57acSmx }
10386f3e57acSmx pci_config_put8(ngep->cfg_handle, PCI_CONF_CACHE_LINESZ,
10396f3e57acSmx ngep->chipinfo.clsize);
10406f3e57acSmx pci_config_put8(ngep->cfg_handle, PCI_CONF_LATENCY_TIMER,
10416f3e57acSmx ngep->chipinfo.latency);
10426f3e57acSmx
10439ae6bcf1Sjj
10449ae6bcf1Sjj if (ngep->dev_spec_param.advanced_pm) {
10456f3e57acSmx
10466f3e57acSmx /* Program software misc register */
10476f3e57acSmx soft_misc.misc_val = nge_reg_get32(ngep, NGE_SOFT_MISC);
10486f3e57acSmx soft_misc.misc_bits.rx_clk_vx_rst = NGE_SET;
10496f3e57acSmx soft_misc.misc_bits.tx_clk_vx_rst = NGE_SET;
10506f3e57acSmx soft_misc.misc_bits.clk12m_vx_rst = NGE_SET;
10516f3e57acSmx soft_misc.misc_bits.fpci_clk_vx_rst = NGE_SET;
10526f3e57acSmx soft_misc.misc_bits.rx_clk_vc_rst = NGE_SET;
10536f3e57acSmx soft_misc.misc_bits.tx_clk_vc_rst = NGE_SET;
10546f3e57acSmx soft_misc.misc_bits.fs_clk_vc_rst = NGE_SET;
10556f3e57acSmx soft_misc.misc_bits.rst_ex_m2pintf = NGE_SET;
10566f3e57acSmx nge_reg_put32(ngep, NGE_SOFT_MISC, soft_misc.misc_val);
10576f3e57acSmx
10589ae6bcf1Sjj /* wait for 32 us */
10599ae6bcf1Sjj drv_usecwait(32);
10606f3e57acSmx
10616f3e57acSmx soft_misc.misc_val = nge_reg_get32(ngep, NGE_SOFT_MISC);
10626f3e57acSmx soft_misc.misc_bits.rx_clk_vx_rst = NGE_CLEAR;
10636f3e57acSmx soft_misc.misc_bits.tx_clk_vx_rst = NGE_CLEAR;
10646f3e57acSmx soft_misc.misc_bits.clk12m_vx_rst = NGE_CLEAR;
10656f3e57acSmx soft_misc.misc_bits.fpci_clk_vx_rst = NGE_CLEAR;
10666f3e57acSmx soft_misc.misc_bits.rx_clk_vc_rst = NGE_CLEAR;
10676f3e57acSmx soft_misc.misc_bits.tx_clk_vc_rst = NGE_CLEAR;
10686f3e57acSmx soft_misc.misc_bits.fs_clk_vc_rst = NGE_CLEAR;
10696f3e57acSmx soft_misc.misc_bits.rst_ex_m2pintf = NGE_CLEAR;
10706f3e57acSmx nge_reg_put32(ngep, NGE_SOFT_MISC, soft_misc.misc_val);
10716f3e57acSmx
10726f3e57acSmx /* Program PMU registers */
10736f3e57acSmx pmu_cntl0.cntl0_val = nge_reg_get32(ngep, NGE_PMU_CNTL0);
10746f3e57acSmx pmu_cntl0.cntl0_bits.core_spd10_fp =
10756f3e57acSmx NGE_PMU_CORE_SPD10_BUSY;
10766f3e57acSmx pmu_cntl0.cntl0_bits.core_spd10_idle =
10776f3e57acSmx NGE_PMU_CORE_SPD10_IDLE;
10786f3e57acSmx pmu_cntl0.cntl0_bits.core_spd100_fp =
10796f3e57acSmx NGE_PMU_CORE_SPD100_BUSY;
10806f3e57acSmx pmu_cntl0.cntl0_bits.core_spd100_idle =
10816f3e57acSmx NGE_PMU_CORE_SPD100_IDLE;
10826f3e57acSmx pmu_cntl0.cntl0_bits.core_spd1000_fp =
10836f3e57acSmx NGE_PMU_CORE_SPD1000_BUSY;
10846f3e57acSmx pmu_cntl0.cntl0_bits.core_spd1000_idle =
10856f3e57acSmx NGE_PMU_CORE_SPD100_IDLE;
10866f3e57acSmx pmu_cntl0.cntl0_bits.core_spd10_idle =
10876f3e57acSmx NGE_PMU_CORE_SPD10_IDLE;
10886f3e57acSmx nge_reg_put32(ngep, NGE_PMU_CNTL0, pmu_cntl0.cntl0_val);
10896f3e57acSmx
10906f3e57acSmx /* Set the core idle limit value */
10916f3e57acSmx nge_reg_put32(ngep, NGE_PMU_CIDLE_LIMIT,
10926f3e57acSmx NGE_PMU_CIDLE_LIMIT_DEF);
10936f3e57acSmx
10946f3e57acSmx /* Set the device idle limit value */
10956f3e57acSmx nge_reg_put32(ngep, NGE_PMU_DIDLE_LIMIT,
10966f3e57acSmx NGE_PMU_DIDLE_LIMIT_DEF);
10976f3e57acSmx
10986f3e57acSmx /* Enable the core/device idle timer in PMU control 2 */
10996f3e57acSmx pmu_cntl2.cntl2_val = nge_reg_get32(ngep, NGE_PMU_CNTL2);
11006f3e57acSmx pmu_cntl2.cntl2_bits.cidle_timer = NGE_SET;
11016f3e57acSmx pmu_cntl2.cntl2_bits.didle_timer = NGE_SET;
11026f3e57acSmx pmu_cntl2.cntl2_bits.core_enable = NGE_SET;
11036f3e57acSmx pmu_cntl2.cntl2_bits.dev_enable = NGE_SET;
11046f3e57acSmx nge_reg_put32(ngep, NGE_PMU_CNTL2, pmu_cntl2.cntl2_val);
11056f3e57acSmx }
11069ae6bcf1Sjj /*
11079ae6bcf1Sjj * Stop the chipset and clear buffer management
11089ae6bcf1Sjj */
11099ae6bcf1Sjj err = nge_chip_stop(ngep, B_FALSE);
11109ae6bcf1Sjj if (err == DDI_FAILURE)
11119ae6bcf1Sjj return (err);
11126f3e57acSmx /*
11136f3e57acSmx * Clear the power state bits for phy since interface no longer
11146f3e57acSmx * works after rebooting from Windows on a multi-boot machine
11156f3e57acSmx */
11166f3e57acSmx if (ngep->chipinfo.device == DEVICE_ID_MCP51_268 ||
11176f3e57acSmx ngep->chipinfo.device == DEVICE_ID_MCP51_269 ||
11186f3e57acSmx ngep->chipinfo.device == DEVICE_ID_MCP55_372 ||
11196f3e57acSmx ngep->chipinfo.device == DEVICE_ID_MCP55_373 ||
11206f3e57acSmx ngep->chipinfo.device == DEVICE_ID_MCP61_3EE ||
1121a01a4735SWinson Wang - Sun Microsystems - Beijing China ngep->chipinfo.device == DEVICE_ID_MCP61_3EF ||
11229fa05d92SWinson Wang - Sun Microsystems - Beijing China ngep->chipinfo.device == DEVICE_ID_MCP77_760 ||
11239fa05d92SWinson Wang - Sun Microsystems - Beijing China ngep->chipinfo.device == DEVICE_ID_MCP79_AB0) {
11246f3e57acSmx
11256f3e57acSmx pm_cntl2.cntl_val = nge_reg_get32(ngep, NGE_PM_CNTL2);
11266f3e57acSmx /* bring phy out of coma mode */
11276f3e57acSmx pm_cntl2.cntl_bits.phy_coma_set = NGE_CLEAR;
11286f3e57acSmx /* disable auto reset coma bits */
11296f3e57acSmx pm_cntl2.cntl_bits.resv4 = NGE_CLEAR;
11306f3e57acSmx /* restore power to gated clocks */
11316f3e57acSmx pm_cntl2.cntl_bits.resv8_11 = NGE_CLEAR;
11326f3e57acSmx nge_reg_put32(ngep, NGE_PM_CNTL2, pm_cntl2.cntl_val);
11336f3e57acSmx }
11346f3e57acSmx
11356f3e57acSmx ngep->nge_chip_state = NGE_CHIP_RESET;
11366f3e57acSmx return (DDI_SUCCESS);
11376f3e57acSmx }
11386f3e57acSmx
11396f3e57acSmx int
nge_chip_start(nge_t * ngep)11406f3e57acSmx nge_chip_start(nge_t *ngep)
11416f3e57acSmx {
11426f3e57acSmx int err;
11436f3e57acSmx nge_itc itc;
11446f3e57acSmx nge_tx_cntl tx_cntl;
11456f3e57acSmx nge_rx_cntrl0 rx_cntl0;
11466f3e57acSmx nge_rx_cntl1 rx_cntl1;
11476f3e57acSmx nge_tx_en tx_en;
11486f3e57acSmx nge_rx_en rx_en;
11496f3e57acSmx nge_mii_cs mii_cs;
11506f3e57acSmx nge_swtr_cntl swtr_cntl;
11516f3e57acSmx nge_rx_fifo_wm rx_fifo;
11526f3e57acSmx nge_intr_mask intr_mask;
11536f3e57acSmx nge_mintr_mask mintr_mask;
11546f3e57acSmx nge_dev_spec_param_t *dev_param_p;
11556f3e57acSmx
11566f3e57acSmx NGE_TRACE(("nge_chip_start($%p)", (void *)ngep));
11576f3e57acSmx
11586f3e57acSmx /*
11596f3e57acSmx * Setup buffer management
11606f3e57acSmx */
11616f3e57acSmx err = nge_buff_setup(ngep);
11626f3e57acSmx if (err == DDI_FAILURE)
11636f3e57acSmx return (err);
11646f3e57acSmx
11656f3e57acSmx dev_param_p = &ngep->dev_spec_param;
11666f3e57acSmx
11676f3e57acSmx /*
11686f3e57acSmx * Enable polling attribute
11696f3e57acSmx */
11706f3e57acSmx mii_cs.cs_val = nge_reg_get32(ngep, NGE_MII_CS);
11716f3e57acSmx mii_cs.cs_bits.ap_paddr = ngep->phy_xmii_addr;
11726f3e57acSmx mii_cs.cs_bits.ap_en = NGE_SET;
11736f3e57acSmx mii_cs.cs_bits.ap_intv = MII_POLL_INTV;
11746f3e57acSmx nge_reg_put32(ngep, NGE_MII_CS, mii_cs.cs_val);
11756f3e57acSmx
11766f3e57acSmx /*
11776f3e57acSmx * Setup link
11786f3e57acSmx */
11796f3e57acSmx (*ngep->physops->phys_update)(ngep);
11806f3e57acSmx
11816f3e57acSmx /*
11826f3e57acSmx * Configure the tx's parameters
11836f3e57acSmx */
11846f3e57acSmx tx_cntl.cntl_val = nge_reg_get32(ngep, NGE_TX_CNTL);
11856f3e57acSmx if (dev_param_p->tx_pause_frame)
11866f3e57acSmx tx_cntl.cntl_bits.paen = NGE_SET;
11876f3e57acSmx else
11886f3e57acSmx tx_cntl.cntl_bits.paen = NGE_CLEAR;
11896f3e57acSmx tx_cntl.cntl_bits.retry_en = NGE_SET;
11906f3e57acSmx tx_cntl.cntl_bits.pad_en = NGE_SET;
11916f3e57acSmx tx_cntl.cntl_bits.fappend_en = NGE_SET;
11926f3e57acSmx tx_cntl.cntl_bits.two_def_en = NGE_SET;
11936f3e57acSmx tx_cntl.cntl_bits.max_retry = 15;
11946f3e57acSmx tx_cntl.cntl_bits.burst_en = NGE_CLEAR;
11956f3e57acSmx tx_cntl.cntl_bits.uflo_err_mask = NGE_CLEAR;
11966f3e57acSmx tx_cntl.cntl_bits.tlcol_mask = NGE_CLEAR;
11976f3e57acSmx tx_cntl.cntl_bits.lcar_mask = NGE_CLEAR;
11986f3e57acSmx tx_cntl.cntl_bits.def_mask = NGE_CLEAR;
11996f3e57acSmx tx_cntl.cntl_bits.exdef_mask = NGE_SET;
12006f3e57acSmx tx_cntl.cntl_bits.lcar_mask = NGE_SET;
12016f3e57acSmx tx_cntl.cntl_bits.tlcol_mask = NGE_SET;
12026f3e57acSmx tx_cntl.cntl_bits.uflo_err_mask = NGE_SET;
12036f3e57acSmx tx_cntl.cntl_bits.jam_seq_en = NGE_CLEAR;
12046f3e57acSmx nge_reg_put32(ngep, NGE_TX_CNTL, tx_cntl.cntl_val);
12056f3e57acSmx
12066f3e57acSmx
12076f3e57acSmx /*
12086f3e57acSmx * Configure the parameters of Rx's state machine
12096f3e57acSmx * Enabe the parameters:
12106f3e57acSmx * 1). Pad Strip
12116f3e57acSmx * 2). FCS Relay
12126f3e57acSmx * 3). Pause
12136f3e57acSmx * 4). Address filter
12146f3e57acSmx * 5). Runt Packet receive
12156f3e57acSmx * 6). Broadcast
12166f3e57acSmx * 7). Receive Deferral
12176f3e57acSmx *
12186f3e57acSmx * Disable the following parameters for decreasing
12196f3e57acSmx * the number of interrupts:
12206f3e57acSmx * 1). Runt Inerrupt.
12216f3e57acSmx * 2). Rx's Late Collision interrupt.
12226f3e57acSmx * 3). Rx's Max length Error Interrupt.
12236f3e57acSmx * 4). Rx's Length Field error Interrupt.
12246f3e57acSmx * 5). Rx's FCS error interrupt.
12256f3e57acSmx * 6). Rx's overflow error interrupt.
12266f3e57acSmx * 7). Rx's Frame alignment error interrupt.
12276f3e57acSmx */
12286f3e57acSmx rx_cntl0.cntl_val = nge_reg_get32(ngep, NGE_RX_CNTL0);
12296f3e57acSmx rx_cntl0.cntl_bits.padsen = NGE_CLEAR;
12306f3e57acSmx rx_cntl0.cntl_bits.fcsren = NGE_CLEAR;
12316f3e57acSmx if (dev_param_p->rx_pause_frame)
12326f3e57acSmx rx_cntl0.cntl_bits.paen = NGE_SET;
12336f3e57acSmx else
12346f3e57acSmx rx_cntl0.cntl_bits.paen = NGE_CLEAR;
12356f3e57acSmx rx_cntl0.cntl_bits.lben = NGE_CLEAR;
12366f3e57acSmx rx_cntl0.cntl_bits.afen = NGE_SET;
12376f3e57acSmx rx_cntl0.cntl_bits.runten = NGE_CLEAR;
12386f3e57acSmx rx_cntl0.cntl_bits.brdis = NGE_CLEAR;
12396f3e57acSmx rx_cntl0.cntl_bits.rdfen = NGE_CLEAR;
12406f3e57acSmx rx_cntl0.cntl_bits.runtm = NGE_CLEAR;
12416f3e57acSmx rx_cntl0.cntl_bits.slfb = NGE_CLEAR;
12426f3e57acSmx rx_cntl0.cntl_bits.rlcolm = NGE_CLEAR;
12436f3e57acSmx rx_cntl0.cntl_bits.maxerm = NGE_CLEAR;
12446f3e57acSmx rx_cntl0.cntl_bits.lferm = NGE_CLEAR;
12456f3e57acSmx rx_cntl0.cntl_bits.crcm = NGE_CLEAR;
12466f3e57acSmx rx_cntl0.cntl_bits.ofolm = NGE_CLEAR;
12476f3e57acSmx rx_cntl0.cntl_bits.framerm = NGE_CLEAR;
12486f3e57acSmx nge_reg_put32(ngep, NGE_RX_CNTL0, rx_cntl0.cntl_val);
12496f3e57acSmx
12506f3e57acSmx /*
12516f3e57acSmx * Configure the watermark for the rx's statemachine
12526f3e57acSmx */
12536f3e57acSmx rx_fifo.wm_val = nge_reg_get32(ngep, NGE_RX_FIFO_WM);
12546f3e57acSmx rx_fifo.wm_bits.data_hwm = ngep->rx_datahwm;
12556f3e57acSmx rx_fifo.wm_bits.prd_lwm = ngep->rx_prdlwm;
12566f3e57acSmx rx_fifo.wm_bits.prd_hwm = ngep->rx_prdhwm;
12576f3e57acSmx nge_reg_put32(ngep, NGE_RX_FIFO_WM, rx_fifo.wm_val);
12586f3e57acSmx
12596f3e57acSmx /*
12606f3e57acSmx * Configure the deffer time slot for rx's state machine
12616f3e57acSmx */
12626f3e57acSmx nge_reg_put8(ngep, NGE_RX_DEf, ngep->rx_def);
12636f3e57acSmx
12646f3e57acSmx /*
12656f3e57acSmx * Configure the length of rx's packet
12666f3e57acSmx */
12676f3e57acSmx rx_cntl1.cntl_val = nge_reg_get32(ngep, NGE_RX_CNTL1);
12686f3e57acSmx rx_cntl1.cntl_bits.length = ngep->max_sdu;
12696f3e57acSmx nge_reg_put32(ngep, NGE_RX_CNTL1, rx_cntl1.cntl_val);
12706f3e57acSmx /*
12716f3e57acSmx * Enable Tx's state machine
12726f3e57acSmx */
12736f3e57acSmx tx_en.val = nge_reg_get8(ngep, NGE_TX_EN);
12746f3e57acSmx tx_en.bits.tx_en = NGE_SET;
12756f3e57acSmx nge_reg_put8(ngep, NGE_TX_EN, tx_en.val);
12766f3e57acSmx
12776f3e57acSmx /*
12786f3e57acSmx * Enable Rx's state machine
12796f3e57acSmx */
12806f3e57acSmx rx_en.val = nge_reg_get8(ngep, NGE_RX_EN);
12816f3e57acSmx rx_en.bits.rx_en = NGE_SET;
12826f3e57acSmx nge_reg_put8(ngep, NGE_RX_EN, rx_en.val);
12836f3e57acSmx
12846f3e57acSmx itc.itc_val = nge_reg_get32(ngep, NGE_SWTR_ITC);
12856f3e57acSmx itc.itc_bits.sw_intv = ngep->sw_intr_intv;
12866f3e57acSmx nge_reg_put32(ngep, NGE_SWTR_ITC, itc.itc_val);
12876f3e57acSmx
12886f3e57acSmx swtr_cntl.ctrl_val = nge_reg_get8(ngep, NGE_SWTR_CNTL);
12896f3e57acSmx swtr_cntl.cntl_bits.sten = NGE_SET;
12906f3e57acSmx swtr_cntl.cntl_bits.stren = NGE_SET;
12916f3e57acSmx nge_reg_put32(ngep, NGE_SWTR_CNTL, swtr_cntl.ctrl_val);
12926f3e57acSmx
12936f3e57acSmx /*
12946f3e57acSmx * Disable all mii read/write operation Interrupt
12956f3e57acSmx */
12966f3e57acSmx mintr_mask.mask_val = nge_reg_get8(ngep, NGE_MINTR_MASK);
12976f3e57acSmx mintr_mask.mask_bits.mrei = NGE_CLEAR;
12986f3e57acSmx mintr_mask.mask_bits.mcc2 = NGE_CLEAR;
12996f3e57acSmx mintr_mask.mask_bits.mcc1 = NGE_CLEAR;
13006f3e57acSmx mintr_mask.mask_bits.mapi = NGE_SET;
13016f3e57acSmx mintr_mask.mask_bits.mpdi = NGE_SET;
13026f3e57acSmx nge_reg_put8(ngep, NGE_MINTR_MASK, mintr_mask.mask_val);
13036f3e57acSmx
13046f3e57acSmx /*
13056f3e57acSmx * Enable all interrupt event
13066f3e57acSmx */
13076f3e57acSmx intr_mask.mask_val = nge_reg_get32(ngep, NGE_INTR_MASK);
13086f3e57acSmx intr_mask.mask_bits.reint = NGE_SET;
13096f3e57acSmx intr_mask.mask_bits.rcint = NGE_SET;
13106f3e57acSmx intr_mask.mask_bits.miss = NGE_SET;
131151fc88a8SWinson Wang - Sun Microsystems - Beijing China intr_mask.mask_bits.teint = NGE_SET;
131251fc88a8SWinson Wang - Sun Microsystems - Beijing China intr_mask.mask_bits.tcint = NGE_CLEAR;
13136f3e57acSmx intr_mask.mask_bits.stint = NGE_CLEAR;
13146f3e57acSmx intr_mask.mask_bits.mint = NGE_CLEAR;
13156f3e57acSmx intr_mask.mask_bits.rfint = NGE_CLEAR;
131651fc88a8SWinson Wang - Sun Microsystems - Beijing China intr_mask.mask_bits.tfint = NGE_SET;
13176f3e57acSmx intr_mask.mask_bits.feint = NGE_SET;
13186f3e57acSmx intr_mask.mask_bits.resv10 = NGE_CLEAR;
13196f3e57acSmx intr_mask.mask_bits.resv11 = NGE_CLEAR;
13206f3e57acSmx intr_mask.mask_bits.resv12 = NGE_CLEAR;
13216f3e57acSmx intr_mask.mask_bits.resv13 = NGE_CLEAR;
13226f3e57acSmx intr_mask.mask_bits.phyint = NGE_CLEAR;
13236f3e57acSmx ngep->intr_masks = intr_mask.mask_val;
13246f3e57acSmx nge_reg_put32(ngep, NGE_INTR_MASK, intr_mask.mask_val);
13256f3e57acSmx ngep->nge_chip_state = NGE_CHIP_RUNNING;
13266f3e57acSmx return (DDI_SUCCESS);
13276f3e57acSmx }
13286f3e57acSmx
13296f3e57acSmx /*
13306f3e57acSmx * nge_chip_sync() -- program the chip with the unicast MAC address,
13316f3e57acSmx * the multicast hash table, the required level of promiscuity.
13326f3e57acSmx */
13336f3e57acSmx void
nge_chip_sync(nge_t * ngep)13346f3e57acSmx nge_chip_sync(nge_t *ngep)
13356f3e57acSmx {
13366f3e57acSmx uint8_t i;
13376f3e57acSmx uint64_t macaddr;
13386f3e57acSmx uint64_t mul_addr;
13396f3e57acSmx uint64_t mul_mask;
13406f3e57acSmx nge_rx_cntrl0 rx_cntl;
13416f3e57acSmx nge_uni_addr1 uni_adr1;
13426f3e57acSmx
13436f3e57acSmx NGE_TRACE(("nge_chip_sync($%p)", (void *)ngep));
13446f3e57acSmx
13456f3e57acSmx macaddr = 0x0ull;
13466f3e57acSmx mul_addr = 0x0ull;
13476f3e57acSmx mul_mask = 0x0ull;
13486f3e57acSmx rx_cntl.cntl_val = nge_reg_get32(ngep, NGE_RX_CNTL0);
13496f3e57acSmx
13506f3e57acSmx if (ngep->promisc) {
13516f3e57acSmx rx_cntl.cntl_bits.afen = NGE_CLEAR;
13526f3e57acSmx rx_cntl.cntl_bits.brdis = NGE_SET;
13536f3e57acSmx } else {
13546f3e57acSmx rx_cntl.cntl_bits.afen = NGE_SET;
13556f3e57acSmx rx_cntl.cntl_bits.brdis = NGE_CLEAR;
13566f3e57acSmx }
13576f3e57acSmx
13586f3e57acSmx /*
13596f3e57acSmx * Transform the MAC address from host to chip format, the unicast
13606f3e57acSmx * MAC address(es) ...
13616f3e57acSmx */
13626f3e57acSmx for (i = ETHERADDRL, macaddr = 0ull; i != 0; --i) {
13636f3e57acSmx macaddr |= ngep->cur_uni_addr.addr[i-1];
13646f3e57acSmx macaddr <<= (i > 1) ? 8 : 0;
13656f3e57acSmx }
13666f3e57acSmx
13676f3e57acSmx nge_reg_put32(ngep, NGE_UNI_ADDR0, (uint32_t)macaddr);
13686f3e57acSmx macaddr = macaddr >>32;
13696f3e57acSmx uni_adr1.addr_val = nge_reg_get32(ngep, NGE_UNI_ADDR1);
13706f3e57acSmx uni_adr1.addr_bits.addr = (uint16_t)macaddr;
13716f3e57acSmx uni_adr1.addr_bits.resv16_31 = (uint16_t)0;
13726f3e57acSmx nge_reg_put32(ngep, NGE_UNI_ADDR1, uni_adr1.addr_val);
13736f3e57acSmx
13746f3e57acSmx /*
13756f3e57acSmx * Reprogram the multicast address table ...
13766f3e57acSmx */
13776f3e57acSmx for (i = ETHERADDRL, mul_addr = 0ull; i != 0; --i) {
13786f3e57acSmx mul_addr |= ngep->cur_mul_addr.addr[i-1];
13796f3e57acSmx mul_addr <<= (i > 1) ? 8 : 0;
13806f3e57acSmx mul_mask |= ngep->cur_mul_mask.addr[i-1];
13816f3e57acSmx mul_mask <<= (i > 1) ? 8 : 0;
13826f3e57acSmx }
13836f3e57acSmx nge_reg_put32(ngep, NGE_MUL_ADDR0, (uint32_t)mul_addr);
13846f3e57acSmx mul_addr >>= 32;
13856f3e57acSmx nge_reg_put32(ngep, NGE_MUL_ADDR1, mul_addr);
13866f3e57acSmx nge_reg_put32(ngep, NGE_MUL_MASK, (uint32_t)mul_mask);
13876f3e57acSmx mul_mask >>= 32;
13886f3e57acSmx nge_reg_put32(ngep, NGE_MUL_MASK1, mul_mask);
13896f3e57acSmx /*
13906f3e57acSmx * Set or clear the PROMISCUOUS mode bit
13916f3e57acSmx */
13926f3e57acSmx nge_reg_put32(ngep, NGE_RX_CNTL0, rx_cntl.cntl_val);
13936f3e57acSmx /*
13946f3e57acSmx * For internal PHY loopback, the link will
13956f3e57acSmx * not be up, so it need to sync mac modes directly.
13966f3e57acSmx */
13976f3e57acSmx if (ngep->param_loop_mode == NGE_LOOP_INTERNAL_PHY)
13986f3e57acSmx nge_sync_mac_modes(ngep);
13996f3e57acSmx }
14006f3e57acSmx
14016f3e57acSmx static void
nge_chip_err(nge_t * ngep)14026f3e57acSmx nge_chip_err(nge_t *ngep)
14036f3e57acSmx {
14046f3e57acSmx nge_reg010 reg010_ins;
14056f3e57acSmx nge_sw_statistics_t *psw_stat;
14066f3e57acSmx nge_intr_mask intr_mask;
14076f3e57acSmx
14086f3e57acSmx NGE_TRACE(("nge_chip_err($%p)", (void *)ngep));
14096f3e57acSmx
14106f3e57acSmx psw_stat = (nge_sw_statistics_t *)&ngep->statistics.sw_statistics;
14116f3e57acSmx reg010_ins.reg010_val = nge_reg_get32(ngep, NGE_REG010);
14126f3e57acSmx if (reg010_ins.reg010_bits.resv0)
14136f3e57acSmx psw_stat->fe_err.tso_err_mss ++;
14146f3e57acSmx
14156f3e57acSmx if (reg010_ins.reg010_bits.resv1)
14166f3e57acSmx psw_stat->fe_err.tso_dis ++;
14176f3e57acSmx
14186f3e57acSmx if (reg010_ins.reg010_bits.resv2)
14196f3e57acSmx psw_stat->fe_err.tso_err_nosum ++;
14206f3e57acSmx
14216f3e57acSmx if (reg010_ins.reg010_bits.resv3)
14226f3e57acSmx psw_stat->fe_err.tso_err_hov ++;
14236f3e57acSmx
14246f3e57acSmx if (reg010_ins.reg010_bits.resv4)
14256f3e57acSmx psw_stat->fe_err.tso_err_huf ++;
14266f3e57acSmx
14276f3e57acSmx if (reg010_ins.reg010_bits.resv5)
14286f3e57acSmx psw_stat->fe_err.tso_err_l2 ++;
14296f3e57acSmx
14306f3e57acSmx if (reg010_ins.reg010_bits.resv6)
14316f3e57acSmx psw_stat->fe_err.tso_err_ip ++;
14326f3e57acSmx
14336f3e57acSmx if (reg010_ins.reg010_bits.resv7)
14346f3e57acSmx psw_stat->fe_err.tso_err_l4 ++;
14356f3e57acSmx
14366f3e57acSmx if (reg010_ins.reg010_bits.resv8)
14376f3e57acSmx psw_stat->fe_err.tso_err_tcp ++;
14386f3e57acSmx
14396f3e57acSmx if (reg010_ins.reg010_bits.resv9)
14406f3e57acSmx psw_stat->fe_err.hsum_err_ip ++;
14416f3e57acSmx
14426f3e57acSmx if (reg010_ins.reg010_bits.resv10)
14436f3e57acSmx psw_stat->fe_err.hsum_err_l4 ++;
14446f3e57acSmx
14456f3e57acSmx if (reg010_ins.reg010_val != 0) {
14466f3e57acSmx
14476f3e57acSmx /*
14486f3e57acSmx * Fatal error is triggered by malformed driver commands.
14496f3e57acSmx * Disable unless debugging.
14506f3e57acSmx */
14516f3e57acSmx intr_mask.mask_val = nge_reg_get32(ngep, NGE_INTR_MASK);
14526f3e57acSmx intr_mask.mask_bits.feint = NGE_CLEAR;
14536f3e57acSmx nge_reg_put32(ngep, NGE_INTR_MASK, intr_mask.mask_val);
14546f3e57acSmx ngep->intr_masks = intr_mask.mask_val;
14556f3e57acSmx
14566f3e57acSmx }
14576f3e57acSmx }
14586f3e57acSmx
14596f3e57acSmx static void
nge_sync_mac_modes(nge_t * ngep)14606f3e57acSmx nge_sync_mac_modes(nge_t *ngep)
14616f3e57acSmx {
14626f3e57acSmx nge_tx_def tx_def;
14636f3e57acSmx nge_tx_fifo_wm tx_fifo;
14646f3e57acSmx nge_bkoff_cntl bk_cntl;
14656f3e57acSmx nge_mac2phy m2p;
14666f3e57acSmx nge_rx_cntrl0 rx_cntl0;
146786d6718fSLi-Zhen You nge_tx_cntl tx_cntl;
14686f3e57acSmx nge_dev_spec_param_t *dev_param_p;
14696f3e57acSmx
14706f3e57acSmx dev_param_p = &ngep->dev_spec_param;
14716f3e57acSmx
14726f3e57acSmx tx_def.def_val = nge_reg_get32(ngep, NGE_TX_DEF);
14736f3e57acSmx m2p.m2p_val = nge_reg_get32(ngep, NGE_MAC2PHY);
14746f3e57acSmx tx_fifo.wm_val = nge_reg_get32(ngep, NGE_TX_FIFO_WM);
14756f3e57acSmx bk_cntl.cntl_val = nge_reg_get32(ngep, NGE_BKOFF_CNTL);
14766f3e57acSmx bk_cntl.bkoff_bits.rseed = BKOFF_RSEED;
14776f3e57acSmx switch (ngep->param_link_speed) {
14786f3e57acSmx case 10:
14796f3e57acSmx m2p.m2p_bits.speed = low_speed;
14806f3e57acSmx tx_def.def_bits.ifg1_def = TX_IFG1_DEFAULT;
14816f3e57acSmx if (ngep->phy_mode == RGMII_IN) {
14826f3e57acSmx tx_def.def_bits.ifg2_def = TX_IFG2_RGMII_10_100;
14836f3e57acSmx tx_def.def_bits.if_def = TX_IFG_RGMII_OTHER;
14846f3e57acSmx } else {
14856f3e57acSmx tx_def.def_bits.if_def = TX_TIFG_MII;
14866f3e57acSmx tx_def.def_bits.ifg2_def = TX_IFG2_MII;
14876f3e57acSmx }
14886f3e57acSmx tx_fifo.wm_bits.nbfb_wm = TX_FIFO_NOB_WM_MII;
14896f3e57acSmx bk_cntl.bkoff_bits.sltm = BKOFF_SLIM_MII;
14906f3e57acSmx break;
14916f3e57acSmx
14926f3e57acSmx case 100:
14936f3e57acSmx m2p.m2p_bits.speed = fast_speed;
14946f3e57acSmx tx_def.def_bits.ifg1_def = TX_IFG1_DEFAULT;
14956f3e57acSmx if (ngep->phy_mode == RGMII_IN) {
14966f3e57acSmx tx_def.def_bits.ifg2_def = TX_IFG2_RGMII_10_100;
14976f3e57acSmx tx_def.def_bits.if_def = TX_IFG_RGMII_OTHER;
14986f3e57acSmx } else {
14996f3e57acSmx tx_def.def_bits.if_def = TX_TIFG_MII;
15006f3e57acSmx tx_def.def_bits.ifg2_def = TX_IFG2_MII;
15016f3e57acSmx }
15026f3e57acSmx tx_fifo.wm_bits.nbfb_wm = TX_FIFO_NOB_WM_MII;
15036f3e57acSmx bk_cntl.bkoff_bits.sltm = BKOFF_SLIM_MII;
15046f3e57acSmx break;
15056f3e57acSmx
15066f3e57acSmx case 1000:
15076f3e57acSmx m2p.m2p_bits.speed = giga_speed;
15086f3e57acSmx tx_def.def_bits.ifg1_def = TX_IFG1_DEFAULT;
15096f3e57acSmx if (ngep->param_link_duplex == LINK_DUPLEX_FULL) {
15106f3e57acSmx tx_def.def_bits.ifg2_def = TX_IFG2_RGMII_1000;
15116f3e57acSmx tx_def.def_bits.if_def = TX_IFG_RGMII_1000_FD;
15126f3e57acSmx } else {
15136f3e57acSmx tx_def.def_bits.ifg2_def = TX_IFG2_RGMII_1000;
15146f3e57acSmx tx_def.def_bits.if_def = TX_IFG_RGMII_OTHER;
15156f3e57acSmx }
15166f3e57acSmx
15176f3e57acSmx tx_fifo.wm_bits.nbfb_wm = TX_FIFO_NOB_WM_GMII;
15186f3e57acSmx bk_cntl.bkoff_bits.sltm = BKOFF_SLIM_GMII;
15196f3e57acSmx break;
15206f3e57acSmx }
15216f3e57acSmx
15226f3e57acSmx if (ngep->chipinfo.device == DEVICE_ID_MCP55_373 ||
15236f3e57acSmx ngep->chipinfo.device == DEVICE_ID_MCP55_372) {
15246f3e57acSmx m2p.m2p_bits.phyintr = NGE_CLEAR;
15256f3e57acSmx m2p.m2p_bits.phyintrlvl = NGE_CLEAR;
15266f3e57acSmx }
15276f3e57acSmx if (ngep->param_link_duplex == LINK_DUPLEX_HALF) {
15286f3e57acSmx m2p.m2p_bits.hdup_en = NGE_SET;
15296f3e57acSmx }
15306f3e57acSmx else
15316f3e57acSmx m2p.m2p_bits.hdup_en = NGE_CLEAR;
15326f3e57acSmx nge_reg_put32(ngep, NGE_MAC2PHY, m2p.m2p_val);
15336f3e57acSmx nge_reg_put32(ngep, NGE_TX_DEF, tx_def.def_val);
15346f3e57acSmx
15356f3e57acSmx tx_fifo.wm_bits.data_lwm = TX_FIFO_DATA_LWM;
15366f3e57acSmx tx_fifo.wm_bits.prd_lwm = TX_FIFO_PRD_LWM;
15376f3e57acSmx tx_fifo.wm_bits.uprd_hwm = TX_FIFO_PRD_HWM;
15386f3e57acSmx tx_fifo.wm_bits.fb_wm = TX_FIFO_TBFW;
15396f3e57acSmx nge_reg_put32(ngep, NGE_TX_FIFO_WM, tx_fifo.wm_val);
15406f3e57acSmx
15416f3e57acSmx nge_reg_put32(ngep, NGE_BKOFF_CNTL, bk_cntl.cntl_val);
15426f3e57acSmx
15436f3e57acSmx rx_cntl0.cntl_val = nge_reg_get32(ngep, NGE_RX_CNTL0);
154486d6718fSLi-Zhen You if (ngep->param_link_rx_pause && dev_param_p->rx_pause_frame) {
154586d6718fSLi-Zhen You if (rx_cntl0.cntl_bits.paen == NGE_CLEAR) {
154686d6718fSLi-Zhen You rx_cntl0.cntl_bits.paen = NGE_SET;
154786d6718fSLi-Zhen You nge_reg_put32(ngep, NGE_RX_CNTL0, rx_cntl0.cntl_val);
154886d6718fSLi-Zhen You }
154986d6718fSLi-Zhen You } else {
155086d6718fSLi-Zhen You if (rx_cntl0.cntl_bits.paen == NGE_SET) {
155186d6718fSLi-Zhen You rx_cntl0.cntl_bits.paen = NGE_CLEAR;
155286d6718fSLi-Zhen You nge_reg_put32(ngep, NGE_RX_CNTL0, rx_cntl0.cntl_val);
155386d6718fSLi-Zhen You }
155486d6718fSLi-Zhen You }
155586d6718fSLi-Zhen You
155686d6718fSLi-Zhen You tx_cntl.cntl_val = nge_reg_get32(ngep, NGE_TX_CNTL);
155786d6718fSLi-Zhen You if (ngep->param_link_tx_pause && dev_param_p->tx_pause_frame) {
155886d6718fSLi-Zhen You if (tx_cntl.cntl_bits.paen == NGE_CLEAR) {
155986d6718fSLi-Zhen You tx_cntl.cntl_bits.paen = NGE_SET;
156086d6718fSLi-Zhen You nge_reg_put32(ngep, NGE_TX_CNTL, tx_cntl.cntl_val);
156186d6718fSLi-Zhen You }
156286d6718fSLi-Zhen You } else {
156386d6718fSLi-Zhen You if (tx_cntl.cntl_bits.paen == NGE_SET) {
156486d6718fSLi-Zhen You tx_cntl.cntl_bits.paen = NGE_CLEAR;
156586d6718fSLi-Zhen You nge_reg_put32(ngep, NGE_TX_CNTL, tx_cntl.cntl_val);
156686d6718fSLi-Zhen You }
156786d6718fSLi-Zhen You }
15686f3e57acSmx }
15696f3e57acSmx
15706f3e57acSmx /*
15716f3e57acSmx * Handler for hardware link state change.
15726f3e57acSmx *
15736f3e57acSmx * When this routine is called, the hardware link state has changed
15746f3e57acSmx * and the new state is reflected in the param_* variables. Here
15756f3e57acSmx * we must update the softstate, reprogram the MAC to match, and
15766f3e57acSmx * record the change in the log and/or on the console.
15776f3e57acSmx */
15786f3e57acSmx static void
nge_factotum_link_handler(nge_t * ngep)15796f3e57acSmx nge_factotum_link_handler(nge_t *ngep)
15806f3e57acSmx {
15816f3e57acSmx /*
15826f3e57acSmx * Update the s/w link_state
15836f3e57acSmx */
15846f3e57acSmx if (ngep->param_link_up)
15856f3e57acSmx ngep->link_state = LINK_STATE_UP;
15866f3e57acSmx else
15876f3e57acSmx ngep->link_state = LINK_STATE_DOWN;
15886f3e57acSmx
15896f3e57acSmx /*
15906f3e57acSmx * Reprogram the MAC modes to match
15916f3e57acSmx */
15926f3e57acSmx nge_sync_mac_modes(ngep);
15936f3e57acSmx }
15946f3e57acSmx
15956f3e57acSmx static boolean_t
nge_factotum_link_check(nge_t * ngep)15966f3e57acSmx nge_factotum_link_check(nge_t *ngep)
15976f3e57acSmx {
15986f3e57acSmx boolean_t lchg;
15996f3e57acSmx boolean_t check;
16006f3e57acSmx
16016f3e57acSmx ASSERT(mutex_owned(ngep->genlock));
16026f3e57acSmx
16036f3e57acSmx (*ngep->physops->phys_check)(ngep);
16046f3e57acSmx switch (ngep->link_state) {
16056f3e57acSmx case LINK_STATE_UP:
16066f3e57acSmx lchg = (ngep->param_link_up == B_FALSE);
16076f3e57acSmx check = (ngep->param_link_up == B_FALSE);
16086f3e57acSmx break;
16096f3e57acSmx
16106f3e57acSmx case LINK_STATE_DOWN:
16116f3e57acSmx lchg = (ngep->param_link_up == B_TRUE);
16126f3e57acSmx check = (ngep->param_link_up == B_TRUE);
16136f3e57acSmx break;
16146f3e57acSmx
16156f3e57acSmx default:
16166f3e57acSmx check = B_TRUE;
16176f3e57acSmx break;
16186f3e57acSmx }
16196f3e57acSmx
16206f3e57acSmx /*
16216f3e57acSmx * If <check> is false, we're sure the link hasn't changed.
16226f3e57acSmx * If true, however, it's not yet definitive; we have to call
16236f3e57acSmx * nge_phys_check() to determine whether the link has settled
16246f3e57acSmx * into a new state yet ... and if it has, then call the link
16256f3e57acSmx * state change handler.But when the chip is 5700 in Dell 6650
16266f3e57acSmx * ,even if check is false, the link may have changed.So we
16276f3e57acSmx * have to call nge_phys_check() to determine the link state.
16286f3e57acSmx */
16296f3e57acSmx if (check)
16306f3e57acSmx nge_factotum_link_handler(ngep);
16316f3e57acSmx
16326f3e57acSmx return (lchg);
16336f3e57acSmx }
16346f3e57acSmx
16356f3e57acSmx /*
16366f3e57acSmx * Factotum routine to check for Tx stall, using the 'watchdog' counter
16376f3e57acSmx */
16386f3e57acSmx static boolean_t nge_factotum_stall_check(nge_t *ngep);
16396f3e57acSmx
16406f3e57acSmx static boolean_t
nge_factotum_stall_check(nge_t * ngep)16416f3e57acSmx nge_factotum_stall_check(nge_t *ngep)
16426f3e57acSmx {
16436f3e57acSmx uint32_t dogval;
164451fc88a8SWinson Wang - Sun Microsystems - Beijing China send_ring_t *srp;
164551fc88a8SWinson Wang - Sun Microsystems - Beijing China srp = ngep->send;
16466f3e57acSmx /*
16476f3e57acSmx * Specific check for Tx stall ...
16486f3e57acSmx *
16496f3e57acSmx * The 'watchdog' counter is incremented whenever a packet
16506f3e57acSmx * is queued, reset to 1 when some (but not all) buffers
16516f3e57acSmx * are reclaimed, reset to 0 (disabled) when all buffers
16526f3e57acSmx * are reclaimed, and shifted left here. If it exceeds the
16536f3e57acSmx * threshold value, the chip is assumed to have stalled and
16546f3e57acSmx * is put into the ERROR state. The factotum will then reset
16556f3e57acSmx * it on the next pass.
16566f3e57acSmx *
16576f3e57acSmx * All of which should ensure that we don't get into a state
16586f3e57acSmx * where packets are left pending indefinitely!
16596f3e57acSmx */
166051fc88a8SWinson Wang - Sun Microsystems - Beijing China if (ngep->watchdog == 0 &&
166151fc88a8SWinson Wang - Sun Microsystems - Beijing China srp->tx_free < srp->desc.nslots)
166251fc88a8SWinson Wang - Sun Microsystems - Beijing China ngep->watchdog = 1;
16636f3e57acSmx dogval = nge_atomic_shl32(&ngep->watchdog, 1);
166451fc88a8SWinson Wang - Sun Microsystems - Beijing China if (dogval >= nge_watchdog_check)
166551fc88a8SWinson Wang - Sun Microsystems - Beijing China nge_tx_recycle(ngep, B_FALSE);
166651fc88a8SWinson Wang - Sun Microsystems - Beijing China if (dogval < nge_watchdog_count)
16676f3e57acSmx return (B_FALSE);
166851fc88a8SWinson Wang - Sun Microsystems - Beijing China else {
16696f3e57acSmx ngep->statistics.sw_statistics.tx_stall++;
16706f3e57acSmx return (B_TRUE);
16716f3e57acSmx }
16726f3e57acSmx }
16736f3e57acSmx
16746f3e57acSmx
16756f3e57acSmx /*
16766f3e57acSmx * The factotum is woken up when there's something to do that we'd rather
16776f3e57acSmx * not do from inside a hardware interrupt handler or high-level cyclic.
16786f3e57acSmx * Its two main tasks are:
16796f3e57acSmx * reset & restart the chip after an error
16806f3e57acSmx * check the link status whenever necessary
16816f3e57acSmx */
16826f3e57acSmx /* ARGSUSED */
16836f3e57acSmx uint_t
nge_chip_factotum(caddr_t args1,caddr_t args2)16846f3e57acSmx nge_chip_factotum(caddr_t args1, caddr_t args2)
16856f3e57acSmx {
16866f3e57acSmx uint_t result;
16876f3e57acSmx nge_t *ngep;
16886f3e57acSmx boolean_t err;
16896f3e57acSmx boolean_t linkchg;
16906f3e57acSmx
16916f3e57acSmx ngep = (nge_t *)args1;
16926f3e57acSmx
16936f3e57acSmx NGE_TRACE(("nge_chip_factotum($%p)", (void *)ngep));
16946f3e57acSmx
16956f3e57acSmx mutex_enter(ngep->softlock);
16966f3e57acSmx if (ngep->factotum_flag == 0) {
16976f3e57acSmx mutex_exit(ngep->softlock);
16986f3e57acSmx return (DDI_INTR_UNCLAIMED);
16996f3e57acSmx }
17006f3e57acSmx ngep->factotum_flag = 0;
17016f3e57acSmx mutex_exit(ngep->softlock);
17026f3e57acSmx err = B_FALSE;
17036f3e57acSmx linkchg = B_FALSE;
17046f3e57acSmx result = DDI_INTR_CLAIMED;
17056f3e57acSmx
17066f3e57acSmx mutex_enter(ngep->genlock);
17076f3e57acSmx switch (ngep->nge_chip_state) {
17086f3e57acSmx default:
17096f3e57acSmx break;
17106f3e57acSmx
17116f3e57acSmx case NGE_CHIP_RUNNING:
17126f3e57acSmx linkchg = nge_factotum_link_check(ngep);
17136f3e57acSmx err = nge_factotum_stall_check(ngep);
17146f3e57acSmx break;
17156f3e57acSmx
17166f3e57acSmx case NGE_CHIP_FAULT:
17176f3e57acSmx (void) nge_restart(ngep);
17186f3e57acSmx NGE_REPORT((ngep, "automatic recovery activated"));
17196f3e57acSmx break;
17206f3e57acSmx }
17216f3e57acSmx
17226f3e57acSmx if (err)
17236f3e57acSmx (void) nge_chip_stop(ngep, B_TRUE);
17246f3e57acSmx mutex_exit(ngep->genlock);
17256f3e57acSmx
17266f3e57acSmx /*
17276f3e57acSmx * If the link state changed, tell the world about it (if
17286f3e57acSmx * this version of MAC supports link state notification).
17296f3e57acSmx * Note: can't do this while still holding the mutex.
17306f3e57acSmx */
17316f3e57acSmx if (linkchg)
17326f3e57acSmx mac_link_update(ngep->mh, ngep->link_state);
17336f3e57acSmx
17346f3e57acSmx return (result);
17356f3e57acSmx
17366f3e57acSmx }
17376f3e57acSmx
17386f3e57acSmx static void
nge_intr_handle(nge_t * ngep,nge_intr_src * pintr_src)17396f3e57acSmx nge_intr_handle(nge_t *ngep, nge_intr_src *pintr_src)
17406f3e57acSmx {
17416f3e57acSmx boolean_t brx;
17426f3e57acSmx boolean_t btx;
17436f3e57acSmx nge_mintr_src mintr_src;
17446f3e57acSmx
17456f3e57acSmx brx = B_FALSE;
17466f3e57acSmx btx = B_FALSE;
17476f3e57acSmx ngep->statistics.sw_statistics.intr_count++;
17486f3e57acSmx ngep->statistics.sw_statistics.intr_lval = pintr_src->intr_val;
17496f3e57acSmx brx = (pintr_src->int_bits.reint | pintr_src->int_bits.miss
17506f3e57acSmx | pintr_src->int_bits.rcint | pintr_src->int_bits.stint)
1751b2fa2f2bSjj != 0 ? B_TRUE : B_FALSE;
17526f3e57acSmx if (pintr_src->int_bits.reint)
17536f3e57acSmx ngep->statistics.sw_statistics.rx_err++;
17546f3e57acSmx if (pintr_src->int_bits.miss)
17556f3e57acSmx ngep->statistics.sw_statistics.rx_nobuffer++;
17566f3e57acSmx
175751fc88a8SWinson Wang - Sun Microsystems - Beijing China btx = (pintr_src->int_bits.teint | pintr_src->int_bits.tfint)
1758b2fa2f2bSjj != 0 ? B_TRUE : B_FALSE;
17596f3e57acSmx if (btx)
17606f3e57acSmx nge_tx_recycle(ngep, B_TRUE);
1761b2fa2f2bSjj if (brx)
1762b2fa2f2bSjj nge_receive(ngep);
17636f3e57acSmx if (pintr_src->int_bits.teint)
17646f3e57acSmx ngep->statistics.sw_statistics.tx_stop_err++;
176502d51d0dSjj if (ngep->intr_moderation && brx) {
176602d51d0dSjj if (ngep->poll) {
176702d51d0dSjj if (ngep->recv_count < ngep->param_rx_intr_hwater) {
176802d51d0dSjj ngep->quiet_time++;
176902d51d0dSjj if (ngep->quiet_time ==
177002d51d0dSjj ngep->param_poll_quiet_time) {
177102d51d0dSjj ngep->poll = B_FALSE;
177202d51d0dSjj ngep->quiet_time = 0;
177302d51d0dSjj }
177402d51d0dSjj } else
177502d51d0dSjj ngep->quiet_time = 0;
177602d51d0dSjj } else {
177702d51d0dSjj if (ngep->recv_count > ngep->param_rx_intr_lwater) {
177802d51d0dSjj ngep->busy_time++;
177902d51d0dSjj if (ngep->busy_time ==
178002d51d0dSjj ngep->param_poll_busy_time) {
178102d51d0dSjj ngep->poll = B_TRUE;
178202d51d0dSjj ngep->busy_time = 0;
178302d51d0dSjj }
178402d51d0dSjj } else
178502d51d0dSjj ngep->busy_time = 0;
17866f3e57acSmx }
17876f3e57acSmx }
178802d51d0dSjj ngep->recv_count = 0;
17896f3e57acSmx if (pintr_src->int_bits.feint)
17906f3e57acSmx nge_chip_err(ngep);
17916f3e57acSmx /* link interrupt, check the link state */
17926f3e57acSmx if (pintr_src->int_bits.mint) {
17936f3e57acSmx mintr_src.src_val = nge_reg_get32(ngep, NGE_MINTR_SRC);
17946f3e57acSmx nge_reg_put32(ngep, NGE_MINTR_SRC, mintr_src.src_val);
17956f3e57acSmx nge_wake_factotum(ngep);
17966f3e57acSmx }
17976f3e57acSmx }
17986f3e57acSmx
17996f3e57acSmx /*
18006f3e57acSmx * nge_chip_intr() -- handle chip interrupts
18016f3e57acSmx */
18026f3e57acSmx /* ARGSUSED */
18036f3e57acSmx uint_t
nge_chip_intr(caddr_t arg1,caddr_t arg2)18046f3e57acSmx nge_chip_intr(caddr_t arg1, caddr_t arg2)
18056f3e57acSmx {
18066f3e57acSmx nge_t *ngep = (nge_t *)arg1;
18076f3e57acSmx nge_intr_src intr_src;
18086f3e57acSmx nge_intr_mask intr_mask;
18096f3e57acSmx
18106f3e57acSmx mutex_enter(ngep->genlock);
18116f3e57acSmx
18122d58516dSmx if (ngep->suspended) {
18132d58516dSmx mutex_exit(ngep->genlock);
18142d58516dSmx return (DDI_INTR_UNCLAIMED);
18152d58516dSmx }
18162d58516dSmx
18176f3e57acSmx /*
18186f3e57acSmx * Check whether chip's says it's asserting #INTA;
18196f3e57acSmx * if not, don't process or claim the interrupt.
18206f3e57acSmx */
18216f3e57acSmx intr_src.intr_val = nge_reg_get32(ngep, NGE_INTR_SRC);
18226f3e57acSmx if (intr_src.intr_val == 0) {
18236f3e57acSmx mutex_exit(ngep->genlock);
18246f3e57acSmx return (DDI_INTR_UNCLAIMED);
18256f3e57acSmx }
18266f3e57acSmx /*
18276f3e57acSmx * Ack the interrupt
18286f3e57acSmx */
18296f3e57acSmx nge_reg_put32(ngep, NGE_INTR_SRC, intr_src.intr_val);
18306f3e57acSmx
18316f3e57acSmx if (ngep->nge_chip_state != NGE_CHIP_RUNNING) {
18326f3e57acSmx mutex_exit(ngep->genlock);
18336f3e57acSmx return (DDI_INTR_CLAIMED);
18346f3e57acSmx }
18356f3e57acSmx nge_intr_handle(ngep, &intr_src);
18366f3e57acSmx if (ngep->poll && !ngep->ch_intr_mode) {
18376f3e57acSmx intr_mask.mask_val = nge_reg_get32(ngep, NGE_INTR_MASK);
18386f3e57acSmx intr_mask.mask_bits.stint = NGE_SET;
183902d51d0dSjj intr_mask.mask_bits.rcint = NGE_CLEAR;
18406f3e57acSmx nge_reg_put32(ngep, NGE_INTR_MASK, intr_mask.mask_val);
18416f3e57acSmx ngep->ch_intr_mode = B_TRUE;
18426f3e57acSmx } else if ((ngep->ch_intr_mode) && (!ngep->poll)) {
18436f3e57acSmx nge_reg_put32(ngep, NGE_INTR_MASK, ngep->intr_masks);
18446f3e57acSmx ngep->ch_intr_mode = B_FALSE;
18456f3e57acSmx }
18466f3e57acSmx mutex_exit(ngep->genlock);
18476f3e57acSmx return (DDI_INTR_CLAIMED);
18486f3e57acSmx }
18496f3e57acSmx
1850*ae5a8bedSAndy Fiddaman #if NGE_DEBUGGING
18516f3e57acSmx static enum ioc_reply
nge_pp_ioctl(nge_t * ngep,int cmd,mblk_t * mp,struct iocblk * iocp)18526f3e57acSmx nge_pp_ioctl(nge_t *ngep, int cmd, mblk_t *mp, struct iocblk *iocp)
18536f3e57acSmx {
18546f3e57acSmx int err;
18556f3e57acSmx uint64_t sizemask;
18566f3e57acSmx uint64_t mem_va;
18576f3e57acSmx uint64_t maxoff;
18586f3e57acSmx boolean_t peek;
18596f3e57acSmx nge_peekpoke_t *ppd;
18606f3e57acSmx int (*ppfn)(nge_t *ngep, nge_peekpoke_t *ppd);
18616f3e57acSmx
18626f3e57acSmx switch (cmd) {
18636f3e57acSmx default:
18646f3e57acSmx return (IOC_INVAL);
18656f3e57acSmx
18666f3e57acSmx case NGE_PEEK:
18676f3e57acSmx peek = B_TRUE;
18686f3e57acSmx break;
18696f3e57acSmx
18706f3e57acSmx case NGE_POKE:
18716f3e57acSmx peek = B_FALSE;
18726f3e57acSmx break;
18736f3e57acSmx }
18746f3e57acSmx
18756f3e57acSmx /*
18766f3e57acSmx * Validate format of ioctl
18776f3e57acSmx */
18786f3e57acSmx if (iocp->ioc_count != sizeof (nge_peekpoke_t))
18796f3e57acSmx return (IOC_INVAL);
18806f3e57acSmx if (mp->b_cont == NULL)
18816f3e57acSmx return (IOC_INVAL);
18826f3e57acSmx ppd = (nge_peekpoke_t *)mp->b_cont->b_rptr;
18836f3e57acSmx
18846f3e57acSmx /*
18856f3e57acSmx * Validate request parameters
18866f3e57acSmx */
18876f3e57acSmx switch (ppd->pp_acc_space) {
18886f3e57acSmx default:
18896f3e57acSmx return (IOC_INVAL);
18906f3e57acSmx
18916f3e57acSmx case NGE_PP_SPACE_CFG:
18926f3e57acSmx /*
18936f3e57acSmx * Config space
18946f3e57acSmx */
18956f3e57acSmx sizemask = 8|4|2|1;
18966f3e57acSmx mem_va = 0;
18976f3e57acSmx maxoff = PCI_CONF_HDR_SIZE;
18986f3e57acSmx ppfn = peek ? nge_chip_peek_cfg : nge_chip_poke_cfg;
18996f3e57acSmx break;
19006f3e57acSmx
19016f3e57acSmx case NGE_PP_SPACE_REG:
19026f3e57acSmx /*
19036f3e57acSmx * Memory-mapped I/O space
19046f3e57acSmx */
19056f3e57acSmx sizemask = 8|4|2|1;
19066f3e57acSmx mem_va = 0;
19076f3e57acSmx maxoff = NGE_REG_SIZE;
19086f3e57acSmx ppfn = peek ? nge_chip_peek_reg : nge_chip_poke_reg;
19096f3e57acSmx break;
19106f3e57acSmx
19116f3e57acSmx case NGE_PP_SPACE_MII:
19126f3e57acSmx sizemask = 4|2|1;
19136f3e57acSmx mem_va = 0;
19146f3e57acSmx maxoff = NGE_MII_SIZE;
19156f3e57acSmx ppfn = peek ? nge_chip_peek_mii : nge_chip_poke_mii;
19166f3e57acSmx break;
19176f3e57acSmx
19186f3e57acSmx case NGE_PP_SPACE_SEEPROM:
19196f3e57acSmx sizemask = 4|2|1;
19206f3e57acSmx mem_va = 0;
19216f3e57acSmx maxoff = NGE_SEEROM_SIZE;
19226f3e57acSmx ppfn = peek ? nge_chip_peek_seeprom : nge_chip_poke_seeprom;
19236f3e57acSmx break;
19246f3e57acSmx }
19256f3e57acSmx
19266f3e57acSmx switch (ppd->pp_acc_size) {
19276f3e57acSmx default:
19286f3e57acSmx return (IOC_INVAL);
19296f3e57acSmx
19306f3e57acSmx case 8:
19316f3e57acSmx case 4:
19326f3e57acSmx case 2:
19336f3e57acSmx case 1:
19346f3e57acSmx if ((ppd->pp_acc_size & sizemask) == 0)
19356f3e57acSmx return (IOC_INVAL);
19366f3e57acSmx break;
19376f3e57acSmx }
19386f3e57acSmx
19396f3e57acSmx if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0)
19406f3e57acSmx return (IOC_INVAL);
19416f3e57acSmx
19426f3e57acSmx if (ppd->pp_acc_offset >= maxoff)
19436f3e57acSmx return (IOC_INVAL);
19446f3e57acSmx
19456f3e57acSmx if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff)
19466f3e57acSmx return (IOC_INVAL);
19476f3e57acSmx
19486f3e57acSmx /*
19496f3e57acSmx * All OK - go do it!
19506f3e57acSmx */
19516f3e57acSmx ppd->pp_acc_offset += mem_va;
19526f3e57acSmx if (ppfn)
19536f3e57acSmx err = (*ppfn)(ngep, ppd);
19546f3e57acSmx if (err != DDI_SUCCESS)
19556f3e57acSmx return (IOC_INVAL);
19566f3e57acSmx return (peek ? IOC_REPLY : IOC_ACK);
19576f3e57acSmx }
19586f3e57acSmx
19596f3e57acSmx static enum ioc_reply nge_diag_ioctl(nge_t *ngep, int cmd, mblk_t *mp,
19606f3e57acSmx struct iocblk *iocp);
19616f3e57acSmx #pragma no_inline(nge_diag_ioctl)
19626f3e57acSmx
19636f3e57acSmx static enum ioc_reply
nge_diag_ioctl(nge_t * ngep,int cmd,mblk_t * mp,struct iocblk * iocp)19646f3e57acSmx nge_diag_ioctl(nge_t *ngep, int cmd, mblk_t *mp, struct iocblk *iocp)
19656f3e57acSmx {
19666f3e57acSmx ASSERT(mutex_owned(ngep->genlock));
19676f3e57acSmx
19686f3e57acSmx switch (cmd) {
19696f3e57acSmx default:
19706f3e57acSmx nge_error(ngep, "nge_diag_ioctl: invalid cmd 0x%x", cmd);
19716f3e57acSmx return (IOC_INVAL);
19726f3e57acSmx
19736f3e57acSmx case NGE_DIAG:
19746f3e57acSmx return (IOC_ACK);
19756f3e57acSmx
19766f3e57acSmx case NGE_PEEK:
19776f3e57acSmx case NGE_POKE:
19786f3e57acSmx return (nge_pp_ioctl(ngep, cmd, mp, iocp));
19796f3e57acSmx
19806f3e57acSmx case NGE_PHY_RESET:
19816f3e57acSmx return (IOC_RESTART_ACK);
19826f3e57acSmx
19836f3e57acSmx case NGE_SOFT_RESET:
19846f3e57acSmx case NGE_HARD_RESET:
19856f3e57acSmx return (IOC_ACK);
19866f3e57acSmx }
19876f3e57acSmx
19886f3e57acSmx /* NOTREACHED */
19896f3e57acSmx }
1990*ae5a8bedSAndy Fiddaman #endif /* NGE_DEBUGGING */
19916f3e57acSmx
19926f3e57acSmx enum ioc_reply
nge_chip_ioctl(nge_t * ngep,mblk_t * mp,struct iocblk * iocp)19936f3e57acSmx nge_chip_ioctl(nge_t *ngep, mblk_t *mp, struct iocblk *iocp)
19946f3e57acSmx {
19956f3e57acSmx int cmd;
19966f3e57acSmx
19976f3e57acSmx ASSERT(mutex_owned(ngep->genlock));
19986f3e57acSmx
19996f3e57acSmx cmd = iocp->ioc_cmd;
20006f3e57acSmx
20016f3e57acSmx switch (cmd) {
20026f3e57acSmx default:
20036f3e57acSmx return (IOC_INVAL);
20046f3e57acSmx
20056f3e57acSmx case NGE_DIAG:
20066f3e57acSmx case NGE_PEEK:
20076f3e57acSmx case NGE_POKE:
20086f3e57acSmx case NGE_PHY_RESET:
20096f3e57acSmx case NGE_SOFT_RESET:
20106f3e57acSmx case NGE_HARD_RESET:
20116f3e57acSmx #if NGE_DEBUGGING
20126f3e57acSmx return (nge_diag_ioctl(ngep, cmd, mp, iocp));
20136f3e57acSmx #else
20146f3e57acSmx return (IOC_INVAL);
20156f3e57acSmx #endif
20166f3e57acSmx
20176f3e57acSmx case NGE_MII_READ:
20186f3e57acSmx case NGE_MII_WRITE:
20196f3e57acSmx return (IOC_INVAL);
20206f3e57acSmx
20216f3e57acSmx #if NGE_SEE_IO32
20226f3e57acSmx case NGE_SEE_READ:
20236f3e57acSmx case NGE_SEE_WRITE:
20246f3e57acSmx return (IOC_INVAL);
20256f3e57acSmx #endif
20266f3e57acSmx
20276f3e57acSmx #if NGE_FLASH_IO32
20286f3e57acSmx case NGE_FLASH_READ:
20296f3e57acSmx case NGE_FLASH_WRITE:
20306f3e57acSmx return (IOC_INVAL);
20316f3e57acSmx #endif
20326f3e57acSmx }
20336f3e57acSmx }
2034