19da57d7bSbt /* 29da57d7bSbt * CDDL HEADER START 39da57d7bSbt * 473cd555cSBin Tu - Sun Microsystems - Beijing China * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 59da57d7bSbt * The contents of this file are subject to the terms of the 69da57d7bSbt * Common Development and Distribution License (the "License"). 79da57d7bSbt * You may not use this file except in compliance with the License. 89da57d7bSbt * 9da14cebeSEric Cheng * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10da14cebeSEric Cheng * or http://www.opensolaris.org/os/licensing. 119da57d7bSbt * See the License for the specific language governing permissions 129da57d7bSbt * and limitations under the License. 139da57d7bSbt * 14da14cebeSEric Cheng * When distributing Covered Code, include this CDDL HEADER in each 15da14cebeSEric Cheng * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 169da57d7bSbt * If applicable, add the following below this CDDL HEADER, with the 179da57d7bSbt * fields enclosed by brackets "[]" replaced with your own identifying 189da57d7bSbt * information: Portions Copyright [yyyy] [name of copyright owner] 199da57d7bSbt * 209da57d7bSbt * CDDL HEADER END 219da57d7bSbt */ 229da57d7bSbt 239da57d7bSbt /* 2413740cb2SPaul Guo * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 25da14cebeSEric Cheng * Use is subject to license terms. 269da57d7bSbt */ 279da57d7bSbt 289da57d7bSbt #ifndef _IXGBE_SW_H 299da57d7bSbt #define _IXGBE_SW_H 309da57d7bSbt 319da57d7bSbt #ifdef __cplusplus 329da57d7bSbt extern "C" { 339da57d7bSbt #endif 349da57d7bSbt 359da57d7bSbt #include <sys/types.h> 369da57d7bSbt #include <sys/conf.h> 379da57d7bSbt #include <sys/debug.h> 389da57d7bSbt #include <sys/stropts.h> 399da57d7bSbt #include <sys/stream.h> 409da57d7bSbt #include <sys/strsun.h> 419da57d7bSbt #include <sys/strlog.h> 429da57d7bSbt #include <sys/kmem.h> 439da57d7bSbt #include <sys/stat.h> 449da57d7bSbt #include <sys/kstat.h> 459da57d7bSbt #include <sys/modctl.h> 469da57d7bSbt #include <sys/errno.h> 479da57d7bSbt #include <sys/dlpi.h> 48da14cebeSEric Cheng #include <sys/mac_provider.h> 499da57d7bSbt #include <sys/mac_ether.h> 509da57d7bSbt #include <sys/vlan.h> 519da57d7bSbt #include <sys/ddi.h> 529da57d7bSbt #include <sys/sunddi.h> 539da57d7bSbt #include <sys/pci.h> 549da57d7bSbt #include <sys/pcie.h> 559da57d7bSbt #include <sys/sdt.h> 569da57d7bSbt #include <sys/ethernet.h> 579da57d7bSbt #include <sys/pattr.h> 589da57d7bSbt #include <sys/strsubr.h> 599da57d7bSbt #include <sys/netlb.h> 609da57d7bSbt #include <sys/random.h> 619da57d7bSbt #include <inet/common.h> 62c971fb7eSgg #include <inet/tcp.h> 639da57d7bSbt #include <inet/ip.h> 649da57d7bSbt #include <inet/mi.h> 659da57d7bSbt #include <inet/nd.h> 669da57d7bSbt #include <sys/bitmap.h> 679da57d7bSbt #include <sys/ddifm.h> 689da57d7bSbt #include <sys/fm/protocol.h> 699da57d7bSbt #include <sys/fm/util.h> 709da57d7bSbt #include <sys/fm/io/ddi.h> 719da57d7bSbt #include "ixgbe_api.h" 729da57d7bSbt 739da57d7bSbt #define MODULE_NAME "ixgbe" /* module name */ 749da57d7bSbt 759da57d7bSbt #define IXGBE_FAILURE DDI_FAILURE 769da57d7bSbt 779da57d7bSbt #define IXGBE_UNKNOWN 0x00 789da57d7bSbt #define IXGBE_INITIALIZED 0x01 799da57d7bSbt #define IXGBE_STARTED 0x02 809da57d7bSbt #define IXGBE_SUSPENDED 0x04 819da57d7bSbt 829da57d7bSbt #define MAX_NUM_UNICAST_ADDRESSES 0x10 839da57d7bSbt #define MAX_NUM_MULTICAST_ADDRESSES 0x1000 849da57d7bSbt #define IXGBE_INTR_NONE 0 859da57d7bSbt #define IXGBE_INTR_MSIX 1 869da57d7bSbt #define IXGBE_INTR_MSI 2 879da57d7bSbt #define IXGBE_INTR_LEGACY 3 889da57d7bSbt 89da14cebeSEric Cheng #define IXGBE_POLL_NULL -1 90da14cebeSEric Cheng 91c971fb7eSgg #define MAX_COOKIE 18 929da57d7bSbt #define MIN_NUM_TX_DESC 2 939da57d7bSbt 94*edf70dc9SPaul Guo #define IXGBE_TX_DESC_LIMIT 32 /* tx desc limitation */ 95*edf70dc9SPaul Guo 9673cd555cSBin Tu - Sun Microsystems - Beijing China #define IXGBE_ADAPTER_REGSET 1 /* map adapter registers */ 9773cd555cSBin Tu - Sun Microsystems - Beijing China 989da57d7bSbt /* 9973cd555cSBin Tu - Sun Microsystems - Beijing China * MAX_xx_QUEUE_NUM and MAX_INTR_VECTOR values need to be the maximum of all 10013740cb2SPaul Guo * supported silicon types. 1019da57d7bSbt */ 10273cd555cSBin Tu - Sun Microsystems - Beijing China #define MAX_TX_QUEUE_NUM 128 10373cd555cSBin Tu - Sun Microsystems - Beijing China #define MAX_RX_QUEUE_NUM 128 10473cd555cSBin Tu - Sun Microsystems - Beijing China #define MAX_INTR_VECTOR 64 1059da57d7bSbt 1069da57d7bSbt /* 10713740cb2SPaul Guo * Maximum values for user configurable parameters 1089da57d7bSbt */ 109da14cebeSEric Cheng #define MAX_RX_GROUP_NUM 1 1109da57d7bSbt #define MAX_TX_RING_SIZE 4096 1119da57d7bSbt #define MAX_RX_RING_SIZE 4096 1129da57d7bSbt 1139da57d7bSbt #define MAX_MTU 16366 1149da57d7bSbt #define MAX_RX_LIMIT_PER_INTR 4096 11573cd555cSBin Tu - Sun Microsystems - Beijing China #define MAX_INTR_THROTTLING_82598 65535 11673cd555cSBin Tu - Sun Microsystems - Beijing China #define MAX_INTR_THROTTLING_82599 0x7FC 1179da57d7bSbt 1189da57d7bSbt #define MAX_RX_COPY_THRESHOLD 9216 1199da57d7bSbt #define MAX_TX_COPY_THRESHOLD 9216 1209da57d7bSbt #define MAX_TX_RECYCLE_THRESHOLD DEFAULT_TX_RING_SIZE 1219da57d7bSbt #define MAX_TX_OVERLOAD_THRESHOLD DEFAULT_TX_RING_SIZE 1229da57d7bSbt #define MAX_TX_RESCHED_THRESHOLD DEFAULT_TX_RING_SIZE 1239da57d7bSbt 1249da57d7bSbt /* 1259da57d7bSbt * Minimum values for user configurable parameters 1269da57d7bSbt */ 127da14cebeSEric Cheng #define MIN_RX_GROUP_NUM 1 1289da57d7bSbt #define MIN_TX_RING_SIZE 64 1299da57d7bSbt #define MIN_RX_RING_SIZE 64 1309da57d7bSbt 1319da57d7bSbt #define MIN_MTU ETHERMIN 1329da57d7bSbt #define MIN_RX_LIMIT_PER_INTR 16 1339da57d7bSbt #define MIN_INTR_THROTTLING 0 1349da57d7bSbt #define MIN_TX_COPY_THRESHOLD 0 1359da57d7bSbt #define MIN_RX_COPY_THRESHOLD 0 1369da57d7bSbt #define MIN_TX_RECYCLE_THRESHOLD MIN_NUM_TX_DESC 1379da57d7bSbt #define MIN_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 1389da57d7bSbt #define MIN_TX_RESCHED_THRESHOLD MIN_NUM_TX_DESC 1399da57d7bSbt 1409da57d7bSbt /* 1419da57d7bSbt * Default values for user configurable parameters 1429da57d7bSbt */ 143da14cebeSEric Cheng #define DEFAULT_RX_GROUP_NUM 1 144da14cebeSEric Cheng #define DEFAULT_TX_RING_SIZE 1024 145da14cebeSEric Cheng #define DEFAULT_RX_RING_SIZE 1024 1469da57d7bSbt 1479da57d7bSbt #define DEFAULT_MTU ETHERMTU 1489da57d7bSbt #define DEFAULT_RX_LIMIT_PER_INTR 256 14973cd555cSBin Tu - Sun Microsystems - Beijing China #define DEFAULT_INTR_THROTTLING_82598 200 /* In unit of 256 nsec */ 15073cd555cSBin Tu - Sun Microsystems - Beijing China #define DEFAULT_INTR_THROTTLING_82599 26 /* In unit of 2 usec */ 1519da57d7bSbt #define DEFAULT_RX_COPY_THRESHOLD 128 1529da57d7bSbt #define DEFAULT_TX_COPY_THRESHOLD 512 153da14cebeSEric Cheng #define DEFAULT_TX_RECYCLE_THRESHOLD (MAX_COOKIE + 1) 1549da57d7bSbt #define DEFAULT_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 1559da57d7bSbt #define DEFAULT_TX_RESCHED_THRESHOLD 128 1569da57d7bSbt #define DEFAULT_FCRTH 0x20000 1579da57d7bSbt #define DEFAULT_FCRTL 0x10000 1589da57d7bSbt #define DEFAULT_FCPAUSE 0xFFFF 1599da57d7bSbt 160da14cebeSEric Cheng #define DEFAULT_TX_HCKSUM_ENABLE B_TRUE 161da14cebeSEric Cheng #define DEFAULT_RX_HCKSUM_ENABLE B_TRUE 162da14cebeSEric Cheng #define DEFAULT_LSO_ENABLE B_TRUE 163da14cebeSEric Cheng #define DEFAULT_MR_ENABLE B_TRUE 164da14cebeSEric Cheng #define DEFAULT_TX_HEAD_WB_ENABLE B_TRUE 165da14cebeSEric Cheng 166da14cebeSEric Cheng #define IXGBE_LSO_MAXLEN 65535 167da14cebeSEric Cheng 1689da57d7bSbt #define TX_DRAIN_TIME 200 1699da57d7bSbt #define RX_DRAIN_TIME 200 1709da57d7bSbt 1719da57d7bSbt #define STALL_WATCHDOG_TIMEOUT 8 /* 8 seconds */ 1729da57d7bSbt #define MAX_LINK_DOWN_TIMEOUT 8 /* 8 seconds */ 1739da57d7bSbt 1749da57d7bSbt /* 1759da57d7bSbt * Extra register bit masks for 82598 1769da57d7bSbt */ 1779da57d7bSbt #define IXGBE_PCS1GANA_FDC 0x20 1789da57d7bSbt #define IXGBE_PCS1GANLP_LPFD 0x20 1799da57d7bSbt #define IXGBE_PCS1GANLP_LPHD 0x40 1809da57d7bSbt 1819da57d7bSbt /* 1829da57d7bSbt * Defined for IP header alignment. 1839da57d7bSbt */ 1849da57d7bSbt #define IPHDR_ALIGN_ROOM 2 1859da57d7bSbt 1869da57d7bSbt /* 1879da57d7bSbt * Bit flags for attach_progress 1889da57d7bSbt */ 1899da57d7bSbt #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 1909da57d7bSbt #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 1919da57d7bSbt #define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */ 1929da57d7bSbt #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */ 1939da57d7bSbt #define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */ 1949da57d7bSbt #define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */ 1959da57d7bSbt #define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */ 1969da57d7bSbt #define ATTACH_PROGRESS_INIT 0x0080 /* Device initialized */ 1979da57d7bSbt #define ATTACH_PROGRESS_INIT_RINGS 0x0100 /* Rings initialized */ 1989da57d7bSbt #define ATTACH_PROGRESS_STATS 0x0200 /* Kstats created */ 1999da57d7bSbt #define ATTACH_PROGRESS_NDD 0x0400 /* NDD initialized */ 2009da57d7bSbt #define ATTACH_PROGRESS_MAC 0x0800 /* MAC registered */ 2019da57d7bSbt #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */ 2029da57d7bSbt #define ATTACH_PROGRESS_FM_INIT 0x2000 /* FMA initialized */ 20313740cb2SPaul Guo #define ATTACH_PROGRESS_LSC_TASKQ 0x4000 /* LSC taskq created */ 2049da57d7bSbt 2059da57d7bSbt #define PROP_DEFAULT_MTU "default_mtu" 2069da57d7bSbt #define PROP_FLOW_CONTROL "flow_control" 2079da57d7bSbt #define PROP_TX_QUEUE_NUM "tx_queue_number" 2089da57d7bSbt #define PROP_TX_RING_SIZE "tx_ring_size" 2099da57d7bSbt #define PROP_RX_QUEUE_NUM "rx_queue_number" 2109da57d7bSbt #define PROP_RX_RING_SIZE "rx_ring_size" 211da14cebeSEric Cheng #define PROP_RX_GROUP_NUM "rx_group_number" 2129da57d7bSbt 2139da57d7bSbt #define PROP_INTR_FORCE "intr_force" 2149da57d7bSbt #define PROP_TX_HCKSUM_ENABLE "tx_hcksum_enable" 2159da57d7bSbt #define PROP_RX_HCKSUM_ENABLE "rx_hcksum_enable" 2169da57d7bSbt #define PROP_LSO_ENABLE "lso_enable" 217da14cebeSEric Cheng #define PROP_MR_ENABLE "mr_enable" 2189da57d7bSbt #define PROP_TX_HEAD_WB_ENABLE "tx_head_wb_enable" 2199da57d7bSbt #define PROP_TX_COPY_THRESHOLD "tx_copy_threshold" 2209da57d7bSbt #define PROP_TX_RECYCLE_THRESHOLD "tx_recycle_threshold" 2219da57d7bSbt #define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold" 2229da57d7bSbt #define PROP_TX_RESCHED_THRESHOLD "tx_resched_threshold" 2239da57d7bSbt #define PROP_RX_COPY_THRESHOLD "rx_copy_threshold" 2249da57d7bSbt #define PROP_RX_LIMIT_PER_INTR "rx_limit_per_intr" 2259da57d7bSbt #define PROP_INTR_THROTTLING "intr_throttling" 2269da57d7bSbt #define PROP_FM_CAPABLE "fm_capable" 2279da57d7bSbt 2289da57d7bSbt #define IXGBE_LB_NONE 0 2299da57d7bSbt #define IXGBE_LB_EXTERNAL 1 2309da57d7bSbt #define IXGBE_LB_INTERNAL_MAC 2 2319da57d7bSbt #define IXGBE_LB_INTERNAL_PHY 3 2329da57d7bSbt #define IXGBE_LB_INTERNAL_SERDES 4 2339da57d7bSbt 23413740cb2SPaul Guo /* 23513740cb2SPaul Guo * capability/feature flags 23613740cb2SPaul Guo * Flags named _CAPABLE are set when the NIC hardware is capable of the feature. 23713740cb2SPaul Guo * Separately, the flag named _ENABLED is set when the feature is enabled. 23813740cb2SPaul Guo */ 23913740cb2SPaul Guo #define IXGBE_FLAG_DCA_ENABLED (u32)(1) 24013740cb2SPaul Guo #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 1) 24113740cb2SPaul Guo #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 2) 24213740cb2SPaul Guo #define IXGBE_FLAG_DCB_CAPABLE (u32)(1 << 4) 24313740cb2SPaul Guo #define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 4) 24413740cb2SPaul Guo #define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 5) 24513740cb2SPaul Guo #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 6) 24613740cb2SPaul Guo #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 7) 24713740cb2SPaul Guo #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 8) 24813740cb2SPaul Guo 24913740cb2SPaul Guo /* adapter-specific info for each supported device type */ 25013740cb2SPaul Guo typedef struct adapter_info { 25113740cb2SPaul Guo uint32_t max_rx_que_num; /* maximum number of rx queues */ 25213740cb2SPaul Guo uint32_t min_rx_que_num; /* minimum number of rx queues */ 25313740cb2SPaul Guo uint32_t def_rx_que_num; /* default number of rx queues */ 25413740cb2SPaul Guo uint32_t max_tx_que_num; /* maximum number of tx queues */ 25513740cb2SPaul Guo uint32_t min_tx_que_num; /* minimum number of tx queues */ 25613740cb2SPaul Guo uint32_t def_tx_que_num; /* default number of tx queues */ 25713740cb2SPaul Guo uint32_t max_msix_vect; /* maximum total msix vectors */ 25813740cb2SPaul Guo uint32_t max_ring_vect; /* maximum number of ring vectors */ 25913740cb2SPaul Guo uint32_t max_other_vect; /* maximum number of other vectors */ 26013740cb2SPaul Guo uint32_t other_intr; /* "other" interrupt types handled */ 26113740cb2SPaul Guo uint32_t flags; /* capability flags */ 26213740cb2SPaul Guo } adapter_info_t; 26313740cb2SPaul Guo 26413740cb2SPaul Guo /* bits representing all interrupt types other than tx & rx */ 26513740cb2SPaul Guo #define IXGBE_OTHER_INTR 0x3ff00000 26673cd555cSBin Tu - Sun Microsystems - Beijing China #define IXGBE_82599_OTHER_INTR 0x86100000 26713740cb2SPaul Guo 2689da57d7bSbt /* 2699da57d7bSbt * Shorthand for the NDD parameters 2709da57d7bSbt */ 2719da57d7bSbt #define param_autoneg_cap nd_params[PARAM_AUTONEG_CAP].val 2729da57d7bSbt #define param_pause_cap nd_params[PARAM_PAUSE_CAP].val 2739da57d7bSbt #define param_asym_pause_cap nd_params[PARAM_ASYM_PAUSE_CAP].val 2749da57d7bSbt #define param_10000fdx_cap nd_params[PARAM_10000FDX_CAP].val 2759da57d7bSbt #define param_1000fdx_cap nd_params[PARAM_1000FDX_CAP].val 2769da57d7bSbt #define param_100fdx_cap nd_params[PARAM_1000FDX_CAP].val 2779da57d7bSbt #define param_rem_fault nd_params[PARAM_REM_FAULT].val 2789da57d7bSbt 2799da57d7bSbt #define param_adv_autoneg_cap nd_params[PARAM_ADV_AUTONEG_CAP].val 2809da57d7bSbt #define param_adv_pause_cap nd_params[PARAM_ADV_PAUSE_CAP].val 2819da57d7bSbt #define param_adv_asym_pause_cap nd_params[PARAM_ADV_ASYM_PAUSE_CAP].val 2829da57d7bSbt #define param_adv_10000fdx_cap nd_params[PARAM_ADV_10000FDX_CAP].val 2839da57d7bSbt #define param_adv_1000fdx_cap nd_params[PARAM_ADV_1000FDX_CAP].val 2849da57d7bSbt #define param_adv_100fdx_cap nd_params[PARAM_ADV_1000FDX_CAP].val 2859da57d7bSbt #define param_adv_rem_fault nd_params[PARAM_ADV_REM_FAULT].val 2869da57d7bSbt 2879da57d7bSbt #define param_lp_autoneg_cap nd_params[PARAM_LP_AUTONEG_CAP].val 2889da57d7bSbt #define param_lp_pause_cap nd_params[PARAM_LP_PAUSE_CAP].val 2899da57d7bSbt #define param_lp_asym_pause_cap nd_params[PARAM_LP_ASYM_PAUSE_CAP].val 2909da57d7bSbt #define param_lp_10000fdx_cap nd_params[PARAM_LP_10000FDX_CAP].val 2919da57d7bSbt #define param_lp_1000fdx_cap nd_params[PARAM_LP_1000FDX_CAP].val 2929da57d7bSbt #define param_lp_100fdx_cap nd_params[PARAM_LP_1000FDX_CAP].val 2939da57d7bSbt #define param_lp_rem_fault nd_params[PARAM_LP_REM_FAULT].val 2949da57d7bSbt 2959da57d7bSbt enum ioc_reply { 2969da57d7bSbt IOC_INVAL = -1, /* bad, NAK with EINVAL */ 2979da57d7bSbt IOC_DONE, /* OK, reply sent */ 2989da57d7bSbt IOC_ACK, /* OK, just send ACK */ 2999da57d7bSbt IOC_REPLY /* OK, just send reply */ 3009da57d7bSbt }; 3019da57d7bSbt 3029da57d7bSbt #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area)->dma_handle, \ 3039da57d7bSbt 0, 0, (flag))) 3049da57d7bSbt 3059da57d7bSbt /* 3069da57d7bSbt * Defined for ring index operations 3079da57d7bSbt * ASSERT(index < limit) 3089da57d7bSbt * ASSERT(step < limit) 3099da57d7bSbt * ASSERT(index1 < limit) 3109da57d7bSbt * ASSERT(index2 < limit) 3119da57d7bSbt */ 3129da57d7bSbt #define NEXT_INDEX(index, step, limit) (((index) + (step)) < (limit) ? \ 3139da57d7bSbt (index) + (step) : (index) + (step) - (limit)) 3149da57d7bSbt #define PREV_INDEX(index, step, limit) ((index) >= (step) ? \ 3159da57d7bSbt (index) - (step) : (index) + (limit) - (step)) 3169da57d7bSbt #define OFFSET(index1, index2, limit) ((index1) <= (index2) ? \ 3179da57d7bSbt (index2) - (index1) : (index2) + (limit) - (index1)) 3189da57d7bSbt 3199da57d7bSbt #define LINK_LIST_INIT(_LH) \ 3209da57d7bSbt (_LH)->head = (_LH)->tail = NULL 3219da57d7bSbt 3229da57d7bSbt #define LIST_GET_HEAD(_LH) ((single_link_t *)((_LH)->head)) 3239da57d7bSbt 3249da57d7bSbt #define LIST_POP_HEAD(_LH) \ 3259da57d7bSbt (single_link_t *)(_LH)->head; \ 3269da57d7bSbt { \ 3279da57d7bSbt if ((_LH)->head != NULL) { \ 3289da57d7bSbt (_LH)->head = (_LH)->head->link; \ 3299da57d7bSbt if ((_LH)->head == NULL) \ 3309da57d7bSbt (_LH)->tail = NULL; \ 3319da57d7bSbt } \ 3329da57d7bSbt } 3339da57d7bSbt 3349da57d7bSbt #define LIST_GET_TAIL(_LH) ((single_link_t *)((_LH)->tail)) 3359da57d7bSbt 3369da57d7bSbt #define LIST_PUSH_TAIL(_LH, _E) \ 3379da57d7bSbt if ((_LH)->tail != NULL) { \ 3389da57d7bSbt (_LH)->tail->link = (single_link_t *)(_E); \ 3399da57d7bSbt (_LH)->tail = (single_link_t *)(_E); \ 3409da57d7bSbt } else { \ 3419da57d7bSbt (_LH)->head = (_LH)->tail = (single_link_t *)(_E); \ 3429da57d7bSbt } \ 3439da57d7bSbt (_E)->link = NULL; 3449da57d7bSbt 3459da57d7bSbt #define LIST_GET_NEXT(_LH, _E) \ 3469da57d7bSbt (((_LH)->tail == (single_link_t *)(_E)) ? \ 3479da57d7bSbt NULL : ((single_link_t *)(_E))->link) 3489da57d7bSbt 3499da57d7bSbt 3509da57d7bSbt typedef struct single_link { 3519da57d7bSbt struct single_link *link; 3529da57d7bSbt } single_link_t; 3539da57d7bSbt 3549da57d7bSbt typedef struct link_list { 3559da57d7bSbt single_link_t *head; 3569da57d7bSbt single_link_t *tail; 3579da57d7bSbt } link_list_t; 3589da57d7bSbt 3599da57d7bSbt /* 3609da57d7bSbt * Property lookups 3619da57d7bSbt */ 3629da57d7bSbt #define IXGBE_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 3639da57d7bSbt DDI_PROP_DONTPASS, (n)) 3649da57d7bSbt #define IXGBE_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 3659da57d7bSbt DDI_PROP_DONTPASS, (n), -1) 3669da57d7bSbt 3679da57d7bSbt 3689da57d7bSbt /* 3699da57d7bSbt * Named Data (ND) Parameter Management Structure 3709da57d7bSbt */ 3719da57d7bSbt typedef struct { 3729da57d7bSbt struct ixgbe *private; 3739da57d7bSbt uint32_t info; 3749da57d7bSbt uint32_t min; 3759da57d7bSbt uint32_t max; 3769da57d7bSbt uint32_t val; 3779da57d7bSbt char *name; 3789da57d7bSbt } nd_param_t; 3799da57d7bSbt 3809da57d7bSbt /* 3819da57d7bSbt * NDD parameter indexes, divided into: 3829da57d7bSbt * 3839da57d7bSbt * read-only parameters describing the hardware's capabilities 3849da57d7bSbt * read-write parameters controlling the advertised capabilities 3859da57d7bSbt * read-only parameters describing the partner's capabilities 3869da57d7bSbt * read-write parameters controlling the force speed and duplex 3879da57d7bSbt * read-only parameters describing the link state 3889da57d7bSbt * read-only parameters describing the driver properties 3899da57d7bSbt * read-write parameters controlling the driver properties 3909da57d7bSbt */ 3919da57d7bSbt enum { 3929da57d7bSbt PARAM_AUTONEG_CAP, 3939da57d7bSbt PARAM_PAUSE_CAP, 3949da57d7bSbt PARAM_ASYM_PAUSE_CAP, 3959da57d7bSbt PARAM_10000FDX_CAP, 3969da57d7bSbt PARAM_1000FDX_CAP, 3979da57d7bSbt PARAM_100FDX_CAP, 3989da57d7bSbt PARAM_REM_FAULT, 3999da57d7bSbt 4009da57d7bSbt PARAM_ADV_AUTONEG_CAP, 4019da57d7bSbt PARAM_ADV_PAUSE_CAP, 4029da57d7bSbt PARAM_ADV_ASYM_PAUSE_CAP, 4039da57d7bSbt PARAM_ADV_10000FDX_CAP, 4049da57d7bSbt PARAM_ADV_1000FDX_CAP, 4059da57d7bSbt PARAM_ADV_100FDX_CAP, 4069da57d7bSbt PARAM_ADV_REM_FAULT, 4079da57d7bSbt 4089da57d7bSbt PARAM_LP_AUTONEG_CAP, 4099da57d7bSbt PARAM_LP_PAUSE_CAP, 4109da57d7bSbt PARAM_LP_ASYM_PAUSE_CAP, 4119da57d7bSbt PARAM_LP_10000FDX_CAP, 4129da57d7bSbt PARAM_LP_1000FDX_CAP, 4139da57d7bSbt PARAM_LP_100FDX_CAP, 4149da57d7bSbt PARAM_LP_REM_FAULT, 4159da57d7bSbt 4169da57d7bSbt PARAM_LINK_STATUS, 4179da57d7bSbt PARAM_LINK_SPEED, 4189da57d7bSbt PARAM_LINK_DUPLEX, 4199da57d7bSbt 4209da57d7bSbt PARAM_COUNT 4219da57d7bSbt }; 4229da57d7bSbt 4239da57d7bSbt typedef union ixgbe_ether_addr { 4249da57d7bSbt struct { 4259da57d7bSbt uint32_t high; 4269da57d7bSbt uint32_t low; 4279da57d7bSbt } reg; 4289da57d7bSbt struct { 4299da57d7bSbt uint8_t set; 4309da57d7bSbt uint8_t redundant; 4319da57d7bSbt uint8_t addr[ETHERADDRL]; 4329da57d7bSbt } mac; 4339da57d7bSbt } ixgbe_ether_addr_t; 4349da57d7bSbt 4359da57d7bSbt typedef enum { 4369da57d7bSbt USE_NONE, 4379da57d7bSbt USE_COPY, 4389da57d7bSbt USE_DMA 4399da57d7bSbt } tx_type_t; 4409da57d7bSbt 4419da57d7bSbt typedef enum { 4429da57d7bSbt RCB_FREE, 4439da57d7bSbt RCB_SENDUP 4449da57d7bSbt } rcb_state_t; 4459da57d7bSbt 446c971fb7eSgg typedef struct ixgbe_tx_context { 4479da57d7bSbt uint32_t hcksum_flags; 4489da57d7bSbt uint32_t ip_hdr_len; 4499da57d7bSbt uint32_t mac_hdr_len; 4509da57d7bSbt uint32_t l4_proto; 451c971fb7eSgg uint32_t mss; 452c971fb7eSgg uint32_t l4_hdr_len; 453c971fb7eSgg boolean_t lso_flag; 454c971fb7eSgg } ixgbe_tx_context_t; 4559da57d7bSbt 4569da57d7bSbt /* 4579da57d7bSbt * Hold address/length of each DMA segment 4589da57d7bSbt */ 4599da57d7bSbt typedef struct sw_desc { 4609da57d7bSbt uint64_t address; 4619da57d7bSbt size_t length; 4629da57d7bSbt } sw_desc_t; 4639da57d7bSbt 4649da57d7bSbt /* 4659da57d7bSbt * Handles and addresses of DMA buffer 4669da57d7bSbt */ 4679da57d7bSbt typedef struct dma_buffer { 4689da57d7bSbt caddr_t address; /* Virtual address */ 4699da57d7bSbt uint64_t dma_address; /* DMA (Hardware) address */ 4709da57d7bSbt ddi_acc_handle_t acc_handle; /* Data access handle */ 4719da57d7bSbt ddi_dma_handle_t dma_handle; /* DMA handle */ 4729da57d7bSbt size_t size; /* Buffer size */ 4739da57d7bSbt size_t len; /* Data length in the buffer */ 4749da57d7bSbt } dma_buffer_t; 4759da57d7bSbt 4769da57d7bSbt /* 4779da57d7bSbt * Tx Control Block 4789da57d7bSbt */ 4799da57d7bSbt typedef struct tx_control_block { 4809da57d7bSbt single_link_t link; 481*edf70dc9SPaul Guo uint32_t last_index; /* last descriptor of the pkt */ 4829da57d7bSbt uint32_t frag_num; 4839da57d7bSbt uint32_t desc_num; 4849da57d7bSbt mblk_t *mp; 4859da57d7bSbt tx_type_t tx_type; 4869da57d7bSbt ddi_dma_handle_t tx_dma_handle; 4879da57d7bSbt dma_buffer_t tx_buf; 4889da57d7bSbt sw_desc_t desc[MAX_COOKIE]; 4899da57d7bSbt } tx_control_block_t; 4909da57d7bSbt 4919da57d7bSbt /* 4929da57d7bSbt * RX Control Block 4939da57d7bSbt */ 4949da57d7bSbt typedef struct rx_control_block { 4959da57d7bSbt mblk_t *mp; 4969da57d7bSbt rcb_state_t state; 4979da57d7bSbt dma_buffer_t rx_buf; 4989da57d7bSbt frtn_t free_rtn; 4999da57d7bSbt struct ixgbe_rx_ring *rx_ring; 5009da57d7bSbt } rx_control_block_t; 5019da57d7bSbt 5029da57d7bSbt /* 5039da57d7bSbt * Software Data Structure for Tx Ring 5049da57d7bSbt */ 5059da57d7bSbt typedef struct ixgbe_tx_ring { 5069da57d7bSbt uint32_t index; /* Ring index */ 5079da57d7bSbt uint32_t intr_vector; /* Interrupt vector index */ 5089da57d7bSbt uint32_t vect_bit; /* vector's bit in register */ 5099da57d7bSbt 5109da57d7bSbt /* 5119da57d7bSbt * Mutexes 5129da57d7bSbt */ 5139da57d7bSbt kmutex_t tx_lock; 5149da57d7bSbt kmutex_t recycle_lock; 5159da57d7bSbt kmutex_t tcb_head_lock; 5169da57d7bSbt kmutex_t tcb_tail_lock; 5179da57d7bSbt 5189da57d7bSbt /* 5199da57d7bSbt * Tx descriptor ring definitions 5209da57d7bSbt */ 5219da57d7bSbt dma_buffer_t tbd_area; 5229da57d7bSbt union ixgbe_adv_tx_desc *tbd_ring; 5239da57d7bSbt uint32_t tbd_head; /* Index of next tbd to recycle */ 5249da57d7bSbt uint32_t tbd_tail; /* Index of next tbd to transmit */ 5259da57d7bSbt uint32_t tbd_free; /* Number of free tbd */ 5269da57d7bSbt 5279da57d7bSbt /* 5289da57d7bSbt * Tx control block list definitions 5299da57d7bSbt */ 5309da57d7bSbt tx_control_block_t *tcb_area; 5319da57d7bSbt tx_control_block_t **work_list; 5329da57d7bSbt tx_control_block_t **free_list; 5339da57d7bSbt uint32_t tcb_head; /* Head index of free list */ 5349da57d7bSbt uint32_t tcb_tail; /* Tail index of free list */ 5359da57d7bSbt uint32_t tcb_free; /* Number of free tcb in free list */ 5369da57d7bSbt 5379da57d7bSbt uint32_t *tbd_head_wb; /* Head write-back */ 5389da57d7bSbt uint32_t (*tx_recycle)(struct ixgbe_tx_ring *); 5399da57d7bSbt 5409da57d7bSbt /* 541c971fb7eSgg * s/w context structure for TCP/UDP checksum offload 542c971fb7eSgg * and LSO. 5439da57d7bSbt */ 544c971fb7eSgg ixgbe_tx_context_t tx_context; 5459da57d7bSbt 5469da57d7bSbt /* 5479da57d7bSbt * Tx ring settings and status 5489da57d7bSbt */ 5499da57d7bSbt uint32_t ring_size; /* Tx descriptor ring size */ 5509da57d7bSbt uint32_t free_list_size; /* Tx free list size */ 5519da57d7bSbt uint32_t copy_thresh; 5529da57d7bSbt uint32_t recycle_thresh; 5539da57d7bSbt uint32_t overload_thresh; 5549da57d7bSbt uint32_t resched_thresh; 5559da57d7bSbt 5569da57d7bSbt boolean_t reschedule; 5579da57d7bSbt uint32_t recycle_fail; 5589da57d7bSbt uint32_t stall_watchdog; 5599da57d7bSbt 5609da57d7bSbt #ifdef IXGBE_DEBUG 5619da57d7bSbt /* 5629da57d7bSbt * Debug statistics 5639da57d7bSbt */ 5649da57d7bSbt uint32_t stat_overload; 5659da57d7bSbt uint32_t stat_fail_no_tbd; 5669da57d7bSbt uint32_t stat_fail_no_tcb; 5679da57d7bSbt uint32_t stat_fail_dma_bind; 5689da57d7bSbt uint32_t stat_reschedule; 569*edf70dc9SPaul Guo uint32_t stat_break_tbd_limit; 570da14cebeSEric Cheng uint32_t stat_lso_header_fail; 5719da57d7bSbt #endif 5729da57d7bSbt 573da14cebeSEric Cheng mac_ring_handle_t ring_handle; 574da14cebeSEric Cheng 5759da57d7bSbt /* 5769da57d7bSbt * Pointer to the ixgbe struct 5779da57d7bSbt */ 5789da57d7bSbt struct ixgbe *ixgbe; 5799da57d7bSbt } ixgbe_tx_ring_t; 5809da57d7bSbt 5819da57d7bSbt /* 5829da57d7bSbt * Software Receive Ring 5839da57d7bSbt */ 5849da57d7bSbt typedef struct ixgbe_rx_ring { 5859da57d7bSbt uint32_t index; /* Ring index */ 5869da57d7bSbt uint32_t intr_vector; /* Interrupt vector index */ 5879da57d7bSbt uint32_t vect_bit; /* vector's bit in register */ 5889da57d7bSbt 5899da57d7bSbt /* 5909da57d7bSbt * Mutexes 5919da57d7bSbt */ 5929da57d7bSbt kmutex_t rx_lock; /* Rx access lock */ 5939da57d7bSbt kmutex_t recycle_lock; /* Recycle lock, for rcb_tail */ 5949da57d7bSbt 5959da57d7bSbt /* 5969da57d7bSbt * Rx descriptor ring definitions 5979da57d7bSbt */ 5989da57d7bSbt dma_buffer_t rbd_area; /* DMA buffer of rx desc ring */ 5999da57d7bSbt union ixgbe_adv_rx_desc *rbd_ring; /* Rx desc ring */ 6009da57d7bSbt uint32_t rbd_next; /* Index of next rx desc */ 6019da57d7bSbt 6029da57d7bSbt /* 6039da57d7bSbt * Rx control block list definitions 6049da57d7bSbt */ 6059da57d7bSbt rx_control_block_t *rcb_area; 6069da57d7bSbt rx_control_block_t **work_list; /* Work list of rcbs */ 6079da57d7bSbt rx_control_block_t **free_list; /* Free list of rcbs */ 6089da57d7bSbt uint32_t rcb_head; /* Index of next free rcb */ 6099da57d7bSbt uint32_t rcb_tail; /* Index to put recycled rcb */ 6109da57d7bSbt uint32_t rcb_free; /* Number of free rcbs */ 6119da57d7bSbt 6129da57d7bSbt /* 6139da57d7bSbt * Rx ring settings and status 6149da57d7bSbt */ 6159da57d7bSbt uint32_t ring_size; /* Rx descriptor ring size */ 6169da57d7bSbt uint32_t free_list_size; /* Rx free list size */ 6179da57d7bSbt uint32_t limit_per_intr; /* Max packets per interrupt */ 6189da57d7bSbt uint32_t copy_thresh; 6199da57d7bSbt 6209da57d7bSbt #ifdef IXGBE_DEBUG 6219da57d7bSbt /* 6229da57d7bSbt * Debug statistics 6239da57d7bSbt */ 6249da57d7bSbt uint32_t stat_frame_error; 6259da57d7bSbt uint32_t stat_cksum_error; 6269da57d7bSbt uint32_t stat_exceed_pkt; 6279da57d7bSbt #endif 6289da57d7bSbt 629da14cebeSEric Cheng mac_ring_handle_t ring_handle; 630da14cebeSEric Cheng uint64_t ring_gen_num; 6319da57d7bSbt 632da14cebeSEric Cheng struct ixgbe *ixgbe; /* Pointer to ixgbe struct */ 6339da57d7bSbt } ixgbe_rx_ring_t; 6349da57d7bSbt 635da14cebeSEric Cheng /* 636da14cebeSEric Cheng * Software Receive Ring Group 637da14cebeSEric Cheng */ 638da14cebeSEric Cheng typedef struct ixgbe_rx_group { 639da14cebeSEric Cheng uint32_t index; /* Group index */ 640da14cebeSEric Cheng mac_group_handle_t group_handle; /* call back group handle */ 641da14cebeSEric Cheng struct ixgbe *ixgbe; /* Pointer to ixgbe struct */ 642da14cebeSEric Cheng } ixgbe_rx_group_t; 643da14cebeSEric Cheng 6449da57d7bSbt /* 64573cd555cSBin Tu - Sun Microsystems - Beijing China * structure to map interrupt cleanup to msi-x vector 6469da57d7bSbt */ 64773cd555cSBin Tu - Sun Microsystems - Beijing China typedef struct ixgbe_intr_vector { 6489da57d7bSbt struct ixgbe *ixgbe; /* point to my adapter */ 6499da57d7bSbt ulong_t rx_map[BT_BITOUL(MAX_RX_QUEUE_NUM)]; /* bitmap of rx rings */ 6509da57d7bSbt int rxr_cnt; /* count rx rings */ 6519da57d7bSbt ulong_t tx_map[BT_BITOUL(MAX_TX_QUEUE_NUM)]; /* bitmap of tx rings */ 6529da57d7bSbt int txr_cnt; /* count tx rings */ 65373cd555cSBin Tu - Sun Microsystems - Beijing China ulong_t other_map[BT_BITOUL(2)]; /* bitmap of other */ 65473cd555cSBin Tu - Sun Microsystems - Beijing China int other_cnt; /* count other interrupt */ 65573cd555cSBin Tu - Sun Microsystems - Beijing China } ixgbe_intr_vector_t; 6569da57d7bSbt 6579da57d7bSbt /* 6589da57d7bSbt * Software adapter state 6599da57d7bSbt */ 6609da57d7bSbt typedef struct ixgbe { 6619da57d7bSbt int instance; 6629da57d7bSbt mac_handle_t mac_hdl; 6639da57d7bSbt dev_info_t *dip; 6649da57d7bSbt struct ixgbe_hw hw; 6659da57d7bSbt struct ixgbe_osdep osdep; 6669da57d7bSbt 66713740cb2SPaul Guo adapter_info_t *capab; /* adapter hardware capabilities */ 66813740cb2SPaul Guo ddi_taskq_t *lsc_taskq; /* link-status-change taskq */ 66913740cb2SPaul Guo uint32_t eims; /* interrupt mask setting */ 67073cd555cSBin Tu - Sun Microsystems - Beijing China uint32_t eimc; /* interrupt mask clear */ 67173cd555cSBin Tu - Sun Microsystems - Beijing China uint32_t eicr; /* interrupt cause reg */ 67213740cb2SPaul Guo 6739da57d7bSbt uint32_t ixgbe_state; 6749da57d7bSbt link_state_t link_state; 6759da57d7bSbt uint32_t link_speed; 6769da57d7bSbt uint32_t link_duplex; 6779da57d7bSbt uint32_t link_down_timeout; 6789da57d7bSbt 6799da57d7bSbt uint32_t reset_count; 6809da57d7bSbt uint32_t attach_progress; 6819da57d7bSbt uint32_t loopback_mode; 6829da57d7bSbt uint32_t default_mtu; 6839da57d7bSbt uint32_t max_frame_size; 6849da57d7bSbt 6859da57d7bSbt /* 68673cd555cSBin Tu - Sun Microsystems - Beijing China * Each msi-x vector: map vector to interrupt cleanup 6879da57d7bSbt */ 68873cd555cSBin Tu - Sun Microsystems - Beijing China ixgbe_intr_vector_t vect_map[MAX_INTR_VECTOR]; 6899da57d7bSbt 6909da57d7bSbt /* 6919da57d7bSbt * Receive Rings 6929da57d7bSbt */ 6939da57d7bSbt ixgbe_rx_ring_t *rx_rings; /* Array of rx rings */ 6949da57d7bSbt uint32_t num_rx_rings; /* Number of rx rings in use */ 6959da57d7bSbt uint32_t rx_ring_size; /* Rx descriptor ring size */ 6969da57d7bSbt uint32_t rx_buf_size; /* Rx buffer size */ 6979da57d7bSbt 698da14cebeSEric Cheng /* 699da14cebeSEric Cheng * Receive Groups 700da14cebeSEric Cheng */ 701da14cebeSEric Cheng ixgbe_rx_group_t *rx_groups; /* Array of rx groups */ 702da14cebeSEric Cheng uint32_t num_rx_groups; /* Number of rx groups in use */ 703da14cebeSEric Cheng 7049da57d7bSbt /* 7059da57d7bSbt * Transmit Rings 7069da57d7bSbt */ 7079da57d7bSbt ixgbe_tx_ring_t *tx_rings; /* Array of tx rings */ 7089da57d7bSbt uint32_t num_tx_rings; /* Number of tx rings in use */ 7099da57d7bSbt uint32_t tx_ring_size; /* Tx descriptor ring size */ 7109da57d7bSbt uint32_t tx_buf_size; /* Tx buffer size */ 7119da57d7bSbt 7129da57d7bSbt boolean_t tx_head_wb_enable; /* Tx head wrtie-back */ 7139da57d7bSbt boolean_t tx_hcksum_enable; /* Tx h/w cksum offload */ 7149da57d7bSbt boolean_t lso_enable; /* Large Segment Offload */ 715da14cebeSEric Cheng boolean_t mr_enable; /* Multiple Tx and Rx Ring */ 7169da57d7bSbt uint32_t tx_copy_thresh; /* Tx copy threshold */ 7179da57d7bSbt uint32_t tx_recycle_thresh; /* Tx recycle threshold */ 7189da57d7bSbt uint32_t tx_overload_thresh; /* Tx overload threshold */ 7199da57d7bSbt uint32_t tx_resched_thresh; /* Tx reschedule threshold */ 7209da57d7bSbt boolean_t rx_hcksum_enable; /* Rx h/w cksum offload */ 7219da57d7bSbt uint32_t rx_copy_thresh; /* Rx copy threshold */ 7229da57d7bSbt uint32_t rx_limit_per_intr; /* Rx pkts per interrupt */ 72373cd555cSBin Tu - Sun Microsystems - Beijing China uint32_t intr_throttling[MAX_INTR_VECTOR]; 7249da57d7bSbt uint32_t intr_force; 7259da57d7bSbt int fm_capabilities; /* FMA capabilities */ 7269da57d7bSbt 7279da57d7bSbt int intr_type; 7289da57d7bSbt int intr_cnt; 7299da57d7bSbt int intr_cap; 7309da57d7bSbt size_t intr_size; 7319da57d7bSbt uint_t intr_pri; 7329da57d7bSbt ddi_intr_handle_t *htable; 7339da57d7bSbt uint32_t eims_mask; 7349da57d7bSbt 7359da57d7bSbt kmutex_t gen_lock; /* General lock for device access */ 7369da57d7bSbt kmutex_t watchdog_lock; 7379da57d7bSbt 7389da57d7bSbt boolean_t watchdog_enable; 7399da57d7bSbt boolean_t watchdog_start; 7409da57d7bSbt timeout_id_t watchdog_tid; 7419da57d7bSbt 7429da57d7bSbt boolean_t unicst_init; 7439da57d7bSbt uint32_t unicst_avail; 7449da57d7bSbt uint32_t unicst_total; 7459da57d7bSbt ixgbe_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 7469da57d7bSbt uint32_t mcast_count; 7479da57d7bSbt struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES]; 7489da57d7bSbt 749da14cebeSEric Cheng ulong_t sys_page_size; 750da14cebeSEric Cheng 7519da57d7bSbt /* 7529da57d7bSbt * Kstat definitions 7539da57d7bSbt */ 7549da57d7bSbt kstat_t *ixgbe_ks; 7559da57d7bSbt 7569da57d7bSbt /* 7579da57d7bSbt * NDD definitions 7589da57d7bSbt */ 7599da57d7bSbt caddr_t nd_data; 7609da57d7bSbt nd_param_t nd_params[PARAM_COUNT]; 7619da57d7bSbt } ixgbe_t; 7629da57d7bSbt 7639da57d7bSbt typedef struct ixgbe_stat { 7649da57d7bSbt kstat_named_t link_speed; /* Link Speed */ 765da14cebeSEric Cheng 7669da57d7bSbt kstat_named_t reset_count; /* Reset Count */ 7679da57d7bSbt 7689da57d7bSbt kstat_named_t rx_frame_error; /* Rx Error in Packet */ 7699da57d7bSbt kstat_named_t rx_cksum_error; /* Rx Checksum Error */ 7709da57d7bSbt kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */ 7719da57d7bSbt 7729da57d7bSbt kstat_named_t tx_overload; /* Tx Desc Ring Overload */ 7739da57d7bSbt kstat_named_t tx_fail_no_tcb; /* Tx Fail Freelist Empty */ 7749da57d7bSbt kstat_named_t tx_fail_no_tbd; /* Tx Fail Desc Ring Empty */ 7759da57d7bSbt kstat_named_t tx_fail_dma_bind; /* Tx Fail DMA bind */ 7769da57d7bSbt kstat_named_t tx_reschedule; /* Tx Reschedule */ 7779da57d7bSbt 7789da57d7bSbt kstat_named_t gprc; /* Good Packets Received Count */ 7799da57d7bSbt kstat_named_t gptc; /* Good Packets Xmitted Count */ 7809da57d7bSbt kstat_named_t gor; /* Good Octets Received Count */ 7819da57d7bSbt kstat_named_t got; /* Good Octets Xmitd Count */ 7829da57d7bSbt kstat_named_t prc64; /* Packets Received - 64b */ 7839da57d7bSbt kstat_named_t prc127; /* Packets Received - 65-127b */ 7849da57d7bSbt kstat_named_t prc255; /* Packets Received - 127-255b */ 7859da57d7bSbt kstat_named_t prc511; /* Packets Received - 256-511b */ 7869da57d7bSbt kstat_named_t prc1023; /* Packets Received - 511-1023b */ 7879da57d7bSbt kstat_named_t prc1522; /* Packets Received - 1024-1522b */ 7889da57d7bSbt kstat_named_t ptc64; /* Packets Xmitted (64b) */ 7899da57d7bSbt kstat_named_t ptc127; /* Packets Xmitted (64-127b) */ 7909da57d7bSbt kstat_named_t ptc255; /* Packets Xmitted (128-255b) */ 7919da57d7bSbt kstat_named_t ptc511; /* Packets Xmitted (255-511b) */ 7929da57d7bSbt kstat_named_t ptc1023; /* Packets Xmitted (512-1023b) */ 7939da57d7bSbt kstat_named_t ptc1522; /* Packets Xmitted (1024-1522b */ 794da14cebeSEric Cheng kstat_named_t qprc[16]; /* Queue Packets Received Count */ 795da14cebeSEric Cheng kstat_named_t qptc[16]; /* Queue Packets Transmitted Count */ 796da14cebeSEric Cheng kstat_named_t qbrc[16]; /* Queue Bytes Received Count */ 797da14cebeSEric Cheng kstat_named_t qbtc[16]; /* Queue Bytes Transmitted Count */ 798da14cebeSEric Cheng 7999da57d7bSbt kstat_named_t crcerrs; /* CRC Error Count */ 8009da57d7bSbt kstat_named_t illerrc; /* Illegal Byte Error Count */ 8019da57d7bSbt kstat_named_t errbc; /* Error Byte Count */ 8029da57d7bSbt kstat_named_t mspdc; /* MAC Short Packet Discard Count */ 8039da57d7bSbt kstat_named_t mpc; /* Missed Packets Count */ 8049da57d7bSbt kstat_named_t mlfc; /* MAC Local Fault Count */ 8059da57d7bSbt kstat_named_t mrfc; /* MAC Remote Fault Count */ 8069da57d7bSbt kstat_named_t rlec; /* Receive Length Error Count */ 8079da57d7bSbt kstat_named_t lxontxc; /* Link XON Transmitted Count */ 8089da57d7bSbt kstat_named_t lxonrxc; /* Link XON Received Count */ 8099da57d7bSbt kstat_named_t lxofftxc; /* Link XOFF Transmitted Count */ 8109da57d7bSbt kstat_named_t lxoffrxc; /* Link XOFF Received Count */ 8119da57d7bSbt kstat_named_t bprc; /* Broadcasts Pkts Received Count */ 8129da57d7bSbt kstat_named_t mprc; /* Multicast Pkts Received Count */ 8139da57d7bSbt kstat_named_t rnbc; /* Receive No Buffers Count */ 8149da57d7bSbt kstat_named_t ruc; /* Receive Undersize Count */ 8159da57d7bSbt kstat_named_t rfc; /* Receive Frag Count */ 8169da57d7bSbt kstat_named_t roc; /* Receive Oversize Count */ 8179da57d7bSbt kstat_named_t rjc; /* Receive Jabber Count */ 8189da57d7bSbt kstat_named_t tor; /* Total Octets Recvd Count */ 819f27d3025Sgg kstat_named_t tot; /* Total Octets Xmitted Count */ 8209da57d7bSbt kstat_named_t tpr; /* Total Packets Received */ 8219da57d7bSbt kstat_named_t tpt; /* Total Packets Xmitted */ 8229da57d7bSbt kstat_named_t mptc; /* Multicast Packets Xmited Count */ 8239da57d7bSbt kstat_named_t bptc; /* Broadcast Packets Xmited Count */ 8249da57d7bSbt } ixgbe_stat_t; 8259da57d7bSbt 8269da57d7bSbt /* 8279da57d7bSbt * Function prototypes in ixgbe_buf.c 8289da57d7bSbt */ 8299da57d7bSbt int ixgbe_alloc_dma(ixgbe_t *); 8309da57d7bSbt void ixgbe_free_dma(ixgbe_t *); 8319da57d7bSbt void ixgbe_set_fma_flags(int, int); 8329da57d7bSbt 8339da57d7bSbt /* 8349da57d7bSbt * Function prototypes in ixgbe_main.c 8359da57d7bSbt */ 8369da57d7bSbt int ixgbe_start(ixgbe_t *); 8379da57d7bSbt void ixgbe_stop(ixgbe_t *); 8389da57d7bSbt int ixgbe_driver_setup_link(ixgbe_t *, boolean_t); 8399da57d7bSbt int ixgbe_multicst_add(ixgbe_t *, const uint8_t *); 8409da57d7bSbt int ixgbe_multicst_remove(ixgbe_t *, const uint8_t *); 8419da57d7bSbt enum ioc_reply ixgbe_loopback_ioctl(ixgbe_t *, struct iocblk *, mblk_t *); 8429da57d7bSbt 8439da57d7bSbt void ixgbe_enable_watchdog_timer(ixgbe_t *); 8449da57d7bSbt void ixgbe_disable_watchdog_timer(ixgbe_t *); 8459da57d7bSbt int ixgbe_atomic_reserve(uint32_t *, uint32_t); 8469da57d7bSbt 8479da57d7bSbt int ixgbe_check_acc_handle(ddi_acc_handle_t handle); 8489da57d7bSbt int ixgbe_check_dma_handle(ddi_dma_handle_t handle); 8499da57d7bSbt void ixgbe_fm_ereport(ixgbe_t *, char *); 8509da57d7bSbt 851da14cebeSEric Cheng void ixgbe_fill_ring(void *, mac_ring_type_t, const int, const int, 852da14cebeSEric Cheng mac_ring_info_t *, mac_ring_handle_t); 853da14cebeSEric Cheng void ixgbe_fill_group(void *arg, mac_ring_type_t, const int, 854da14cebeSEric Cheng mac_group_info_t *, mac_group_handle_t); 855da14cebeSEric Cheng int ixgbe_rx_ring_intr_enable(mac_intr_handle_t); 856da14cebeSEric Cheng int ixgbe_rx_ring_intr_disable(mac_intr_handle_t); 857da14cebeSEric Cheng 8589da57d7bSbt /* 8599da57d7bSbt * Function prototypes in ixgbe_gld.c 8609da57d7bSbt */ 8619da57d7bSbt int ixgbe_m_start(void *); 8629da57d7bSbt void ixgbe_m_stop(void *); 8639da57d7bSbt int ixgbe_m_promisc(void *, boolean_t); 8649da57d7bSbt int ixgbe_m_multicst(void *, boolean_t, const uint8_t *); 8659da57d7bSbt int ixgbe_m_stat(void *, uint_t, uint64_t *); 8669da57d7bSbt void ixgbe_m_resources(void *); 8679da57d7bSbt void ixgbe_m_ioctl(void *, queue_t *, mblk_t *); 8689da57d7bSbt boolean_t ixgbe_m_getcapab(void *, mac_capab_t, void *); 8699da57d7bSbt 8709da57d7bSbt /* 8719da57d7bSbt * Function prototypes in ixgbe_rx.c 8729da57d7bSbt */ 873da14cebeSEric Cheng mblk_t *ixgbe_ring_rx(ixgbe_rx_ring_t *, int); 8749da57d7bSbt void ixgbe_rx_recycle(caddr_t arg); 875da14cebeSEric Cheng mblk_t *ixgbe_ring_rx_poll(void *, int); 8769da57d7bSbt 8779da57d7bSbt /* 8789da57d7bSbt * Function prototypes in ixgbe_tx.c 8799da57d7bSbt */ 880da14cebeSEric Cheng mblk_t *ixgbe_ring_tx(void *, mblk_t *); 8819da57d7bSbt void ixgbe_free_tcb(tx_control_block_t *); 8829da57d7bSbt void ixgbe_put_free_list(ixgbe_tx_ring_t *, link_list_t *); 8839da57d7bSbt uint32_t ixgbe_tx_recycle_legacy(ixgbe_tx_ring_t *); 8849da57d7bSbt uint32_t ixgbe_tx_recycle_head_wb(ixgbe_tx_ring_t *); 8859da57d7bSbt 8869da57d7bSbt /* 8879da57d7bSbt * Function prototypes in ixgbe_log.c 8889da57d7bSbt */ 8899da57d7bSbt void ixgbe_notice(void *, const char *, ...); 8909da57d7bSbt void ixgbe_log(void *, const char *, ...); 8919da57d7bSbt void ixgbe_error(void *, const char *, ...); 8929da57d7bSbt 8939da57d7bSbt /* 8949da57d7bSbt * Function prototypes in ixgbe_ndd.c 8959da57d7bSbt */ 8969da57d7bSbt int ixgbe_nd_init(ixgbe_t *); 8979da57d7bSbt void ixgbe_nd_cleanup(ixgbe_t *); 8989da57d7bSbt enum ioc_reply ixgbe_nd_ioctl(ixgbe_t *, queue_t *, mblk_t *, struct iocblk *); 8999da57d7bSbt 9009da57d7bSbt /* 9019da57d7bSbt * Function prototypes in ixgbe_stat.c 9029da57d7bSbt */ 9039da57d7bSbt int ixgbe_init_stats(ixgbe_t *); 9049da57d7bSbt 9059da57d7bSbt #ifdef __cplusplus 9069da57d7bSbt } 9079da57d7bSbt #endif 9089da57d7bSbt 9099da57d7bSbt #endif /* _IXGBE_SW_H */ 910