1*9da57d7bSbt /* 2*9da57d7bSbt * CDDL HEADER START 3*9da57d7bSbt * 4*9da57d7bSbt * Copyright(c) 2007-2008 Intel Corporation. All rights reserved. 5*9da57d7bSbt * The contents of this file are subject to the terms of the 6*9da57d7bSbt * Common Development and Distribution License (the "License"). 7*9da57d7bSbt * You may not use this file except in compliance with the License. 8*9da57d7bSbt * 9*9da57d7bSbt * You can obtain a copy of the license at: 10*9da57d7bSbt * http://www.opensolaris.org/os/licensing. 11*9da57d7bSbt * See the License for the specific language governing permissions 12*9da57d7bSbt * and limitations under the License. 13*9da57d7bSbt * 14*9da57d7bSbt * When using or redistributing this file, you may do so under the 15*9da57d7bSbt * License only. No other modification of this header is permitted. 16*9da57d7bSbt * 17*9da57d7bSbt * If applicable, add the following below this CDDL HEADER, with the 18*9da57d7bSbt * fields enclosed by brackets "[]" replaced with your own identifying 19*9da57d7bSbt * information: Portions Copyright [yyyy] [name of copyright owner] 20*9da57d7bSbt * 21*9da57d7bSbt * CDDL HEADER END 22*9da57d7bSbt */ 23*9da57d7bSbt 24*9da57d7bSbt /* 25*9da57d7bSbt * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 26*9da57d7bSbt * Use is subject to license terms of the CDDL. 27*9da57d7bSbt */ 28*9da57d7bSbt 29*9da57d7bSbt #ifndef _IXGBE_SW_H 30*9da57d7bSbt #define _IXGBE_SW_H 31*9da57d7bSbt 32*9da57d7bSbt #pragma ident "%Z%%M% %I% %E% SMI" 33*9da57d7bSbt 34*9da57d7bSbt #ifdef __cplusplus 35*9da57d7bSbt extern "C" { 36*9da57d7bSbt #endif 37*9da57d7bSbt 38*9da57d7bSbt #include <sys/types.h> 39*9da57d7bSbt #include <sys/conf.h> 40*9da57d7bSbt #include <sys/debug.h> 41*9da57d7bSbt #include <sys/stropts.h> 42*9da57d7bSbt #include <sys/stream.h> 43*9da57d7bSbt #include <sys/strsun.h> 44*9da57d7bSbt #include <sys/strlog.h> 45*9da57d7bSbt #include <sys/kmem.h> 46*9da57d7bSbt #include <sys/stat.h> 47*9da57d7bSbt #include <sys/kstat.h> 48*9da57d7bSbt #include <sys/modctl.h> 49*9da57d7bSbt #include <sys/errno.h> 50*9da57d7bSbt #include <sys/dlpi.h> 51*9da57d7bSbt #include <sys/mac.h> 52*9da57d7bSbt #include <sys/mac_ether.h> 53*9da57d7bSbt #include <sys/vlan.h> 54*9da57d7bSbt #include <sys/ddi.h> 55*9da57d7bSbt #include <sys/sunddi.h> 56*9da57d7bSbt #include <sys/pci.h> 57*9da57d7bSbt #include <sys/pcie.h> 58*9da57d7bSbt #include <sys/sdt.h> 59*9da57d7bSbt #include <sys/ethernet.h> 60*9da57d7bSbt #include <sys/pattr.h> 61*9da57d7bSbt #include <sys/strsubr.h> 62*9da57d7bSbt #include <sys/netlb.h> 63*9da57d7bSbt #include <sys/random.h> 64*9da57d7bSbt #include <inet/common.h> 65*9da57d7bSbt #include <inet/ip.h> 66*9da57d7bSbt #include <inet/mi.h> 67*9da57d7bSbt #include <inet/nd.h> 68*9da57d7bSbt #include <sys/bitmap.h> 69*9da57d7bSbt #include <sys/ddifm.h> 70*9da57d7bSbt #include <sys/fm/protocol.h> 71*9da57d7bSbt #include <sys/fm/util.h> 72*9da57d7bSbt #include <sys/fm/io/ddi.h> 73*9da57d7bSbt #include "ixgbe_api.h" 74*9da57d7bSbt 75*9da57d7bSbt #define MODULE_NAME "ixgbe" /* module name */ 76*9da57d7bSbt 77*9da57d7bSbt #define IXGBE_FAILURE DDI_FAILURE 78*9da57d7bSbt 79*9da57d7bSbt #define IXGBE_UNKNOWN 0x00 80*9da57d7bSbt #define IXGBE_INITIALIZED 0x01 81*9da57d7bSbt #define IXGBE_STARTED 0x02 82*9da57d7bSbt #define IXGBE_SUSPENDED 0x04 83*9da57d7bSbt 84*9da57d7bSbt #define MAX_NUM_UNICAST_ADDRESSES 0x10 85*9da57d7bSbt #define MAX_NUM_MULTICAST_ADDRESSES 0x1000 86*9da57d7bSbt #define IXGBE_INTR_NONE 0 87*9da57d7bSbt #define IXGBE_INTR_MSIX 1 88*9da57d7bSbt #define IXGBE_INTR_MSI 2 89*9da57d7bSbt #define IXGBE_INTR_LEGACY 3 90*9da57d7bSbt 91*9da57d7bSbt #define MAX_COOKIE 16 92*9da57d7bSbt #define MIN_NUM_TX_DESC 2 93*9da57d7bSbt 94*9da57d7bSbt /* 95*9da57d7bSbt * Maximum values for user configurable parameters 96*9da57d7bSbt */ 97*9da57d7bSbt 98*9da57d7bSbt /* 99*9da57d7bSbt * MAX_xx_QUEUE_NUM values need to be the maximum of all supported 100*9da57d7bSbt * silicon types. 101*9da57d7bSbt */ 102*9da57d7bSbt #define MAX_TX_QUEUE_NUM 32 103*9da57d7bSbt #define MAX_RX_QUEUE_NUM 64 104*9da57d7bSbt 105*9da57d7bSbt #define MAX_TX_RING_SIZE 4096 106*9da57d7bSbt #define MAX_RX_RING_SIZE 4096 107*9da57d7bSbt 108*9da57d7bSbt #define MAX_MTU 16366 109*9da57d7bSbt #define MAX_RX_LIMIT_PER_INTR 4096 110*9da57d7bSbt #define MAX_INTR_THROTTLING 65535 111*9da57d7bSbt 112*9da57d7bSbt #define MAX_RX_COPY_THRESHOLD 9216 113*9da57d7bSbt #define MAX_TX_COPY_THRESHOLD 9216 114*9da57d7bSbt #define MAX_TX_RECYCLE_THRESHOLD DEFAULT_TX_RING_SIZE 115*9da57d7bSbt #define MAX_TX_OVERLOAD_THRESHOLD DEFAULT_TX_RING_SIZE 116*9da57d7bSbt #define MAX_TX_RESCHED_THRESHOLD DEFAULT_TX_RING_SIZE 117*9da57d7bSbt 118*9da57d7bSbt /* 119*9da57d7bSbt * Minimum values for user configurable parameters 120*9da57d7bSbt */ 121*9da57d7bSbt #define MIN_TX_QUEUE_NUM 1 122*9da57d7bSbt #define MIN_RX_QUEUE_NUM 1 123*9da57d7bSbt #define MIN_TX_RING_SIZE 64 124*9da57d7bSbt #define MIN_RX_RING_SIZE 64 125*9da57d7bSbt 126*9da57d7bSbt #define MIN_MTU ETHERMIN 127*9da57d7bSbt #define MIN_RX_LIMIT_PER_INTR 16 128*9da57d7bSbt #define MIN_INTR_THROTTLING 0 129*9da57d7bSbt #define MIN_TX_COPY_THRESHOLD 0 130*9da57d7bSbt #define MIN_RX_COPY_THRESHOLD 0 131*9da57d7bSbt #define MIN_TX_RECYCLE_THRESHOLD MIN_NUM_TX_DESC 132*9da57d7bSbt #define MIN_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 133*9da57d7bSbt #define MIN_TX_RESCHED_THRESHOLD MIN_NUM_TX_DESC 134*9da57d7bSbt 135*9da57d7bSbt /* 136*9da57d7bSbt * Default values for user configurable parameters 137*9da57d7bSbt */ 138*9da57d7bSbt #define DEFAULT_TX_QUEUE_NUM 1 139*9da57d7bSbt #define DEFAULT_RX_QUEUE_NUM 1 140*9da57d7bSbt #define DEFAULT_TX_RING_SIZE 512 141*9da57d7bSbt #define DEFAULT_RX_RING_SIZE 512 142*9da57d7bSbt 143*9da57d7bSbt #define DEFAULT_MTU ETHERMTU 144*9da57d7bSbt #define DEFAULT_RX_LIMIT_PER_INTR 256 145*9da57d7bSbt #define DEFAULT_INTR_THROTTLING 200 /* In unit of 256 nsec */ 146*9da57d7bSbt #define DEFAULT_RX_COPY_THRESHOLD 128 147*9da57d7bSbt #define DEFAULT_TX_COPY_THRESHOLD 512 148*9da57d7bSbt #define DEFAULT_TX_RECYCLE_THRESHOLD MAX_COOKIE 149*9da57d7bSbt #define DEFAULT_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 150*9da57d7bSbt #define DEFAULT_TX_RESCHED_THRESHOLD 128 151*9da57d7bSbt #define DEFAULT_FCRTH 0x20000 152*9da57d7bSbt #define DEFAULT_FCRTL 0x10000 153*9da57d7bSbt #define DEFAULT_FCPAUSE 0xFFFF 154*9da57d7bSbt 155*9da57d7bSbt #define TX_DRAIN_TIME 200 156*9da57d7bSbt #define RX_DRAIN_TIME 200 157*9da57d7bSbt 158*9da57d7bSbt #define STALL_WATCHDOG_TIMEOUT 8 /* 8 seconds */ 159*9da57d7bSbt #define MAX_LINK_DOWN_TIMEOUT 8 /* 8 seconds */ 160*9da57d7bSbt 161*9da57d7bSbt /* 162*9da57d7bSbt * limits on msi-x vectors for 82598 163*9da57d7bSbt */ 164*9da57d7bSbt #define IXGBE_MAX_INTR_VECTOR 18 165*9da57d7bSbt #define IXGBE_MAX_OTHER_VECTOR 2 166*9da57d7bSbt #define IXGBE_MAX_RING_VECTOR (IXGBE_MAX_INTR_VECTOR - IXGBE_MAX_OTHER_VECTOR) 167*9da57d7bSbt 168*9da57d7bSbt /* 169*9da57d7bSbt * Extra register bit masks for 82598 170*9da57d7bSbt */ 171*9da57d7bSbt #define IXGBE_PCS1GANA_FDC 0x20 172*9da57d7bSbt #define IXGBE_PCS1GANLP_LPFD 0x20 173*9da57d7bSbt #define IXGBE_PCS1GANLP_LPHD 0x40 174*9da57d7bSbt 175*9da57d7bSbt 176*9da57d7bSbt /* 177*9da57d7bSbt * Defined for IP header alignment. 178*9da57d7bSbt */ 179*9da57d7bSbt #define IPHDR_ALIGN_ROOM 2 180*9da57d7bSbt 181*9da57d7bSbt /* 182*9da57d7bSbt * Bit flags for attach_progress 183*9da57d7bSbt */ 184*9da57d7bSbt #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 185*9da57d7bSbt #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 186*9da57d7bSbt #define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */ 187*9da57d7bSbt #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */ 188*9da57d7bSbt #define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */ 189*9da57d7bSbt #define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */ 190*9da57d7bSbt #define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */ 191*9da57d7bSbt #define ATTACH_PROGRESS_INIT 0x0080 /* Device initialized */ 192*9da57d7bSbt #define ATTACH_PROGRESS_INIT_RINGS 0x0100 /* Rings initialized */ 193*9da57d7bSbt #define ATTACH_PROGRESS_STATS 0x0200 /* Kstats created */ 194*9da57d7bSbt #define ATTACH_PROGRESS_NDD 0x0400 /* NDD initialized */ 195*9da57d7bSbt #define ATTACH_PROGRESS_MAC 0x0800 /* MAC registered */ 196*9da57d7bSbt #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */ 197*9da57d7bSbt #define ATTACH_PROGRESS_FM_INIT 0x2000 /* FMA initialized */ 198*9da57d7bSbt 199*9da57d7bSbt #define PROP_DEFAULT_MTU "default_mtu" 200*9da57d7bSbt #define PROP_FLOW_CONTROL "flow_control" 201*9da57d7bSbt #define PROP_TX_QUEUE_NUM "tx_queue_number" 202*9da57d7bSbt #define PROP_TX_RING_SIZE "tx_ring_size" 203*9da57d7bSbt #define PROP_RX_QUEUE_NUM "rx_queue_number" 204*9da57d7bSbt #define PROP_RX_RING_SIZE "rx_ring_size" 205*9da57d7bSbt 206*9da57d7bSbt #define PROP_INTR_FORCE "intr_force" 207*9da57d7bSbt #define PROP_TX_HCKSUM_ENABLE "tx_hcksum_enable" 208*9da57d7bSbt #define PROP_RX_HCKSUM_ENABLE "rx_hcksum_enable" 209*9da57d7bSbt #define PROP_LSO_ENABLE "lso_enable" 210*9da57d7bSbt #define PROP_TX_HEAD_WB_ENABLE "tx_head_wb_enable" 211*9da57d7bSbt #define PROP_TX_COPY_THRESHOLD "tx_copy_threshold" 212*9da57d7bSbt #define PROP_TX_RECYCLE_THRESHOLD "tx_recycle_threshold" 213*9da57d7bSbt #define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold" 214*9da57d7bSbt #define PROP_TX_RESCHED_THRESHOLD "tx_resched_threshold" 215*9da57d7bSbt #define PROP_RX_COPY_THRESHOLD "rx_copy_threshold" 216*9da57d7bSbt #define PROP_RX_LIMIT_PER_INTR "rx_limit_per_intr" 217*9da57d7bSbt #define PROP_INTR_THROTTLING "intr_throttling" 218*9da57d7bSbt #define PROP_FM_CAPABLE "fm_capable" 219*9da57d7bSbt 220*9da57d7bSbt #define IXGBE_LB_NONE 0 221*9da57d7bSbt #define IXGBE_LB_EXTERNAL 1 222*9da57d7bSbt #define IXGBE_LB_INTERNAL_MAC 2 223*9da57d7bSbt #define IXGBE_LB_INTERNAL_PHY 3 224*9da57d7bSbt #define IXGBE_LB_INTERNAL_SERDES 4 225*9da57d7bSbt 226*9da57d7bSbt /* 227*9da57d7bSbt * Shorthand for the NDD parameters 228*9da57d7bSbt */ 229*9da57d7bSbt #define param_autoneg_cap nd_params[PARAM_AUTONEG_CAP].val 230*9da57d7bSbt #define param_pause_cap nd_params[PARAM_PAUSE_CAP].val 231*9da57d7bSbt #define param_asym_pause_cap nd_params[PARAM_ASYM_PAUSE_CAP].val 232*9da57d7bSbt #define param_10000fdx_cap nd_params[PARAM_10000FDX_CAP].val 233*9da57d7bSbt #define param_1000fdx_cap nd_params[PARAM_1000FDX_CAP].val 234*9da57d7bSbt #define param_100fdx_cap nd_params[PARAM_1000FDX_CAP].val 235*9da57d7bSbt #define param_rem_fault nd_params[PARAM_REM_FAULT].val 236*9da57d7bSbt 237*9da57d7bSbt #define param_adv_autoneg_cap nd_params[PARAM_ADV_AUTONEG_CAP].val 238*9da57d7bSbt #define param_adv_pause_cap nd_params[PARAM_ADV_PAUSE_CAP].val 239*9da57d7bSbt #define param_adv_asym_pause_cap nd_params[PARAM_ADV_ASYM_PAUSE_CAP].val 240*9da57d7bSbt #define param_adv_10000fdx_cap nd_params[PARAM_ADV_10000FDX_CAP].val 241*9da57d7bSbt #define param_adv_1000fdx_cap nd_params[PARAM_ADV_1000FDX_CAP].val 242*9da57d7bSbt #define param_adv_100fdx_cap nd_params[PARAM_ADV_1000FDX_CAP].val 243*9da57d7bSbt #define param_adv_rem_fault nd_params[PARAM_ADV_REM_FAULT].val 244*9da57d7bSbt 245*9da57d7bSbt #define param_lp_autoneg_cap nd_params[PARAM_LP_AUTONEG_CAP].val 246*9da57d7bSbt #define param_lp_pause_cap nd_params[PARAM_LP_PAUSE_CAP].val 247*9da57d7bSbt #define param_lp_asym_pause_cap nd_params[PARAM_LP_ASYM_PAUSE_CAP].val 248*9da57d7bSbt #define param_lp_10000fdx_cap nd_params[PARAM_LP_10000FDX_CAP].val 249*9da57d7bSbt #define param_lp_1000fdx_cap nd_params[PARAM_LP_1000FDX_CAP].val 250*9da57d7bSbt #define param_lp_100fdx_cap nd_params[PARAM_LP_1000FDX_CAP].val 251*9da57d7bSbt #define param_lp_rem_fault nd_params[PARAM_LP_REM_FAULT].val 252*9da57d7bSbt 253*9da57d7bSbt enum ioc_reply { 254*9da57d7bSbt IOC_INVAL = -1, /* bad, NAK with EINVAL */ 255*9da57d7bSbt IOC_DONE, /* OK, reply sent */ 256*9da57d7bSbt IOC_ACK, /* OK, just send ACK */ 257*9da57d7bSbt IOC_REPLY /* OK, just send reply */ 258*9da57d7bSbt }; 259*9da57d7bSbt 260*9da57d7bSbt #define MBLK_LEN(mp) ((uintptr_t)(mp)->b_wptr - \ 261*9da57d7bSbt (uintptr_t)(mp)->b_rptr) 262*9da57d7bSbt 263*9da57d7bSbt #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area)->dma_handle, \ 264*9da57d7bSbt 0, 0, (flag))) 265*9da57d7bSbt 266*9da57d7bSbt /* 267*9da57d7bSbt * Defined for ring index operations 268*9da57d7bSbt * ASSERT(index < limit) 269*9da57d7bSbt * ASSERT(step < limit) 270*9da57d7bSbt * ASSERT(index1 < limit) 271*9da57d7bSbt * ASSERT(index2 < limit) 272*9da57d7bSbt */ 273*9da57d7bSbt #define NEXT_INDEX(index, step, limit) (((index) + (step)) < (limit) ? \ 274*9da57d7bSbt (index) + (step) : (index) + (step) - (limit)) 275*9da57d7bSbt #define PREV_INDEX(index, step, limit) ((index) >= (step) ? \ 276*9da57d7bSbt (index) - (step) : (index) + (limit) - (step)) 277*9da57d7bSbt #define OFFSET(index1, index2, limit) ((index1) <= (index2) ? \ 278*9da57d7bSbt (index2) - (index1) : (index2) + (limit) - (index1)) 279*9da57d7bSbt 280*9da57d7bSbt #define LINK_LIST_INIT(_LH) \ 281*9da57d7bSbt (_LH)->head = (_LH)->tail = NULL 282*9da57d7bSbt 283*9da57d7bSbt #define LIST_GET_HEAD(_LH) ((single_link_t *)((_LH)->head)) 284*9da57d7bSbt 285*9da57d7bSbt #define LIST_POP_HEAD(_LH) \ 286*9da57d7bSbt (single_link_t *)(_LH)->head; \ 287*9da57d7bSbt { \ 288*9da57d7bSbt if ((_LH)->head != NULL) { \ 289*9da57d7bSbt (_LH)->head = (_LH)->head->link; \ 290*9da57d7bSbt if ((_LH)->head == NULL) \ 291*9da57d7bSbt (_LH)->tail = NULL; \ 292*9da57d7bSbt } \ 293*9da57d7bSbt } 294*9da57d7bSbt 295*9da57d7bSbt #define LIST_GET_TAIL(_LH) ((single_link_t *)((_LH)->tail)) 296*9da57d7bSbt 297*9da57d7bSbt #define LIST_PUSH_TAIL(_LH, _E) \ 298*9da57d7bSbt if ((_LH)->tail != NULL) { \ 299*9da57d7bSbt (_LH)->tail->link = (single_link_t *)(_E); \ 300*9da57d7bSbt (_LH)->tail = (single_link_t *)(_E); \ 301*9da57d7bSbt } else { \ 302*9da57d7bSbt (_LH)->head = (_LH)->tail = (single_link_t *)(_E); \ 303*9da57d7bSbt } \ 304*9da57d7bSbt (_E)->link = NULL; 305*9da57d7bSbt 306*9da57d7bSbt #define LIST_GET_NEXT(_LH, _E) \ 307*9da57d7bSbt (((_LH)->tail == (single_link_t *)(_E)) ? \ 308*9da57d7bSbt NULL : ((single_link_t *)(_E))->link) 309*9da57d7bSbt 310*9da57d7bSbt 311*9da57d7bSbt typedef struct single_link { 312*9da57d7bSbt struct single_link *link; 313*9da57d7bSbt } single_link_t; 314*9da57d7bSbt 315*9da57d7bSbt typedef struct link_list { 316*9da57d7bSbt single_link_t *head; 317*9da57d7bSbt single_link_t *tail; 318*9da57d7bSbt } link_list_t; 319*9da57d7bSbt 320*9da57d7bSbt /* 321*9da57d7bSbt * Property lookups 322*9da57d7bSbt */ 323*9da57d7bSbt #define IXGBE_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 324*9da57d7bSbt DDI_PROP_DONTPASS, (n)) 325*9da57d7bSbt #define IXGBE_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 326*9da57d7bSbt DDI_PROP_DONTPASS, (n), -1) 327*9da57d7bSbt 328*9da57d7bSbt 329*9da57d7bSbt /* 330*9da57d7bSbt * Named Data (ND) Parameter Management Structure 331*9da57d7bSbt */ 332*9da57d7bSbt typedef struct { 333*9da57d7bSbt struct ixgbe *private; 334*9da57d7bSbt uint32_t info; 335*9da57d7bSbt uint32_t min; 336*9da57d7bSbt uint32_t max; 337*9da57d7bSbt uint32_t val; 338*9da57d7bSbt char *name; 339*9da57d7bSbt } nd_param_t; 340*9da57d7bSbt 341*9da57d7bSbt /* 342*9da57d7bSbt * NDD parameter indexes, divided into: 343*9da57d7bSbt * 344*9da57d7bSbt * read-only parameters describing the hardware's capabilities 345*9da57d7bSbt * read-write parameters controlling the advertised capabilities 346*9da57d7bSbt * read-only parameters describing the partner's capabilities 347*9da57d7bSbt * read-write parameters controlling the force speed and duplex 348*9da57d7bSbt * read-only parameters describing the link state 349*9da57d7bSbt * read-only parameters describing the driver properties 350*9da57d7bSbt * read-write parameters controlling the driver properties 351*9da57d7bSbt */ 352*9da57d7bSbt enum { 353*9da57d7bSbt PARAM_AUTONEG_CAP, 354*9da57d7bSbt PARAM_PAUSE_CAP, 355*9da57d7bSbt PARAM_ASYM_PAUSE_CAP, 356*9da57d7bSbt PARAM_10000FDX_CAP, 357*9da57d7bSbt PARAM_1000FDX_CAP, 358*9da57d7bSbt PARAM_100FDX_CAP, 359*9da57d7bSbt PARAM_REM_FAULT, 360*9da57d7bSbt 361*9da57d7bSbt PARAM_ADV_AUTONEG_CAP, 362*9da57d7bSbt PARAM_ADV_PAUSE_CAP, 363*9da57d7bSbt PARAM_ADV_ASYM_PAUSE_CAP, 364*9da57d7bSbt PARAM_ADV_10000FDX_CAP, 365*9da57d7bSbt PARAM_ADV_1000FDX_CAP, 366*9da57d7bSbt PARAM_ADV_100FDX_CAP, 367*9da57d7bSbt PARAM_ADV_REM_FAULT, 368*9da57d7bSbt 369*9da57d7bSbt PARAM_LP_AUTONEG_CAP, 370*9da57d7bSbt PARAM_LP_PAUSE_CAP, 371*9da57d7bSbt PARAM_LP_ASYM_PAUSE_CAP, 372*9da57d7bSbt PARAM_LP_10000FDX_CAP, 373*9da57d7bSbt PARAM_LP_1000FDX_CAP, 374*9da57d7bSbt PARAM_LP_100FDX_CAP, 375*9da57d7bSbt PARAM_LP_REM_FAULT, 376*9da57d7bSbt 377*9da57d7bSbt PARAM_LINK_STATUS, 378*9da57d7bSbt PARAM_LINK_SPEED, 379*9da57d7bSbt PARAM_LINK_DUPLEX, 380*9da57d7bSbt 381*9da57d7bSbt PARAM_COUNT 382*9da57d7bSbt }; 383*9da57d7bSbt 384*9da57d7bSbt typedef union ixgbe_ether_addr { 385*9da57d7bSbt struct { 386*9da57d7bSbt uint32_t high; 387*9da57d7bSbt uint32_t low; 388*9da57d7bSbt } reg; 389*9da57d7bSbt struct { 390*9da57d7bSbt uint8_t set; 391*9da57d7bSbt uint8_t redundant; 392*9da57d7bSbt uint8_t addr[ETHERADDRL]; 393*9da57d7bSbt } mac; 394*9da57d7bSbt } ixgbe_ether_addr_t; 395*9da57d7bSbt 396*9da57d7bSbt typedef enum { 397*9da57d7bSbt USE_NONE, 398*9da57d7bSbt USE_COPY, 399*9da57d7bSbt USE_DMA 400*9da57d7bSbt } tx_type_t; 401*9da57d7bSbt 402*9da57d7bSbt typedef enum { 403*9da57d7bSbt RCB_FREE, 404*9da57d7bSbt RCB_SENDUP 405*9da57d7bSbt } rcb_state_t; 406*9da57d7bSbt 407*9da57d7bSbt typedef struct hcksum_context { 408*9da57d7bSbt uint32_t hcksum_flags; 409*9da57d7bSbt uint32_t ip_hdr_len; 410*9da57d7bSbt uint32_t mac_hdr_len; 411*9da57d7bSbt uint32_t l4_proto; 412*9da57d7bSbt } hcksum_context_t; 413*9da57d7bSbt 414*9da57d7bSbt /* 415*9da57d7bSbt * Hold address/length of each DMA segment 416*9da57d7bSbt */ 417*9da57d7bSbt typedef struct sw_desc { 418*9da57d7bSbt uint64_t address; 419*9da57d7bSbt size_t length; 420*9da57d7bSbt } sw_desc_t; 421*9da57d7bSbt 422*9da57d7bSbt /* 423*9da57d7bSbt * Handles and addresses of DMA buffer 424*9da57d7bSbt */ 425*9da57d7bSbt typedef struct dma_buffer { 426*9da57d7bSbt caddr_t address; /* Virtual address */ 427*9da57d7bSbt uint64_t dma_address; /* DMA (Hardware) address */ 428*9da57d7bSbt ddi_acc_handle_t acc_handle; /* Data access handle */ 429*9da57d7bSbt ddi_dma_handle_t dma_handle; /* DMA handle */ 430*9da57d7bSbt size_t size; /* Buffer size */ 431*9da57d7bSbt size_t len; /* Data length in the buffer */ 432*9da57d7bSbt } dma_buffer_t; 433*9da57d7bSbt 434*9da57d7bSbt /* 435*9da57d7bSbt * Tx Control Block 436*9da57d7bSbt */ 437*9da57d7bSbt typedef struct tx_control_block { 438*9da57d7bSbt single_link_t link; 439*9da57d7bSbt uint32_t frag_num; 440*9da57d7bSbt uint32_t desc_num; 441*9da57d7bSbt mblk_t *mp; 442*9da57d7bSbt tx_type_t tx_type; 443*9da57d7bSbt ddi_dma_handle_t tx_dma_handle; 444*9da57d7bSbt dma_buffer_t tx_buf; 445*9da57d7bSbt sw_desc_t desc[MAX_COOKIE]; 446*9da57d7bSbt } tx_control_block_t; 447*9da57d7bSbt 448*9da57d7bSbt /* 449*9da57d7bSbt * RX Control Block 450*9da57d7bSbt */ 451*9da57d7bSbt typedef struct rx_control_block { 452*9da57d7bSbt mblk_t *mp; 453*9da57d7bSbt rcb_state_t state; 454*9da57d7bSbt dma_buffer_t rx_buf; 455*9da57d7bSbt frtn_t free_rtn; 456*9da57d7bSbt struct ixgbe_rx_ring *rx_ring; 457*9da57d7bSbt } rx_control_block_t; 458*9da57d7bSbt 459*9da57d7bSbt /* 460*9da57d7bSbt * Software Data Structure for Tx Ring 461*9da57d7bSbt */ 462*9da57d7bSbt typedef struct ixgbe_tx_ring { 463*9da57d7bSbt uint32_t index; /* Ring index */ 464*9da57d7bSbt uint32_t intr_vector; /* Interrupt vector index */ 465*9da57d7bSbt uint32_t vect_bit; /* vector's bit in register */ 466*9da57d7bSbt 467*9da57d7bSbt /* 468*9da57d7bSbt * Mutexes 469*9da57d7bSbt */ 470*9da57d7bSbt kmutex_t tx_lock; 471*9da57d7bSbt kmutex_t recycle_lock; 472*9da57d7bSbt kmutex_t tcb_head_lock; 473*9da57d7bSbt kmutex_t tcb_tail_lock; 474*9da57d7bSbt 475*9da57d7bSbt /* 476*9da57d7bSbt * Tx descriptor ring definitions 477*9da57d7bSbt */ 478*9da57d7bSbt dma_buffer_t tbd_area; 479*9da57d7bSbt union ixgbe_adv_tx_desc *tbd_ring; 480*9da57d7bSbt uint32_t tbd_head; /* Index of next tbd to recycle */ 481*9da57d7bSbt uint32_t tbd_tail; /* Index of next tbd to transmit */ 482*9da57d7bSbt uint32_t tbd_free; /* Number of free tbd */ 483*9da57d7bSbt 484*9da57d7bSbt /* 485*9da57d7bSbt * Tx control block list definitions 486*9da57d7bSbt */ 487*9da57d7bSbt tx_control_block_t *tcb_area; 488*9da57d7bSbt tx_control_block_t **work_list; 489*9da57d7bSbt tx_control_block_t **free_list; 490*9da57d7bSbt uint32_t tcb_head; /* Head index of free list */ 491*9da57d7bSbt uint32_t tcb_tail; /* Tail index of free list */ 492*9da57d7bSbt uint32_t tcb_free; /* Number of free tcb in free list */ 493*9da57d7bSbt 494*9da57d7bSbt uint32_t *tbd_head_wb; /* Head write-back */ 495*9da57d7bSbt uint32_t (*tx_recycle)(struct ixgbe_tx_ring *); 496*9da57d7bSbt 497*9da57d7bSbt /* 498*9da57d7bSbt * TCP/UDP checksum offload 499*9da57d7bSbt */ 500*9da57d7bSbt hcksum_context_t hcksum_context; 501*9da57d7bSbt 502*9da57d7bSbt /* 503*9da57d7bSbt * Tx ring settings and status 504*9da57d7bSbt */ 505*9da57d7bSbt uint32_t ring_size; /* Tx descriptor ring size */ 506*9da57d7bSbt uint32_t free_list_size; /* Tx free list size */ 507*9da57d7bSbt uint32_t copy_thresh; 508*9da57d7bSbt uint32_t recycle_thresh; 509*9da57d7bSbt uint32_t overload_thresh; 510*9da57d7bSbt uint32_t resched_thresh; 511*9da57d7bSbt 512*9da57d7bSbt boolean_t reschedule; 513*9da57d7bSbt uint32_t recycle_fail; 514*9da57d7bSbt uint32_t stall_watchdog; 515*9da57d7bSbt 516*9da57d7bSbt #ifdef IXGBE_DEBUG 517*9da57d7bSbt /* 518*9da57d7bSbt * Debug statistics 519*9da57d7bSbt */ 520*9da57d7bSbt uint32_t stat_overload; 521*9da57d7bSbt uint32_t stat_fail_no_tbd; 522*9da57d7bSbt uint32_t stat_fail_no_tcb; 523*9da57d7bSbt uint32_t stat_fail_dma_bind; 524*9da57d7bSbt uint32_t stat_reschedule; 525*9da57d7bSbt #endif 526*9da57d7bSbt 527*9da57d7bSbt /* 528*9da57d7bSbt * Pointer to the ixgbe struct 529*9da57d7bSbt */ 530*9da57d7bSbt struct ixgbe *ixgbe; 531*9da57d7bSbt 532*9da57d7bSbt } ixgbe_tx_ring_t; 533*9da57d7bSbt 534*9da57d7bSbt /* 535*9da57d7bSbt * Software Receive Ring 536*9da57d7bSbt */ 537*9da57d7bSbt typedef struct ixgbe_rx_ring { 538*9da57d7bSbt uint32_t index; /* Ring index */ 539*9da57d7bSbt uint32_t intr_vector; /* Interrupt vector index */ 540*9da57d7bSbt uint32_t vect_bit; /* vector's bit in register */ 541*9da57d7bSbt 542*9da57d7bSbt /* 543*9da57d7bSbt * Mutexes 544*9da57d7bSbt */ 545*9da57d7bSbt kmutex_t rx_lock; /* Rx access lock */ 546*9da57d7bSbt kmutex_t recycle_lock; /* Recycle lock, for rcb_tail */ 547*9da57d7bSbt 548*9da57d7bSbt /* 549*9da57d7bSbt * Rx descriptor ring definitions 550*9da57d7bSbt */ 551*9da57d7bSbt dma_buffer_t rbd_area; /* DMA buffer of rx desc ring */ 552*9da57d7bSbt union ixgbe_adv_rx_desc *rbd_ring; /* Rx desc ring */ 553*9da57d7bSbt uint32_t rbd_next; /* Index of next rx desc */ 554*9da57d7bSbt 555*9da57d7bSbt /* 556*9da57d7bSbt * Rx control block list definitions 557*9da57d7bSbt */ 558*9da57d7bSbt rx_control_block_t *rcb_area; 559*9da57d7bSbt rx_control_block_t **work_list; /* Work list of rcbs */ 560*9da57d7bSbt rx_control_block_t **free_list; /* Free list of rcbs */ 561*9da57d7bSbt uint32_t rcb_head; /* Index of next free rcb */ 562*9da57d7bSbt uint32_t rcb_tail; /* Index to put recycled rcb */ 563*9da57d7bSbt uint32_t rcb_free; /* Number of free rcbs */ 564*9da57d7bSbt 565*9da57d7bSbt /* 566*9da57d7bSbt * Rx ring settings and status 567*9da57d7bSbt */ 568*9da57d7bSbt uint32_t ring_size; /* Rx descriptor ring size */ 569*9da57d7bSbt uint32_t free_list_size; /* Rx free list size */ 570*9da57d7bSbt uint32_t limit_per_intr; /* Max packets per interrupt */ 571*9da57d7bSbt uint32_t copy_thresh; 572*9da57d7bSbt 573*9da57d7bSbt #ifdef IXGBE_DEBUG 574*9da57d7bSbt /* 575*9da57d7bSbt * Debug statistics 576*9da57d7bSbt */ 577*9da57d7bSbt uint32_t stat_frame_error; 578*9da57d7bSbt uint32_t stat_cksum_error; 579*9da57d7bSbt uint32_t stat_exceed_pkt; 580*9da57d7bSbt #endif 581*9da57d7bSbt 582*9da57d7bSbt struct ixgbe *ixgbe; /* Pointer to ixgbe struct */ 583*9da57d7bSbt 584*9da57d7bSbt } ixgbe_rx_ring_t; 585*9da57d7bSbt 586*9da57d7bSbt /* 587*9da57d7bSbt * structure to map ring cleanup to msi-x vector 588*9da57d7bSbt */ 589*9da57d7bSbt typedef struct ixgbe_ring_vector { 590*9da57d7bSbt struct ixgbe *ixgbe; /* point to my adapter */ 591*9da57d7bSbt ulong_t rx_map[BT_BITOUL(MAX_RX_QUEUE_NUM)]; /* bitmap of rx rings */ 592*9da57d7bSbt int rxr_cnt; /* count rx rings */ 593*9da57d7bSbt ulong_t tx_map[BT_BITOUL(MAX_TX_QUEUE_NUM)]; /* bitmap of tx rings */ 594*9da57d7bSbt int txr_cnt; /* count tx rings */ 595*9da57d7bSbt } ixgbe_ring_vector_t; 596*9da57d7bSbt 597*9da57d7bSbt /* 598*9da57d7bSbt * Software adapter state 599*9da57d7bSbt */ 600*9da57d7bSbt typedef struct ixgbe { 601*9da57d7bSbt int instance; 602*9da57d7bSbt mac_handle_t mac_hdl; 603*9da57d7bSbt dev_info_t *dip; 604*9da57d7bSbt struct ixgbe_hw hw; 605*9da57d7bSbt struct ixgbe_osdep osdep; 606*9da57d7bSbt 607*9da57d7bSbt uint32_t ixgbe_state; 608*9da57d7bSbt link_state_t link_state; 609*9da57d7bSbt uint32_t link_speed; 610*9da57d7bSbt uint32_t link_duplex; 611*9da57d7bSbt uint32_t link_down_timeout; 612*9da57d7bSbt 613*9da57d7bSbt uint32_t reset_count; 614*9da57d7bSbt uint32_t attach_progress; 615*9da57d7bSbt uint32_t loopback_mode; 616*9da57d7bSbt uint32_t default_mtu; 617*9da57d7bSbt uint32_t max_frame_size; 618*9da57d7bSbt 619*9da57d7bSbt /* 620*9da57d7bSbt * Each msi-x vector: map vector to ring cleanup 621*9da57d7bSbt */ 622*9da57d7bSbt ixgbe_ring_vector_t vect_map[IXGBE_MAX_RING_VECTOR]; 623*9da57d7bSbt 624*9da57d7bSbt /* 625*9da57d7bSbt * Receive Rings 626*9da57d7bSbt */ 627*9da57d7bSbt ixgbe_rx_ring_t *rx_rings; /* Array of rx rings */ 628*9da57d7bSbt uint32_t num_rx_rings; /* Number of rx rings in use */ 629*9da57d7bSbt uint32_t rx_ring_size; /* Rx descriptor ring size */ 630*9da57d7bSbt uint32_t rx_buf_size; /* Rx buffer size */ 631*9da57d7bSbt 632*9da57d7bSbt /* 633*9da57d7bSbt * Transmit Rings 634*9da57d7bSbt */ 635*9da57d7bSbt ixgbe_tx_ring_t *tx_rings; /* Array of tx rings */ 636*9da57d7bSbt uint32_t num_tx_rings; /* Number of tx rings in use */ 637*9da57d7bSbt uint32_t tx_ring_size; /* Tx descriptor ring size */ 638*9da57d7bSbt uint32_t tx_buf_size; /* Tx buffer size */ 639*9da57d7bSbt 640*9da57d7bSbt boolean_t tx_head_wb_enable; /* Tx head wrtie-back */ 641*9da57d7bSbt boolean_t tx_hcksum_enable; /* Tx h/w cksum offload */ 642*9da57d7bSbt boolean_t lso_enable; /* Large Segment Offload */ 643*9da57d7bSbt uint32_t tx_copy_thresh; /* Tx copy threshold */ 644*9da57d7bSbt uint32_t tx_recycle_thresh; /* Tx recycle threshold */ 645*9da57d7bSbt uint32_t tx_overload_thresh; /* Tx overload threshold */ 646*9da57d7bSbt uint32_t tx_resched_thresh; /* Tx reschedule threshold */ 647*9da57d7bSbt boolean_t rx_hcksum_enable; /* Rx h/w cksum offload */ 648*9da57d7bSbt uint32_t rx_copy_thresh; /* Rx copy threshold */ 649*9da57d7bSbt uint32_t rx_limit_per_intr; /* Rx pkts per interrupt */ 650*9da57d7bSbt uint32_t intr_throttling[IXGBE_MAX_RING_VECTOR]; 651*9da57d7bSbt uint32_t intr_force; 652*9da57d7bSbt int fm_capabilities; /* FMA capabilities */ 653*9da57d7bSbt 654*9da57d7bSbt int intr_type; 655*9da57d7bSbt int intr_cnt; 656*9da57d7bSbt int intr_cap; 657*9da57d7bSbt size_t intr_size; 658*9da57d7bSbt uint_t intr_pri; 659*9da57d7bSbt ddi_intr_handle_t *htable; 660*9da57d7bSbt uint32_t eims_mask; 661*9da57d7bSbt 662*9da57d7bSbt kmutex_t gen_lock; /* General lock for device access */ 663*9da57d7bSbt kmutex_t watchdog_lock; 664*9da57d7bSbt 665*9da57d7bSbt boolean_t watchdog_enable; 666*9da57d7bSbt boolean_t watchdog_start; 667*9da57d7bSbt timeout_id_t watchdog_tid; 668*9da57d7bSbt 669*9da57d7bSbt boolean_t unicst_init; 670*9da57d7bSbt uint32_t unicst_avail; 671*9da57d7bSbt uint32_t unicst_total; 672*9da57d7bSbt ixgbe_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 673*9da57d7bSbt uint32_t mcast_count; 674*9da57d7bSbt struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES]; 675*9da57d7bSbt 676*9da57d7bSbt /* 677*9da57d7bSbt * Kstat definitions 678*9da57d7bSbt */ 679*9da57d7bSbt kstat_t *ixgbe_ks; 680*9da57d7bSbt 681*9da57d7bSbt /* 682*9da57d7bSbt * NDD definitions 683*9da57d7bSbt */ 684*9da57d7bSbt caddr_t nd_data; 685*9da57d7bSbt nd_param_t nd_params[PARAM_COUNT]; 686*9da57d7bSbt 687*9da57d7bSbt } ixgbe_t; 688*9da57d7bSbt 689*9da57d7bSbt typedef struct ixgbe_stat { 690*9da57d7bSbt 691*9da57d7bSbt kstat_named_t link_speed; /* Link Speed */ 692*9da57d7bSbt #ifdef IXGBE_DEBUG 693*9da57d7bSbt kstat_named_t reset_count; /* Reset Count */ 694*9da57d7bSbt 695*9da57d7bSbt kstat_named_t rx_frame_error; /* Rx Error in Packet */ 696*9da57d7bSbt kstat_named_t rx_cksum_error; /* Rx Checksum Error */ 697*9da57d7bSbt kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */ 698*9da57d7bSbt 699*9da57d7bSbt kstat_named_t tx_overload; /* Tx Desc Ring Overload */ 700*9da57d7bSbt kstat_named_t tx_fail_no_tcb; /* Tx Fail Freelist Empty */ 701*9da57d7bSbt kstat_named_t tx_fail_no_tbd; /* Tx Fail Desc Ring Empty */ 702*9da57d7bSbt kstat_named_t tx_fail_dma_bind; /* Tx Fail DMA bind */ 703*9da57d7bSbt kstat_named_t tx_reschedule; /* Tx Reschedule */ 704*9da57d7bSbt 705*9da57d7bSbt kstat_named_t gprc; /* Good Packets Received Count */ 706*9da57d7bSbt kstat_named_t gptc; /* Good Packets Xmitted Count */ 707*9da57d7bSbt kstat_named_t gor; /* Good Octets Received Count */ 708*9da57d7bSbt kstat_named_t got; /* Good Octets Xmitd Count */ 709*9da57d7bSbt kstat_named_t prc64; /* Packets Received - 64b */ 710*9da57d7bSbt kstat_named_t prc127; /* Packets Received - 65-127b */ 711*9da57d7bSbt kstat_named_t prc255; /* Packets Received - 127-255b */ 712*9da57d7bSbt kstat_named_t prc511; /* Packets Received - 256-511b */ 713*9da57d7bSbt kstat_named_t prc1023; /* Packets Received - 511-1023b */ 714*9da57d7bSbt kstat_named_t prc1522; /* Packets Received - 1024-1522b */ 715*9da57d7bSbt kstat_named_t ptc64; /* Packets Xmitted (64b) */ 716*9da57d7bSbt kstat_named_t ptc127; /* Packets Xmitted (64-127b) */ 717*9da57d7bSbt kstat_named_t ptc255; /* Packets Xmitted (128-255b) */ 718*9da57d7bSbt kstat_named_t ptc511; /* Packets Xmitted (255-511b) */ 719*9da57d7bSbt kstat_named_t ptc1023; /* Packets Xmitted (512-1023b) */ 720*9da57d7bSbt kstat_named_t ptc1522; /* Packets Xmitted (1024-1522b */ 721*9da57d7bSbt #endif 722*9da57d7bSbt kstat_named_t crcerrs; /* CRC Error Count */ 723*9da57d7bSbt kstat_named_t illerrc; /* Illegal Byte Error Count */ 724*9da57d7bSbt kstat_named_t errbc; /* Error Byte Count */ 725*9da57d7bSbt kstat_named_t mspdc; /* MAC Short Packet Discard Count */ 726*9da57d7bSbt kstat_named_t mpc; /* Missed Packets Count */ 727*9da57d7bSbt kstat_named_t mlfc; /* MAC Local Fault Count */ 728*9da57d7bSbt kstat_named_t mrfc; /* MAC Remote Fault Count */ 729*9da57d7bSbt kstat_named_t rlec; /* Receive Length Error Count */ 730*9da57d7bSbt kstat_named_t lxontxc; /* Link XON Transmitted Count */ 731*9da57d7bSbt kstat_named_t lxonrxc; /* Link XON Received Count */ 732*9da57d7bSbt kstat_named_t lxofftxc; /* Link XOFF Transmitted Count */ 733*9da57d7bSbt kstat_named_t lxoffrxc; /* Link XOFF Received Count */ 734*9da57d7bSbt kstat_named_t bprc; /* Broadcasts Pkts Received Count */ 735*9da57d7bSbt kstat_named_t mprc; /* Multicast Pkts Received Count */ 736*9da57d7bSbt kstat_named_t rnbc; /* Receive No Buffers Count */ 737*9da57d7bSbt kstat_named_t ruc; /* Receive Undersize Count */ 738*9da57d7bSbt kstat_named_t rfc; /* Receive Frag Count */ 739*9da57d7bSbt kstat_named_t roc; /* Receive Oversize Count */ 740*9da57d7bSbt kstat_named_t rjc; /* Receive Jabber Count */ 741*9da57d7bSbt kstat_named_t tor; /* Total Octets Recvd Count */ 742*9da57d7bSbt kstat_named_t tpr; /* Total Packets Received */ 743*9da57d7bSbt kstat_named_t tpt; /* Total Packets Xmitted */ 744*9da57d7bSbt kstat_named_t mptc; /* Multicast Packets Xmited Count */ 745*9da57d7bSbt kstat_named_t bptc; /* Broadcast Packets Xmited Count */ 746*9da57d7bSbt } ixgbe_stat_t; 747*9da57d7bSbt 748*9da57d7bSbt /* 749*9da57d7bSbt * Function prototypes in ixgbe_buf.c 750*9da57d7bSbt */ 751*9da57d7bSbt int ixgbe_alloc_dma(ixgbe_t *); 752*9da57d7bSbt void ixgbe_free_dma(ixgbe_t *); 753*9da57d7bSbt void ixgbe_set_fma_flags(int, int); 754*9da57d7bSbt 755*9da57d7bSbt /* 756*9da57d7bSbt * Function prototypes in ixgbe_main.c 757*9da57d7bSbt */ 758*9da57d7bSbt int ixgbe_start(ixgbe_t *); 759*9da57d7bSbt void ixgbe_stop(ixgbe_t *); 760*9da57d7bSbt int ixgbe_driver_setup_link(ixgbe_t *, boolean_t); 761*9da57d7bSbt int ixgbe_unicst_set(ixgbe_t *, const uint8_t *, mac_addr_slot_t); 762*9da57d7bSbt int ixgbe_multicst_add(ixgbe_t *, const uint8_t *); 763*9da57d7bSbt int ixgbe_multicst_remove(ixgbe_t *, const uint8_t *); 764*9da57d7bSbt enum ioc_reply ixgbe_loopback_ioctl(ixgbe_t *, struct iocblk *, mblk_t *); 765*9da57d7bSbt 766*9da57d7bSbt void ixgbe_enable_watchdog_timer(ixgbe_t *); 767*9da57d7bSbt void ixgbe_disable_watchdog_timer(ixgbe_t *); 768*9da57d7bSbt int ixgbe_atomic_reserve(uint32_t *, uint32_t); 769*9da57d7bSbt 770*9da57d7bSbt int ixgbe_check_acc_handle(ddi_acc_handle_t handle); 771*9da57d7bSbt int ixgbe_check_dma_handle(ddi_dma_handle_t handle); 772*9da57d7bSbt void ixgbe_fm_ereport(ixgbe_t *, char *); 773*9da57d7bSbt 774*9da57d7bSbt /* 775*9da57d7bSbt * Function prototypes in ixgbe_gld.c 776*9da57d7bSbt */ 777*9da57d7bSbt int ixgbe_m_start(void *); 778*9da57d7bSbt void ixgbe_m_stop(void *); 779*9da57d7bSbt int ixgbe_m_promisc(void *, boolean_t); 780*9da57d7bSbt int ixgbe_m_multicst(void *, boolean_t, const uint8_t *); 781*9da57d7bSbt int ixgbe_m_unicst(void *, const uint8_t *); 782*9da57d7bSbt int ixgbe_m_stat(void *, uint_t, uint64_t *); 783*9da57d7bSbt void ixgbe_m_resources(void *); 784*9da57d7bSbt void ixgbe_m_ioctl(void *, queue_t *, mblk_t *); 785*9da57d7bSbt int ixgbe_m_unicst_add(void *, mac_multi_addr_t *); 786*9da57d7bSbt int ixgbe_m_unicst_remove(void *, mac_addr_slot_t); 787*9da57d7bSbt int ixgbe_m_unicst_modify(void *, mac_multi_addr_t *); 788*9da57d7bSbt int ixgbe_m_unicst_get(void *, mac_multi_addr_t *); 789*9da57d7bSbt boolean_t ixgbe_m_getcapab(void *, mac_capab_t, void *); 790*9da57d7bSbt 791*9da57d7bSbt /* 792*9da57d7bSbt * Function prototypes in ixgbe_rx.c 793*9da57d7bSbt */ 794*9da57d7bSbt mblk_t *ixgbe_rx(ixgbe_rx_ring_t *); 795*9da57d7bSbt void ixgbe_rx_recycle(caddr_t arg); 796*9da57d7bSbt 797*9da57d7bSbt /* 798*9da57d7bSbt * Function prototypes in ixgbe_tx.c 799*9da57d7bSbt */ 800*9da57d7bSbt mblk_t *ixgbe_m_tx(void *, mblk_t *); 801*9da57d7bSbt void ixgbe_free_tcb(tx_control_block_t *); 802*9da57d7bSbt void ixgbe_put_free_list(ixgbe_tx_ring_t *, link_list_t *); 803*9da57d7bSbt uint32_t ixgbe_tx_recycle_legacy(ixgbe_tx_ring_t *); 804*9da57d7bSbt uint32_t ixgbe_tx_recycle_head_wb(ixgbe_tx_ring_t *); 805*9da57d7bSbt 806*9da57d7bSbt /* 807*9da57d7bSbt * Function prototypes in ixgbe_log.c 808*9da57d7bSbt */ 809*9da57d7bSbt void ixgbe_notice(void *, const char *, ...); 810*9da57d7bSbt void ixgbe_log(void *, const char *, ...); 811*9da57d7bSbt void ixgbe_error(void *, const char *, ...); 812*9da57d7bSbt 813*9da57d7bSbt /* 814*9da57d7bSbt * Function prototypes in ixgbe_ndd.c 815*9da57d7bSbt */ 816*9da57d7bSbt int ixgbe_nd_init(ixgbe_t *); 817*9da57d7bSbt void ixgbe_nd_cleanup(ixgbe_t *); 818*9da57d7bSbt enum ioc_reply ixgbe_nd_ioctl(ixgbe_t *, queue_t *, mblk_t *, struct iocblk *); 819*9da57d7bSbt 820*9da57d7bSbt /* 821*9da57d7bSbt * Function prototypes in ixgbe_stat.c 822*9da57d7bSbt */ 823*9da57d7bSbt int ixgbe_init_stats(ixgbe_t *); 824*9da57d7bSbt 825*9da57d7bSbt 826*9da57d7bSbt #ifdef __cplusplus 827*9da57d7bSbt } 828*9da57d7bSbt #endif 829*9da57d7bSbt 830*9da57d7bSbt #endif /* _IXGBE_SW_H */ 831