163b3bba8SJerry Jelinek /****************************************************************************** 2*48ed61a7SRobert Mustacchi SPDX-License-Identifier: BSD-3-Clause 363b3bba8SJerry Jelinek 4*48ed61a7SRobert Mustacchi Copyright (c) 2001-2017, Intel Corporation 563b3bba8SJerry Jelinek All rights reserved. 6*48ed61a7SRobert Mustacchi 7*48ed61a7SRobert Mustacchi Redistribution and use in source and binary forms, with or without 863b3bba8SJerry Jelinek modification, are permitted provided that the following conditions are met: 9*48ed61a7SRobert Mustacchi 10*48ed61a7SRobert Mustacchi 1. Redistributions of source code must retain the above copyright notice, 1163b3bba8SJerry Jelinek this list of conditions and the following disclaimer. 12*48ed61a7SRobert Mustacchi 13*48ed61a7SRobert Mustacchi 2. Redistributions in binary form must reproduce the above copyright 14*48ed61a7SRobert Mustacchi notice, this list of conditions and the following disclaimer in the 1563b3bba8SJerry Jelinek documentation and/or other materials provided with the distribution. 16*48ed61a7SRobert Mustacchi 17*48ed61a7SRobert Mustacchi 3. Neither the name of the Intel Corporation nor the names of its 18*48ed61a7SRobert Mustacchi contributors may be used to endorse or promote products derived from 1963b3bba8SJerry Jelinek this software without specific prior written permission. 20*48ed61a7SRobert Mustacchi 2163b3bba8SJerry Jelinek THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22*48ed61a7SRobert Mustacchi AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23*48ed61a7SRobert Mustacchi IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24*48ed61a7SRobert Mustacchi ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25*48ed61a7SRobert Mustacchi LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26*48ed61a7SRobert Mustacchi CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27*48ed61a7SRobert Mustacchi SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28*48ed61a7SRobert Mustacchi INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29*48ed61a7SRobert Mustacchi CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3063b3bba8SJerry Jelinek ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3163b3bba8SJerry Jelinek POSSIBILITY OF SUCH DAMAGE. 3263b3bba8SJerry Jelinek 3363b3bba8SJerry Jelinek ******************************************************************************/ 34dc0cb1cdSDale Ghent /*$FreeBSD$*/ 3563b3bba8SJerry Jelinek 3663b3bba8SJerry Jelinek #ifndef _IXGBE_TYPE_H_ 3763b3bba8SJerry Jelinek #define _IXGBE_TYPE_H_ 389da57d7bSbt 39dc0cb1cdSDale Ghent /* 40dc0cb1cdSDale Ghent * The following is a brief description of the error categories used by the 41dc0cb1cdSDale Ghent * ERROR_REPORT* macros. 42dc0cb1cdSDale Ghent * 43dc0cb1cdSDale Ghent * - IXGBE_ERROR_INVALID_STATE 44dc0cb1cdSDale Ghent * This category is for errors which represent a serious failure state that is 45dc0cb1cdSDale Ghent * unexpected, and could be potentially harmful to device operation. It should 46dc0cb1cdSDale Ghent * not be used for errors relating to issues that can be worked around or 47dc0cb1cdSDale Ghent * ignored. 48dc0cb1cdSDale Ghent * 49dc0cb1cdSDale Ghent * - IXGBE_ERROR_POLLING 50dc0cb1cdSDale Ghent * This category is for errors related to polling/timeout issues and should be 51dc0cb1cdSDale Ghent * used in any case where the timeout occurred, or a failure to obtain a lock, or 52dc0cb1cdSDale Ghent * failure to receive data within the time limit. 53dc0cb1cdSDale Ghent * 54dc0cb1cdSDale Ghent * - IXGBE_ERROR_CAUTION 55dc0cb1cdSDale Ghent * This category should be used for reporting issues that may be the cause of 56dc0cb1cdSDale Ghent * other errors, such as temperature warnings. It should indicate an event which 57dc0cb1cdSDale Ghent * could be serious, but hasn't necessarily caused problems yet. 58dc0cb1cdSDale Ghent * 59dc0cb1cdSDale Ghent * - IXGBE_ERROR_SOFTWARE 60dc0cb1cdSDale Ghent * This category is intended for errors due to software state preventing 61dc0cb1cdSDale Ghent * something. The category is not intended for errors due to bad arguments, or 62dc0cb1cdSDale Ghent * due to unsupported features. It should be used when a state occurs which 63dc0cb1cdSDale Ghent * prevents action but is not a serious issue. 64dc0cb1cdSDale Ghent * 65dc0cb1cdSDale Ghent * - IXGBE_ERROR_ARGUMENT 66dc0cb1cdSDale Ghent * This category is for when a bad or invalid argument is passed. It should be 67dc0cb1cdSDale Ghent * used whenever a function is called and error checking has detected the 68dc0cb1cdSDale Ghent * argument is wrong or incorrect. 69dc0cb1cdSDale Ghent * 70dc0cb1cdSDale Ghent * - IXGBE_ERROR_UNSUPPORTED 71dc0cb1cdSDale Ghent * This category is for errors which are due to unsupported circumstances or 72dc0cb1cdSDale Ghent * configuration issues. It should not be used when the issue is due to an 73dc0cb1cdSDale Ghent * invalid argument, but for when something has occurred that is unsupported 74dc0cb1cdSDale Ghent * (Ex: Flow control autonegotiation or an unsupported SFP+ module.) 75dc0cb1cdSDale Ghent */ 76dc0cb1cdSDale Ghent 779da57d7bSbt #include "ixgbe_osdep.h" 789da57d7bSbt 79dc0cb1cdSDale Ghent /* Override this by setting IOMEM in your ixgbe_osdep.h header */ 80dc0cb1cdSDale Ghent #define IOMEM 8163b3bba8SJerry Jelinek 829da57d7bSbt /* Vendor ID */ 8369b5a878SDan McDonald #define IXGBE_INTEL_VENDOR_ID 0x8086 849da57d7bSbt 859da57d7bSbt /* Device IDs */ 8669b5a878SDan McDonald #define IXGBE_DEV_ID_82598 0x10B6 8769b5a878SDan McDonald #define IXGBE_DEV_ID_82598_BX 0x1508 8869b5a878SDan McDonald #define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6 8969b5a878SDan McDonald #define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7 9069b5a878SDan McDonald #define IXGBE_DEV_ID_82598AT 0x10C8 9169b5a878SDan McDonald #define IXGBE_DEV_ID_82598AT2 0x150B 9269b5a878SDan McDonald #define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB 9369b5a878SDan McDonald #define IXGBE_DEV_ID_82598EB_CX4 0x10DD 9469b5a878SDan McDonald #define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC 9569b5a878SDan McDonald #define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1 9669b5a878SDan McDonald #define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1 9769b5a878SDan McDonald #define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4 9869b5a878SDan McDonald #define IXGBE_DEV_ID_82599_KX4 0x10F7 9969b5a878SDan McDonald #define IXGBE_DEV_ID_82599_KX4_MEZZ 0x1514 10069b5a878SDan McDonald #define IXGBE_DEV_ID_82599_KR 0x1517 10169b5a878SDan McDonald #define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8 10269b5a878SDan McDonald #define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ 0x000C 1030fa55b7aSRobert Mustacchi #define IXGBE_DEV_ID_82599_CX4 0x10F9 1040fa55b7aSRobert Mustacchi #define IXGBE_DEV_ID_82599_SFP 0x10FB 10569b5a878SDan McDonald #define IXGBE_SUBDEV_ID_82599_SFP 0x11A9 106dc0cb1cdSDale Ghent #define IXGBE_SUBDEV_ID_82599_SFP_WOL0 0x1071 107dc0cb1cdSDale Ghent #define IXGBE_SUBDEV_ID_82599_RNDC 0x1F72 10869b5a878SDan McDonald #define IXGBE_SUBDEV_ID_82599_560FLR 0x17D0 109dc0cb1cdSDale Ghent #define IXGBE_SUBDEV_ID_82599_ECNA_DP 0x0470 110dc0cb1cdSDale Ghent #define IXGBE_SUBDEV_ID_82599_SP_560FLR 0x211B 111dc0cb1cdSDale Ghent #define IXGBE_SUBDEV_ID_82599_LOM_SNAP6 0x2159 112dc0cb1cdSDale Ghent #define IXGBE_SUBDEV_ID_82599_SFP_1OCP 0x000D 113dc0cb1cdSDale Ghent #define IXGBE_SUBDEV_ID_82599_SFP_2OCP 0x0008 114*48ed61a7SRobert Mustacchi #define IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1 0x8976 115*48ed61a7SRobert Mustacchi #define IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2 0x06EE 11669b5a878SDan McDonald #define IXGBE_DEV_ID_82599_BACKPLANE_FCOE 0x152A 11769b5a878SDan McDonald #define IXGBE_DEV_ID_82599_SFP_FCOE 0x1529 1180fa55b7aSRobert Mustacchi #define IXGBE_DEV_ID_82599_SFP_EM 0x1507 11969b5a878SDan McDonald #define IXGBE_DEV_ID_82599_SFP_SF2 0x154D 120dc0cb1cdSDale Ghent #define IXGBE_DEV_ID_82599_SFP_SF_QP 0x154A 121dc0cb1cdSDale Ghent #define IXGBE_DEV_ID_82599_QSFP_SF_QP 0x1558 1220fa55b7aSRobert Mustacchi #define IXGBE_DEV_ID_82599EN_SFP 0x1557 123dc0cb1cdSDale Ghent #define IXGBE_SUBDEV_ID_82599EN_SFP_OCP1 0x0001 12469b5a878SDan McDonald #define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC 12569b5a878SDan McDonald #define IXGBE_DEV_ID_82599_T3_LOM 0x151C 12669b5a878SDan McDonald #define IXGBE_DEV_ID_82599_VF 0x10ED 127dc0cb1cdSDale Ghent #define IXGBE_DEV_ID_82599_VF_HV 0x152E 128dc0cb1cdSDale Ghent #define IXGBE_DEV_ID_82599_BYPASS 0x155D 12969b5a878SDan McDonald #define IXGBE_DEV_ID_X540T 0x1528 130dc0cb1cdSDale Ghent #define IXGBE_DEV_ID_X540_VF 0x1515 131dc0cb1cdSDale Ghent #define IXGBE_DEV_ID_X540_VF_HV 0x1530 132dc0cb1cdSDale Ghent #define IXGBE_DEV_ID_X540_BYPASS 0x155C 13369b5a878SDan McDonald #define IXGBE_DEV_ID_X540T1 0x1560 134dc0cb1cdSDale Ghent #define IXGBE_DEV_ID_X550T 0x1563 135dc0cb1cdSDale Ghent #define IXGBE_DEV_ID_X550T1 0x15D1 136*48ed61a7SRobert Mustacchi #define IXGBE_DEV_ID_X550EM_A_KR 0x15C2 137*48ed61a7SRobert Mustacchi #define IXGBE_DEV_ID_X550EM_A_KR_L 0x15C3 138*48ed61a7SRobert Mustacchi #define IXGBE_DEV_ID_X550EM_A_SFP_N 0x15C4 139*48ed61a7SRobert Mustacchi #define IXGBE_DEV_ID_X550EM_A_SGMII 0x15C6 140*48ed61a7SRobert Mustacchi #define IXGBE_DEV_ID_X550EM_A_SGMII_L 0x15C7 141*48ed61a7SRobert Mustacchi #define IXGBE_DEV_ID_X550EM_A_10G_T 0x15C8 142*48ed61a7SRobert Mustacchi #define IXGBE_DEV_ID_X550EM_A_QSFP 0x15CA 143*48ed61a7SRobert Mustacchi #define IXGBE_DEV_ID_X550EM_A_QSFP_N 0x15CC 144*48ed61a7SRobert Mustacchi #define IXGBE_DEV_ID_X550EM_A_SFP 0x15CE 145*48ed61a7SRobert Mustacchi #define IXGBE_DEV_ID_X550EM_A_1G_T 0x15E4 146*48ed61a7SRobert Mustacchi #define IXGBE_DEV_ID_X550EM_A_1G_T_L 0x15E5 147dc0cb1cdSDale Ghent #define IXGBE_DEV_ID_X550EM_X_KX4 0x15AA 148dc0cb1cdSDale Ghent #define IXGBE_DEV_ID_X550EM_X_KR 0x15AB 149dc0cb1cdSDale Ghent #define IXGBE_DEV_ID_X550EM_X_SFP 0x15AC 150dc0cb1cdSDale Ghent #define IXGBE_DEV_ID_X550EM_X_10G_T 0x15AD 151dc0cb1cdSDale Ghent #define IXGBE_DEV_ID_X550EM_X_1G_T 0x15AE 152*48ed61a7SRobert Mustacchi #define IXGBE_DEV_ID_X550EM_X_XFI 0x15B0 153dc0cb1cdSDale Ghent #define IXGBE_DEV_ID_X550_VF_HV 0x1564 154dc0cb1cdSDale Ghent #define IXGBE_DEV_ID_X550_VF 0x1565 155*48ed61a7SRobert Mustacchi #define IXGBE_DEV_ID_X550EM_A_VF 0x15C5 156*48ed61a7SRobert Mustacchi #define IXGBE_DEV_ID_X550EM_A_VF_HV 0x15B4 157dc0cb1cdSDale Ghent #define IXGBE_DEV_ID_X550EM_X_VF 0x15A8 158dc0cb1cdSDale Ghent #define IXGBE_DEV_ID_X550EM_X_VF_HV 0x15A9 159dc0cb1cdSDale Ghent 160dc0cb1cdSDale Ghent #define IXGBE_CAT(r,m) IXGBE_##r##m 161dc0cb1cdSDale Ghent 162dc0cb1cdSDale Ghent #define IXGBE_BY_MAC(_hw, r) ((_hw)->mvals[IXGBE_CAT(r, _IDX)]) 1639da57d7bSbt 1649da57d7bSbt /* General Registers */ 16569b5a878SDan McDonald #define IXGBE_CTRL 0x00000 16669b5a878SDan McDonald #define IXGBE_STATUS 0x00008 16769b5a878SDan McDonald #define IXGBE_CTRL_EXT 0x00018 16869b5a878SDan McDonald #define IXGBE_ESDP 0x00020 16969b5a878SDan McDonald #define IXGBE_EODSDP 0x00028 170dc0cb1cdSDale Ghent #define IXGBE_I2CCTL_82599 0x00028 171dc0cb1cdSDale Ghent #define IXGBE_I2CCTL IXGBE_I2CCTL_82599 172dc0cb1cdSDale Ghent #define IXGBE_I2CCTL_X540 IXGBE_I2CCTL_82599 173dc0cb1cdSDale Ghent #define IXGBE_I2CCTL_X550 0x15F5C 174dc0cb1cdSDale Ghent #define IXGBE_I2CCTL_X550EM_x IXGBE_I2CCTL_X550 175*48ed61a7SRobert Mustacchi #define IXGBE_I2CCTL_X550EM_a IXGBE_I2CCTL_X550 176dc0cb1cdSDale Ghent #define IXGBE_I2CCTL_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2CCTL) 17769b5a878SDan McDonald #define IXGBE_PHY_GPIO 0x00028 17869b5a878SDan McDonald #define IXGBE_MAC_GPIO 0x00030 17969b5a878SDan McDonald #define IXGBE_PHYINT_STATUS0 0x00100 18069b5a878SDan McDonald #define IXGBE_PHYINT_STATUS1 0x00104 18169b5a878SDan McDonald #define IXGBE_PHYINT_STATUS2 0x00108 18269b5a878SDan McDonald #define IXGBE_LEDCTL 0x00200 18369b5a878SDan McDonald #define IXGBE_FRTIMER 0x00048 18469b5a878SDan McDonald #define IXGBE_TCPTIMER 0x0004C 18569b5a878SDan McDonald #define IXGBE_CORESPARE 0x00600 18669b5a878SDan McDonald #define IXGBE_EXVET 0x05078 1879da57d7bSbt 1889da57d7bSbt /* NVM Registers */ 189dc0cb1cdSDale Ghent #define IXGBE_EEC 0x10010 190dc0cb1cdSDale Ghent #define IXGBE_EEC_X540 IXGBE_EEC 191dc0cb1cdSDale Ghent #define IXGBE_EEC_X550 IXGBE_EEC 192dc0cb1cdSDale Ghent #define IXGBE_EEC_X550EM_x IXGBE_EEC 193*48ed61a7SRobert Mustacchi #define IXGBE_EEC_X550EM_a 0x15FF8 194*48ed61a7SRobert Mustacchi #define IXGBE_EEC_BY_MAC(_hw) IXGBE_BY_MAC((_hw), EEC) 195dc0cb1cdSDale Ghent 196dc0cb1cdSDale Ghent #define IXGBE_EERD 0x10014 197dc0cb1cdSDale Ghent #define IXGBE_EEWR 0x10018 198dc0cb1cdSDale Ghent 199dc0cb1cdSDale Ghent #define IXGBE_FLA 0x1001C 200dc0cb1cdSDale Ghent #define IXGBE_FLA_X540 IXGBE_FLA 201dc0cb1cdSDale Ghent #define IXGBE_FLA_X550 IXGBE_FLA 202dc0cb1cdSDale Ghent #define IXGBE_FLA_X550EM_x IXGBE_FLA 203*48ed61a7SRobert Mustacchi #define IXGBE_FLA_X550EM_a 0x15F68 204*48ed61a7SRobert Mustacchi #define IXGBE_FLA_BY_MAC(_hw) IXGBE_BY_MAC((_hw), FLA) 205dc0cb1cdSDale Ghent 20669b5a878SDan McDonald #define IXGBE_EEMNGCTL 0x10110 20769b5a878SDan McDonald #define IXGBE_EEMNGDATA 0x10114 20869b5a878SDan McDonald #define IXGBE_FLMNGCTL 0x10118 20969b5a878SDan McDonald #define IXGBE_FLMNGDATA 0x1011C 21069b5a878SDan McDonald #define IXGBE_FLMNGCNT 0x10120 21169b5a878SDan McDonald #define IXGBE_FLOP 0x1013C 212dc0cb1cdSDale Ghent 213dc0cb1cdSDale Ghent #define IXGBE_GRC 0x10200 214dc0cb1cdSDale Ghent #define IXGBE_GRC_X540 IXGBE_GRC 215dc0cb1cdSDale Ghent #define IXGBE_GRC_X550 IXGBE_GRC 216dc0cb1cdSDale Ghent #define IXGBE_GRC_X550EM_x IXGBE_GRC 217*48ed61a7SRobert Mustacchi #define IXGBE_GRC_X550EM_a 0x15F64 218*48ed61a7SRobert Mustacchi #define IXGBE_GRC_BY_MAC(_hw) IXGBE_BY_MAC((_hw), GRC) 219dc0cb1cdSDale Ghent 220dc0cb1cdSDale Ghent #define IXGBE_SRAMREL 0x10210 221dc0cb1cdSDale Ghent #define IXGBE_SRAMREL_X540 IXGBE_SRAMREL 222dc0cb1cdSDale Ghent #define IXGBE_SRAMREL_X550 IXGBE_SRAMREL 223dc0cb1cdSDale Ghent #define IXGBE_SRAMREL_X550EM_x IXGBE_SRAMREL 224*48ed61a7SRobert Mustacchi #define IXGBE_SRAMREL_X550EM_a 0x15F6C 225*48ed61a7SRobert Mustacchi #define IXGBE_SRAMREL_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SRAMREL) 226dc0cb1cdSDale Ghent 22769b5a878SDan McDonald #define IXGBE_PHYDBG 0x10218 2289da57d7bSbt 22973cd555cSBin Tu - Sun Microsystems - Beijing China /* General Receive Control */ 23069b5a878SDan McDonald #define IXGBE_GRC_MNG 0x00000001 /* Manageability Enable */ 23169b5a878SDan McDonald #define IXGBE_GRC_APME 0x00000002 /* APM enabled in EEPROM */ 23273cd555cSBin Tu - Sun Microsystems - Beijing China 23369b5a878SDan McDonald #define IXGBE_VPDDIAG0 0x10204 23469b5a878SDan McDonald #define IXGBE_VPDDIAG1 0x10208 23573cd555cSBin Tu - Sun Microsystems - Beijing China 23673cd555cSBin Tu - Sun Microsystems - Beijing China /* I2CCTL Bit Masks */ 237dc0cb1cdSDale Ghent #define IXGBE_I2C_CLK_IN 0x00000001 238dc0cb1cdSDale Ghent #define IXGBE_I2C_CLK_IN_X540 IXGBE_I2C_CLK_IN 239dc0cb1cdSDale Ghent #define IXGBE_I2C_CLK_IN_X550 0x00004000 240dc0cb1cdSDale Ghent #define IXGBE_I2C_CLK_IN_X550EM_x IXGBE_I2C_CLK_IN_X550 241*48ed61a7SRobert Mustacchi #define IXGBE_I2C_CLK_IN_X550EM_a IXGBE_I2C_CLK_IN_X550 242dc0cb1cdSDale Ghent #define IXGBE_I2C_CLK_IN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_IN) 243dc0cb1cdSDale Ghent 244dc0cb1cdSDale Ghent #define IXGBE_I2C_CLK_OUT 0x00000002 245dc0cb1cdSDale Ghent #define IXGBE_I2C_CLK_OUT_X540 IXGBE_I2C_CLK_OUT 246dc0cb1cdSDale Ghent #define IXGBE_I2C_CLK_OUT_X550 0x00000200 247dc0cb1cdSDale Ghent #define IXGBE_I2C_CLK_OUT_X550EM_x IXGBE_I2C_CLK_OUT_X550 248*48ed61a7SRobert Mustacchi #define IXGBE_I2C_CLK_OUT_X550EM_a IXGBE_I2C_CLK_OUT_X550 249dc0cb1cdSDale Ghent #define IXGBE_I2C_CLK_OUT_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_OUT) 250dc0cb1cdSDale Ghent 251dc0cb1cdSDale Ghent #define IXGBE_I2C_DATA_IN 0x00000004 252dc0cb1cdSDale Ghent #define IXGBE_I2C_DATA_IN_X540 IXGBE_I2C_DATA_IN 253dc0cb1cdSDale Ghent #define IXGBE_I2C_DATA_IN_X550 0x00001000 254dc0cb1cdSDale Ghent #define IXGBE_I2C_DATA_IN_X550EM_x IXGBE_I2C_DATA_IN_X550 255*48ed61a7SRobert Mustacchi #define IXGBE_I2C_DATA_IN_X550EM_a IXGBE_I2C_DATA_IN_X550 256dc0cb1cdSDale Ghent #define IXGBE_I2C_DATA_IN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_IN) 257dc0cb1cdSDale Ghent 258dc0cb1cdSDale Ghent #define IXGBE_I2C_DATA_OUT 0x00000008 259dc0cb1cdSDale Ghent #define IXGBE_I2C_DATA_OUT_X540 IXGBE_I2C_DATA_OUT 260dc0cb1cdSDale Ghent #define IXGBE_I2C_DATA_OUT_X550 0x00000400 261dc0cb1cdSDale Ghent #define IXGBE_I2C_DATA_OUT_X550EM_x IXGBE_I2C_DATA_OUT_X550 262*48ed61a7SRobert Mustacchi #define IXGBE_I2C_DATA_OUT_X550EM_a IXGBE_I2C_DATA_OUT_X550 263dc0cb1cdSDale Ghent #define IXGBE_I2C_DATA_OUT_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_OUT) 264dc0cb1cdSDale Ghent 265dc0cb1cdSDale Ghent #define IXGBE_I2C_DATA_OE_N_EN 0 266dc0cb1cdSDale Ghent #define IXGBE_I2C_DATA_OE_N_EN_X540 IXGBE_I2C_DATA_OE_N_EN 267dc0cb1cdSDale Ghent #define IXGBE_I2C_DATA_OE_N_EN_X550 0x00000800 268dc0cb1cdSDale Ghent #define IXGBE_I2C_DATA_OE_N_EN_X550EM_x IXGBE_I2C_DATA_OE_N_EN_X550 269*48ed61a7SRobert Mustacchi #define IXGBE_I2C_DATA_OE_N_EN_X550EM_a IXGBE_I2C_DATA_OE_N_EN_X550 270dc0cb1cdSDale Ghent #define IXGBE_I2C_DATA_OE_N_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_OE_N_EN) 271dc0cb1cdSDale Ghent 272dc0cb1cdSDale Ghent #define IXGBE_I2C_BB_EN 0 273dc0cb1cdSDale Ghent #define IXGBE_I2C_BB_EN_X540 IXGBE_I2C_BB_EN 274dc0cb1cdSDale Ghent #define IXGBE_I2C_BB_EN_X550 0x00000100 275dc0cb1cdSDale Ghent #define IXGBE_I2C_BB_EN_X550EM_x IXGBE_I2C_BB_EN_X550 276*48ed61a7SRobert Mustacchi #define IXGBE_I2C_BB_EN_X550EM_a IXGBE_I2C_BB_EN_X550 277dc0cb1cdSDale Ghent #define IXGBE_I2C_BB_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_BB_EN) 278dc0cb1cdSDale Ghent 279dc0cb1cdSDale Ghent #define IXGBE_I2C_CLK_OE_N_EN 0 280dc0cb1cdSDale Ghent #define IXGBE_I2C_CLK_OE_N_EN_X540 IXGBE_I2C_CLK_OE_N_EN 281dc0cb1cdSDale Ghent #define IXGBE_I2C_CLK_OE_N_EN_X550 0x00002000 282dc0cb1cdSDale Ghent #define IXGBE_I2C_CLK_OE_N_EN_X550EM_x IXGBE_I2C_CLK_OE_N_EN_X550 283*48ed61a7SRobert Mustacchi #define IXGBE_I2C_CLK_OE_N_EN_X550EM_a IXGBE_I2C_CLK_OE_N_EN_X550 284dc0cb1cdSDale Ghent #define IXGBE_I2C_CLK_OE_N_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_OE_N_EN) 28569b5a878SDan McDonald #define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT 500 28669b5a878SDan McDonald 28773cd555cSBin Tu - Sun Microsystems - Beijing China 288*48ed61a7SRobert Mustacchi 289*48ed61a7SRobert Mustacchi #define NVM_OROM_OFFSET 0x17 290*48ed61a7SRobert Mustacchi #define NVM_OROM_BLK_LOW 0x83 291*48ed61a7SRobert Mustacchi #define NVM_OROM_BLK_HI 0x84 292*48ed61a7SRobert Mustacchi #define NVM_OROM_PATCH_MASK 0xFF 293*48ed61a7SRobert Mustacchi #define NVM_OROM_SHIFT 8 294*48ed61a7SRobert Mustacchi 295*48ed61a7SRobert Mustacchi #define NVM_VER_MASK 0x00FF /* version mask */ 296*48ed61a7SRobert Mustacchi #define NVM_VER_SHIFT 8 /* version bit shift */ 297*48ed61a7SRobert Mustacchi #define NVM_OEM_PROD_VER_PTR 0x1B /* OEM Product version block pointer */ 298*48ed61a7SRobert Mustacchi #define NVM_OEM_PROD_VER_CAP_OFF 0x1 /* OEM Product version format offset */ 299*48ed61a7SRobert Mustacchi #define NVM_OEM_PROD_VER_OFF_L 0x2 /* OEM Product version offset low */ 300*48ed61a7SRobert Mustacchi #define NVM_OEM_PROD_VER_OFF_H 0x3 /* OEM Product version offset high */ 301*48ed61a7SRobert Mustacchi #define NVM_OEM_PROD_VER_CAP_MASK 0xF /* OEM Product version cap mask */ 302*48ed61a7SRobert Mustacchi #define NVM_OEM_PROD_VER_MOD_LEN 0x3 /* OEM Product version module length */ 303*48ed61a7SRobert Mustacchi #define NVM_ETK_OFF_LOW 0x2D /* version low order word */ 304*48ed61a7SRobert Mustacchi #define NVM_ETK_OFF_HI 0x2E /* version high order word */ 305*48ed61a7SRobert Mustacchi #define NVM_ETK_SHIFT 16 /* high version word shift */ 306*48ed61a7SRobert Mustacchi #define NVM_VER_INVALID 0xFFFF 307*48ed61a7SRobert Mustacchi #define NVM_ETK_VALID 0x8000 308*48ed61a7SRobert Mustacchi #define NVM_INVALID_PTR 0xFFFF 309*48ed61a7SRobert Mustacchi #define NVM_VER_SIZE 32 /* version sting size */ 310*48ed61a7SRobert Mustacchi 311*48ed61a7SRobert Mustacchi struct ixgbe_nvm_version { 312*48ed61a7SRobert Mustacchi u32 etk_id; 313*48ed61a7SRobert Mustacchi u8 nvm_major; 314*48ed61a7SRobert Mustacchi u16 nvm_minor; 315*48ed61a7SRobert Mustacchi u8 nvm_id; 316*48ed61a7SRobert Mustacchi 317*48ed61a7SRobert Mustacchi bool oem_valid; 318*48ed61a7SRobert Mustacchi u8 oem_major; 319*48ed61a7SRobert Mustacchi u8 oem_minor; 320*48ed61a7SRobert Mustacchi u16 oem_release; 321*48ed61a7SRobert Mustacchi 322*48ed61a7SRobert Mustacchi bool or_valid; 323*48ed61a7SRobert Mustacchi u8 or_major; 324*48ed61a7SRobert Mustacchi u16 or_build; 325*48ed61a7SRobert Mustacchi u8 or_patch; 326*48ed61a7SRobert Mustacchi 327*48ed61a7SRobert Mustacchi }; 328*48ed61a7SRobert Mustacchi 3299da57d7bSbt /* Interrupt Registers */ 33069b5a878SDan McDonald #define IXGBE_EICR 0x00800 33169b5a878SDan McDonald #define IXGBE_EICS 0x00808 33269b5a878SDan McDonald #define IXGBE_EIMS 0x00880 33369b5a878SDan McDonald #define IXGBE_EIMC 0x00888 33469b5a878SDan McDonald #define IXGBE_EIAC 0x00810 33569b5a878SDan McDonald #define IXGBE_EIAM 0x00890 33669b5a878SDan McDonald #define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4) 33769b5a878SDan McDonald #define IXGBE_EIMS_EX(_i) (0x00AA0 + (_i) * 4) 33869b5a878SDan McDonald #define IXGBE_EIMC_EX(_i) (0x00AB0 + (_i) * 4) 33969b5a878SDan McDonald #define IXGBE_EIAM_EX(_i) (0x00AD0 + (_i) * 4) 34073cd555cSBin Tu - Sun Microsystems - Beijing China /* 82599 EITR is only 12 bits, with the lower 3 always zero */ 34173cd555cSBin Tu - Sun Microsystems - Beijing China /* 34273cd555cSBin Tu - Sun Microsystems - Beijing China * 82598 EITR is 16 bits but set the limits based on the max 34373cd555cSBin Tu - Sun Microsystems - Beijing China * supported by all ixgbe hardware 34473cd555cSBin Tu - Sun Microsystems - Beijing China */ 34569b5a878SDan McDonald #define IXGBE_MAX_INT_RATE 488281 34669b5a878SDan McDonald #define IXGBE_MIN_INT_RATE 956 34769b5a878SDan McDonald #define IXGBE_MAX_EITR 0x00000FF8 34869b5a878SDan McDonald #define IXGBE_MIN_EITR 8 34969b5a878SDan McDonald #define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \ 35069b5a878SDan McDonald (0x012300 + (((_i) - 24) * 4))) 35169b5a878SDan McDonald #define IXGBE_EITR_ITR_INT_MASK 0x00000FF8 35269b5a878SDan McDonald #define IXGBE_EITR_LLI_MOD 0x00008000 35369b5a878SDan McDonald #define IXGBE_EITR_CNT_WDIS 0x80000000 35469b5a878SDan McDonald #define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */ 35569b5a878SDan McDonald #define IXGBE_IVAR_MISC 0x00A00 /* misc MSI-X interrupt causes */ 35669b5a878SDan McDonald #define IXGBE_EITRSEL 0x00894 35769b5a878SDan McDonald #define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */ 35869b5a878SDan McDonald #define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */ 35969b5a878SDan McDonald #define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4))) 36069b5a878SDan McDonald #define IXGBE_GPIE 0x00898 3619da57d7bSbt 3629da57d7bSbt /* Flow Control Registers */ 36369b5a878SDan McDonald #define IXGBE_FCADBUL 0x03210 36469b5a878SDan McDonald #define IXGBE_FCADBUH 0x03214 36569b5a878SDan McDonald #define IXGBE_FCAMACL 0x04328 36669b5a878SDan McDonald #define IXGBE_FCAMACH 0x0432C 36769b5a878SDan McDonald #define IXGBE_FCRTH_82599(_i) (0x03260 + ((_i) * 4)) /* 8 of these (0-7) */ 36869b5a878SDan McDonald #define IXGBE_FCRTL_82599(_i) (0x03220 + ((_i) * 4)) /* 8 of these (0-7) */ 36969b5a878SDan McDonald #define IXGBE_PFCTOP 0x03008 37069b5a878SDan McDonald #define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */ 37169b5a878SDan McDonald #define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */ 37269b5a878SDan McDonald #define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */ 37369b5a878SDan McDonald #define IXGBE_FCRTV 0x032A0 37469b5a878SDan McDonald #define IXGBE_FCCFG 0x03D00 37569b5a878SDan McDonald #define IXGBE_TFCS 0x0CE00 3769da57d7bSbt 3779da57d7bSbt /* Receive DMA Registers */ 37869b5a878SDan McDonald #define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \ 37969b5a878SDan McDonald (0x0D000 + (((_i) - 64) * 0x40))) 38069b5a878SDan McDonald #define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \ 38169b5a878SDan McDonald (0x0D004 + (((_i) - 64) * 0x40))) 38269b5a878SDan McDonald #define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \ 38369b5a878SDan McDonald (0x0D008 + (((_i) - 64) * 0x40))) 38469b5a878SDan McDonald #define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \ 38569b5a878SDan McDonald (0x0D010 + (((_i) - 64) * 0x40))) 38669b5a878SDan McDonald #define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \ 38769b5a878SDan McDonald (0x0D018 + (((_i) - 64) * 0x40))) 38869b5a878SDan McDonald #define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \ 38969b5a878SDan McDonald (0x0D028 + (((_i) - 64) * 0x40))) 39069b5a878SDan McDonald #define IXGBE_RSCCTL(_i) (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \ 39169b5a878SDan McDonald (0x0D02C + (((_i) - 64) * 0x40))) 39269b5a878SDan McDonald #define IXGBE_RSCDBU 0x03028 39369b5a878SDan McDonald #define IXGBE_RDDCC 0x02F20 39469b5a878SDan McDonald #define IXGBE_RXMEMWRAP 0x03190 39569b5a878SDan McDonald #define IXGBE_STARCTRL 0x03024 3969da57d7bSbt /* 3979da57d7bSbt * Split and Replication Receive Control Registers 3989da57d7bSbt * 00-15 : 0x02100 + n*4 3999da57d7bSbt * 16-64 : 0x01014 + n*0x40 4009da57d7bSbt * 64-127: 0x0D014 + (n-64)*0x40 4019da57d7bSbt */ 40269b5a878SDan McDonald #define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \ 40369b5a878SDan McDonald (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \ 40469b5a878SDan McDonald (0x0D014 + (((_i) - 64) * 0x40)))) 4059da57d7bSbt /* 4069da57d7bSbt * Rx DCA Control Register: 4079da57d7bSbt * 00-15 : 0x02200 + n*4 4089da57d7bSbt * 16-64 : 0x0100C + n*0x40 4099da57d7bSbt * 64-127: 0x0D00C + (n-64)*0x40 4109da57d7bSbt */ 41169b5a878SDan McDonald #define IXGBE_DCA_RXCTRL(_i) (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \ 41269b5a878SDan McDonald (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \ 41369b5a878SDan McDonald (0x0D00C + (((_i) - 64) * 0x40)))) 41469b5a878SDan McDonald #define IXGBE_RDRXCTL 0x02F00 41569b5a878SDan McDonald /* 8 of these 0x03C00 - 0x03C1C */ 41669b5a878SDan McDonald #define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4)) 41769b5a878SDan McDonald #define IXGBE_RXCTRL 0x03000 41869b5a878SDan McDonald #define IXGBE_DROPEN 0x03D04 41969b5a878SDan McDonald #define IXGBE_RXPBSIZE_SHIFT 10 420dc0cb1cdSDale Ghent #define IXGBE_RXPBSIZE_MASK 0x000FFC00 4219da57d7bSbt 4229da57d7bSbt /* Receive Registers */ 42369b5a878SDan McDonald #define IXGBE_RXCSUM 0x05000 42469b5a878SDan McDonald #define IXGBE_RFCTL 0x05008 42569b5a878SDan McDonald #define IXGBE_DRECCCTL 0x02F08 42669b5a878SDan McDonald #define IXGBE_DRECCCTL_DISABLE 0 42769b5a878SDan McDonald #define IXGBE_DRECCCTL2 0x02F8C 42863b3bba8SJerry Jelinek 4299da57d7bSbt /* Multicast Table Array - 128 entries */ 43069b5a878SDan McDonald #define IXGBE_MTA(_i) (0x05200 + ((_i) * 4)) 43169b5a878SDan McDonald #define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \ 43269b5a878SDan McDonald (0x0A200 + ((_i) * 8))) 43369b5a878SDan McDonald #define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \ 43469b5a878SDan McDonald (0x0A204 + ((_i) * 8))) 43569b5a878SDan McDonald #define IXGBE_MPSAR_LO(_i) (0x0A600 + ((_i) * 8)) 43669b5a878SDan McDonald #define IXGBE_MPSAR_HI(_i) (0x0A604 + ((_i) * 8)) 4379da57d7bSbt /* Packet split receive type */ 43869b5a878SDan McDonald #define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \ 43969b5a878SDan McDonald (0x0EA00 + ((_i) * 4))) 4409da57d7bSbt /* array of 4096 1-bit vlan filters */ 44169b5a878SDan McDonald #define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4)) 44263b3bba8SJerry Jelinek /*array of 4096 4-bit vlan vmdq indices */ 44369b5a878SDan McDonald #define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4)) 44469b5a878SDan McDonald #define IXGBE_FCTRL 0x05080 44569b5a878SDan McDonald #define IXGBE_VLNCTRL 0x05088 44669b5a878SDan McDonald #define IXGBE_MCSTCTRL 0x05090 44769b5a878SDan McDonald #define IXGBE_MRQC 0x05818 44869b5a878SDan McDonald #define IXGBE_SAQF(_i) (0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */ 44969b5a878SDan McDonald #define IXGBE_DAQF(_i) (0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */ 45069b5a878SDan McDonald #define IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */ 45169b5a878SDan McDonald #define IXGBE_FTQF(_i) (0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */ 45269b5a878SDan McDonald #define IXGBE_ETQF(_i) (0x05128 + ((_i) * 4)) /* EType Queue Filter */ 45369b5a878SDan McDonald #define IXGBE_ETQS(_i) (0x0EC00 + ((_i) * 4)) /* EType Queue Select */ 45469b5a878SDan McDonald #define IXGBE_SYNQF 0x0EC30 /* SYN Packet Queue Filter */ 45569b5a878SDan McDonald #define IXGBE_RQTC 0x0EC70 45669b5a878SDan McDonald #define IXGBE_MTQC 0x08120 45769b5a878SDan McDonald #define IXGBE_VLVF(_i) (0x0F100 + ((_i) * 4)) /* 64 of these (0-63) */ 45869b5a878SDan McDonald #define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4)) /* 128 of these (0-127) */ 45969b5a878SDan McDonald #define IXGBE_VMVIR(_i) (0x08000 + ((_i) * 4)) /* 64 of these (0-63) */ 460dc0cb1cdSDale Ghent #define IXGBE_PFFLPL 0x050B0 461dc0cb1cdSDale Ghent #define IXGBE_PFFLPH 0x050B4 46269b5a878SDan McDonald #define IXGBE_VT_CTL 0x051B0 46369b5a878SDan McDonald #define IXGBE_PFMAILBOX(_i) (0x04B00 + (4 * (_i))) /* 64 total */ 46469b5a878SDan McDonald /* 64 Mailboxes, 16 DW each */ 46569b5a878SDan McDonald #define IXGBE_PFMBMEM(_i) (0x13000 + (64 * (_i))) 46669b5a878SDan McDonald #define IXGBE_PFMBICR(_i) (0x00710 + (4 * (_i))) /* 4 total */ 46769b5a878SDan McDonald #define IXGBE_PFMBIMR(_i) (0x00720 + (4 * (_i))) /* 4 total */ 46869b5a878SDan McDonald #define IXGBE_VFRE(_i) (0x051E0 + ((_i) * 4)) 46969b5a878SDan McDonald #define IXGBE_VFTE(_i) (0x08110 + ((_i) * 4)) 47069b5a878SDan McDonald #define IXGBE_VMECM(_i) (0x08790 + ((_i) * 4)) 47169b5a878SDan McDonald #define IXGBE_QDE 0x2F04 47269b5a878SDan McDonald #define IXGBE_VMTXSW(_i) (0x05180 + ((_i) * 4)) /* 2 total */ 47369b5a878SDan McDonald #define IXGBE_VMOLR(_i) (0x0F000 + ((_i) * 4)) /* 64 total */ 47469b5a878SDan McDonald #define IXGBE_UTA(_i) (0x0F400 + ((_i) * 4)) 47569b5a878SDan McDonald #define IXGBE_MRCTL(_i) (0x0F600 + ((_i) * 4)) 47669b5a878SDan McDonald #define IXGBE_VMRVLAN(_i) (0x0F610 + ((_i) * 4)) 47769b5a878SDan McDonald #define IXGBE_VMRVM(_i) (0x0F630 + ((_i) * 4)) 478dc0cb1cdSDale Ghent #define IXGBE_LVMMC_RX 0x2FA8 479dc0cb1cdSDale Ghent #define IXGBE_LVMMC_TX 0x8108 480dc0cb1cdSDale Ghent #define IXGBE_LMVM_RX 0x2FA4 481dc0cb1cdSDale Ghent #define IXGBE_LMVM_TX 0x8124 482dc0cb1cdSDale Ghent #define IXGBE_WQBR_RX(_i) (0x2FB0 + ((_i) * 4)) /* 4 total */ 483dc0cb1cdSDale Ghent #define IXGBE_WQBR_TX(_i) (0x8130 + ((_i) * 4)) /* 4 total */ 48469b5a878SDan McDonald #define IXGBE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/ 48569b5a878SDan McDonald #define IXGBE_RXFECCERR0 0x051B8 48669b5a878SDan McDonald #define IXGBE_LLITHRESH 0x0EC90 48769b5a878SDan McDonald #define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */ 48869b5a878SDan McDonald #define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */ 48969b5a878SDan McDonald #define IXGBE_IMIRVP 0x05AC0 49069b5a878SDan McDonald #define IXGBE_VMD_CTL 0x0581C 49169b5a878SDan McDonald #define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */ 492dc0cb1cdSDale Ghent #define IXGBE_ERETA(_i) (0x0EE80 + ((_i) * 4)) /* 96 of these (0-95) */ 49369b5a878SDan McDonald #define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */ 4949da57d7bSbt 495dc0cb1cdSDale Ghent /* Registers for setting up RSS on X550 with SRIOV 496dc0cb1cdSDale Ghent * _p - pool number (0..63) 497dc0cb1cdSDale Ghent * _i - index (0..10 for PFVFRSSRK, 0..15 for PFVFRETA) 498dc0cb1cdSDale Ghent */ 499dc0cb1cdSDale Ghent #define IXGBE_PFVFMRQC(_p) (0x03400 + ((_p) * 4)) 500dc0cb1cdSDale Ghent #define IXGBE_PFVFRSSRK(_i, _p) (0x018000 + ((_i) * 4) + ((_p) * 0x40)) 501dc0cb1cdSDale Ghent #define IXGBE_PFVFRETA(_i, _p) (0x019000 + ((_i) * 4) + ((_p) * 0x40)) 502dc0cb1cdSDale Ghent 50373cd555cSBin Tu - Sun Microsystems - Beijing China /* Flow Director registers */ 50469b5a878SDan McDonald #define IXGBE_FDIRCTRL 0x0EE00 50569b5a878SDan McDonald #define IXGBE_FDIRHKEY 0x0EE68 50669b5a878SDan McDonald #define IXGBE_FDIRSKEY 0x0EE6C 50769b5a878SDan McDonald #define IXGBE_FDIRDIP4M 0x0EE3C 50869b5a878SDan McDonald #define IXGBE_FDIRSIP4M 0x0EE40 50969b5a878SDan McDonald #define IXGBE_FDIRTCPM 0x0EE44 51069b5a878SDan McDonald #define IXGBE_FDIRUDPM 0x0EE48 511dc0cb1cdSDale Ghent #define IXGBE_FDIRSCTPM 0x0EE78 51269b5a878SDan McDonald #define IXGBE_FDIRIP6M 0x0EE74 51369b5a878SDan McDonald #define IXGBE_FDIRM 0x0EE70 51473cd555cSBin Tu - Sun Microsystems - Beijing China 51573cd555cSBin Tu - Sun Microsystems - Beijing China /* Flow Director Stats registers */ 51669b5a878SDan McDonald #define IXGBE_FDIRFREE 0x0EE38 51769b5a878SDan McDonald #define IXGBE_FDIRLEN 0x0EE4C 51869b5a878SDan McDonald #define IXGBE_FDIRUSTAT 0x0EE50 51969b5a878SDan McDonald #define IXGBE_FDIRFSTAT 0x0EE54 52069b5a878SDan McDonald #define IXGBE_FDIRMATCH 0x0EE58 52169b5a878SDan McDonald #define IXGBE_FDIRMISS 0x0EE5C 52273cd555cSBin Tu - Sun Microsystems - Beijing China 52373cd555cSBin Tu - Sun Microsystems - Beijing China /* Flow Director Programming registers */ 52463b3bba8SJerry Jelinek #define IXGBE_FDIRSIPv6(_i) (0x0EE0C + ((_i) * 4)) /* 3 of these (0-2) */ 52569b5a878SDan McDonald #define IXGBE_FDIRIPSA 0x0EE18 52669b5a878SDan McDonald #define IXGBE_FDIRIPDA 0x0EE1C 52769b5a878SDan McDonald #define IXGBE_FDIRPORT 0x0EE20 52869b5a878SDan McDonald #define IXGBE_FDIRVLAN 0x0EE24 52969b5a878SDan McDonald #define IXGBE_FDIRHASH 0x0EE28 53069b5a878SDan McDonald #define IXGBE_FDIRCMD 0x0EE2C 53173cd555cSBin Tu - Sun Microsystems - Beijing China 5329da57d7bSbt /* Transmit DMA registers */ 53369b5a878SDan McDonald #define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of them (0-31)*/ 53469b5a878SDan McDonald #define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40)) 53569b5a878SDan McDonald #define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40)) 53669b5a878SDan McDonald #define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40)) 53769b5a878SDan McDonald #define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40)) 53869b5a878SDan McDonald #define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40)) 53969b5a878SDan McDonald #define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40)) 54069b5a878SDan McDonald #define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40)) 54169b5a878SDan McDonald #define IXGBE_DTXCTL 0x07E00 54269b5a878SDan McDonald 54369b5a878SDan McDonald #define IXGBE_DMATXCTL 0x04A80 54469b5a878SDan McDonald #define IXGBE_PFVFSPOOF(_i) (0x08200 + ((_i) * 4)) /* 8 of these 0 - 7 */ 54569b5a878SDan McDonald #define IXGBE_PFDTXGSWC 0x08220 54669b5a878SDan McDonald #define IXGBE_DTXMXSZRQ 0x08100 54769b5a878SDan McDonald #define IXGBE_DTXTCPFLGL 0x04A88 54869b5a878SDan McDonald #define IXGBE_DTXTCPFLGH 0x04A8C 54969b5a878SDan McDonald #define IXGBE_LBDRPEN 0x0CA00 55069b5a878SDan McDonald #define IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */ 55169b5a878SDan McDonald 55269b5a878SDan McDonald #define IXGBE_DMATXCTL_TE 0x1 /* Transmit Enable */ 55369b5a878SDan McDonald #define IXGBE_DMATXCTL_NS 0x2 /* No Snoop LSO hdr buffer */ 55469b5a878SDan McDonald #define IXGBE_DMATXCTL_GDV 0x8 /* Global Double VLAN */ 555dc0cb1cdSDale Ghent #define IXGBE_DMATXCTL_MDP_EN 0x20 /* Bit 5 */ 556dc0cb1cdSDale Ghent #define IXGBE_DMATXCTL_MBINTEN 0x40 /* Bit 6 */ 55769b5a878SDan McDonald #define IXGBE_DMATXCTL_VT_SHIFT 16 /* VLAN EtherType */ 55869b5a878SDan McDonald 55969b5a878SDan McDonald #define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */ 56063b3bba8SJerry Jelinek 56163b3bba8SJerry Jelinek /* Anti-spoofing defines */ 56269b5a878SDan McDonald #define IXGBE_SPOOF_MACAS_MASK 0xFF 56369b5a878SDan McDonald #define IXGBE_SPOOF_VLANAS_MASK 0xFF00 56469b5a878SDan McDonald #define IXGBE_SPOOF_VLANAS_SHIFT 8 565dc0cb1cdSDale Ghent #define IXGBE_SPOOF_ETHERTYPEAS 0xFF000000 566dc0cb1cdSDale Ghent #define IXGBE_SPOOF_ETHERTYPEAS_SHIFT 16 56769b5a878SDan McDonald #define IXGBE_PFVFSPOOF_REG_COUNT 8 56869b5a878SDan McDonald /* 16 of these (0-15) */ 56969b5a878SDan McDonald #define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) 57073cd555cSBin Tu - Sun Microsystems - Beijing China /* Tx DCA Control register : 128 of these (0-127) */ 57169b5a878SDan McDonald #define IXGBE_DCA_TXCTRL_82599(_i) (0x0600C + ((_i) * 0x40)) 57269b5a878SDan McDonald #define IXGBE_TIPG 0x0CB00 57369b5a878SDan McDonald #define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4)) /* 8 of these */ 57469b5a878SDan McDonald #define IXGBE_MNGTXMAP 0x0CD10 57569b5a878SDan McDonald #define IXGBE_TIPG_FIBER_DEFAULT 3 57669b5a878SDan McDonald #define IXGBE_TXPBSIZE_SHIFT 10 5779da57d7bSbt 5789da57d7bSbt /* Wake up registers */ 57969b5a878SDan McDonald #define IXGBE_WUC 0x05800 58069b5a878SDan McDonald #define IXGBE_WUFC 0x05808 58169b5a878SDan McDonald #define IXGBE_WUS 0x05810 58269b5a878SDan McDonald #define IXGBE_IPAV 0x05838 58369b5a878SDan McDonald #define IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */ 58469b5a878SDan McDonald #define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */ 58569b5a878SDan McDonald 58669b5a878SDan McDonald #define IXGBE_WUPL 0x05900 58769b5a878SDan McDonald #define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */ 588dc0cb1cdSDale Ghent #define IXGBE_PROXYS 0x05F60 /* Proxying Status Register */ 589dc0cb1cdSDale Ghent #define IXGBE_PROXYFC 0x05F64 /* Proxying Filter Control Register */ 590dc0cb1cdSDale Ghent #define IXGBE_VXLANCTRL 0x0000507C /* Rx filter VXLAN UDPPORT Register */ 591dc0cb1cdSDale Ghent 592*48ed61a7SRobert Mustacchi /* masks for accessing VXLAN and GENEVE UDP ports */ 593*48ed61a7SRobert Mustacchi #define IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK 0x0000ffff /* VXLAN port */ 594*48ed61a7SRobert Mustacchi #define IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK 0xffff0000 /* GENEVE port */ 595*48ed61a7SRobert Mustacchi #define IXGBE_VXLANCTRL_ALL_UDPPORT_MASK 0xffffffff /* GENEVE/VXLAN */ 596*48ed61a7SRobert Mustacchi #define IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT 16 597*48ed61a7SRobert Mustacchi 598dc0cb1cdSDale Ghent #define IXGBE_FHFT(_n) (0x09000 + ((_n) * 0x100)) /* Flex host filter table */ 59969b5a878SDan McDonald /* Ext Flexible Host Filter Table */ 600dc0cb1cdSDale Ghent #define IXGBE_FHFT_EXT(_n) (0x09800 + ((_n) * 0x100)) 601dc0cb1cdSDale Ghent #define IXGBE_FHFT_EXT_X550(_n) (0x09600 + ((_n) * 0x100)) 60269b5a878SDan McDonald 603dc0cb1cdSDale Ghent /* Four Flexible Filters are supported */ 60469b5a878SDan McDonald #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4 605dc0cb1cdSDale Ghent /* Six Flexible Filters are supported */ 606dc0cb1cdSDale Ghent #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX_6 6 607dc0cb1cdSDale Ghent /* Eight Flexible Filters are supported */ 608dc0cb1cdSDale Ghent #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX_8 8 60969b5a878SDan McDonald #define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2 61073cd555cSBin Tu - Sun Microsystems - Beijing China 61173cd555cSBin Tu - Sun Microsystems - Beijing China /* Each Flexible Filter is at most 128 (0x80) bytes in length */ 61269b5a878SDan McDonald #define IXGBE_FLEXIBLE_FILTER_SIZE_MAX 128 61369b5a878SDan McDonald #define IXGBE_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */ 61469b5a878SDan McDonald #define IXGBE_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */ 61573cd555cSBin Tu - Sun Microsystems - Beijing China 61673cd555cSBin Tu - Sun Microsystems - Beijing China /* Definitions for power management and wakeup registers */ 61773cd555cSBin Tu - Sun Microsystems - Beijing China /* Wake Up Control */ 61869b5a878SDan McDonald #define IXGBE_WUC_PME_EN 0x00000002 /* PME Enable */ 61969b5a878SDan McDonald #define IXGBE_WUC_PME_STATUS 0x00000004 /* PME Status */ 62069b5a878SDan McDonald #define IXGBE_WUC_WKEN 0x00000010 /* Enable PE_WAKE_N pin assertion */ 62173cd555cSBin Tu - Sun Microsystems - Beijing China 62273cd555cSBin Tu - Sun Microsystems - Beijing China /* Wake Up Filter Control */ 62369b5a878SDan McDonald #define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 62469b5a878SDan McDonald #define IXGBE_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 62569b5a878SDan McDonald #define IXGBE_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 62669b5a878SDan McDonald #define IXGBE_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 62769b5a878SDan McDonald #define IXGBE_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 62869b5a878SDan McDonald #define IXGBE_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 62969b5a878SDan McDonald #define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ 63069b5a878SDan McDonald #define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ 63169b5a878SDan McDonald #define IXGBE_WUFC_MNG 0x00000100 /* Directed Mgmt Packet Wakeup Enable */ 63269b5a878SDan McDonald 63369b5a878SDan McDonald #define IXGBE_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */ 63469b5a878SDan McDonald #define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ 63569b5a878SDan McDonald #define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ 63669b5a878SDan McDonald #define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ 63769b5a878SDan McDonald #define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ 63869b5a878SDan McDonald #define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */ 63969b5a878SDan McDonald #define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */ 640dc0cb1cdSDale Ghent #define IXGBE_WUFC_FLX_FILTERS 0x000F0000 /* Mask for 4 flex filters */ 641dc0cb1cdSDale Ghent #define IXGBE_WUFC_FLX_FILTERS_6 0x003F0000 /* Mask for 6 flex filters */ 642dc0cb1cdSDale Ghent #define IXGBE_WUFC_FLX_FILTERS_8 0x00FF0000 /* Mask for 8 flex filters */ 643dc0cb1cdSDale Ghent #define IXGBE_WUFC_FW_RST_WK 0x80000000 /* Ena wake on FW reset assertion */ 64469b5a878SDan McDonald /* Mask for Ext. flex filters */ 64569b5a878SDan McDonald #define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000 646dc0cb1cdSDale Ghent #define IXGBE_WUFC_ALL_FILTERS 0x000F00FF /* Mask all 4 flex filters */ 647dc0cb1cdSDale Ghent #define IXGBE_WUFC_ALL_FILTERS_6 0x003F00FF /* Mask all 6 flex filters */ 648dc0cb1cdSDale Ghent #define IXGBE_WUFC_ALL_FILTERS_8 0x00FF00FF /* Mask all 8 flex filters */ 64969b5a878SDan McDonald #define IXGBE_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */ 65073cd555cSBin Tu - Sun Microsystems - Beijing China 65173cd555cSBin Tu - Sun Microsystems - Beijing China /* Wake Up Status */ 65269b5a878SDan McDonald #define IXGBE_WUS_LNKC IXGBE_WUFC_LNKC 65369b5a878SDan McDonald #define IXGBE_WUS_MAG IXGBE_WUFC_MAG 65469b5a878SDan McDonald #define IXGBE_WUS_EX IXGBE_WUFC_EX 65569b5a878SDan McDonald #define IXGBE_WUS_MC IXGBE_WUFC_MC 65669b5a878SDan McDonald #define IXGBE_WUS_BC IXGBE_WUFC_BC 65769b5a878SDan McDonald #define IXGBE_WUS_ARP IXGBE_WUFC_ARP 65869b5a878SDan McDonald #define IXGBE_WUS_IPV4 IXGBE_WUFC_IPV4 65969b5a878SDan McDonald #define IXGBE_WUS_IPV6 IXGBE_WUFC_IPV6 66069b5a878SDan McDonald #define IXGBE_WUS_MNG IXGBE_WUFC_MNG 66169b5a878SDan McDonald #define IXGBE_WUS_FLX0 IXGBE_WUFC_FLX0 66269b5a878SDan McDonald #define IXGBE_WUS_FLX1 IXGBE_WUFC_FLX1 66369b5a878SDan McDonald #define IXGBE_WUS_FLX2 IXGBE_WUFC_FLX2 66469b5a878SDan McDonald #define IXGBE_WUS_FLX3 IXGBE_WUFC_FLX3 66569b5a878SDan McDonald #define IXGBE_WUS_FLX4 IXGBE_WUFC_FLX4 66669b5a878SDan McDonald #define IXGBE_WUS_FLX5 IXGBE_WUFC_FLX5 66769b5a878SDan McDonald #define IXGBE_WUS_FLX_FILTERS IXGBE_WUFC_FLX_FILTERS 668dc0cb1cdSDale Ghent #define IXGBE_WUS_FW_RST_WK IXGBE_WUFC_FW_RST_WK 669dc0cb1cdSDale Ghent /* Proxy Status */ 670dc0cb1cdSDale Ghent #define IXGBE_PROXYS_EX 0x00000004 /* Exact packet received */ 671dc0cb1cdSDale Ghent #define IXGBE_PROXYS_ARP_DIR 0x00000020 /* ARP w/filter match received */ 672dc0cb1cdSDale Ghent #define IXGBE_PROXYS_NS 0x00000200 /* IPV6 NS received */ 673dc0cb1cdSDale Ghent #define IXGBE_PROXYS_NS_DIR 0x00000400 /* IPV6 NS w/DA match received */ 674dc0cb1cdSDale Ghent #define IXGBE_PROXYS_ARP 0x00000800 /* ARP request packet received */ 675dc0cb1cdSDale Ghent #define IXGBE_PROXYS_MLD 0x00001000 /* IPv6 MLD packet received */ 676dc0cb1cdSDale Ghent 677dc0cb1cdSDale Ghent /* Proxying Filter Control */ 678dc0cb1cdSDale Ghent #define IXGBE_PROXYFC_ENABLE 0x00000001 /* Port Proxying Enable */ 679dc0cb1cdSDale Ghent #define IXGBE_PROXYFC_EX 0x00000004 /* Directed Exact Proxy Enable */ 680dc0cb1cdSDale Ghent #define IXGBE_PROXYFC_ARP_DIR 0x00000020 /* Directed ARP Proxy Enable */ 681dc0cb1cdSDale Ghent #define IXGBE_PROXYFC_NS 0x00000200 /* IPv6 Neighbor Solicitation */ 682dc0cb1cdSDale Ghent #define IXGBE_PROXYFC_ARP 0x00000800 /* ARP Request Proxy Enable */ 683dc0cb1cdSDale Ghent #define IXGBE_PROXYFC_MLD 0x00000800 /* IPv6 MLD Proxy Enable */ 684dc0cb1cdSDale Ghent #define IXGBE_PROXYFC_NO_TCO 0x00008000 /* Ignore TCO packets */ 68573cd555cSBin Tu - Sun Microsystems - Beijing China 68669b5a878SDan McDonald #define IXGBE_WUPL_LENGTH_MASK 0xFFFF 68773cd555cSBin Tu - Sun Microsystems - Beijing China 68873cd555cSBin Tu - Sun Microsystems - Beijing China /* DCB registers */ 68969b5a878SDan McDonald #define IXGBE_DCB_MAX_TRAFFIC_CLASS 8 69069b5a878SDan McDonald #define IXGBE_RMCS 0x03D00 69169b5a878SDan McDonald #define IXGBE_DPMCS 0x07F40 69269b5a878SDan McDonald #define IXGBE_PDPMCS 0x0CD00 69369b5a878SDan McDonald #define IXGBE_RUPPBMR 0x050A0 69469b5a878SDan McDonald #define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */ 69569b5a878SDan McDonald #define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */ 69669b5a878SDan McDonald #define IXGBE_TDTQ2TCCR(_i) (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */ 69769b5a878SDan McDonald #define IXGBE_TDTQ2TCSR(_i) (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */ 69869b5a878SDan McDonald #define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */ 69969b5a878SDan McDonald #define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */ 70063b3bba8SJerry Jelinek 701dc0cb1cdSDale Ghent /* Power Management */ 702dc0cb1cdSDale Ghent /* DMA Coalescing configuration */ 703dc0cb1cdSDale Ghent struct ixgbe_dmac_config { 704dc0cb1cdSDale Ghent u16 watchdog_timer; /* usec units */ 705dc0cb1cdSDale Ghent bool fcoe_en; 706dc0cb1cdSDale Ghent u32 link_speed; 707dc0cb1cdSDale Ghent u8 fcoe_tc; 708dc0cb1cdSDale Ghent u8 num_tcs; 709dc0cb1cdSDale Ghent }; 710dc0cb1cdSDale Ghent 711dc0cb1cdSDale Ghent /* 712dc0cb1cdSDale Ghent * DMA Coalescing threshold Rx PB TC[n] value in Kilobyte by link speed. 713dc0cb1cdSDale Ghent * DMACRXT = 10Gbps = 10,000 bits / usec = 1250 bytes / usec 70 * 1250 == 714dc0cb1cdSDale Ghent * 87500 bytes [85KB] 715dc0cb1cdSDale Ghent */ 716dc0cb1cdSDale Ghent #define IXGBE_DMACRXT_10G 0x55 717dc0cb1cdSDale Ghent #define IXGBE_DMACRXT_1G 0x09 718dc0cb1cdSDale Ghent #define IXGBE_DMACRXT_100M 0x01 719dc0cb1cdSDale Ghent 720dc0cb1cdSDale Ghent /* DMA Coalescing registers */ 721dc0cb1cdSDale Ghent #define IXGBE_DMCMNGTH 0x15F20 /* Management Threshold */ 722dc0cb1cdSDale Ghent #define IXGBE_DMACR 0x02400 /* Control register */ 723dc0cb1cdSDale Ghent #define IXGBE_DMCTH(_i) (0x03300 + ((_i) * 4)) /* 8 of these */ 724dc0cb1cdSDale Ghent #define IXGBE_DMCTLX 0x02404 /* Time to Lx request */ 725dc0cb1cdSDale Ghent /* DMA Coalescing register fields */ 726dc0cb1cdSDale Ghent #define IXGBE_DMCMNGTH_DMCMNGTH_MASK 0x000FFFF0 /* Mng Threshold mask */ 727dc0cb1cdSDale Ghent #define IXGBE_DMCMNGTH_DMCMNGTH_SHIFT 4 /* Management Threshold shift */ 728dc0cb1cdSDale Ghent #define IXGBE_DMACR_DMACWT_MASK 0x0000FFFF /* Watchdog Timer mask */ 729dc0cb1cdSDale Ghent #define IXGBE_DMACR_HIGH_PRI_TC_MASK 0x00FF0000 730dc0cb1cdSDale Ghent #define IXGBE_DMACR_HIGH_PRI_TC_SHIFT 16 731dc0cb1cdSDale Ghent #define IXGBE_DMACR_EN_MNG_IND 0x10000000 /* Enable Mng Indications */ 732dc0cb1cdSDale Ghent #define IXGBE_DMACR_LX_COAL_IND 0x40000000 /* Lx Coalescing indicate */ 733dc0cb1cdSDale Ghent #define IXGBE_DMACR_DMAC_EN 0x80000000 /* DMA Coalescing Enable */ 734dc0cb1cdSDale Ghent #define IXGBE_DMCTH_DMACRXT_MASK 0x000001FF /* Receive Threshold mask */ 735dc0cb1cdSDale Ghent #define IXGBE_DMCTLX_TTLX_MASK 0x00000FFF /* Time to Lx request mask */ 736dc0cb1cdSDale Ghent 737dc0cb1cdSDale Ghent /* EEE registers */ 738dc0cb1cdSDale Ghent #define IXGBE_EEER 0x043A0 /* EEE register */ 739dc0cb1cdSDale Ghent #define IXGBE_EEE_STAT 0x04398 /* EEE Status */ 740dc0cb1cdSDale Ghent #define IXGBE_EEE_SU 0x04380 /* EEE Set up */ 741dc0cb1cdSDale Ghent #define IXGBE_EEE_SU_TEEE_DLY_SHIFT 26 742dc0cb1cdSDale Ghent #define IXGBE_TLPIC 0x041F4 /* EEE Tx LPI count */ 743dc0cb1cdSDale Ghent #define IXGBE_RLPIC 0x041F8 /* EEE Rx LPI count */ 744dc0cb1cdSDale Ghent 745dc0cb1cdSDale Ghent /* EEE register fields */ 746dc0cb1cdSDale Ghent #define IXGBE_EEER_TX_LPI_EN 0x00010000 /* Enable EEE LPI TX path */ 747dc0cb1cdSDale Ghent #define IXGBE_EEER_RX_LPI_EN 0x00020000 /* Enable EEE LPI RX path */ 748dc0cb1cdSDale Ghent #define IXGBE_EEE_STAT_NEG 0x20000000 /* EEE support neg on link */ 749dc0cb1cdSDale Ghent #define IXGBE_EEE_RX_LPI_STATUS 0x40000000 /* RX Link in LPI status */ 750dc0cb1cdSDale Ghent #define IXGBE_EEE_TX_LPI_STATUS 0x80000000 /* TX Link in LPI status */ 751dc0cb1cdSDale Ghent 75273cd555cSBin Tu - Sun Microsystems - Beijing China /* Security Control Registers */ 75369b5a878SDan McDonald #define IXGBE_SECTXCTRL 0x08800 75469b5a878SDan McDonald #define IXGBE_SECTXSTAT 0x08804 75569b5a878SDan McDonald #define IXGBE_SECTXBUFFAF 0x08808 75669b5a878SDan McDonald #define IXGBE_SECTXMINIFG 0x08810 75769b5a878SDan McDonald #define IXGBE_SECRXCTRL 0x08D00 75869b5a878SDan McDonald #define IXGBE_SECRXSTAT 0x08D04 75973cd555cSBin Tu - Sun Microsystems - Beijing China 76073cd555cSBin Tu - Sun Microsystems - Beijing China /* Security Bit Fields and Masks */ 76169b5a878SDan McDonald #define IXGBE_SECTXCTRL_SECTX_DIS 0x00000001 76269b5a878SDan McDonald #define IXGBE_SECTXCTRL_TX_DIS 0x00000002 76369b5a878SDan McDonald #define IXGBE_SECTXCTRL_STORE_FORWARD 0x00000004 76473cd555cSBin Tu - Sun Microsystems - Beijing China 76569b5a878SDan McDonald #define IXGBE_SECTXSTAT_SECTX_RDY 0x00000001 76669b5a878SDan McDonald #define IXGBE_SECTXSTAT_ECC_TXERR 0x00000002 76773cd555cSBin Tu - Sun Microsystems - Beijing China 76869b5a878SDan McDonald #define IXGBE_SECRXCTRL_SECRX_DIS 0x00000001 76969b5a878SDan McDonald #define IXGBE_SECRXCTRL_RX_DIS 0x00000002 77073cd555cSBin Tu - Sun Microsystems - Beijing China 77169b5a878SDan McDonald #define IXGBE_SECRXSTAT_SECRX_RDY 0x00000001 77269b5a878SDan McDonald #define IXGBE_SECRXSTAT_ECC_RXERR 0x00000002 77373cd555cSBin Tu - Sun Microsystems - Beijing China 77473cd555cSBin Tu - Sun Microsystems - Beijing China /* LinkSec (MacSec) Registers */ 77569b5a878SDan McDonald #define IXGBE_LSECTXCAP 0x08A00 77669b5a878SDan McDonald #define IXGBE_LSECRXCAP 0x08F00 77769b5a878SDan McDonald #define IXGBE_LSECTXCTRL 0x08A04 77869b5a878SDan McDonald #define IXGBE_LSECTXSCL 0x08A08 /* SCI Low */ 77969b5a878SDan McDonald #define IXGBE_LSECTXSCH 0x08A0C /* SCI High */ 78069b5a878SDan McDonald #define IXGBE_LSECTXSA 0x08A10 78169b5a878SDan McDonald #define IXGBE_LSECTXPN0 0x08A14 78269b5a878SDan McDonald #define IXGBE_LSECTXPN1 0x08A18 78369b5a878SDan McDonald #define IXGBE_LSECTXKEY0(_n) (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */ 78469b5a878SDan McDonald #define IXGBE_LSECTXKEY1(_n) (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */ 78569b5a878SDan McDonald #define IXGBE_LSECRXCTRL 0x08F04 78669b5a878SDan McDonald #define IXGBE_LSECRXSCL 0x08F08 78769b5a878SDan McDonald #define IXGBE_LSECRXSCH 0x08F0C 78869b5a878SDan McDonald #define IXGBE_LSECRXSA(_i) (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */ 78969b5a878SDan McDonald #define IXGBE_LSECRXPN(_i) (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */ 79069b5a878SDan McDonald #define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m)))) 79169b5a878SDan McDonald #define IXGBE_LSECTXUT 0x08A3C /* OutPktsUntagged */ 79269b5a878SDan McDonald #define IXGBE_LSECTXPKTE 0x08A40 /* OutPktsEncrypted */ 79369b5a878SDan McDonald #define IXGBE_LSECTXPKTP 0x08A44 /* OutPktsProtected */ 79469b5a878SDan McDonald #define IXGBE_LSECTXOCTE 0x08A48 /* OutOctetsEncrypted */ 79569b5a878SDan McDonald #define IXGBE_LSECTXOCTP 0x08A4C /* OutOctetsProtected */ 79669b5a878SDan McDonald #define IXGBE_LSECRXUT 0x08F40 /* InPktsUntagged/InPktsNoTag */ 79769b5a878SDan McDonald #define IXGBE_LSECRXOCTD 0x08F44 /* InOctetsDecrypted */ 79869b5a878SDan McDonald #define IXGBE_LSECRXOCTV 0x08F48 /* InOctetsValidated */ 79969b5a878SDan McDonald #define IXGBE_LSECRXBAD 0x08F4C /* InPktsBadTag */ 80069b5a878SDan McDonald #define IXGBE_LSECRXNOSCI 0x08F50 /* InPktsNoSci */ 80169b5a878SDan McDonald #define IXGBE_LSECRXUNSCI 0x08F54 /* InPktsUnknownSci */ 80269b5a878SDan McDonald #define IXGBE_LSECRXUNCH 0x08F58 /* InPktsUnchecked */ 80369b5a878SDan McDonald #define IXGBE_LSECRXDELAY 0x08F5C /* InPktsDelayed */ 80469b5a878SDan McDonald #define IXGBE_LSECRXLATE 0x08F60 /* InPktsLate */ 80569b5a878SDan McDonald #define IXGBE_LSECRXOK(_n) (0x08F64 + (0x04 * (_n))) /* InPktsOk */ 80669b5a878SDan McDonald #define IXGBE_LSECRXINV(_n) (0x08F6C + (0x04 * (_n))) /* InPktsInvalid */ 80769b5a878SDan McDonald #define IXGBE_LSECRXNV(_n) (0x08F74 + (0x04 * (_n))) /* InPktsNotValid */ 80869b5a878SDan McDonald #define IXGBE_LSECRXUNSA 0x08F7C /* InPktsUnusedSa */ 80969b5a878SDan McDonald #define IXGBE_LSECRXNUSA 0x08F80 /* InPktsNotUsingSa */ 81073cd555cSBin Tu - Sun Microsystems - Beijing China 81173cd555cSBin Tu - Sun Microsystems - Beijing China /* LinkSec (MacSec) Bit Fields and Masks */ 81269b5a878SDan McDonald #define IXGBE_LSECTXCAP_SUM_MASK 0x00FF0000 81369b5a878SDan McDonald #define IXGBE_LSECTXCAP_SUM_SHIFT 16 81469b5a878SDan McDonald #define IXGBE_LSECRXCAP_SUM_MASK 0x00FF0000 81569b5a878SDan McDonald #define IXGBE_LSECRXCAP_SUM_SHIFT 16 81669b5a878SDan McDonald 81769b5a878SDan McDonald #define IXGBE_LSECTXCTRL_EN_MASK 0x00000003 81869b5a878SDan McDonald #define IXGBE_LSECTXCTRL_DISABLE 0x0 81969b5a878SDan McDonald #define IXGBE_LSECTXCTRL_AUTH 0x1 82069b5a878SDan McDonald #define IXGBE_LSECTXCTRL_AUTH_ENCRYPT 0x2 82169b5a878SDan McDonald #define IXGBE_LSECTXCTRL_AISCI 0x00000020 82269b5a878SDan McDonald #define IXGBE_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00 82369b5a878SDan McDonald #define IXGBE_LSECTXCTRL_RSV_MASK 0x000000D8 82469b5a878SDan McDonald 82569b5a878SDan McDonald #define IXGBE_LSECRXCTRL_EN_MASK 0x0000000C 82669b5a878SDan McDonald #define IXGBE_LSECRXCTRL_EN_SHIFT 2 82769b5a878SDan McDonald #define IXGBE_LSECRXCTRL_DISABLE 0x0 82869b5a878SDan McDonald #define IXGBE_LSECRXCTRL_CHECK 0x1 82969b5a878SDan McDonald #define IXGBE_LSECRXCTRL_STRICT 0x2 83069b5a878SDan McDonald #define IXGBE_LSECRXCTRL_DROP 0x3 83169b5a878SDan McDonald #define IXGBE_LSECRXCTRL_PLSH 0x00000040 83269b5a878SDan McDonald #define IXGBE_LSECRXCTRL_RP 0x00000080 83369b5a878SDan McDonald #define IXGBE_LSECRXCTRL_RSV_MASK 0xFFFFFF33 83473cd555cSBin Tu - Sun Microsystems - Beijing China 83573cd555cSBin Tu - Sun Microsystems - Beijing China /* IpSec Registers */ 83669b5a878SDan McDonald #define IXGBE_IPSTXIDX 0x08900 83769b5a878SDan McDonald #define IXGBE_IPSTXSALT 0x08904 83869b5a878SDan McDonald #define IXGBE_IPSTXKEY(_i) (0x08908 + (4 * (_i))) /* 4 of these (0-3) */ 83969b5a878SDan McDonald #define IXGBE_IPSRXIDX 0x08E00 84069b5a878SDan McDonald #define IXGBE_IPSRXIPADDR(_i) (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */ 84169b5a878SDan McDonald #define IXGBE_IPSRXSPI 0x08E14 84269b5a878SDan McDonald #define IXGBE_IPSRXIPIDX 0x08E18 84369b5a878SDan McDonald #define IXGBE_IPSRXKEY(_i) (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */ 84469b5a878SDan McDonald #define IXGBE_IPSRXSALT 0x08E2C 84569b5a878SDan McDonald #define IXGBE_IPSRXMOD 0x08E30 84669b5a878SDan McDonald 84769b5a878SDan McDonald #define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE 0x4 84873cd555cSBin Tu - Sun Microsystems - Beijing China 84973cd555cSBin Tu - Sun Microsystems - Beijing China /* DCB registers */ 85069b5a878SDan McDonald #define IXGBE_RTRPCS 0x02430 85169b5a878SDan McDonald #define IXGBE_RTTDCS 0x04900 85269b5a878SDan McDonald #define IXGBE_RTTDCS_ARBDIS 0x00000040 /* DCB arbiter disable */ 85369b5a878SDan McDonald #define IXGBE_RTTPCS 0x0CD00 85469b5a878SDan McDonald #define IXGBE_RTRUP2TC 0x03020 85569b5a878SDan McDonald #define IXGBE_RTTUP2TC 0x0C800 85669b5a878SDan McDonald #define IXGBE_RTRPT4C(_i) (0x02140 + ((_i) * 4)) /* 8 of these (0-7) */ 85769b5a878SDan McDonald #define IXGBE_TXLLQ(_i) (0x082E0 + ((_i) * 4)) /* 4 of these (0-3) */ 85869b5a878SDan McDonald #define IXGBE_RTRPT4S(_i) (0x02160 + ((_i) * 4)) /* 8 of these (0-7) */ 85969b5a878SDan McDonald #define IXGBE_RTTDT2C(_i) (0x04910 + ((_i) * 4)) /* 8 of these (0-7) */ 86069b5a878SDan McDonald #define IXGBE_RTTDT2S(_i) (0x04930 + ((_i) * 4)) /* 8 of these (0-7) */ 86169b5a878SDan McDonald #define IXGBE_RTTPT2C(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */ 86269b5a878SDan McDonald #define IXGBE_RTTPT2S(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */ 86369b5a878SDan McDonald #define IXGBE_RTTDQSEL 0x04904 86469b5a878SDan McDonald #define IXGBE_RTTDT1C 0x04908 86569b5a878SDan McDonald #define IXGBE_RTTDT1S 0x0490C 86669b5a878SDan McDonald #define IXGBE_RTTDTECC 0x04990 86769b5a878SDan McDonald #define IXGBE_RTTDTECC_NO_BCN 0x00000100 86869b5a878SDan McDonald 86969b5a878SDan McDonald #define IXGBE_RTTBCNRC 0x04984 87069b5a878SDan McDonald #define IXGBE_RTTBCNRC_RS_ENA 0x80000000 87169b5a878SDan McDonald #define IXGBE_RTTBCNRC_RF_DEC_MASK 0x00003FFF 87269b5a878SDan McDonald #define IXGBE_RTTBCNRC_RF_INT_SHIFT 14 87363b3bba8SJerry Jelinek #define IXGBE_RTTBCNRC_RF_INT_MASK \ 87463b3bba8SJerry Jelinek (IXGBE_RTTBCNRC_RF_DEC_MASK << IXGBE_RTTBCNRC_RF_INT_SHIFT) 87569b5a878SDan McDonald #define IXGBE_RTTBCNRM 0x04980 87663b3bba8SJerry Jelinek 87763b3bba8SJerry Jelinek /* BCN (for DCB) Registers */ 87869b5a878SDan McDonald #define IXGBE_RTTBCNRS 0x04988 87969b5a878SDan McDonald #define IXGBE_RTTBCNCR 0x08B00 88069b5a878SDan McDonald #define IXGBE_RTTBCNACH 0x08B04 88169b5a878SDan McDonald #define IXGBE_RTTBCNACL 0x08B08 88269b5a878SDan McDonald #define IXGBE_RTTBCNTG 0x04A90 88369b5a878SDan McDonald #define IXGBE_RTTBCNIDX 0x08B0C 88469b5a878SDan McDonald #define IXGBE_RTTBCNCP 0x08B10 88569b5a878SDan McDonald #define IXGBE_RTFRTIMER 0x08B14 88669b5a878SDan McDonald #define IXGBE_RTTBCNRTT 0x05150 88769b5a878SDan McDonald #define IXGBE_RTTBCNRD 0x0498C 88873cd555cSBin Tu - Sun Microsystems - Beijing China 88973cd555cSBin Tu - Sun Microsystems - Beijing China /* FCoE DMA Context Registers */ 890dc0cb1cdSDale Ghent /* FCoE Direct DMA Context */ 891dc0cb1cdSDale Ghent #define IXGBE_FCDDC(_i, _j) (0x20000 + ((_i) * 0x4) + ((_j) * 0x10)) 89269b5a878SDan McDonald #define IXGBE_FCPTRL 0x02410 /* FC User Desc. PTR Low */ 89369b5a878SDan McDonald #define IXGBE_FCPTRH 0x02414 /* FC USer Desc. PTR High */ 89469b5a878SDan McDonald #define IXGBE_FCBUFF 0x02418 /* FC Buffer Control */ 89569b5a878SDan McDonald #define IXGBE_FCDMARW 0x02420 /* FC Receive DMA RW */ 89669b5a878SDan McDonald #define IXGBE_FCBUFF_VALID (1 << 0) /* DMA Context Valid */ 89769b5a878SDan McDonald #define IXGBE_FCBUFF_BUFFSIZE (3 << 3) /* User Buffer Size */ 89869b5a878SDan McDonald #define IXGBE_FCBUFF_WRCONTX (1 << 7) /* 0: Initiator, 1: Target */ 89969b5a878SDan McDonald #define IXGBE_FCBUFF_BUFFCNT 0x0000ff00 /* Number of User Buffers */ 90069b5a878SDan McDonald #define IXGBE_FCBUFF_OFFSET 0xffff0000 /* User Buffer Offset */ 90169b5a878SDan McDonald #define IXGBE_FCBUFF_BUFFSIZE_SHIFT 3 90269b5a878SDan McDonald #define IXGBE_FCBUFF_BUFFCNT_SHIFT 8 90369b5a878SDan McDonald #define IXGBE_FCBUFF_OFFSET_SHIFT 16 90469b5a878SDan McDonald #define IXGBE_FCDMARW_WE (1 << 14) /* Write enable */ 90569b5a878SDan McDonald #define IXGBE_FCDMARW_RE (1 << 15) /* Read enable */ 90669b5a878SDan McDonald #define IXGBE_FCDMARW_FCOESEL 0x000001ff /* FC X_ID: 11 bits */ 90769b5a878SDan McDonald #define IXGBE_FCDMARW_LASTSIZE 0xffff0000 /* Last User Buffer Size */ 90869b5a878SDan McDonald #define IXGBE_FCDMARW_LASTSIZE_SHIFT 16 90973cd555cSBin Tu - Sun Microsystems - Beijing China /* FCoE SOF/EOF */ 91069b5a878SDan McDonald #define IXGBE_TEOFF 0x04A94 /* Tx FC EOF */ 91169b5a878SDan McDonald #define IXGBE_TSOFF 0x04A98 /* Tx FC SOF */ 91269b5a878SDan McDonald #define IXGBE_REOFF 0x05158 /* Rx FC EOF */ 91369b5a878SDan McDonald #define IXGBE_RSOFF 0x051F8 /* Rx FC SOF */ 91473cd555cSBin Tu - Sun Microsystems - Beijing China /* FCoE Filter Context Registers */ 915dc0cb1cdSDale Ghent #define IXGBE_FCD_ID 0x05114 /* FCoE D_ID */ 916dc0cb1cdSDale Ghent #define IXGBE_FCSMAC 0x0510C /* FCoE Source MAC */ 917dc0cb1cdSDale Ghent #define IXGBE_FCFLTRW_SMAC_HIGH_SHIFT 16 918dc0cb1cdSDale Ghent /* FCoE Direct Filter Context */ 919dc0cb1cdSDale Ghent #define IXGBE_FCDFC(_i, _j) (0x28000 + ((_i) * 0x4) + ((_j) * 0x10)) 920dc0cb1cdSDale Ghent #define IXGBE_FCDFCD(_i) (0x30000 + ((_i) * 0x4)) 92169b5a878SDan McDonald #define IXGBE_FCFLT 0x05108 /* FC FLT Context */ 92269b5a878SDan McDonald #define IXGBE_FCFLTRW 0x05110 /* FC Filter RW Control */ 92369b5a878SDan McDonald #define IXGBE_FCPARAM 0x051d8 /* FC Offset Parameter */ 92469b5a878SDan McDonald #define IXGBE_FCFLT_VALID (1 << 0) /* Filter Context Valid */ 92569b5a878SDan McDonald #define IXGBE_FCFLT_FIRST (1 << 1) /* Filter First */ 92669b5a878SDan McDonald #define IXGBE_FCFLT_SEQID 0x00ff0000 /* Sequence ID */ 92769b5a878SDan McDonald #define IXGBE_FCFLT_SEQCNT 0xff000000 /* Sequence Count */ 92869b5a878SDan McDonald #define IXGBE_FCFLTRW_RVALDT (1 << 13) /* Fast Re-Validation */ 92969b5a878SDan McDonald #define IXGBE_FCFLTRW_WE (1 << 14) /* Write Enable */ 93069b5a878SDan McDonald #define IXGBE_FCFLTRW_RE (1 << 15) /* Read Enable */ 93173cd555cSBin Tu - Sun Microsystems - Beijing China /* FCoE Receive Control */ 93269b5a878SDan McDonald #define IXGBE_FCRXCTRL 0x05100 /* FC Receive Control */ 93369b5a878SDan McDonald #define IXGBE_FCRXCTRL_FCOELLI (1 << 0) /* Low latency interrupt */ 93469b5a878SDan McDonald #define IXGBE_FCRXCTRL_SAVBAD (1 << 1) /* Save Bad Frames */ 93569b5a878SDan McDonald #define IXGBE_FCRXCTRL_FRSTRDH (1 << 2) /* EN 1st Read Header */ 93669b5a878SDan McDonald #define IXGBE_FCRXCTRL_LASTSEQH (1 << 3) /* EN Last Header in Seq */ 93769b5a878SDan McDonald #define IXGBE_FCRXCTRL_ALLH (1 << 4) /* EN All Headers */ 93869b5a878SDan McDonald #define IXGBE_FCRXCTRL_FRSTSEQH (1 << 5) /* EN 1st Seq. Header */ 93969b5a878SDan McDonald #define IXGBE_FCRXCTRL_ICRC (1 << 6) /* Ignore Bad FC CRC */ 94069b5a878SDan McDonald #define IXGBE_FCRXCTRL_FCCRCBO (1 << 7) /* FC CRC Byte Ordering */ 94169b5a878SDan McDonald #define IXGBE_FCRXCTRL_FCOEVER 0x00000f00 /* FCoE Version: 4 bits */ 94269b5a878SDan McDonald #define IXGBE_FCRXCTRL_FCOEVER_SHIFT 8 94373cd555cSBin Tu - Sun Microsystems - Beijing China /* FCoE Redirection */ 94469b5a878SDan McDonald #define IXGBE_FCRECTL 0x0ED00 /* FC Redirection Control */ 94569b5a878SDan McDonald #define IXGBE_FCRETA0 0x0ED10 /* FC Redirection Table 0 */ 94669b5a878SDan McDonald #define IXGBE_FCRETA(_i) (IXGBE_FCRETA0 + ((_i) * 4)) /* FCoE Redir */ 94769b5a878SDan McDonald #define IXGBE_FCRECTL_ENA 0x1 /* FCoE Redir Table Enable */ 94869b5a878SDan McDonald #define IXGBE_FCRETASEL_ENA 0x2 /* FCoE FCRETASEL bit */ 94969b5a878SDan McDonald #define IXGBE_FCRETA_SIZE 8 /* Max entries in FCRETA */ 95069b5a878SDan McDonald #define IXGBE_FCRETA_ENTRY_MASK 0x0000007f /* 7 bits for the queue index */ 951dc0cb1cdSDale Ghent #define IXGBE_FCRETA_SIZE_X550 32 /* Max entries in FCRETA */ 952dc0cb1cdSDale Ghent /* Higher 7 bits for the queue index */ 953dc0cb1cdSDale Ghent #define IXGBE_FCRETA_ENTRY_HIGH_MASK 0x007F0000 954dc0cb1cdSDale Ghent #define IXGBE_FCRETA_ENTRY_HIGH_SHIFT 16 9559da57d7bSbt 9569da57d7bSbt /* Stats registers */ 95769b5a878SDan McDonald #define IXGBE_CRCERRS 0x04000 95869b5a878SDan McDonald #define IXGBE_ILLERRC 0x04004 95969b5a878SDan McDonald #define IXGBE_ERRBC 0x04008 96069b5a878SDan McDonald #define IXGBE_MSPDC 0x04010 96169b5a878SDan McDonald #define IXGBE_MPC(_i) (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/ 96269b5a878SDan McDonald #define IXGBE_MLFC 0x04034 96369b5a878SDan McDonald #define IXGBE_MRFC 0x04038 96469b5a878SDan McDonald #define IXGBE_RLEC 0x04040 96569b5a878SDan McDonald #define IXGBE_LXONTXC 0x03F60 96669b5a878SDan McDonald #define IXGBE_LXONRXC 0x0CF60 96769b5a878SDan McDonald #define IXGBE_LXOFFTXC 0x03F68 96869b5a878SDan McDonald #define IXGBE_LXOFFRXC 0x0CF68 96969b5a878SDan McDonald #define IXGBE_LXONRXCNT 0x041A4 97069b5a878SDan McDonald #define IXGBE_LXOFFRXCNT 0x041A8 97169b5a878SDan McDonald #define IXGBE_PXONRXCNT(_i) (0x04140 + ((_i) * 4)) /* 8 of these */ 97269b5a878SDan McDonald #define IXGBE_PXOFFRXCNT(_i) (0x04160 + ((_i) * 4)) /* 8 of these */ 97369b5a878SDan McDonald #define IXGBE_PXON2OFFCNT(_i) (0x03240 + ((_i) * 4)) /* 8 of these */ 97469b5a878SDan McDonald #define IXGBE_PXONTXC(_i) (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/ 97569b5a878SDan McDonald #define IXGBE_PXONRXC(_i) (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/ 97669b5a878SDan McDonald #define IXGBE_PXOFFTXC(_i) (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/ 97769b5a878SDan McDonald #define IXGBE_PXOFFRXC(_i) (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/ 97869b5a878SDan McDonald #define IXGBE_PRC64 0x0405C 97969b5a878SDan McDonald #define IXGBE_PRC127 0x04060 98069b5a878SDan McDonald #define IXGBE_PRC255 0x04064 98169b5a878SDan McDonald #define IXGBE_PRC511 0x04068 98269b5a878SDan McDonald #define IXGBE_PRC1023 0x0406C 98369b5a878SDan McDonald #define IXGBE_PRC1522 0x04070 98469b5a878SDan McDonald #define IXGBE_GPRC 0x04074 98569b5a878SDan McDonald #define IXGBE_BPRC 0x04078 98669b5a878SDan McDonald #define IXGBE_MPRC 0x0407C 98769b5a878SDan McDonald #define IXGBE_GPTC 0x04080 98869b5a878SDan McDonald #define IXGBE_GORCL 0x04088 98969b5a878SDan McDonald #define IXGBE_GORCH 0x0408C 99069b5a878SDan McDonald #define IXGBE_GOTCL 0x04090 99169b5a878SDan McDonald #define IXGBE_GOTCH 0x04094 99269b5a878SDan McDonald #define IXGBE_RNBC(_i) (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/ 99369b5a878SDan McDonald #define IXGBE_RUC 0x040A4 99469b5a878SDan McDonald #define IXGBE_RFC 0x040A8 99569b5a878SDan McDonald #define IXGBE_ROC 0x040AC 99669b5a878SDan McDonald #define IXGBE_RJC 0x040B0 99769b5a878SDan McDonald #define IXGBE_MNGPRC 0x040B4 99869b5a878SDan McDonald #define IXGBE_MNGPDC 0x040B8 99969b5a878SDan McDonald #define IXGBE_MNGPTC 0x0CF90 100069b5a878SDan McDonald #define IXGBE_TORL 0x040C0 100169b5a878SDan McDonald #define IXGBE_TORH 0x040C4 100269b5a878SDan McDonald #define IXGBE_TPR 0x040D0 100369b5a878SDan McDonald #define IXGBE_TPT 0x040D4 100469b5a878SDan McDonald #define IXGBE_PTC64 0x040D8 100569b5a878SDan McDonald #define IXGBE_PTC127 0x040DC 100669b5a878SDan McDonald #define IXGBE_PTC255 0x040E0 100769b5a878SDan McDonald #define IXGBE_PTC511 0x040E4 100869b5a878SDan McDonald #define IXGBE_PTC1023 0x040E8 100969b5a878SDan McDonald #define IXGBE_PTC1522 0x040EC 101069b5a878SDan McDonald #define IXGBE_MPTC 0x040F0 101169b5a878SDan McDonald #define IXGBE_BPTC 0x040F4 101269b5a878SDan McDonald #define IXGBE_XEC 0x04120 101369b5a878SDan McDonald #define IXGBE_SSVPC 0x08780 101469b5a878SDan McDonald 101569b5a878SDan McDonald #define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4)) 101669b5a878SDan McDonald #define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \ 101769b5a878SDan McDonald (0x08600 + ((_i) * 4))) 101869b5a878SDan McDonald #define IXGBE_TQSM(_i) (0x08600 + ((_i) * 4)) 101969b5a878SDan McDonald 102069b5a878SDan McDonald #define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */ 102169b5a878SDan McDonald #define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */ 102269b5a878SDan McDonald #define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */ 102369b5a878SDan McDonald #define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */ 102469b5a878SDan McDonald #define IXGBE_QBRC_L(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */ 102569b5a878SDan McDonald #define IXGBE_QBRC_H(_i) (0x01038 + ((_i) * 0x40)) /* 16 of these */ 102669b5a878SDan McDonald #define IXGBE_QPRDC(_i) (0x01430 + ((_i) * 0x40)) /* 16 of these */ 102769b5a878SDan McDonald #define IXGBE_QBTC_L(_i) (0x08700 + ((_i) * 0x8)) /* 16 of these */ 102869b5a878SDan McDonald #define IXGBE_QBTC_H(_i) (0x08704 + ((_i) * 0x8)) /* 16 of these */ 102969b5a878SDan McDonald #define IXGBE_FCCRC 0x05118 /* Num of Good Eth CRC w/ Bad FC CRC */ 103069b5a878SDan McDonald #define IXGBE_FCOERPDC 0x0241C /* FCoE Rx Packets Dropped Count */ 103169b5a878SDan McDonald #define IXGBE_FCLAST 0x02424 /* FCoE Last Error Count */ 103269b5a878SDan McDonald #define IXGBE_FCOEPRC 0x02428 /* Number of FCoE Packets Received */ 103369b5a878SDan McDonald #define IXGBE_FCOEDWRC 0x0242C /* Number of FCoE DWords Received */ 103469b5a878SDan McDonald #define IXGBE_FCOEPTC 0x08784 /* Number of FCoE Packets Transmitted */ 103569b5a878SDan McDonald #define IXGBE_FCOEDWTC 0x08788 /* Number of FCoE DWords Transmitted */ 103669b5a878SDan McDonald #define IXGBE_FCCRC_CNT_MASK 0x0000FFFF /* CRC_CNT: bit 0 - 15 */ 103769b5a878SDan McDonald #define IXGBE_FCLAST_CNT_MASK 0x0000FFFF /* Last_CNT: bit 0 - 15 */ 103869b5a878SDan McDonald #define IXGBE_O2BGPTC 0x041C4 103969b5a878SDan McDonald #define IXGBE_O2BSPC 0x087B0 104069b5a878SDan McDonald #define IXGBE_B2OSPC 0x041C0 104169b5a878SDan McDonald #define IXGBE_B2OGPRC 0x02F90 104269b5a878SDan McDonald #define IXGBE_BUPRC 0x04180 104369b5a878SDan McDonald #define IXGBE_BMPRC 0x04184 104469b5a878SDan McDonald #define IXGBE_BBPRC 0x04188 104569b5a878SDan McDonald #define IXGBE_BUPTC 0x0418C 104669b5a878SDan McDonald #define IXGBE_BMPTC 0x04190 104769b5a878SDan McDonald #define IXGBE_BBPTC 0x04194 104869b5a878SDan McDonald #define IXGBE_BCRCERRS 0x04198 104969b5a878SDan McDonald #define IXGBE_BXONRXC 0x0419C 105069b5a878SDan McDonald #define IXGBE_BXOFFRXC 0x041E0 105169b5a878SDan McDonald #define IXGBE_BXONTXC 0x041E4 105269b5a878SDan McDonald #define IXGBE_BXOFFTXC 0x041E8 10539da57d7bSbt 10549da57d7bSbt /* Management */ 105569b5a878SDan McDonald #define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */ 105669b5a878SDan McDonald #define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */ 105769b5a878SDan McDonald #define IXGBE_MANC 0x05820 105869b5a878SDan McDonald #define IXGBE_MFVAL 0x05824 105969b5a878SDan McDonald #define IXGBE_MANC2H 0x05860 106069b5a878SDan McDonald #define IXGBE_MDEF(_i) (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */ 106169b5a878SDan McDonald #define IXGBE_MIPAF 0x058B0 106269b5a878SDan McDonald #define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */ 106369b5a878SDan McDonald #define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */ 106469b5a878SDan McDonald #define IXGBE_FTFT 0x09400 /* 0x9400-0x97FC */ 106569b5a878SDan McDonald #define IXGBE_METF(_i) (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */ 106669b5a878SDan McDonald #define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */ 1067*48ed61a7SRobert Mustacchi #define IXGBE_LSWFW 0x15F14 106869b5a878SDan McDonald #define IXGBE_BMCIP(_i) (0x05050 + ((_i) * 4)) /* 0x5050-0x505C */ 106969b5a878SDan McDonald #define IXGBE_BMCIPVAL 0x05060 107069b5a878SDan McDonald #define IXGBE_BMCIP_IPADDR_TYPE 0x00000001 107169b5a878SDan McDonald #define IXGBE_BMCIP_IPADDR_VALID 0x00000002 107269b5a878SDan McDonald 107369b5a878SDan McDonald /* Management Bit Fields and Masks */ 1074dc0cb1cdSDale Ghent #define IXGBE_MANC_MPROXYE 0x40000000 /* Management Proxy Enable */ 1075dc0cb1cdSDale Ghent #define IXGBE_MANC_RCV_TCO_EN 0x00020000 /* Rcv TCO packet enable */ 107669b5a878SDan McDonald #define IXGBE_MANC_EN_BMC2OS 0x10000000 /* Ena BMC2OS and OS2BMC traffic */ 107769b5a878SDan McDonald #define IXGBE_MANC_EN_BMC2OS_SHIFT 28 107869b5a878SDan McDonald 107969b5a878SDan McDonald /* Firmware Semaphore Register */ 108069b5a878SDan McDonald #define IXGBE_FWSM_MODE_MASK 0xE 1081dc0cb1cdSDale Ghent #define IXGBE_FWSM_TS_ENABLED 0x1 1082dc0cb1cdSDale Ghent #define IXGBE_FWSM_FW_MODE_PT 0x4 10839da57d7bSbt 10849da57d7bSbt /* ARC Subsystem registers */ 108569b5a878SDan McDonald #define IXGBE_HICR 0x15F00 108669b5a878SDan McDonald #define IXGBE_FWSTS 0x15F0C 108769b5a878SDan McDonald #define IXGBE_HSMC0R 0x15F04 108869b5a878SDan McDonald #define IXGBE_HSMC1R 0x15F08 108969b5a878SDan McDonald #define IXGBE_SWSR 0x15F10 109069b5a878SDan McDonald #define IXGBE_HFDR 0x15FE8 109169b5a878SDan McDonald #define IXGBE_FLEX_MNG 0x15800 /* 0x15800 - 0x15EFC */ 109269b5a878SDan McDonald 109369b5a878SDan McDonald #define IXGBE_HICR_EN 0x01 /* Enable bit - RO */ 109469b5a878SDan McDonald /* Driver sets this bit when done to put command in RAM */ 109569b5a878SDan McDonald #define IXGBE_HICR_C 0x02 109669b5a878SDan McDonald #define IXGBE_HICR_SV 0x04 /* Status Validity */ 109769b5a878SDan McDonald #define IXGBE_HICR_FW_RESET_ENABLE 0x40 109869b5a878SDan McDonald #define IXGBE_HICR_FW_RESET 0x80 10999da57d7bSbt 11009da57d7bSbt /* PCI-E registers */ 110169b5a878SDan McDonald #define IXGBE_GCR 0x11000 110269b5a878SDan McDonald #define IXGBE_GTV 0x11004 110369b5a878SDan McDonald #define IXGBE_FUNCTAG 0x11008 110469b5a878SDan McDonald #define IXGBE_GLT 0x1100C 110569b5a878SDan McDonald #define IXGBE_PCIEPIPEADR 0x11004 110669b5a878SDan McDonald #define IXGBE_PCIEPIPEDAT 0x11008 110769b5a878SDan McDonald #define IXGBE_GSCL_1 0x11010 110869b5a878SDan McDonald #define IXGBE_GSCL_2 0x11014 1109*48ed61a7SRobert Mustacchi #define IXGBE_GSCL_1_X540 IXGBE_GSCL_1 1110*48ed61a7SRobert Mustacchi #define IXGBE_GSCL_2_X540 IXGBE_GSCL_2 111169b5a878SDan McDonald #define IXGBE_GSCL_3 0x11018 111269b5a878SDan McDonald #define IXGBE_GSCL_4 0x1101C 111369b5a878SDan McDonald #define IXGBE_GSCN_0 0x11020 111469b5a878SDan McDonald #define IXGBE_GSCN_1 0x11024 111569b5a878SDan McDonald #define IXGBE_GSCN_2 0x11028 111669b5a878SDan McDonald #define IXGBE_GSCN_3 0x1102C 1117*48ed61a7SRobert Mustacchi #define IXGBE_GSCN_0_X540 IXGBE_GSCN_0 1118*48ed61a7SRobert Mustacchi #define IXGBE_GSCN_1_X540 IXGBE_GSCN_1 1119*48ed61a7SRobert Mustacchi #define IXGBE_GSCN_2_X540 IXGBE_GSCN_2 1120*48ed61a7SRobert Mustacchi #define IXGBE_GSCN_3_X540 IXGBE_GSCN_3 112169b5a878SDan McDonald #define IXGBE_FACTPS 0x10150 1122dc0cb1cdSDale Ghent #define IXGBE_FACTPS_X540 IXGBE_FACTPS 1123*48ed61a7SRobert Mustacchi #define IXGBE_GSCL_1_X550 0x11800 1124*48ed61a7SRobert Mustacchi #define IXGBE_GSCL_2_X550 0x11804 1125*48ed61a7SRobert Mustacchi #define IXGBE_GSCL_1_X550EM_x IXGBE_GSCL_1_X550 1126*48ed61a7SRobert Mustacchi #define IXGBE_GSCL_2_X550EM_x IXGBE_GSCL_2_X550 1127*48ed61a7SRobert Mustacchi #define IXGBE_GSCN_0_X550 0x11820 1128*48ed61a7SRobert Mustacchi #define IXGBE_GSCN_1_X550 0x11824 1129*48ed61a7SRobert Mustacchi #define IXGBE_GSCN_2_X550 0x11828 1130*48ed61a7SRobert Mustacchi #define IXGBE_GSCN_3_X550 0x1182C 1131*48ed61a7SRobert Mustacchi #define IXGBE_GSCN_0_X550EM_x IXGBE_GSCN_0_X550 1132*48ed61a7SRobert Mustacchi #define IXGBE_GSCN_1_X550EM_x IXGBE_GSCN_1_X550 1133*48ed61a7SRobert Mustacchi #define IXGBE_GSCN_2_X550EM_x IXGBE_GSCN_2_X550 1134*48ed61a7SRobert Mustacchi #define IXGBE_GSCN_3_X550EM_x IXGBE_GSCN_3_X550 1135dc0cb1cdSDale Ghent #define IXGBE_FACTPS_X550 IXGBE_FACTPS 1136dc0cb1cdSDale Ghent #define IXGBE_FACTPS_X550EM_x IXGBE_FACTPS 1137*48ed61a7SRobert Mustacchi #define IXGBE_GSCL_1_X550EM_a IXGBE_GSCL_1_X550 1138*48ed61a7SRobert Mustacchi #define IXGBE_GSCL_2_X550EM_a IXGBE_GSCL_2_X550 1139*48ed61a7SRobert Mustacchi #define IXGBE_GSCN_0_X550EM_a IXGBE_GSCN_0_X550 1140*48ed61a7SRobert Mustacchi #define IXGBE_GSCN_1_X550EM_a IXGBE_GSCN_1_X550 1141*48ed61a7SRobert Mustacchi #define IXGBE_GSCN_2_X550EM_a IXGBE_GSCN_2_X550 1142*48ed61a7SRobert Mustacchi #define IXGBE_GSCN_3_X550EM_a IXGBE_GSCN_3_X550 1143*48ed61a7SRobert Mustacchi #define IXGBE_FACTPS_X550EM_a 0x15FEC 1144*48ed61a7SRobert Mustacchi #define IXGBE_FACTPS_BY_MAC(_hw) IXGBE_BY_MAC((_hw), FACTPS) 1145dc0cb1cdSDale Ghent 114669b5a878SDan McDonald #define IXGBE_PCIEANACTL 0x11040 114769b5a878SDan McDonald #define IXGBE_SWSM 0x10140 1148dc0cb1cdSDale Ghent #define IXGBE_SWSM_X540 IXGBE_SWSM 1149dc0cb1cdSDale Ghent #define IXGBE_SWSM_X550 IXGBE_SWSM 1150dc0cb1cdSDale Ghent #define IXGBE_SWSM_X550EM_x IXGBE_SWSM 1151*48ed61a7SRobert Mustacchi #define IXGBE_SWSM_X550EM_a 0x15F70 1152*48ed61a7SRobert Mustacchi #define IXGBE_SWSM_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SWSM) 1153dc0cb1cdSDale Ghent 115469b5a878SDan McDonald #define IXGBE_FWSM 0x10148 1155dc0cb1cdSDale Ghent #define IXGBE_FWSM_X540 IXGBE_FWSM 1156dc0cb1cdSDale Ghent #define IXGBE_FWSM_X550 IXGBE_FWSM 1157dc0cb1cdSDale Ghent #define IXGBE_FWSM_X550EM_x IXGBE_FWSM 1158*48ed61a7SRobert Mustacchi #define IXGBE_FWSM_X550EM_a 0x15F74 1159*48ed61a7SRobert Mustacchi #define IXGBE_FWSM_BY_MAC(_hw) IXGBE_BY_MAC((_hw), FWSM) 1160dc0cb1cdSDale Ghent 1161dc0cb1cdSDale Ghent #define IXGBE_SWFW_SYNC IXGBE_GSSR 1162dc0cb1cdSDale Ghent #define IXGBE_SWFW_SYNC_X540 IXGBE_SWFW_SYNC 1163dc0cb1cdSDale Ghent #define IXGBE_SWFW_SYNC_X550 IXGBE_SWFW_SYNC 1164dc0cb1cdSDale Ghent #define IXGBE_SWFW_SYNC_X550EM_x IXGBE_SWFW_SYNC 1165*48ed61a7SRobert Mustacchi #define IXGBE_SWFW_SYNC_X550EM_a 0x15F78 1166*48ed61a7SRobert Mustacchi #define IXGBE_SWFW_SYNC_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SWFW_SYNC) 1167dc0cb1cdSDale Ghent 116869b5a878SDan McDonald #define IXGBE_GSSR 0x10160 116969b5a878SDan McDonald #define IXGBE_MREVID 0x11064 117069b5a878SDan McDonald #define IXGBE_DCA_ID 0x11070 117169b5a878SDan McDonald #define IXGBE_DCA_CTRL 0x11074 11729da57d7bSbt 1173185c5677SPaul Guo /* PCI-E registers 82599-Specific */ 117469b5a878SDan McDonald #define IXGBE_GCR_EXT 0x11050 117569b5a878SDan McDonald #define IXGBE_GSCL_5_82599 0x11030 117669b5a878SDan McDonald #define IXGBE_GSCL_6_82599 0x11034 117769b5a878SDan McDonald #define IXGBE_GSCL_7_82599 0x11038 117869b5a878SDan McDonald #define IXGBE_GSCL_8_82599 0x1103C 1179*48ed61a7SRobert Mustacchi #define IXGBE_GSCL_5_X540 IXGBE_GSCL_5_82599 1180*48ed61a7SRobert Mustacchi #define IXGBE_GSCL_6_X540 IXGBE_GSCL_6_82599 1181*48ed61a7SRobert Mustacchi #define IXGBE_GSCL_7_X540 IXGBE_GSCL_7_82599 1182*48ed61a7SRobert Mustacchi #define IXGBE_GSCL_8_X540 IXGBE_GSCL_8_82599 118369b5a878SDan McDonald #define IXGBE_PHYADR_82599 0x11040 118469b5a878SDan McDonald #define IXGBE_PHYDAT_82599 0x11044 118569b5a878SDan McDonald #define IXGBE_PHYCTL_82599 0x11048 118669b5a878SDan McDonald #define IXGBE_PBACLR_82599 0x11068 1187dc0cb1cdSDale Ghent #define IXGBE_CIAA 0x11088 1188dc0cb1cdSDale Ghent #define IXGBE_CIAD 0x1108C 1189dc0cb1cdSDale Ghent #define IXGBE_CIAA_82599 IXGBE_CIAA 1190dc0cb1cdSDale Ghent #define IXGBE_CIAD_82599 IXGBE_CIAD 1191dc0cb1cdSDale Ghent #define IXGBE_CIAA_X540 IXGBE_CIAA 1192dc0cb1cdSDale Ghent #define IXGBE_CIAD_X540 IXGBE_CIAD 1193*48ed61a7SRobert Mustacchi #define IXGBE_GSCL_5_X550 0x11810 1194*48ed61a7SRobert Mustacchi #define IXGBE_GSCL_6_X550 0x11814 1195*48ed61a7SRobert Mustacchi #define IXGBE_GSCL_7_X550 0x11818 1196*48ed61a7SRobert Mustacchi #define IXGBE_GSCL_8_X550 0x1181C 1197*48ed61a7SRobert Mustacchi #define IXGBE_GSCL_5_X550EM_x IXGBE_GSCL_5_X550 1198*48ed61a7SRobert Mustacchi #define IXGBE_GSCL_6_X550EM_x IXGBE_GSCL_6_X550 1199*48ed61a7SRobert Mustacchi #define IXGBE_GSCL_7_X550EM_x IXGBE_GSCL_7_X550 1200*48ed61a7SRobert Mustacchi #define IXGBE_GSCL_8_X550EM_x IXGBE_GSCL_8_X550 1201dc0cb1cdSDale Ghent #define IXGBE_CIAA_X550 0x11508 1202dc0cb1cdSDale Ghent #define IXGBE_CIAD_X550 0x11510 1203dc0cb1cdSDale Ghent #define IXGBE_CIAA_X550EM_x IXGBE_CIAA_X550 1204dc0cb1cdSDale Ghent #define IXGBE_CIAD_X550EM_x IXGBE_CIAD_X550 1205*48ed61a7SRobert Mustacchi #define IXGBE_GSCL_5_X550EM_a IXGBE_GSCL_5_X550 1206*48ed61a7SRobert Mustacchi #define IXGBE_GSCL_6_X550EM_a IXGBE_GSCL_6_X550 1207*48ed61a7SRobert Mustacchi #define IXGBE_GSCL_7_X550EM_a IXGBE_GSCL_7_X550 1208*48ed61a7SRobert Mustacchi #define IXGBE_GSCL_8_X550EM_a IXGBE_GSCL_8_X550 1209*48ed61a7SRobert Mustacchi #define IXGBE_CIAA_X550EM_a IXGBE_CIAA_X550 1210*48ed61a7SRobert Mustacchi #define IXGBE_CIAD_X550EM_a IXGBE_CIAD_X550 1211dc0cb1cdSDale Ghent #define IXGBE_CIAA_BY_MAC(_hw) IXGBE_BY_MAC((_hw), CIAA) 1212dc0cb1cdSDale Ghent #define IXGBE_CIAD_BY_MAC(_hw) IXGBE_BY_MAC((_hw), CIAD) 121369b5a878SDan McDonald #define IXGBE_PICAUSE 0x110B0 121469b5a878SDan McDonald #define IXGBE_PIENA 0x110B8 121569b5a878SDan McDonald #define IXGBE_CDQ_MBR_82599 0x110B4 121669b5a878SDan McDonald #define IXGBE_PCIESPARE 0x110BC 121769b5a878SDan McDonald #define IXGBE_MISC_REG_82599 0x110F0 121869b5a878SDan McDonald #define IXGBE_ECC_CTRL_0_82599 0x11100 121969b5a878SDan McDonald #define IXGBE_ECC_CTRL_1_82599 0x11104 122069b5a878SDan McDonald #define IXGBE_ECC_STATUS_82599 0x110E0 122169b5a878SDan McDonald #define IXGBE_BAR_CTRL_82599 0x110F4 122273cd555cSBin Tu - Sun Microsystems - Beijing China 12233cfa0eb9Schenlu chen - Sun Microsystems - Beijing China /* PCI Express Control */ 122469b5a878SDan McDonald #define IXGBE_GCR_CMPL_TMOUT_MASK 0x0000F000 122569b5a878SDan McDonald #define IXGBE_GCR_CMPL_TMOUT_10ms 0x00001000 122669b5a878SDan McDonald #define IXGBE_GCR_CMPL_TMOUT_RESEND 0x00010000 122769b5a878SDan McDonald #define IXGBE_GCR_CAP_VER2 0x00040000 122869b5a878SDan McDonald 122969b5a878SDan McDonald #define IXGBE_GCR_EXT_MSIX_EN 0x80000000 123069b5a878SDan McDonald #define IXGBE_GCR_EXT_BUFFERS_CLEAR 0x40000000 123169b5a878SDan McDonald #define IXGBE_GCR_EXT_VT_MODE_16 0x00000001 123269b5a878SDan McDonald #define IXGBE_GCR_EXT_VT_MODE_32 0x00000002 123369b5a878SDan McDonald #define IXGBE_GCR_EXT_VT_MODE_64 0x00000003 123469b5a878SDan McDonald #define IXGBE_GCR_EXT_SRIOV (IXGBE_GCR_EXT_MSIX_EN | \ 123569b5a878SDan McDonald IXGBE_GCR_EXT_VT_MODE_64) 123669b5a878SDan McDonald #define IXGBE_GCR_EXT_VT_MODE_MASK 0x00000003 123773cd555cSBin Tu - Sun Microsystems - Beijing China /* Time Sync Registers */ 123869b5a878SDan McDonald #define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */ 123969b5a878SDan McDonald #define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */ 124069b5a878SDan McDonald #define IXGBE_RXSTMPL 0x051E8 /* Rx timestamp Low - RO */ 124169b5a878SDan McDonald #define IXGBE_RXSTMPH 0x051A4 /* Rx timestamp High - RO */ 124269b5a878SDan McDonald #define IXGBE_RXSATRL 0x051A0 /* Rx timestamp attribute low - RO */ 124369b5a878SDan McDonald #define IXGBE_RXSATRH 0x051A8 /* Rx timestamp attribute high - RO */ 124469b5a878SDan McDonald #define IXGBE_RXMTRL 0x05120 /* RX message type register low - RW */ 124569b5a878SDan McDonald #define IXGBE_TXSTMPL 0x08C04 /* Tx timestamp value Low - RO */ 124669b5a878SDan McDonald #define IXGBE_TXSTMPH 0x08C08 /* Tx timestamp value High - RO */ 124769b5a878SDan McDonald #define IXGBE_SYSTIML 0x08C0C /* System time register Low - RO */ 124869b5a878SDan McDonald #define IXGBE_SYSTIMH 0x08C10 /* System time register High - RO */ 1249dc0cb1cdSDale Ghent #define IXGBE_SYSTIMR 0x08C58 /* System time register Residue - RO */ 125069b5a878SDan McDonald #define IXGBE_TIMINCA 0x08C14 /* Increment attributes register - RW */ 125169b5a878SDan McDonald #define IXGBE_TIMADJL 0x08C18 /* Time Adjustment Offset register Low - RW */ 125269b5a878SDan McDonald #define IXGBE_TIMADJH 0x08C1C /* Time Adjustment Offset register High - RW */ 125369b5a878SDan McDonald #define IXGBE_TSAUXC 0x08C20 /* TimeSync Auxiliary Control register - RW */ 125469b5a878SDan McDonald #define IXGBE_TRGTTIML0 0x08C24 /* Target Time Register 0 Low - RW */ 125569b5a878SDan McDonald #define IXGBE_TRGTTIMH0 0x08C28 /* Target Time Register 0 High - RW */ 125669b5a878SDan McDonald #define IXGBE_TRGTTIML1 0x08C2C /* Target Time Register 1 Low - RW */ 125769b5a878SDan McDonald #define IXGBE_TRGTTIMH1 0x08C30 /* Target Time Register 1 High - RW */ 125869b5a878SDan McDonald #define IXGBE_CLKTIML 0x08C34 /* Clock Out Time Register Low - RW */ 125969b5a878SDan McDonald #define IXGBE_CLKTIMH 0x08C38 /* Clock Out Time Register High - RW */ 126069b5a878SDan McDonald #define IXGBE_FREQOUT0 0x08C34 /* Frequency Out 0 Control register - RW */ 126169b5a878SDan McDonald #define IXGBE_FREQOUT1 0x08C38 /* Frequency Out 1 Control register - RW */ 126269b5a878SDan McDonald #define IXGBE_AUXSTMPL0 0x08C3C /* Auxiliary Time Stamp 0 register Low - RO */ 126369b5a878SDan McDonald #define IXGBE_AUXSTMPH0 0x08C40 /* Auxiliary Time Stamp 0 register High - RO */ 126469b5a878SDan McDonald #define IXGBE_AUXSTMPL1 0x08C44 /* Auxiliary Time Stamp 1 register Low - RO */ 126569b5a878SDan McDonald #define IXGBE_AUXSTMPH1 0x08C48 /* Auxiliary Time Stamp 1 register High - RO */ 1266dc0cb1cdSDale Ghent #define IXGBE_TSIM 0x08C68 /* TimeSync Interrupt Mask Register - RW */ 1267dc0cb1cdSDale Ghent #define IXGBE_TSICR 0x08C60 /* TimeSync Interrupt Cause Register - WO */ 1268dc0cb1cdSDale Ghent #define IXGBE_TSSDP 0x0003C /* TimeSync SDP Configuration Register - RW */ 126973cd555cSBin Tu - Sun Microsystems - Beijing China 12709da57d7bSbt /* Diagnostic Registers */ 127169b5a878SDan McDonald #define IXGBE_RDSTATCTL 0x02C20 127269b5a878SDan McDonald #define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */ 127369b5a878SDan McDonald #define IXGBE_RDHMPN 0x02F08 127469b5a878SDan McDonald #define IXGBE_RIC_DW(_i) (0x02F10 + ((_i) * 4)) 127569b5a878SDan McDonald #define IXGBE_RDPROBE 0x02F20 127669b5a878SDan McDonald #define IXGBE_RDMAM 0x02F30 127769b5a878SDan McDonald #define IXGBE_RDMAD 0x02F34 127869b5a878SDan McDonald #define IXGBE_TDHMPN 0x07F08 127969b5a878SDan McDonald #define IXGBE_TDHMPN2 0x082FC 128069b5a878SDan McDonald #define IXGBE_TXDESCIC 0x082CC 128169b5a878SDan McDonald #define IXGBE_TIC_DW(_i) (0x07F10 + ((_i) * 4)) 128269b5a878SDan McDonald #define IXGBE_TIC_DW2(_i) (0x082B0 + ((_i) * 4)) 128369b5a878SDan McDonald #define IXGBE_TDPROBE 0x07F20 128469b5a878SDan McDonald #define IXGBE_TXBUFCTRL 0x0C600 128569b5a878SDan McDonald #define IXGBE_TXBUFDATA0 0x0C610 128669b5a878SDan McDonald #define IXGBE_TXBUFDATA1 0x0C614 128769b5a878SDan McDonald #define IXGBE_TXBUFDATA2 0x0C618 128869b5a878SDan McDonald #define IXGBE_TXBUFDATA3 0x0C61C 128969b5a878SDan McDonald #define IXGBE_RXBUFCTRL 0x03600 129069b5a878SDan McDonald #define IXGBE_RXBUFDATA0 0x03610 129169b5a878SDan McDonald #define IXGBE_RXBUFDATA1 0x03614 129269b5a878SDan McDonald #define IXGBE_RXBUFDATA2 0x03618 129369b5a878SDan McDonald #define IXGBE_RXBUFDATA3 0x0361C 129469b5a878SDan McDonald #define IXGBE_PCIE_DIAG(_i) (0x11090 + ((_i) * 4)) /* 8 of these */ 129569b5a878SDan McDonald #define IXGBE_RFVAL 0x050A4 129669b5a878SDan McDonald #define IXGBE_MDFTC1 0x042B8 129769b5a878SDan McDonald #define IXGBE_MDFTC2 0x042C0 129869b5a878SDan McDonald #define IXGBE_MDFTFIFO1 0x042C4 129969b5a878SDan McDonald #define IXGBE_MDFTFIFO2 0x042C8 130069b5a878SDan McDonald #define IXGBE_MDFTS 0x042CC 130169b5a878SDan McDonald #define IXGBE_RXDATAWRPTR(_i) (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/ 130269b5a878SDan McDonald #define IXGBE_RXDESCWRPTR(_i) (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/ 130369b5a878SDan McDonald #define IXGBE_RXDATARDPTR(_i) (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/ 130469b5a878SDan McDonald #define IXGBE_RXDESCRDPTR(_i) (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/ 130569b5a878SDan McDonald #define IXGBE_TXDATAWRPTR(_i) (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/ 130669b5a878SDan McDonald #define IXGBE_TXDESCWRPTR(_i) (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/ 130769b5a878SDan McDonald #define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/ 130869b5a878SDan McDonald #define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/ 130969b5a878SDan McDonald #define IXGBE_PCIEECCCTL 0x1106C 131069b5a878SDan McDonald #define IXGBE_RXWRPTR(_i) (0x03100 + ((_i) * 4)) /* 8 of these 3100-310C*/ 131169b5a878SDan McDonald #define IXGBE_RXUSED(_i) (0x03120 + ((_i) * 4)) /* 8 of these 3120-312C*/ 131269b5a878SDan McDonald #define IXGBE_RXRDPTR(_i) (0x03140 + ((_i) * 4)) /* 8 of these 3140-314C*/ 131369b5a878SDan McDonald #define IXGBE_RXRDWRPTR(_i) (0x03160 + ((_i) * 4)) /* 8 of these 3160-310C*/ 131469b5a878SDan McDonald #define IXGBE_TXWRPTR(_i) (0x0C100 + ((_i) * 4)) /* 8 of these C100-C10C*/ 131569b5a878SDan McDonald #define IXGBE_TXUSED(_i) (0x0C120 + ((_i) * 4)) /* 8 of these C120-C12C*/ 131669b5a878SDan McDonald #define IXGBE_TXRDPTR(_i) (0x0C140 + ((_i) * 4)) /* 8 of these C140-C14C*/ 131769b5a878SDan McDonald #define IXGBE_TXRDWRPTR(_i) (0x0C160 + ((_i) * 4)) /* 8 of these C160-C10C*/ 131869b5a878SDan McDonald #define IXGBE_PCIEECCCTL0 0x11100 131969b5a878SDan McDonald #define IXGBE_PCIEECCCTL1 0x11104 132069b5a878SDan McDonald #define IXGBE_RXDBUECC 0x03F70 132169b5a878SDan McDonald #define IXGBE_TXDBUECC 0x0CF70 132269b5a878SDan McDonald #define IXGBE_RXDBUEST 0x03F74 132369b5a878SDan McDonald #define IXGBE_TXDBUEST 0x0CF74 132469b5a878SDan McDonald #define IXGBE_PBTXECC 0x0C300 132569b5a878SDan McDonald #define IXGBE_PBRXECC 0x03300 132669b5a878SDan McDonald #define IXGBE_GHECCR 0x110B0 13279da57d7bSbt 13289da57d7bSbt /* MAC Registers */ 132969b5a878SDan McDonald #define IXGBE_PCS1GCFIG 0x04200 133069b5a878SDan McDonald #define IXGBE_PCS1GLCTL 0x04208 133169b5a878SDan McDonald #define IXGBE_PCS1GLSTA 0x0420C 133269b5a878SDan McDonald #define IXGBE_PCS1GDBG0 0x04210 133369b5a878SDan McDonald #define IXGBE_PCS1GDBG1 0x04214 133469b5a878SDan McDonald #define IXGBE_PCS1GANA 0x04218 133569b5a878SDan McDonald #define IXGBE_PCS1GANLP 0x0421C 133669b5a878SDan McDonald #define IXGBE_PCS1GANNP 0x04220 133769b5a878SDan McDonald #define IXGBE_PCS1GANLPNP 0x04224 133869b5a878SDan McDonald #define IXGBE_HLREG0 0x04240 133969b5a878SDan McDonald #define IXGBE_HLREG1 0x04244 134069b5a878SDan McDonald #define IXGBE_PAP 0x04248 134169b5a878SDan McDonald #define IXGBE_MACA 0x0424C 134269b5a878SDan McDonald #define IXGBE_APAE 0x04250 134369b5a878SDan McDonald #define IXGBE_ARD 0x04254 134469b5a878SDan McDonald #define IXGBE_AIS 0x04258 134569b5a878SDan McDonald #define IXGBE_MSCA 0x0425C 134669b5a878SDan McDonald #define IXGBE_MSRWD 0x04260 134769b5a878SDan McDonald #define IXGBE_MLADD 0x04264 134869b5a878SDan McDonald #define IXGBE_MHADD 0x04268 134969b5a878SDan McDonald #define IXGBE_MAXFRS 0x04268 135069b5a878SDan McDonald #define IXGBE_TREG 0x0426C 135169b5a878SDan McDonald #define IXGBE_PCSS1 0x04288 135269b5a878SDan McDonald #define IXGBE_PCSS2 0x0428C 135369b5a878SDan McDonald #define IXGBE_XPCSS 0x04290 135469b5a878SDan McDonald #define IXGBE_MFLCN 0x04294 135569b5a878SDan McDonald #define IXGBE_SERDESC 0x04298 1356*48ed61a7SRobert Mustacchi #define IXGBE_MAC_SGMII_BUSY 0x04298 135769b5a878SDan McDonald #define IXGBE_MACS 0x0429C 135869b5a878SDan McDonald #define IXGBE_AUTOC 0x042A0 135969b5a878SDan McDonald #define IXGBE_LINKS 0x042A4 136069b5a878SDan McDonald #define IXGBE_LINKS2 0x04324 136169b5a878SDan McDonald #define IXGBE_AUTOC2 0x042A8 136269b5a878SDan McDonald #define IXGBE_AUTOC3 0x042AC 136369b5a878SDan McDonald #define IXGBE_ANLP1 0x042B0 136469b5a878SDan McDonald #define IXGBE_ANLP2 0x042B4 136569b5a878SDan McDonald #define IXGBE_MACC 0x04330 136669b5a878SDan McDonald #define IXGBE_ATLASCTL 0x04800 136769b5a878SDan McDonald #define IXGBE_MMNGC 0x042D0 136869b5a878SDan McDonald #define IXGBE_ANLPNP1 0x042D4 136969b5a878SDan McDonald #define IXGBE_ANLPNP2 0x042D8 137069b5a878SDan McDonald #define IXGBE_KRPCSFC 0x042E0 137169b5a878SDan McDonald #define IXGBE_KRPCSS 0x042E4 137269b5a878SDan McDonald #define IXGBE_FECS1 0x042E8 137369b5a878SDan McDonald #define IXGBE_FECS2 0x042EC 137469b5a878SDan McDonald #define IXGBE_SMADARCTL 0x14F10 137569b5a878SDan McDonald #define IXGBE_MPVC 0x04318 137669b5a878SDan McDonald #define IXGBE_SGMIIC 0x04314 137769b5a878SDan McDonald 137869b5a878SDan McDonald /* Statistics Registers */ 137969b5a878SDan McDonald #define IXGBE_RXNFGPC 0x041B0 138069b5a878SDan McDonald #define IXGBE_RXNFGBCL 0x041B4 138169b5a878SDan McDonald #define IXGBE_RXNFGBCH 0x041B8 138269b5a878SDan McDonald #define IXGBE_RXDGPC 0x02F50 138369b5a878SDan McDonald #define IXGBE_RXDGBCL 0x02F54 138469b5a878SDan McDonald #define IXGBE_RXDGBCH 0x02F58 138569b5a878SDan McDonald #define IXGBE_RXDDGPC 0x02F5C 138669b5a878SDan McDonald #define IXGBE_RXDDGBCL 0x02F60 138769b5a878SDan McDonald #define IXGBE_RXDDGBCH 0x02F64 138869b5a878SDan McDonald #define IXGBE_RXLPBKGPC 0x02F68 138969b5a878SDan McDonald #define IXGBE_RXLPBKGBCL 0x02F6C 139069b5a878SDan McDonald #define IXGBE_RXLPBKGBCH 0x02F70 139169b5a878SDan McDonald #define IXGBE_RXDLPBKGPC 0x02F74 139269b5a878SDan McDonald #define IXGBE_RXDLPBKGBCL 0x02F78 139369b5a878SDan McDonald #define IXGBE_RXDLPBKGBCH 0x02F7C 139469b5a878SDan McDonald #define IXGBE_TXDGPC 0x087A0 139569b5a878SDan McDonald #define IXGBE_TXDGBCL 0x087A4 139669b5a878SDan McDonald #define IXGBE_TXDGBCH 0x087A8 139769b5a878SDan McDonald 139869b5a878SDan McDonald #define IXGBE_RXDSTATCTRL 0x02F40 139973cd555cSBin Tu - Sun Microsystems - Beijing China 140019843f01SPaul Guo /* Copper Pond 2 link timeout */ 140163b3bba8SJerry Jelinek #define IXGBE_VALIDATE_LINK_READY_TIMEOUT 50 140219843f01SPaul Guo 140373cd555cSBin Tu - Sun Microsystems - Beijing China /* Omer CORECTL */ 140469b5a878SDan McDonald #define IXGBE_CORECTL 0x014F00 140573cd555cSBin Tu - Sun Microsystems - Beijing China /* BARCTRL */ 140669b5a878SDan McDonald #define IXGBE_BARCTRL 0x110F4 140769b5a878SDan McDonald #define IXGBE_BARCTRL_FLSIZE 0x0700 140869b5a878SDan McDonald #define IXGBE_BARCTRL_FLSIZE_SHIFT 8 140969b5a878SDan McDonald #define IXGBE_BARCTRL_CSRSIZE 0x2000 141073cd555cSBin Tu - Sun Microsystems - Beijing China 141173cd555cSBin Tu - Sun Microsystems - Beijing China /* RSCCTL Bit Masks */ 141269b5a878SDan McDonald #define IXGBE_RSCCTL_RSCEN 0x01 141369b5a878SDan McDonald #define IXGBE_RSCCTL_MAXDESC_1 0x00 141469b5a878SDan McDonald #define IXGBE_RSCCTL_MAXDESC_4 0x04 141569b5a878SDan McDonald #define IXGBE_RSCCTL_MAXDESC_8 0x08 141669b5a878SDan McDonald #define IXGBE_RSCCTL_MAXDESC_16 0x0C 1417dc0cb1cdSDale Ghent #define IXGBE_RSCCTL_TS_DIS 0x02 141873cd555cSBin Tu - Sun Microsystems - Beijing China 141973cd555cSBin Tu - Sun Microsystems - Beijing China /* RSCDBU Bit Masks */ 142069b5a878SDan McDonald #define IXGBE_RSCDBU_RSCSMALDIS_MASK 0x0000007F 142169b5a878SDan McDonald #define IXGBE_RSCDBU_RSCACKDIS 0x00000080 14229da57d7bSbt 142313740cb2SPaul Guo /* RDRXCTL Bit Masks */ 142469b5a878SDan McDonald #define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 /* Rx Desc Min THLD Size */ 142569b5a878SDan McDonald #define IXGBE_RDRXCTL_CRCSTRIP 0x00000002 /* CRC Strip */ 1426dc0cb1cdSDale Ghent #define IXGBE_RDRXCTL_PSP 0x00000004 /* Pad Small Packet */ 142769b5a878SDan McDonald #define IXGBE_RDRXCTL_MVMEN 0x00000020 1428dc0cb1cdSDale Ghent #define IXGBE_RDRXCTL_RSC_PUSH_DIS 0x00000020 142969b5a878SDan McDonald #define IXGBE_RDRXCTL_DMAIDONE 0x00000008 /* DMA init cycle done */ 1430dc0cb1cdSDale Ghent #define IXGBE_RDRXCTL_RSC_PUSH 0x00000080 143169b5a878SDan McDonald #define IXGBE_RDRXCTL_AGGDIS 0x00010000 /* Aggregation disable */ 143269b5a878SDan McDonald #define IXGBE_RDRXCTL_RSCFRSTSIZE 0x003E0000 /* RSC First packet size */ 1433dc0cb1cdSDale Ghent #define IXGBE_RDRXCTL_RSCLLIDIS 0x00800000 /* Disable RSC compl on LLI*/ 143469b5a878SDan McDonald #define IXGBE_RDRXCTL_RSCACKC 0x02000000 /* must set 1 when RSC ena */ 143569b5a878SDan McDonald #define IXGBE_RDRXCTL_FCOE_WRFIX 0x04000000 /* must set 1 when RSC ena */ 1436dc0cb1cdSDale Ghent #define IXGBE_RDRXCTL_MBINTEN 0x10000000 1437dc0cb1cdSDale Ghent #define IXGBE_RDRXCTL_MDP_EN 0x20000000 143873cd555cSBin Tu - Sun Microsystems - Beijing China 143973cd555cSBin Tu - Sun Microsystems - Beijing China /* RQTC Bit Masks and Shifts */ 144069b5a878SDan McDonald #define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4) 144169b5a878SDan McDonald #define IXGBE_RQTC_TC0_MASK (0x7 << 0) 144269b5a878SDan McDonald #define IXGBE_RQTC_TC1_MASK (0x7 << 4) 144369b5a878SDan McDonald #define IXGBE_RQTC_TC2_MASK (0x7 << 8) 144469b5a878SDan McDonald #define IXGBE_RQTC_TC3_MASK (0x7 << 12) 144569b5a878SDan McDonald #define IXGBE_RQTC_TC4_MASK (0x7 << 16) 144669b5a878SDan McDonald #define IXGBE_RQTC_TC5_MASK (0x7 << 20) 144769b5a878SDan McDonald #define IXGBE_RQTC_TC6_MASK (0x7 << 24) 144869b5a878SDan McDonald #define IXGBE_RQTC_TC7_MASK (0x7 << 28) 144973cd555cSBin Tu - Sun Microsystems - Beijing China 145073cd555cSBin Tu - Sun Microsystems - Beijing China /* PSRTYPE.RQPL Bit masks and shift */ 145169b5a878SDan McDonald #define IXGBE_PSRTYPE_RQPL_MASK 0x7 145269b5a878SDan McDonald #define IXGBE_PSRTYPE_RQPL_SHIFT 29 14539da57d7bSbt 14549da57d7bSbt /* CTRL Bit Masks */ 145569b5a878SDan McDonald #define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Master Disable bit */ 145669b5a878SDan McDonald #define IXGBE_CTRL_LNK_RST 0x00000008 /* Link Reset. Resets everything. */ 145769b5a878SDan McDonald #define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */ 145869b5a878SDan McDonald #define IXGBE_CTRL_RST_MASK (IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST) 14599da57d7bSbt 14609da57d7bSbt /* FACTPS */ 1461dc0cb1cdSDale Ghent #define IXGBE_FACTPS_MNGCG 0x20000000 /* Manageblility Clock Gated */ 146269b5a878SDan McDonald #define IXGBE_FACTPS_LFS 0x40000000 /* LAN Function Select */ 14639da57d7bSbt 14649da57d7bSbt /* MHADD Bit Masks */ 146569b5a878SDan McDonald #define IXGBE_MHADD_MFS_MASK 0xFFFF0000 146669b5a878SDan McDonald #define IXGBE_MHADD_MFS_SHIFT 16 14679da57d7bSbt 14689da57d7bSbt /* Extended Device Control */ 146969b5a878SDan McDonald #define IXGBE_CTRL_EXT_PFRSTD 0x00004000 /* Physical Function Reset Done */ 147069b5a878SDan McDonald #define IXGBE_CTRL_EXT_NS_DIS 0x00010000 /* No Snoop disable */ 147169b5a878SDan McDonald #define IXGBE_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 147269b5a878SDan McDonald #define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ 14739da57d7bSbt 14749da57d7bSbt /* Direct Cache Access (DCA) definitions */ 147569b5a878SDan McDonald #define IXGBE_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */ 147669b5a878SDan McDonald #define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */ 147769b5a878SDan McDonald 147869b5a878SDan McDonald #define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */ 147969b5a878SDan McDonald #define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */ 148069b5a878SDan McDonald 148169b5a878SDan McDonald #define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */ 148269b5a878SDan McDonald #define IXGBE_DCA_RXCTRL_CPUID_MASK_82599 0xFF000000 /* Rx CPUID Mask */ 148369b5a878SDan McDonald #define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24 /* Rx CPUID Shift */ 148469b5a878SDan McDonald #define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* Rx Desc enable */ 148569b5a878SDan McDonald #define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* Rx Desc header ena */ 148669b5a878SDan McDonald #define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* Rx Desc payload ena */ 148769b5a878SDan McDonald #define IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* Rx rd Desc Relax Order */ 148869b5a878SDan McDonald #define IXGBE_DCA_RXCTRL_DATA_WRO_EN (1 << 13) /* Rx wr data Relax Order */ 148969b5a878SDan McDonald #define IXGBE_DCA_RXCTRL_HEAD_WRO_EN (1 << 15) /* Rx wr header RO */ 149069b5a878SDan McDonald 149169b5a878SDan McDonald #define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */ 149269b5a878SDan McDonald #define IXGBE_DCA_TXCTRL_CPUID_MASK_82599 0xFF000000 /* Tx CPUID Mask */ 149369b5a878SDan McDonald #define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24 /* Tx CPUID Shift */ 149469b5a878SDan McDonald #define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */ 149569b5a878SDan McDonald #define IXGBE_DCA_TXCTRL_DESC_RRO_EN (1 << 9) /* Tx rd Desc Relax Order */ 149669b5a878SDan McDonald #define IXGBE_DCA_TXCTRL_DESC_WRO_EN (1 << 11) /* Tx Desc writeback RO bit */ 149769b5a878SDan McDonald #define IXGBE_DCA_TXCTRL_DATA_RRO_EN (1 << 13) /* Tx rd data Relax Order */ 149869b5a878SDan McDonald #define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */ 14999da57d7bSbt 15009da57d7bSbt /* MSCA Bit Masks */ 150169b5a878SDan McDonald #define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF /* MDI Addr (new prot) */ 150269b5a878SDan McDonald #define IXGBE_MSCA_NP_ADDR_SHIFT 0 150369b5a878SDan McDonald #define IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000 /* Dev Type (new prot) */ 150469b5a878SDan McDonald #define IXGBE_MSCA_DEV_TYPE_SHIFT 16 /* Register Address (old prot */ 150569b5a878SDan McDonald #define IXGBE_MSCA_PHY_ADDR_MASK 0x03E00000 /* PHY Address mask */ 150669b5a878SDan McDonald #define IXGBE_MSCA_PHY_ADDR_SHIFT 21 /* PHY Address shift*/ 150769b5a878SDan McDonald #define IXGBE_MSCA_OP_CODE_MASK 0x0C000000 /* OP CODE mask */ 150869b5a878SDan McDonald #define IXGBE_MSCA_OP_CODE_SHIFT 26 /* OP CODE shift */ 150969b5a878SDan McDonald #define IXGBE_MSCA_ADDR_CYCLE 0x00000000 /* OP CODE 00 (addr cycle) */ 151069b5a878SDan McDonald #define IXGBE_MSCA_WRITE 0x04000000 /* OP CODE 01 (wr) */ 151169b5a878SDan McDonald #define IXGBE_MSCA_READ 0x0C000000 /* OP CODE 11 (rd) */ 151269b5a878SDan McDonald #define IXGBE_MSCA_READ_AUTOINC 0x08000000 /* OP CODE 10 (rd auto inc)*/ 151369b5a878SDan McDonald #define IXGBE_MSCA_ST_CODE_MASK 0x30000000 /* ST Code mask */ 151469b5a878SDan McDonald #define IXGBE_MSCA_ST_CODE_SHIFT 28 /* ST Code shift */ 151569b5a878SDan McDonald #define IXGBE_MSCA_NEW_PROTOCOL 0x00000000 /* ST CODE 00 (new prot) */ 151669b5a878SDan McDonald #define IXGBE_MSCA_OLD_PROTOCOL 0x10000000 /* ST CODE 01 (old prot) */ 151769b5a878SDan McDonald #define IXGBE_MSCA_MDI_COMMAND 0x40000000 /* Initiate MDI command */ 151869b5a878SDan McDonald #define IXGBE_MSCA_MDI_IN_PROG_EN 0x80000000 /* MDI in progress ena */ 15199da57d7bSbt 15209da57d7bSbt /* MSRWD bit masks */ 152169b5a878SDan McDonald #define IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF 152269b5a878SDan McDonald #define IXGBE_MSRWD_WRITE_DATA_SHIFT 0 152369b5a878SDan McDonald #define IXGBE_MSRWD_READ_DATA_MASK 0xFFFF0000 152469b5a878SDan McDonald #define IXGBE_MSRWD_READ_DATA_SHIFT 16 15259da57d7bSbt 15269da57d7bSbt /* Atlas registers */ 152769b5a878SDan McDonald #define IXGBE_ATLAS_PDN_LPBK 0x24 152869b5a878SDan McDonald #define IXGBE_ATLAS_PDN_10G 0xB 152969b5a878SDan McDonald #define IXGBE_ATLAS_PDN_1G 0xC 153069b5a878SDan McDonald #define IXGBE_ATLAS_PDN_AN 0xD 15319da57d7bSbt 15329da57d7bSbt /* Atlas bit masks */ 153369b5a878SDan McDonald #define IXGBE_ATLASCTL_WRITE_CMD 0x00010000 153469b5a878SDan McDonald #define IXGBE_ATLAS_PDN_TX_REG_EN 0x10 153569b5a878SDan McDonald #define IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0 153669b5a878SDan McDonald #define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0 153769b5a878SDan McDonald #define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0 15389da57d7bSbt 153973cd555cSBin Tu - Sun Microsystems - Beijing China /* Omer bit masks */ 154069b5a878SDan McDonald #define IXGBE_CORECTL_WRITE_CMD 0x00010000 154173cd555cSBin Tu - Sun Microsystems - Beijing China 15429da57d7bSbt /* Device Type definitions for new protocol MDIO commands */ 1543*48ed61a7SRobert Mustacchi #define IXGBE_MDIO_ZERO_DEV_TYPE 0x0 154469b5a878SDan McDonald #define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1 154569b5a878SDan McDonald #define IXGBE_MDIO_PCS_DEV_TYPE 0x3 154669b5a878SDan McDonald #define IXGBE_MDIO_PHY_XS_DEV_TYPE 0x4 154769b5a878SDan McDonald #define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7 154869b5a878SDan McDonald #define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE 0x1E /* Device 30 */ 154969b5a878SDan McDonald #define IXGBE_TWINAX_DEV 1 155069b5a878SDan McDonald 155169b5a878SDan McDonald #define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */ 155269b5a878SDan McDonald 155369b5a878SDan McDonald #define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Ctrl Reg */ 155469b5a878SDan McDonald #define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */ 155569b5a878SDan McDonald #define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */ 155669b5a878SDan McDonald #define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0-10G, 1-1G */ 155769b5a878SDan McDonald #define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018 155869b5a878SDan McDonald #define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010 155969b5a878SDan McDonald 156069b5a878SDan McDonald #define IXGBE_MDIO_AUTO_NEG_CONTROL 0x0 /* AUTO_NEG Control Reg */ 156169b5a878SDan McDonald #define IXGBE_MDIO_AUTO_NEG_STATUS 0x1 /* AUTO_NEG Status Reg */ 1562dc0cb1cdSDale Ghent #define IXGBE_MDIO_AUTO_NEG_VENDOR_STAT 0xC800 /* AUTO_NEG Vendor Status Reg */ 1563dc0cb1cdSDale Ghent #define IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM 0xCC00 /* AUTO_NEG Vendor TX Reg */ 1564dc0cb1cdSDale Ghent #define IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2 0xCC01 /* AUTO_NEG Vendor Tx Reg */ 1565dc0cb1cdSDale Ghent #define IXGBE_MDIO_AUTO_NEG_VEN_LSC 0x1 /* AUTO_NEG Vendor Tx LSC */ 156669b5a878SDan McDonald #define IXGBE_MDIO_AUTO_NEG_ADVT 0x10 /* AUTO_NEG Advt Reg */ 156769b5a878SDan McDonald #define IXGBE_MDIO_AUTO_NEG_LP 0x13 /* AUTO_NEG LP Status Reg */ 1568dc0cb1cdSDale Ghent #define IXGBE_MDIO_AUTO_NEG_EEE_ADVT 0x3C /* AUTO_NEG EEE Advt Reg */ 1569dc0cb1cdSDale Ghent #define IXGBE_AUTO_NEG_10GBASE_EEE_ADVT 0x8 /* AUTO NEG EEE 10GBaseT Advt */ 1570dc0cb1cdSDale Ghent #define IXGBE_AUTO_NEG_1000BASE_EEE_ADVT 0x4 /* AUTO NEG EEE 1000BaseT Advt */ 1571dc0cb1cdSDale Ghent #define IXGBE_AUTO_NEG_100BASE_EEE_ADVT 0x2 /* AUTO NEG EEE 100BaseT Advt */ 157269b5a878SDan McDonald #define IXGBE_MDIO_PHY_XS_CONTROL 0x0 /* PHY_XS Control Reg */ 157369b5a878SDan McDonald #define IXGBE_MDIO_PHY_XS_RESET 0x8000 /* PHY_XS Reset */ 157469b5a878SDan McDonald #define IXGBE_MDIO_PHY_ID_HIGH 0x2 /* PHY ID High Reg*/ 157569b5a878SDan McDonald #define IXGBE_MDIO_PHY_ID_LOW 0x3 /* PHY ID Low Reg*/ 157669b5a878SDan McDonald #define IXGBE_MDIO_PHY_SPEED_ABILITY 0x4 /* Speed Ability Reg */ 157769b5a878SDan McDonald #define IXGBE_MDIO_PHY_SPEED_10G 0x0001 /* 10G capable */ 157869b5a878SDan McDonald #define IXGBE_MDIO_PHY_SPEED_1G 0x0010 /* 1G capable */ 157969b5a878SDan McDonald #define IXGBE_MDIO_PHY_SPEED_100M 0x0020 /* 100M capable */ 158069b5a878SDan McDonald #define IXGBE_MDIO_PHY_EXT_ABILITY 0xB /* Ext Ability Reg */ 158169b5a878SDan McDonald #define IXGBE_MDIO_PHY_10GBASET_ABILITY 0x0004 /* 10GBaseT capable */ 158269b5a878SDan McDonald #define IXGBE_MDIO_PHY_1000BASET_ABILITY 0x0020 /* 1000BaseT capable */ 158369b5a878SDan McDonald #define IXGBE_MDIO_PHY_100BASETX_ABILITY 0x0080 /* 100BaseTX capable */ 158469b5a878SDan McDonald #define IXGBE_MDIO_PHY_SET_LOW_POWER_MODE 0x0800 /* Set low power mode */ 1585dc0cb1cdSDale Ghent #define IXGBE_AUTO_NEG_LP_STATUS 0xE820 /* AUTO NEG Rx LP Status Reg */ 1586dc0cb1cdSDale Ghent #define IXGBE_AUTO_NEG_LP_1000BASE_CAP 0x8000 /* AUTO NEG Rx LP 1000BaseT Cap */ 1587dc0cb1cdSDale Ghent #define IXGBE_AUTO_NEG_LP_10GBASE_CAP 0x0800 /* AUTO NEG Rx LP 10GBaseT Cap */ 1588dc0cb1cdSDale Ghent #define IXGBE_AUTO_NEG_10GBASET_STAT 0x0021 /* AUTO NEG 10G BaseT Stat */ 1589dc0cb1cdSDale Ghent 1590dc0cb1cdSDale Ghent #define IXGBE_MDIO_TX_VENDOR_ALARMS_3 0xCC02 /* Vendor Alarms 3 Reg */ 1591dc0cb1cdSDale Ghent #define IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK 0x3 /* PHY Reset Complete Mask */ 1592dc0cb1cdSDale Ghent #define IXGBE_MDIO_GLOBAL_RES_PR_10 0xC479 /* Global Resv Provisioning 10 Reg */ 1593dc0cb1cdSDale Ghent #define IXGBE_MDIO_POWER_UP_STALL 0x8000 /* Power Up Stall */ 1594dc0cb1cdSDale Ghent #define IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK 0xFF00 /* int std mask */ 1595dc0cb1cdSDale Ghent #define IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG 0xFC00 /* chip std int flag */ 1596dc0cb1cdSDale Ghent #define IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK 0xFF01 /* int chip-wide mask */ 1597dc0cb1cdSDale Ghent #define IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG 0xFC01 /* int chip-wide mask */ 1598dc0cb1cdSDale Ghent #define IXGBE_MDIO_GLOBAL_ALARM_1 0xCC00 /* Global alarm 1 */ 1599dc0cb1cdSDale Ghent #define IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT 0x0010 /* device fault */ 1600dc0cb1cdSDale Ghent #define IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL 0x4000 /* high temp failure */ 1601dc0cb1cdSDale Ghent #define IXGBE_MDIO_GLOBAL_FAULT_MSG 0xC850 /* Global Fault Message */ 1602dc0cb1cdSDale Ghent #define IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP 0x8007 /* high temp failure */ 1603dc0cb1cdSDale Ghent #define IXGBE_MDIO_GLOBAL_INT_MASK 0xD400 /* Global int mask */ 1604dc0cb1cdSDale Ghent #define IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN 0x1000 /* autoneg vendor alarm int enable */ 1605dc0cb1cdSDale Ghent #define IXGBE_MDIO_GLOBAL_ALARM_1_INT 0x4 /* int in Global alarm 1 */ 1606dc0cb1cdSDale Ghent #define IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN 0x1 /* vendor alarm int enable */ 1607dc0cb1cdSDale Ghent #define IXGBE_MDIO_GLOBAL_STD_ALM2_INT 0x200 /* vendor alarm2 int mask */ 1608dc0cb1cdSDale Ghent #define IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN 0x4000 /* int high temp enable */ 1609*48ed61a7SRobert Mustacchi #define IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN 0x0010 /* int dev fault enable */ 161069b5a878SDan McDonald #define IXGBE_MDIO_PMA_PMD_CONTROL_ADDR 0x0000 /* PMA/PMD Control Reg */ 161169b5a878SDan McDonald #define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */ 161269b5a878SDan McDonald #define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */ 161369b5a878SDan McDonald #define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */ 1614dc0cb1cdSDale Ghent #define IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK 0xD401 /* PHY TX Vendor LASI */ 1615dc0cb1cdSDale Ghent #define IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN 0x1 /* PHY TX Vendor LASI enable */ 1616dc0cb1cdSDale Ghent #define IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR 0x9 /* Standard Transmit Dis Reg */ 1617dc0cb1cdSDale Ghent #define IXGBE_MDIO_PMD_GLOBAL_TX_DISABLE 0x0001 /* PMD Global Transmit Dis */ 1618dc0cb1cdSDale Ghent 1619dc0cb1cdSDale Ghent #define IXGBE_PCRC8ECL 0x0E810 /* PCR CRC-8 Error Count Lo */ 1620dc0cb1cdSDale Ghent #define IXGBE_PCRC8ECH 0x0E811 /* PCR CRC-8 Error Count Hi */ 1621dc0cb1cdSDale Ghent #define IXGBE_PCRC8ECH_MASK 0x1F 1622dc0cb1cdSDale Ghent #define IXGBE_LDPCECL 0x0E820 /* PCR Uncorrected Error Count Lo */ 1623dc0cb1cdSDale Ghent #define IXGBE_LDPCECH 0x0E821 /* PCR Uncorrected Error Count Hi */ 162413740cb2SPaul Guo 16259da57d7bSbt /* MII clause 22/28 definitions */ 162669b5a878SDan McDonald #define IXGBE_MDIO_PHY_LOW_POWER_MODE 0x0800 162763b3bba8SJerry Jelinek 1628dc0cb1cdSDale Ghent #define IXGBE_MDIO_XENPAK_LASI_STATUS 0x9005 /* XENPAK LASI Status register*/ 1629dc0cb1cdSDale Ghent #define IXGBE_XENPAK_LASI_LINK_STATUS_ALARM 0x1 /* Link Status Alarm change */ 1630dc0cb1cdSDale Ghent 1631dc0cb1cdSDale Ghent #define IXGBE_MDIO_AUTO_NEG_LINK_STATUS 0x4 /* Indicates if link is up */ 1632dc0cb1cdSDale Ghent 1633dc0cb1cdSDale Ghent #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK 0x7 /* Speed/Duplex Mask */ 1634dc0cb1cdSDale Ghent #define IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK 0x6 /* Speed Mask */ 1635dc0cb1cdSDale Ghent #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_HALF 0x0 /* 10Mb/s Half Duplex */ 1636dc0cb1cdSDale Ghent #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_FULL 0x1 /* 10Mb/s Full Duplex */ 1637dc0cb1cdSDale Ghent #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_HALF 0x2 /* 100Mb/s Half Duplex */ 1638dc0cb1cdSDale Ghent #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_FULL 0x3 /* 100Mb/s Full Duplex */ 1639dc0cb1cdSDale Ghent #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_HALF 0x4 /* 1Gb/s Half Duplex */ 1640dc0cb1cdSDale Ghent #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL 0x5 /* 1Gb/s Full Duplex */ 1641dc0cb1cdSDale Ghent #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_HALF 0x6 /* 10Gb/s Half Duplex */ 1642dc0cb1cdSDale Ghent #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL 0x7 /* 10Gb/s Full Duplex */ 1643dc0cb1cdSDale Ghent #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB 0x4 /* 1Gb/s */ 1644dc0cb1cdSDale Ghent #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB 0x6 /* 10Gb/s */ 1645dc0cb1cdSDale Ghent 164669b5a878SDan McDonald #define IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG 0x20 /* 10G Control Reg */ 164763b3bba8SJerry Jelinek #define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */ 164869b5a878SDan McDonald #define IXGBE_MII_AUTONEG_XNP_TX_REG 0x17 /* 1G XNP Transmit */ 164969b5a878SDan McDonald #define IXGBE_MII_AUTONEG_ADVERTISE_REG 0x10 /* 100M Advertisement */ 165069b5a878SDan McDonald #define IXGBE_MII_10GBASE_T_ADVERTISE 0x1000 /* full duplex, bit:12*/ 165169b5a878SDan McDonald #define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX 0x4000 /* full duplex, bit:14*/ 165269b5a878SDan McDonald #define IXGBE_MII_1GBASE_T_ADVERTISE 0x8000 /* full duplex, bit:15*/ 1653dc0cb1cdSDale Ghent #define IXGBE_MII_2_5GBASE_T_ADVERTISE 0x0400 1654dc0cb1cdSDale Ghent #define IXGBE_MII_5GBASE_T_ADVERTISE 0x0800 165569b5a878SDan McDonald #define IXGBE_MII_100BASE_T_ADVERTISE 0x0100 /* full duplex, bit:8 */ 165669b5a878SDan McDonald #define IXGBE_MII_100BASE_T_ADVERTISE_HALF 0x0080 /* half duplex, bit:7 */ 165769b5a878SDan McDonald #define IXGBE_MII_RESTART 0x200 165869b5a878SDan McDonald #define IXGBE_MII_AUTONEG_COMPLETE 0x20 165969b5a878SDan McDonald #define IXGBE_MII_AUTONEG_LINK_UP 0x04 166069b5a878SDan McDonald #define IXGBE_MII_AUTONEG_REG 0x0 166169b5a878SDan McDonald 166269b5a878SDan McDonald #define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0 166369b5a878SDan McDonald #define IXGBE_MAX_PHY_ADDR 32 166463b3bba8SJerry Jelinek 166563b3bba8SJerry Jelinek /* PHY IDs*/ 166669b5a878SDan McDonald #define TN1010_PHY_ID 0x00A19410 166769b5a878SDan McDonald #define TNX_FW_REV 0xB 166869b5a878SDan McDonald #define X540_PHY_ID 0x01540200 1669dc0cb1cdSDale Ghent #define X550_PHY_ID2 0x01540223 1670dc0cb1cdSDale Ghent #define X550_PHY_ID3 0x01540221 1671dc0cb1cdSDale Ghent #define X557_PHY_ID 0x01540240 1672*48ed61a7SRobert Mustacchi #define X557_PHY_ID2 0x01540250 167369b5a878SDan McDonald #define AQ_FW_REV 0x20 167469b5a878SDan McDonald #define QT2022_PHY_ID 0x0043A400 167569b5a878SDan McDonald #define ATH_PHY_ID 0x03429050 167613740cb2SPaul Guo 167713740cb2SPaul Guo /* PHY Types */ 1678*48ed61a7SRobert Mustacchi #define IXGBE_M88E1500_E_PHY_ID 0x01410DD0 1679*48ed61a7SRobert Mustacchi #define IXGBE_M88E1543_E_PHY_ID 0x01410EA0 168013740cb2SPaul Guo 168113740cb2SPaul Guo /* Special PHY Init Routine */ 168269b5a878SDan McDonald #define IXGBE_PHY_INIT_OFFSET_NL 0x002B 168369b5a878SDan McDonald #define IXGBE_PHY_INIT_END_NL 0xFFFF 168469b5a878SDan McDonald #define IXGBE_CONTROL_MASK_NL 0xF000 168569b5a878SDan McDonald #define IXGBE_DATA_MASK_NL 0x0FFF 168669b5a878SDan McDonald #define IXGBE_CONTROL_SHIFT_NL 12 168769b5a878SDan McDonald #define IXGBE_DELAY_NL 0 168869b5a878SDan McDonald #define IXGBE_DATA_NL 1 168969b5a878SDan McDonald #define IXGBE_CONTROL_NL 0x000F 169069b5a878SDan McDonald #define IXGBE_CONTROL_EOL_NL 0x0FFF 169169b5a878SDan McDonald #define IXGBE_CONTROL_SOL_NL 0x0000 16929da57d7bSbt 16939da57d7bSbt /* General purpose Interrupt Enable */ 169469b5a878SDan McDonald #define IXGBE_SDP0_GPIEN 0x00000001 /* SDP0 */ 169569b5a878SDan McDonald #define IXGBE_SDP1_GPIEN 0x00000002 /* SDP1 */ 169669b5a878SDan McDonald #define IXGBE_SDP2_GPIEN 0x00000004 /* SDP2 */ 1697dc0cb1cdSDale Ghent #define IXGBE_SDP0_GPIEN_X540 0x00000002 /* SDP0 on X540 and X550 */ 1698dc0cb1cdSDale Ghent #define IXGBE_SDP1_GPIEN_X540 0x00000004 /* SDP1 on X540 and X550 */ 1699dc0cb1cdSDale Ghent #define IXGBE_SDP2_GPIEN_X540 0x00000008 /* SDP2 on X540 and X550 */ 1700dc0cb1cdSDale Ghent #define IXGBE_SDP0_GPIEN_X550 IXGBE_SDP0_GPIEN_X540 1701dc0cb1cdSDale Ghent #define IXGBE_SDP1_GPIEN_X550 IXGBE_SDP1_GPIEN_X540 1702dc0cb1cdSDale Ghent #define IXGBE_SDP2_GPIEN_X550 IXGBE_SDP2_GPIEN_X540 1703dc0cb1cdSDale Ghent #define IXGBE_SDP0_GPIEN_X550EM_x IXGBE_SDP0_GPIEN_X540 1704dc0cb1cdSDale Ghent #define IXGBE_SDP1_GPIEN_X550EM_x IXGBE_SDP1_GPIEN_X540 1705dc0cb1cdSDale Ghent #define IXGBE_SDP2_GPIEN_X550EM_x IXGBE_SDP2_GPIEN_X540 1706*48ed61a7SRobert Mustacchi #define IXGBE_SDP0_GPIEN_X550EM_a IXGBE_SDP0_GPIEN_X540 1707*48ed61a7SRobert Mustacchi #define IXGBE_SDP1_GPIEN_X550EM_a IXGBE_SDP1_GPIEN_X540 1708*48ed61a7SRobert Mustacchi #define IXGBE_SDP2_GPIEN_X550EM_a IXGBE_SDP2_GPIEN_X540 1709dc0cb1cdSDale Ghent #define IXGBE_SDP0_GPIEN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SDP0_GPIEN) 1710dc0cb1cdSDale Ghent #define IXGBE_SDP1_GPIEN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SDP1_GPIEN) 1711dc0cb1cdSDale Ghent #define IXGBE_SDP2_GPIEN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SDP2_GPIEN) 1712dc0cb1cdSDale Ghent 171369b5a878SDan McDonald #define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */ 171469b5a878SDan McDonald #define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */ 171569b5a878SDan McDonald #define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */ 171669b5a878SDan McDonald #define IXGBE_GPIE_EIAME 0x40000000 171769b5a878SDan McDonald #define IXGBE_GPIE_PBA_SUPPORT 0x80000000 171869b5a878SDan McDonald #define IXGBE_GPIE_RSC_DELAY_SHIFT 11 171969b5a878SDan McDonald #define IXGBE_GPIE_VTMODE_MASK 0x0000C000 /* VT Mode Mask */ 172069b5a878SDan McDonald #define IXGBE_GPIE_VTMODE_16 0x00004000 /* 16 VFs 8 queues per VF */ 172169b5a878SDan McDonald #define IXGBE_GPIE_VTMODE_32 0x00008000 /* 32 VFs 4 queues per VF */ 172269b5a878SDan McDonald #define IXGBE_GPIE_VTMODE_64 0x0000C000 /* 64 VFs 2 queues per VF */ 172369b5a878SDan McDonald 172469b5a878SDan McDonald /* Packet Buffer Initialization */ 172569b5a878SDan McDonald #define IXGBE_MAX_PACKET_BUFFERS 8 172669b5a878SDan McDonald 172769b5a878SDan McDonald #define IXGBE_TXPBSIZE_20KB 0x00005000 /* 20KB Packet Buffer */ 172869b5a878SDan McDonald #define IXGBE_TXPBSIZE_40KB 0x0000A000 /* 40KB Packet Buffer */ 172969b5a878SDan McDonald #define IXGBE_RXPBSIZE_48KB 0x0000C000 /* 48KB Packet Buffer */ 173069b5a878SDan McDonald #define IXGBE_RXPBSIZE_64KB 0x00010000 /* 64KB Packet Buffer */ 173169b5a878SDan McDonald #define IXGBE_RXPBSIZE_80KB 0x00014000 /* 80KB Packet Buffer */ 173269b5a878SDan McDonald #define IXGBE_RXPBSIZE_128KB 0x00020000 /* 128KB Packet Buffer */ 173369b5a878SDan McDonald #define IXGBE_RXPBSIZE_MAX 0x00080000 /* 512KB Packet Buffer */ 173469b5a878SDan McDonald #define IXGBE_TXPBSIZE_MAX 0x00028000 /* 160KB Packet Buffer */ 173569b5a878SDan McDonald 173669b5a878SDan McDonald #define IXGBE_TXPKT_SIZE_MAX 0xA /* Max Tx Packet size */ 173769b5a878SDan McDonald #define IXGBE_MAX_PB 8 173869b5a878SDan McDonald 173969b5a878SDan McDonald /* Packet buffer allocation strategies */ 174069b5a878SDan McDonald enum { 174169b5a878SDan McDonald PBA_STRATEGY_EQUAL = 0, /* Distribute PB space equally */ 174269b5a878SDan McDonald #define PBA_STRATEGY_EQUAL PBA_STRATEGY_EQUAL 174369b5a878SDan McDonald PBA_STRATEGY_WEIGHTED = 1, /* Weight front half of TCs */ 174469b5a878SDan McDonald #define PBA_STRATEGY_WEIGHTED PBA_STRATEGY_WEIGHTED 174569b5a878SDan McDonald }; 17469da57d7bSbt 17479da57d7bSbt /* Transmit Flow Control status */ 174869b5a878SDan McDonald #define IXGBE_TFCS_TXOFF 0x00000001 174969b5a878SDan McDonald #define IXGBE_TFCS_TXOFF0 0x00000100 175069b5a878SDan McDonald #define IXGBE_TFCS_TXOFF1 0x00000200 175169b5a878SDan McDonald #define IXGBE_TFCS_TXOFF2 0x00000400 175269b5a878SDan McDonald #define IXGBE_TFCS_TXOFF3 0x00000800 175369b5a878SDan McDonald #define IXGBE_TFCS_TXOFF4 0x00001000 175469b5a878SDan McDonald #define IXGBE_TFCS_TXOFF5 0x00002000 175569b5a878SDan McDonald #define IXGBE_TFCS_TXOFF6 0x00004000 175669b5a878SDan McDonald #define IXGBE_TFCS_TXOFF7 0x00008000 17579da57d7bSbt 17589da57d7bSbt /* TCP Timer */ 175969b5a878SDan McDonald #define IXGBE_TCPTIMER_KS 0x00000100 176069b5a878SDan McDonald #define IXGBE_TCPTIMER_COUNT_ENABLE 0x00000200 176169b5a878SDan McDonald #define IXGBE_TCPTIMER_COUNT_FINISH 0x00000400 176269b5a878SDan McDonald #define IXGBE_TCPTIMER_LOOP 0x00000800 176369b5a878SDan McDonald #define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF 17649da57d7bSbt 17659da57d7bSbt /* HLREG0 Bit Masks */ 176669b5a878SDan McDonald #define IXGBE_HLREG0_TXCRCEN 0x00000001 /* bit 0 */ 176769b5a878SDan McDonald #define IXGBE_HLREG0_RXCRCSTRP 0x00000002 /* bit 1 */ 176869b5a878SDan McDonald #define IXGBE_HLREG0_JUMBOEN 0x00000004 /* bit 2 */ 176969b5a878SDan McDonald #define IXGBE_HLREG0_TXPADEN 0x00000400 /* bit 10 */ 177069b5a878SDan McDonald #define IXGBE_HLREG0_TXPAUSEEN 0x00001000 /* bit 12 */ 177169b5a878SDan McDonald #define IXGBE_HLREG0_RXPAUSEEN 0x00004000 /* bit 14 */ 177269b5a878SDan McDonald #define IXGBE_HLREG0_LPBK 0x00008000 /* bit 15 */ 177369b5a878SDan McDonald #define IXGBE_HLREG0_MDCSPD 0x00010000 /* bit 16 */ 177469b5a878SDan McDonald #define IXGBE_HLREG0_CONTMDC 0x00020000 /* bit 17 */ 177569b5a878SDan McDonald #define IXGBE_HLREG0_CTRLFLTR 0x00040000 /* bit 18 */ 177669b5a878SDan McDonald #define IXGBE_HLREG0_PREPEND 0x00F00000 /* bits 20-23 */ 177769b5a878SDan McDonald #define IXGBE_HLREG0_PRIPAUSEEN 0x01000000 /* bit 24 */ 177869b5a878SDan McDonald #define IXGBE_HLREG0_RXPAUSERECDA 0x06000000 /* bits 25-26 */ 177969b5a878SDan McDonald #define IXGBE_HLREG0_RXLNGTHERREN 0x08000000 /* bit 27 */ 178069b5a878SDan McDonald #define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000 /* bit 28 */ 17819da57d7bSbt 17829da57d7bSbt /* VMD_CTL bitmasks */ 178369b5a878SDan McDonald #define IXGBE_VMD_CTL_VMDQ_EN 0x00000001 178469b5a878SDan McDonald #define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002 17859da57d7bSbt 178673cd555cSBin Tu - Sun Microsystems - Beijing China /* VT_CTL bitmasks */ 178769b5a878SDan McDonald #define IXGBE_VT_CTL_DIS_DEFPL 0x20000000 /* disable default pool */ 178869b5a878SDan McDonald #define IXGBE_VT_CTL_REPLEN 0x40000000 /* replication enabled */ 178969b5a878SDan McDonald #define IXGBE_VT_CTL_VT_ENABLE 0x00000001 /* Enable VT Mode */ 179069b5a878SDan McDonald #define IXGBE_VT_CTL_POOL_SHIFT 7 179169b5a878SDan McDonald #define IXGBE_VT_CTL_POOL_MASK (0x3F << IXGBE_VT_CTL_POOL_SHIFT) 179273cd555cSBin Tu - Sun Microsystems - Beijing China 179373cd555cSBin Tu - Sun Microsystems - Beijing China /* VMOLR bitmasks */ 1794*48ed61a7SRobert Mustacchi #define IXGBE_VMOLR_UPE 0x00400000 /* unicast promiscuous */ 1795*48ed61a7SRobert Mustacchi #define IXGBE_VMOLR_VPE 0x00800000 /* VLAN promiscuous */ 179669b5a878SDan McDonald #define IXGBE_VMOLR_AUPE 0x01000000 /* accept untagged packets */ 179769b5a878SDan McDonald #define IXGBE_VMOLR_ROMPE 0x02000000 /* accept packets in MTA tbl */ 179869b5a878SDan McDonald #define IXGBE_VMOLR_ROPE 0x04000000 /* accept packets in UC tbl */ 179969b5a878SDan McDonald #define IXGBE_VMOLR_BAM 0x08000000 /* accept broadcast packets */ 180069b5a878SDan McDonald #define IXGBE_VMOLR_MPE 0x10000000 /* multicast promiscuous */ 180173cd555cSBin Tu - Sun Microsystems - Beijing China 180273cd555cSBin Tu - Sun Microsystems - Beijing China /* VFRE bitmask */ 180369b5a878SDan McDonald #define IXGBE_VFRE_ENABLE_ALL 0xFFFFFFFF 180473cd555cSBin Tu - Sun Microsystems - Beijing China 180569b5a878SDan McDonald #define IXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */ 1806185c5677SPaul Guo 18079da57d7bSbt /* RDHMPN and TDHMPN bitmasks */ 180869b5a878SDan McDonald #define IXGBE_RDHMPN_RDICADDR 0x007FF800 180969b5a878SDan McDonald #define IXGBE_RDHMPN_RDICRDREQ 0x00800000 181069b5a878SDan McDonald #define IXGBE_RDHMPN_RDICADDR_SHIFT 11 181169b5a878SDan McDonald #define IXGBE_TDHMPN_TDICADDR 0x003FF800 181269b5a878SDan McDonald #define IXGBE_TDHMPN_TDICRDREQ 0x00800000 181369b5a878SDan McDonald #define IXGBE_TDHMPN_TDICADDR_SHIFT 11 181469b5a878SDan McDonald 181569b5a878SDan McDonald #define IXGBE_RDMAM_MEM_SEL_SHIFT 13 181669b5a878SDan McDonald #define IXGBE_RDMAM_DWORD_SHIFT 9 181769b5a878SDan McDonald #define IXGBE_RDMAM_DESC_COMP_FIFO 1 181869b5a878SDan McDonald #define IXGBE_RDMAM_DFC_CMD_FIFO 2 181969b5a878SDan McDonald #define IXGBE_RDMAM_RSC_HEADER_ADDR 3 182069b5a878SDan McDonald #define IXGBE_RDMAM_TCN_STATUS_RAM 4 182169b5a878SDan McDonald #define IXGBE_RDMAM_WB_COLL_FIFO 5 182269b5a878SDan McDonald #define IXGBE_RDMAM_QSC_CNT_RAM 6 182369b5a878SDan McDonald #define IXGBE_RDMAM_QSC_FCOE_RAM 7 182469b5a878SDan McDonald #define IXGBE_RDMAM_QSC_QUEUE_CNT 8 182569b5a878SDan McDonald #define IXGBE_RDMAM_QSC_QUEUE_RAM 0xA 182669b5a878SDan McDonald #define IXGBE_RDMAM_QSC_RSC_RAM 0xB 182769b5a878SDan McDonald #define IXGBE_RDMAM_DESC_COM_FIFO_RANGE 135 182869b5a878SDan McDonald #define IXGBE_RDMAM_DESC_COM_FIFO_COUNT 4 182969b5a878SDan McDonald #define IXGBE_RDMAM_DFC_CMD_FIFO_RANGE 48 183069b5a878SDan McDonald #define IXGBE_RDMAM_DFC_CMD_FIFO_COUNT 7 183169b5a878SDan McDonald #define IXGBE_RDMAM_RSC_HEADER_ADDR_RANGE 32 183269b5a878SDan McDonald #define IXGBE_RDMAM_RSC_HEADER_ADDR_COUNT 4 183369b5a878SDan McDonald #define IXGBE_RDMAM_TCN_STATUS_RAM_RANGE 256 183469b5a878SDan McDonald #define IXGBE_RDMAM_TCN_STATUS_RAM_COUNT 9 183569b5a878SDan McDonald #define IXGBE_RDMAM_WB_COLL_FIFO_RANGE 8 183669b5a878SDan McDonald #define IXGBE_RDMAM_WB_COLL_FIFO_COUNT 4 183769b5a878SDan McDonald #define IXGBE_RDMAM_QSC_CNT_RAM_RANGE 64 183869b5a878SDan McDonald #define IXGBE_RDMAM_QSC_CNT_RAM_COUNT 4 183969b5a878SDan McDonald #define IXGBE_RDMAM_QSC_FCOE_RAM_RANGE 512 184069b5a878SDan McDonald #define IXGBE_RDMAM_QSC_FCOE_RAM_COUNT 5 184169b5a878SDan McDonald #define IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE 32 184269b5a878SDan McDonald #define IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT 4 184369b5a878SDan McDonald #define IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE 128 184469b5a878SDan McDonald #define IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT 8 184569b5a878SDan McDonald #define IXGBE_RDMAM_QSC_RSC_RAM_RANGE 32 184669b5a878SDan McDonald #define IXGBE_RDMAM_QSC_RSC_RAM_COUNT 8 184769b5a878SDan McDonald 184869b5a878SDan McDonald #define IXGBE_TXDESCIC_READY 0x80000000 184973cd555cSBin Tu - Sun Microsystems - Beijing China 18509da57d7bSbt /* Receive Checksum Control */ 185169b5a878SDan McDonald #define IXGBE_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ 185269b5a878SDan McDonald #define IXGBE_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 18539da57d7bSbt 18549da57d7bSbt /* FCRTL Bit Masks */ 185569b5a878SDan McDonald #define IXGBE_FCRTL_XONE 0x80000000 /* XON enable */ 185669b5a878SDan McDonald #define IXGBE_FCRTH_FCEN 0x80000000 /* Packet buffer fc enable */ 18579da57d7bSbt 185863b3bba8SJerry Jelinek /* PAP bit masks*/ 185969b5a878SDan McDonald #define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */ 18609da57d7bSbt 18619da57d7bSbt /* RMCS Bit Masks */ 186269b5a878SDan McDonald #define IXGBE_RMCS_RRM 0x00000002 /* Rx Recycle Mode enable */ 18639da57d7bSbt /* Receive Arbitration Control: 0 Round Robin, 1 DFP */ 186469b5a878SDan McDonald #define IXGBE_RMCS_RAC 0x00000004 186569b5a878SDan McDonald /* Deficit Fixed Prio ena */ 186669b5a878SDan McDonald #define IXGBE_RMCS_DFP IXGBE_RMCS_RAC 186769b5a878SDan McDonald #define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority FC ena */ 186869b5a878SDan McDonald #define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority FC ena */ 186969b5a878SDan McDonald #define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */ 18709da57d7bSbt 187173cd555cSBin Tu - Sun Microsystems - Beijing China /* FCCFG Bit Masks */ 187269b5a878SDan McDonald #define IXGBE_FCCFG_TFCE_802_3X 0x00000008 /* Tx link FC enable */ 187369b5a878SDan McDonald #define IXGBE_FCCFG_TFCE_PRIORITY 0x00000010 /* Tx priority FC enable */ 18749da57d7bSbt 18759da57d7bSbt /* Interrupt register bitmasks */ 18769da57d7bSbt 18779da57d7bSbt /* Extended Interrupt Cause Read */ 187869b5a878SDan McDonald #define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */ 187969b5a878SDan McDonald #define IXGBE_EICR_FLOW_DIR 0x00010000 /* FDir Exception */ 188069b5a878SDan McDonald #define IXGBE_EICR_RX_MISS 0x00020000 /* Packet Buffer Overrun */ 188169b5a878SDan McDonald #define IXGBE_EICR_PCI 0x00040000 /* PCI Exception */ 188269b5a878SDan McDonald #define IXGBE_EICR_MAILBOX 0x00080000 /* VF to PF Mailbox Interrupt */ 188369b5a878SDan McDonald #define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */ 188469b5a878SDan McDonald #define IXGBE_EICR_LINKSEC 0x00200000 /* PN Threshold */ 188569b5a878SDan McDonald #define IXGBE_EICR_MNG 0x00400000 /* Manageability Event Interrupt */ 188669b5a878SDan McDonald #define IXGBE_EICR_TS 0x00800000 /* Thermal Sensor Event */ 188769b5a878SDan McDonald #define IXGBE_EICR_TIMESYNC 0x01000000 /* Timesync Event */ 188869b5a878SDan McDonald #define IXGBE_EICR_GPI_SDP0 0x01000000 /* Gen Purpose Interrupt on SDP0 */ 188969b5a878SDan McDonald #define IXGBE_EICR_GPI_SDP1 0x02000000 /* Gen Purpose Interrupt on SDP1 */ 189069b5a878SDan McDonald #define IXGBE_EICR_GPI_SDP2 0x04000000 /* Gen Purpose Interrupt on SDP2 */ 189169b5a878SDan McDonald #define IXGBE_EICR_ECC 0x10000000 /* ECC Error */ 1892dc0cb1cdSDale Ghent #define IXGBE_EICR_GPI_SDP0_X540 0x02000000 /* Gen Purpose Interrupt on SDP0 */ 1893dc0cb1cdSDale Ghent #define IXGBE_EICR_GPI_SDP1_X540 0x04000000 /* Gen Purpose Interrupt on SDP1 */ 1894dc0cb1cdSDale Ghent #define IXGBE_EICR_GPI_SDP2_X540 0x08000000 /* Gen Purpose Interrupt on SDP2 */ 1895dc0cb1cdSDale Ghent #define IXGBE_EICR_GPI_SDP0_X550 IXGBE_EICR_GPI_SDP0_X540 1896dc0cb1cdSDale Ghent #define IXGBE_EICR_GPI_SDP1_X550 IXGBE_EICR_GPI_SDP1_X540 1897dc0cb1cdSDale Ghent #define IXGBE_EICR_GPI_SDP2_X550 IXGBE_EICR_GPI_SDP2_X540 1898dc0cb1cdSDale Ghent #define IXGBE_EICR_GPI_SDP0_X550EM_x IXGBE_EICR_GPI_SDP0_X540 1899dc0cb1cdSDale Ghent #define IXGBE_EICR_GPI_SDP1_X550EM_x IXGBE_EICR_GPI_SDP1_X540 1900dc0cb1cdSDale Ghent #define IXGBE_EICR_GPI_SDP2_X550EM_x IXGBE_EICR_GPI_SDP2_X540 1901*48ed61a7SRobert Mustacchi #define IXGBE_EICR_GPI_SDP0_X550EM_a IXGBE_EICR_GPI_SDP0_X540 1902*48ed61a7SRobert Mustacchi #define IXGBE_EICR_GPI_SDP1_X550EM_a IXGBE_EICR_GPI_SDP1_X540 1903*48ed61a7SRobert Mustacchi #define IXGBE_EICR_GPI_SDP2_X550EM_a IXGBE_EICR_GPI_SDP2_X540 1904dc0cb1cdSDale Ghent #define IXGBE_EICR_GPI_SDP0_BY_MAC(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP0) 1905dc0cb1cdSDale Ghent #define IXGBE_EICR_GPI_SDP1_BY_MAC(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP1) 1906dc0cb1cdSDale Ghent #define IXGBE_EICR_GPI_SDP2_BY_MAC(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP2) 1907dc0cb1cdSDale Ghent 190869b5a878SDan McDonald #define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */ 190969b5a878SDan McDonald #define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */ 191069b5a878SDan McDonald #define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */ 191169b5a878SDan McDonald #define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ 19129da57d7bSbt 19139da57d7bSbt /* Extended Interrupt Cause Set */ 191469b5a878SDan McDonald #define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 191569b5a878SDan McDonald #define IXGBE_EICS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */ 191669b5a878SDan McDonald #define IXGBE_EICS_RX_MISS IXGBE_EICR_RX_MISS /* Pkt Buffer Overrun */ 191769b5a878SDan McDonald #define IXGBE_EICS_PCI IXGBE_EICR_PCI /* PCI Exception */ 191869b5a878SDan McDonald #define IXGBE_EICS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */ 191969b5a878SDan McDonald #define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */ 192069b5a878SDan McDonald #define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 192169b5a878SDan McDonald #define IXGBE_EICS_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */ 192269b5a878SDan McDonald #define IXGBE_EICS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */ 192369b5a878SDan McDonald #define IXGBE_EICS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */ 192469b5a878SDan McDonald #define IXGBE_EICS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */ 192569b5a878SDan McDonald #define IXGBE_EICS_ECC IXGBE_EICR_ECC /* ECC Error */ 1926dc0cb1cdSDale Ghent #define IXGBE_EICS_GPI_SDP0_BY_MAC(_hw) IXGBE_EICR_GPI_SDP0_BY_MAC(_hw) 1927dc0cb1cdSDale Ghent #define IXGBE_EICS_GPI_SDP1_BY_MAC(_hw) IXGBE_EICR_GPI_SDP1_BY_MAC(_hw) 1928dc0cb1cdSDale Ghent #define IXGBE_EICS_GPI_SDP2_BY_MAC(_hw) IXGBE_EICR_GPI_SDP2_BY_MAC(_hw) 192969b5a878SDan McDonald #define IXGBE_EICS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ 193069b5a878SDan McDonald #define IXGBE_EICS_DHER IXGBE_EICR_DHER /* Desc Handler Error */ 193169b5a878SDan McDonald #define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 193269b5a878SDan McDonald #define IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ 19339da57d7bSbt 19349da57d7bSbt /* Extended Interrupt Mask Set */ 193569b5a878SDan McDonald #define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 193669b5a878SDan McDonald #define IXGBE_EIMS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */ 193769b5a878SDan McDonald #define IXGBE_EIMS_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */ 193869b5a878SDan McDonald #define IXGBE_EIMS_PCI IXGBE_EICR_PCI /* PCI Exception */ 193969b5a878SDan McDonald #define IXGBE_EIMS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */ 194069b5a878SDan McDonald #define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */ 194169b5a878SDan McDonald #define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 194269b5a878SDan McDonald #define IXGBE_EIMS_TS IXGBE_EICR_TS /* Thermal Sensor Event */ 194369b5a878SDan McDonald #define IXGBE_EIMS_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */ 194469b5a878SDan McDonald #define IXGBE_EIMS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */ 194569b5a878SDan McDonald #define IXGBE_EIMS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */ 194669b5a878SDan McDonald #define IXGBE_EIMS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */ 194769b5a878SDan McDonald #define IXGBE_EIMS_ECC IXGBE_EICR_ECC /* ECC Error */ 1948dc0cb1cdSDale Ghent #define IXGBE_EIMS_GPI_SDP0_BY_MAC(_hw) IXGBE_EICR_GPI_SDP0_BY_MAC(_hw) 1949dc0cb1cdSDale Ghent #define IXGBE_EIMS_GPI_SDP1_BY_MAC(_hw) IXGBE_EICR_GPI_SDP1_BY_MAC(_hw) 1950dc0cb1cdSDale Ghent #define IXGBE_EIMS_GPI_SDP2_BY_MAC(_hw) IXGBE_EICR_GPI_SDP2_BY_MAC(_hw) 195169b5a878SDan McDonald #define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ 195269b5a878SDan McDonald #define IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */ 195369b5a878SDan McDonald #define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 195469b5a878SDan McDonald #define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ 19559da57d7bSbt 19569da57d7bSbt /* Extended Interrupt Mask Clear */ 195769b5a878SDan McDonald #define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 195869b5a878SDan McDonald #define IXGBE_EIMC_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */ 195969b5a878SDan McDonald #define IXGBE_EIMC_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */ 196069b5a878SDan McDonald #define IXGBE_EIMC_PCI IXGBE_EICR_PCI /* PCI Exception */ 196169b5a878SDan McDonald #define IXGBE_EIMC_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */ 196269b5a878SDan McDonald #define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */ 196369b5a878SDan McDonald #define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 196469b5a878SDan McDonald #define IXGBE_EIMC_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */ 196569b5a878SDan McDonald #define IXGBE_EIMC_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */ 196669b5a878SDan McDonald #define IXGBE_EIMC_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */ 196769b5a878SDan McDonald #define IXGBE_EIMC_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */ 196869b5a878SDan McDonald #define IXGBE_EIMC_ECC IXGBE_EICR_ECC /* ECC Error */ 1969dc0cb1cdSDale Ghent #define IXGBE_EIMC_GPI_SDP0_BY_MAC(_hw) IXGBE_EICR_GPI_SDP0_BY_MAC(_hw) 1970dc0cb1cdSDale Ghent #define IXGBE_EIMC_GPI_SDP1_BY_MAC(_hw) IXGBE_EICR_GPI_SDP1_BY_MAC(_hw) 1971dc0cb1cdSDale Ghent #define IXGBE_EIMC_GPI_SDP2_BY_MAC(_hw) IXGBE_EICR_GPI_SDP2_BY_MAC(_hw) 197269b5a878SDan McDonald #define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ 197369b5a878SDan McDonald #define IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Err */ 197469b5a878SDan McDonald #define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 197569b5a878SDan McDonald #define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ 197663b3bba8SJerry Jelinek 197763b3bba8SJerry Jelinek #define IXGBE_EIMS_ENABLE_MASK ( \ 197869b5a878SDan McDonald IXGBE_EIMS_RTX_QUEUE | \ 197969b5a878SDan McDonald IXGBE_EIMS_LSC | \ 198069b5a878SDan McDonald IXGBE_EIMS_TCP_TIMER | \ 198169b5a878SDan McDonald IXGBE_EIMS_OTHER) 19829da57d7bSbt 19839da57d7bSbt /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */ 198469b5a878SDan McDonald #define IXGBE_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */ 198569b5a878SDan McDonald #define IXGBE_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */ 198669b5a878SDan McDonald #define IXGBE_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */ 198769b5a878SDan McDonald #define IXGBE_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */ 198869b5a878SDan McDonald #define IXGBE_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */ 198969b5a878SDan McDonald #define IXGBE_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */ 199069b5a878SDan McDonald #define IXGBE_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */ 199169b5a878SDan McDonald #define IXGBE_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */ 199269b5a878SDan McDonald #define IXGBE_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */ 199369b5a878SDan McDonald #define IXGBE_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of control bits */ 199469b5a878SDan McDonald #define IXGBE_IMIR_SIZE_BP_82599 0x00001000 /* Packet size bypass */ 199569b5a878SDan McDonald #define IXGBE_IMIR_CTRL_URG_82599 0x00002000 /* Check URG bit in header */ 199669b5a878SDan McDonald #define IXGBE_IMIR_CTRL_ACK_82599 0x00004000 /* Check ACK bit in header */ 199769b5a878SDan McDonald #define IXGBE_IMIR_CTRL_PSH_82599 0x00008000 /* Check PSH bit in header */ 199869b5a878SDan McDonald #define IXGBE_IMIR_CTRL_RST_82599 0x00010000 /* Check RST bit in header */ 199969b5a878SDan McDonald #define IXGBE_IMIR_CTRL_SYN_82599 0x00020000 /* Check SYN bit in header */ 200069b5a878SDan McDonald #define IXGBE_IMIR_CTRL_FIN_82599 0x00040000 /* Check FIN bit in header */ 200169b5a878SDan McDonald #define IXGBE_IMIR_CTRL_BP_82599 0x00080000 /* Bypass chk of ctrl bits */ 200269b5a878SDan McDonald #define IXGBE_IMIR_LLI_EN_82599 0x00100000 /* Enables low latency Int */ 200369b5a878SDan McDonald #define IXGBE_IMIR_RX_QUEUE_MASK_82599 0x0000007F /* Rx Queue Mask */ 200469b5a878SDan McDonald #define IXGBE_IMIR_RX_QUEUE_SHIFT_82599 21 /* Rx Queue Shift */ 200569b5a878SDan McDonald #define IXGBE_IMIRVP_PRIORITY_MASK 0x00000007 /* VLAN priority mask */ 200669b5a878SDan McDonald #define IXGBE_IMIRVP_PRIORITY_EN 0x00000008 /* VLAN priority enable */ 200769b5a878SDan McDonald 200869b5a878SDan McDonald #define IXGBE_MAX_FTQF_FILTERS 128 200969b5a878SDan McDonald #define IXGBE_FTQF_PROTOCOL_MASK 0x00000003 201069b5a878SDan McDonald #define IXGBE_FTQF_PROTOCOL_TCP 0x00000000 201169b5a878SDan McDonald #define IXGBE_FTQF_PROTOCOL_UDP 0x00000001 201269b5a878SDan McDonald #define IXGBE_FTQF_PROTOCOL_SCTP 2 201369b5a878SDan McDonald #define IXGBE_FTQF_PRIORITY_MASK 0x00000007 201469b5a878SDan McDonald #define IXGBE_FTQF_PRIORITY_SHIFT 2 201569b5a878SDan McDonald #define IXGBE_FTQF_POOL_MASK 0x0000003F 201669b5a878SDan McDonald #define IXGBE_FTQF_POOL_SHIFT 8 201769b5a878SDan McDonald #define IXGBE_FTQF_5TUPLE_MASK_MASK 0x0000001F 201869b5a878SDan McDonald #define IXGBE_FTQF_5TUPLE_MASK_SHIFT 25 201969b5a878SDan McDonald #define IXGBE_FTQF_SOURCE_ADDR_MASK 0x1E 202069b5a878SDan McDonald #define IXGBE_FTQF_DEST_ADDR_MASK 0x1D 202169b5a878SDan McDonald #define IXGBE_FTQF_SOURCE_PORT_MASK 0x1B 202269b5a878SDan McDonald #define IXGBE_FTQF_DEST_PORT_MASK 0x17 202369b5a878SDan McDonald #define IXGBE_FTQF_PROTOCOL_COMP_MASK 0x0F 202469b5a878SDan McDonald #define IXGBE_FTQF_POOL_MASK_EN 0x40000000 202569b5a878SDan McDonald #define IXGBE_FTQF_QUEUE_ENABLE 0x80000000 20269da57d7bSbt 20279da57d7bSbt /* Interrupt clear mask */ 202869b5a878SDan McDonald #define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF 20299da57d7bSbt 20309da57d7bSbt /* Interrupt Vector Allocation Registers */ 203169b5a878SDan McDonald #define IXGBE_IVAR_REG_NUM 25 203269b5a878SDan McDonald #define IXGBE_IVAR_REG_NUM_82599 64 203369b5a878SDan McDonald #define IXGBE_IVAR_TXRX_ENTRY 96 203469b5a878SDan McDonald #define IXGBE_IVAR_RX_ENTRY 64 203569b5a878SDan McDonald #define IXGBE_IVAR_RX_QUEUE(_i) (0 + (_i)) 203669b5a878SDan McDonald #define IXGBE_IVAR_TX_QUEUE(_i) (64 + (_i)) 203769b5a878SDan McDonald #define IXGBE_IVAR_TX_ENTRY 32 20389da57d7bSbt 203969b5a878SDan McDonald #define IXGBE_IVAR_TCP_TIMER_INDEX 96 /* 0 based index */ 204069b5a878SDan McDonald #define IXGBE_IVAR_OTHER_CAUSES_INDEX 97 /* 0 based index */ 20419da57d7bSbt 204269b5a878SDan McDonald #define IXGBE_MSIX_VECTOR(_i) (0 + (_i)) 20439da57d7bSbt 204469b5a878SDan McDonald #define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */ 20459da57d7bSbt 204673cd555cSBin Tu - Sun Microsystems - Beijing China /* ETYPE Queue Filter/Select Bit Masks */ 204769b5a878SDan McDonald #define IXGBE_MAX_ETQF_FILTERS 8 204869b5a878SDan McDonald #define IXGBE_ETQF_FCOE 0x08000000 /* bit 27 */ 204969b5a878SDan McDonald #define IXGBE_ETQF_BCN 0x10000000 /* bit 28 */ 2050dc0cb1cdSDale Ghent #define IXGBE_ETQF_TX_ANTISPOOF 0x20000000 /* bit 29 */ 205169b5a878SDan McDonald #define IXGBE_ETQF_1588 0x40000000 /* bit 30 */ 205269b5a878SDan McDonald #define IXGBE_ETQF_FILTER_EN 0x80000000 /* bit 31 */ 205369b5a878SDan McDonald #define IXGBE_ETQF_POOL_ENABLE (1 << 26) /* bit 26 */ 205469b5a878SDan McDonald #define IXGBE_ETQF_POOL_SHIFT 20 205569b5a878SDan McDonald 205669b5a878SDan McDonald #define IXGBE_ETQS_RX_QUEUE 0x007F0000 /* bits 22:16 */ 205769b5a878SDan McDonald #define IXGBE_ETQS_RX_QUEUE_SHIFT 16 205869b5a878SDan McDonald #define IXGBE_ETQS_LLI 0x20000000 /* bit 29 */ 205969b5a878SDan McDonald #define IXGBE_ETQS_QUEUE_EN 0x80000000 /* bit 31 */ 206073cd555cSBin Tu - Sun Microsystems - Beijing China 206173cd555cSBin Tu - Sun Microsystems - Beijing China /* 206273cd555cSBin Tu - Sun Microsystems - Beijing China * ETQF filter list: one static filter per filter consumer. This is 206369b5a878SDan McDonald * to avoid filter collisions later. Add new filters 206469b5a878SDan McDonald * here!! 206573cd555cSBin Tu - Sun Microsystems - Beijing China * 206673cd555cSBin Tu - Sun Microsystems - Beijing China * Current filters: 206769b5a878SDan McDonald * EAPOL 802.1x (0x888e): Filter 0 206869b5a878SDan McDonald * FCoE (0x8906): Filter 2 206969b5a878SDan McDonald * 1588 (0x88f7): Filter 3 207069b5a878SDan McDonald * FIP (0x8914): Filter 4 2071dc0cb1cdSDale Ghent * LLDP (0x88CC): Filter 5 2072dc0cb1cdSDale Ghent * LACP (0x8809): Filter 6 2073dc0cb1cdSDale Ghent * FC (0x8808): Filter 7 207473cd555cSBin Tu - Sun Microsystems - Beijing China */ 207569b5a878SDan McDonald #define IXGBE_ETQF_FILTER_EAPOL 0 207669b5a878SDan McDonald #define IXGBE_ETQF_FILTER_FCOE 2 207769b5a878SDan McDonald #define IXGBE_ETQF_FILTER_1588 3 207869b5a878SDan McDonald #define IXGBE_ETQF_FILTER_FIP 4 2079dc0cb1cdSDale Ghent #define IXGBE_ETQF_FILTER_LLDP 5 2080dc0cb1cdSDale Ghent #define IXGBE_ETQF_FILTER_LACP 6 2081dc0cb1cdSDale Ghent #define IXGBE_ETQF_FILTER_FC 7 20829da57d7bSbt /* VLAN Control Bit Masks */ 208369b5a878SDan McDonald #define IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */ 208469b5a878SDan McDonald #define IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */ 208569b5a878SDan McDonald #define IXGBE_VLNCTRL_CFIEN 0x20000000 /* bit 29 */ 208669b5a878SDan McDonald #define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */ 208769b5a878SDan McDonald #define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */ 20889da57d7bSbt 208973cd555cSBin Tu - Sun Microsystems - Beijing China /* VLAN pool filtering masks */ 209069b5a878SDan McDonald #define IXGBE_VLVF_VIEN 0x80000000 /* filter is valid */ 209169b5a878SDan McDonald #define IXGBE_VLVF_ENTRIES 64 209269b5a878SDan McDonald #define IXGBE_VLVF_VLANID_MASK 0x00000FFF 20935b6dd21fSchenlu chen - Sun Microsystems - Beijing China /* Per VF Port VLAN insertion rules */ 209469b5a878SDan McDonald #define IXGBE_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */ 209569b5a878SDan McDonald #define IXGBE_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */ 20969da57d7bSbt 209769b5a878SDan McDonald #define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */ 20989da57d7bSbt 20999da57d7bSbt /* STATUS Bit Masks */ 210069b5a878SDan McDonald #define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */ 210169b5a878SDan McDonald #define IXGBE_STATUS_LAN_ID_SHIFT 2 /* LAN ID Shift*/ 210269b5a878SDan McDonald #define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Ena Status */ 21039da57d7bSbt 210469b5a878SDan McDonald #define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */ 210569b5a878SDan McDonald #define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */ 21069da57d7bSbt 21079da57d7bSbt /* ESDP Bit Masks */ 210869b5a878SDan McDonald #define IXGBE_ESDP_SDP0 0x00000001 /* SDP0 Data Value */ 210969b5a878SDan McDonald #define IXGBE_ESDP_SDP1 0x00000002 /* SDP1 Data Value */ 211069b5a878SDan McDonald #define IXGBE_ESDP_SDP2 0x00000004 /* SDP2 Data Value */ 211169b5a878SDan McDonald #define IXGBE_ESDP_SDP3 0x00000008 /* SDP3 Data Value */ 211269b5a878SDan McDonald #define IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */ 211369b5a878SDan McDonald #define IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */ 211469b5a878SDan McDonald #define IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */ 211569b5a878SDan McDonald #define IXGBE_ESDP_SDP7 0x00000080 /* SDP7 Data Value */ 211669b5a878SDan McDonald #define IXGBE_ESDP_SDP0_DIR 0x00000100 /* SDP0 IO direction */ 211769b5a878SDan McDonald #define IXGBE_ESDP_SDP1_DIR 0x00000200 /* SDP1 IO direction */ 2118dc0cb1cdSDale Ghent #define IXGBE_ESDP_SDP2_DIR 0x00000400 /* SDP1 IO direction */ 211969b5a878SDan McDonald #define IXGBE_ESDP_SDP3_DIR 0x00000800 /* SDP3 IO direction */ 212069b5a878SDan McDonald #define IXGBE_ESDP_SDP4_DIR 0x00001000 /* SDP4 IO direction */ 212169b5a878SDan McDonald #define IXGBE_ESDP_SDP5_DIR 0x00002000 /* SDP5 IO direction */ 212269b5a878SDan McDonald #define IXGBE_ESDP_SDP6_DIR 0x00004000 /* SDP6 IO direction */ 212369b5a878SDan McDonald #define IXGBE_ESDP_SDP7_DIR 0x00008000 /* SDP7 IO direction */ 212469b5a878SDan McDonald #define IXGBE_ESDP_SDP0_NATIVE 0x00010000 /* SDP0 IO mode */ 212569b5a878SDan McDonald #define IXGBE_ESDP_SDP1_NATIVE 0x00020000 /* SDP1 IO mode */ 212669b5a878SDan McDonald 21279da57d7bSbt 21289da57d7bSbt /* LEDCTL Bit Masks */ 212969b5a878SDan McDonald #define IXGBE_LED_IVRT_BASE 0x00000040 213069b5a878SDan McDonald #define IXGBE_LED_BLINK_BASE 0x00000080 213169b5a878SDan McDonald #define IXGBE_LED_MODE_MASK_BASE 0x0000000F 213269b5a878SDan McDonald #define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i))) 213369b5a878SDan McDonald #define IXGBE_LED_MODE_SHIFT(_i) (8*(_i)) 213469b5a878SDan McDonald #define IXGBE_LED_IVRT(_i) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i) 213569b5a878SDan McDonald #define IXGBE_LED_BLINK(_i) IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i) 213669b5a878SDan McDonald #define IXGBE_LED_MODE_MASK(_i) IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i) 2137dc0cb1cdSDale Ghent #define IXGBE_X557_LED_MANUAL_SET_MASK (1 << 8) 2138dc0cb1cdSDale Ghent #define IXGBE_X557_MAX_LED_INDEX 3 2139dc0cb1cdSDale Ghent #define IXGBE_X557_LED_PROVISIONING 0xC430 21409da57d7bSbt 21419da57d7bSbt /* LED modes */ 214269b5a878SDan McDonald #define IXGBE_LED_LINK_UP 0x0 214369b5a878SDan McDonald #define IXGBE_LED_LINK_10G 0x1 214469b5a878SDan McDonald #define IXGBE_LED_MAC 0x2 214569b5a878SDan McDonald #define IXGBE_LED_FILTER 0x3 214669b5a878SDan McDonald #define IXGBE_LED_LINK_ACTIVE 0x4 214769b5a878SDan McDonald #define IXGBE_LED_LINK_1G 0x5 214869b5a878SDan McDonald #define IXGBE_LED_ON 0xE 214969b5a878SDan McDonald #define IXGBE_LED_OFF 0xF 21509da57d7bSbt 21519da57d7bSbt /* AUTOC Bit Masks */ 215263b3bba8SJerry Jelinek #define IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000 215369b5a878SDan McDonald #define IXGBE_AUTOC_KX4_SUPP 0x80000000 215469b5a878SDan McDonald #define IXGBE_AUTOC_KX_SUPP 0x40000000 215569b5a878SDan McDonald #define IXGBE_AUTOC_PAUSE 0x30000000 215669b5a878SDan McDonald #define IXGBE_AUTOC_ASM_PAUSE 0x20000000 215769b5a878SDan McDonald #define IXGBE_AUTOC_SYM_PAUSE 0x10000000 215869b5a878SDan McDonald #define IXGBE_AUTOC_RF 0x08000000 215969b5a878SDan McDonald #define IXGBE_AUTOC_PD_TMR 0x06000000 216069b5a878SDan McDonald #define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000 216169b5a878SDan McDonald #define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000 216269b5a878SDan McDonald #define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000 216369b5a878SDan McDonald #define IXGBE_AUTOC_FECA 0x00040000 216469b5a878SDan McDonald #define IXGBE_AUTOC_FECR 0x00020000 216569b5a878SDan McDonald #define IXGBE_AUTOC_KR_SUPP 0x00010000 216669b5a878SDan McDonald #define IXGBE_AUTOC_AN_RESTART 0x00001000 216769b5a878SDan McDonald #define IXGBE_AUTOC_FLU 0x00000001 216869b5a878SDan McDonald #define IXGBE_AUTOC_LMS_SHIFT 13 216969b5a878SDan McDonald #define IXGBE_AUTOC_LMS_10G_SERIAL (0x3 << IXGBE_AUTOC_LMS_SHIFT) 217069b5a878SDan McDonald #define IXGBE_AUTOC_LMS_KX4_KX_KR (0x4 << IXGBE_AUTOC_LMS_SHIFT) 217169b5a878SDan McDonald #define IXGBE_AUTOC_LMS_SGMII_1G_100M (0x5 << IXGBE_AUTOC_LMS_SHIFT) 217269b5a878SDan McDonald #define IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT) 217369b5a878SDan McDonald #define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII (0x7 << IXGBE_AUTOC_LMS_SHIFT) 217469b5a878SDan McDonald #define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT) 217569b5a878SDan McDonald #define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT) 217669b5a878SDan McDonald #define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT) 217769b5a878SDan McDonald #define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT) 217869b5a878SDan McDonald #define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT) 217969b5a878SDan McDonald #define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT) 218069b5a878SDan McDonald #define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 218169b5a878SDan McDonald 218269b5a878SDan McDonald #define IXGBE_AUTOC_1G_PMA_PMD_MASK 0x00000200 218369b5a878SDan McDonald #define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9 218469b5a878SDan McDonald #define IXGBE_AUTOC_10G_PMA_PMD_MASK 0x00000180 218569b5a878SDan McDonald #define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7 218669b5a878SDan McDonald #define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 218769b5a878SDan McDonald #define IXGBE_AUTOC_10G_KX4 (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 218869b5a878SDan McDonald #define IXGBE_AUTOC_10G_CX4 (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 218969b5a878SDan McDonald #define IXGBE_AUTOC_1G_BX (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 219069b5a878SDan McDonald #define IXGBE_AUTOC_1G_KX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 219169b5a878SDan McDonald #define IXGBE_AUTOC_1G_SFI (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 219269b5a878SDan McDonald #define IXGBE_AUTOC_1G_KX_BX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 219369b5a878SDan McDonald 219469b5a878SDan McDonald #define IXGBE_AUTOC2_UPPER_MASK 0xFFFF0000 219569b5a878SDan McDonald #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK 0x00030000 219669b5a878SDan McDonald #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16 219769b5a878SDan McDonald #define IXGBE_AUTOC2_10G_KR (0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT) 219869b5a878SDan McDonald #define IXGBE_AUTOC2_10G_XFI (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT) 219969b5a878SDan McDonald #define IXGBE_AUTOC2_10G_SFI (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT) 2200dc0cb1cdSDale Ghent #define IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK 0x50000000 2201dc0cb1cdSDale Ghent #define IXGBE_AUTOC2_LINK_DISABLE_MASK 0x70000000 220269b5a878SDan McDonald 220369b5a878SDan McDonald #define IXGBE_MACC_FLU 0x00000001 220469b5a878SDan McDonald #define IXGBE_MACC_FSV_10G 0x00030000 220569b5a878SDan McDonald #define IXGBE_MACC_FS 0x00040000 220669b5a878SDan McDonald #define IXGBE_MAC_RX2TX_LPBK 0x00000002 22079da57d7bSbt 2208dc0cb1cdSDale Ghent /* Veto Bit definition */ 2209dc0cb1cdSDale Ghent #define IXGBE_MMNGC_MNG_VETO 0x00000001 2210dc0cb1cdSDale Ghent 22119da57d7bSbt /* LINKS Bit Masks */ 221269b5a878SDan McDonald #define IXGBE_LINKS_KX_AN_COMP 0x80000000 221369b5a878SDan McDonald #define IXGBE_LINKS_UP 0x40000000 221469b5a878SDan McDonald #define IXGBE_LINKS_SPEED 0x20000000 221569b5a878SDan McDonald #define IXGBE_LINKS_MODE 0x18000000 221669b5a878SDan McDonald #define IXGBE_LINKS_RX_MODE 0x06000000 221769b5a878SDan McDonald #define IXGBE_LINKS_TX_MODE 0x01800000 221869b5a878SDan McDonald #define IXGBE_LINKS_XGXS_EN 0x00400000 221969b5a878SDan McDonald #define IXGBE_LINKS_SGMII_EN 0x02000000 222069b5a878SDan McDonald #define IXGBE_LINKS_PCS_1G_EN 0x00200000 222169b5a878SDan McDonald #define IXGBE_LINKS_1G_AN_EN 0x00100000 222269b5a878SDan McDonald #define IXGBE_LINKS_KX_AN_IDLE 0x00080000 222369b5a878SDan McDonald #define IXGBE_LINKS_1G_SYNC 0x00040000 222469b5a878SDan McDonald #define IXGBE_LINKS_10G_ALIGN 0x00020000 222569b5a878SDan McDonald #define IXGBE_LINKS_10G_LANE_SYNC 0x00017000 222669b5a878SDan McDonald #define IXGBE_LINKS_TL_FAULT 0x00001000 222769b5a878SDan McDonald #define IXGBE_LINKS_SIGNAL 0x00000F00 222869b5a878SDan McDonald 2229dc0cb1cdSDale Ghent #define IXGBE_LINKS_SPEED_NON_STD 0x08000000 223069b5a878SDan McDonald #define IXGBE_LINKS_SPEED_82599 0x30000000 223169b5a878SDan McDonald #define IXGBE_LINKS_SPEED_10G_82599 0x30000000 223269b5a878SDan McDonald #define IXGBE_LINKS_SPEED_1G_82599 0x20000000 223369b5a878SDan McDonald #define IXGBE_LINKS_SPEED_100_82599 0x10000000 2234*48ed61a7SRobert Mustacchi #define IXGBE_LINKS_SPEED_10_X550EM_A 0x00000000 223569b5a878SDan McDonald #define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */ 223669b5a878SDan McDonald #define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */ 223769b5a878SDan McDonald 223869b5a878SDan McDonald #define IXGBE_LINKS2_AN_SUPPORTED 0x00000040 22393cfa0eb9Schenlu chen - Sun Microsystems - Beijing China 224073cd555cSBin Tu - Sun Microsystems - Beijing China /* PCS1GLSTA Bit Masks */ 224169b5a878SDan McDonald #define IXGBE_PCS1GLSTA_LINK_OK 1 224269b5a878SDan McDonald #define IXGBE_PCS1GLSTA_SYNK_OK 0x10 224369b5a878SDan McDonald #define IXGBE_PCS1GLSTA_AN_COMPLETE 0x10000 224469b5a878SDan McDonald #define IXGBE_PCS1GLSTA_AN_PAGE_RX 0x20000 224569b5a878SDan McDonald #define IXGBE_PCS1GLSTA_AN_TIMED_OUT 0x40000 224669b5a878SDan McDonald #define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000 224769b5a878SDan McDonald #define IXGBE_PCS1GLSTA_AN_ERROR_RWS 0x100000 224873cd555cSBin Tu - Sun Microsystems - Beijing China 224969b5a878SDan McDonald #define IXGBE_PCS1GANA_SYM_PAUSE 0x80 225069b5a878SDan McDonald #define IXGBE_PCS1GANA_ASM_PAUSE 0x100 225173cd555cSBin Tu - Sun Microsystems - Beijing China 225273cd555cSBin Tu - Sun Microsystems - Beijing China /* PCS1GLCTL Bit Masks */ 225369b5a878SDan McDonald #define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN 0x00040000 /* PCS 1G autoneg to en */ 225469b5a878SDan McDonald #define IXGBE_PCS1GLCTL_FLV_LINK_UP 1 225569b5a878SDan McDonald #define IXGBE_PCS1GLCTL_FORCE_LINK 0x20 225669b5a878SDan McDonald #define IXGBE_PCS1GLCTL_LOW_LINK_LATCH 0x40 225769b5a878SDan McDonald #define IXGBE_PCS1GLCTL_AN_ENABLE 0x10000 225869b5a878SDan McDonald #define IXGBE_PCS1GLCTL_AN_RESTART 0x20000 22599da57d7bSbt 22603cfa0eb9Schenlu chen - Sun Microsystems - Beijing China /* ANLP1 Bit Masks */ 226169b5a878SDan McDonald #define IXGBE_ANLP1_PAUSE 0x0C00 226269b5a878SDan McDonald #define IXGBE_ANLP1_SYM_PAUSE 0x0400 226369b5a878SDan McDonald #define IXGBE_ANLP1_ASM_PAUSE 0x0800 226469b5a878SDan McDonald #define IXGBE_ANLP1_AN_STATE_MASK 0x000f0000 22653cfa0eb9Schenlu chen - Sun Microsystems - Beijing China 22669da57d7bSbt /* SW Semaphore Register bitmasks */ 226769b5a878SDan McDonald #define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 226869b5a878SDan McDonald #define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 226969b5a878SDan McDonald #define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */ 227069b5a878SDan McDonald #define IXGBE_SWFW_REGSMP 0x80000000 /* Register Semaphore bit 31 */ 22719da57d7bSbt 22723cfa0eb9Schenlu chen - Sun Microsystems - Beijing China /* SW_FW_SYNC/GSSR definitions */ 2273dc0cb1cdSDale Ghent #define IXGBE_GSSR_EEP_SM 0x0001 2274dc0cb1cdSDale Ghent #define IXGBE_GSSR_PHY0_SM 0x0002 2275dc0cb1cdSDale Ghent #define IXGBE_GSSR_PHY1_SM 0x0004 2276dc0cb1cdSDale Ghent #define IXGBE_GSSR_MAC_CSR_SM 0x0008 2277dc0cb1cdSDale Ghent #define IXGBE_GSSR_FLASH_SM 0x0010 2278dc0cb1cdSDale Ghent #define IXGBE_GSSR_NVM_UPDATE_SM 0x0200 2279dc0cb1cdSDale Ghent #define IXGBE_GSSR_SW_MNG_SM 0x0400 2280*48ed61a7SRobert Mustacchi #define IXGBE_GSSR_TOKEN_SM 0x40000000 /* SW bit for shared access */ 2281dc0cb1cdSDale Ghent #define IXGBE_GSSR_SHARED_I2C_SM 0x1806 /* Wait for both phys and both I2Cs */ 2282dc0cb1cdSDale Ghent #define IXGBE_GSSR_I2C_MASK 0x1800 2283dc0cb1cdSDale Ghent #define IXGBE_GSSR_NVM_PHY_MASK 0xF 228469b5a878SDan McDonald 228569b5a878SDan McDonald /* FW Status register bitmask */ 228669b5a878SDan McDonald #define IXGBE_FWSTS_FWRI 0x00000200 /* Firmware Reset Indication */ 22879da57d7bSbt 22889da57d7bSbt /* EEC Register */ 228969b5a878SDan McDonald #define IXGBE_EEC_SK 0x00000001 /* EEPROM Clock */ 229069b5a878SDan McDonald #define IXGBE_EEC_CS 0x00000002 /* EEPROM Chip Select */ 229169b5a878SDan McDonald #define IXGBE_EEC_DI 0x00000004 /* EEPROM Data In */ 229269b5a878SDan McDonald #define IXGBE_EEC_DO 0x00000008 /* EEPROM Data Out */ 229369b5a878SDan McDonald #define IXGBE_EEC_FWE_MASK 0x00000030 /* FLASH Write Enable */ 229469b5a878SDan McDonald #define IXGBE_EEC_FWE_DIS 0x00000010 /* Disable FLASH writes */ 229569b5a878SDan McDonald #define IXGBE_EEC_FWE_EN 0x00000020 /* Enable FLASH writes */ 229669b5a878SDan McDonald #define IXGBE_EEC_FWE_SHIFT 4 229769b5a878SDan McDonald #define IXGBE_EEC_REQ 0x00000040 /* EEPROM Access Request */ 229869b5a878SDan McDonald #define IXGBE_EEC_GNT 0x00000080 /* EEPROM Access Grant */ 229969b5a878SDan McDonald #define IXGBE_EEC_PRES 0x00000100 /* EEPROM Present */ 230069b5a878SDan McDonald #define IXGBE_EEC_ARD 0x00000200 /* EEPROM Auto Read Done */ 230169b5a878SDan McDonald #define IXGBE_EEC_FLUP 0x00800000 /* Flash update command */ 230269b5a878SDan McDonald #define IXGBE_EEC_SEC1VAL 0x02000000 /* Sector 1 Valid */ 230369b5a878SDan McDonald #define IXGBE_EEC_FLUDONE 0x04000000 /* Flash update done */ 23049da57d7bSbt /* EEPROM Addressing bits based on type (0-small, 1-large) */ 230569b5a878SDan McDonald #define IXGBE_EEC_ADDR_SIZE 0x00000400 230669b5a878SDan McDonald #define IXGBE_EEC_SIZE 0x00007800 /* EEPROM Size */ 230769b5a878SDan McDonald #define IXGBE_EERD_MAX_ADDR 0x00003FFF /* EERD alows 14 bits for addr. */ 23089da57d7bSbt 230969b5a878SDan McDonald #define IXGBE_EEC_SIZE_SHIFT 11 231069b5a878SDan McDonald #define IXGBE_EEPROM_WORD_SIZE_SHIFT 6 231169b5a878SDan McDonald #define IXGBE_EEPROM_OPCODE_BITS 8 231263b3bba8SJerry Jelinek 2313dc0cb1cdSDale Ghent /* FLA Register */ 2314dc0cb1cdSDale Ghent #define IXGBE_FLA_LOCKED 0x00000040 2315dc0cb1cdSDale Ghent 231663b3bba8SJerry Jelinek /* Part Number String Length */ 231769b5a878SDan McDonald #define IXGBE_PBANUM_LENGTH 11 23189da57d7bSbt 23199da57d7bSbt /* Checksum and EEPROM pointers */ 2320dc0cb1cdSDale Ghent #define IXGBE_PBANUM_PTR_GUARD 0xFAFA 2321dc0cb1cdSDale Ghent #define IXGBE_EEPROM_CHECKSUM 0x3F 2322dc0cb1cdSDale Ghent #define IXGBE_EEPROM_SUM 0xBABA 2323*48ed61a7SRobert Mustacchi #define IXGBE_EEPROM_CTRL_4 0x45 2324*48ed61a7SRobert Mustacchi #define IXGBE_EE_CTRL_4_INST_ID 0x10 2325*48ed61a7SRobert Mustacchi #define IXGBE_EE_CTRL_4_INST_ID_SHIFT 4 2326dc0cb1cdSDale Ghent #define IXGBE_PCIE_ANALOG_PTR 0x03 2327dc0cb1cdSDale Ghent #define IXGBE_ATLAS0_CONFIG_PTR 0x04 2328dc0cb1cdSDale Ghent #define IXGBE_PHY_PTR 0x04 2329dc0cb1cdSDale Ghent #define IXGBE_ATLAS1_CONFIG_PTR 0x05 2330dc0cb1cdSDale Ghent #define IXGBE_OPTION_ROM_PTR 0x05 2331dc0cb1cdSDale Ghent #define IXGBE_PCIE_GENERAL_PTR 0x06 2332dc0cb1cdSDale Ghent #define IXGBE_PCIE_CONFIG0_PTR 0x07 2333dc0cb1cdSDale Ghent #define IXGBE_PCIE_CONFIG1_PTR 0x08 2334dc0cb1cdSDale Ghent #define IXGBE_CORE0_PTR 0x09 2335dc0cb1cdSDale Ghent #define IXGBE_CORE1_PTR 0x0A 2336dc0cb1cdSDale Ghent #define IXGBE_MAC0_PTR 0x0B 2337dc0cb1cdSDale Ghent #define IXGBE_MAC1_PTR 0x0C 2338dc0cb1cdSDale Ghent #define IXGBE_CSR0_CONFIG_PTR 0x0D 2339dc0cb1cdSDale Ghent #define IXGBE_CSR1_CONFIG_PTR 0x0E 2340dc0cb1cdSDale Ghent #define IXGBE_PCIE_ANALOG_PTR_X550 0x02 2341dc0cb1cdSDale Ghent #define IXGBE_SHADOW_RAM_SIZE_X550 0x4000 2342dc0cb1cdSDale Ghent #define IXGBE_IXGBE_PCIE_GENERAL_SIZE 0x24 2343dc0cb1cdSDale Ghent #define IXGBE_PCIE_CONFIG_SIZE 0x08 2344dc0cb1cdSDale Ghent #define IXGBE_EEPROM_LAST_WORD 0x41 2345dc0cb1cdSDale Ghent #define IXGBE_FW_PTR 0x0F 2346dc0cb1cdSDale Ghent #define IXGBE_PBANUM0_PTR 0x15 2347dc0cb1cdSDale Ghent #define IXGBE_PBANUM1_PTR 0x16 2348dc0cb1cdSDale Ghent #define IXGBE_ALT_MAC_ADDR_PTR 0x37 2349dc0cb1cdSDale Ghent #define IXGBE_FREE_SPACE_PTR 0X3E 235069b5a878SDan McDonald 235169b5a878SDan McDonald #define IXGBE_SAN_MAC_ADDR_PTR 0x28 235269b5a878SDan McDonald #define IXGBE_DEVICE_CAPS 0x2C 2353*48ed61a7SRobert Mustacchi #define IXGBE_82599_SERIAL_NUMBER_MAC_ADDR 0x11 2354*48ed61a7SRobert Mustacchi #define IXGBE_X550_SERIAL_NUMBER_MAC_ADDR 0x04 2355*48ed61a7SRobert Mustacchi 235669b5a878SDan McDonald #define IXGBE_PCIE_MSIX_82599_CAPS 0x72 235769b5a878SDan McDonald #define IXGBE_MAX_MSIX_VECTORS_82599 0x40 235869b5a878SDan McDonald #define IXGBE_PCIE_MSIX_82598_CAPS 0x62 235969b5a878SDan McDonald #define IXGBE_MAX_MSIX_VECTORS_82598 0x13 236073cd555cSBin Tu - Sun Microsystems - Beijing China 236173cd555cSBin Tu - Sun Microsystems - Beijing China /* MSI-X capability fields masks */ 236269b5a878SDan McDonald #define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF 23639da57d7bSbt 23649da57d7bSbt /* Legacy EEPROM word offsets */ 236569b5a878SDan McDonald #define IXGBE_ISCSI_BOOT_CAPS 0x0033 236669b5a878SDan McDonald #define IXGBE_ISCSI_SETUP_PORT_0 0x0030 236769b5a878SDan McDonald #define IXGBE_ISCSI_SETUP_PORT_1 0x0034 23689da57d7bSbt 23699da57d7bSbt /* EEPROM Commands - SPI */ 237069b5a878SDan McDonald #define IXGBE_EEPROM_MAX_RETRY_SPI 5000 /* Max wait 5ms for RDY signal */ 237169b5a878SDan McDonald #define IXGBE_EEPROM_STATUS_RDY_SPI 0x01 237269b5a878SDan McDonald #define IXGBE_EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */ 237369b5a878SDan McDonald #define IXGBE_EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */ 237469b5a878SDan McDonald #define IXGBE_EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = addr bit-8 */ 237569b5a878SDan McDonald #define IXGBE_EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Ena latch */ 23769da57d7bSbt /* EEPROM reset Write Enable latch */ 237769b5a878SDan McDonald #define IXGBE_EEPROM_WRDI_OPCODE_SPI 0x04 237869b5a878SDan McDonald #define IXGBE_EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status reg */ 237969b5a878SDan McDonald #define IXGBE_EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status reg */ 238069b5a878SDan McDonald #define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */ 238169b5a878SDan McDonald #define IXGBE_EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */ 238269b5a878SDan McDonald #define IXGBE_EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */ 23839da57d7bSbt 23849da57d7bSbt /* EEPROM Read Register */ 238569b5a878SDan McDonald #define IXGBE_EEPROM_RW_REG_DATA 16 /* data offset in EEPROM read reg */ 238669b5a878SDan McDonald #define IXGBE_EEPROM_RW_REG_DONE 2 /* Offset to READ done bit */ 238769b5a878SDan McDonald #define IXGBE_EEPROM_RW_REG_START 1 /* First bit to start operation */ 238869b5a878SDan McDonald #define IXGBE_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 238969b5a878SDan McDonald #define IXGBE_NVM_POLL_WRITE 1 /* Flag for polling for wr complete */ 239069b5a878SDan McDonald #define IXGBE_NVM_POLL_READ 0 /* Flag for polling for rd complete */ 239169b5a878SDan McDonald 2392dc0cb1cdSDale Ghent #define NVM_INIT_CTRL_3 0x38 2393dc0cb1cdSDale Ghent #define NVM_INIT_CTRL_3_LPLU 0x8 2394dc0cb1cdSDale Ghent #define NVM_INIT_CTRL_3_D10GMP_PORT0 0x40 2395dc0cb1cdSDale Ghent #define NVM_INIT_CTRL_3_D10GMP_PORT1 0x100 2396dc0cb1cdSDale Ghent 239769b5a878SDan McDonald #define IXGBE_ETH_LENGTH_OF_ADDRESS 6 23989da57d7bSbt 239969b5a878SDan McDonald #define IXGBE_EEPROM_PAGE_SIZE_MAX 128 2400dc0cb1cdSDale Ghent #define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT 256 /* words rd in burst */ 240169b5a878SDan McDonald #define IXGBE_EEPROM_WR_BUFFER_MAX_COUNT 256 /* words wr in burst */ 2402dc0cb1cdSDale Ghent #define IXGBE_EEPROM_CTRL_2 1 /* EEPROM CTRL word 2 */ 2403dc0cb1cdSDale Ghent #define IXGBE_EEPROM_CCD_BIT 2 24049da57d7bSbt 24059da57d7bSbt #ifndef IXGBE_EEPROM_GRANT_ATTEMPTS 240669b5a878SDan McDonald #define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM attempts to gain grant */ 24079da57d7bSbt #endif 24089da57d7bSbt 240963b3bba8SJerry Jelinek /* Number of 5 microseconds we wait for EERD read and 241063b3bba8SJerry Jelinek * EERW write to complete */ 241169b5a878SDan McDonald #define IXGBE_EERD_EEWR_ATTEMPTS 100000 24123cfa0eb9Schenlu chen - Sun Microsystems - Beijing China 24133cfa0eb9Schenlu chen - Sun Microsystems - Beijing China /* # attempts we wait for flush update to complete */ 241469b5a878SDan McDonald #define IXGBE_FLUDONE_ATTEMPTS 20000 241569b5a878SDan McDonald 241669b5a878SDan McDonald #define IXGBE_PCIE_CTRL2 0x5 /* PCIe Control 2 Offset */ 241769b5a878SDan McDonald #define IXGBE_PCIE_CTRL2_DUMMY_ENABLE 0x8 /* Dummy Function Enable */ 241869b5a878SDan McDonald #define IXGBE_PCIE_CTRL2_LAN_DISABLE 0x2 /* LAN PCI Disable */ 241969b5a878SDan McDonald #define IXGBE_PCIE_CTRL2_DISABLE_SELECT 0x1 /* LAN Disable Select */ 242069b5a878SDan McDonald 242169b5a878SDan McDonald #define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0 242269b5a878SDan McDonald #define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3 242369b5a878SDan McDonald #define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1 242469b5a878SDan McDonald #define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS 0x2 2425*48ed61a7SRobert Mustacchi #define IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR (1 << 7) 242669b5a878SDan McDonald #define IXGBE_FW_LESM_PARAMETERS_PTR 0x2 242769b5a878SDan McDonald #define IXGBE_FW_LESM_STATE_1 0x1 242869b5a878SDan McDonald #define IXGBE_FW_LESM_STATE_ENABLED 0x8000 /* LESM Enable bit */ 242969b5a878SDan McDonald #define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4 243069b5a878SDan McDonald #define IXGBE_FW_PATCH_VERSION_4 0x7 243169b5a878SDan McDonald #define IXGBE_FCOE_IBA_CAPS_BLK_PTR 0x33 /* iSCSI/FCOE block */ 243269b5a878SDan McDonald #define IXGBE_FCOE_IBA_CAPS_FCOE 0x20 /* FCOE flags */ 243369b5a878SDan McDonald #define IXGBE_ISCSI_FCOE_BLK_PTR 0x17 /* iSCSI/FCOE block */ 243469b5a878SDan McDonald #define IXGBE_ISCSI_FCOE_FLAGS_OFFSET 0x0 /* FCOE flags */ 243569b5a878SDan McDonald #define IXGBE_ISCSI_FCOE_FLAGS_ENABLE 0x1 /* FCOE flags enable bit */ 243669b5a878SDan McDonald #define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR 0x27 /* Alt. SAN MAC block */ 243769b5a878SDan McDonald #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET 0x0 /* Alt SAN MAC capability */ 243869b5a878SDan McDonald #define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1 /* Alt SAN MAC 0 offset */ 243969b5a878SDan McDonald #define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4 /* Alt SAN MAC 1 offset */ 244069b5a878SDan McDonald #define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET 0x7 /* Alt WWNN prefix offset */ 244169b5a878SDan McDonald #define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET 0x8 /* Alt WWPN prefix offset */ 244269b5a878SDan McDonald #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC 0x0 /* Alt SAN MAC exists */ 244369b5a878SDan McDonald #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN 0x1 /* Alt WWN base exists */ 244469b5a878SDan McDonald 2445dc0cb1cdSDale Ghent /* FW header offset */ 2446dc0cb1cdSDale Ghent #define IXGBE_X540_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4 2447dc0cb1cdSDale Ghent #define IXGBE_X540_FW_MODULE_MASK 0x7FFF 2448dc0cb1cdSDale Ghent /* 4KB multiplier */ 2449dc0cb1cdSDale Ghent #define IXGBE_X540_FW_MODULE_LENGTH 0x1000 2450dc0cb1cdSDale Ghent /* version word 2 (month & day) */ 2451dc0cb1cdSDale Ghent #define IXGBE_X540_FW_PATCH_VERSION_2 0x5 2452dc0cb1cdSDale Ghent /* version word 3 (silicon compatibility & year) */ 2453dc0cb1cdSDale Ghent #define IXGBE_X540_FW_PATCH_VERSION_3 0x6 2454dc0cb1cdSDale Ghent /* version word 4 (major & minor numbers) */ 2455dc0cb1cdSDale Ghent #define IXGBE_X540_FW_PATCH_VERSION_4 0x7 2456dc0cb1cdSDale Ghent 245769b5a878SDan McDonald #define IXGBE_DEVICE_CAPS_WOL_PORT0_1 0x4 /* WoL supported on ports 0 & 1 */ 245869b5a878SDan McDonald #define IXGBE_DEVICE_CAPS_WOL_PORT0 0x8 /* WoL supported on port 0 */ 245969b5a878SDan McDonald #define IXGBE_DEVICE_CAPS_WOL_MASK 0xC /* Mask for WoL capabilities */ 246073cd555cSBin Tu - Sun Microsystems - Beijing China 24619da57d7bSbt /* PCI Bus Info */ 246269b5a878SDan McDonald #define IXGBE_PCI_DEVICE_STATUS 0xAA 246369b5a878SDan McDonald #define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING 0x0020 246469b5a878SDan McDonald #define IXGBE_PCI_LINK_STATUS 0xB2 246569b5a878SDan McDonald #define IXGBE_PCI_DEVICE_CONTROL2 0xC8 246669b5a878SDan McDonald #define IXGBE_PCI_LINK_WIDTH 0x3F0 246769b5a878SDan McDonald #define IXGBE_PCI_LINK_WIDTH_1 0x10 246869b5a878SDan McDonald #define IXGBE_PCI_LINK_WIDTH_2 0x20 246969b5a878SDan McDonald #define IXGBE_PCI_LINK_WIDTH_4 0x40 247069b5a878SDan McDonald #define IXGBE_PCI_LINK_WIDTH_8 0x80 247169b5a878SDan McDonald #define IXGBE_PCI_LINK_SPEED 0xF 247269b5a878SDan McDonald #define IXGBE_PCI_LINK_SPEED_2500 0x1 247369b5a878SDan McDonald #define IXGBE_PCI_LINK_SPEED_5000 0x2 247469b5a878SDan McDonald #define IXGBE_PCI_LINK_SPEED_8000 0x3 247569b5a878SDan McDonald #define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E 247669b5a878SDan McDonald #define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80 247769b5a878SDan McDonald #define IXGBE_PCI_DEVICE_CONTROL2_16ms 0x0005 24789da57d7bSbt 2479dc0cb1cdSDale Ghent #define IXGBE_PCIDEVCTRL2_TIMEO_MASK 0xf 2480dc0cb1cdSDale Ghent #define IXGBE_PCIDEVCTRL2_16_32ms_def 0x0 2481dc0cb1cdSDale Ghent #define IXGBE_PCIDEVCTRL2_50_100us 0x1 2482dc0cb1cdSDale Ghent #define IXGBE_PCIDEVCTRL2_1_2ms 0x2 2483dc0cb1cdSDale Ghent #define IXGBE_PCIDEVCTRL2_16_32ms 0x5 2484dc0cb1cdSDale Ghent #define IXGBE_PCIDEVCTRL2_65_130ms 0x6 2485dc0cb1cdSDale Ghent #define IXGBE_PCIDEVCTRL2_260_520ms 0x9 2486dc0cb1cdSDale Ghent #define IXGBE_PCIDEVCTRL2_1_2s 0xa 2487dc0cb1cdSDale Ghent #define IXGBE_PCIDEVCTRL2_4_8s 0xd 2488dc0cb1cdSDale Ghent #define IXGBE_PCIDEVCTRL2_17_34s 0xe 2489dc0cb1cdSDale Ghent 24909da57d7bSbt /* Number of 100 microseconds we wait for PCI Express master disable */ 249169b5a878SDan McDonald #define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800 24929da57d7bSbt 249369b5a878SDan McDonald /* Check whether address is multicast. This is little-endian specific check.*/ 249463b3bba8SJerry Jelinek #define IXGBE_IS_MULTICAST(Address) \ 249569b5a878SDan McDonald (bool)(((u8 *)(Address))[0] & ((u8)0x01)) 24969da57d7bSbt 24979da57d7bSbt /* Check whether an address is broadcast. */ 249869b5a878SDan McDonald #define IXGBE_IS_BROADCAST(Address) \ 249969b5a878SDan McDonald ((((u8 *)(Address))[0] == ((u8)0xff)) && \ 250069b5a878SDan McDonald (((u8 *)(Address))[1] == ((u8)0xff))) 25019da57d7bSbt 25029da57d7bSbt /* RAH */ 250369b5a878SDan McDonald #define IXGBE_RAH_VIND_MASK 0x003C0000 250469b5a878SDan McDonald #define IXGBE_RAH_VIND_SHIFT 18 250569b5a878SDan McDonald #define IXGBE_RAH_AV 0x80000000 250669b5a878SDan McDonald #define IXGBE_CLEAR_VMDQ_ALL 0xFFFFFFFF 25079da57d7bSbt 25089da57d7bSbt /* Header split receive */ 250969b5a878SDan McDonald #define IXGBE_RFCTL_ISCSI_DIS 0x00000001 251069b5a878SDan McDonald #define IXGBE_RFCTL_ISCSI_DWC_MASK 0x0000003E 251169b5a878SDan McDonald #define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1 2512dc0cb1cdSDale Ghent #define IXGBE_RFCTL_RSC_DIS 0x00000020 251369b5a878SDan McDonald #define IXGBE_RFCTL_NFSW_DIS 0x00000040 251469b5a878SDan McDonald #define IXGBE_RFCTL_NFSR_DIS 0x00000080 251569b5a878SDan McDonald #define IXGBE_RFCTL_NFS_VER_MASK 0x00000300 251669b5a878SDan McDonald #define IXGBE_RFCTL_NFS_VER_SHIFT 8 251769b5a878SDan McDonald #define IXGBE_RFCTL_NFS_VER_2 0 251869b5a878SDan McDonald #define IXGBE_RFCTL_NFS_VER_3 1 251969b5a878SDan McDonald #define IXGBE_RFCTL_NFS_VER_4 2 252069b5a878SDan McDonald #define IXGBE_RFCTL_IPV6_DIS 0x00000400 252169b5a878SDan McDonald #define IXGBE_RFCTL_IPV6_XSUM_DIS 0x00000800 252269b5a878SDan McDonald #define IXGBE_RFCTL_IPFRSP_DIS 0x00004000 252369b5a878SDan McDonald #define IXGBE_RFCTL_IPV6_EX_DIS 0x00010000 252469b5a878SDan McDonald #define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 25259da57d7bSbt 25269da57d7bSbt /* Transmit Config masks */ 252769b5a878SDan McDonald #define IXGBE_TXDCTL_ENABLE 0x02000000 /* Ena specific Tx Queue */ 252869b5a878SDan McDonald #define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. wr-bk flushing */ 252969b5a878SDan McDonald #define IXGBE_TXDCTL_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */ 25309da57d7bSbt /* Enable short packet padding to 64 bytes */ 253169b5a878SDan McDonald #define IXGBE_TX_PAD_ENABLE 0x00000400 253269b5a878SDan McDonald #define IXGBE_JUMBO_FRAME_ENABLE 0x00000004 /* Allow jumbo frames */ 25339da57d7bSbt /* This allows for 16K packets + 4k for vlan */ 253469b5a878SDan McDonald #define IXGBE_MAX_FRAME_SZ 0x40040000 25359da57d7bSbt 253669b5a878SDan McDonald #define IXGBE_TDWBAL_HEAD_WB_ENABLE 0x1 /* Tx head write-back enable */ 253769b5a878SDan McDonald #define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2 /* Tx seq# write-back enable */ 25389da57d7bSbt 25399da57d7bSbt /* Receive Config masks */ 254069b5a878SDan McDonald #define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */ 254169b5a878SDan McDonald #define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Desc Monitor Bypass */ 254269b5a878SDan McDonald #define IXGBE_RXDCTL_ENABLE 0x02000000 /* Ena specific Rx Queue */ 254369b5a878SDan McDonald #define IXGBE_RXDCTL_SWFLSH 0x04000000 /* Rx Desc wr-bk flushing */ 254469b5a878SDan McDonald #define IXGBE_RXDCTL_RLPMLMASK 0x00003FFF /* X540 supported only */ 254569b5a878SDan McDonald #define IXGBE_RXDCTL_RLPML_EN 0x00008000 254669b5a878SDan McDonald #define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */ 254769b5a878SDan McDonald 254869b5a878SDan McDonald #define IXGBE_TSAUXC_EN_CLK 0x00000004 254969b5a878SDan McDonald #define IXGBE_TSAUXC_SYNCLK 0x00000008 255069b5a878SDan McDonald #define IXGBE_TSAUXC_SDP0_INT 0x00000040 2551dc0cb1cdSDale Ghent #define IXGBE_TSAUXC_EN_TT0 0x00000001 2552dc0cb1cdSDale Ghent #define IXGBE_TSAUXC_EN_TT1 0x00000002 2553dc0cb1cdSDale Ghent #define IXGBE_TSAUXC_ST0 0x00000010 2554dc0cb1cdSDale Ghent #define IXGBE_TSAUXC_DISABLE_SYSTIME 0x80000000 2555dc0cb1cdSDale Ghent 2556dc0cb1cdSDale Ghent #define IXGBE_TSSDP_TS_SDP0_SEL_MASK 0x000000C0 2557dc0cb1cdSDale Ghent #define IXGBE_TSSDP_TS_SDP0_CLK0 0x00000080 2558dc0cb1cdSDale Ghent #define IXGBE_TSSDP_TS_SDP0_EN 0x00000100 255969b5a878SDan McDonald 256069b5a878SDan McDonald #define IXGBE_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */ 256169b5a878SDan McDonald #define IXGBE_TSYNCTXCTL_ENABLED 0x00000010 /* Tx timestamping enabled */ 256269b5a878SDan McDonald 256369b5a878SDan McDonald #define IXGBE_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */ 256469b5a878SDan McDonald #define IXGBE_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */ 256569b5a878SDan McDonald #define IXGBE_TSYNCRXCTL_TYPE_L2_V2 0x00 256669b5a878SDan McDonald #define IXGBE_TSYNCRXCTL_TYPE_L4_V1 0x02 256769b5a878SDan McDonald #define IXGBE_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 2568dc0cb1cdSDale Ghent #define IXGBE_TSYNCRXCTL_TYPE_ALL 0x08 256969b5a878SDan McDonald #define IXGBE_TSYNCRXCTL_TYPE_EVENT_V2 0x0A 257069b5a878SDan McDonald #define IXGBE_TSYNCRXCTL_ENABLED 0x00000010 /* Rx Timestamping enabled */ 2571dc0cb1cdSDale Ghent #define IXGBE_TSYNCRXCTL_TSIP_UT_EN 0x00800000 /* Rx Timestamp in Packet */ 2572dc0cb1cdSDale Ghent #define IXGBE_TSYNCRXCTL_TSIP_UP_MASK 0xFF000000 /* Rx Timestamp UP Mask */ 2573dc0cb1cdSDale Ghent 2574dc0cb1cdSDale Ghent #define IXGBE_TSIM_SYS_WRAP 0x00000001 2575dc0cb1cdSDale Ghent #define IXGBE_TSIM_TXTS 0x00000002 2576dc0cb1cdSDale Ghent #define IXGBE_TSIM_TADJ 0x00000080 2577dc0cb1cdSDale Ghent 2578dc0cb1cdSDale Ghent #define IXGBE_TSICR_SYS_WRAP IXGBE_TSIM_SYS_WRAP 2579dc0cb1cdSDale Ghent #define IXGBE_TSICR_TXTS IXGBE_TSIM_TXTS 2580dc0cb1cdSDale Ghent #define IXGBE_TSICR_TADJ IXGBE_TSIM_TADJ 258169b5a878SDan McDonald 258269b5a878SDan McDonald #define IXGBE_RXMTRL_V1_CTRLT_MASK 0x000000FF 258369b5a878SDan McDonald #define IXGBE_RXMTRL_V1_SYNC_MSG 0x00 258469b5a878SDan McDonald #define IXGBE_RXMTRL_V1_DELAY_REQ_MSG 0x01 258569b5a878SDan McDonald #define IXGBE_RXMTRL_V1_FOLLOWUP_MSG 0x02 258669b5a878SDan McDonald #define IXGBE_RXMTRL_V1_DELAY_RESP_MSG 0x03 258769b5a878SDan McDonald #define IXGBE_RXMTRL_V1_MGMT_MSG 0x04 258869b5a878SDan McDonald 258969b5a878SDan McDonald #define IXGBE_RXMTRL_V2_MSGID_MASK 0x0000FF00 259069b5a878SDan McDonald #define IXGBE_RXMTRL_V2_SYNC_MSG 0x0000 259169b5a878SDan McDonald #define IXGBE_RXMTRL_V2_DELAY_REQ_MSG 0x0100 259269b5a878SDan McDonald #define IXGBE_RXMTRL_V2_PDELAY_REQ_MSG 0x0200 259369b5a878SDan McDonald #define IXGBE_RXMTRL_V2_PDELAY_RESP_MSG 0x0300 259469b5a878SDan McDonald #define IXGBE_RXMTRL_V2_FOLLOWUP_MSG 0x0800 259569b5a878SDan McDonald #define IXGBE_RXMTRL_V2_DELAY_RESP_MSG 0x0900 259669b5a878SDan McDonald #define IXGBE_RXMTRL_V2_PDELAY_FOLLOWUP_MSG 0x0A00 259769b5a878SDan McDonald #define IXGBE_RXMTRL_V2_ANNOUNCE_MSG 0x0B00 259869b5a878SDan McDonald #define IXGBE_RXMTRL_V2_SIGNALLING_MSG 0x0C00 259969b5a878SDan McDonald #define IXGBE_RXMTRL_V2_MGMT_MSG 0x0D00 260069b5a878SDan McDonald 260169b5a878SDan McDonald #define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */ 260269b5a878SDan McDonald #define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/ 260369b5a878SDan McDonald #define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */ 260469b5a878SDan McDonald #define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */ 260569b5a878SDan McDonald #define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */ 260669b5a878SDan McDonald #define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */ 26079da57d7bSbt /* Receive Priority Flow Control Enable */ 260869b5a878SDan McDonald #define IXGBE_FCTRL_RPFCE 0x00004000 260969b5a878SDan McDonald #define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */ 261069b5a878SDan McDonald #define IXGBE_MFLCN_PMCF 0x00000001 /* Pass MAC Control Frames */ 261169b5a878SDan McDonald #define IXGBE_MFLCN_DPF 0x00000002 /* Discard Pause Frame */ 261269b5a878SDan McDonald #define IXGBE_MFLCN_RPFCE 0x00000004 /* Receive Priority FC Enable */ 261369b5a878SDan McDonald #define IXGBE_MFLCN_RFCE 0x00000008 /* Receive FC Enable */ 261469b5a878SDan McDonald #define IXGBE_MFLCN_RPFCE_MASK 0x00000FF4 /* Rx Priority FC bitmap mask */ 261569b5a878SDan McDonald #define IXGBE_MFLCN_RPFCE_SHIFT 4 /* Rx Priority FC bitmap shift */ 26169da57d7bSbt 26179da57d7bSbt /* Multiple Receive Queue Control */ 261869b5a878SDan McDonald #define IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */ 261969b5a878SDan McDonald #define IXGBE_MRQC_MRQE_MASK 0xF /* Bits 3:0 */ 262069b5a878SDan McDonald #define IXGBE_MRQC_RT8TCEN 0x00000002 /* 8 TC no RSS */ 262169b5a878SDan McDonald #define IXGBE_MRQC_RT4TCEN 0x00000003 /* 4 TC no RSS */ 262269b5a878SDan McDonald #define IXGBE_MRQC_RTRSS8TCEN 0x00000004 /* 8 TC w/ RSS */ 262369b5a878SDan McDonald #define IXGBE_MRQC_RTRSS4TCEN 0x00000005 /* 4 TC w/ RSS */ 262469b5a878SDan McDonald #define IXGBE_MRQC_VMDQEN 0x00000008 /* VMDq2 64 pools no RSS */ 262569b5a878SDan McDonald #define IXGBE_MRQC_VMDQRSS32EN 0x0000000A /* VMDq2 32 pools w/ RSS */ 262669b5a878SDan McDonald #define IXGBE_MRQC_VMDQRSS64EN 0x0000000B /* VMDq2 64 pools w/ RSS */ 262769b5a878SDan McDonald #define IXGBE_MRQC_VMDQRT8TCEN 0x0000000C /* VMDq2/RT 16 pool 8 TC */ 262869b5a878SDan McDonald #define IXGBE_MRQC_VMDQRT4TCEN 0x0000000D /* VMDq2/RT 32 pool 4 TC */ 2629*48ed61a7SRobert Mustacchi #define IXGBE_MRQC_L3L4TXSWEN 0x00008000 /* Enable L3/L4 Tx switch */ 263069b5a878SDan McDonald #define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000 263169b5a878SDan McDonald #define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 263269b5a878SDan McDonald #define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000 263363b3bba8SJerry Jelinek #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000 263469b5a878SDan McDonald #define IXGBE_MRQC_RSS_FIELD_IPV6_EX 0x00080000 263569b5a878SDan McDonald #define IXGBE_MRQC_RSS_FIELD_IPV6 0x00100000 263669b5a878SDan McDonald #define IXGBE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 263769b5a878SDan McDonald #define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 263869b5a878SDan McDonald #define IXGBE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 263963b3bba8SJerry Jelinek #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000 2640dc0cb1cdSDale Ghent #define IXGBE_MRQC_MULTIPLE_RSS 0x00002000 264169b5a878SDan McDonald #define IXGBE_MRQC_L3L4TXSWEN 0x00008000 264273cd555cSBin Tu - Sun Microsystems - Beijing China 264373cd555cSBin Tu - Sun Microsystems - Beijing China /* Queue Drop Enable */ 264469b5a878SDan McDonald #define IXGBE_QDE_ENABLE 0x00000001 2645dc0cb1cdSDale Ghent #define IXGBE_QDE_HIDE_VLAN 0x00000002 264669b5a878SDan McDonald #define IXGBE_QDE_IDX_MASK 0x00007F00 264769b5a878SDan McDonald #define IXGBE_QDE_IDX_SHIFT 8 264869b5a878SDan McDonald #define IXGBE_QDE_WRITE 0x00010000 264969b5a878SDan McDonald #define IXGBE_QDE_READ 0x00020000 265069b5a878SDan McDonald 265169b5a878SDan McDonald #define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 265269b5a878SDan McDonald #define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 265369b5a878SDan McDonald #define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */ 265469b5a878SDan McDonald #define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 265569b5a878SDan McDonald #define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 265669b5a878SDan McDonald #define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */ 265769b5a878SDan McDonald #define IXGBE_TXD_CMD_DEXT 0x20000000 /* Desc extension (0 = legacy) */ 265869b5a878SDan McDonald #define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 265969b5a878SDan McDonald #define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 266069b5a878SDan McDonald 266169b5a878SDan McDonald #define IXGBE_RXDADV_IPSEC_STATUS_SECP 0x00020000 266269b5a878SDan McDonald #define IXGBE_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000 266369b5a878SDan McDonald #define IXGBE_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000 266469b5a878SDan McDonald #define IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED 0x18000000 266569b5a878SDan McDonald #define IXGBE_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000 266673cd555cSBin Tu - Sun Microsystems - Beijing China /* Multiple Transmit Queue Command Register */ 266769b5a878SDan McDonald #define IXGBE_MTQC_RT_ENA 0x1 /* DCB Enable */ 266869b5a878SDan McDonald #define IXGBE_MTQC_VT_ENA 0x2 /* VMDQ2 Enable */ 266969b5a878SDan McDonald #define IXGBE_MTQC_64Q_1PB 0x0 /* 64 queues 1 pack buffer */ 267069b5a878SDan McDonald #define IXGBE_MTQC_32VF 0x8 /* 4 TX Queues per pool w/32VF's */ 267169b5a878SDan McDonald #define IXGBE_MTQC_64VF 0x4 /* 2 TX Queues per pool w/64VF's */ 267269b5a878SDan McDonald #define IXGBE_MTQC_4TC_4TQ 0x8 /* 4 TC if RT_ENA and VT_ENA */ 267369b5a878SDan McDonald #define IXGBE_MTQC_8TC_8TQ 0xC /* 8 TC if RT_ENA or 8 TQ if VT_ENA */ 267473cd555cSBin Tu - Sun Microsystems - Beijing China 26759da57d7bSbt /* Receive Descriptor bit definitions */ 267669b5a878SDan McDonald #define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */ 267769b5a878SDan McDonald #define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */ 267869b5a878SDan McDonald #define IXGBE_RXD_STAT_FLM 0x04 /* FDir Match */ 267969b5a878SDan McDonald #define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 268069b5a878SDan McDonald #define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0 /* Next Descriptor Index */ 268169b5a878SDan McDonald #define IXGBE_RXDADV_NEXTP_SHIFT 0x00000004 268269b5a878SDan McDonald #define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 268369b5a878SDan McDonald #define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */ 268469b5a878SDan McDonald #define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 268569b5a878SDan McDonald #define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 268669b5a878SDan McDonald #define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */ 2687dc0cb1cdSDale Ghent #define IXGBE_RXD_STAT_OUTERIPCS 0x100 /* Cloud IP xsum calculated */ 268869b5a878SDan McDonald #define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */ 268969b5a878SDan McDonald #define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ 269069b5a878SDan McDonald #define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ 269169b5a878SDan McDonald #define IXGBE_RXD_STAT_LLINT 0x800 /* Pkt caused Low Latency Interrupt */ 2692dc0cb1cdSDale Ghent #define IXGBE_RXD_STAT_TSIP 0x08000 /* Time Stamp in packet buffer */ 269369b5a878SDan McDonald #define IXGBE_RXD_STAT_TS 0x10000 /* Time Stamp */ 269469b5a878SDan McDonald #define IXGBE_RXD_STAT_SECP 0x20000 /* Security Processing */ 269569b5a878SDan McDonald #define IXGBE_RXD_STAT_LB 0x40000 /* Loopback Status */ 269669b5a878SDan McDonald #define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ 269769b5a878SDan McDonald #define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */ 269869b5a878SDan McDonald #define IXGBE_RXD_ERR_LE 0x02 /* Length Error */ 269969b5a878SDan McDonald #define IXGBE_RXD_ERR_PE 0x08 /* Packet Error */ 270069b5a878SDan McDonald #define IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */ 270169b5a878SDan McDonald #define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */ 270269b5a878SDan McDonald #define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */ 270369b5a878SDan McDonald #define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */ 270469b5a878SDan McDonald #define IXGBE_RXDADV_ERR_MASK 0xfff00000 /* RDESC.ERRORS mask */ 270569b5a878SDan McDonald #define IXGBE_RXDADV_ERR_SHIFT 20 /* RDESC.ERRORS shift */ 2706dc0cb1cdSDale Ghent #define IXGBE_RXDADV_ERR_OUTERIPER 0x04000000 /* CRC IP Header error */ 270769b5a878SDan McDonald #define IXGBE_RXDADV_ERR_RXE 0x20000000 /* Any MAC Error */ 2708dc0cb1cdSDale Ghent #define IXGBE_RXDADV_ERR_FCEOFE 0x80000000 /* FCEOFe/IPE */ 270969b5a878SDan McDonald #define IXGBE_RXDADV_ERR_FCERR 0x00700000 /* FCERR/FDIRERR */ 271069b5a878SDan McDonald #define IXGBE_RXDADV_ERR_FDIR_LEN 0x00100000 /* FDIR Length error */ 271169b5a878SDan McDonald #define IXGBE_RXDADV_ERR_FDIR_DROP 0x00200000 /* FDIR Drop error */ 271269b5a878SDan McDonald #define IXGBE_RXDADV_ERR_FDIR_COLL 0x00400000 /* FDIR Collision error */ 271369b5a878SDan McDonald #define IXGBE_RXDADV_ERR_HBO 0x00800000 /*Header Buffer Overflow */ 271469b5a878SDan McDonald #define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */ 271569b5a878SDan McDonald #define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */ 271669b5a878SDan McDonald #define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */ 271769b5a878SDan McDonald #define IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */ 271869b5a878SDan McDonald #define IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */ 271969b5a878SDan McDonald #define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */ 272069b5a878SDan McDonald #define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */ 272169b5a878SDan McDonald #define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 272269b5a878SDan McDonald #define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ 272369b5a878SDan McDonald #define IXGBE_RXD_PRI_SHIFT 13 272469b5a878SDan McDonald #define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */ 272569b5a878SDan McDonald #define IXGBE_RXD_CFI_SHIFT 12 272669b5a878SDan McDonald 272769b5a878SDan McDonald #define IXGBE_RXDADV_STAT_DD IXGBE_RXD_STAT_DD /* Done */ 272869b5a878SDan McDonald #define IXGBE_RXDADV_STAT_EOP IXGBE_RXD_STAT_EOP /* End of Packet */ 272969b5a878SDan McDonald #define IXGBE_RXDADV_STAT_FLM IXGBE_RXD_STAT_FLM /* FDir Match */ 273069b5a878SDan McDonald #define IXGBE_RXDADV_STAT_VP IXGBE_RXD_STAT_VP /* IEEE VLAN Pkt */ 273169b5a878SDan McDonald #define IXGBE_RXDADV_STAT_MASK 0x000fffff /* Stat/NEXTP: bit 0-19 */ 273269b5a878SDan McDonald #define IXGBE_RXDADV_STAT_FCEOFS 0x00000040 /* FCoE EOF/SOF Stat */ 273369b5a878SDan McDonald #define IXGBE_RXDADV_STAT_FCSTAT 0x00000030 /* FCoE Pkt Stat */ 273469b5a878SDan McDonald #define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */ 273569b5a878SDan McDonald #define IXGBE_RXDADV_STAT_FCSTAT_NODDP 0x00000010 /* 01: Ctxt w/o DDP */ 273669b5a878SDan McDonald #define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */ 273769b5a878SDan McDonald #define IXGBE_RXDADV_STAT_FCSTAT_DDP 0x00000030 /* 11: Ctxt w/ DDP */ 273869b5a878SDan McDonald #define IXGBE_RXDADV_STAT_TS 0x00010000 /* IEEE1588 Time Stamp */ 2739dc0cb1cdSDale Ghent #define IXGBE_RXDADV_STAT_TSIP 0x00008000 /* Time Stamp in packet buffer */ 274073cd555cSBin Tu - Sun Microsystems - Beijing China 274173cd555cSBin Tu - Sun Microsystems - Beijing China /* PSRTYPE bit definitions */ 274269b5a878SDan McDonald #define IXGBE_PSRTYPE_TCPHDR 0x00000010 274369b5a878SDan McDonald #define IXGBE_PSRTYPE_UDPHDR 0x00000020 274469b5a878SDan McDonald #define IXGBE_PSRTYPE_IPV4HDR 0x00000100 274569b5a878SDan McDonald #define IXGBE_PSRTYPE_IPV6HDR 0x00000200 274669b5a878SDan McDonald #define IXGBE_PSRTYPE_L2HDR 0x00001000 274773cd555cSBin Tu - Sun Microsystems - Beijing China 27489da57d7bSbt /* SRRCTL bit definitions */ 274969b5a878SDan McDonald #define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */ 2750dc0cb1cdSDale Ghent #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* 64byte resolution (>> 6) 2751dc0cb1cdSDale Ghent * + at bit 8 offset (<< 8) 2752dc0cb1cdSDale Ghent * = (<< 2) 2753dc0cb1cdSDale Ghent */ 275469b5a878SDan McDonald #define IXGBE_SRRCTL_RDMTS_SHIFT 22 275569b5a878SDan McDonald #define IXGBE_SRRCTL_RDMTS_MASK 0x01C00000 275669b5a878SDan McDonald #define IXGBE_SRRCTL_DROP_EN 0x10000000 275769b5a878SDan McDonald #define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F 275869b5a878SDan McDonald #define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00 275969b5a878SDan McDonald #define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000 276063b3bba8SJerry Jelinek #define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 276169b5a878SDan McDonald #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 276263b3bba8SJerry Jelinek #define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000 276363b3bba8SJerry Jelinek #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 276469b5a878SDan McDonald #define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000 276563b3bba8SJerry Jelinek 276669b5a878SDan McDonald #define IXGBE_RXDPS_HDRSTAT_HDRSP 0x00008000 276769b5a878SDan McDonald #define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF 276863b3bba8SJerry Jelinek 276969b5a878SDan McDonald #define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F 277069b5a878SDan McDonald #define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0 277169b5a878SDan McDonald #define IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0 277269b5a878SDan McDonald #define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0 277369b5a878SDan McDonald #define IXGBE_RXDADV_RSCCNT_MASK 0x001E0000 277469b5a878SDan McDonald #define IXGBE_RXDADV_RSCCNT_SHIFT 17 277569b5a878SDan McDonald #define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5 277669b5a878SDan McDonald #define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000 277769b5a878SDan McDonald #define IXGBE_RXDADV_SPH 0x8000 27789da57d7bSbt 27799da57d7bSbt /* RSS Hash results */ 278069b5a878SDan McDonald #define IXGBE_RXDADV_RSSTYPE_NONE 0x00000000 278169b5a878SDan McDonald #define IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001 278269b5a878SDan McDonald #define IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002 278369b5a878SDan McDonald #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003 278469b5a878SDan McDonald #define IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004 278569b5a878SDan McDonald #define IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005 278663b3bba8SJerry Jelinek #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006 278769b5a878SDan McDonald #define IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007 278869b5a878SDan McDonald #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008 278963b3bba8SJerry Jelinek #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009 27909da57d7bSbt 27919da57d7bSbt /* RSS Packet Types as indicated in the receive descriptor. */ 279269b5a878SDan McDonald #define IXGBE_RXDADV_PKTTYPE_NONE 0x00000000 279369b5a878SDan McDonald #define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPv4 hdr present */ 279469b5a878SDan McDonald #define IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPv4 hdr + extensions */ 279569b5a878SDan McDonald #define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPv6 hdr present */ 279669b5a878SDan McDonald #define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPv6 hdr + extensions */ 279769b5a878SDan McDonald #define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */ 279869b5a878SDan McDonald #define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */ 279969b5a878SDan McDonald #define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */ 280069b5a878SDan McDonald #define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */ 2801*48ed61a7SRobert Mustacchi #define IXGBE_RXDADV_PKTTYPE_GENEVE 0x00000800 /* GENEVE hdr present */ 2802dc0cb1cdSDale Ghent #define IXGBE_RXDADV_PKTTYPE_VXLAN 0x00000800 /* VXLAN hdr present */ 2803dc0cb1cdSDale Ghent #define IXGBE_RXDADV_PKTTYPE_TUNNEL 0x00010000 /* Tunnel type */ 280469b5a878SDan McDonald #define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */ 280569b5a878SDan McDonald #define IXGBE_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */ 280669b5a878SDan McDonald #define IXGBE_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */ 280769b5a878SDan McDonald #define IXGBE_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */ 280869b5a878SDan McDonald #define IXGBE_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */ 280969b5a878SDan McDonald #define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */ 281073cd555cSBin Tu - Sun Microsystems - Beijing China 281173cd555cSBin Tu - Sun Microsystems - Beijing China /* Security Processing bit Indication */ 281269b5a878SDan McDonald #define IXGBE_RXDADV_LNKSEC_STATUS_SECP 0x00020000 281369b5a878SDan McDonald #define IXGBE_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000 281469b5a878SDan McDonald #define IXGBE_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000 281569b5a878SDan McDonald #define IXGBE_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000 281669b5a878SDan McDonald #define IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000 28179da57d7bSbt 28189da57d7bSbt /* Masks to determine if packets should be dropped due to frame errors */ 281963b3bba8SJerry Jelinek #define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \ 282069b5a878SDan McDonald IXGBE_RXD_ERR_CE | \ 282169b5a878SDan McDonald IXGBE_RXD_ERR_LE | \ 282269b5a878SDan McDonald IXGBE_RXD_ERR_PE | \ 282369b5a878SDan McDonald IXGBE_RXD_ERR_OSE | \ 282469b5a878SDan McDonald IXGBE_RXD_ERR_USE) 282563b3bba8SJerry Jelinek 282663b3bba8SJerry Jelinek #define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \ 282769b5a878SDan McDonald IXGBE_RXDADV_ERR_CE | \ 282869b5a878SDan McDonald IXGBE_RXDADV_ERR_LE | \ 282969b5a878SDan McDonald IXGBE_RXDADV_ERR_PE | \ 283069b5a878SDan McDonald IXGBE_RXDADV_ERR_OSE | \ 283169b5a878SDan McDonald IXGBE_RXDADV_ERR_USE) 283269b5a878SDan McDonald 283369b5a878SDan McDonald #define IXGBE_RXDADV_ERR_FRAME_ERR_MASK_82599 IXGBE_RXDADV_ERR_RXE 28349da57d7bSbt 28359da57d7bSbt /* Multicast bit mask */ 283669b5a878SDan McDonald #define IXGBE_MCSTCTRL_MFE 0x4 28379da57d7bSbt 28389da57d7bSbt /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 283969b5a878SDan McDonald #define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8 284069b5a878SDan McDonald #define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8 284169b5a878SDan McDonald #define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024 28429da57d7bSbt 28439da57d7bSbt /* Vlan-specific macros */ 284469b5a878SDan McDonald #define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID in lower 12 bits */ 284569b5a878SDan McDonald #define IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority in upper 3 bits */ 284669b5a878SDan McDonald #define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */ 284769b5a878SDan McDonald #define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 28489da57d7bSbt 2849185c5677SPaul Guo /* SR-IOV specific macros */ 285069b5a878SDan McDonald #define IXGBE_MBVFICR_INDEX(vf_number) (vf_number >> 4) 285169b5a878SDan McDonald #define IXGBE_MBVFICR(_i) (0x00710 + ((_i) * 4)) 285269b5a878SDan McDonald #define IXGBE_VFLRE(_i) (((_i & 1) ? 0x001C0 : 0x00600)) 285369b5a878SDan McDonald #define IXGBE_VFLREC(_i) (0x00700 + ((_i) * 4)) 2854dc0cb1cdSDale Ghent /* Translated register #defines */ 2855dc0cb1cdSDale Ghent #define IXGBE_PVFCTRL(P) (0x00300 + (4 * (P))) 2856dc0cb1cdSDale Ghent #define IXGBE_PVFSTATUS(P) (0x00008 + (0 * (P))) 2857dc0cb1cdSDale Ghent #define IXGBE_PVFLINKS(P) (0x042A4 + (0 * (P))) 2858dc0cb1cdSDale Ghent #define IXGBE_PVFRTIMER(P) (0x00048 + (0 * (P))) 2859dc0cb1cdSDale Ghent #define IXGBE_PVFMAILBOX(P) (0x04C00 + (4 * (P))) 2860dc0cb1cdSDale Ghent #define IXGBE_PVFRXMEMWRAP(P) (0x03190 + (0 * (P))) 2861dc0cb1cdSDale Ghent #define IXGBE_PVTEICR(P) (0x00B00 + (4 * (P))) 2862dc0cb1cdSDale Ghent #define IXGBE_PVTEICS(P) (0x00C00 + (4 * (P))) 2863dc0cb1cdSDale Ghent #define IXGBE_PVTEIMS(P) (0x00D00 + (4 * (P))) 2864dc0cb1cdSDale Ghent #define IXGBE_PVTEIMC(P) (0x00E00 + (4 * (P))) 2865dc0cb1cdSDale Ghent #define IXGBE_PVTEIAC(P) (0x00F00 + (4 * (P))) 2866dc0cb1cdSDale Ghent #define IXGBE_PVTEIAM(P) (0x04D00 + (4 * (P))) 2867dc0cb1cdSDale Ghent #define IXGBE_PVTEITR(P) (((P) < 24) ? (0x00820 + ((P) * 4)) : \ 2868dc0cb1cdSDale Ghent (0x012300 + (((P) - 24) * 4))) 2869dc0cb1cdSDale Ghent #define IXGBE_PVTIVAR(P) (0x12500 + (4 * (P))) 2870dc0cb1cdSDale Ghent #define IXGBE_PVTIVAR_MISC(P) (0x04E00 + (4 * (P))) 2871dc0cb1cdSDale Ghent #define IXGBE_PVTRSCINT(P) (0x12000 + (4 * (P))) 2872dc0cb1cdSDale Ghent #define IXGBE_VFPBACL(P) (0x110C8 + (4 * (P))) 2873dc0cb1cdSDale Ghent #define IXGBE_PVFRDBAL(P) ((P < 64) ? (0x01000 + (0x40 * (P))) \ 2874dc0cb1cdSDale Ghent : (0x0D000 + (0x40 * ((P) - 64)))) 2875dc0cb1cdSDale Ghent #define IXGBE_PVFRDBAH(P) ((P < 64) ? (0x01004 + (0x40 * (P))) \ 2876dc0cb1cdSDale Ghent : (0x0D004 + (0x40 * ((P) - 64)))) 2877dc0cb1cdSDale Ghent #define IXGBE_PVFRDLEN(P) ((P < 64) ? (0x01008 + (0x40 * (P))) \ 2878dc0cb1cdSDale Ghent : (0x0D008 + (0x40 * ((P) - 64)))) 2879dc0cb1cdSDale Ghent #define IXGBE_PVFRDH(P) ((P < 64) ? (0x01010 + (0x40 * (P))) \ 2880dc0cb1cdSDale Ghent : (0x0D010 + (0x40 * ((P) - 64)))) 2881dc0cb1cdSDale Ghent #define IXGBE_PVFRDT(P) ((P < 64) ? (0x01018 + (0x40 * (P))) \ 2882dc0cb1cdSDale Ghent : (0x0D018 + (0x40 * ((P) - 64)))) 2883dc0cb1cdSDale Ghent #define IXGBE_PVFRXDCTL(P) ((P < 64) ? (0x01028 + (0x40 * (P))) \ 2884dc0cb1cdSDale Ghent : (0x0D028 + (0x40 * ((P) - 64)))) 2885dc0cb1cdSDale Ghent #define IXGBE_PVFSRRCTL(P) ((P < 64) ? (0x01014 + (0x40 * (P))) \ 2886dc0cb1cdSDale Ghent : (0x0D014 + (0x40 * ((P) - 64)))) 2887dc0cb1cdSDale Ghent #define IXGBE_PVFPSRTYPE(P) (0x0EA00 + (4 * (P))) 2888dc0cb1cdSDale Ghent #define IXGBE_PVFTDBAL(P) (0x06000 + (0x40 * (P))) 2889dc0cb1cdSDale Ghent #define IXGBE_PVFTDBAH(P) (0x06004 + (0x40 * (P))) 2890*48ed61a7SRobert Mustacchi #define IXGBE_PVFTDLEN(P) (0x06008 + (0x40 * (P))) 2891dc0cb1cdSDale Ghent #define IXGBE_PVFTDH(P) (0x06010 + (0x40 * (P))) 2892dc0cb1cdSDale Ghent #define IXGBE_PVFTDT(P) (0x06018 + (0x40 * (P))) 2893dc0cb1cdSDale Ghent #define IXGBE_PVFTXDCTL(P) (0x06028 + (0x40 * (P))) 2894dc0cb1cdSDale Ghent #define IXGBE_PVFTDWBAL(P) (0x06038 + (0x40 * (P))) 2895dc0cb1cdSDale Ghent #define IXGBE_PVFTDWBAH(P) (0x0603C + (0x40 * (P))) 2896dc0cb1cdSDale Ghent #define IXGBE_PVFDCA_RXCTRL(P) (((P) < 64) ? (0x0100C + (0x40 * (P))) \ 2897dc0cb1cdSDale Ghent : (0x0D00C + (0x40 * ((P) - 64)))) 2898dc0cb1cdSDale Ghent #define IXGBE_PVFDCA_TXCTRL(P) (0x0600C + (0x40 * (P))) 2899dc0cb1cdSDale Ghent #define IXGBE_PVFGPRC(x) (0x0101C + (0x40 * (x))) 2900dc0cb1cdSDale Ghent #define IXGBE_PVFGPTC(x) (0x08300 + (0x04 * (x))) 2901dc0cb1cdSDale Ghent #define IXGBE_PVFGORC_LSB(x) (0x01020 + (0x40 * (x))) 2902dc0cb1cdSDale Ghent #define IXGBE_PVFGORC_MSB(x) (0x0D020 + (0x40 * (x))) 2903dc0cb1cdSDale Ghent #define IXGBE_PVFGOTC_LSB(x) (0x08400 + (0x08 * (x))) 2904dc0cb1cdSDale Ghent #define IXGBE_PVFGOTC_MSB(x) (0x08404 + (0x08 * (x))) 2905dc0cb1cdSDale Ghent #define IXGBE_PVFMPRC(x) (0x0D01C + (0x40 * (x))) 2906dc0cb1cdSDale Ghent 2907dc0cb1cdSDale Ghent #define IXGBE_PVFTDWBALn(q_per_pool, vf_number, vf_q_index) \ 2908dc0cb1cdSDale Ghent (IXGBE_PVFTDWBAL((q_per_pool)*(vf_number) + (vf_q_index))) 2909dc0cb1cdSDale Ghent #define IXGBE_PVFTDWBAHn(q_per_pool, vf_number, vf_q_index) \ 2910dc0cb1cdSDale Ghent (IXGBE_PVFTDWBAH((q_per_pool)*(vf_number) + (vf_q_index))) 2911dc0cb1cdSDale Ghent 2912dc0cb1cdSDale Ghent #define IXGBE_PVFTDHn(q_per_pool, vf_number, vf_q_index) \ 2913dc0cb1cdSDale Ghent (IXGBE_PVFTDH((q_per_pool)*(vf_number) + (vf_q_index))) 2914dc0cb1cdSDale Ghent #define IXGBE_PVFTDTn(q_per_pool, vf_number, vf_q_index) \ 2915dc0cb1cdSDale Ghent (IXGBE_PVFTDT((q_per_pool)*(vf_number) + (vf_q_index))) 29165b6dd21fSchenlu chen - Sun Microsystems - Beijing China 291763b3bba8SJerry Jelinek /* Little Endian defines */ 291863b3bba8SJerry Jelinek #ifndef __le16 291963b3bba8SJerry Jelinek #define __le16 u16 292063b3bba8SJerry Jelinek #endif 292163b3bba8SJerry Jelinek #ifndef __le32 292263b3bba8SJerry Jelinek #define __le32 u32 292313740cb2SPaul Guo #endif 292463b3bba8SJerry Jelinek #ifndef __le64 292563b3bba8SJerry Jelinek #define __le64 u64 29269da57d7bSbt 29279da57d7bSbt #endif 292863b3bba8SJerry Jelinek #ifndef __be16 292963b3bba8SJerry Jelinek /* Big Endian defines */ 293063b3bba8SJerry Jelinek #define __be16 u16 293163b3bba8SJerry Jelinek #define __be32 u32 293263b3bba8SJerry Jelinek #define __be64 u64 293313740cb2SPaul Guo 293463b3bba8SJerry Jelinek #endif 293573cd555cSBin Tu - Sun Microsystems - Beijing China enum ixgbe_fdir_pballoc_type { 293669b5a878SDan McDonald IXGBE_FDIR_PBALLOC_NONE = 0, 293769b5a878SDan McDonald IXGBE_FDIR_PBALLOC_64K = 1, 293869b5a878SDan McDonald IXGBE_FDIR_PBALLOC_128K = 2, 293969b5a878SDan McDonald IXGBE_FDIR_PBALLOC_256K = 3, 294073cd555cSBin Tu - Sun Microsystems - Beijing China }; 294173cd555cSBin Tu - Sun Microsystems - Beijing China 294273cd555cSBin Tu - Sun Microsystems - Beijing China /* Flow Director register values */ 294369b5a878SDan McDonald #define IXGBE_FDIRCTRL_PBALLOC_64K 0x00000001 294469b5a878SDan McDonald #define IXGBE_FDIRCTRL_PBALLOC_128K 0x00000002 294569b5a878SDan McDonald #define IXGBE_FDIRCTRL_PBALLOC_256K 0x00000003 294669b5a878SDan McDonald #define IXGBE_FDIRCTRL_INIT_DONE 0x00000008 294769b5a878SDan McDonald #define IXGBE_FDIRCTRL_PERFECT_MATCH 0x00000010 294869b5a878SDan McDonald #define IXGBE_FDIRCTRL_REPORT_STATUS 0x00000020 294969b5a878SDan McDonald #define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS 0x00000080 295069b5a878SDan McDonald #define IXGBE_FDIRCTRL_DROP_Q_SHIFT 8 2951dc0cb1cdSDale Ghent #define IXGBE_FDIRCTRL_DROP_Q_MASK 0x00007F00 295269b5a878SDan McDonald #define IXGBE_FDIRCTRL_FLEX_SHIFT 16 2953dc0cb1cdSDale Ghent #define IXGBE_FDIRCTRL_DROP_NO_MATCH 0x00008000 2954dc0cb1cdSDale Ghent #define IXGBE_FDIRCTRL_FILTERMODE_SHIFT 21 2955dc0cb1cdSDale Ghent #define IXGBE_FDIRCTRL_FILTERMODE_MACVLAN 0x0001 /* bit 23:21, 001b */ 2956dc0cb1cdSDale Ghent #define IXGBE_FDIRCTRL_FILTERMODE_CLOUD 0x0002 /* bit 23:21, 010b */ 295769b5a878SDan McDonald #define IXGBE_FDIRCTRL_SEARCHLIM 0x00800000 2958dc0cb1cdSDale Ghent #define IXGBE_FDIRCTRL_FILTERMODE_MASK 0x00E00000 295969b5a878SDan McDonald #define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT 24 296069b5a878SDan McDonald #define IXGBE_FDIRCTRL_FULL_THRESH_MASK 0xF0000000 296169b5a878SDan McDonald #define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT 28 296269b5a878SDan McDonald 296369b5a878SDan McDonald #define IXGBE_FDIRTCPM_DPORTM_SHIFT 16 296469b5a878SDan McDonald #define IXGBE_FDIRUDPM_DPORTM_SHIFT 16 296569b5a878SDan McDonald #define IXGBE_FDIRIP6M_DIPM_SHIFT 16 296669b5a878SDan McDonald #define IXGBE_FDIRM_VLANID 0x00000001 296769b5a878SDan McDonald #define IXGBE_FDIRM_VLANP 0x00000002 296869b5a878SDan McDonald #define IXGBE_FDIRM_POOL 0x00000004 296969b5a878SDan McDonald #define IXGBE_FDIRM_L4P 0x00000008 297069b5a878SDan McDonald #define IXGBE_FDIRM_FLEX 0x00000010 297169b5a878SDan McDonald #define IXGBE_FDIRM_DIPv6 0x00000020 2972dc0cb1cdSDale Ghent #define IXGBE_FDIRM_L3P 0x00000040 2973dc0cb1cdSDale Ghent 2974dc0cb1cdSDale Ghent #define IXGBE_FDIRIP6M_INNER_MAC 0x03F0 /* bit 9:4 */ 2975dc0cb1cdSDale Ghent #define IXGBE_FDIRIP6M_TUNNEL_TYPE 0x0800 /* bit 11 */ 2976dc0cb1cdSDale Ghent #define IXGBE_FDIRIP6M_TNI_VNI 0xF000 /* bit 15:12 */ 2977dc0cb1cdSDale Ghent #define IXGBE_FDIRIP6M_TNI_VNI_24 0x1000 /* bit 12 */ 2978dc0cb1cdSDale Ghent #define IXGBE_FDIRIP6M_ALWAYS_MASK 0x040F /* bit 10, 3:0 */ 297969b5a878SDan McDonald 298069b5a878SDan McDonald #define IXGBE_FDIRFREE_FREE_MASK 0xFFFF 298169b5a878SDan McDonald #define IXGBE_FDIRFREE_FREE_SHIFT 0 298269b5a878SDan McDonald #define IXGBE_FDIRFREE_COLL_MASK 0x7FFF0000 298369b5a878SDan McDonald #define IXGBE_FDIRFREE_COLL_SHIFT 16 298469b5a878SDan McDonald #define IXGBE_FDIRLEN_MAXLEN_MASK 0x3F 298569b5a878SDan McDonald #define IXGBE_FDIRLEN_MAXLEN_SHIFT 0 298669b5a878SDan McDonald #define IXGBE_FDIRLEN_MAXHASH_MASK 0x7FFF0000 298769b5a878SDan McDonald #define IXGBE_FDIRLEN_MAXHASH_SHIFT 16 298869b5a878SDan McDonald #define IXGBE_FDIRUSTAT_ADD_MASK 0xFFFF 298969b5a878SDan McDonald #define IXGBE_FDIRUSTAT_ADD_SHIFT 0 299069b5a878SDan McDonald #define IXGBE_FDIRUSTAT_REMOVE_MASK 0xFFFF0000 299169b5a878SDan McDonald #define IXGBE_FDIRUSTAT_REMOVE_SHIFT 16 299269b5a878SDan McDonald #define IXGBE_FDIRFSTAT_FADD_MASK 0x00FF 299369b5a878SDan McDonald #define IXGBE_FDIRFSTAT_FADD_SHIFT 0 299469b5a878SDan McDonald #define IXGBE_FDIRFSTAT_FREMOVE_MASK 0xFF00 299569b5a878SDan McDonald #define IXGBE_FDIRFSTAT_FREMOVE_SHIFT 8 299669b5a878SDan McDonald #define IXGBE_FDIRPORT_DESTINATION_SHIFT 16 299769b5a878SDan McDonald #define IXGBE_FDIRVLAN_FLEX_SHIFT 16 299869b5a878SDan McDonald #define IXGBE_FDIRHASH_BUCKET_VALID_SHIFT 15 299969b5a878SDan McDonald #define IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT 16 300069b5a878SDan McDonald 300169b5a878SDan McDonald #define IXGBE_FDIRCMD_CMD_MASK 0x00000003 300269b5a878SDan McDonald #define IXGBE_FDIRCMD_CMD_ADD_FLOW 0x00000001 300369b5a878SDan McDonald #define IXGBE_FDIRCMD_CMD_REMOVE_FLOW 0x00000002 300469b5a878SDan McDonald #define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT 0x00000003 300569b5a878SDan McDonald #define IXGBE_FDIRCMD_FILTER_VALID 0x00000004 300669b5a878SDan McDonald #define IXGBE_FDIRCMD_FILTER_UPDATE 0x00000008 300769b5a878SDan McDonald #define IXGBE_FDIRCMD_IPv6DMATCH 0x00000010 300869b5a878SDan McDonald #define IXGBE_FDIRCMD_L4TYPE_UDP 0x00000020 300969b5a878SDan McDonald #define IXGBE_FDIRCMD_L4TYPE_TCP 0x00000040 301069b5a878SDan McDonald #define IXGBE_FDIRCMD_L4TYPE_SCTP 0x00000060 301169b5a878SDan McDonald #define IXGBE_FDIRCMD_IPV6 0x00000080 301269b5a878SDan McDonald #define IXGBE_FDIRCMD_CLEARHT 0x00000100 301369b5a878SDan McDonald #define IXGBE_FDIRCMD_DROP 0x00000200 301469b5a878SDan McDonald #define IXGBE_FDIRCMD_INT 0x00000400 301569b5a878SDan McDonald #define IXGBE_FDIRCMD_LAST 0x00000800 301669b5a878SDan McDonald #define IXGBE_FDIRCMD_COLLISION 0x00001000 301769b5a878SDan McDonald #define IXGBE_FDIRCMD_QUEUE_EN 0x00008000 301869b5a878SDan McDonald #define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT 5 301969b5a878SDan McDonald #define IXGBE_FDIRCMD_RX_QUEUE_SHIFT 16 3020dc0cb1cdSDale Ghent #define IXGBE_FDIRCMD_TUNNEL_FILTER_SHIFT 23 302169b5a878SDan McDonald #define IXGBE_FDIRCMD_VT_POOL_SHIFT 24 302269b5a878SDan McDonald #define IXGBE_FDIR_INIT_DONE_POLL 10 302369b5a878SDan McDonald #define IXGBE_FDIRCMD_CMD_POLL 10 3024dc0cb1cdSDale Ghent #define IXGBE_FDIRCMD_TUNNEL_FILTER 0x00800000 302569b5a878SDan McDonald #define IXGBE_FDIR_DROP_QUEUE 127 302669b5a878SDan McDonald 302769b5a878SDan McDonald 302869b5a878SDan McDonald /* Manageablility Host Interface defines */ 302969b5a878SDan McDonald #define IXGBE_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Num of bytes in range */ 303069b5a878SDan McDonald #define IXGBE_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Num of dwords in range */ 303169b5a878SDan McDonald #define IXGBE_HI_COMMAND_TIMEOUT 500 /* Process HI command limit */ 3032dc0cb1cdSDale Ghent #define IXGBE_HI_FLASH_ERASE_TIMEOUT 1000 /* Process Erase command limit */ 3033dc0cb1cdSDale Ghent #define IXGBE_HI_FLASH_UPDATE_TIMEOUT 5000 /* Process Update command limit */ 3034dc0cb1cdSDale Ghent #define IXGBE_HI_FLASH_APPLY_TIMEOUT 0 /* Process Apply command limit */ 3035dc0cb1cdSDale Ghent #define IXGBE_HI_PHY_MGMT_REQ_TIMEOUT 2000 /* Wait up to 2 seconds */ 303669b5a878SDan McDonald 303769b5a878SDan McDonald /* CEM Support */ 303869b5a878SDan McDonald #define FW_CEM_HDR_LEN 0x4 303969b5a878SDan McDonald #define FW_CEM_CMD_DRIVER_INFO 0xDD 304069b5a878SDan McDonald #define FW_CEM_CMD_DRIVER_INFO_LEN 0x5 304169b5a878SDan McDonald #define FW_CEM_CMD_RESERVED 0X0 304269b5a878SDan McDonald #define FW_CEM_UNUSED_VER 0x0 304369b5a878SDan McDonald #define FW_CEM_MAX_RETRIES 3 304469b5a878SDan McDonald #define FW_CEM_RESP_STATUS_SUCCESS 0x1 3045*48ed61a7SRobert Mustacchi #define FW_CEM_DRIVER_VERSION_SIZE 39 /* +9 would send 48 bytes to fw */ 3046dc0cb1cdSDale Ghent #define FW_READ_SHADOW_RAM_CMD 0x31 3047dc0cb1cdSDale Ghent #define FW_READ_SHADOW_RAM_LEN 0x6 3048dc0cb1cdSDale Ghent #define FW_WRITE_SHADOW_RAM_CMD 0x33 3049dc0cb1cdSDale Ghent #define FW_WRITE_SHADOW_RAM_LEN 0xA /* 8 plus 1 WORD to write */ 3050dc0cb1cdSDale Ghent #define FW_SHADOW_RAM_DUMP_CMD 0x36 3051dc0cb1cdSDale Ghent #define FW_SHADOW_RAM_DUMP_LEN 0 3052dc0cb1cdSDale Ghent #define FW_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */ 3053dc0cb1cdSDale Ghent #define FW_NVM_DATA_OFFSET 3 3054dc0cb1cdSDale Ghent #define FW_MAX_READ_BUFFER_SIZE 1024 3055dc0cb1cdSDale Ghent #define FW_DISABLE_RXEN_CMD 0xDE 3056dc0cb1cdSDale Ghent #define FW_DISABLE_RXEN_LEN 0x1 3057dc0cb1cdSDale Ghent #define FW_PHY_MGMT_REQ_CMD 0x20 3058*48ed61a7SRobert Mustacchi #define FW_PHY_TOKEN_REQ_CMD 0xA 3059*48ed61a7SRobert Mustacchi #define FW_PHY_TOKEN_REQ_LEN 2 3060*48ed61a7SRobert Mustacchi #define FW_PHY_TOKEN_REQ 0 3061*48ed61a7SRobert Mustacchi #define FW_PHY_TOKEN_REL 1 3062*48ed61a7SRobert Mustacchi #define FW_PHY_TOKEN_OK 1 3063*48ed61a7SRobert Mustacchi #define FW_PHY_TOKEN_RETRY 0x80 3064*48ed61a7SRobert Mustacchi #define FW_PHY_TOKEN_DELAY 5 /* milliseconds */ 3065*48ed61a7SRobert Mustacchi #define FW_PHY_TOKEN_WAIT 5 /* seconds */ 3066*48ed61a7SRobert Mustacchi #define FW_PHY_TOKEN_RETRIES ((FW_PHY_TOKEN_WAIT * 1000) / FW_PHY_TOKEN_DELAY) 3067dc0cb1cdSDale Ghent #define FW_INT_PHY_REQ_CMD 0xB 3068dc0cb1cdSDale Ghent #define FW_INT_PHY_REQ_LEN 10 3069dc0cb1cdSDale Ghent #define FW_INT_PHY_REQ_READ 0 3070dc0cb1cdSDale Ghent #define FW_INT_PHY_REQ_WRITE 1 3071*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_REQ_CMD 5 3072*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_DATA_COUNT 4 3073*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_REQ_LEN (4 + 4 * FW_PHY_ACT_DATA_COUNT) 3074*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_INIT_PHY 1 3075*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_SETUP_LINK 2 3076*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_LINK_SPEED_10 (1u << 0) 3077*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_LINK_SPEED_100 (1u << 1) 3078*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_LINK_SPEED_1G (1u << 2) 3079*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_LINK_SPEED_2_5G (1u << 3) 3080*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_LINK_SPEED_5G (1u << 4) 3081*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_LINK_SPEED_10G (1u << 5) 3082*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_LINK_SPEED_20G (1u << 6) 3083*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_LINK_SPEED_25G (1u << 7) 3084*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_LINK_SPEED_40G (1u << 8) 3085*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_LINK_SPEED_50G (1u << 9) 3086*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_LINK_SPEED_100G (1u << 10) 3087*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT 16 3088*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_SETUP_LINK_PAUSE_MASK (3u << \ 3089*48ed61a7SRobert Mustacchi FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT) 3090*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_SETUP_LINK_PAUSE_NONE 0u 3091*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_SETUP_LINK_PAUSE_TX 1u 3092*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_SETUP_LINK_PAUSE_RX 2u 3093*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX 3u 3094*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_SETUP_LINK_LP (1u << 18) 3095*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_SETUP_LINK_HP (1u << 19) 3096*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_SETUP_LINK_EEE (1u << 20) 3097*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_SETUP_LINK_AN (1u << 22) 3098*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_SETUP_LINK_RSP_DOWN (1u << 0) 3099*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_GET_LINK_INFO 3 3100*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_GET_LINK_INFO_EEE (1u << 19) 3101*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_GET_LINK_INFO_FC_TX (1u << 20) 3102*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_GET_LINK_INFO_FC_RX (1u << 21) 3103*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_GET_LINK_INFO_POWER (1u << 22) 3104*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE (1u << 24) 3105*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_GET_LINK_INFO_TEMP (1u << 25) 3106*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX (1u << 28) 3107*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX (1u << 29) 3108*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_FORCE_LINK_DOWN 4 3109*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_FORCE_LINK_DOWN_OFF (1u << 0) 3110*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_PHY_SW_RESET 5 3111*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_PHY_HW_RESET 6 3112*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_GET_PHY_INFO 7 3113*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_UD_2 0x1002 3114*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_UD_2_10G_KR_EEE (1u << 6) 3115*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_UD_2_10G_KX4_EEE (1u << 5) 3116*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_UD_2_1G_KX_EEE (1u << 4) 3117*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_UD_2_10G_T_EEE (1u << 3) 3118*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_UD_2_1G_T_EEE (1u << 2) 3119*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_UD_2_100M_TX_EEE (1u << 1) 3120*48ed61a7SRobert Mustacchi #define FW_PHY_ACT_RETRIES 50 3121*48ed61a7SRobert Mustacchi #define FW_PHY_INFO_SPEED_MASK 0xFFFu 3122*48ed61a7SRobert Mustacchi #define FW_PHY_INFO_ID_HI_MASK 0xFFFF0000u 3123*48ed61a7SRobert Mustacchi #define FW_PHY_INFO_ID_LO_MASK 0x0000FFFFu 312469b5a878SDan McDonald 312569b5a878SDan McDonald /* Host Interface Command Structures */ 312669b5a878SDan McDonald 3127*48ed61a7SRobert Mustacchi #pragma pack(push, 1) 3128*48ed61a7SRobert Mustacchi 312969b5a878SDan McDonald struct ixgbe_hic_hdr { 313069b5a878SDan McDonald u8 cmd; 313169b5a878SDan McDonald u8 buf_len; 313269b5a878SDan McDonald union { 313369b5a878SDan McDonald u8 cmd_resv; 313469b5a878SDan McDonald u8 ret_status; 313569b5a878SDan McDonald } cmd_or_resp; 313669b5a878SDan McDonald u8 checksum; 313769b5a878SDan McDonald }; 313869b5a878SDan McDonald 3139dc0cb1cdSDale Ghent struct ixgbe_hic_hdr2_req { 3140dc0cb1cdSDale Ghent u8 cmd; 3141dc0cb1cdSDale Ghent u8 buf_lenh; 3142dc0cb1cdSDale Ghent u8 buf_lenl; 3143dc0cb1cdSDale Ghent u8 checksum; 3144dc0cb1cdSDale Ghent }; 3145dc0cb1cdSDale Ghent 3146dc0cb1cdSDale Ghent struct ixgbe_hic_hdr2_rsp { 3147dc0cb1cdSDale Ghent u8 cmd; 3148dc0cb1cdSDale Ghent u8 buf_lenl; 3149dc0cb1cdSDale Ghent u8 buf_lenh_status; /* 7-5: high bits of buf_len, 4-0: status */ 3150dc0cb1cdSDale Ghent u8 checksum; 3151dc0cb1cdSDale Ghent }; 3152dc0cb1cdSDale Ghent 3153dc0cb1cdSDale Ghent union ixgbe_hic_hdr2 { 3154dc0cb1cdSDale Ghent struct ixgbe_hic_hdr2_req req; 3155dc0cb1cdSDale Ghent struct ixgbe_hic_hdr2_rsp rsp; 3156dc0cb1cdSDale Ghent }; 3157dc0cb1cdSDale Ghent 315869b5a878SDan McDonald struct ixgbe_hic_drv_info { 315969b5a878SDan McDonald struct ixgbe_hic_hdr hdr; 316069b5a878SDan McDonald u8 port_num; 316169b5a878SDan McDonald u8 ver_sub; 316269b5a878SDan McDonald u8 ver_build; 316369b5a878SDan McDonald u8 ver_min; 316469b5a878SDan McDonald u8 ver_maj; 316569b5a878SDan McDonald u8 pad; /* end spacing to ensure length is mult. of dword */ 316669b5a878SDan McDonald u16 pad2; /* end spacing to ensure length is mult. of dword2 */ 316769b5a878SDan McDonald }; 316873cd555cSBin Tu - Sun Microsystems - Beijing China 3169*48ed61a7SRobert Mustacchi struct ixgbe_hic_drv_info2 { 3170*48ed61a7SRobert Mustacchi struct ixgbe_hic_hdr hdr; 3171*48ed61a7SRobert Mustacchi u8 port_num; 3172*48ed61a7SRobert Mustacchi u8 ver_sub; 3173*48ed61a7SRobert Mustacchi u8 ver_build; 3174*48ed61a7SRobert Mustacchi u8 ver_min; 3175*48ed61a7SRobert Mustacchi u8 ver_maj; 3176*48ed61a7SRobert Mustacchi char driver_string[FW_CEM_DRIVER_VERSION_SIZE]; 3177*48ed61a7SRobert Mustacchi }; 3178*48ed61a7SRobert Mustacchi 3179dc0cb1cdSDale Ghent /* These need to be dword aligned */ 3180dc0cb1cdSDale Ghent struct ixgbe_hic_read_shadow_ram { 3181dc0cb1cdSDale Ghent union ixgbe_hic_hdr2 hdr; 3182dc0cb1cdSDale Ghent u32 address; 3183dc0cb1cdSDale Ghent u16 length; 3184dc0cb1cdSDale Ghent u16 pad2; 3185dc0cb1cdSDale Ghent u16 data; 3186dc0cb1cdSDale Ghent u16 pad3; 3187dc0cb1cdSDale Ghent }; 3188dc0cb1cdSDale Ghent 3189dc0cb1cdSDale Ghent struct ixgbe_hic_write_shadow_ram { 3190dc0cb1cdSDale Ghent union ixgbe_hic_hdr2 hdr; 3191dc0cb1cdSDale Ghent u32 address; 3192dc0cb1cdSDale Ghent u16 length; 3193dc0cb1cdSDale Ghent u16 pad2; 3194dc0cb1cdSDale Ghent u16 data; 3195dc0cb1cdSDale Ghent u16 pad3; 3196dc0cb1cdSDale Ghent }; 3197dc0cb1cdSDale Ghent 3198dc0cb1cdSDale Ghent struct ixgbe_hic_disable_rxen { 3199dc0cb1cdSDale Ghent struct ixgbe_hic_hdr hdr; 3200dc0cb1cdSDale Ghent u8 port_number; 3201dc0cb1cdSDale Ghent u8 pad2; 3202dc0cb1cdSDale Ghent u16 pad3; 3203dc0cb1cdSDale Ghent }; 3204dc0cb1cdSDale Ghent 3205*48ed61a7SRobert Mustacchi struct ixgbe_hic_phy_token_req { 3206*48ed61a7SRobert Mustacchi struct ixgbe_hic_hdr hdr; 3207*48ed61a7SRobert Mustacchi u8 port_number; 3208*48ed61a7SRobert Mustacchi u8 command_type; 3209*48ed61a7SRobert Mustacchi u16 pad; 3210*48ed61a7SRobert Mustacchi }; 3211*48ed61a7SRobert Mustacchi 3212dc0cb1cdSDale Ghent struct ixgbe_hic_internal_phy_req { 3213dc0cb1cdSDale Ghent struct ixgbe_hic_hdr hdr; 3214dc0cb1cdSDale Ghent u8 port_number; 3215dc0cb1cdSDale Ghent u8 command_type; 3216*48ed61a7SRobert Mustacchi __be16 address; 3217dc0cb1cdSDale Ghent u16 rsv1; 3218*48ed61a7SRobert Mustacchi __be32 write_data; 3219dc0cb1cdSDale Ghent u16 pad; 3220dc0cb1cdSDale Ghent }; 3221dc0cb1cdSDale Ghent 3222dc0cb1cdSDale Ghent struct ixgbe_hic_internal_phy_resp { 3223dc0cb1cdSDale Ghent struct ixgbe_hic_hdr hdr; 3224*48ed61a7SRobert Mustacchi __be32 read_data; 3225dc0cb1cdSDale Ghent }; 3226dc0cb1cdSDale Ghent 3227*48ed61a7SRobert Mustacchi struct ixgbe_hic_phy_activity_req { 3228*48ed61a7SRobert Mustacchi struct ixgbe_hic_hdr hdr; 3229*48ed61a7SRobert Mustacchi u8 port_number; 3230*48ed61a7SRobert Mustacchi u8 pad; 3231*48ed61a7SRobert Mustacchi __le16 activity_id; 3232*48ed61a7SRobert Mustacchi __be32 data[FW_PHY_ACT_DATA_COUNT]; 3233*48ed61a7SRobert Mustacchi }; 3234*48ed61a7SRobert Mustacchi 3235*48ed61a7SRobert Mustacchi struct ixgbe_hic_phy_activity_resp { 3236*48ed61a7SRobert Mustacchi struct ixgbe_hic_hdr hdr; 3237*48ed61a7SRobert Mustacchi __be32 data[FW_PHY_ACT_DATA_COUNT]; 3238*48ed61a7SRobert Mustacchi }; 3239*48ed61a7SRobert Mustacchi 3240*48ed61a7SRobert Mustacchi #pragma pack(pop) 3241dc0cb1cdSDale Ghent 32429da57d7bSbt /* Transmit Descriptor - Legacy */ 32439da57d7bSbt struct ixgbe_legacy_tx_desc { 324469b5a878SDan McDonald u64 buffer_addr; /* Address of the descriptor's data buffer */ 32459da57d7bSbt union { 32469da57d7bSbt __le32 data; 32479da57d7bSbt struct { 324869b5a878SDan McDonald __le16 length; /* Data buffer length */ 324969b5a878SDan McDonald u8 cso; /* Checksum offset */ 325069b5a878SDan McDonald u8 cmd; /* Descriptor control */ 32519da57d7bSbt } flags; 32529da57d7bSbt } lower; 32539da57d7bSbt union { 32549da57d7bSbt __le32 data; 32559da57d7bSbt struct { 325669b5a878SDan McDonald u8 status; /* Descriptor status */ 325769b5a878SDan McDonald u8 css; /* Checksum start */ 32589da57d7bSbt __le16 vlan; 32599da57d7bSbt } fields; 32609da57d7bSbt } upper; 32619da57d7bSbt }; 32629da57d7bSbt 32639da57d7bSbt /* Transmit Descriptor - Advanced */ 32649da57d7bSbt union ixgbe_adv_tx_desc { 32659da57d7bSbt struct { 326669b5a878SDan McDonald __le64 buffer_addr; /* Address of descriptor's data buf */ 32679da57d7bSbt __le32 cmd_type_len; 32689da57d7bSbt __le32 olinfo_status; 32699da57d7bSbt } read; 32709da57d7bSbt struct { 327169b5a878SDan McDonald __le64 rsvd; /* Reserved */ 32729da57d7bSbt __le32 nxtseq_seed; 32739da57d7bSbt __le32 status; 32749da57d7bSbt } wb; 32759da57d7bSbt }; 32769da57d7bSbt 32779da57d7bSbt /* Receive Descriptor - Legacy */ 32789da57d7bSbt struct ixgbe_legacy_rx_desc { 327963b3bba8SJerry Jelinek __le64 buffer_addr; /* Address of the descriptor's data buffer */ 328069b5a878SDan McDonald __le16 length; /* Length of data DMAed into data buffer */ 328169b5a878SDan McDonald __le16 csum; /* Packet checksum */ 328269b5a878SDan McDonald u8 status; /* Descriptor status */ 328369b5a878SDan McDonald u8 errors; /* Descriptor Errors */ 32849da57d7bSbt __le16 vlan; 32859da57d7bSbt }; 32869da57d7bSbt 32879da57d7bSbt /* Receive Descriptor - Advanced */ 32889da57d7bSbt union ixgbe_adv_rx_desc { 32899da57d7bSbt struct { 32909da57d7bSbt __le64 pkt_addr; /* Packet buffer address */ 32919da57d7bSbt __le64 hdr_addr; /* Header buffer address */ 32929da57d7bSbt } read; 32939da57d7bSbt struct { 32949da57d7bSbt struct { 32959da57d7bSbt union { 32969da57d7bSbt __le32 data; 32979da57d7bSbt struct { 329863b3bba8SJerry Jelinek __le16 pkt_info; /* RSS, Pkt type */ 329963b3bba8SJerry Jelinek __le16 hdr_info; /* Splithdr, hdrlen */ 33009da57d7bSbt } hs_rss; 33019da57d7bSbt } lo_dword; 33029da57d7bSbt union { 33039da57d7bSbt __le32 rss; /* RSS Hash */ 33049da57d7bSbt struct { 33059da57d7bSbt __le16 ip_id; /* IP id */ 33069da57d7bSbt __le16 csum; /* Packet Checksum */ 33079da57d7bSbt } csum_ip; 33089da57d7bSbt } hi_dword; 33099da57d7bSbt } lower; 33109da57d7bSbt struct { 33119da57d7bSbt __le32 status_error; /* ext status/error */ 33129da57d7bSbt __le16 length; /* Packet length */ 33139da57d7bSbt __le16 vlan; /* VLAN tag */ 33149da57d7bSbt } upper; 33159da57d7bSbt } wb; /* writeback */ 33169da57d7bSbt }; 33179da57d7bSbt 33189da57d7bSbt /* Context descriptors */ 33199da57d7bSbt struct ixgbe_adv_tx_context_desc { 33209da57d7bSbt __le32 vlan_macip_lens; 33219da57d7bSbt __le32 seqnum_seed; 33229da57d7bSbt __le32 type_tucmd_mlhl; 33239da57d7bSbt __le32 mss_l4len_idx; 33249da57d7bSbt }; 33259da57d7bSbt 33269da57d7bSbt /* Adv Transmit Descriptor Config Masks */ 332769b5a878SDan McDonald #define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF /* Data buf length(bytes) */ 332869b5a878SDan McDonald #define IXGBE_ADVTXD_MAC_LINKSEC 0x00040000 /* Insert LinkSec */ 332969b5a878SDan McDonald #define IXGBE_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 time stamp */ 333069b5a878SDan McDonald #define IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK 0x000003FF /* IPSec SA index */ 333169b5a878SDan McDonald #define IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK 0x000001FF /* IPSec ESP length */ 333269b5a878SDan McDonald #define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */ 333369b5a878SDan McDonald #define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Adv Context Desc */ 333469b5a878SDan McDonald #define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Adv Data Descriptor */ 333569b5a878SDan McDonald #define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */ 333669b5a878SDan McDonald #define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */ 333769b5a878SDan McDonald #define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */ 333869b5a878SDan McDonald #define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */ 333969b5a878SDan McDonald #define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext 1=Adv */ 334069b5a878SDan McDonald #define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */ 334169b5a878SDan McDonald #define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ 334269b5a878SDan McDonald #define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */ 334369b5a878SDan McDonald #define IXGBE_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED pres in WB */ 334469b5a878SDan McDonald #define IXGBE_ADVTXD_STAT_RSV 0x0000000C /* STA Reserved */ 334569b5a878SDan McDonald #define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */ 334669b5a878SDan McDonald #define IXGBE_ADVTXD_CC 0x00000080 /* Check Context */ 334769b5a878SDan McDonald #define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */ 334869b5a878SDan McDonald #define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \ 334969b5a878SDan McDonald IXGBE_ADVTXD_POPTS_SHIFT) 335069b5a878SDan McDonald #define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \ 335169b5a878SDan McDonald IXGBE_ADVTXD_POPTS_SHIFT) 335269b5a878SDan McDonald #define IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */ 335369b5a878SDan McDonald #define IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */ 335469b5a878SDan McDonald #define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */ 335569b5a878SDan McDonald /* 1st&Last TSO-full iSCSI PDU */ 335669b5a878SDan McDonald #define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 335769b5a878SDan McDonald #define IXGBE_ADVTXD_POPTS_RSV 0x00002000 /* POPTS Reserved */ 335869b5a878SDan McDonald #define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ 335969b5a878SDan McDonald #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ 336069b5a878SDan McDonald #define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */ 336169b5a878SDan McDonald #define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ 336269b5a878SDan McDonald #define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */ 336369b5a878SDan McDonald #define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */ 336469b5a878SDan McDonald #define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ 336569b5a878SDan McDonald #define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */ 3366*48ed61a7SRobert Mustacchi #define IXGBE_ADVTXD_TUCMD_L4T_RSV 0x00001800 /* RSV L4 Packet TYPE */ 336769b5a878SDan McDonald #define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /* req Markers and CRC */ 336869b5a878SDan McDonald #define IXGBE_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */ 336963b3bba8SJerry Jelinek #define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */ 337063b3bba8SJerry Jelinek #define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */ 337169b5a878SDan McDonald #define IXGBE_ADVTXT_TUCMD_FCOE 0x00008000 /* FCoE Frame Type */ 337269b5a878SDan McDonald #define IXGBE_ADVTXD_FCOEF_EOF_MASK (0x3 << 10) /* FC EOF index */ 337369b5a878SDan McDonald #define IXGBE_ADVTXD_FCOEF_SOF ((1 << 2) << 10) /* FC SOF index */ 337469b5a878SDan McDonald #define IXGBE_ADVTXD_FCOEF_PARINC ((1 << 3) << 10) /* Rel_Off in F_CTL */ 337569b5a878SDan McDonald #define IXGBE_ADVTXD_FCOEF_ORIE ((1 << 4) << 10) /* Orientation End */ 337669b5a878SDan McDonald #define IXGBE_ADVTXD_FCOEF_ORIS ((1 << 5) << 10) /* Orientation Start */ 337769b5a878SDan McDonald #define IXGBE_ADVTXD_FCOEF_EOF_N (0x0 << 10) /* 00: EOFn */ 337869b5a878SDan McDonald #define IXGBE_ADVTXD_FCOEF_EOF_T (0x1 << 10) /* 01: EOFt */ 337969b5a878SDan McDonald #define IXGBE_ADVTXD_FCOEF_EOF_NI (0x2 << 10) /* 10: EOFni */ 338069b5a878SDan McDonald #define IXGBE_ADVTXD_FCOEF_EOF_A (0x3 << 10) /* 11: EOFa */ 338169b5a878SDan McDonald #define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ 338269b5a878SDan McDonald #define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ 33839da57d7bSbt 3384dc0cb1cdSDale Ghent #define IXGBE_ADVTXD_OUTER_IPLEN 16 /* Adv ctxt OUTERIPLEN shift */ 3385dc0cb1cdSDale Ghent #define IXGBE_ADVTXD_TUNNEL_LEN 24 /* Adv ctxt TUNNELLEN shift */ 3386dc0cb1cdSDale Ghent #define IXGBE_ADVTXD_TUNNEL_TYPE_SHIFT 16 /* Adv Tx Desc Tunnel Type shift */ 3387dc0cb1cdSDale Ghent #define IXGBE_ADVTXD_OUTERIPCS_SHIFT 17 /* Adv Tx Desc OUTERIPCS Shift */ 3388dc0cb1cdSDale Ghent #define IXGBE_ADVTXD_TUNNEL_TYPE_NVGRE 1 /* Adv Tx Desc Tunnel Type NVGRE */ 3389*48ed61a7SRobert Mustacchi /* Adv Tx Desc OUTERIPCS Shift for X550EM_a */ 3390*48ed61a7SRobert Mustacchi #define IXGBE_ADVTXD_OUTERIPCS_SHIFT_X550EM_a 26 33919da57d7bSbt /* Autonegotiation advertised speeds */ 33929da57d7bSbt typedef u32 ixgbe_autoneg_advertised; 33939da57d7bSbt /* Link speed */ 33949da57d7bSbt typedef u32 ixgbe_link_speed; 339569b5a878SDan McDonald #define IXGBE_LINK_SPEED_UNKNOWN 0 3396*48ed61a7SRobert Mustacchi #define IXGBE_LINK_SPEED_10_FULL 0x0002 339769b5a878SDan McDonald #define IXGBE_LINK_SPEED_100_FULL 0x0008 339869b5a878SDan McDonald #define IXGBE_LINK_SPEED_1GB_FULL 0x0020 3399dc0cb1cdSDale Ghent #define IXGBE_LINK_SPEED_2_5GB_FULL 0x0400 3400dc0cb1cdSDale Ghent #define IXGBE_LINK_SPEED_5GB_FULL 0x0800 340169b5a878SDan McDonald #define IXGBE_LINK_SPEED_10GB_FULL 0x0080 340269b5a878SDan McDonald #define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \ 340369b5a878SDan McDonald IXGBE_LINK_SPEED_10GB_FULL) 340469b5a878SDan McDonald #define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \ 340569b5a878SDan McDonald IXGBE_LINK_SPEED_1GB_FULL | \ 340669b5a878SDan McDonald IXGBE_LINK_SPEED_10GB_FULL) 340763b3bba8SJerry Jelinek 340813740cb2SPaul Guo /* Physical layer type */ 3409*48ed61a7SRobert Mustacchi typedef u64 ixgbe_physical_layer; 341069b5a878SDan McDonald #define IXGBE_PHYSICAL_LAYER_UNKNOWN 0 3411*48ed61a7SRobert Mustacchi #define IXGBE_PHYSICAL_LAYER_10GBASE_T 0x00001 3412*48ed61a7SRobert Mustacchi #define IXGBE_PHYSICAL_LAYER_1000BASE_T 0x00002 3413*48ed61a7SRobert Mustacchi #define IXGBE_PHYSICAL_LAYER_100BASE_TX 0x00004 3414*48ed61a7SRobert Mustacchi #define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x00008 3415*48ed61a7SRobert Mustacchi #define IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x00010 3416*48ed61a7SRobert Mustacchi #define IXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x00020 3417*48ed61a7SRobert Mustacchi #define IXGBE_PHYSICAL_LAYER_10GBASE_SR 0x00040 3418*48ed61a7SRobert Mustacchi #define IXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x00080 3419*48ed61a7SRobert Mustacchi #define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x00100 3420*48ed61a7SRobert Mustacchi #define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x00200 3421*48ed61a7SRobert Mustacchi #define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x00400 3422*48ed61a7SRobert Mustacchi #define IXGBE_PHYSICAL_LAYER_10GBASE_KR 0x00800 3423*48ed61a7SRobert Mustacchi #define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x01000 3424*48ed61a7SRobert Mustacchi #define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA 0x02000 3425*48ed61a7SRobert Mustacchi #define IXGBE_PHYSICAL_LAYER_1000BASE_SX 0x04000 3426*48ed61a7SRobert Mustacchi #define IXGBE_PHYSICAL_LAYER_10BASE_T 0x08000 3427*48ed61a7SRobert Mustacchi #define IXGBE_PHYSICAL_LAYER_2500BASE_KX 0x10000 342869b5a878SDan McDonald 342969b5a878SDan McDonald /* Flow Control Data Sheet defined values 343069b5a878SDan McDonald * Calculation and defines taken from 802.1bb Annex O 343169b5a878SDan McDonald */ 343269b5a878SDan McDonald 343369b5a878SDan McDonald /* BitTimes (BT) conversion */ 343469b5a878SDan McDonald #define IXGBE_BT2KB(BT) ((BT + (8 * 1024 - 1)) / (8 * 1024)) 343569b5a878SDan McDonald #define IXGBE_B2BT(BT) (BT * 8) 343669b5a878SDan McDonald 343769b5a878SDan McDonald /* Calculate Delay to respond to PFC */ 343869b5a878SDan McDonald #define IXGBE_PFC_D 672 343969b5a878SDan McDonald 344069b5a878SDan McDonald /* Calculate Cable Delay */ 344169b5a878SDan McDonald #define IXGBE_CABLE_DC 5556 /* Delay Copper */ 344269b5a878SDan McDonald #define IXGBE_CABLE_DO 5000 /* Delay Optical */ 344369b5a878SDan McDonald 344469b5a878SDan McDonald /* Calculate Interface Delay X540 */ 344569b5a878SDan McDonald #define IXGBE_PHY_DC 25600 /* Delay 10G BASET */ 344669b5a878SDan McDonald #define IXGBE_MAC_DC 8192 /* Delay Copper XAUI interface */ 344769b5a878SDan McDonald #define IXGBE_XAUI_DC (2 * 2048) /* Delay Copper Phy */ 344869b5a878SDan McDonald 344969b5a878SDan McDonald #define IXGBE_ID_X540 (IXGBE_MAC_DC + IXGBE_XAUI_DC + IXGBE_PHY_DC) 345069b5a878SDan McDonald 345169b5a878SDan McDonald /* Calculate Interface Delay 82598, 82599 */ 345269b5a878SDan McDonald #define IXGBE_PHY_D 12800 345369b5a878SDan McDonald #define IXGBE_MAC_D 4096 345469b5a878SDan McDonald #define IXGBE_XAUI_D (2 * 1024) 345569b5a878SDan McDonald 345669b5a878SDan McDonald #define IXGBE_ID (IXGBE_MAC_D + IXGBE_XAUI_D + IXGBE_PHY_D) 345769b5a878SDan McDonald 345869b5a878SDan McDonald /* Calculate Delay incurred from higher layer */ 345969b5a878SDan McDonald #define IXGBE_HD 6144 346069b5a878SDan McDonald 346169b5a878SDan McDonald /* Calculate PCI Bus delay for low thresholds */ 346269b5a878SDan McDonald #define IXGBE_PCI_DELAY 10000 346369b5a878SDan McDonald 346469b5a878SDan McDonald /* Calculate X540 delay value in bit times */ 346569b5a878SDan McDonald #define IXGBE_DV_X540(_max_frame_link, _max_frame_tc) \ 346669b5a878SDan McDonald ((36 * \ 346769b5a878SDan McDonald (IXGBE_B2BT(_max_frame_link) + \ 346869b5a878SDan McDonald IXGBE_PFC_D + \ 346969b5a878SDan McDonald (2 * IXGBE_CABLE_DC) + \ 347069b5a878SDan McDonald (2 * IXGBE_ID_X540) + \ 347169b5a878SDan McDonald IXGBE_HD) / 25 + 1) + \ 347269b5a878SDan McDonald 2 * IXGBE_B2BT(_max_frame_tc)) 347369b5a878SDan McDonald 347469b5a878SDan McDonald /* Calculate 82599, 82598 delay value in bit times */ 347569b5a878SDan McDonald #define IXGBE_DV(_max_frame_link, _max_frame_tc) \ 347669b5a878SDan McDonald ((36 * \ 347769b5a878SDan McDonald (IXGBE_B2BT(_max_frame_link) + \ 347869b5a878SDan McDonald IXGBE_PFC_D + \ 347969b5a878SDan McDonald (2 * IXGBE_CABLE_DC) + \ 348069b5a878SDan McDonald (2 * IXGBE_ID) + \ 348169b5a878SDan McDonald IXGBE_HD) / 25 + 1) + \ 348269b5a878SDan McDonald 2 * IXGBE_B2BT(_max_frame_tc)) 348369b5a878SDan McDonald 348469b5a878SDan McDonald /* Calculate low threshold delay values */ 348569b5a878SDan McDonald #define IXGBE_LOW_DV_X540(_max_frame_tc) \ 348669b5a878SDan McDonald (2 * IXGBE_B2BT(_max_frame_tc) + \ 348769b5a878SDan McDonald (36 * IXGBE_PCI_DELAY / 25) + 1) 348869b5a878SDan McDonald #define IXGBE_LOW_DV(_max_frame_tc) \ 348969b5a878SDan McDonald (2 * IXGBE_LOW_DV_X540(_max_frame_tc)) 349073cd555cSBin Tu - Sun Microsystems - Beijing China 349173cd555cSBin Tu - Sun Microsystems - Beijing China /* Software ATR hash keys */ 349269b5a878SDan McDonald #define IXGBE_ATR_BUCKET_HASH_KEY 0x3DAD14E2 349369b5a878SDan McDonald #define IXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614 349463b3bba8SJerry Jelinek 349563b3bba8SJerry Jelinek /* Software ATR input stream values and masks */ 349669b5a878SDan McDonald #define IXGBE_ATR_HASH_MASK 0x7fff 349769b5a878SDan McDonald #define IXGBE_ATR_L4TYPE_MASK 0x3 349869b5a878SDan McDonald #define IXGBE_ATR_L4TYPE_UDP 0x1 349969b5a878SDan McDonald #define IXGBE_ATR_L4TYPE_TCP 0x2 350069b5a878SDan McDonald #define IXGBE_ATR_L4TYPE_SCTP 0x3 350169b5a878SDan McDonald #define IXGBE_ATR_L4TYPE_IPV6_MASK 0x4 3502dc0cb1cdSDale Ghent #define IXGBE_ATR_L4TYPE_TUNNEL_MASK 0x10 350363b3bba8SJerry Jelinek enum ixgbe_atr_flow_type { 350469b5a878SDan McDonald IXGBE_ATR_FLOW_TYPE_IPV4 = 0x0, 350569b5a878SDan McDonald IXGBE_ATR_FLOW_TYPE_UDPV4 = 0x1, 350669b5a878SDan McDonald IXGBE_ATR_FLOW_TYPE_TCPV4 = 0x2, 350769b5a878SDan McDonald IXGBE_ATR_FLOW_TYPE_SCTPV4 = 0x3, 350869b5a878SDan McDonald IXGBE_ATR_FLOW_TYPE_IPV6 = 0x4, 350969b5a878SDan McDonald IXGBE_ATR_FLOW_TYPE_UDPV6 = 0x5, 351069b5a878SDan McDonald IXGBE_ATR_FLOW_TYPE_TCPV6 = 0x6, 351169b5a878SDan McDonald IXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7, 3512dc0cb1cdSDale Ghent IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4 = 0x10, 3513dc0cb1cdSDale Ghent IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4 = 0x11, 3514dc0cb1cdSDale Ghent IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4 = 0x12, 3515dc0cb1cdSDale Ghent IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4 = 0x13, 3516dc0cb1cdSDale Ghent IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV6 = 0x14, 3517dc0cb1cdSDale Ghent IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV6 = 0x15, 3518dc0cb1cdSDale Ghent IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV6 = 0x16, 3519dc0cb1cdSDale Ghent IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV6 = 0x17, 352063b3bba8SJerry Jelinek }; 352173cd555cSBin Tu - Sun Microsystems - Beijing China 352273cd555cSBin Tu - Sun Microsystems - Beijing China /* Flow Director ATR input struct. */ 352363b3bba8SJerry Jelinek union ixgbe_atr_input { 352473cd555cSBin Tu - Sun Microsystems - Beijing China /* 352573cd555cSBin Tu - Sun Microsystems - Beijing China * Byte layout in order, all values with MSB first: 352673cd555cSBin Tu - Sun Microsystems - Beijing China * 352769b5a878SDan McDonald * vm_pool - 1 byte 352869b5a878SDan McDonald * flow_type - 1 byte 352969b5a878SDan McDonald * vlan_id - 2 bytes 353069b5a878SDan McDonald * src_ip - 16 bytes 3531dc0cb1cdSDale Ghent * inner_mac - 6 bytes 3532dc0cb1cdSDale Ghent * cloud_mode - 2 bytes 3533dc0cb1cdSDale Ghent * tni_vni - 4 bytes 353469b5a878SDan McDonald * dst_ip - 16 bytes 353569b5a878SDan McDonald * src_port - 2 bytes 353669b5a878SDan McDonald * dst_port - 2 bytes 353769b5a878SDan McDonald * flex_bytes - 2 bytes 353869b5a878SDan McDonald * bkt_hash - 2 bytes 353973cd555cSBin Tu - Sun Microsystems - Beijing China */ 354063b3bba8SJerry Jelinek struct { 354169b5a878SDan McDonald u8 vm_pool; 354269b5a878SDan McDonald u8 flow_type; 354363b3bba8SJerry Jelinek __be16 vlan_id; 354463b3bba8SJerry Jelinek __be32 dst_ip[4]; 354563b3bba8SJerry Jelinek __be32 src_ip[4]; 3546dc0cb1cdSDale Ghent u8 inner_mac[6]; 3547dc0cb1cdSDale Ghent __be16 tunnel_type; 3548dc0cb1cdSDale Ghent __be32 tni_vni; 354963b3bba8SJerry Jelinek __be16 src_port; 355063b3bba8SJerry Jelinek __be16 dst_port; 355163b3bba8SJerry Jelinek __be16 flex_bytes; 355269b5a878SDan McDonald __be16 bkt_hash; 355363b3bba8SJerry Jelinek } formatted; 3554dc0cb1cdSDale Ghent __be32 dword_stream[14]; 355573cd555cSBin Tu - Sun Microsystems - Beijing China }; 355613740cb2SPaul Guo 355763b3bba8SJerry Jelinek /* Flow Director compressed ATR hash input struct */ 355863b3bba8SJerry Jelinek union ixgbe_atr_hash_dword { 355963b3bba8SJerry Jelinek struct { 356063b3bba8SJerry Jelinek u8 vm_pool; 356163b3bba8SJerry Jelinek u8 flow_type; 356263b3bba8SJerry Jelinek __be16 vlan_id; 356363b3bba8SJerry Jelinek } formatted; 356463b3bba8SJerry Jelinek __be32 ip; 356563b3bba8SJerry Jelinek struct { 356663b3bba8SJerry Jelinek __be16 src; 356763b3bba8SJerry Jelinek __be16 dst; 356863b3bba8SJerry Jelinek } port; 356963b3bba8SJerry Jelinek __be16 flex_bytes; 357063b3bba8SJerry Jelinek __be32 dword; 357163b3bba8SJerry Jelinek }; 357263b3bba8SJerry Jelinek 357363b3bba8SJerry Jelinek 3574dc0cb1cdSDale Ghent #define IXGBE_MVALS_INIT(m) \ 3575dc0cb1cdSDale Ghent IXGBE_CAT(EEC, m), \ 3576dc0cb1cdSDale Ghent IXGBE_CAT(FLA, m), \ 3577dc0cb1cdSDale Ghent IXGBE_CAT(GRC, m), \ 3578dc0cb1cdSDale Ghent IXGBE_CAT(SRAMREL, m), \ 3579dc0cb1cdSDale Ghent IXGBE_CAT(FACTPS, m), \ 3580dc0cb1cdSDale Ghent IXGBE_CAT(SWSM, m), \ 3581dc0cb1cdSDale Ghent IXGBE_CAT(SWFW_SYNC, m), \ 3582dc0cb1cdSDale Ghent IXGBE_CAT(FWSM, m), \ 3583dc0cb1cdSDale Ghent IXGBE_CAT(SDP0_GPIEN, m), \ 3584dc0cb1cdSDale Ghent IXGBE_CAT(SDP1_GPIEN, m), \ 3585dc0cb1cdSDale Ghent IXGBE_CAT(SDP2_GPIEN, m), \ 3586dc0cb1cdSDale Ghent IXGBE_CAT(EICR_GPI_SDP0, m), \ 3587dc0cb1cdSDale Ghent IXGBE_CAT(EICR_GPI_SDP1, m), \ 3588dc0cb1cdSDale Ghent IXGBE_CAT(EICR_GPI_SDP2, m), \ 3589dc0cb1cdSDale Ghent IXGBE_CAT(CIAA, m), \ 3590dc0cb1cdSDale Ghent IXGBE_CAT(CIAD, m), \ 3591dc0cb1cdSDale Ghent IXGBE_CAT(I2C_CLK_IN, m), \ 3592dc0cb1cdSDale Ghent IXGBE_CAT(I2C_CLK_OUT, m), \ 3593dc0cb1cdSDale Ghent IXGBE_CAT(I2C_DATA_IN, m), \ 3594dc0cb1cdSDale Ghent IXGBE_CAT(I2C_DATA_OUT, m), \ 3595dc0cb1cdSDale Ghent IXGBE_CAT(I2C_DATA_OE_N_EN, m), \ 3596dc0cb1cdSDale Ghent IXGBE_CAT(I2C_BB_EN, m), \ 3597dc0cb1cdSDale Ghent IXGBE_CAT(I2C_CLK_OE_N_EN, m), \ 3598dc0cb1cdSDale Ghent IXGBE_CAT(I2CCTL, m) 3599dc0cb1cdSDale Ghent 3600dc0cb1cdSDale Ghent enum ixgbe_mvals { 3601dc0cb1cdSDale Ghent IXGBE_MVALS_INIT(_IDX), 3602dc0cb1cdSDale Ghent IXGBE_MVALS_IDX_LIMIT 3603dc0cb1cdSDale Ghent }; 3604dc0cb1cdSDale Ghent 36055b6dd21fSchenlu chen - Sun Microsystems - Beijing China /* 36065b6dd21fSchenlu chen - Sun Microsystems - Beijing China * Unavailable: The FCoE Boot Option ROM is not present in the flash. 36075b6dd21fSchenlu chen - Sun Microsystems - Beijing China * Disabled: Present; boot order is not set for any targets on the port. 36085b6dd21fSchenlu chen - Sun Microsystems - Beijing China * Enabled: Present; boot order is set for at least one target on the port. 36095b6dd21fSchenlu chen - Sun Microsystems - Beijing China */ 36105b6dd21fSchenlu chen - Sun Microsystems - Beijing China enum ixgbe_fcoe_boot_status { 361169b5a878SDan McDonald ixgbe_fcoe_bootstatus_disabled = 0, 361269b5a878SDan McDonald ixgbe_fcoe_bootstatus_enabled = 1, 361369b5a878SDan McDonald ixgbe_fcoe_bootstatus_unavailable = 0xFFFF 36145b6dd21fSchenlu chen - Sun Microsystems - Beijing China }; 36155b6dd21fSchenlu chen - Sun Microsystems - Beijing China 36169da57d7bSbt enum ixgbe_eeprom_type { 36179da57d7bSbt ixgbe_eeprom_uninitialized = 0, 36189da57d7bSbt ixgbe_eeprom_spi, 36193cfa0eb9Schenlu chen - Sun Microsystems - Beijing China ixgbe_flash, 36209da57d7bSbt ixgbe_eeprom_none /* No NVM support */ 36219da57d7bSbt }; 36229da57d7bSbt 36239da57d7bSbt enum ixgbe_mac_type { 36249da57d7bSbt ixgbe_mac_unknown = 0, 36259da57d7bSbt ixgbe_mac_82598EB, 362673cd555cSBin Tu - Sun Microsystems - Beijing China ixgbe_mac_82599EB, 362769b5a878SDan McDonald ixgbe_mac_82599_vf, 362869b5a878SDan McDonald ixgbe_mac_X540, 362969b5a878SDan McDonald ixgbe_mac_X540_vf, 3630dc0cb1cdSDale Ghent ixgbe_mac_X550, 3631dc0cb1cdSDale Ghent ixgbe_mac_X550EM_x, 3632*48ed61a7SRobert Mustacchi ixgbe_mac_X550EM_a, 3633dc0cb1cdSDale Ghent ixgbe_mac_X550_vf, 3634dc0cb1cdSDale Ghent ixgbe_mac_X550EM_x_vf, 3635*48ed61a7SRobert Mustacchi ixgbe_mac_X550EM_a_vf, 36369da57d7bSbt ixgbe_num_macs 36379da57d7bSbt }; 36389da57d7bSbt 36399da57d7bSbt enum ixgbe_phy_type { 36409da57d7bSbt ixgbe_phy_unknown = 0, 364173cd555cSBin Tu - Sun Microsystems - Beijing China ixgbe_phy_none, 364213740cb2SPaul Guo ixgbe_phy_tn, 3643185c5677SPaul Guo ixgbe_phy_aq, 3644dc0cb1cdSDale Ghent ixgbe_phy_x550em_kr, 3645dc0cb1cdSDale Ghent ixgbe_phy_x550em_kx4, 3646*48ed61a7SRobert Mustacchi ixgbe_phy_x550em_xfi, 3647dc0cb1cdSDale Ghent ixgbe_phy_x550em_ext_t, 3648*48ed61a7SRobert Mustacchi ixgbe_phy_ext_1g_t, 364973cd555cSBin Tu - Sun Microsystems - Beijing China ixgbe_phy_cu_unknown, 3650185c5677SPaul Guo ixgbe_phy_qt, 36519da57d7bSbt ixgbe_phy_xaui, 365213740cb2SPaul Guo ixgbe_phy_nl, 36535b6dd21fSchenlu chen - Sun Microsystems - Beijing China ixgbe_phy_sfp_passive_tyco, 36545b6dd21fSchenlu chen - Sun Microsystems - Beijing China ixgbe_phy_sfp_passive_unknown, 36555b6dd21fSchenlu chen - Sun Microsystems - Beijing China ixgbe_phy_sfp_active_unknown, 365613740cb2SPaul Guo ixgbe_phy_sfp_avago, 365713740cb2SPaul Guo ixgbe_phy_sfp_ftl, 36585b6dd21fSchenlu chen - Sun Microsystems - Beijing China ixgbe_phy_sfp_ftl_active, 365913740cb2SPaul Guo ixgbe_phy_sfp_unknown, 366073cd555cSBin Tu - Sun Microsystems - Beijing China ixgbe_phy_sfp_intel, 3661dc0cb1cdSDale Ghent ixgbe_phy_qsfp_passive_unknown, 3662dc0cb1cdSDale Ghent ixgbe_phy_qsfp_active_unknown, 3663dc0cb1cdSDale Ghent ixgbe_phy_qsfp_intel, 3664dc0cb1cdSDale Ghent ixgbe_phy_qsfp_unknown, 366563b3bba8SJerry Jelinek ixgbe_phy_sfp_unsupported, /*Enforce bit set with unsupported module*/ 3666*48ed61a7SRobert Mustacchi ixgbe_phy_sgmii, 3667*48ed61a7SRobert Mustacchi ixgbe_phy_fw, 36689da57d7bSbt ixgbe_phy_generic 36699da57d7bSbt }; 36709da57d7bSbt 367113740cb2SPaul Guo /* 367213740cb2SPaul Guo * SFP+ module type IDs: 367313740cb2SPaul Guo * 367463b3bba8SJerry Jelinek * ID Module Type 367513740cb2SPaul Guo * ============= 367663b3bba8SJerry Jelinek * 0 SFP_DA_CU 367763b3bba8SJerry Jelinek * 1 SFP_SR 367863b3bba8SJerry Jelinek * 2 SFP_LR 367969b5a878SDan McDonald * 3 SFP_DA_CU_CORE0 - 82599-specific 368069b5a878SDan McDonald * 4 SFP_DA_CU_CORE1 - 82599-specific 368169b5a878SDan McDonald * 5 SFP_SR/LR_CORE0 - 82599-specific 368269b5a878SDan McDonald * 6 SFP_SR/LR_CORE1 - 82599-specific 368313740cb2SPaul Guo */ 368413740cb2SPaul Guo enum ixgbe_sfp_type { 368513740cb2SPaul Guo ixgbe_sfp_type_da_cu = 0, 368613740cb2SPaul Guo ixgbe_sfp_type_sr = 1, 368713740cb2SPaul Guo ixgbe_sfp_type_lr = 2, 368873cd555cSBin Tu - Sun Microsystems - Beijing China ixgbe_sfp_type_da_cu_core0 = 3, 368973cd555cSBin Tu - Sun Microsystems - Beijing China ixgbe_sfp_type_da_cu_core1 = 4, 369073cd555cSBin Tu - Sun Microsystems - Beijing China ixgbe_sfp_type_srlr_core0 = 5, 369173cd555cSBin Tu - Sun Microsystems - Beijing China ixgbe_sfp_type_srlr_core1 = 6, 36925b6dd21fSchenlu chen - Sun Microsystems - Beijing China ixgbe_sfp_type_da_act_lmt_core0 = 7, 36935b6dd21fSchenlu chen - Sun Microsystems - Beijing China ixgbe_sfp_type_da_act_lmt_core1 = 8, 36945b6dd21fSchenlu chen - Sun Microsystems - Beijing China ixgbe_sfp_type_1g_cu_core0 = 9, 36955b6dd21fSchenlu chen - Sun Microsystems - Beijing China ixgbe_sfp_type_1g_cu_core1 = 10, 369669b5a878SDan McDonald ixgbe_sfp_type_1g_sx_core0 = 11, 369769b5a878SDan McDonald ixgbe_sfp_type_1g_sx_core1 = 12, 3698eb341807SSaso Kiselkov ixgbe_sfp_type_1g_lx_core0 = 13, 3699eb341807SSaso Kiselkov ixgbe_sfp_type_1g_lx_core1 = 14, 370013740cb2SPaul Guo ixgbe_sfp_type_not_present = 0xFFFE, 370113740cb2SPaul Guo ixgbe_sfp_type_unknown = 0xFFFF 370213740cb2SPaul Guo }; 370313740cb2SPaul Guo 37049da57d7bSbt enum ixgbe_media_type { 37059da57d7bSbt ixgbe_media_type_unknown = 0, 37069da57d7bSbt ixgbe_media_type_fiber, 3707dc0cb1cdSDale Ghent ixgbe_media_type_fiber_fixed, 3708dc0cb1cdSDale Ghent ixgbe_media_type_fiber_qsfp, 37099da57d7bSbt ixgbe_media_type_copper, 37109da57d7bSbt ixgbe_media_type_backplane, 37113cfa0eb9Schenlu chen - Sun Microsystems - Beijing China ixgbe_media_type_cx4, 37129da57d7bSbt ixgbe_media_type_virtual 37139da57d7bSbt }; 37149da57d7bSbt 37159da57d7bSbt /* Flow Control Settings */ 371673cd555cSBin Tu - Sun Microsystems - Beijing China enum ixgbe_fc_mode { 37179da57d7bSbt ixgbe_fc_none = 0, 37189da57d7bSbt ixgbe_fc_rx_pause, 37199da57d7bSbt ixgbe_fc_tx_pause, 37209da57d7bSbt ixgbe_fc_full, 37219da57d7bSbt ixgbe_fc_default 37229da57d7bSbt }; 37239da57d7bSbt 37243cfa0eb9Schenlu chen - Sun Microsystems - Beijing China /* Smart Speed Settings */ 372563b3bba8SJerry Jelinek #define IXGBE_SMARTSPEED_MAX_RETRIES 3 37263cfa0eb9Schenlu chen - Sun Microsystems - Beijing China enum ixgbe_smart_speed { 37273cfa0eb9Schenlu chen - Sun Microsystems - Beijing China ixgbe_smart_speed_auto = 0, 37283cfa0eb9Schenlu chen - Sun Microsystems - Beijing China ixgbe_smart_speed_on, 37293cfa0eb9Schenlu chen - Sun Microsystems - Beijing China ixgbe_smart_speed_off 37303cfa0eb9Schenlu chen - Sun Microsystems - Beijing China }; 37313cfa0eb9Schenlu chen - Sun Microsystems - Beijing China 37329da57d7bSbt /* PCI bus types */ 37339da57d7bSbt enum ixgbe_bus_type { 37349da57d7bSbt ixgbe_bus_type_unknown = 0, 37359da57d7bSbt ixgbe_bus_type_pci, 37369da57d7bSbt ixgbe_bus_type_pcix, 37379da57d7bSbt ixgbe_bus_type_pci_express, 3738dc0cb1cdSDale Ghent ixgbe_bus_type_internal, 37399da57d7bSbt ixgbe_bus_type_reserved 37409da57d7bSbt }; 37419da57d7bSbt 37429da57d7bSbt /* PCI bus speeds */ 37439da57d7bSbt enum ixgbe_bus_speed { 374469b5a878SDan McDonald ixgbe_bus_speed_unknown = 0, 374569b5a878SDan McDonald ixgbe_bus_speed_33 = 33, 374669b5a878SDan McDonald ixgbe_bus_speed_66 = 66, 374769b5a878SDan McDonald ixgbe_bus_speed_100 = 100, 374869b5a878SDan McDonald ixgbe_bus_speed_120 = 120, 374969b5a878SDan McDonald ixgbe_bus_speed_133 = 133, 375069b5a878SDan McDonald ixgbe_bus_speed_2500 = 2500, 375169b5a878SDan McDonald ixgbe_bus_speed_5000 = 5000, 375269b5a878SDan McDonald ixgbe_bus_speed_8000 = 8000, 37539da57d7bSbt ixgbe_bus_speed_reserved 37549da57d7bSbt }; 37559da57d7bSbt 37569da57d7bSbt /* PCI bus widths */ 37579da57d7bSbt enum ixgbe_bus_width { 375869b5a878SDan McDonald ixgbe_bus_width_unknown = 0, 375969b5a878SDan McDonald ixgbe_bus_width_pcie_x1 = 1, 376069b5a878SDan McDonald ixgbe_bus_width_pcie_x2 = 2, 376169b5a878SDan McDonald ixgbe_bus_width_pcie_x4 = 4, 376269b5a878SDan McDonald ixgbe_bus_width_pcie_x8 = 8, 376369b5a878SDan McDonald ixgbe_bus_width_32 = 32, 376469b5a878SDan McDonald ixgbe_bus_width_64 = 64, 37659da57d7bSbt ixgbe_bus_width_reserved 37669da57d7bSbt }; 37679da57d7bSbt 37689da57d7bSbt struct ixgbe_addr_filter_info { 37699da57d7bSbt u32 num_mc_addrs; 37709da57d7bSbt u32 rar_used_count; 37719da57d7bSbt u32 mta_in_use; 37729da57d7bSbt u32 overflow_promisc; 37739da57d7bSbt bool user_set_promisc; 37749da57d7bSbt }; 37759da57d7bSbt 37769da57d7bSbt /* Bus parameters */ 37779da57d7bSbt struct ixgbe_bus_info { 37789da57d7bSbt enum ixgbe_bus_speed speed; 37799da57d7bSbt enum ixgbe_bus_width width; 37809da57d7bSbt enum ixgbe_bus_type type; 378173cd555cSBin Tu - Sun Microsystems - Beijing China 378273cd555cSBin Tu - Sun Microsystems - Beijing China u16 func; 3783*48ed61a7SRobert Mustacchi u8 lan_id; 3784*48ed61a7SRobert Mustacchi u16 instance_id; 37859da57d7bSbt }; 37869da57d7bSbt 37879da57d7bSbt /* Flow control parameters */ 37889da57d7bSbt struct ixgbe_fc_info { 378969b5a878SDan McDonald u32 high_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl High-water */ 379069b5a878SDan McDonald u32 low_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl Low-water */ 37919da57d7bSbt u16 pause_time; /* Flow Control Pause timer */ 37929da57d7bSbt bool send_xon; /* Flow control send XON */ 37939da57d7bSbt bool strict_ieee; /* Strict IEEE mode */ 379473cd555cSBin Tu - Sun Microsystems - Beijing China bool disable_fc_autoneg; /* Do not autonegotiate FC */ 379573cd555cSBin Tu - Sun Microsystems - Beijing China bool fc_was_autonegged; /* Is current_mode the result of autonegging? */ 379673cd555cSBin Tu - Sun Microsystems - Beijing China enum ixgbe_fc_mode current_mode; /* FC mode in effect */ 379773cd555cSBin Tu - Sun Microsystems - Beijing China enum ixgbe_fc_mode requested_mode; /* FC mode requested by caller */ 37989da57d7bSbt }; 37999da57d7bSbt 38009da57d7bSbt /* Statistics counters collected by the MAC */ 38019da57d7bSbt struct ixgbe_hw_stats { 38029da57d7bSbt u64 crcerrs; 38039da57d7bSbt u64 illerrc; 38049da57d7bSbt u64 errbc; 38059da57d7bSbt u64 mspdc; 38069da57d7bSbt u64 mpctotal; 38079da57d7bSbt u64 mpc[8]; 38089da57d7bSbt u64 mlfc; 38099da57d7bSbt u64 mrfc; 38109da57d7bSbt u64 rlec; 38119da57d7bSbt u64 lxontxc; 38129da57d7bSbt u64 lxonrxc; 38139da57d7bSbt u64 lxofftxc; 38149da57d7bSbt u64 lxoffrxc; 38159da57d7bSbt u64 pxontxc[8]; 38169da57d7bSbt u64 pxonrxc[8]; 38179da57d7bSbt u64 pxofftxc[8]; 38189da57d7bSbt u64 pxoffrxc[8]; 38199da57d7bSbt u64 prc64; 38209da57d7bSbt u64 prc127; 38219da57d7bSbt u64 prc255; 38229da57d7bSbt u64 prc511; 38239da57d7bSbt u64 prc1023; 38249da57d7bSbt u64 prc1522; 38259da57d7bSbt u64 gprc; 38269da57d7bSbt u64 bprc; 38279da57d7bSbt u64 mprc; 38289da57d7bSbt u64 gptc; 38299da57d7bSbt u64 gorc; 38309da57d7bSbt u64 gotc; 38319da57d7bSbt u64 rnbc[8]; 38329da57d7bSbt u64 ruc; 38339da57d7bSbt u64 rfc; 38349da57d7bSbt u64 roc; 38359da57d7bSbt u64 rjc; 38369da57d7bSbt u64 mngprc; 38379da57d7bSbt u64 mngpdc; 38389da57d7bSbt u64 mngptc; 38399da57d7bSbt u64 tor; 38409da57d7bSbt u64 tpr; 38419da57d7bSbt u64 tpt; 38429da57d7bSbt u64 ptc64; 38439da57d7bSbt u64 ptc127; 38449da57d7bSbt u64 ptc255; 38459da57d7bSbt u64 ptc511; 38469da57d7bSbt u64 ptc1023; 38479da57d7bSbt u64 ptc1522; 38489da57d7bSbt u64 mptc; 38499da57d7bSbt u64 bptc; 38509da57d7bSbt u64 xec; 38519da57d7bSbt u64 qprc[16]; 38529da57d7bSbt u64 qptc[16]; 38539da57d7bSbt u64 qbrc[16]; 38549da57d7bSbt u64 qbtc[16]; 385573cd555cSBin Tu - Sun Microsystems - Beijing China u64 qprdc[16]; 385673cd555cSBin Tu - Sun Microsystems - Beijing China u64 pxon2offc[8]; 385773cd555cSBin Tu - Sun Microsystems - Beijing China u64 fdirustat_add; 385873cd555cSBin Tu - Sun Microsystems - Beijing China u64 fdirustat_remove; 385973cd555cSBin Tu - Sun Microsystems - Beijing China u64 fdirfstat_fadd; 386073cd555cSBin Tu - Sun Microsystems - Beijing China u64 fdirfstat_fremove; 386173cd555cSBin Tu - Sun Microsystems - Beijing China u64 fdirmatch; 386273cd555cSBin Tu - Sun Microsystems - Beijing China u64 fdirmiss; 386373cd555cSBin Tu - Sun Microsystems - Beijing China u64 fccrc; 386473cd555cSBin Tu - Sun Microsystems - Beijing China u64 fclast; 386573cd555cSBin Tu - Sun Microsystems - Beijing China u64 fcoerpdc; 386673cd555cSBin Tu - Sun Microsystems - Beijing China u64 fcoeprc; 386773cd555cSBin Tu - Sun Microsystems - Beijing China u64 fcoeptc; 386873cd555cSBin Tu - Sun Microsystems - Beijing China u64 fcoedwrc; 386973cd555cSBin Tu - Sun Microsystems - Beijing China u64 fcoedwtc; 387069b5a878SDan McDonald u64 fcoe_noddp; 387169b5a878SDan McDonald u64 fcoe_noddp_ext_buff; 387269b5a878SDan McDonald u64 ldpcec; 387369b5a878SDan McDonald u64 pcrc8ec; 387469b5a878SDan McDonald u64 b2ospc; 387569b5a878SDan McDonald u64 b2ogprc; 387669b5a878SDan McDonald u64 o2bgptc; 387769b5a878SDan McDonald u64 o2bspc; 38789da57d7bSbt }; 38799da57d7bSbt 38809da57d7bSbt /* forward declaration */ 38819da57d7bSbt struct ixgbe_hw; 38829da57d7bSbt 38839da57d7bSbt /* iterator type for walking multicast address lists */ 38849da57d7bSbt typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr, 388569b5a878SDan McDonald u32 *vmdq); 38869da57d7bSbt 38879da57d7bSbt /* Function pointer table */ 38889da57d7bSbt struct ixgbe_eeprom_operations { 38899da57d7bSbt s32 (*init_params)(struct ixgbe_hw *); 38909da57d7bSbt s32 (*read)(struct ixgbe_hw *, u16, u16 *); 389169b5a878SDan McDonald s32 (*read_buffer)(struct ixgbe_hw *, u16, u16, u16 *); 38929da57d7bSbt s32 (*write)(struct ixgbe_hw *, u16, u16); 389369b5a878SDan McDonald s32 (*write_buffer)(struct ixgbe_hw *, u16, u16, u16 *); 38949da57d7bSbt s32 (*validate_checksum)(struct ixgbe_hw *, u16 *); 38959da57d7bSbt s32 (*update_checksum)(struct ixgbe_hw *); 3896dc0cb1cdSDale Ghent s32 (*calc_checksum)(struct ixgbe_hw *); 38979da57d7bSbt }; 38989da57d7bSbt 38999da57d7bSbt struct ixgbe_mac_operations { 39009da57d7bSbt s32 (*init_hw)(struct ixgbe_hw *); 39019da57d7bSbt s32 (*reset_hw)(struct ixgbe_hw *); 39029da57d7bSbt s32 (*start_hw)(struct ixgbe_hw *); 39039da57d7bSbt s32 (*clear_hw_cntrs)(struct ixgbe_hw *); 390419843f01SPaul Guo void (*enable_relaxed_ordering)(struct ixgbe_hw *); 39059da57d7bSbt enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *); 3906*48ed61a7SRobert Mustacchi u64 (*get_supported_physical_layer)(struct ixgbe_hw *); 39079da57d7bSbt s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *); 390873cd555cSBin Tu - Sun Microsystems - Beijing China s32 (*get_san_mac_addr)(struct ixgbe_hw *, u8 *); 390973cd555cSBin Tu - Sun Microsystems - Beijing China s32 (*set_san_mac_addr)(struct ixgbe_hw *, u8 *); 391073cd555cSBin Tu - Sun Microsystems - Beijing China s32 (*get_device_caps)(struct ixgbe_hw *, u16 *); 39113cfa0eb9Schenlu chen - Sun Microsystems - Beijing China s32 (*get_wwn_prefix)(struct ixgbe_hw *, u16 *, u16 *); 39125b6dd21fSchenlu chen - Sun Microsystems - Beijing China s32 (*get_fcoe_boot_status)(struct ixgbe_hw *, u16 *); 39139da57d7bSbt s32 (*stop_adapter)(struct ixgbe_hw *); 39149da57d7bSbt s32 (*get_bus_info)(struct ixgbe_hw *); 3915*48ed61a7SRobert Mustacchi s32 (*negotiate_api_version)(struct ixgbe_hw *, int); 391673cd555cSBin Tu - Sun Microsystems - Beijing China void (*set_lan_id)(struct ixgbe_hw *); 391763b3bba8SJerry Jelinek s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*); 391863b3bba8SJerry Jelinek s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8); 391973cd555cSBin Tu - Sun Microsystems - Beijing China s32 (*setup_sfp)(struct ixgbe_hw *); 392073cd555cSBin Tu - Sun Microsystems - Beijing China s32 (*enable_rx_dma)(struct ixgbe_hw *, u32); 392169b5a878SDan McDonald s32 (*disable_sec_rx_path)(struct ixgbe_hw *); 392269b5a878SDan McDonald s32 (*enable_sec_rx_path)(struct ixgbe_hw *); 3923dc0cb1cdSDale Ghent s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u32); 3924dc0cb1cdSDale Ghent void (*release_swfw_sync)(struct ixgbe_hw *, u32); 3925*48ed61a7SRobert Mustacchi void (*init_swfw_sync)(struct ixgbe_hw *); 3926dc0cb1cdSDale Ghent s32 (*prot_autoc_read)(struct ixgbe_hw *, bool *, u32 *); 3927dc0cb1cdSDale Ghent s32 (*prot_autoc_write)(struct ixgbe_hw *, u32, bool); 39289da57d7bSbt 39299da57d7bSbt /* Link */ 39305b6dd21fSchenlu chen - Sun Microsystems - Beijing China void (*disable_tx_laser)(struct ixgbe_hw *); 39315b6dd21fSchenlu chen - Sun Microsystems - Beijing China void (*enable_tx_laser)(struct ixgbe_hw *); 39325b6dd21fSchenlu chen - Sun Microsystems - Beijing China void (*flap_tx_laser)(struct ixgbe_hw *); 3933dc0cb1cdSDale Ghent s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool); 3934dc0cb1cdSDale Ghent s32 (*setup_mac_link)(struct ixgbe_hw *, ixgbe_link_speed, bool); 393513740cb2SPaul Guo s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool); 39369da57d7bSbt s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *, 393769b5a878SDan McDonald bool *); 3938dc0cb1cdSDale Ghent void (*set_rate_select_speed)(struct ixgbe_hw *, ixgbe_link_speed); 393969b5a878SDan McDonald 394069b5a878SDan McDonald /* Packet Buffer manipulation */ 394169b5a878SDan McDonald void (*setup_rxpba)(struct ixgbe_hw *, int, u32, int); 39429da57d7bSbt 39439da57d7bSbt /* LED */ 39449da57d7bSbt s32 (*led_on)(struct ixgbe_hw *, u32); 39459da57d7bSbt s32 (*led_off)(struct ixgbe_hw *, u32); 39469da57d7bSbt s32 (*blink_led_start)(struct ixgbe_hw *, u32); 39479da57d7bSbt s32 (*blink_led_stop)(struct ixgbe_hw *, u32); 3948*48ed61a7SRobert Mustacchi s32 (*init_led_link_act)(struct ixgbe_hw *); 39499da57d7bSbt 39509da57d7bSbt /* RAR, Multicast, VLAN */ 39519da57d7bSbt s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32); 395269b5a878SDan McDonald s32 (*set_uc_addr)(struct ixgbe_hw *, u32, u8 *); 395313740cb2SPaul Guo s32 (*clear_rar)(struct ixgbe_hw *, u32); 395473cd555cSBin Tu - Sun Microsystems - Beijing China s32 (*insert_mac_addr)(struct ixgbe_hw *, u8 *, u32); 39559da57d7bSbt s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32); 395669b5a878SDan McDonald s32 (*set_vmdq_san_mac)(struct ixgbe_hw *, u32); 395713740cb2SPaul Guo s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32); 39589da57d7bSbt s32 (*init_rx_addrs)(struct ixgbe_hw *); 39599da57d7bSbt s32 (*update_uc_addr_list)(struct ixgbe_hw *, u8 *, u32, 396069b5a878SDan McDonald ixgbe_mc_addr_itr); 39619da57d7bSbt s32 (*update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32, 396269b5a878SDan McDonald ixgbe_mc_addr_itr, bool clear); 3963*48ed61a7SRobert Mustacchi s32 (*update_xcast_mode)(struct ixgbe_hw *, int); 39649da57d7bSbt s32 (*enable_mc)(struct ixgbe_hw *); 39659da57d7bSbt s32 (*disable_mc)(struct ixgbe_hw *); 39669da57d7bSbt s32 (*clear_vfta)(struct ixgbe_hw *); 3967*48ed61a7SRobert Mustacchi s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool, bool); 3968*48ed61a7SRobert Mustacchi s32 (*set_vlvf)(struct ixgbe_hw *, u32, u32, bool, u32 *, u32, 3969*48ed61a7SRobert Mustacchi bool); 3970*48ed61a7SRobert Mustacchi s32 (*set_rlpml)(struct ixgbe_hw *, u16); 397113740cb2SPaul Guo s32 (*init_uta_tables)(struct ixgbe_hw *); 397263b3bba8SJerry Jelinek void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int); 397363b3bba8SJerry Jelinek void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int); 39749da57d7bSbt 39759da57d7bSbt /* Flow Control */ 397669b5a878SDan McDonald s32 (*fc_enable)(struct ixgbe_hw *); 3977dc0cb1cdSDale Ghent s32 (*setup_fc)(struct ixgbe_hw *); 3978*48ed61a7SRobert Mustacchi void (*fc_autoneg)(struct ixgbe_hw *); 397969b5a878SDan McDonald 398069b5a878SDan McDonald /* Manageability interface */ 3981*48ed61a7SRobert Mustacchi s32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8, u16, 3982*48ed61a7SRobert Mustacchi const char *); 3983*48ed61a7SRobert Mustacchi s32 (*bypass_rw) (struct ixgbe_hw *hw, u32 cmd, u32 *status); 3984*48ed61a7SRobert Mustacchi bool (*bypass_valid_rd) (u32 in_reg, u32 out_reg); 3985*48ed61a7SRobert Mustacchi s32 (*bypass_set) (struct ixgbe_hw *hw, u32 cmd, u32 event, u32 action); 3986*48ed61a7SRobert Mustacchi s32 (*bypass_rd_eep) (struct ixgbe_hw *hw, u32 addr, u8 *value); 3987dc0cb1cdSDale Ghent void (*get_rtrup2tc)(struct ixgbe_hw *hw, u8 *map); 3988dc0cb1cdSDale Ghent void (*disable_rx)(struct ixgbe_hw *hw); 3989dc0cb1cdSDale Ghent void (*enable_rx)(struct ixgbe_hw *hw); 3990dc0cb1cdSDale Ghent void (*set_source_address_pruning)(struct ixgbe_hw *, bool, 3991dc0cb1cdSDale Ghent unsigned int); 3992dc0cb1cdSDale Ghent void (*set_ethertype_anti_spoofing)(struct ixgbe_hw *, bool, int); 3993dc0cb1cdSDale Ghent s32 (*dmac_update_tcs)(struct ixgbe_hw *hw); 3994dc0cb1cdSDale Ghent s32 (*dmac_config_tcs)(struct ixgbe_hw *hw); 3995dc0cb1cdSDale Ghent s32 (*dmac_config)(struct ixgbe_hw *hw); 3996dc0cb1cdSDale Ghent s32 (*setup_eee)(struct ixgbe_hw *hw, bool enable_eee); 3997dc0cb1cdSDale Ghent s32 (*read_iosf_sb_reg)(struct ixgbe_hw *, u32, u32, u32 *); 3998dc0cb1cdSDale Ghent s32 (*write_iosf_sb_reg)(struct ixgbe_hw *, u32, u32, u32); 3999dc0cb1cdSDale Ghent void (*disable_mdd)(struct ixgbe_hw *hw); 4000dc0cb1cdSDale Ghent void (*enable_mdd)(struct ixgbe_hw *hw); 4001dc0cb1cdSDale Ghent void (*mdd_event)(struct ixgbe_hw *hw, u32 *vf_bitmap); 4002dc0cb1cdSDale Ghent void (*restore_mdd_vf)(struct ixgbe_hw *hw, u32 vf); 40039da57d7bSbt }; 40049da57d7bSbt 40059da57d7bSbt struct ixgbe_phy_operations { 40069da57d7bSbt s32 (*identify)(struct ixgbe_hw *); 400713740cb2SPaul Guo s32 (*identify_sfp)(struct ixgbe_hw *); 400873cd555cSBin Tu - Sun Microsystems - Beijing China s32 (*init)(struct ixgbe_hw *); 40099da57d7bSbt s32 (*reset)(struct ixgbe_hw *); 40109da57d7bSbt s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *); 40119da57d7bSbt s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16); 4012dc0cb1cdSDale Ghent s32 (*read_reg_mdi)(struct ixgbe_hw *, u32, u32, u16 *); 4013dc0cb1cdSDale Ghent s32 (*write_reg_mdi)(struct ixgbe_hw *, u32, u32, u16); 40149da57d7bSbt s32 (*setup_link)(struct ixgbe_hw *); 4015dc0cb1cdSDale Ghent s32 (*setup_internal_link)(struct ixgbe_hw *); 4016dc0cb1cdSDale Ghent s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool); 401713740cb2SPaul Guo s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *); 401813740cb2SPaul Guo s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *); 401913740cb2SPaul Guo s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *); 402013740cb2SPaul Guo s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8); 4021dc0cb1cdSDale Ghent s32 (*read_i2c_sff8472)(struct ixgbe_hw *, u8 , u8 *); 402263b3bba8SJerry Jelinek s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *); 402313740cb2SPaul Guo s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8); 402473cd555cSBin Tu - Sun Microsystems - Beijing China void (*i2c_bus_clear)(struct ixgbe_hw *); 40255b6dd21fSchenlu chen - Sun Microsystems - Beijing China s32 (*check_overtemp)(struct ixgbe_hw *); 4026dc0cb1cdSDale Ghent s32 (*set_phy_power)(struct ixgbe_hw *, bool on); 4027dc0cb1cdSDale Ghent s32 (*enter_lplu)(struct ixgbe_hw *); 4028dc0cb1cdSDale Ghent s32 (*handle_lasi)(struct ixgbe_hw *hw); 4029dc0cb1cdSDale Ghent s32 (*read_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr, 4030dc0cb1cdSDale Ghent u8 *value); 4031dc0cb1cdSDale Ghent s32 (*write_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr, 4032dc0cb1cdSDale Ghent u8 value); 40339da57d7bSbt }; 40349da57d7bSbt 4035*48ed61a7SRobert Mustacchi struct ixgbe_link_operations { 4036*48ed61a7SRobert Mustacchi s32 (*read_link)(struct ixgbe_hw *, u8 addr, u16 reg, u16 *val); 4037*48ed61a7SRobert Mustacchi s32 (*read_link_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg, 4038*48ed61a7SRobert Mustacchi u16 *val); 4039*48ed61a7SRobert Mustacchi s32 (*write_link)(struct ixgbe_hw *, u8 addr, u16 reg, u16 val); 4040*48ed61a7SRobert Mustacchi s32 (*write_link_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg, 4041*48ed61a7SRobert Mustacchi u16 val); 4042*48ed61a7SRobert Mustacchi }; 4043*48ed61a7SRobert Mustacchi 4044*48ed61a7SRobert Mustacchi struct ixgbe_link_info { 4045*48ed61a7SRobert Mustacchi struct ixgbe_link_operations ops; 4046*48ed61a7SRobert Mustacchi u8 addr; 4047*48ed61a7SRobert Mustacchi }; 4048*48ed61a7SRobert Mustacchi 40499da57d7bSbt struct ixgbe_eeprom_info { 405069b5a878SDan McDonald struct ixgbe_eeprom_operations ops; 405169b5a878SDan McDonald enum ixgbe_eeprom_type type; 405269b5a878SDan McDonald u32 semaphore_delay; 405369b5a878SDan McDonald u16 word_size; 405469b5a878SDan McDonald u16 address_bits; 405569b5a878SDan McDonald u16 word_page_size; 4056dc0cb1cdSDale Ghent u16 ctrl_word_3; 40579da57d7bSbt }; 40589da57d7bSbt 405963b3bba8SJerry Jelinek #define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED 0x01 40609da57d7bSbt struct ixgbe_mac_info { 406169b5a878SDan McDonald struct ixgbe_mac_operations ops; 406269b5a878SDan McDonald enum ixgbe_mac_type type; 406369b5a878SDan McDonald u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; 406469b5a878SDan McDonald u8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; 406569b5a878SDan McDonald u8 san_addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; 40663cfa0eb9Schenlu chen - Sun Microsystems - Beijing China /* prefix for World Wide Node Name (WWNN) */ 406769b5a878SDan McDonald u16 wwnn_prefix; 40683cfa0eb9Schenlu chen - Sun Microsystems - Beijing China /* prefix for World Wide Port Name (WWPN) */ 406969b5a878SDan McDonald u16 wwpn_prefix; 407063b3bba8SJerry Jelinek #define IXGBE_MAX_MTA 128 407169b5a878SDan McDonald u32 mta_shadow[IXGBE_MAX_MTA]; 407269b5a878SDan McDonald s32 mc_filter_type; 407369b5a878SDan McDonald u32 mcft_size; 407469b5a878SDan McDonald u32 vft_size; 407569b5a878SDan McDonald u32 num_rar_entries; 407669b5a878SDan McDonald u32 rar_highwater; 407769b5a878SDan McDonald u32 rx_pb_size; 407869b5a878SDan McDonald u32 max_tx_queues; 407969b5a878SDan McDonald u32 max_rx_queues; 408069b5a878SDan McDonald u32 orig_autoc; 408169b5a878SDan McDonald u8 san_mac_rar_index; 4082dc0cb1cdSDale Ghent bool get_link_status; 408369b5a878SDan McDonald u32 orig_autoc2; 408469b5a878SDan McDonald u16 max_msix_vectors; 408569b5a878SDan McDonald bool arc_subsystem_valid; 408669b5a878SDan McDonald bool orig_link_settings_stored; 408769b5a878SDan McDonald bool autotry_restart; 408869b5a878SDan McDonald u8 flags; 4089dc0cb1cdSDale Ghent struct ixgbe_dmac_config dmac_config; 4090dc0cb1cdSDale Ghent bool set_lben; 4091dc0cb1cdSDale Ghent u32 max_link_up_time; 4092*48ed61a7SRobert Mustacchi u8 led_link_act; 40939da57d7bSbt }; 40949da57d7bSbt 40959da57d7bSbt struct ixgbe_phy_info { 409669b5a878SDan McDonald struct ixgbe_phy_operations ops; 409769b5a878SDan McDonald enum ixgbe_phy_type type; 409869b5a878SDan McDonald u32 addr; 409969b5a878SDan McDonald u32 id; 410069b5a878SDan McDonald enum ixgbe_sfp_type sfp_type; 410169b5a878SDan McDonald bool sfp_setup_needed; 410269b5a878SDan McDonald u32 revision; 410369b5a878SDan McDonald enum ixgbe_media_type media_type; 4104dc0cb1cdSDale Ghent u32 phy_semaphore_mask; 410569b5a878SDan McDonald bool reset_disable; 410669b5a878SDan McDonald ixgbe_autoneg_advertised autoneg_advertised; 4107dc0cb1cdSDale Ghent ixgbe_link_speed speeds_supported; 4108*48ed61a7SRobert Mustacchi ixgbe_link_speed eee_speeds_supported; 4109*48ed61a7SRobert Mustacchi ixgbe_link_speed eee_speeds_advertised; 411069b5a878SDan McDonald enum ixgbe_smart_speed smart_speed; 411169b5a878SDan McDonald bool smart_speed_active; 411269b5a878SDan McDonald bool multispeed_fiber; 411369b5a878SDan McDonald bool reset_if_overtemp; 4114dc0cb1cdSDale Ghent bool qsfp_shared_i2c_bus; 4115dc0cb1cdSDale Ghent u32 nw_mng_if_sel; 411669b5a878SDan McDonald }; 411769b5a878SDan McDonald 411869b5a878SDan McDonald #include "ixgbe_mbx.h" 411969b5a878SDan McDonald 412069b5a878SDan McDonald struct ixgbe_mbx_operations { 412169b5a878SDan McDonald void (*init_params)(struct ixgbe_hw *hw); 412269b5a878SDan McDonald s32 (*read)(struct ixgbe_hw *, u32 *, u16, u16); 412369b5a878SDan McDonald s32 (*write)(struct ixgbe_hw *, u32 *, u16, u16); 412469b5a878SDan McDonald s32 (*read_posted)(struct ixgbe_hw *, u32 *, u16, u16); 412569b5a878SDan McDonald s32 (*write_posted)(struct ixgbe_hw *, u32 *, u16, u16); 412669b5a878SDan McDonald s32 (*check_for_msg)(struct ixgbe_hw *, u16); 412769b5a878SDan McDonald s32 (*check_for_ack)(struct ixgbe_hw *, u16); 412869b5a878SDan McDonald s32 (*check_for_rst)(struct ixgbe_hw *, u16); 412969b5a878SDan McDonald }; 413069b5a878SDan McDonald 413169b5a878SDan McDonald struct ixgbe_mbx_stats { 413269b5a878SDan McDonald u32 msgs_tx; 413369b5a878SDan McDonald u32 msgs_rx; 413469b5a878SDan McDonald 413569b5a878SDan McDonald u32 acks; 413669b5a878SDan McDonald u32 reqs; 413769b5a878SDan McDonald u32 rsts; 413869b5a878SDan McDonald }; 413969b5a878SDan McDonald 414069b5a878SDan McDonald struct ixgbe_mbx_info { 414169b5a878SDan McDonald struct ixgbe_mbx_operations ops; 414269b5a878SDan McDonald struct ixgbe_mbx_stats stats; 414369b5a878SDan McDonald u32 timeout; 414469b5a878SDan McDonald u32 usec_delay; 414569b5a878SDan McDonald u32 v2p_mailbox; 414669b5a878SDan McDonald u16 size; 41479da57d7bSbt }; 41489da57d7bSbt 41499da57d7bSbt struct ixgbe_hw { 4150dc0cb1cdSDale Ghent u8 IOMEM *hw_addr; 415169b5a878SDan McDonald void *back; 415269b5a878SDan McDonald struct ixgbe_mac_info mac; 415369b5a878SDan McDonald struct ixgbe_addr_filter_info addr_ctrl; 415469b5a878SDan McDonald struct ixgbe_fc_info fc; 415569b5a878SDan McDonald struct ixgbe_phy_info phy; 4156*48ed61a7SRobert Mustacchi struct ixgbe_link_info link; 415769b5a878SDan McDonald struct ixgbe_eeprom_info eeprom; 415869b5a878SDan McDonald struct ixgbe_bus_info bus; 415969b5a878SDan McDonald struct ixgbe_mbx_info mbx; 4160dc0cb1cdSDale Ghent const u32 *mvals; 416169b5a878SDan McDonald u16 device_id; 416269b5a878SDan McDonald u16 vendor_id; 416369b5a878SDan McDonald u16 subsystem_device_id; 416469b5a878SDan McDonald u16 subsystem_vendor_id; 416569b5a878SDan McDonald u8 revision_id; 416669b5a878SDan McDonald bool adapter_stopped; 4167dc0cb1cdSDale Ghent int api_version; 416869b5a878SDan McDonald bool force_full_reset; 416969b5a878SDan McDonald bool allow_unsupported_sfp; 4170dc0cb1cdSDale Ghent bool wol_enabled; 4171*48ed61a7SRobert Mustacchi bool need_crosstalk_fix; 41729da57d7bSbt }; 41739da57d7bSbt 417463b3bba8SJerry Jelinek #define ixgbe_call_func(hw, func, params, error) \ 417569b5a878SDan McDonald (func != NULL) ? func params : error 41769da57d7bSbt 41779da57d7bSbt 417863b3bba8SJerry Jelinek /* Error Codes */ 417969b5a878SDan McDonald #define IXGBE_SUCCESS 0 418069b5a878SDan McDonald #define IXGBE_ERR_EEPROM -1 418169b5a878SDan McDonald #define IXGBE_ERR_EEPROM_CHECKSUM -2 418269b5a878SDan McDonald #define IXGBE_ERR_PHY -3 418369b5a878SDan McDonald #define IXGBE_ERR_CONFIG -4 418469b5a878SDan McDonald #define IXGBE_ERR_PARAM -5 418569b5a878SDan McDonald #define IXGBE_ERR_MAC_TYPE -6 418669b5a878SDan McDonald #define IXGBE_ERR_UNKNOWN_PHY -7 418769b5a878SDan McDonald #define IXGBE_ERR_LINK_SETUP -8 418869b5a878SDan McDonald #define IXGBE_ERR_ADAPTER_STOPPED -9 418969b5a878SDan McDonald #define IXGBE_ERR_INVALID_MAC_ADDR -10 419069b5a878SDan McDonald #define IXGBE_ERR_DEVICE_NOT_SUPPORTED -11 419169b5a878SDan McDonald #define IXGBE_ERR_MASTER_REQUESTS_PENDING -12 419269b5a878SDan McDonald #define IXGBE_ERR_INVALID_LINK_SETTINGS -13 419369b5a878SDan McDonald #define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14 419469b5a878SDan McDonald #define IXGBE_ERR_RESET_FAILED -15 419569b5a878SDan McDonald #define IXGBE_ERR_SWFW_SYNC -16 419669b5a878SDan McDonald #define IXGBE_ERR_PHY_ADDR_INVALID -17 419769b5a878SDan McDonald #define IXGBE_ERR_I2C -18 419869b5a878SDan McDonald #define IXGBE_ERR_SFP_NOT_SUPPORTED -19 419969b5a878SDan McDonald #define IXGBE_ERR_SFP_NOT_PRESENT -20 420069b5a878SDan McDonald #define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT -21 420169b5a878SDan McDonald #define IXGBE_ERR_NO_SAN_ADDR_PTR -22 420269b5a878SDan McDonald #define IXGBE_ERR_FDIR_REINIT_FAILED -23 420369b5a878SDan McDonald #define IXGBE_ERR_EEPROM_VERSION -24 420469b5a878SDan McDonald #define IXGBE_ERR_NO_SPACE -25 420569b5a878SDan McDonald #define IXGBE_ERR_OVERTEMP -26 420669b5a878SDan McDonald #define IXGBE_ERR_FC_NOT_NEGOTIATED -27 420769b5a878SDan McDonald #define IXGBE_ERR_FC_NOT_SUPPORTED -28 420869b5a878SDan McDonald #define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE -30 420969b5a878SDan McDonald #define IXGBE_ERR_PBA_SECTION -31 421069b5a878SDan McDonald #define IXGBE_ERR_INVALID_ARGUMENT -32 421169b5a878SDan McDonald #define IXGBE_ERR_HOST_INTERFACE_COMMAND -33 421269b5a878SDan McDonald #define IXGBE_ERR_OUT_OF_MEM -34 4213*48ed61a7SRobert Mustacchi #define IXGBE_BYPASS_FW_WRITE_FAILURE -35 4214dc0cb1cdSDale Ghent #define IXGBE_ERR_FEATURE_NOT_SUPPORTED -36 4215dc0cb1cdSDale Ghent #define IXGBE_ERR_EEPROM_PROTECTED_REGION -37 4216dc0cb1cdSDale Ghent #define IXGBE_ERR_FDIR_CMD_INCOMPLETE -38 4217*48ed61a7SRobert Mustacchi #define IXGBE_ERR_FW_RESP_INVALID -39 4218*48ed61a7SRobert Mustacchi #define IXGBE_ERR_TOKEN_RETRY -40 421969b5a878SDan McDonald 422069b5a878SDan McDonald #define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF 422163b3bba8SJerry Jelinek 422263b3bba8SJerry Jelinek 4223*48ed61a7SRobert Mustacchi #define BYPASS_PAGE_CTL0 0x00000000 4224*48ed61a7SRobert Mustacchi #define BYPASS_PAGE_CTL1 0x40000000 4225*48ed61a7SRobert Mustacchi #define BYPASS_PAGE_CTL2 0x80000000 4226*48ed61a7SRobert Mustacchi #define BYPASS_PAGE_M 0xc0000000 4227*48ed61a7SRobert Mustacchi #define BYPASS_WE 0x20000000 4228*48ed61a7SRobert Mustacchi 4229*48ed61a7SRobert Mustacchi #define BYPASS_AUTO 0x0 4230*48ed61a7SRobert Mustacchi #define BYPASS_NOP 0x0 4231*48ed61a7SRobert Mustacchi #define BYPASS_NORM 0x1 4232*48ed61a7SRobert Mustacchi #define BYPASS_BYPASS 0x2 4233*48ed61a7SRobert Mustacchi #define BYPASS_ISOLATE 0x3 4234*48ed61a7SRobert Mustacchi 4235*48ed61a7SRobert Mustacchi #define BYPASS_EVENT_MAIN_ON 0x1 4236*48ed61a7SRobert Mustacchi #define BYPASS_EVENT_AUX_ON 0x2 4237*48ed61a7SRobert Mustacchi #define BYPASS_EVENT_MAIN_OFF 0x3 4238*48ed61a7SRobert Mustacchi #define BYPASS_EVENT_AUX_OFF 0x4 4239*48ed61a7SRobert Mustacchi #define BYPASS_EVENT_WDT_TO 0x5 4240*48ed61a7SRobert Mustacchi #define BYPASS_EVENT_USR 0x6 4241*48ed61a7SRobert Mustacchi 4242*48ed61a7SRobert Mustacchi #define BYPASS_MODE_OFF_M 0x00000003 4243*48ed61a7SRobert Mustacchi #define BYPASS_STATUS_OFF_M 0x0000000c 4244*48ed61a7SRobert Mustacchi #define BYPASS_AUX_ON_M 0x00000030 4245*48ed61a7SRobert Mustacchi #define BYPASS_MAIN_ON_M 0x000000c0 4246*48ed61a7SRobert Mustacchi #define BYPASS_MAIN_OFF_M 0x00000300 4247*48ed61a7SRobert Mustacchi #define BYPASS_AUX_OFF_M 0x00000c00 4248*48ed61a7SRobert Mustacchi #define BYPASS_WDTIMEOUT_M 0x00003000 4249*48ed61a7SRobert Mustacchi #define BYPASS_WDT_ENABLE_M 0x00004000 4250*48ed61a7SRobert Mustacchi #define BYPASS_WDT_VALUE_M 0x00070000 4251*48ed61a7SRobert Mustacchi 4252*48ed61a7SRobert Mustacchi #define BYPASS_MODE_OFF_SHIFT 0 4253*48ed61a7SRobert Mustacchi #define BYPASS_STATUS_OFF_SHIFT 2 4254*48ed61a7SRobert Mustacchi #define BYPASS_AUX_ON_SHIFT 4 4255*48ed61a7SRobert Mustacchi #define BYPASS_MAIN_ON_SHIFT 6 4256*48ed61a7SRobert Mustacchi #define BYPASS_MAIN_OFF_SHIFT 8 4257*48ed61a7SRobert Mustacchi #define BYPASS_AUX_OFF_SHIFT 10 4258*48ed61a7SRobert Mustacchi #define BYPASS_WDTIMEOUT_SHIFT 12 4259*48ed61a7SRobert Mustacchi #define BYPASS_WDT_ENABLE_SHIFT 14 4260*48ed61a7SRobert Mustacchi #define BYPASS_WDT_TIME_SHIFT 16 4261*48ed61a7SRobert Mustacchi 4262*48ed61a7SRobert Mustacchi #define BYPASS_WDT_1 0x0 4263*48ed61a7SRobert Mustacchi #define BYPASS_WDT_1_5 0x1 4264*48ed61a7SRobert Mustacchi #define BYPASS_WDT_2 0x2 4265*48ed61a7SRobert Mustacchi #define BYPASS_WDT_3 0x3 4266*48ed61a7SRobert Mustacchi #define BYPASS_WDT_4 0x4 4267*48ed61a7SRobert Mustacchi #define BYPASS_WDT_8 0x5 4268*48ed61a7SRobert Mustacchi #define BYPASS_WDT_16 0x6 4269*48ed61a7SRobert Mustacchi #define BYPASS_WDT_32 0x7 4270*48ed61a7SRobert Mustacchi #define BYPASS_WDT_OFF 0xffff 4271*48ed61a7SRobert Mustacchi 4272*48ed61a7SRobert Mustacchi #define BYPASS_CTL1_TIME_M 0x01ffffff 4273*48ed61a7SRobert Mustacchi #define BYPASS_CTL1_VALID_M 0x02000000 4274*48ed61a7SRobert Mustacchi #define BYPASS_CTL1_OFFTRST_M 0x04000000 4275*48ed61a7SRobert Mustacchi #define BYPASS_CTL1_WDT_PET_M 0x08000000 4276*48ed61a7SRobert Mustacchi 4277*48ed61a7SRobert Mustacchi #define BYPASS_CTL1_VALID 0x02000000 4278*48ed61a7SRobert Mustacchi #define BYPASS_CTL1_OFFTRST 0x04000000 4279*48ed61a7SRobert Mustacchi #define BYPASS_CTL1_WDT_PET 0x08000000 4280*48ed61a7SRobert Mustacchi 4281*48ed61a7SRobert Mustacchi #define BYPASS_CTL2_DATA_M 0x000000ff 4282*48ed61a7SRobert Mustacchi #define BYPASS_CTL2_OFFSET_M 0x0000ff00 4283*48ed61a7SRobert Mustacchi #define BYPASS_CTL2_RW_M 0x00010000 4284*48ed61a7SRobert Mustacchi #define BYPASS_CTL2_HEAD_M 0x0ff00000 4285*48ed61a7SRobert Mustacchi 4286*48ed61a7SRobert Mustacchi #define BYPASS_CTL2_OFFSET_SHIFT 8 4287*48ed61a7SRobert Mustacchi #define BYPASS_CTL2_HEAD_SHIFT 20 4288*48ed61a7SRobert Mustacchi 4289*48ed61a7SRobert Mustacchi #define BYPASS_CTL2_RW 0x00010000 4290*48ed61a7SRobert Mustacchi 4291*48ed61a7SRobert Mustacchi struct ixgbe_bypass_eeprom { 4292*48ed61a7SRobert Mustacchi u32 logs; 4293*48ed61a7SRobert Mustacchi u32 clear_off; 4294*48ed61a7SRobert Mustacchi u8 actions; 4295*48ed61a7SRobert Mustacchi }; 4296*48ed61a7SRobert Mustacchi 4297*48ed61a7SRobert Mustacchi #define BYPASS_MAX_LOGS 43 4298*48ed61a7SRobert Mustacchi #define BYPASS_LOG_SIZE 5 4299*48ed61a7SRobert Mustacchi #define BYPASS_LOG_LINE_SIZE 37 4300*48ed61a7SRobert Mustacchi 4301*48ed61a7SRobert Mustacchi #define BYPASS_EEPROM_VER_ADD 0x02 4302*48ed61a7SRobert Mustacchi 4303*48ed61a7SRobert Mustacchi #define BYPASS_LOG_TIME_M 0x01ffffff 4304*48ed61a7SRobert Mustacchi #define BYPASS_LOG_TIME_VALID_M 0x02000000 4305*48ed61a7SRobert Mustacchi #define BYPASS_LOG_HEAD_M 0x04000000 4306*48ed61a7SRobert Mustacchi #define BYPASS_LOG_CLEAR_M 0x08000000 4307*48ed61a7SRobert Mustacchi #define BYPASS_LOG_EVENT_M 0xf0000000 4308*48ed61a7SRobert Mustacchi #define BYPASS_LOG_ACTION_M 0x03 4309*48ed61a7SRobert Mustacchi 4310*48ed61a7SRobert Mustacchi #define BYPASS_LOG_EVENT_SHIFT 28 4311*48ed61a7SRobert Mustacchi #define BYPASS_LOG_CLEAR_SHIFT 24 /* bit offset */ 4312*48ed61a7SRobert Mustacchi 4313dc0cb1cdSDale Ghent #define IXGBE_FUSES0_GROUP(_i) (0x11158 + ((_i) * 4)) 4314dc0cb1cdSDale Ghent #define IXGBE_FUSES0_300MHZ (1 << 5) 4315*48ed61a7SRobert Mustacchi #define IXGBE_FUSES0_REV_MASK (3 << 6) 4316dc0cb1cdSDale Ghent 4317dc0cb1cdSDale Ghent #define IXGBE_KRM_PORT_CAR_GEN_CTRL(P) ((P) ? 0x8010 : 0x4010) 4318*48ed61a7SRobert Mustacchi #define IXGBE_KRM_LINK_S1(P) ((P) ? 0x8200 : 0x4200) 4319dc0cb1cdSDale Ghent #define IXGBE_KRM_LINK_CTRL_1(P) ((P) ? 0x820C : 0x420C) 4320dc0cb1cdSDale Ghent #define IXGBE_KRM_AN_CNTL_1(P) ((P) ? 0x822C : 0x422C) 4321*48ed61a7SRobert Mustacchi #define IXGBE_KRM_AN_CNTL_4(P) ((P) ? 0x8238 : 0x4238) 4322*48ed61a7SRobert Mustacchi #define IXGBE_KRM_AN_CNTL_8(P) ((P) ? 0x8248 : 0x4248) 4323*48ed61a7SRobert Mustacchi #define IXGBE_KRM_PCS_KX_AN(P) ((P) ? 0x9918 : 0x5918) 4324*48ed61a7SRobert Mustacchi #define IXGBE_KRM_PCS_KX_AN_LP(P) ((P) ? 0x991C : 0x591C) 4325*48ed61a7SRobert Mustacchi #define IXGBE_KRM_SGMII_CTRL(P) ((P) ? 0x82A0 : 0x42A0) 4326*48ed61a7SRobert Mustacchi #define IXGBE_KRM_LP_BASE_PAGE_HIGH(P) ((P) ? 0x836C : 0x436C) 4327dc0cb1cdSDale Ghent #define IXGBE_KRM_DSP_TXFFE_STATE_4(P) ((P) ? 0x8634 : 0x4634) 4328dc0cb1cdSDale Ghent #define IXGBE_KRM_DSP_TXFFE_STATE_5(P) ((P) ? 0x8638 : 0x4638) 4329dc0cb1cdSDale Ghent #define IXGBE_KRM_RX_TRN_LINKUP_CTRL(P) ((P) ? 0x8B00 : 0x4B00) 4330dc0cb1cdSDale Ghent #define IXGBE_KRM_PMD_DFX_BURNIN(P) ((P) ? 0x8E00 : 0x4E00) 4331*48ed61a7SRobert Mustacchi #define IXGBE_KRM_PMD_FLX_MASK_ST20(P) ((P) ? 0x9054 : 0x5054) 4332dc0cb1cdSDale Ghent #define IXGBE_KRM_TX_COEFF_CTRL_1(P) ((P) ? 0x9520 : 0x5520) 4333dc0cb1cdSDale Ghent #define IXGBE_KRM_RX_ANA_CTL(P) ((P) ? 0x9A00 : 0x5A00) 4334dc0cb1cdSDale Ghent 4335*48ed61a7SRobert Mustacchi #define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA ~(0x3 << 20) 4336*48ed61a7SRobert Mustacchi #define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR (1u << 20) 4337*48ed61a7SRobert Mustacchi #define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_LR (0x2 << 20) 4338*48ed61a7SRobert Mustacchi #define IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN (1u << 25) 4339*48ed61a7SRobert Mustacchi #define IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN (1u << 26) 4340*48ed61a7SRobert Mustacchi #define IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN (1u << 27) 4341*48ed61a7SRobert Mustacchi #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10M ~(0x7 << 28) 4342*48ed61a7SRobert Mustacchi #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_100M (1u << 28) 4343*48ed61a7SRobert Mustacchi #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G (0x2 << 28) 4344*48ed61a7SRobert Mustacchi #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G (0x3 << 28) 4345*48ed61a7SRobert Mustacchi #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN (0x4 << 28) 4346*48ed61a7SRobert Mustacchi #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_2_5G (0x7 << 28) 4347*48ed61a7SRobert Mustacchi #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK (0x7 << 28) 4348*48ed61a7SRobert Mustacchi #define IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART (1u << 31) 4349*48ed61a7SRobert Mustacchi 4350dc0cb1cdSDale Ghent #define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B (1 << 9) 4351dc0cb1cdSDale Ghent #define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS (1 << 11) 4352dc0cb1cdSDale Ghent 4353dc0cb1cdSDale Ghent #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK (0x7 << 8) 4354dc0cb1cdSDale Ghent #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G (2 << 8) 4355dc0cb1cdSDale Ghent #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G (4 << 8) 4356*48ed61a7SRobert Mustacchi #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN (1 << 12) 4357*48ed61a7SRobert Mustacchi #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN (1 << 13) 4358dc0cb1cdSDale Ghent #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ (1 << 14) 4359dc0cb1cdSDale Ghent #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC (1 << 15) 4360dc0cb1cdSDale Ghent #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX (1 << 16) 4361dc0cb1cdSDale Ghent #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR (1 << 18) 4362dc0cb1cdSDale Ghent #define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX (1 << 24) 4363dc0cb1cdSDale Ghent #define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR (1 << 26) 4364*48ed61a7SRobert Mustacchi #define IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE (1 << 28) 4365dc0cb1cdSDale Ghent #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE (1 << 29) 4366*48ed61a7SRobert Mustacchi #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART (1 << 31) 4367dc0cb1cdSDale Ghent 4368dc0cb1cdSDale Ghent #define IXGBE_KRM_AN_CNTL_1_SYM_PAUSE (1 << 28) 4369dc0cb1cdSDale Ghent #define IXGBE_KRM_AN_CNTL_1_ASM_PAUSE (1 << 29) 4370*48ed61a7SRobert Mustacchi #define IXGBE_KRM_PCS_KX_AN_SYM_PAUSE (1 << 1) 4371*48ed61a7SRobert Mustacchi #define IXGBE_KRM_PCS_KX_AN_ASM_PAUSE (1 << 2) 4372*48ed61a7SRobert Mustacchi #define IXGBE_KRM_PCS_KX_AN_LP_SYM_PAUSE (1 << 2) 4373*48ed61a7SRobert Mustacchi #define IXGBE_KRM_PCS_KX_AN_LP_ASM_PAUSE (1 << 3) 4374*48ed61a7SRobert Mustacchi #define IXGBE_KRM_AN_CNTL_4_ECSR_AN37_OVER_73 (1 << 29) 4375*48ed61a7SRobert Mustacchi #define IXGBE_KRM_AN_CNTL_8_LINEAR (1 << 0) 4376*48ed61a7SRobert Mustacchi #define IXGBE_KRM_AN_CNTL_8_LIMITING (1 << 1) 4377*48ed61a7SRobert Mustacchi 4378*48ed61a7SRobert Mustacchi #define IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE (1 << 10) 4379*48ed61a7SRobert Mustacchi #define IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE (1 << 11) 4380*48ed61a7SRobert Mustacchi 4381*48ed61a7SRobert Mustacchi #define IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D (1 << 12) 4382*48ed61a7SRobert Mustacchi #define IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D (1 << 19) 4383dc0cb1cdSDale Ghent 4384dc0cb1cdSDale Ghent #define IXGBE_KRM_DSP_TXFFE_STATE_C0_EN (1 << 6) 4385dc0cb1cdSDale Ghent #define IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN (1 << 15) 4386dc0cb1cdSDale Ghent #define IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN (1 << 16) 4387dc0cb1cdSDale Ghent 4388dc0cb1cdSDale Ghent #define IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL (1 << 4) 4389dc0cb1cdSDale Ghent #define IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS (1 << 2) 4390dc0cb1cdSDale Ghent 4391dc0cb1cdSDale Ghent #define IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK (0x3 << 16) 4392dc0cb1cdSDale Ghent 4393dc0cb1cdSDale Ghent #define IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN (1 << 1) 4394dc0cb1cdSDale Ghent #define IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN (1 << 2) 4395dc0cb1cdSDale Ghent #define IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN (1 << 3) 4396*48ed61a7SRobert Mustacchi #define IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN (1 << 31) 4397dc0cb1cdSDale Ghent 4398dc0cb1cdSDale Ghent #define IXGBE_SB_IOSF_INDIRECT_CTRL 0x00011144 4399dc0cb1cdSDale Ghent #define IXGBE_SB_IOSF_INDIRECT_DATA 0x00011148 4400dc0cb1cdSDale Ghent 4401dc0cb1cdSDale Ghent #define IXGBE_SB_IOSF_CTRL_ADDR_SHIFT 0 4402dc0cb1cdSDale Ghent #define IXGBE_SB_IOSF_CTRL_ADDR_MASK 0xFF 4403dc0cb1cdSDale Ghent #define IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT 18 4404dc0cb1cdSDale Ghent #define IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK \ 4405dc0cb1cdSDale Ghent (0x3 << IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT) 4406dc0cb1cdSDale Ghent #define IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT 20 4407dc0cb1cdSDale Ghent #define IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK \ 4408dc0cb1cdSDale Ghent (0xFF << IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT) 4409dc0cb1cdSDale Ghent #define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT 28 4410dc0cb1cdSDale Ghent #define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_MASK 0x7 4411dc0cb1cdSDale Ghent #define IXGBE_SB_IOSF_CTRL_BUSY_SHIFT 31 4412*48ed61a7SRobert Mustacchi #define IXGBE_SB_IOSF_CTRL_BUSY (1 << IXGBE_SB_IOSF_CTRL_BUSY_SHIFT) 4413dc0cb1cdSDale Ghent #define IXGBE_SB_IOSF_TARGET_KR_PHY 0 4414dc0cb1cdSDale Ghent 4415dc0cb1cdSDale Ghent #define IXGBE_NW_MNG_IF_SEL 0x00011178 4416*48ed61a7SRobert Mustacchi #define IXGBE_NW_MNG_IF_SEL_MDIO_ACT (1u << 1) 4417*48ed61a7SRobert Mustacchi #define IXGBE_NW_MNG_IF_SEL_MDIO_IF_MODE (1u << 2) 4418*48ed61a7SRobert Mustacchi #define IXGBE_NW_MNG_IF_SEL_EN_SHARED_MDIO (1u << 13) 4419*48ed61a7SRobert Mustacchi #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_10M (1u << 17) 4420*48ed61a7SRobert Mustacchi #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_100M (1u << 18) 4421*48ed61a7SRobert Mustacchi #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_1G (1u << 19) 4422*48ed61a7SRobert Mustacchi #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G (1u << 20) 4423*48ed61a7SRobert Mustacchi #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_10G (1u << 21) 4424*48ed61a7SRobert Mustacchi #define IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE (1u << 25) 4425*48ed61a7SRobert Mustacchi #define IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE (1 << 24) /* X552 reg field only */ 4426*48ed61a7SRobert Mustacchi #define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT 3 4427*48ed61a7SRobert Mustacchi #define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD \ 4428*48ed61a7SRobert Mustacchi (0x1F << IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT) 4429*48ed61a7SRobert Mustacchi 4430*48ed61a7SRobert Mustacchi #define IXGBE_REQUEST_TASK_MOD 0x01 4431*48ed61a7SRobert Mustacchi #define IXGBE_REQUEST_TASK_MSF 0x02 4432*48ed61a7SRobert Mustacchi #define IXGBE_REQUEST_TASK_MBX 0x04 4433*48ed61a7SRobert Mustacchi #define IXGBE_REQUEST_TASK_FDIR 0x08 4434*48ed61a7SRobert Mustacchi #define IXGBE_REQUEST_TASK_PHY 0x10 4435*48ed61a7SRobert Mustacchi #define IXGBE_REQUEST_TASK_LSC 0x20 4436dc0cb1cdSDale Ghent 443763b3bba8SJerry Jelinek #endif /* _IXGBE_TYPE_H_ */ 4438