1dc0cb1cdSDale Ghent /****************************************************************************** 2*48ed61a7SRobert Mustacchi SPDX-License-Identifier: BSD-3-Clause 3dc0cb1cdSDale Ghent 4*48ed61a7SRobert Mustacchi Copyright (c) 2001-2017, Intel Corporation 5dc0cb1cdSDale Ghent All rights reserved. 6*48ed61a7SRobert Mustacchi 7*48ed61a7SRobert Mustacchi Redistribution and use in source and binary forms, with or without 8dc0cb1cdSDale Ghent modification, are permitted provided that the following conditions are met: 9*48ed61a7SRobert Mustacchi 10*48ed61a7SRobert Mustacchi 1. Redistributions of source code must retain the above copyright notice, 11dc0cb1cdSDale Ghent this list of conditions and the following disclaimer. 12*48ed61a7SRobert Mustacchi 13*48ed61a7SRobert Mustacchi 2. Redistributions in binary form must reproduce the above copyright 14*48ed61a7SRobert Mustacchi notice, this list of conditions and the following disclaimer in the 15dc0cb1cdSDale Ghent documentation and/or other materials provided with the distribution. 16*48ed61a7SRobert Mustacchi 17*48ed61a7SRobert Mustacchi 3. Neither the name of the Intel Corporation nor the names of its 18*48ed61a7SRobert Mustacchi contributors may be used to endorse or promote products derived from 19dc0cb1cdSDale Ghent this software without specific prior written permission. 20*48ed61a7SRobert Mustacchi 21dc0cb1cdSDale Ghent THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22*48ed61a7SRobert Mustacchi AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23*48ed61a7SRobert Mustacchi IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24*48ed61a7SRobert Mustacchi ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25*48ed61a7SRobert Mustacchi LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26*48ed61a7SRobert Mustacchi CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27*48ed61a7SRobert Mustacchi SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28*48ed61a7SRobert Mustacchi INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29*48ed61a7SRobert Mustacchi CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30dc0cb1cdSDale Ghent ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31dc0cb1cdSDale Ghent POSSIBILITY OF SUCH DAMAGE. 32dc0cb1cdSDale Ghent 33dc0cb1cdSDale Ghent ******************************************************************************/ 34dc0cb1cdSDale Ghent /*$FreeBSD$*/ 35dc0cb1cdSDale Ghent 36dc0cb1cdSDale Ghent #ifndef _IXGBE_DCB_82598_H_ 37dc0cb1cdSDale Ghent #define _IXGBE_DCB_82598_H_ 38dc0cb1cdSDale Ghent 39dc0cb1cdSDale Ghent /* DCB register definitions */ 40dc0cb1cdSDale Ghent 41dc0cb1cdSDale Ghent #define IXGBE_DPMCS_MTSOS_SHIFT 16 42dc0cb1cdSDale Ghent #define IXGBE_DPMCS_TDPAC 0x00000001 /* 0 Round Robin, 43dc0cb1cdSDale Ghent * 1 DFP - Deficit Fixed Priority */ 44dc0cb1cdSDale Ghent #define IXGBE_DPMCS_TRM 0x00000010 /* Transmit Recycle Mode */ 45dc0cb1cdSDale Ghent #define IXGBE_DPMCS_ARBDIS 0x00000040 /* DCB arbiter disable */ 46dc0cb1cdSDale Ghent #define IXGBE_DPMCS_TSOEF 0x00080000 /* TSO Expand Factor: 0=x4, 1=x2 */ 47dc0cb1cdSDale Ghent 48dc0cb1cdSDale Ghent #define IXGBE_RUPPBMR_MQA 0x80000000 /* Enable UP to queue mapping */ 49dc0cb1cdSDale Ghent 50dc0cb1cdSDale Ghent #define IXGBE_RT2CR_MCL_SHIFT 12 /* Offset to Max Credit Limit setting */ 51dc0cb1cdSDale Ghent #define IXGBE_RT2CR_LSP 0x80000000 /* LSP enable bit */ 52dc0cb1cdSDale Ghent 53dc0cb1cdSDale Ghent #define IXGBE_RDRXCTL_MPBEN 0x00000010 /* DMA config for multiple packet 54dc0cb1cdSDale Ghent * buffers enable */ 55dc0cb1cdSDale Ghent #define IXGBE_RDRXCTL_MCEN 0x00000040 /* DMA config for multiple cores 56dc0cb1cdSDale Ghent * (RSS) enable */ 57dc0cb1cdSDale Ghent 58dc0cb1cdSDale Ghent #define IXGBE_TDTQ2TCCR_MCL_SHIFT 12 59dc0cb1cdSDale Ghent #define IXGBE_TDTQ2TCCR_BWG_SHIFT 9 60dc0cb1cdSDale Ghent #define IXGBE_TDTQ2TCCR_GSP 0x40000000 61dc0cb1cdSDale Ghent #define IXGBE_TDTQ2TCCR_LSP 0x80000000 62dc0cb1cdSDale Ghent 63dc0cb1cdSDale Ghent #define IXGBE_TDPT2TCCR_MCL_SHIFT 12 64dc0cb1cdSDale Ghent #define IXGBE_TDPT2TCCR_BWG_SHIFT 9 65dc0cb1cdSDale Ghent #define IXGBE_TDPT2TCCR_GSP 0x40000000 66dc0cb1cdSDale Ghent #define IXGBE_TDPT2TCCR_LSP 0x80000000 67dc0cb1cdSDale Ghent 68dc0cb1cdSDale Ghent #define IXGBE_PDPMCS_TPPAC 0x00000020 /* 0 Round Robin, 69dc0cb1cdSDale Ghent * 1 DFP - Deficit Fixed Priority */ 70dc0cb1cdSDale Ghent #define IXGBE_PDPMCS_ARBDIS 0x00000040 /* Arbiter disable */ 71dc0cb1cdSDale Ghent #define IXGBE_PDPMCS_TRM 0x00000100 /* Transmit Recycle Mode enable */ 72dc0cb1cdSDale Ghent 73dc0cb1cdSDale Ghent #define IXGBE_DTXCTL_ENDBUBD 0x00000004 /* Enable DBU buffer division */ 74dc0cb1cdSDale Ghent 75dc0cb1cdSDale Ghent #define IXGBE_TXPBSIZE_40KB 0x0000A000 /* 40KB Packet Buffer */ 76dc0cb1cdSDale Ghent #define IXGBE_RXPBSIZE_48KB 0x0000C000 /* 48KB Packet Buffer */ 77dc0cb1cdSDale Ghent #define IXGBE_RXPBSIZE_64KB 0x00010000 /* 64KB Packet Buffer */ 78dc0cb1cdSDale Ghent #define IXGBE_RXPBSIZE_80KB 0x00014000 /* 80KB Packet Buffer */ 79dc0cb1cdSDale Ghent 80dc0cb1cdSDale Ghent /* DCB driver APIs */ 81dc0cb1cdSDale Ghent 82dc0cb1cdSDale Ghent /* DCB PFC */ 83dc0cb1cdSDale Ghent s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *, u8); 84dc0cb1cdSDale Ghent 85dc0cb1cdSDale Ghent /* DCB stats */ 86dc0cb1cdSDale Ghent s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *); 87dc0cb1cdSDale Ghent s32 ixgbe_dcb_get_tc_stats_82598(struct ixgbe_hw *, 88dc0cb1cdSDale Ghent struct ixgbe_hw_stats *, u8); 89dc0cb1cdSDale Ghent s32 ixgbe_dcb_get_pfc_stats_82598(struct ixgbe_hw *, 90dc0cb1cdSDale Ghent struct ixgbe_hw_stats *, u8); 91dc0cb1cdSDale Ghent 92dc0cb1cdSDale Ghent /* DCB config arbiters */ 93dc0cb1cdSDale Ghent s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *, u16 *, u16 *, 94dc0cb1cdSDale Ghent u8 *, u8 *); 95dc0cb1cdSDale Ghent s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *, u16 *, u16 *, 96dc0cb1cdSDale Ghent u8 *, u8 *); 97dc0cb1cdSDale Ghent s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *, u16 *, u16 *, u8 *); 98dc0cb1cdSDale Ghent 99dc0cb1cdSDale Ghent /* DCB initialization */ 100dc0cb1cdSDale Ghent s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *, int, u16 *, u16 *, u8 *, u8 *); 101dc0cb1cdSDale Ghent #endif /* _IXGBE_DCB_82958_H_ */ 102