1fd43cf6eSHans Rosenfeld /* $NetBSD: if_iwnreg.h,v 1.15 2014/11/09 14:40:54 nonaka Exp $ */ 2fd43cf6eSHans Rosenfeld /* $OpenBSD: if_iwnreg.h,v 1.49 2014/09/09 18:56:24 sthen Exp $ */ 3fd43cf6eSHans Rosenfeld 4fd43cf6eSHans Rosenfeld /*- 5fd43cf6eSHans Rosenfeld * Copyright (c) 2007, 2008 6fd43cf6eSHans Rosenfeld * Damien Bergamini <damien.bergamini@free.fr> 7fd43cf6eSHans Rosenfeld * 8fd43cf6eSHans Rosenfeld * Permission to use, copy, modify, and distribute this software for any 9fd43cf6eSHans Rosenfeld * purpose with or without fee is hereby granted, provided that the above 10fd43cf6eSHans Rosenfeld * copyright notice and this permission notice appear in all copies. 11fd43cf6eSHans Rosenfeld * 12fd43cf6eSHans Rosenfeld * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13fd43cf6eSHans Rosenfeld * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14fd43cf6eSHans Rosenfeld * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15fd43cf6eSHans Rosenfeld * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16fd43cf6eSHans Rosenfeld * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17fd43cf6eSHans Rosenfeld * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18fd43cf6eSHans Rosenfeld * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19fd43cf6eSHans Rosenfeld */ 20fd43cf6eSHans Rosenfeld 21fd43cf6eSHans Rosenfeld /* 22fd43cf6eSHans Rosenfeld * Copyright 2016 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> 23fd43cf6eSHans Rosenfeld */ 24fd43cf6eSHans Rosenfeld 25fd43cf6eSHans Rosenfeld #ifndef _IF_IWNREG_H 26fd43cf6eSHans Rosenfeld #define _IF_IWNREG_H 27fd43cf6eSHans Rosenfeld 28fd43cf6eSHans Rosenfeld /* XXX Added for NetBSD */ 29fd43cf6eSHans Rosenfeld #define IEEE80211_TKIP_MICLEN 8 30fd43cf6eSHans Rosenfeld 31fd43cf6eSHans Rosenfeld #define IWN_TX_RING_COUNT 256 32fd43cf6eSHans Rosenfeld #define IWN_TX_RING_LOMARK 192 33fd43cf6eSHans Rosenfeld #define IWN_TX_RING_HIMARK 224 34fd43cf6eSHans Rosenfeld #define IWN_RX_RING_COUNT_LOG 6 35fd43cf6eSHans Rosenfeld #define IWN_RX_RING_COUNT (1 << IWN_RX_RING_COUNT_LOG) 36fd43cf6eSHans Rosenfeld 37fd43cf6eSHans Rosenfeld #define IWN4965_NTXQUEUES 16 38fd43cf6eSHans Rosenfeld #define IWN5000_NTXQUEUES 20 39fd43cf6eSHans Rosenfeld 40fd43cf6eSHans Rosenfeld #define IWN_CMD_QUEUE_NUM 4 41fd43cf6eSHans Rosenfeld 42fd43cf6eSHans Rosenfeld #define IWN4965_NDMACHNLS 7 43fd43cf6eSHans Rosenfeld #define IWN5000_NDMACHNLS 8 44fd43cf6eSHans Rosenfeld 45fd43cf6eSHans Rosenfeld #define IWN_SRVC_DMACHNL 9 46fd43cf6eSHans Rosenfeld 47fd43cf6eSHans Rosenfeld #define IWN_KW_SIZE 4096 48fd43cf6eSHans Rosenfeld 49fd43cf6eSHans Rosenfeld #define IWN_ICT_SIZE 4096 50fd43cf6eSHans Rosenfeld #define IWN_ICT_COUNT (IWN_ICT_SIZE / sizeof (uint32_t)) 51fd43cf6eSHans Rosenfeld 52fd43cf6eSHans Rosenfeld /* Maximum number of DMA segments for TX. */ 53fd43cf6eSHans Rosenfeld #define IWN_MAX_SCATTER 20 54fd43cf6eSHans Rosenfeld 55fd43cf6eSHans Rosenfeld /* RX buffers must be large enough to hold a full 4K A-MPDU. */ 56fd43cf6eSHans Rosenfeld #define IWN_RBUF_SIZE (4 * 1024) 57fd43cf6eSHans Rosenfeld 58fd43cf6eSHans Rosenfeld #define IWN_TBUF_SIZE (4 * 1024) 59fd43cf6eSHans Rosenfeld 60fd43cf6eSHans Rosenfeld 61fd43cf6eSHans Rosenfeld #if defined(_LP64) 62fd43cf6eSHans Rosenfeld /* HW supports 36-bit DMA addresses. */ 63fd43cf6eSHans Rosenfeld #define IWN_LOADDR(paddr) ((uint32_t)(paddr)) 64fd43cf6eSHans Rosenfeld #define IWN_HIADDR(paddr) (((paddr) >> 32) & 0xf) 65fd43cf6eSHans Rosenfeld #else 66fd43cf6eSHans Rosenfeld #define IWN_LOADDR(paddr) (paddr) 67fd43cf6eSHans Rosenfeld #define IWN_HIADDR(paddr) (0) 68fd43cf6eSHans Rosenfeld #endif 69fd43cf6eSHans Rosenfeld 70fd43cf6eSHans Rosenfeld /* Base Address Register. */ 71fd43cf6eSHans Rosenfeld #define IWN_PCI_BAR0 PCI_MAPREG_START 72fd43cf6eSHans Rosenfeld 73fd43cf6eSHans Rosenfeld /* 74fd43cf6eSHans Rosenfeld * Control and status registers. 75fd43cf6eSHans Rosenfeld */ 76fd43cf6eSHans Rosenfeld #define IWN_HW_IF_CONFIG 0x000 77fd43cf6eSHans Rosenfeld #define IWN_INT_COALESCING 0x004 78fd43cf6eSHans Rosenfeld #define IWN_INT_PERIODIC 0x005 /* use IWN_WRITE_1 */ 79fd43cf6eSHans Rosenfeld #define IWN_INT 0x008 80fd43cf6eSHans Rosenfeld #define IWN_INT_MASK 0x00c 81fd43cf6eSHans Rosenfeld #define IWN_FH_INT 0x010 82fd43cf6eSHans Rosenfeld #define IWN_RESET 0x020 83fd43cf6eSHans Rosenfeld #define IWN_GP_CNTRL 0x024 84fd43cf6eSHans Rosenfeld #define IWN_HW_REV 0x028 85fd43cf6eSHans Rosenfeld #define IWN_EEPROM 0x02c 86fd43cf6eSHans Rosenfeld #define IWN_EEPROM_GP 0x030 87fd43cf6eSHans Rosenfeld #define IWN_OTP_GP 0x034 88fd43cf6eSHans Rosenfeld #define IWN_GIO 0x03c 89fd43cf6eSHans Rosenfeld #define IWN_GP_DRIVER 0x050 90fd43cf6eSHans Rosenfeld #define IWN_UCODE_GP1_CLR 0x05c 91fd43cf6eSHans Rosenfeld #define IWN_LED 0x094 92fd43cf6eSHans Rosenfeld #define IWN_DRAM_INT_TBL 0x0a0 93fd43cf6eSHans Rosenfeld #define IWN_SHADOW_REG_CTRL 0x0a8 94fd43cf6eSHans Rosenfeld #define IWN_GIO_CHICKEN 0x100 95fd43cf6eSHans Rosenfeld #define IWN_ANA_PLL 0x20c 96fd43cf6eSHans Rosenfeld #define IWN_HW_REV_WA 0x22c 97fd43cf6eSHans Rosenfeld #define IWN_DBG_HPET_MEM 0x240 98fd43cf6eSHans Rosenfeld #define IWN_DBG_LINK_PWR_MGMT 0x250 99fd43cf6eSHans Rosenfeld #define IWN_MEM_RADDR 0x40c 100fd43cf6eSHans Rosenfeld #define IWN_MEM_WADDR 0x410 101fd43cf6eSHans Rosenfeld #define IWN_MEM_WDATA 0x418 102fd43cf6eSHans Rosenfeld #define IWN_MEM_RDATA 0x41c 103*b302a200SToomas Soome #define IWN_PRPH_WADDR 0x444 104*b302a200SToomas Soome #define IWN_PRPH_RADDR 0x448 105*b302a200SToomas Soome #define IWN_PRPH_WDATA 0x44c 106*b302a200SToomas Soome #define IWN_PRPH_RDATA 0x450 107fd43cf6eSHans Rosenfeld #define IWN_HBUS_TARG_WRPTR 0x460 108fd43cf6eSHans Rosenfeld 109fd43cf6eSHans Rosenfeld /* 110fd43cf6eSHans Rosenfeld * Flow-Handler registers. 111fd43cf6eSHans Rosenfeld */ 112fd43cf6eSHans Rosenfeld #define IWN_FH_TFBD_CTRL0(qid) (0x1900 + (qid) * 8) 113fd43cf6eSHans Rosenfeld #define IWN_FH_TFBD_CTRL1(qid) (0x1904 + (qid) * 8) 114fd43cf6eSHans Rosenfeld #define IWN_FH_KW_ADDR 0x197c 115fd43cf6eSHans Rosenfeld #define IWN_FH_SRAM_ADDR(qid) (0x19a4 + (qid) * 4) 116fd43cf6eSHans Rosenfeld #define IWN_FH_CBBC_QUEUE(qid) (0x19d0 + (qid) * 4) 117fd43cf6eSHans Rosenfeld #define IWN_FH_STATUS_WPTR 0x1bc0 118fd43cf6eSHans Rosenfeld #define IWN_FH_RX_BASE 0x1bc4 119fd43cf6eSHans Rosenfeld #define IWN_FH_RX_WPTR 0x1bc8 120fd43cf6eSHans Rosenfeld #define IWN_FH_RX_CONFIG 0x1c00 121fd43cf6eSHans Rosenfeld #define IWN_FH_RX_STATUS 0x1c44 122fd43cf6eSHans Rosenfeld #define IWN_FH_TX_CONFIG(qid) (0x1d00 + (qid) * 32) 123fd43cf6eSHans Rosenfeld #define IWN_FH_TXBUF_STATUS(qid) (0x1d08 + (qid) * 32) 124fd43cf6eSHans Rosenfeld #define IWN_FH_TX_CHICKEN 0x1e98 125fd43cf6eSHans Rosenfeld #define IWN_FH_TX_STATUS 0x1eb0 126fd43cf6eSHans Rosenfeld 127fd43cf6eSHans Rosenfeld /* 128fd43cf6eSHans Rosenfeld * TX scheduler registers. 129fd43cf6eSHans Rosenfeld */ 130fd43cf6eSHans Rosenfeld #define IWN_SCHED_BASE 0xa02c00 131fd43cf6eSHans Rosenfeld #define IWN_SCHED_SRAM_ADDR (IWN_SCHED_BASE + 0x000) 132fd43cf6eSHans Rosenfeld #define IWN5000_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x008) 133fd43cf6eSHans Rosenfeld #define IWN4965_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x010) 134fd43cf6eSHans Rosenfeld #define IWN5000_SCHED_TXFACT (IWN_SCHED_BASE + 0x010) 135fd43cf6eSHans Rosenfeld #define IWN4965_SCHED_TXFACT (IWN_SCHED_BASE + 0x01c) 136fd43cf6eSHans Rosenfeld #define IWN4965_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x064 + (qid) * 4) 137fd43cf6eSHans Rosenfeld #define IWN5000_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x068 + (qid) * 4) 138fd43cf6eSHans Rosenfeld #define IWN4965_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0d0) 139fd43cf6eSHans Rosenfeld #define IWN4965_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x0e4) 140fd43cf6eSHans Rosenfeld #define IWN5000_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0e8) 141fd43cf6eSHans Rosenfeld #define IWN4965_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x104 + (qid) * 4) 142fd43cf6eSHans Rosenfeld #define IWN5000_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x108) 143fd43cf6eSHans Rosenfeld #define IWN5000_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x10c + (qid) * 4) 144fd43cf6eSHans Rosenfeld #define IWN5000_SCHED_AGGR_SEL (IWN_SCHED_BASE + 0x248) 145fd43cf6eSHans Rosenfeld 146fd43cf6eSHans Rosenfeld /* 147fd43cf6eSHans Rosenfeld * Offsets in TX scheduler's SRAM. 148fd43cf6eSHans Rosenfeld */ 149fd43cf6eSHans Rosenfeld #define IWN4965_SCHED_CTX_OFF 0x380 150fd43cf6eSHans Rosenfeld #define IWN4965_SCHED_CTX_LEN 416 151fd43cf6eSHans Rosenfeld #define IWN4965_SCHED_QUEUE_OFFSET(qid) (0x380 + (qid) * 8) 152fd43cf6eSHans Rosenfeld #define IWN4965_SCHED_TRANS_TBL(qid) (0x500 + (qid) * 2) 153fd43cf6eSHans Rosenfeld #define IWN5000_SCHED_CTX_OFF 0x600 154fd43cf6eSHans Rosenfeld #define IWN5000_SCHED_CTX_LEN 520 155fd43cf6eSHans Rosenfeld #define IWN5000_SCHED_QUEUE_OFFSET(qid) (0x600 + (qid) * 8) 156fd43cf6eSHans Rosenfeld #define IWN5000_SCHED_TRANS_TBL(qid) (0x7e0 + (qid) * 2) 157fd43cf6eSHans Rosenfeld 158fd43cf6eSHans Rosenfeld /* 159fd43cf6eSHans Rosenfeld * NIC internal memory offsets. 160fd43cf6eSHans Rosenfeld */ 161fd43cf6eSHans Rosenfeld #define IWN_APMG_CLK_CTRL 0x3000 162fd43cf6eSHans Rosenfeld #define IWN_APMG_CLK_EN 0x3004 163fd43cf6eSHans Rosenfeld #define IWN_APMG_CLK_DIS 0x3008 164fd43cf6eSHans Rosenfeld #define IWN_APMG_PS 0x300c 165fd43cf6eSHans Rosenfeld #define IWN_APMG_DIGITAL_SVR 0x3058 166fd43cf6eSHans Rosenfeld #define IWN_APMG_ANALOG_SVR 0x306c 167fd43cf6eSHans Rosenfeld #define IWN_APMG_PCI_STT 0x3010 168fd43cf6eSHans Rosenfeld #define IWN_BSM_WR_CTRL 0x3400 169fd43cf6eSHans Rosenfeld #define IWN_BSM_WR_MEM_SRC 0x3404 170fd43cf6eSHans Rosenfeld #define IWN_BSM_WR_MEM_DST 0x3408 171fd43cf6eSHans Rosenfeld #define IWN_BSM_WR_DWCOUNT 0x340c 172fd43cf6eSHans Rosenfeld #define IWN_BSM_DRAM_TEXT_ADDR 0x3490 173fd43cf6eSHans Rosenfeld #define IWN_BSM_DRAM_TEXT_SIZE 0x3494 174fd43cf6eSHans Rosenfeld #define IWN_BSM_DRAM_DATA_ADDR 0x3498 175fd43cf6eSHans Rosenfeld #define IWN_BSM_DRAM_DATA_SIZE 0x349c 176fd43cf6eSHans Rosenfeld #define IWN_BSM_SRAM_BASE 0x3800 177fd43cf6eSHans Rosenfeld 178fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_HW_IF_CONFIG. */ 179fd43cf6eSHans Rosenfeld #define IWN_HW_IF_CONFIG_4965_R (1 << 4) 180fd43cf6eSHans Rosenfeld #define IWN_HW_IF_CONFIG_MAC_SI (1 << 8) 181fd43cf6eSHans Rosenfeld #define IWN_HW_IF_CONFIG_RADIO_SI (1 << 9) 182fd43cf6eSHans Rosenfeld #define IWN_HW_IF_CONFIG_EEPROM_LOCKED (1 << 21) 183fd43cf6eSHans Rosenfeld #define IWN_HW_IF_CONFIG_NIC_READY (1 << 22) 184fd43cf6eSHans Rosenfeld #define IWN_HW_IF_CONFIG_HAP_WAKE_L1A (1 << 23) 185fd43cf6eSHans Rosenfeld #define IWN_HW_IF_CONFIG_PREPARE_DONE (1 << 25) 186fd43cf6eSHans Rosenfeld #define IWN_HW_IF_CONFIG_PREPARE (1 << 27) 187fd43cf6eSHans Rosenfeld 188fd43cf6eSHans Rosenfeld /* Possible values for register IWN_INT_PERIODIC. */ 189fd43cf6eSHans Rosenfeld #define IWN_INT_PERIODIC_DIS 0x00 190fd43cf6eSHans Rosenfeld #define IWN_INT_PERIODIC_ENA 0xff 191fd43cf6eSHans Rosenfeld 192fd43cf6eSHans Rosenfeld /* Possible flags for registers IWN_PRPH_RADDR/IWN_PRPH_WADDR. */ 193fd43cf6eSHans Rosenfeld #define IWN_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) 194fd43cf6eSHans Rosenfeld 195fd43cf6eSHans Rosenfeld /* Possible values for IWN_BSM_WR_MEM_DST. */ 196fd43cf6eSHans Rosenfeld #define IWN_FW_TEXT_BASE 0x00000000 197fd43cf6eSHans Rosenfeld #define IWN_FW_DATA_BASE 0x00800000 198fd43cf6eSHans Rosenfeld 199fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_RESET. */ 200fd43cf6eSHans Rosenfeld #define IWN_RESET_NEVO (1U << 0) 201fd43cf6eSHans Rosenfeld #define IWN_RESET_SW (1U << 7) 202fd43cf6eSHans Rosenfeld #define IWN_RESET_MASTER_DISABLED (1U << 8) 203fd43cf6eSHans Rosenfeld #define IWN_RESET_STOP_MASTER (1U << 9) 204fd43cf6eSHans Rosenfeld #define IWN_RESET_LINK_PWR_MGMT_DIS (1U << 31) 205fd43cf6eSHans Rosenfeld 206fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_GP_CNTRL. */ 207fd43cf6eSHans Rosenfeld #define IWN_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) 208fd43cf6eSHans Rosenfeld #define IWN_GP_CNTRL_MAC_CLOCK_READY (1 << 0) 209fd43cf6eSHans Rosenfeld #define IWN_GP_CNTRL_INIT_DONE (1 << 2) 210fd43cf6eSHans Rosenfeld #define IWN_GP_CNTRL_MAC_ACCESS_REQ (1 << 3) 211fd43cf6eSHans Rosenfeld #define IWN_GP_CNTRL_SLEEP (1 << 4) 212fd43cf6eSHans Rosenfeld #define IWN_GP_CNTRL_RFKILL (1 << 27) 213fd43cf6eSHans Rosenfeld 214fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_HW_REV. */ 215fd43cf6eSHans Rosenfeld #define IWN_HW_REV_TYPE_SHIFT 4 216fd43cf6eSHans Rosenfeld #define IWN_HW_REV_TYPE_MASK 0x000001f0 217fd43cf6eSHans Rosenfeld #define IWN_HW_REV_TYPE_4965 0 218fd43cf6eSHans Rosenfeld #define IWN_HW_REV_TYPE_5300 2 219fd43cf6eSHans Rosenfeld #define IWN_HW_REV_TYPE_5350 3 220fd43cf6eSHans Rosenfeld #define IWN_HW_REV_TYPE_5150 4 221fd43cf6eSHans Rosenfeld #define IWN_HW_REV_TYPE_5100 5 222fd43cf6eSHans Rosenfeld #define IWN_HW_REV_TYPE_1000 6 223fd43cf6eSHans Rosenfeld #define IWN_HW_REV_TYPE_6000 7 224fd43cf6eSHans Rosenfeld #define IWN_HW_REV_TYPE_6050 8 225fd43cf6eSHans Rosenfeld #define IWN_HW_REV_TYPE_6005 11 226fd43cf6eSHans Rosenfeld /* Types 6030 and 6035 also return 11 */ 227fd43cf6eSHans Rosenfeld #define IWN_HW_REV_TYPE_2030 12 228fd43cf6eSHans Rosenfeld #define IWN_HW_REV_TYPE_2000 16 229fd43cf6eSHans Rosenfeld #define IWN_HW_REV_TYPE_105 17 230fd43cf6eSHans Rosenfeld #define IWN_HW_REV_TYPE_135 18 231fd43cf6eSHans Rosenfeld 232fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_GIO_CHICKEN. */ 233fd43cf6eSHans Rosenfeld #define IWN_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) 234fd43cf6eSHans Rosenfeld #define IWN_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29) 235fd43cf6eSHans Rosenfeld 236fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_GIO. */ 237fd43cf6eSHans Rosenfeld #define IWN_GIO_L0S_ENA (1 << 1) 238fd43cf6eSHans Rosenfeld 239fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_GP_DRIVER. */ 240fd43cf6eSHans Rosenfeld #define IWN_GP_DRIVER_RADIO_3X3_HYB (0 << 0) 241fd43cf6eSHans Rosenfeld #define IWN_GP_DRIVER_RADIO_2X2_HYB (1 << 0) 242fd43cf6eSHans Rosenfeld #define IWN_GP_DRIVER_RADIO_2X2_IPA (2 << 0) 243fd43cf6eSHans Rosenfeld #define IWN_GP_DRIVER_CALIB_VER6 (1 << 2) 244fd43cf6eSHans Rosenfeld #define IWN_GP_DRIVER_6050_1X2 (1 << 3) 245fd43cf6eSHans Rosenfeld #define IWN_GP_DRIVER_RADIO_IQ_INVERT (1 << 7) 246fd43cf6eSHans Rosenfeld 247fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_UCODE_GP1_CLR. */ 248fd43cf6eSHans Rosenfeld #define IWN_UCODE_GP1_RFKILL (1 << 1) 249fd43cf6eSHans Rosenfeld #define IWN_UCODE_GP1_CMD_BLOCKED (1 << 2) 250fd43cf6eSHans Rosenfeld #define IWN_UCODE_GP1_CTEMP_STOP_RF (1 << 3) 251fd43cf6eSHans Rosenfeld 252fd43cf6eSHans Rosenfeld /* Possible flags/values for register IWN_LED. */ 253fd43cf6eSHans Rosenfeld #define IWN_LED_BSM_CTRL (1 << 5) 254fd43cf6eSHans Rosenfeld #define IWN_LED_OFF 0x00000038 255fd43cf6eSHans Rosenfeld #define IWN_LED_ON 0x00000078 256fd43cf6eSHans Rosenfeld 257fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_DRAM_INT_TBL. */ 258fd43cf6eSHans Rosenfeld #define IWN_DRAM_INT_TBL_WRAP_CHECK (1 << 27) 259fd43cf6eSHans Rosenfeld #define IWN_DRAM_INT_TBL_ENABLE (1 << 31) 260fd43cf6eSHans Rosenfeld 261fd43cf6eSHans Rosenfeld /* Possible values for register IWN_ANA_PLL. */ 262fd43cf6eSHans Rosenfeld #define IWN_ANA_PLL_INIT 0x00880300 263fd43cf6eSHans Rosenfeld 264fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_FH_RX_STATUS. */ 265fd43cf6eSHans Rosenfeld #define IWN_FH_RX_STATUS_IDLE (1 << 24) 266fd43cf6eSHans Rosenfeld 267fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_BSM_WR_CTRL. */ 268fd43cf6eSHans Rosenfeld #define IWN_BSM_WR_CTRL_START_EN (1 << 30) 269fd43cf6eSHans Rosenfeld #define IWN_BSM_WR_CTRL_START (1 << 31) 270fd43cf6eSHans Rosenfeld 271fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_INT. */ 272fd43cf6eSHans Rosenfeld #define IWN_INT_ALIVE (1 << 0) 273fd43cf6eSHans Rosenfeld #define IWN_INT_WAKEUP (1 << 1) 274fd43cf6eSHans Rosenfeld #define IWN_INT_SW_RX (1 << 3) 275fd43cf6eSHans Rosenfeld #define IWN_INT_CT_REACHED (1 << 6) 276fd43cf6eSHans Rosenfeld #define IWN_INT_RF_TOGGLED (1 << 7) 277fd43cf6eSHans Rosenfeld #define IWN_INT_SW_ERR (1 << 25) 278fd43cf6eSHans Rosenfeld #define IWN_INT_SCHED (1 << 26) 279fd43cf6eSHans Rosenfeld #define IWN_INT_FH_TX (1 << 27) 280fd43cf6eSHans Rosenfeld #define IWN_INT_RX_PERIODIC (1 << 28) 281fd43cf6eSHans Rosenfeld #define IWN_INT_HW_ERR (1 << 29) 282fd43cf6eSHans Rosenfeld #define IWN_INT_FH_RX (1U << 31) 283fd43cf6eSHans Rosenfeld 284fd43cf6eSHans Rosenfeld /* Shortcut. */ 285fd43cf6eSHans Rosenfeld #define IWN_INT_MASK_DEF \ 286fd43cf6eSHans Rosenfeld (IWN_INT_SW_ERR | IWN_INT_HW_ERR | IWN_INT_FH_TX | \ 287fd43cf6eSHans Rosenfeld IWN_INT_FH_RX | IWN_INT_ALIVE | IWN_INT_WAKEUP | \ 288fd43cf6eSHans Rosenfeld IWN_INT_SW_RX | IWN_INT_CT_REACHED | IWN_INT_RF_TOGGLED) 289fd43cf6eSHans Rosenfeld 290fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_FH_INT. */ 291fd43cf6eSHans Rosenfeld #define IWN_FH_INT_TX_CHNL(x) (1 << (x)) 292fd43cf6eSHans Rosenfeld #define IWN_FH_INT_RX_CHNL(x) (1 << ((x) + 16)) 293fd43cf6eSHans Rosenfeld #define IWN_FH_INT_HI_PRIOR (1 << 30) 294fd43cf6eSHans Rosenfeld /* Shortcuts for the above. */ 295fd43cf6eSHans Rosenfeld #define IWN_FH_INT_TX \ 296fd43cf6eSHans Rosenfeld (IWN_FH_INT_TX_CHNL(0) | IWN_FH_INT_TX_CHNL(1)) 297fd43cf6eSHans Rosenfeld #define IWN_FH_INT_RX \ 298fd43cf6eSHans Rosenfeld (IWN_FH_INT_RX_CHNL(0) | IWN_FH_INT_RX_CHNL(1) | IWN_FH_INT_HI_PRIOR) 299fd43cf6eSHans Rosenfeld 300fd43cf6eSHans Rosenfeld /* Possible flags/values for register IWN_FH_TX_CONFIG. */ 301fd43cf6eSHans Rosenfeld #define IWN_FH_TX_CONFIG_DMA_PAUSE 0 302fd43cf6eSHans Rosenfeld #define IWN_FH_TX_CONFIG_DMA_ENA (1U << 31) 303fd43cf6eSHans Rosenfeld #define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD (1U << 20) 304fd43cf6eSHans Rosenfeld 305fd43cf6eSHans Rosenfeld /* Possible flags/values for register IWN_FH_TXBUF_STATUS. */ 306fd43cf6eSHans Rosenfeld #define IWN_FH_TXBUF_STATUS_TBNUM(x) ((x) << 20) 307fd43cf6eSHans Rosenfeld #define IWN_FH_TXBUF_STATUS_TBIDX(x) ((x) << 12) 308fd43cf6eSHans Rosenfeld #define IWN_FH_TXBUF_STATUS_TFBD_VALID 3 309fd43cf6eSHans Rosenfeld 310fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_FH_TX_CHICKEN. */ 311fd43cf6eSHans Rosenfeld #define IWN_FH_TX_CHICKEN_SCHED_RETRY (1 << 1) 312fd43cf6eSHans Rosenfeld 313fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_FH_TX_STATUS. */ 314fd43cf6eSHans Rosenfeld #define IWN_FH_TX_STATUS_IDLE(chnl) (1 << ((chnl) + 16)) 315fd43cf6eSHans Rosenfeld 316fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_FH_RX_CONFIG. */ 317fd43cf6eSHans Rosenfeld #define IWN_FH_RX_CONFIG_ENA (1U << 31) 318fd43cf6eSHans Rosenfeld #define IWN_FH_RX_CONFIG_NRBD(x) ((x) << 20) 319fd43cf6eSHans Rosenfeld #define IWN_FH_RX_CONFIG_RB_SIZE_8K (1U << 16) 320fd43cf6eSHans Rosenfeld #define IWN_FH_RX_CONFIG_SINGLE_FRAME (1U << 15) 321fd43cf6eSHans Rosenfeld #define IWN_FH_RX_CONFIG_IRQ_DST_HOST (1U << 12) 322fd43cf6eSHans Rosenfeld #define IWN_FH_RX_CONFIG_RB_TIMEOUT(x) ((x) << 4) 323fd43cf6eSHans Rosenfeld #define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY (1U << 2) 324fd43cf6eSHans Rosenfeld 325fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_FH_TX_CONFIG. */ 326fd43cf6eSHans Rosenfeld #define IWN_FH_TX_CONFIG_DMA_ENA (1U << 31) 327fd43cf6eSHans Rosenfeld #define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA (1U << 3) 328fd43cf6eSHans Rosenfeld 329fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_EEPROM. */ 330fd43cf6eSHans Rosenfeld #define IWN_EEPROM_READ_VALID (1 << 0) 331fd43cf6eSHans Rosenfeld #define IWN_EEPROM_CMD (1 << 1) 332fd43cf6eSHans Rosenfeld 333fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_EEPROM_GP. */ 334fd43cf6eSHans Rosenfeld #define IWN_EEPROM_GP_IF_OWNER 0x00000180 335fd43cf6eSHans Rosenfeld 336fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_OTP_GP. */ 337fd43cf6eSHans Rosenfeld #define IWN_OTP_GP_DEV_SEL_OTP (1 << 16) 338fd43cf6eSHans Rosenfeld #define IWN_OTP_GP_RELATIVE_ACCESS (1 << 17) 339fd43cf6eSHans Rosenfeld #define IWN_OTP_GP_ECC_CORR_STTS (1 << 20) 340fd43cf6eSHans Rosenfeld #define IWN_OTP_GP_ECC_UNCORR_STTS (1 << 21) 341fd43cf6eSHans Rosenfeld 342fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_SCHED_QUEUE_STATUS. */ 343fd43cf6eSHans Rosenfeld #define IWN4965_TXQ_STATUS_ACTIVE 0x0007fc01 344fd43cf6eSHans Rosenfeld #define IWN4965_TXQ_STATUS_INACTIVE 0x0007fc00 345fd43cf6eSHans Rosenfeld #define IWN4965_TXQ_STATUS_AGGR_ENA (1 << 5 | 1 << 8) 346fd43cf6eSHans Rosenfeld #define IWN4965_TXQ_STATUS_CHGACT (1 << 10) 347fd43cf6eSHans Rosenfeld #define IWN5000_TXQ_STATUS_ACTIVE 0x00ff0018 348fd43cf6eSHans Rosenfeld #define IWN5000_TXQ_STATUS_INACTIVE 0x00ff0010 349fd43cf6eSHans Rosenfeld #define IWN5000_TXQ_STATUS_CHGACT (1 << 19) 350fd43cf6eSHans Rosenfeld 351fd43cf6eSHans Rosenfeld /* Possible flags for registers IWN_APMG_CLK_*. */ 352fd43cf6eSHans Rosenfeld #define IWN_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9) 353fd43cf6eSHans Rosenfeld #define IWN_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11) 354fd43cf6eSHans Rosenfeld 355fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_APMG_PS. */ 356fd43cf6eSHans Rosenfeld #define IWN_APMG_PS_EARLY_PWROFF_DIS (1 << 22) 357fd43cf6eSHans Rosenfeld #define IWN_APMG_PS_PWR_SRC(x) ((x) << 24) 358fd43cf6eSHans Rosenfeld #define IWN_APMG_PS_PWR_SRC_VMAIN 0 359fd43cf6eSHans Rosenfeld #define IWN_APMG_PS_PWR_SRC_VAUX 2 360fd43cf6eSHans Rosenfeld #define IWN_APMG_PS_PWR_SRC_MASK IWN_APMG_PS_PWR_SRC(3) 361fd43cf6eSHans Rosenfeld #define IWN_APMG_PS_RESET_REQ (1 << 26) 362fd43cf6eSHans Rosenfeld 363fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_APMG_DIGITAL_SVR. */ 364fd43cf6eSHans Rosenfeld #define IWN_APMG_DIGITAL_SVR_VOLTAGE(x) (((x) & 0xf) << 5) 365fd43cf6eSHans Rosenfeld #define IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK \ 366fd43cf6eSHans Rosenfeld IWN_APMG_DIGITAL_SVR_VOLTAGE(0xf) 367fd43cf6eSHans Rosenfeld #define IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32 \ 368fd43cf6eSHans Rosenfeld IWN_APMG_DIGITAL_SVR_VOLTAGE(3) 369fd43cf6eSHans Rosenfeld 370fd43cf6eSHans Rosenfeld /* Possible flags for IWN_APMG_PCI_STT. */ 371fd43cf6eSHans Rosenfeld #define IWN_APMG_PCI_STT_L1A_DIS (1 << 11) 372fd43cf6eSHans Rosenfeld 373fd43cf6eSHans Rosenfeld /* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */ 374fd43cf6eSHans Rosenfeld #define IWN_FW_UPDATED (1U << 31) 375fd43cf6eSHans Rosenfeld 376fd43cf6eSHans Rosenfeld #define IWN_SCHED_WINSZ 64 377fd43cf6eSHans Rosenfeld #define IWN_SCHED_LIMIT 64 378fd43cf6eSHans Rosenfeld #define IWN4965_SCHED_COUNT 512 379fd43cf6eSHans Rosenfeld #define IWN5000_SCHED_COUNT (IWN_TX_RING_COUNT + IWN_SCHED_WINSZ) 380fd43cf6eSHans Rosenfeld #define IWN4965_SCHEDSZ (IWN4965_NTXQUEUES * IWN4965_SCHED_COUNT * 2) 381fd43cf6eSHans Rosenfeld #define IWN5000_SCHEDSZ (IWN5000_NTXQUEUES * IWN5000_SCHED_COUNT * 2) 382fd43cf6eSHans Rosenfeld 383fd43cf6eSHans Rosenfeld struct iwn_tx_desc { 384fd43cf6eSHans Rosenfeld uint8_t reserved1[3]; 385fd43cf6eSHans Rosenfeld uint8_t nsegs; 386fd43cf6eSHans Rosenfeld struct { 387fd43cf6eSHans Rosenfeld uint32_t addr; 388fd43cf6eSHans Rosenfeld uint16_t len; 389fd43cf6eSHans Rosenfeld } __packed segs[IWN_MAX_SCATTER]; 390fd43cf6eSHans Rosenfeld /* Pad to 128 bytes. */ 391fd43cf6eSHans Rosenfeld uint32_t reserved2; 392fd43cf6eSHans Rosenfeld } __packed; 393fd43cf6eSHans Rosenfeld 394fd43cf6eSHans Rosenfeld struct iwn_rx_status { 395fd43cf6eSHans Rosenfeld uint16_t closed_count; 396fd43cf6eSHans Rosenfeld uint16_t closed_rx_count; 397fd43cf6eSHans Rosenfeld uint16_t finished_count; 398fd43cf6eSHans Rosenfeld uint16_t finished_rx_count; 399fd43cf6eSHans Rosenfeld uint32_t reserved[2]; 400fd43cf6eSHans Rosenfeld } __packed; 401fd43cf6eSHans Rosenfeld 402fd43cf6eSHans Rosenfeld struct iwn_rx_desc { 403fd43cf6eSHans Rosenfeld uint32_t len; 404fd43cf6eSHans Rosenfeld uint8_t type; 405fd43cf6eSHans Rosenfeld #define IWN_UC_READY 1 406fd43cf6eSHans Rosenfeld #define IWN_ADD_NODE_DONE 24 407fd43cf6eSHans Rosenfeld #define IWN_TX_DONE 28 408fd43cf6eSHans Rosenfeld #define IWN5000_CALIBRATION_RESULT 102 409fd43cf6eSHans Rosenfeld #define IWN5000_CALIBRATION_DONE 103 410fd43cf6eSHans Rosenfeld #define IWN_START_SCAN 130 411fd43cf6eSHans Rosenfeld #define IWN_STOP_SCAN 132 412fd43cf6eSHans Rosenfeld #define IWN_RX_STATISTICS 156 413fd43cf6eSHans Rosenfeld #define IWN_BEACON_STATISTICS 157 414fd43cf6eSHans Rosenfeld #define IWN_STATE_CHANGED 161 415fd43cf6eSHans Rosenfeld #define IWN_BEACON_MISSED 162 416fd43cf6eSHans Rosenfeld #define IWN_RX_PHY 192 417fd43cf6eSHans Rosenfeld #define IWN_MPDU_RX_DONE 193 418fd43cf6eSHans Rosenfeld #define IWN_RX_DONE 195 419fd43cf6eSHans Rosenfeld #define IWN_RX_COMPRESSED_BA 197 420fd43cf6eSHans Rosenfeld 421fd43cf6eSHans Rosenfeld uint8_t flags; 422fd43cf6eSHans Rosenfeld uint8_t idx; 423fd43cf6eSHans Rosenfeld uint8_t qid; 424fd43cf6eSHans Rosenfeld } __packed; 425fd43cf6eSHans Rosenfeld 426fd43cf6eSHans Rosenfeld /* Possible RX status flags. */ 427fd43cf6eSHans Rosenfeld #define IWN_RX_NO_CRC_ERR (1 << 0) 428fd43cf6eSHans Rosenfeld #define IWN_RX_NO_OVFL_ERR (1 << 1) 429fd43cf6eSHans Rosenfeld /* Shortcut for the above. */ 430fd43cf6eSHans Rosenfeld #define IWN_RX_NOERROR (IWN_RX_NO_CRC_ERR | IWN_RX_NO_OVFL_ERR) 431fd43cf6eSHans Rosenfeld #define IWN_RX_MPDU_MIC_OK (1 << 6) 432fd43cf6eSHans Rosenfeld #define IWN_RX_CIPHER_MASK (7 << 8) 433fd43cf6eSHans Rosenfeld #define IWN_RX_CIPHER_CCMP (2 << 8) 434fd43cf6eSHans Rosenfeld #define IWN_RX_MPDU_DEC (1 << 11) 435fd43cf6eSHans Rosenfeld #define IWN_RX_DECRYPT_MASK (3 << 11) 436fd43cf6eSHans Rosenfeld #define IWN_RX_DECRYPT_OK (3 << 11) 437fd43cf6eSHans Rosenfeld 438fd43cf6eSHans Rosenfeld struct iwn_tx_cmd { 439fd43cf6eSHans Rosenfeld uint8_t code; 440fd43cf6eSHans Rosenfeld #define IWN_CMD_RXON 16 441fd43cf6eSHans Rosenfeld #define IWN_CMD_RXON_ASSOC 17 442fd43cf6eSHans Rosenfeld #define IWN_CMD_EDCA_PARAMS 19 443fd43cf6eSHans Rosenfeld #define IWN_CMD_TIMING 20 444fd43cf6eSHans Rosenfeld #define IWN_CMD_ADD_NODE 24 445fd43cf6eSHans Rosenfeld #define IWN_CMD_TX_DATA 28 446fd43cf6eSHans Rosenfeld #define IWN_CMD_SET_LED 72 447fd43cf6eSHans Rosenfeld #define IWN_CMD_LINK_QUALITY 78 448fd43cf6eSHans Rosenfeld #define IWN5000_CMD_WIMAX_COEX 90 449fd43cf6eSHans Rosenfeld #define IWN5000_CMD_CALIB_CONFIG 101 450fd43cf6eSHans Rosenfeld #define IWN_CMD_SET_POWER_MODE 119 451fd43cf6eSHans Rosenfeld #define IWN_CMD_SCAN 128 452fd43cf6eSHans Rosenfeld #define IWN_CMD_TXPOWER_DBM 149 453fd43cf6eSHans Rosenfeld #define IWN_CMD_TXPOWER 151 454fd43cf6eSHans Rosenfeld #define IWN5000_CMD_TX_ANT_CONFIG 152 455fd43cf6eSHans Rosenfeld #define IWN_CMD_BT_COEX 155 456fd43cf6eSHans Rosenfeld #define IWN_CMD_GET_STATISTICS 156 457fd43cf6eSHans Rosenfeld #define IWN_CMD_SET_CRITICAL_TEMP 164 458fd43cf6eSHans Rosenfeld #define IWN_CMD_SET_SENSITIVITY 168 459fd43cf6eSHans Rosenfeld #define IWN_CMD_PHY_CALIB 176 460fd43cf6eSHans Rosenfeld #define IWN_CMD_BT_COEX_PRIO_TABLE 204 461fd43cf6eSHans Rosenfeld #define IWN_CMD_BT_COEX_PROT 205 462fd43cf6eSHans Rosenfeld 463fd43cf6eSHans Rosenfeld uint8_t flags; 464fd43cf6eSHans Rosenfeld uint8_t idx; 465fd43cf6eSHans Rosenfeld uint8_t qid; 466fd43cf6eSHans Rosenfeld uint8_t data[136]; 467fd43cf6eSHans Rosenfeld } __packed; 468fd43cf6eSHans Rosenfeld 469fd43cf6eSHans Rosenfeld /* Antenna flags, used in various commands. */ 470fd43cf6eSHans Rosenfeld #define IWN_ANT_A (1 << 0) 471fd43cf6eSHans Rosenfeld #define IWN_ANT_B (1 << 1) 472fd43cf6eSHans Rosenfeld #define IWN_ANT_C (1 << 2) 473fd43cf6eSHans Rosenfeld /* Shortcuts. */ 474fd43cf6eSHans Rosenfeld #define IWN_ANT_AB (IWN_ANT_A | IWN_ANT_B) 475fd43cf6eSHans Rosenfeld #define IWN_ANT_BC (IWN_ANT_B | IWN_ANT_C) 476fd43cf6eSHans Rosenfeld #define IWN_ANT_ABC (IWN_ANT_A | IWN_ANT_B | IWN_ANT_C) 477fd43cf6eSHans Rosenfeld 478fd43cf6eSHans Rosenfeld /* Structure for command IWN_CMD_RXON. */ 479fd43cf6eSHans Rosenfeld struct iwn_rxon { 480fd43cf6eSHans Rosenfeld uint8_t myaddr[IEEE80211_ADDR_LEN]; 481fd43cf6eSHans Rosenfeld uint16_t reserved1; 482fd43cf6eSHans Rosenfeld uint8_t bssid[IEEE80211_ADDR_LEN]; 483fd43cf6eSHans Rosenfeld uint16_t reserved2; 484fd43cf6eSHans Rosenfeld uint8_t wlap[IEEE80211_ADDR_LEN]; 485fd43cf6eSHans Rosenfeld uint16_t reserved3; 486fd43cf6eSHans Rosenfeld uint8_t mode; 487fd43cf6eSHans Rosenfeld #define IWN_MODE_HOSTAP 1 488fd43cf6eSHans Rosenfeld #define IWN_MODE_STA 3 489fd43cf6eSHans Rosenfeld #define IWN_MODE_IBSS 4 490fd43cf6eSHans Rosenfeld #define IWN_MODE_MONITOR 6 491fd43cf6eSHans Rosenfeld 492fd43cf6eSHans Rosenfeld uint8_t air; 493fd43cf6eSHans Rosenfeld uint16_t rxchain; 494fd43cf6eSHans Rosenfeld #define IWN_RXCHAIN_DRIVER_FORCE (1 << 0) 495fd43cf6eSHans Rosenfeld #define IWN_RXCHAIN_VALID(x) (((x) & IWN_ANT_ABC) << 1) 496fd43cf6eSHans Rosenfeld #define IWN_RXCHAIN_FORCE_SEL(x) (((x) & IWN_ANT_ABC) << 4) 497fd43cf6eSHans Rosenfeld #define IWN_RXCHAIN_FORCE_MIMO_SEL(x) (((x) & IWN_ANT_ABC) << 7) 498fd43cf6eSHans Rosenfeld #define IWN_RXCHAIN_IDLE_COUNT(x) ((x) << 10) 499fd43cf6eSHans Rosenfeld #define IWN_RXCHAIN_MIMO_COUNT(x) ((x) << 12) 500fd43cf6eSHans Rosenfeld #define IWN_RXCHAIN_MIMO_FORCE (1 << 14) 501fd43cf6eSHans Rosenfeld 502fd43cf6eSHans Rosenfeld uint8_t ofdm_mask; 503fd43cf6eSHans Rosenfeld uint8_t cck_mask; 504fd43cf6eSHans Rosenfeld uint16_t associd; 505fd43cf6eSHans Rosenfeld uint32_t flags; 506fd43cf6eSHans Rosenfeld #define IWN_RXON_24GHZ (1 << 0) 507fd43cf6eSHans Rosenfeld #define IWN_RXON_CCK (1 << 1) 508fd43cf6eSHans Rosenfeld #define IWN_RXON_AUTO (1 << 2) 509fd43cf6eSHans Rosenfeld #define IWN_RXON_SHSLOT (1 << 4) 510fd43cf6eSHans Rosenfeld #define IWN_RXON_SHPREAMBLE (1 << 5) 511fd43cf6eSHans Rosenfeld #define IWN_RXON_NODIVERSITY (1 << 7) 512fd43cf6eSHans Rosenfeld #define IWN_RXON_ANTENNA_A (1 << 8) 513fd43cf6eSHans Rosenfeld #define IWN_RXON_ANTENNA_B (1 << 9) 514fd43cf6eSHans Rosenfeld #define IWN_RXON_TSF (1 << 15) 515fd43cf6eSHans Rosenfeld #define IWN_RXON_CTS_TO_SELF (1 << 30) 516fd43cf6eSHans Rosenfeld 517fd43cf6eSHans Rosenfeld uint32_t filter; 518fd43cf6eSHans Rosenfeld #define IWN_FILTER_PROMISC (1 << 0) 519fd43cf6eSHans Rosenfeld #define IWN_FILTER_CTL (1 << 1) 520fd43cf6eSHans Rosenfeld #define IWN_FILTER_MULTICAST (1 << 2) 521fd43cf6eSHans Rosenfeld #define IWN_FILTER_NODECRYPT (1 << 3) 522fd43cf6eSHans Rosenfeld #define IWN_FILTER_MC_NODECRYPT (1 << 4) 523fd43cf6eSHans Rosenfeld #define IWN_FILTER_BSS (1 << 5) 524fd43cf6eSHans Rosenfeld #define IWN_FILTER_BEACON (1 << 6) 525fd43cf6eSHans Rosenfeld 526fd43cf6eSHans Rosenfeld uint8_t chan; 527fd43cf6eSHans Rosenfeld uint8_t reserved4; 528fd43cf6eSHans Rosenfeld uint8_t ht_single_mask; 529fd43cf6eSHans Rosenfeld uint8_t ht_dual_mask; 530fd43cf6eSHans Rosenfeld /* The following fields are for >=5000 Series only. */ 531fd43cf6eSHans Rosenfeld uint8_t ht_triple_mask; 532fd43cf6eSHans Rosenfeld uint8_t reserved5; 533fd43cf6eSHans Rosenfeld uint16_t acquisition; 534fd43cf6eSHans Rosenfeld uint16_t reserved6; 535fd43cf6eSHans Rosenfeld } __packed; 536fd43cf6eSHans Rosenfeld 537fd43cf6eSHans Rosenfeld #define IWN4965_RXONSZ (sizeof (struct iwn_rxon) - 6) 538fd43cf6eSHans Rosenfeld #define IWN5000_RXONSZ (sizeof (struct iwn_rxon)) 539fd43cf6eSHans Rosenfeld 540fd43cf6eSHans Rosenfeld /* Structure for command IWN_CMD_ASSOCIATE. */ 541fd43cf6eSHans Rosenfeld struct iwn_assoc { 542fd43cf6eSHans Rosenfeld uint32_t flags; 543fd43cf6eSHans Rosenfeld uint32_t filter; 544fd43cf6eSHans Rosenfeld uint8_t ofdm_mask; 545fd43cf6eSHans Rosenfeld uint8_t cck_mask; 546fd43cf6eSHans Rosenfeld uint16_t reserved; 547fd43cf6eSHans Rosenfeld } __packed; 548fd43cf6eSHans Rosenfeld 549fd43cf6eSHans Rosenfeld /* Structure for command IWN_CMD_EDCA_PARAMS. */ 550fd43cf6eSHans Rosenfeld struct iwn_edca_params { 551fd43cf6eSHans Rosenfeld uint32_t flags; 552fd43cf6eSHans Rosenfeld #define IWN_EDCA_UPDATE (1 << 0) 553fd43cf6eSHans Rosenfeld #define IWN_EDCA_TXOP (1 << 4) 554fd43cf6eSHans Rosenfeld 555fd43cf6eSHans Rosenfeld struct { 556fd43cf6eSHans Rosenfeld uint16_t cwmin; 557fd43cf6eSHans Rosenfeld uint16_t cwmax; 558fd43cf6eSHans Rosenfeld uint8_t aifsn; 559fd43cf6eSHans Rosenfeld uint8_t reserved; 560fd43cf6eSHans Rosenfeld uint16_t txoplimit; 561fd43cf6eSHans Rosenfeld } __packed ac[WME_NUM_AC]; 562fd43cf6eSHans Rosenfeld } __packed; 563fd43cf6eSHans Rosenfeld 564fd43cf6eSHans Rosenfeld /* Structure for command IWN_CMD_TIMING. */ 565fd43cf6eSHans Rosenfeld struct iwn_cmd_timing { 566fd43cf6eSHans Rosenfeld uint64_t tstamp; 567fd43cf6eSHans Rosenfeld uint16_t bintval; 568fd43cf6eSHans Rosenfeld uint16_t atim; 569fd43cf6eSHans Rosenfeld uint32_t binitval; 570fd43cf6eSHans Rosenfeld uint16_t lintval; 571fd43cf6eSHans Rosenfeld uint16_t reserved; 572fd43cf6eSHans Rosenfeld } __packed; 573fd43cf6eSHans Rosenfeld 574fd43cf6eSHans Rosenfeld /* Structure for command IWN_CMD_ADD_NODE. */ 575fd43cf6eSHans Rosenfeld struct iwn_node_info { 576fd43cf6eSHans Rosenfeld uint8_t control; 577fd43cf6eSHans Rosenfeld #define IWN_NODE_UPDATE (1 << 0) 578fd43cf6eSHans Rosenfeld 579fd43cf6eSHans Rosenfeld uint8_t reserved1[3]; 580fd43cf6eSHans Rosenfeld 581fd43cf6eSHans Rosenfeld uint8_t macaddr[IEEE80211_ADDR_LEN]; 582fd43cf6eSHans Rosenfeld uint16_t reserved2; 583fd43cf6eSHans Rosenfeld uint8_t id; 584fd43cf6eSHans Rosenfeld #define IWN_ID_BSS 0 585fd43cf6eSHans Rosenfeld #define IWN5000_ID_BROADCAST 15 586fd43cf6eSHans Rosenfeld #define IWN4965_ID_BROADCAST 31 587fd43cf6eSHans Rosenfeld 588fd43cf6eSHans Rosenfeld uint8_t flags; 589fd43cf6eSHans Rosenfeld #define IWN_FLAG_SET_KEY (1 << 0) 590fd43cf6eSHans Rosenfeld #define IWN_FLAG_SET_DISABLE_TID (1 << 1) 591fd43cf6eSHans Rosenfeld #define IWN_FLAG_SET_TXRATE (1 << 2) 592fd43cf6eSHans Rosenfeld #define IWN_FLAG_SET_ADDBA (1 << 3) 593fd43cf6eSHans Rosenfeld #define IWN_FLAG_SET_DELBA (1 << 4) 594fd43cf6eSHans Rosenfeld 595fd43cf6eSHans Rosenfeld uint16_t reserved3; 596fd43cf6eSHans Rosenfeld uint16_t kflags; 597fd43cf6eSHans Rosenfeld #define IWN_KFLAG_CCMP (1 << 1) 598fd43cf6eSHans Rosenfeld #define IWN_KFLAG_MAP (1 << 3) 599fd43cf6eSHans Rosenfeld #define IWN_KFLAG_KID(kid) ((kid) << 8) 600fd43cf6eSHans Rosenfeld #define IWN_KFLAG_INVALID (1 << 11) 601fd43cf6eSHans Rosenfeld #define IWN_KFLAG_GROUP (1 << 14) 602fd43cf6eSHans Rosenfeld 603fd43cf6eSHans Rosenfeld uint8_t tsc2; /* TKIP TSC2 */ 604fd43cf6eSHans Rosenfeld uint8_t reserved4; 605fd43cf6eSHans Rosenfeld uint16_t ttak[5]; 606fd43cf6eSHans Rosenfeld uint8_t kid; 607fd43cf6eSHans Rosenfeld uint8_t reserved5; 608fd43cf6eSHans Rosenfeld uint8_t key[16]; 609fd43cf6eSHans Rosenfeld /* The following 3 fields are for 5000 Series only. */ 610fd43cf6eSHans Rosenfeld uint64_t tsc; 611fd43cf6eSHans Rosenfeld uint8_t rxmic[IEEE80211_TKIP_MICLEN]; 612fd43cf6eSHans Rosenfeld uint8_t txmic[IEEE80211_TKIP_MICLEN]; 613fd43cf6eSHans Rosenfeld 614fd43cf6eSHans Rosenfeld uint32_t htflags; 615fd43cf6eSHans Rosenfeld #define IWN_AMDPU_SIZE_FACTOR(x) ((x) << 19) 616fd43cf6eSHans Rosenfeld #define IWN_AMDPU_DENSITY(x) ((x) << 23) 617fd43cf6eSHans Rosenfeld 618fd43cf6eSHans Rosenfeld uint32_t mask; 619fd43cf6eSHans Rosenfeld uint16_t disable_tid; 620fd43cf6eSHans Rosenfeld uint16_t reserved6; 621fd43cf6eSHans Rosenfeld uint8_t addba_tid; 622fd43cf6eSHans Rosenfeld uint8_t delba_tid; 623fd43cf6eSHans Rosenfeld uint16_t addba_ssn; 624fd43cf6eSHans Rosenfeld uint32_t reserved7; 625fd43cf6eSHans Rosenfeld } __packed; 626fd43cf6eSHans Rosenfeld 627fd43cf6eSHans Rosenfeld struct iwn4965_node_info { 628fd43cf6eSHans Rosenfeld uint8_t control; 629fd43cf6eSHans Rosenfeld uint8_t reserved1[3]; 630fd43cf6eSHans Rosenfeld uint8_t macaddr[IEEE80211_ADDR_LEN]; 631fd43cf6eSHans Rosenfeld uint16_t reserved2; 632fd43cf6eSHans Rosenfeld uint8_t id; 633fd43cf6eSHans Rosenfeld uint8_t flags; 634fd43cf6eSHans Rosenfeld uint16_t reserved3; 635fd43cf6eSHans Rosenfeld uint16_t kflags; 636fd43cf6eSHans Rosenfeld uint8_t tsc2; /* TKIP TSC2 */ 637fd43cf6eSHans Rosenfeld uint8_t reserved4; 638fd43cf6eSHans Rosenfeld uint16_t ttak[5]; 639fd43cf6eSHans Rosenfeld uint8_t kid; 640fd43cf6eSHans Rosenfeld uint8_t reserved5; 641fd43cf6eSHans Rosenfeld uint8_t key[16]; 642fd43cf6eSHans Rosenfeld uint32_t htflags; 643fd43cf6eSHans Rosenfeld uint32_t mask; 644fd43cf6eSHans Rosenfeld uint16_t disable_tid; 645fd43cf6eSHans Rosenfeld uint16_t reserved6; 646fd43cf6eSHans Rosenfeld uint8_t addba_tid; 647fd43cf6eSHans Rosenfeld uint8_t delba_tid; 648fd43cf6eSHans Rosenfeld uint16_t addba_ssn; 649fd43cf6eSHans Rosenfeld uint32_t reserved7; 650fd43cf6eSHans Rosenfeld } __packed; 651fd43cf6eSHans Rosenfeld 652fd43cf6eSHans Rosenfeld #define IWN_RFLAG_CCK (1 << 1) 653fd43cf6eSHans Rosenfeld #define IWN_RFLAG_ANT(x) ((x) << 6) 654fd43cf6eSHans Rosenfeld 655fd43cf6eSHans Rosenfeld /* Structure for command IWN_CMD_TX_DATA. */ 656fd43cf6eSHans Rosenfeld struct iwn_cmd_data { 657fd43cf6eSHans Rosenfeld uint16_t len; 658fd43cf6eSHans Rosenfeld uint16_t lnext; 659fd43cf6eSHans Rosenfeld uint32_t flags; 660fd43cf6eSHans Rosenfeld #define IWN_TX_NEED_PROTECTION (1 << 0) /* 5000 only */ 661fd43cf6eSHans Rosenfeld #define IWN_TX_NEED_RTS (1 << 1) 662fd43cf6eSHans Rosenfeld #define IWN_TX_NEED_CTS (1 << 2) 663fd43cf6eSHans Rosenfeld #define IWN_TX_NEED_ACK (1 << 3) 664fd43cf6eSHans Rosenfeld #define IWN_TX_LINKQ (1 << 4) 665fd43cf6eSHans Rosenfeld #define IWN_TX_IMM_BA (1 << 6) 666fd43cf6eSHans Rosenfeld #define IWN_TX_FULL_TXOP (1 << 7) 667fd43cf6eSHans Rosenfeld #define IWN_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 668fd43cf6eSHans Rosenfeld #define IWN_TX_AUTO_SEQ (1 << 13) 669fd43cf6eSHans Rosenfeld #define IWN_TX_MORE_FRAG (1 << 14) 670fd43cf6eSHans Rosenfeld #define IWN_TX_INSERT_TSTAMP (1 << 16) 671fd43cf6eSHans Rosenfeld #define IWN_TX_NEED_PADDING (1 << 20) 672fd43cf6eSHans Rosenfeld 673fd43cf6eSHans Rosenfeld uint32_t scratch; 674fd43cf6eSHans Rosenfeld uint8_t plcp; 675fd43cf6eSHans Rosenfeld uint8_t rflags; 676fd43cf6eSHans Rosenfeld uint16_t xrflags; 677fd43cf6eSHans Rosenfeld 678fd43cf6eSHans Rosenfeld uint8_t id; 679fd43cf6eSHans Rosenfeld uint8_t security; 680fd43cf6eSHans Rosenfeld #define IWN_CIPHER_WEP40 1 681fd43cf6eSHans Rosenfeld #define IWN_CIPHER_CCMP 2 682fd43cf6eSHans Rosenfeld #define IWN_CIPHER_TKIP 3 683fd43cf6eSHans Rosenfeld #define IWN_CIPHER_WEP104 9 684fd43cf6eSHans Rosenfeld 685fd43cf6eSHans Rosenfeld uint8_t linkq; 686fd43cf6eSHans Rosenfeld uint8_t reserved2; 687fd43cf6eSHans Rosenfeld uint8_t key[16]; 688fd43cf6eSHans Rosenfeld uint16_t fnext; 689fd43cf6eSHans Rosenfeld uint16_t reserved3; 690fd43cf6eSHans Rosenfeld uint32_t lifetime; 691fd43cf6eSHans Rosenfeld #define IWN_LIFETIME_INFINITE 0xffffffff 692fd43cf6eSHans Rosenfeld 693fd43cf6eSHans Rosenfeld uint32_t loaddr; 694fd43cf6eSHans Rosenfeld uint8_t hiaddr; 695fd43cf6eSHans Rosenfeld uint8_t rts_ntries; 696fd43cf6eSHans Rosenfeld uint8_t data_ntries; 697fd43cf6eSHans Rosenfeld uint8_t tid; 698fd43cf6eSHans Rosenfeld uint16_t timeout; 699fd43cf6eSHans Rosenfeld uint16_t txop; 700fd43cf6eSHans Rosenfeld } __packed; 701fd43cf6eSHans Rosenfeld 702fd43cf6eSHans Rosenfeld /* Structure for command IWN_CMD_LINK_QUALITY. */ 703fd43cf6eSHans Rosenfeld #define IWN_MAX_TX_RETRIES 16 704fd43cf6eSHans Rosenfeld struct iwn_cmd_link_quality { 705fd43cf6eSHans Rosenfeld uint8_t id; 706fd43cf6eSHans Rosenfeld uint8_t reserved1; 707fd43cf6eSHans Rosenfeld uint16_t ctl; 708fd43cf6eSHans Rosenfeld uint8_t flags; 709fd43cf6eSHans Rosenfeld uint8_t mimo; 710fd43cf6eSHans Rosenfeld uint8_t antmsk_1stream; 711fd43cf6eSHans Rosenfeld uint8_t antmsk_2stream; 712fd43cf6eSHans Rosenfeld uint8_t ridx[WME_NUM_AC]; 713fd43cf6eSHans Rosenfeld uint16_t ampdu_limit; 714fd43cf6eSHans Rosenfeld uint8_t ampdu_threshold; 715fd43cf6eSHans Rosenfeld uint8_t ampdu_max; 716fd43cf6eSHans Rosenfeld uint32_t reserved2; 717fd43cf6eSHans Rosenfeld struct { 718fd43cf6eSHans Rosenfeld uint8_t plcp; 719fd43cf6eSHans Rosenfeld uint8_t rflags; 720fd43cf6eSHans Rosenfeld uint16_t xrflags; 721fd43cf6eSHans Rosenfeld } __packed retry[IWN_MAX_TX_RETRIES]; 722fd43cf6eSHans Rosenfeld uint32_t reserved3; 723fd43cf6eSHans Rosenfeld } __packed; 724fd43cf6eSHans Rosenfeld 725fd43cf6eSHans Rosenfeld /* Structure for command IWN_CMD_SET_LED. */ 726fd43cf6eSHans Rosenfeld struct iwn_cmd_led { 727fd43cf6eSHans Rosenfeld uint32_t unit; /* multiplier (in usecs) */ 728fd43cf6eSHans Rosenfeld uint8_t which; 729fd43cf6eSHans Rosenfeld #define IWN_LED_ACTIVITY 1 730fd43cf6eSHans Rosenfeld #define IWN_LED_LINK 2 731fd43cf6eSHans Rosenfeld 732fd43cf6eSHans Rosenfeld uint8_t off; 733fd43cf6eSHans Rosenfeld uint8_t on; 734fd43cf6eSHans Rosenfeld uint8_t reserved; 735fd43cf6eSHans Rosenfeld } __packed; 736fd43cf6eSHans Rosenfeld 737fd43cf6eSHans Rosenfeld /* Structure for command IWN5000_CMD_WIMAX_COEX. */ 738fd43cf6eSHans Rosenfeld struct iwn5000_wimax_coex { 739fd43cf6eSHans Rosenfeld uint32_t flags; 740fd43cf6eSHans Rosenfeld #define IWN_WIMAX_COEX_STA_TABLE_VALID (1 << 0) 741fd43cf6eSHans Rosenfeld #define IWN_WIMAX_COEX_UNASSOC_WA_UNMASK (1 << 2) 742fd43cf6eSHans Rosenfeld #define IWN_WIMAX_COEX_ASSOC_WA_UNMASK (1 << 3) 743fd43cf6eSHans Rosenfeld #define IWN_WIMAX_COEX_ENABLE (1 << 7) 744fd43cf6eSHans Rosenfeld 745fd43cf6eSHans Rosenfeld struct iwn5000_wimax_event { 746fd43cf6eSHans Rosenfeld uint8_t request; 747fd43cf6eSHans Rosenfeld uint8_t window; 748fd43cf6eSHans Rosenfeld uint8_t reserved; 749fd43cf6eSHans Rosenfeld uint8_t flags; 750fd43cf6eSHans Rosenfeld } __packed events[16]; 751fd43cf6eSHans Rosenfeld } __packed; 752fd43cf6eSHans Rosenfeld 753fd43cf6eSHans Rosenfeld /* Structures for command IWN5000_CMD_CALIB_CONFIG. */ 754fd43cf6eSHans Rosenfeld struct iwn5000_calib_elem { 755fd43cf6eSHans Rosenfeld uint32_t enable; 756fd43cf6eSHans Rosenfeld uint32_t start; 757fd43cf6eSHans Rosenfeld #define IWN5000_CALIB_DC (1 << 1) 758fd43cf6eSHans Rosenfeld uint32_t send; 759fd43cf6eSHans Rosenfeld uint32_t apply; 760fd43cf6eSHans Rosenfeld uint32_t reserved; 761fd43cf6eSHans Rosenfeld } __packed; 762fd43cf6eSHans Rosenfeld 763fd43cf6eSHans Rosenfeld struct iwn5000_calib_status { 764fd43cf6eSHans Rosenfeld struct iwn5000_calib_elem once; 765fd43cf6eSHans Rosenfeld struct iwn5000_calib_elem perd; 766fd43cf6eSHans Rosenfeld uint32_t flags; 767fd43cf6eSHans Rosenfeld } __packed; 768fd43cf6eSHans Rosenfeld 769fd43cf6eSHans Rosenfeld struct iwn5000_calib_config { 770fd43cf6eSHans Rosenfeld struct iwn5000_calib_status ucode; 771fd43cf6eSHans Rosenfeld struct iwn5000_calib_status driver; 772fd43cf6eSHans Rosenfeld uint32_t reserved; 773fd43cf6eSHans Rosenfeld } __packed; 774fd43cf6eSHans Rosenfeld 775fd43cf6eSHans Rosenfeld /* Structure for command IWN_CMD_SET_POWER_MODE. */ 776fd43cf6eSHans Rosenfeld struct iwn_pmgt_cmd { 777fd43cf6eSHans Rosenfeld uint16_t flags; 778fd43cf6eSHans Rosenfeld #define IWN_PS_ALLOW_SLEEP (1 << 0) 779fd43cf6eSHans Rosenfeld #define IWN_PS_NOTIFY (1 << 1) 780fd43cf6eSHans Rosenfeld #define IWN_PS_SLEEP_OVER_DTIM (1 << 2) 781fd43cf6eSHans Rosenfeld #define IWN_PS_PCI_PMGT (1 << 3) 782fd43cf6eSHans Rosenfeld #define IWN_PS_FAST_PD (1 << 4) 783fd43cf6eSHans Rosenfeld 784fd43cf6eSHans Rosenfeld uint8_t keepalive; 785fd43cf6eSHans Rosenfeld uint8_t debug; 786fd43cf6eSHans Rosenfeld uint32_t rxtimeout; 787fd43cf6eSHans Rosenfeld uint32_t txtimeout; 788fd43cf6eSHans Rosenfeld uint32_t intval[5]; 789fd43cf6eSHans Rosenfeld uint32_t beacons; 790fd43cf6eSHans Rosenfeld } __packed; 791fd43cf6eSHans Rosenfeld 792fd43cf6eSHans Rosenfeld /* Structures for command IWN_CMD_SCAN. */ 793fd43cf6eSHans Rosenfeld struct iwn_scan_essid { 794fd43cf6eSHans Rosenfeld uint8_t id; 795fd43cf6eSHans Rosenfeld uint8_t len; 796fd43cf6eSHans Rosenfeld uint8_t data[IEEE80211_NWID_LEN]; 797fd43cf6eSHans Rosenfeld } __packed; 798fd43cf6eSHans Rosenfeld 799fd43cf6eSHans Rosenfeld struct iwn_scan_hdr { 800fd43cf6eSHans Rosenfeld uint16_t len; 801fd43cf6eSHans Rosenfeld uint8_t scan_flags; 802fd43cf6eSHans Rosenfeld #define IWN_SCAN_PASSIVE2ACTIVE (1<<5) 803fd43cf6eSHans Rosenfeld 804fd43cf6eSHans Rosenfeld uint8_t nchan; 805fd43cf6eSHans Rosenfeld uint16_t quiet_time; 806fd43cf6eSHans Rosenfeld uint16_t quiet_threshold; 807fd43cf6eSHans Rosenfeld uint16_t crc_threshold; 808fd43cf6eSHans Rosenfeld uint16_t rxchain; 809fd43cf6eSHans Rosenfeld uint32_t max_svc; /* background scans */ 810fd43cf6eSHans Rosenfeld uint32_t pause_svc; /* background scans */ 811fd43cf6eSHans Rosenfeld uint32_t flags; 812fd43cf6eSHans Rosenfeld uint32_t filter; 813fd43cf6eSHans Rosenfeld 814fd43cf6eSHans Rosenfeld /* Followed by a struct iwn_cmd_data. */ 815fd43cf6eSHans Rosenfeld /* Followed by an array of 20 structs iwn_scan_essid. */ 816fd43cf6eSHans Rosenfeld /* Followed by probe request body. */ 817fd43cf6eSHans Rosenfeld /* Followed by an array of ``nchan'' structs iwn_scan_chan. */ 818fd43cf6eSHans Rosenfeld } __packed; 819fd43cf6eSHans Rosenfeld 820fd43cf6eSHans Rosenfeld struct iwn_scan_chan { 821fd43cf6eSHans Rosenfeld uint32_t flags; 822fd43cf6eSHans Rosenfeld #define IWN_CHAN_ACTIVE (1 << 0) 823fd43cf6eSHans Rosenfeld #define IWN_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) 824fd43cf6eSHans Rosenfeld 825fd43cf6eSHans Rosenfeld uint16_t chan; 826fd43cf6eSHans Rosenfeld uint8_t rf_gain; 827fd43cf6eSHans Rosenfeld uint8_t dsp_gain; 828fd43cf6eSHans Rosenfeld uint16_t active; /* msecs */ 829fd43cf6eSHans Rosenfeld uint16_t passive; /* msecs */ 830fd43cf6eSHans Rosenfeld } __packed; 831fd43cf6eSHans Rosenfeld 832fd43cf6eSHans Rosenfeld /* Maximum size of a scan command. */ 833fd43cf6eSHans Rosenfeld #define IWN_SCAN_MAXSZ 4092 834fd43cf6eSHans Rosenfeld 835fd43cf6eSHans Rosenfeld /* 836fd43cf6eSHans Rosenfeld * For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after 837fd43cf6eSHans Rosenfeld * sending probe req. This should be set long enough to hear probe responses 838fd43cf6eSHans Rosenfeld * from more than one AP. 839fd43cf6eSHans Rosenfeld */ 840fd43cf6eSHans Rosenfeld #define IWN_ACTIVE_DWELL_TIME_2GHZ (30) /* all times in msec */ 841fd43cf6eSHans Rosenfeld #define IWN_ACTIVE_DWELL_TIME_5GHZ (20) 842fd43cf6eSHans Rosenfeld #define IWN_ACTIVE_DWELL_FACTOR_2GHZ (3) 843fd43cf6eSHans Rosenfeld #define IWN_ACTIVE_DWELL_FACTOR_5GHZ (2) 844fd43cf6eSHans Rosenfeld 845fd43cf6eSHans Rosenfeld /* 846fd43cf6eSHans Rosenfeld * For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel. 847fd43cf6eSHans Rosenfeld * Must be set longer than active dwell time. 848fd43cf6eSHans Rosenfeld * For the most reliable scan, set > AP beacon interval (typically 100msec). 849fd43cf6eSHans Rosenfeld */ 850fd43cf6eSHans Rosenfeld #define IWN_PASSIVE_DWELL_TIME_2GHZ (20) /* all times in msec */ 851fd43cf6eSHans Rosenfeld #define IWN_PASSIVE_DWELL_TIME_5GHZ (10) 852fd43cf6eSHans Rosenfeld #define IWN_PASSIVE_DWELL_BASE (100) 853fd43cf6eSHans Rosenfeld #define IWN_CHANNEL_TUNE_TIME (5) 854fd43cf6eSHans Rosenfeld 855fd43cf6eSHans Rosenfeld /* 856fd43cf6eSHans Rosenfeld * If active scanning is requested but a certain channel is 857fd43cf6eSHans Rosenfeld * marked passive, we can do active scanning if we detect 858fd43cf6eSHans Rosenfeld * transmissions. 859fd43cf6eSHans Rosenfeld * 860fd43cf6eSHans Rosenfeld * There is an issue with some firmware versions that triggers 861fd43cf6eSHans Rosenfeld * a sysassert on a "good CRC threshold" of zero (== disabled), 862fd43cf6eSHans Rosenfeld * on a radar channel even though this means that we should NOT 863fd43cf6eSHans Rosenfeld * send probes. 864fd43cf6eSHans Rosenfeld * 865fd43cf6eSHans Rosenfeld * The "good CRC threshold" is the number of frames that we 866fd43cf6eSHans Rosenfeld * need to receive during our dwell time on a channel before 867fd43cf6eSHans Rosenfeld * sending out probes -- setting this to a huge value will 868fd43cf6eSHans Rosenfeld * mean we never reach it, but at the same time work around 869fd43cf6eSHans Rosenfeld * the aforementioned issue. Thus use IWN_GOOD_CRC_TH_NEVER 870fd43cf6eSHans Rosenfeld * here instead of IWN_GOOD_CRC_TH_DISABLED. 871fd43cf6eSHans Rosenfeld * 872fd43cf6eSHans Rosenfeld * This was fixed in later versions along with some other 873fd43cf6eSHans Rosenfeld * scan changes, and the threshold behaves as a flag in those 874fd43cf6eSHans Rosenfeld * versions. 875fd43cf6eSHans Rosenfeld */ 876fd43cf6eSHans Rosenfeld #define IWN_GOOD_CRC_TH_DISABLED 0 877fd43cf6eSHans Rosenfeld #define IWN_GOOD_CRC_TH_DEFAULT htole16(1) 878fd43cf6eSHans Rosenfeld #define IWN_GOOD_CRC_TH_NEVER htole16(0xffff) 879fd43cf6eSHans Rosenfeld 880fd43cf6eSHans Rosenfeld /* Structure for command IWN_CMD_TXPOWER (4965AGN only.) */ 881fd43cf6eSHans Rosenfeld #define IWN_RIDX_MAX 32 882fd43cf6eSHans Rosenfeld struct iwn4965_cmd_txpower { 883fd43cf6eSHans Rosenfeld uint8_t band; 884fd43cf6eSHans Rosenfeld uint8_t reserved1; 885fd43cf6eSHans Rosenfeld uint8_t chan; 886fd43cf6eSHans Rosenfeld uint8_t reserved2; 887fd43cf6eSHans Rosenfeld struct { 888fd43cf6eSHans Rosenfeld uint8_t rf_gain[2]; 889fd43cf6eSHans Rosenfeld uint8_t dsp_gain[2]; 890fd43cf6eSHans Rosenfeld } __packed power[IWN_RIDX_MAX + 1]; 891fd43cf6eSHans Rosenfeld } __packed; 892fd43cf6eSHans Rosenfeld 893fd43cf6eSHans Rosenfeld /* Structure for command IWN_CMD_TXPOWER_DBM (5000 Series only.) */ 894fd43cf6eSHans Rosenfeld struct iwn5000_cmd_txpower { 895fd43cf6eSHans Rosenfeld int8_t global_limit; /* in half-dBm */ 896fd43cf6eSHans Rosenfeld #define IWN5000_TXPOWER_AUTO 0x7f 897fd43cf6eSHans Rosenfeld #define IWN5000_TXPOWER_MAX_DBM 16 898fd43cf6eSHans Rosenfeld 899fd43cf6eSHans Rosenfeld uint8_t flags; 900fd43cf6eSHans Rosenfeld #define IWN5000_TXPOWER_NO_CLOSED (1 << 6) 901fd43cf6eSHans Rosenfeld 902fd43cf6eSHans Rosenfeld int8_t srv_limit; /* in half-dBm */ 903fd43cf6eSHans Rosenfeld uint8_t reserved; 904fd43cf6eSHans Rosenfeld } __packed; 905fd43cf6eSHans Rosenfeld 906fd43cf6eSHans Rosenfeld /* Structure for command IWN_CMD_BT_COEX. */ 907fd43cf6eSHans Rosenfeld struct iwn_bluetooth { 908fd43cf6eSHans Rosenfeld uint8_t flags; 909fd43cf6eSHans Rosenfeld #define IWN_BT_COEX_CHAN_ANN (1 << 0) 910fd43cf6eSHans Rosenfeld #define IWN_BT_COEX_BT_PRIO (1 << 1) 911fd43cf6eSHans Rosenfeld #define IWN_BT_COEX_2_WIRE (1 << 2) 912fd43cf6eSHans Rosenfeld #define IWN_BT_COEX_ENABLE (IWN_BT_COEX_CHAN_ANN | IWN_BT_COEX_BT_PRIO) 913fd43cf6eSHans Rosenfeld uint8_t lead_time; 914fd43cf6eSHans Rosenfeld #define IWN_BT_LEAD_TIME_DEF 30 915fd43cf6eSHans Rosenfeld uint8_t max_kill; 916fd43cf6eSHans Rosenfeld #define IWN_BT_MAX_KILL_DEF 5 917fd43cf6eSHans Rosenfeld uint8_t bt3_timer_t7_value; 918fd43cf6eSHans Rosenfeld #define IWN_BT_BT3_T7_DEF 1 919fd43cf6eSHans Rosenfeld uint32_t kill_ack_mask; 920fd43cf6eSHans Rosenfeld #define IWN_BT_KILL_ACK_MASK_DEF htole32(0xffff0000) 921fd43cf6eSHans Rosenfeld uint32_t kill_cts_mask; 922fd43cf6eSHans Rosenfeld #define IWN_BT_KILL_CTS_MASK_DEF htole32(0xffff0000) 923fd43cf6eSHans Rosenfeld } __packed; 924fd43cf6eSHans Rosenfeld 925fd43cf6eSHans Rosenfeld struct iwn_bt_basic { 926fd43cf6eSHans Rosenfeld struct iwn_bluetooth bt; 927fd43cf6eSHans Rosenfeld #define IWN_BT_BASIC_CHAN_INHIBITION 1 928fd43cf6eSHans Rosenfeld #define IWN_BT_BASIC_MODE_MASK ((1 << 3) | (1 << 4) | (1 << 5)) 929fd43cf6eSHans Rosenfeld #define IWN_BT_BASIC_MODE_SHIFT 3 930fd43cf6eSHans Rosenfeld #define IWN_BT_BASIC_MODE_DISABLED 0 931fd43cf6eSHans Rosenfeld #define IWN_BT_BASIC_MODE_LEGACY_2W 1 932fd43cf6eSHans Rosenfeld #define IWN_BT_BASIC_MODE_3W 2 933fd43cf6eSHans Rosenfeld #define IWN_BT_BASIC_MODE_4W 3 934fd43cf6eSHans Rosenfeld #define IWN_BT_UCODE_DEFAULT (1 << 6) 935fd43cf6eSHans Rosenfeld #define IWN_BT_SYNC_2_BT_DISABLE (1 << 7) 936fd43cf6eSHans Rosenfeld uint8_t bt3_prio_sample_time; 937fd43cf6eSHans Rosenfeld #define IWN_BT_BT3_PRIO_SAMPLE_DEF 2 938fd43cf6eSHans Rosenfeld uint8_t bt3_timer_t2_value; 939fd43cf6eSHans Rosenfeld #define IWN_BT_BT3_T2_DEF 12 940fd43cf6eSHans Rosenfeld uint16_t bt4_reaction_time; /* unused */ 941fd43cf6eSHans Rosenfeld uint32_t bt3_lookup_table[12]; 942fd43cf6eSHans Rosenfeld 943fd43cf6eSHans Rosenfeld uint16_t reduce_txpower; /* bit 0 */ 944fd43cf6eSHans Rosenfeld #if 0 945fd43cf6eSHans Rosenfeld /* 946fd43cf6eSHans Rosenfeld * The original code causes problems with lint. These declarations 947fd43cf6eSHans Rosenfeld * could be fixed with lint tags, but the assignment to 948fd43cf6eSHans Rosenfeld * reduce_txpower in iwn_config_bt_coex_adv_config() cannot. 949fd43cf6eSHans Rosenfeld * For reference it remains here but is ifdef'ed out. 950fd43cf6eSHans Rosenfeld */ 951fd43cf6eSHans Rosenfeld union { 952fd43cf6eSHans Rosenfeld struct { 953fd43cf6eSHans Rosenfeld uint8_t reduce_txpower; /* bit 0 */ 954fd43cf6eSHans Rosenfeld uint8_t reserved; 955fd43cf6eSHans Rosenfeld }; 956fd43cf6eSHans Rosenfeld uint16_t bt4_decision; 957fd43cf6eSHans Rosenfeld }; 958fd43cf6eSHans Rosenfeld #endif 959fd43cf6eSHans Rosenfeld uint16_t valid; 960fd43cf6eSHans Rosenfeld #define IWN_BT_VALID_ENABLE_FLAGS htole16(1 << 0) 961fd43cf6eSHans Rosenfeld #define IWN_BT_VALID_BOOST htole16(1 << 1) 962fd43cf6eSHans Rosenfeld #define IWN_BT_VALID_MAX_KILL htole16(1 << 2) 963fd43cf6eSHans Rosenfeld #define IWN_BT_VALID_3W_TIMERS htole16(1 << 3) 964fd43cf6eSHans Rosenfeld #define IWN_BT_VALID_KILL_ACK_MASK htole16(1 << 4) 965fd43cf6eSHans Rosenfeld #define IWN_BT_VALID_KILL_CTS_MASK htole16(1 << 5) 966fd43cf6eSHans Rosenfeld #define IWN_BT_VALID_REDUCED_TX_PWR htole16(1 << 6) 967fd43cf6eSHans Rosenfeld #define IWN_BT_VALID_3W_LUT htole16(1 << 7) 968fd43cf6eSHans Rosenfeld #define IWN_BT_ALL_VALID_MASK (IWN_BT_VALID_ENABLE_FLAGS | \ 969fd43cf6eSHans Rosenfeld IWN_BT_VALID_BOOST | \ 970fd43cf6eSHans Rosenfeld IWN_BT_VALID_MAX_KILL | \ 971fd43cf6eSHans Rosenfeld IWN_BT_VALID_3W_TIMERS | \ 972fd43cf6eSHans Rosenfeld IWN_BT_VALID_KILL_ACK_MASK | \ 973fd43cf6eSHans Rosenfeld IWN_BT_VALID_KILL_CTS_MASK | \ 974fd43cf6eSHans Rosenfeld IWN_BT_VALID_REDUCED_TX_PWR | \ 975fd43cf6eSHans Rosenfeld IWN_BT_VALID_3W_LUT) 976fd43cf6eSHans Rosenfeld } __packed; 977fd43cf6eSHans Rosenfeld 978fd43cf6eSHans Rosenfeld struct iwn_bt_adv1 { 979fd43cf6eSHans Rosenfeld struct iwn_bt_basic basic; 980fd43cf6eSHans Rosenfeld uint8_t prio_boost; 981fd43cf6eSHans Rosenfeld #define IWN_BT_PRIO_BOOST_DEF 0xf0 982fd43cf6eSHans Rosenfeld /* set IWLAGN_BT_VALID_BOOST to "1" in "valid" bitmask for */ 983fd43cf6eSHans Rosenfeld uint8_t tx_prio_boost; 984fd43cf6eSHans Rosenfeld uint16_t rx_prio_boost; 985fd43cf6eSHans Rosenfeld } __packed; 986fd43cf6eSHans Rosenfeld 987fd43cf6eSHans Rosenfeld struct iwn_bt_adv2 { 988fd43cf6eSHans Rosenfeld struct iwn_bt_basic basic; 989fd43cf6eSHans Rosenfeld uint32_t prio_boost; 990fd43cf6eSHans Rosenfeld #define IWN_BT_PRIO_BOOST_DEF32 0xf0f0f0 991fd43cf6eSHans Rosenfeld uint8_t reserved; 992fd43cf6eSHans Rosenfeld /* set IWLAGN_BT_VALID_BOOST to "1" in "valid" bitmask for */ 993fd43cf6eSHans Rosenfeld uint8_t tx_prio_boost; 994fd43cf6eSHans Rosenfeld uint16_t rx_prio_boost; 995fd43cf6eSHans Rosenfeld } __packed; 996fd43cf6eSHans Rosenfeld 997fd43cf6eSHans Rosenfeld /* Structure for command IWN_CMD_BT_COEX_PRIOTABLE */ 998fd43cf6eSHans Rosenfeld struct iwn_btcoex_priotable { 999fd43cf6eSHans Rosenfeld uint8_t calib_init1; 1000fd43cf6eSHans Rosenfeld uint8_t calib_init2; 1001fd43cf6eSHans Rosenfeld uint8_t calib_periodic_low1; 1002fd43cf6eSHans Rosenfeld uint8_t calib_periodic_low2; 1003fd43cf6eSHans Rosenfeld uint8_t calib_periodic_high1; 1004fd43cf6eSHans Rosenfeld uint8_t calib_periodic_high2; 1005fd43cf6eSHans Rosenfeld uint8_t dtim; 1006fd43cf6eSHans Rosenfeld uint8_t scan52; 1007fd43cf6eSHans Rosenfeld uint8_t scan24; 1008fd43cf6eSHans Rosenfeld uint8_t reserved[7]; 1009fd43cf6eSHans Rosenfeld } __packed; 1010fd43cf6eSHans Rosenfeld 1011fd43cf6eSHans Rosenfeld /* Structure for command IWN_CMD_BT_COEX_PROT */ 1012fd43cf6eSHans Rosenfeld struct iwn_btcoex_prot { 1013fd43cf6eSHans Rosenfeld uint8_t open; 1014fd43cf6eSHans Rosenfeld uint8_t type; 1015fd43cf6eSHans Rosenfeld uint8_t reserved[2]; 1016fd43cf6eSHans Rosenfeld } __packed; 1017fd43cf6eSHans Rosenfeld 1018fd43cf6eSHans Rosenfeld /* Structure for command IWN_CMD_SET_CRITICAL_TEMP. */ 1019fd43cf6eSHans Rosenfeld struct iwn_critical_temp { 1020fd43cf6eSHans Rosenfeld uint32_t reserved; 1021fd43cf6eSHans Rosenfeld uint32_t tempM; 1022fd43cf6eSHans Rosenfeld uint32_t tempR; 1023fd43cf6eSHans Rosenfeld /* degK <-> degC conversion macros. */ 1024fd43cf6eSHans Rosenfeld #define IWN_CTOK(c) ((c) + 273) 1025fd43cf6eSHans Rosenfeld #define IWN_KTOC(k) ((k) - 273) 1026fd43cf6eSHans Rosenfeld #define IWN_CTOMUK(c) (((c) * 1000000) + 273150000) 1027fd43cf6eSHans Rosenfeld } __packed; 1028fd43cf6eSHans Rosenfeld 1029fd43cf6eSHans Rosenfeld /* Structures for command IWN_CMD_SET_SENSITIVITY. */ 1030fd43cf6eSHans Rosenfeld struct iwn_sensitivity_cmd { 1031fd43cf6eSHans Rosenfeld uint16_t which; 1032fd43cf6eSHans Rosenfeld #define IWN_SENSITIVITY_DEFAULTTBL 0 1033fd43cf6eSHans Rosenfeld #define IWN_SENSITIVITY_WORKTBL 1 1034fd43cf6eSHans Rosenfeld 1035fd43cf6eSHans Rosenfeld uint16_t energy_cck; 1036fd43cf6eSHans Rosenfeld uint16_t energy_ofdm; 1037fd43cf6eSHans Rosenfeld uint16_t corr_ofdm_x1; 1038fd43cf6eSHans Rosenfeld uint16_t corr_ofdm_mrc_x1; 1039fd43cf6eSHans Rosenfeld uint16_t corr_cck_mrc_x4; 1040fd43cf6eSHans Rosenfeld uint16_t corr_ofdm_x4; 1041fd43cf6eSHans Rosenfeld uint16_t corr_ofdm_mrc_x4; 1042fd43cf6eSHans Rosenfeld uint16_t corr_barker; 1043fd43cf6eSHans Rosenfeld uint16_t corr_barker_mrc; 1044fd43cf6eSHans Rosenfeld uint16_t corr_cck_x4; 1045fd43cf6eSHans Rosenfeld uint16_t energy_ofdm_th; 1046fd43cf6eSHans Rosenfeld } __packed; 1047fd43cf6eSHans Rosenfeld 1048fd43cf6eSHans Rosenfeld struct iwn_enhanced_sensitivity_cmd { 1049fd43cf6eSHans Rosenfeld uint16_t which; 1050fd43cf6eSHans Rosenfeld uint16_t energy_cck; 1051fd43cf6eSHans Rosenfeld uint16_t energy_ofdm; 1052fd43cf6eSHans Rosenfeld uint16_t corr_ofdm_x1; 1053fd43cf6eSHans Rosenfeld uint16_t corr_ofdm_mrc_x1; 1054fd43cf6eSHans Rosenfeld uint16_t corr_cck_mrc_x4; 1055fd43cf6eSHans Rosenfeld uint16_t corr_ofdm_x4; 1056fd43cf6eSHans Rosenfeld uint16_t corr_ofdm_mrc_x4; 1057fd43cf6eSHans Rosenfeld uint16_t corr_barker; 1058fd43cf6eSHans Rosenfeld uint16_t corr_barker_mrc; 1059fd43cf6eSHans Rosenfeld uint16_t corr_cck_x4; 1060fd43cf6eSHans Rosenfeld uint16_t energy_ofdm_th; 1061fd43cf6eSHans Rosenfeld /* "Enhanced" part. */ 1062fd43cf6eSHans Rosenfeld uint16_t ina_det_ofdm; 1063fd43cf6eSHans Rosenfeld uint16_t ina_det_cck; 1064fd43cf6eSHans Rosenfeld uint16_t corr_11_9_en; 1065fd43cf6eSHans Rosenfeld uint16_t ofdm_det_slope_mrc; 1066fd43cf6eSHans Rosenfeld uint16_t ofdm_det_icept_mrc; 1067fd43cf6eSHans Rosenfeld uint16_t ofdm_det_slope; 1068fd43cf6eSHans Rosenfeld uint16_t ofdm_det_icept; 1069fd43cf6eSHans Rosenfeld uint16_t cck_det_slope_mrc; 1070fd43cf6eSHans Rosenfeld uint16_t cck_det_icept_mrc; 1071fd43cf6eSHans Rosenfeld uint16_t cck_det_slope; 1072fd43cf6eSHans Rosenfeld uint16_t cck_det_icept; 1073fd43cf6eSHans Rosenfeld uint16_t reserved; 1074fd43cf6eSHans Rosenfeld } __packed; 1075fd43cf6eSHans Rosenfeld 1076fd43cf6eSHans Rosenfeld /* Structures for command IWN_CMD_PHY_CALIB. */ 1077fd43cf6eSHans Rosenfeld struct iwn_phy_calib { 1078fd43cf6eSHans Rosenfeld uint8_t code; 1079fd43cf6eSHans Rosenfeld #define IWN4965_PHY_CALIB_DIFF_GAIN 7 1080fd43cf6eSHans Rosenfeld #define IWN5000_PHY_CALIB_DC 8 1081fd43cf6eSHans Rosenfeld #define IWN5000_PHY_CALIB_LO 9 1082fd43cf6eSHans Rosenfeld #define IWN5000_PHY_CALIB_TX_IQ 11 1083fd43cf6eSHans Rosenfeld #define IWN5000_PHY_CALIB_CRYSTAL 15 1084fd43cf6eSHans Rosenfeld #define IWN5000_PHY_CALIB_BASE_BAND 16 1085fd43cf6eSHans Rosenfeld #define IWN5000_PHY_CALIB_TX_IQ_PERIODIC 17 1086fd43cf6eSHans Rosenfeld #define IWN5000_PHY_CALIB_RESET_NOISE_GAIN 18 1087fd43cf6eSHans Rosenfeld #define IWN5000_PHY_CALIB_NOISE_GAIN 19 1088fd43cf6eSHans Rosenfeld 1089fd43cf6eSHans Rosenfeld #define IWN6000_PHY_CALIB_TEMP_OFFSET 18 1090fd43cf6eSHans Rosenfeld #define IWN2000_PHY_CALIB_TEMP_OFFSET 18 1091fd43cf6eSHans Rosenfeld 1092fd43cf6eSHans Rosenfeld #define IWN5000_PHY_CALIB_MAX 253 1093fd43cf6eSHans Rosenfeld 1094fd43cf6eSHans Rosenfeld uint8_t group; 1095fd43cf6eSHans Rosenfeld uint8_t ngroups; 1096fd43cf6eSHans Rosenfeld uint8_t isvalid; 1097fd43cf6eSHans Rosenfeld } __packed; 1098fd43cf6eSHans Rosenfeld 1099fd43cf6eSHans Rosenfeld struct iwn5000_phy_calib_crystal { 1100fd43cf6eSHans Rosenfeld uint8_t code; 1101fd43cf6eSHans Rosenfeld uint8_t group; 1102fd43cf6eSHans Rosenfeld uint8_t ngroups; 1103fd43cf6eSHans Rosenfeld uint8_t isvalid; 1104fd43cf6eSHans Rosenfeld 1105fd43cf6eSHans Rosenfeld uint8_t cap_pin[2]; 1106fd43cf6eSHans Rosenfeld uint8_t reserved[2]; 1107fd43cf6eSHans Rosenfeld } __packed; 1108fd43cf6eSHans Rosenfeld 1109fd43cf6eSHans Rosenfeld struct iwn6000_phy_calib_temp_offset { 1110fd43cf6eSHans Rosenfeld uint8_t code; 1111fd43cf6eSHans Rosenfeld uint8_t group; 1112fd43cf6eSHans Rosenfeld uint8_t ngroups; 1113fd43cf6eSHans Rosenfeld uint8_t isvalid; 1114fd43cf6eSHans Rosenfeld int16_t offset; 1115fd43cf6eSHans Rosenfeld #define IWN_DEFAULT_TEMP_OFFSET 2700 1116fd43cf6eSHans Rosenfeld 1117fd43cf6eSHans Rosenfeld uint16_t reserved; 1118fd43cf6eSHans Rosenfeld } __packed; 1119fd43cf6eSHans Rosenfeld 1120fd43cf6eSHans Rosenfeld struct iwn2000_phy_calib_temp_offset { 1121fd43cf6eSHans Rosenfeld uint8_t code; 1122fd43cf6eSHans Rosenfeld uint8_t group; 1123fd43cf6eSHans Rosenfeld uint8_t ngroups; 1124fd43cf6eSHans Rosenfeld uint8_t isvalid; 1125fd43cf6eSHans Rosenfeld int16_t offset_high; 1126fd43cf6eSHans Rosenfeld int16_t offset_low; 1127fd43cf6eSHans Rosenfeld int16_t burnt_voltage_ref; 1128fd43cf6eSHans Rosenfeld int16_t reserved; 1129fd43cf6eSHans Rosenfeld } __packed; 1130fd43cf6eSHans Rosenfeld 1131fd43cf6eSHans Rosenfeld struct iwn_phy_calib_gain { 1132fd43cf6eSHans Rosenfeld uint8_t code; 1133fd43cf6eSHans Rosenfeld uint8_t group; 1134fd43cf6eSHans Rosenfeld uint8_t ngroups; 1135fd43cf6eSHans Rosenfeld uint8_t isvalid; 1136fd43cf6eSHans Rosenfeld 1137fd43cf6eSHans Rosenfeld int8_t gain[3]; 1138fd43cf6eSHans Rosenfeld uint8_t reserved; 1139fd43cf6eSHans Rosenfeld } __packed; 1140fd43cf6eSHans Rosenfeld 1141fd43cf6eSHans Rosenfeld /* Structure for command IWN_CMD_SPECTRUM_MEASUREMENT. */ 1142fd43cf6eSHans Rosenfeld struct iwn_spectrum_cmd { 1143fd43cf6eSHans Rosenfeld uint16_t len; 1144fd43cf6eSHans Rosenfeld uint8_t token; 1145fd43cf6eSHans Rosenfeld uint8_t id; 1146fd43cf6eSHans Rosenfeld uint8_t origin; 1147fd43cf6eSHans Rosenfeld uint8_t periodic; 1148fd43cf6eSHans Rosenfeld uint16_t timeout; 1149fd43cf6eSHans Rosenfeld uint32_t start; 1150fd43cf6eSHans Rosenfeld uint32_t reserved1; 1151fd43cf6eSHans Rosenfeld uint32_t flags; 1152fd43cf6eSHans Rosenfeld uint32_t filter; 1153fd43cf6eSHans Rosenfeld uint16_t nchan; 1154fd43cf6eSHans Rosenfeld uint16_t reserved2; 1155fd43cf6eSHans Rosenfeld struct { 1156fd43cf6eSHans Rosenfeld uint32_t duration; 1157fd43cf6eSHans Rosenfeld uint8_t chan; 1158fd43cf6eSHans Rosenfeld uint8_t type; 1159fd43cf6eSHans Rosenfeld #define IWN_MEASUREMENT_BASIC (1 << 0) 1160fd43cf6eSHans Rosenfeld #define IWN_MEASUREMENT_CCA (1 << 1) 1161fd43cf6eSHans Rosenfeld #define IWN_MEASUREMENT_RPI_HISTOGRAM (1 << 2) 1162fd43cf6eSHans Rosenfeld #define IWN_MEASUREMENT_NOISE_HISTOGRAM (1 << 3) 1163fd43cf6eSHans Rosenfeld #define IWN_MEASUREMENT_FRAME (1 << 4) 1164fd43cf6eSHans Rosenfeld #define IWN_MEASUREMENT_IDLE (1 << 7) 1165fd43cf6eSHans Rosenfeld 1166fd43cf6eSHans Rosenfeld uint16_t reserved; 1167fd43cf6eSHans Rosenfeld } __packed chan[10]; 1168fd43cf6eSHans Rosenfeld } __packed; 1169fd43cf6eSHans Rosenfeld 1170fd43cf6eSHans Rosenfeld /* Structure for IWN_UC_READY notification. */ 1171fd43cf6eSHans Rosenfeld #define IWN_NATTEN_GROUPS 5 1172fd43cf6eSHans Rosenfeld struct iwn_ucode_info { 1173fd43cf6eSHans Rosenfeld uint8_t minor; 1174fd43cf6eSHans Rosenfeld uint8_t major; 1175fd43cf6eSHans Rosenfeld uint16_t reserved1; 1176fd43cf6eSHans Rosenfeld uint8_t revision[8]; 1177fd43cf6eSHans Rosenfeld uint8_t type; 1178fd43cf6eSHans Rosenfeld uint8_t subtype; 1179fd43cf6eSHans Rosenfeld #define IWN_UCODE_RUNTIME 0 1180fd43cf6eSHans Rosenfeld #define IWN_UCODE_INIT 9 1181fd43cf6eSHans Rosenfeld 1182fd43cf6eSHans Rosenfeld uint16_t reserved2; 1183fd43cf6eSHans Rosenfeld uint32_t logptr; 1184fd43cf6eSHans Rosenfeld uint32_t errptr; 1185fd43cf6eSHans Rosenfeld uint32_t tstamp; 1186fd43cf6eSHans Rosenfeld uint32_t valid; 1187fd43cf6eSHans Rosenfeld 1188fd43cf6eSHans Rosenfeld /* The following fields are for UCODE_INIT only. */ 1189fd43cf6eSHans Rosenfeld int32_t volt; 1190fd43cf6eSHans Rosenfeld struct { 1191fd43cf6eSHans Rosenfeld int32_t chan20MHz; 1192fd43cf6eSHans Rosenfeld int32_t chan40MHz; 1193fd43cf6eSHans Rosenfeld } __packed temp[4]; 1194fd43cf6eSHans Rosenfeld int32_t atten[IWN_NATTEN_GROUPS][2]; 1195fd43cf6eSHans Rosenfeld } __packed; 1196fd43cf6eSHans Rosenfeld 1197fd43cf6eSHans Rosenfeld /* Structures for IWN_TX_DONE notification. */ 1198fd43cf6eSHans Rosenfeld struct iwn4965_tx_stat { 1199fd43cf6eSHans Rosenfeld uint8_t nframes; 1200fd43cf6eSHans Rosenfeld uint8_t btkillcnt; 1201fd43cf6eSHans Rosenfeld uint8_t rtsfailcnt; 1202fd43cf6eSHans Rosenfeld uint8_t ackfailcnt; 1203fd43cf6eSHans Rosenfeld uint8_t rate; 1204fd43cf6eSHans Rosenfeld uint8_t rflags; 1205fd43cf6eSHans Rosenfeld uint16_t xrflags; 1206fd43cf6eSHans Rosenfeld uint16_t duration; 1207fd43cf6eSHans Rosenfeld uint16_t reserved; 1208fd43cf6eSHans Rosenfeld uint32_t power[2]; 1209fd43cf6eSHans Rosenfeld uint32_t status; 1210fd43cf6eSHans Rosenfeld } __packed; 1211fd43cf6eSHans Rosenfeld 1212fd43cf6eSHans Rosenfeld struct iwn5000_tx_stat { 1213fd43cf6eSHans Rosenfeld uint8_t nframes; 1214fd43cf6eSHans Rosenfeld uint8_t btkillcnt; 1215fd43cf6eSHans Rosenfeld uint8_t rtsfailcnt; 1216fd43cf6eSHans Rosenfeld uint8_t ackfailcnt; 1217fd43cf6eSHans Rosenfeld uint8_t rate; 1218fd43cf6eSHans Rosenfeld uint8_t rflags; 1219fd43cf6eSHans Rosenfeld uint16_t xrflags; 1220fd43cf6eSHans Rosenfeld uint16_t duration; 1221fd43cf6eSHans Rosenfeld uint16_t reserved; 1222fd43cf6eSHans Rosenfeld uint32_t power[2]; 1223fd43cf6eSHans Rosenfeld uint32_t info; 1224fd43cf6eSHans Rosenfeld uint16_t seq; 1225fd43cf6eSHans Rosenfeld uint16_t len; 1226fd43cf6eSHans Rosenfeld uint8_t tlc; 1227fd43cf6eSHans Rosenfeld uint8_t ratid; 1228fd43cf6eSHans Rosenfeld uint8_t fc[2]; 1229fd43cf6eSHans Rosenfeld uint16_t status; 1230fd43cf6eSHans Rosenfeld uint16_t sequence; 1231fd43cf6eSHans Rosenfeld } __packed; 1232fd43cf6eSHans Rosenfeld 1233fd43cf6eSHans Rosenfeld /* Structure for IWN_BEACON_MISSED notification. */ 1234fd43cf6eSHans Rosenfeld struct iwn_beacon_missed { 1235fd43cf6eSHans Rosenfeld uint32_t consecutive; 1236fd43cf6eSHans Rosenfeld uint32_t total; 1237fd43cf6eSHans Rosenfeld uint32_t expected; 1238fd43cf6eSHans Rosenfeld uint32_t received; 1239fd43cf6eSHans Rosenfeld } __packed; 1240fd43cf6eSHans Rosenfeld 1241fd43cf6eSHans Rosenfeld /* Structure for IWN_MPDU_RX_DONE notification. */ 1242fd43cf6eSHans Rosenfeld struct iwn_rx_mpdu { 1243fd43cf6eSHans Rosenfeld uint16_t len; 1244fd43cf6eSHans Rosenfeld uint16_t reserved; 1245fd43cf6eSHans Rosenfeld } __packed; 1246fd43cf6eSHans Rosenfeld 1247fd43cf6eSHans Rosenfeld /* Structures for IWN_RX_DONE and IWN_MPDU_RX_DONE notifications. */ 1248fd43cf6eSHans Rosenfeld struct iwn4965_rx_phystat { 1249fd43cf6eSHans Rosenfeld uint16_t antenna; 1250fd43cf6eSHans Rosenfeld uint16_t agc; 1251fd43cf6eSHans Rosenfeld uint8_t rssi[6]; 1252fd43cf6eSHans Rosenfeld } __packed; 1253fd43cf6eSHans Rosenfeld 1254fd43cf6eSHans Rosenfeld struct iwn5000_rx_phystat { 1255fd43cf6eSHans Rosenfeld uint32_t reserved1; 1256fd43cf6eSHans Rosenfeld uint32_t agc; 1257fd43cf6eSHans Rosenfeld uint16_t rssi[3]; 1258fd43cf6eSHans Rosenfeld } __packed; 1259fd43cf6eSHans Rosenfeld 1260fd43cf6eSHans Rosenfeld struct iwn_rx_stat { 1261fd43cf6eSHans Rosenfeld uint8_t phy_len; 1262fd43cf6eSHans Rosenfeld uint8_t cfg_phy_len; 1263fd43cf6eSHans Rosenfeld #define IWN_STAT_MAXLEN 20 1264fd43cf6eSHans Rosenfeld 1265fd43cf6eSHans Rosenfeld uint8_t id; 1266fd43cf6eSHans Rosenfeld uint8_t reserved1; 1267fd43cf6eSHans Rosenfeld uint64_t tstamp; 1268fd43cf6eSHans Rosenfeld uint32_t beacon; 1269fd43cf6eSHans Rosenfeld uint16_t flags; 1270fd43cf6eSHans Rosenfeld #define IWN_STAT_FLAG_SHPREAMBLE (1 << 2) 1271fd43cf6eSHans Rosenfeld 1272fd43cf6eSHans Rosenfeld uint16_t chan; 1273fd43cf6eSHans Rosenfeld uint8_t phybuf[32]; 1274fd43cf6eSHans Rosenfeld uint8_t rate; 1275fd43cf6eSHans Rosenfeld uint8_t rflags; 1276fd43cf6eSHans Rosenfeld uint16_t xrflags; 1277fd43cf6eSHans Rosenfeld uint16_t len; 1278fd43cf6eSHans Rosenfeld uint16_t reserve3; 1279fd43cf6eSHans Rosenfeld } __packed; 1280fd43cf6eSHans Rosenfeld 1281fd43cf6eSHans Rosenfeld #define IWN_RSSI_TO_DBM 44 1282fd43cf6eSHans Rosenfeld 1283fd43cf6eSHans Rosenfeld /* Structure for IWN_RX_COMPRESSED_BA notification. */ 1284fd43cf6eSHans Rosenfeld struct iwn_compressed_ba { 1285fd43cf6eSHans Rosenfeld uint8_t macaddr[IEEE80211_ADDR_LEN]; 1286fd43cf6eSHans Rosenfeld uint16_t reserved; 1287fd43cf6eSHans Rosenfeld uint8_t id; 1288fd43cf6eSHans Rosenfeld uint8_t tid; 1289fd43cf6eSHans Rosenfeld uint16_t seq; 1290fd43cf6eSHans Rosenfeld uint64_t bitmap; 1291fd43cf6eSHans Rosenfeld uint16_t qid; 1292fd43cf6eSHans Rosenfeld uint16_t ssn; 1293fd43cf6eSHans Rosenfeld } __packed; 1294fd43cf6eSHans Rosenfeld 1295fd43cf6eSHans Rosenfeld /* Structure for IWN_START_SCAN notification. */ 1296fd43cf6eSHans Rosenfeld struct iwn_start_scan { 1297fd43cf6eSHans Rosenfeld uint64_t tstamp; 1298fd43cf6eSHans Rosenfeld uint32_t tbeacon; 1299fd43cf6eSHans Rosenfeld uint8_t chan; 1300fd43cf6eSHans Rosenfeld uint8_t band; 1301fd43cf6eSHans Rosenfeld uint16_t reserved; 1302fd43cf6eSHans Rosenfeld uint32_t status; 1303fd43cf6eSHans Rosenfeld } __packed; 1304fd43cf6eSHans Rosenfeld 1305fd43cf6eSHans Rosenfeld /* Structure for IWN_STOP_SCAN notification. */ 1306fd43cf6eSHans Rosenfeld struct iwn_stop_scan { 1307fd43cf6eSHans Rosenfeld uint8_t nchan; 1308fd43cf6eSHans Rosenfeld uint8_t status; 1309fd43cf6eSHans Rosenfeld uint8_t reserved; 1310fd43cf6eSHans Rosenfeld uint8_t chan; 1311fd43cf6eSHans Rosenfeld uint64_t tsf; 1312fd43cf6eSHans Rosenfeld } __packed; 1313fd43cf6eSHans Rosenfeld 1314fd43cf6eSHans Rosenfeld /* Structure for IWN_SPECTRUM_MEASUREMENT notification. */ 1315fd43cf6eSHans Rosenfeld struct iwn_spectrum_notif { 1316fd43cf6eSHans Rosenfeld uint8_t id; 1317fd43cf6eSHans Rosenfeld uint8_t token; 1318fd43cf6eSHans Rosenfeld uint8_t idx; 1319fd43cf6eSHans Rosenfeld uint8_t state; 1320fd43cf6eSHans Rosenfeld #define IWN_MEASUREMENT_START 0 1321fd43cf6eSHans Rosenfeld #define IWN_MEASUREMENT_STOP 1 1322fd43cf6eSHans Rosenfeld 1323fd43cf6eSHans Rosenfeld uint32_t start; 1324fd43cf6eSHans Rosenfeld uint8_t band; 1325fd43cf6eSHans Rosenfeld uint8_t chan; 1326fd43cf6eSHans Rosenfeld uint8_t type; 1327fd43cf6eSHans Rosenfeld uint8_t reserved1; 1328fd43cf6eSHans Rosenfeld uint32_t cca_ofdm; 1329fd43cf6eSHans Rosenfeld uint32_t cca_cck; 1330fd43cf6eSHans Rosenfeld uint32_t cca_time; 1331fd43cf6eSHans Rosenfeld uint8_t basic; 1332fd43cf6eSHans Rosenfeld uint8_t reserved2[3]; 1333fd43cf6eSHans Rosenfeld uint32_t ofdm[8]; 1334fd43cf6eSHans Rosenfeld uint32_t cck[8]; 1335fd43cf6eSHans Rosenfeld uint32_t stop; 1336fd43cf6eSHans Rosenfeld uint32_t status; 1337fd43cf6eSHans Rosenfeld #define IWN_MEASUREMENT_OK 0 1338fd43cf6eSHans Rosenfeld #define IWN_MEASUREMENT_CONCURRENT 1 1339fd43cf6eSHans Rosenfeld #define IWN_MEASUREMENT_CSA_CONFLICT 2 1340fd43cf6eSHans Rosenfeld #define IWN_MEASUREMENT_TGH_CONFLICT 3 1341fd43cf6eSHans Rosenfeld #define IWN_MEASUREMENT_STOPPED 6 1342fd43cf6eSHans Rosenfeld #define IWN_MEASUREMENT_TIMEOUT 7 1343fd43cf6eSHans Rosenfeld #define IWN_MEASUREMENT_FAILED 8 1344fd43cf6eSHans Rosenfeld } __packed; 1345fd43cf6eSHans Rosenfeld 1346fd43cf6eSHans Rosenfeld /* Structures for IWN_{RX,BEACON}_STATISTICS notification. */ 1347fd43cf6eSHans Rosenfeld struct iwn_rx_phy_stats { 1348fd43cf6eSHans Rosenfeld uint32_t ina; 1349fd43cf6eSHans Rosenfeld uint32_t fina; 1350fd43cf6eSHans Rosenfeld uint32_t bad_plcp; 1351fd43cf6eSHans Rosenfeld uint32_t bad_crc32; 1352fd43cf6eSHans Rosenfeld uint32_t overrun; 1353fd43cf6eSHans Rosenfeld uint32_t eoverrun; 1354fd43cf6eSHans Rosenfeld uint32_t good_crc32; 1355fd43cf6eSHans Rosenfeld uint32_t fa; 1356fd43cf6eSHans Rosenfeld uint32_t bad_fina_sync; 1357fd43cf6eSHans Rosenfeld uint32_t sfd_timeout; 1358fd43cf6eSHans Rosenfeld uint32_t fina_timeout; 1359fd43cf6eSHans Rosenfeld uint32_t no_rts_ack; 1360fd43cf6eSHans Rosenfeld uint32_t rxe_limit; 1361fd43cf6eSHans Rosenfeld uint32_t ack; 1362fd43cf6eSHans Rosenfeld uint32_t cts; 1363fd43cf6eSHans Rosenfeld uint32_t ba_resp; 1364fd43cf6eSHans Rosenfeld uint32_t dsp_kill; 1365fd43cf6eSHans Rosenfeld uint32_t bad_mh; 1366fd43cf6eSHans Rosenfeld uint32_t rssi_sum; 1367fd43cf6eSHans Rosenfeld uint32_t reserved; 1368fd43cf6eSHans Rosenfeld } __packed; 1369fd43cf6eSHans Rosenfeld 1370fd43cf6eSHans Rosenfeld struct iwn_rx_general_stats { 1371fd43cf6eSHans Rosenfeld uint32_t bad_cts; 1372fd43cf6eSHans Rosenfeld uint32_t bad_ack; 1373fd43cf6eSHans Rosenfeld uint32_t not_bss; 1374fd43cf6eSHans Rosenfeld uint32_t filtered; 1375fd43cf6eSHans Rosenfeld uint32_t bad_chan; 1376fd43cf6eSHans Rosenfeld uint32_t beacons; 1377fd43cf6eSHans Rosenfeld uint32_t missed_beacons; 1378fd43cf6eSHans Rosenfeld uint32_t adc_saturated; /* time in 0.8us */ 1379fd43cf6eSHans Rosenfeld uint32_t ina_searched; /* time in 0.8us */ 1380fd43cf6eSHans Rosenfeld int32_t noise[3]; 1381fd43cf6eSHans Rosenfeld uint32_t flags; 1382fd43cf6eSHans Rosenfeld uint32_t load; 1383fd43cf6eSHans Rosenfeld uint32_t fa; 1384fd43cf6eSHans Rosenfeld uint32_t rssi[3]; 1385fd43cf6eSHans Rosenfeld uint32_t energy[3]; 1386fd43cf6eSHans Rosenfeld } __packed; 1387fd43cf6eSHans Rosenfeld 1388fd43cf6eSHans Rosenfeld struct iwn_rx_ht_phy_stats { 1389fd43cf6eSHans Rosenfeld uint32_t bad_plcp; 1390fd43cf6eSHans Rosenfeld uint32_t overrun; 1391fd43cf6eSHans Rosenfeld uint32_t eoverrun; 1392fd43cf6eSHans Rosenfeld uint32_t good_crc32; 1393fd43cf6eSHans Rosenfeld uint32_t bad_crc32; 1394fd43cf6eSHans Rosenfeld uint32_t bad_mh; 1395fd43cf6eSHans Rosenfeld uint32_t good_ampdu_crc32; 1396fd43cf6eSHans Rosenfeld uint32_t ampdu; 1397fd43cf6eSHans Rosenfeld uint32_t fragment; 1398fd43cf6eSHans Rosenfeld uint32_t reserved; 1399fd43cf6eSHans Rosenfeld } __packed; 1400fd43cf6eSHans Rosenfeld 1401fd43cf6eSHans Rosenfeld struct iwn_rx_stats { 1402fd43cf6eSHans Rosenfeld struct iwn_rx_phy_stats ofdm; 1403fd43cf6eSHans Rosenfeld struct iwn_rx_phy_stats cck; 1404fd43cf6eSHans Rosenfeld struct iwn_rx_general_stats general; 1405fd43cf6eSHans Rosenfeld struct iwn_rx_ht_phy_stats ht; 1406fd43cf6eSHans Rosenfeld } __packed; 1407fd43cf6eSHans Rosenfeld 1408fd43cf6eSHans Rosenfeld struct iwn_tx_stats { 1409fd43cf6eSHans Rosenfeld uint32_t preamble; 1410fd43cf6eSHans Rosenfeld uint32_t rx_detected; 1411fd43cf6eSHans Rosenfeld uint32_t bt_defer; 1412fd43cf6eSHans Rosenfeld uint32_t bt_kill; 1413fd43cf6eSHans Rosenfeld uint32_t short_len; 1414fd43cf6eSHans Rosenfeld uint32_t cts_timeout; 1415fd43cf6eSHans Rosenfeld uint32_t ack_timeout; 1416fd43cf6eSHans Rosenfeld uint32_t exp_ack; 1417fd43cf6eSHans Rosenfeld uint32_t ack; 1418fd43cf6eSHans Rosenfeld uint32_t msdu; 1419fd43cf6eSHans Rosenfeld uint32_t busrt_err1; 1420fd43cf6eSHans Rosenfeld uint32_t burst_err2; 1421fd43cf6eSHans Rosenfeld uint32_t cts_collision; 1422fd43cf6eSHans Rosenfeld uint32_t ack_collision; 1423fd43cf6eSHans Rosenfeld uint32_t ba_timeout; 1424fd43cf6eSHans Rosenfeld uint32_t ba_resched; 1425fd43cf6eSHans Rosenfeld uint32_t query_ampdu; 1426fd43cf6eSHans Rosenfeld uint32_t query; 1427fd43cf6eSHans Rosenfeld uint32_t query_ampdu_frag; 1428fd43cf6eSHans Rosenfeld uint32_t query_mismatch; 1429fd43cf6eSHans Rosenfeld uint32_t not_ready; 1430fd43cf6eSHans Rosenfeld uint32_t underrun; 1431fd43cf6eSHans Rosenfeld uint32_t bt_ht_kill; 1432fd43cf6eSHans Rosenfeld uint32_t rx_ba_resp; 1433fd43cf6eSHans Rosenfeld uint32_t reserved[2]; 1434fd43cf6eSHans Rosenfeld } __packed; 1435fd43cf6eSHans Rosenfeld 1436fd43cf6eSHans Rosenfeld struct iwn_general_stats { 1437fd43cf6eSHans Rosenfeld uint32_t temp; 1438fd43cf6eSHans Rosenfeld uint32_t temp_m; 1439fd43cf6eSHans Rosenfeld uint32_t burst_check; 1440fd43cf6eSHans Rosenfeld uint32_t burst; 1441fd43cf6eSHans Rosenfeld uint32_t reserved1[4]; 1442fd43cf6eSHans Rosenfeld uint32_t sleep; 1443fd43cf6eSHans Rosenfeld uint32_t slot_out; 1444fd43cf6eSHans Rosenfeld uint32_t slot_idle; 1445fd43cf6eSHans Rosenfeld uint32_t ttl_tstamp; 1446fd43cf6eSHans Rosenfeld uint32_t tx_ant_a; 1447fd43cf6eSHans Rosenfeld uint32_t tx_ant_b; 1448fd43cf6eSHans Rosenfeld uint32_t exec; 1449fd43cf6eSHans Rosenfeld uint32_t probe; 1450fd43cf6eSHans Rosenfeld uint32_t reserved2[2]; 1451fd43cf6eSHans Rosenfeld uint32_t rx_enabled; 1452fd43cf6eSHans Rosenfeld uint32_t reserved3[3]; 1453fd43cf6eSHans Rosenfeld } __packed; 1454fd43cf6eSHans Rosenfeld 1455fd43cf6eSHans Rosenfeld struct iwn_stats { 1456fd43cf6eSHans Rosenfeld uint32_t flags; 1457fd43cf6eSHans Rosenfeld struct iwn_rx_stats rx; 1458fd43cf6eSHans Rosenfeld struct iwn_tx_stats tx; 1459fd43cf6eSHans Rosenfeld struct iwn_general_stats general; 1460fd43cf6eSHans Rosenfeld } __packed; 1461fd43cf6eSHans Rosenfeld 1462fd43cf6eSHans Rosenfeld 1463fd43cf6eSHans Rosenfeld /* Firmware error dump. */ 1464fd43cf6eSHans Rosenfeld struct iwn_fw_dump { 1465fd43cf6eSHans Rosenfeld uint32_t valid; 1466fd43cf6eSHans Rosenfeld uint32_t id; 1467fd43cf6eSHans Rosenfeld uint32_t pc; 1468fd43cf6eSHans Rosenfeld uint32_t branch_link[2]; 1469fd43cf6eSHans Rosenfeld uint32_t interrupt_link[2]; 1470fd43cf6eSHans Rosenfeld uint32_t error_data[2]; 1471fd43cf6eSHans Rosenfeld uint32_t src_line; 1472fd43cf6eSHans Rosenfeld uint32_t tsf; 1473fd43cf6eSHans Rosenfeld uint32_t time[2]; 1474fd43cf6eSHans Rosenfeld } __packed; 1475fd43cf6eSHans Rosenfeld 1476fd43cf6eSHans Rosenfeld /* TLV firmware header. */ 1477fd43cf6eSHans Rosenfeld struct iwn_fw_tlv_hdr { 1478fd43cf6eSHans Rosenfeld uint32_t zero; /* Always 0, to differentiate from legacy. */ 1479fd43cf6eSHans Rosenfeld uint32_t signature; 1480fd43cf6eSHans Rosenfeld #define IWN_FW_SIGNATURE 0x0a4c5749 /* "IWL\n" */ 1481fd43cf6eSHans Rosenfeld 1482fd43cf6eSHans Rosenfeld uint8_t descr[64]; 1483fd43cf6eSHans Rosenfeld uint32_t rev; 1484fd43cf6eSHans Rosenfeld #define IWN_FW_API(x) (((x) >> 8) & 0xff) 1485fd43cf6eSHans Rosenfeld 1486fd43cf6eSHans Rosenfeld uint32_t build; 1487fd43cf6eSHans Rosenfeld uint64_t altmask; 1488fd43cf6eSHans Rosenfeld } __packed; 1489fd43cf6eSHans Rosenfeld 1490fd43cf6eSHans Rosenfeld /* TLV header. */ 1491fd43cf6eSHans Rosenfeld struct iwn_fw_tlv { 1492fd43cf6eSHans Rosenfeld uint16_t type; 1493fd43cf6eSHans Rosenfeld #define IWN_FW_TLV_MAIN_TEXT 1 1494fd43cf6eSHans Rosenfeld #define IWN_FW_TLV_MAIN_DATA 2 1495fd43cf6eSHans Rosenfeld #define IWN_FW_TLV_INIT_TEXT 3 1496fd43cf6eSHans Rosenfeld #define IWN_FW_TLV_INIT_DATA 4 1497fd43cf6eSHans Rosenfeld #define IWN_FW_TLV_BOOT_TEXT 5 1498fd43cf6eSHans Rosenfeld #define IWN_FW_TLV_PBREQ_MAXLEN 6 1499fd43cf6eSHans Rosenfeld #define IWN_FW_TLV_ENH_SENS 14 1500fd43cf6eSHans Rosenfeld #define IWN_FW_TLV_PHY_CALIB 15 1501fd43cf6eSHans Rosenfeld #define IWN_FW_TLV_FLAGS 18 1502fd43cf6eSHans Rosenfeld 1503fd43cf6eSHans Rosenfeld uint16_t alt; 1504fd43cf6eSHans Rosenfeld uint32_t len; 1505fd43cf6eSHans Rosenfeld } __packed; 1506fd43cf6eSHans Rosenfeld 1507fd43cf6eSHans Rosenfeld #define IWN4965_FW_TEXT_MAXSZ ( 96 * 1024) 1508fd43cf6eSHans Rosenfeld #define IWN4965_FW_DATA_MAXSZ ( 40 * 1024) 1509fd43cf6eSHans Rosenfeld #define IWN5000_FW_TEXT_MAXSZ (256 * 1024) 1510fd43cf6eSHans Rosenfeld #define IWN5000_FW_DATA_MAXSZ ( 80 * 1024) 1511fd43cf6eSHans Rosenfeld #define IWN_FW_BOOT_TEXT_MAXSZ 1024 1512fd43cf6eSHans Rosenfeld #define IWN4965_FWSZ (IWN4965_FW_TEXT_MAXSZ + IWN4965_FW_DATA_MAXSZ) 1513fd43cf6eSHans Rosenfeld #define IWN5000_FWSZ IWN5000_FW_TEXT_MAXSZ 1514fd43cf6eSHans Rosenfeld 1515fd43cf6eSHans Rosenfeld /** 1516fd43cf6eSHans Rosenfeld * enum iwn_ucode_tlv_flag - ucode API flags 1517fd43cf6eSHans Rosenfeld * @IWN_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously 1518fd43cf6eSHans Rosenfeld * was a separate TLV but moved here to save space. 1519fd43cf6eSHans Rosenfeld * @IWN_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID, 1520fd43cf6eSHans Rosenfeld * treats good CRC threshold as a boolean 1521fd43cf6eSHans Rosenfeld * @IWN_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). 1522fd43cf6eSHans Rosenfeld * @IWN_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P. 1523fd43cf6eSHans Rosenfeld * @IWN_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS 1524fd43cf6eSHans Rosenfeld * @IWN_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD 1525fd43cf6eSHans Rosenfeld * @IWN_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan 1526fd43cf6eSHans Rosenfeld * offload profile config command. 1527fd43cf6eSHans Rosenfeld * @IWN_UCODE_TLV_FLAGS_RX_ENERGY_API: supports rx signal strength api 1528fd43cf6eSHans Rosenfeld * @IWN_UCODE_TLV_FLAGS_TIME_EVENT_API_V2: using the new time event API. 1529fd43cf6eSHans Rosenfeld * @IWN_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six 1530fd43cf6eSHans Rosenfeld * (rather than two) IPv6 addresses 1531fd43cf6eSHans Rosenfeld * @IWN_UCODE_TLV_FLAGS_BF_UPDATED: new beacon filtering API 1532fd43cf6eSHans Rosenfeld * @IWN_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element 1533fd43cf6eSHans Rosenfeld * from the probe request template. 1534fd43cf6eSHans Rosenfeld * @IWN_UCODE_TLV_FLAGS_D3_CONTINUITY_API: modified D3 API to allow keeping 1535fd43cf6eSHans Rosenfeld * connection when going back to D0 1536fd43cf6eSHans Rosenfeld * @IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version) 1537fd43cf6eSHans Rosenfeld * @IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version) 1538fd43cf6eSHans Rosenfeld * @IWN_UCODE_TLV_FLAGS_SCHED_SCAN: this uCode image supports scheduled scan. 1539fd43cf6eSHans Rosenfeld * @IWN_UCODE_TLV_FLAGS_STA_KEY_CMD: new ADD_STA and ADD_STA_KEY command API 1540fd43cf6eSHans Rosenfeld * @IWN_UCODE_TLV_FLAGS_DEVICE_PS_CMD: support device wide power command 1541fd43cf6eSHans Rosenfeld * containing CAM (Continuous Active Mode) indication. 1542fd43cf6eSHans Rosenfeld */ 1543fd43cf6eSHans Rosenfeld enum iwn_ucode_tlv_flag { 1544fd43cf6eSHans Rosenfeld IWN_UCODE_TLV_FLAGS_PAN = (1 << 0), 1545fd43cf6eSHans Rosenfeld IWN_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1), 1546fd43cf6eSHans Rosenfeld IWN_UCODE_TLV_FLAGS_MFP = (1 << 2), 1547fd43cf6eSHans Rosenfeld IWN_UCODE_TLV_FLAGS_P2P = (1 << 3), 1548fd43cf6eSHans Rosenfeld IWN_UCODE_TLV_FLAGS_DW_BC_TABLE = (1 << 4), 1549fd43cf6eSHans Rosenfeld IWN_UCODE_TLV_FLAGS_NEWBT_COEX = (1 << 5), 1550fd43cf6eSHans Rosenfeld IWN_UCODE_TLV_FLAGS_UAPSD = (1 << 6), 1551fd43cf6eSHans Rosenfeld IWN_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7), 1552fd43cf6eSHans Rosenfeld IWN_UCODE_TLV_FLAGS_RX_ENERGY_API = (1 << 8), 1553fd43cf6eSHans Rosenfeld IWN_UCODE_TLV_FLAGS_TIME_EVENT_API_V2 = (1 << 9), 1554fd43cf6eSHans Rosenfeld IWN_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10), 1555fd43cf6eSHans Rosenfeld IWN_UCODE_TLV_FLAGS_BF_UPDATED = (1 << 11), 1556fd43cf6eSHans Rosenfeld IWN_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12), 1557fd43cf6eSHans Rosenfeld IWN_UCODE_TLV_FLAGS_D3_CONTINUITY_API = (1 << 14), 1558fd43cf6eSHans Rosenfeld IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15), 1559fd43cf6eSHans Rosenfeld IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16), 1560fd43cf6eSHans Rosenfeld IWN_UCODE_TLV_FLAGS_SCHED_SCAN = (1 << 17), 1561fd43cf6eSHans Rosenfeld IWN_UCODE_TLV_FLAGS_STA_KEY_CMD = (1 << 19), 1562fd43cf6eSHans Rosenfeld IWN_UCODE_TLV_FLAGS_DEVICE_PS_CMD = (1 << 20), 1563fd43cf6eSHans Rosenfeld }; 1564fd43cf6eSHans Rosenfeld 1565fd43cf6eSHans Rosenfeld /* 1566fd43cf6eSHans Rosenfeld * Offsets into EEPROM. 1567fd43cf6eSHans Rosenfeld */ 1568fd43cf6eSHans Rosenfeld #define IWN_EEPROM_MAC 0x015 1569fd43cf6eSHans Rosenfeld #define IWN_EEPROM_SKU_CAP 0x045 1570fd43cf6eSHans Rosenfeld #define IWN_EEPROM_RFCFG 0x048 1571fd43cf6eSHans Rosenfeld #define IWN4965_EEPROM_DOMAIN 0x060 1572fd43cf6eSHans Rosenfeld #define IWN4965_EEPROM_BAND1 0x063 1573fd43cf6eSHans Rosenfeld #define IWN5000_EEPROM_REG 0x066 1574fd43cf6eSHans Rosenfeld #define IWN5000_EEPROM_CAL 0x067 1575fd43cf6eSHans Rosenfeld #define IWN4965_EEPROM_BAND2 0x072 1576fd43cf6eSHans Rosenfeld #define IWN4965_EEPROM_BAND3 0x080 1577fd43cf6eSHans Rosenfeld #define IWN4965_EEPROM_BAND4 0x08d 1578fd43cf6eSHans Rosenfeld #define IWN4965_EEPROM_BAND5 0x099 1579fd43cf6eSHans Rosenfeld #define IWN4965_EEPROM_BAND6 0x0a0 1580fd43cf6eSHans Rosenfeld #define IWN4965_EEPROM_BAND7 0x0a8 1581fd43cf6eSHans Rosenfeld #define IWN4965_EEPROM_MAXPOW 0x0e8 1582fd43cf6eSHans Rosenfeld #define IWN4965_EEPROM_VOLTAGE 0x0e9 1583fd43cf6eSHans Rosenfeld #define IWN4965_EEPROM_BANDS 0x0ea 1584fd43cf6eSHans Rosenfeld /* Indirect offsets. */ 1585fd43cf6eSHans Rosenfeld #define IWN5000_EEPROM_DOMAIN 0x001 1586fd43cf6eSHans Rosenfeld #define IWN5000_EEPROM_BAND1 0x004 1587fd43cf6eSHans Rosenfeld #define IWN5000_EEPROM_BAND2 0x013 1588fd43cf6eSHans Rosenfeld #define IWN5000_EEPROM_BAND3 0x021 1589fd43cf6eSHans Rosenfeld #define IWN5000_EEPROM_BAND4 0x02e 1590fd43cf6eSHans Rosenfeld #define IWN5000_EEPROM_BAND5 0x03a 1591fd43cf6eSHans Rosenfeld #define IWN5000_EEPROM_BAND6 0x041 1592fd43cf6eSHans Rosenfeld #define IWN5000_EEPROM_BAND7 0x049 1593fd43cf6eSHans Rosenfeld #define IWN6000_EEPROM_ENHINFO 0x054 1594fd43cf6eSHans Rosenfeld #define IWN5000_EEPROM_CRYSTAL 0x128 1595fd43cf6eSHans Rosenfeld #define IWN5000_EEPROM_TEMP 0x12a 1596fd43cf6eSHans Rosenfeld #define IWN5000_EEPROM_VOLT 0x12b 1597fd43cf6eSHans Rosenfeld #define IWN2000_EEPROM_RAWTEMP 0x12b 1598fd43cf6eSHans Rosenfeld 1599fd43cf6eSHans Rosenfeld /* Possible flags for IWN_EEPROM_SKU_CAP. */ 1600fd43cf6eSHans Rosenfeld #define IWN_EEPROM_SKU_CAP_11N (1 << 6) 1601fd43cf6eSHans Rosenfeld #define IWN_EEPROM_SKU_CAP_AMT (1 << 7) 1602fd43cf6eSHans Rosenfeld #define IWN_EEPROM_SKU_CAP_IPAN (1 << 8) 1603fd43cf6eSHans Rosenfeld 1604fd43cf6eSHans Rosenfeld /* Possible flags for IWN_EEPROM_RFCFG. */ 1605fd43cf6eSHans Rosenfeld #define IWN_RFCFG_TYPE(x) (((x) >> 0) & 0x3) 1606fd43cf6eSHans Rosenfeld #define IWN_RFCFG_STEP(x) (((x) >> 2) & 0x3) 1607fd43cf6eSHans Rosenfeld #define IWN_RFCFG_DASH(x) (((x) >> 4) & 0x3) 1608fd43cf6eSHans Rosenfeld #define IWN_RFCFG_TXANTMSK(x) (((x) >> 8) & 0xf) 1609fd43cf6eSHans Rosenfeld #define IWN_RFCFG_RXANTMSK(x) (((x) >> 12) & 0xf) 1610fd43cf6eSHans Rosenfeld 1611fd43cf6eSHans Rosenfeld struct iwn_eeprom_chan { 1612fd43cf6eSHans Rosenfeld uint8_t flags; 1613fd43cf6eSHans Rosenfeld #define IWN_EEPROM_CHAN_VALID (1 << 0) 1614fd43cf6eSHans Rosenfeld #define IWN_EEPROM_CHAN_IBSS (1 << 1) 1615fd43cf6eSHans Rosenfeld #define IWN_EEPROM_CHAN_ACTIVE (1 << 3) 1616fd43cf6eSHans Rosenfeld #define IWN_EEPROM_CHAN_RADAR (1 << 4) 1617fd43cf6eSHans Rosenfeld #define IWN_EEPROM_CHAN_WIDE (1 << 5) 1618fd43cf6eSHans Rosenfeld #define IWN_EEPROM_CHAN_DFS (1 << 7) 1619fd43cf6eSHans Rosenfeld 1620fd43cf6eSHans Rosenfeld int8_t maxpwr; 1621fd43cf6eSHans Rosenfeld } __packed; 1622fd43cf6eSHans Rosenfeld 1623fd43cf6eSHans Rosenfeld struct iwn_eeprom_enhinfo { 1624fd43cf6eSHans Rosenfeld uint16_t chan; 1625fd43cf6eSHans Rosenfeld int8_t chain[3]; /* max power in half-dBm */ 1626fd43cf6eSHans Rosenfeld uint8_t reserved; 1627fd43cf6eSHans Rosenfeld int8_t mimo2; /* max power in half-dBm */ 1628fd43cf6eSHans Rosenfeld int8_t mimo3; /* max power in half-dBm */ 1629fd43cf6eSHans Rosenfeld } __packed; 1630fd43cf6eSHans Rosenfeld 1631fd43cf6eSHans Rosenfeld struct iwn5000_eeprom_calib_hdr { 1632fd43cf6eSHans Rosenfeld uint8_t version; 1633fd43cf6eSHans Rosenfeld uint8_t pa_type; 1634fd43cf6eSHans Rosenfeld uint16_t volt; 1635fd43cf6eSHans Rosenfeld } __packed; 1636fd43cf6eSHans Rosenfeld 1637fd43cf6eSHans Rosenfeld #define IWN_NSAMPLES 3 1638fd43cf6eSHans Rosenfeld struct iwn4965_eeprom_chan_samples { 1639fd43cf6eSHans Rosenfeld uint8_t num; 1640fd43cf6eSHans Rosenfeld struct { 1641fd43cf6eSHans Rosenfeld uint8_t temp; 1642fd43cf6eSHans Rosenfeld uint8_t gain; 1643fd43cf6eSHans Rosenfeld uint8_t power; 1644fd43cf6eSHans Rosenfeld int8_t pa_det; 1645fd43cf6eSHans Rosenfeld } samples[2][IWN_NSAMPLES]; 1646fd43cf6eSHans Rosenfeld } __packed; 1647fd43cf6eSHans Rosenfeld 1648fd43cf6eSHans Rosenfeld #define IWN_NBANDS 8 1649fd43cf6eSHans Rosenfeld struct iwn4965_eeprom_band { 1650fd43cf6eSHans Rosenfeld uint8_t lo; /* low channel number */ 1651fd43cf6eSHans Rosenfeld uint8_t hi; /* high channel number */ 1652fd43cf6eSHans Rosenfeld struct iwn4965_eeprom_chan_samples chans[2]; 1653fd43cf6eSHans Rosenfeld } __packed; 1654fd43cf6eSHans Rosenfeld 1655fd43cf6eSHans Rosenfeld /* 1656fd43cf6eSHans Rosenfeld * Offsets of channels descriptions in EEPROM. 1657fd43cf6eSHans Rosenfeld */ 1658fd43cf6eSHans Rosenfeld static const uint32_t iwn4965_regulatory_bands[IWN_NBANDS] = { 1659fd43cf6eSHans Rosenfeld IWN4965_EEPROM_BAND1, 1660fd43cf6eSHans Rosenfeld IWN4965_EEPROM_BAND2, 1661fd43cf6eSHans Rosenfeld IWN4965_EEPROM_BAND3, 1662fd43cf6eSHans Rosenfeld IWN4965_EEPROM_BAND4, 1663fd43cf6eSHans Rosenfeld IWN4965_EEPROM_BAND5, 1664fd43cf6eSHans Rosenfeld IWN4965_EEPROM_BAND6, 1665fd43cf6eSHans Rosenfeld IWN4965_EEPROM_BAND7 1666fd43cf6eSHans Rosenfeld }; 1667fd43cf6eSHans Rosenfeld 1668fd43cf6eSHans Rosenfeld static const uint32_t iwn5000_regulatory_bands[IWN_NBANDS] = { 1669fd43cf6eSHans Rosenfeld IWN5000_EEPROM_BAND1, 1670fd43cf6eSHans Rosenfeld IWN5000_EEPROM_BAND2, 1671fd43cf6eSHans Rosenfeld IWN5000_EEPROM_BAND3, 1672fd43cf6eSHans Rosenfeld IWN5000_EEPROM_BAND4, 1673fd43cf6eSHans Rosenfeld IWN5000_EEPROM_BAND5, 1674fd43cf6eSHans Rosenfeld IWN5000_EEPROM_BAND6, 1675fd43cf6eSHans Rosenfeld IWN5000_EEPROM_BAND7 1676fd43cf6eSHans Rosenfeld }; 1677fd43cf6eSHans Rosenfeld 1678fd43cf6eSHans Rosenfeld #define IWN_CHAN_BANDS_COUNT 7 1679fd43cf6eSHans Rosenfeld #define IWN_MAX_CHAN_PER_BAND 14 1680fd43cf6eSHans Rosenfeld static const struct iwn_chan_band { 1681fd43cf6eSHans Rosenfeld uint8_t nchan; 1682fd43cf6eSHans Rosenfeld uint8_t chan[IWN_MAX_CHAN_PER_BAND]; 1683fd43cf6eSHans Rosenfeld } iwn_bands[] = { 1684fd43cf6eSHans Rosenfeld /* 20MHz channels, 2GHz band. */ 1685fd43cf6eSHans Rosenfeld { 14, { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 1686fd43cf6eSHans Rosenfeld /* 20MHz channels, 5GHz band. */ 1687fd43cf6eSHans Rosenfeld { 13, { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 1688fd43cf6eSHans Rosenfeld { 12, { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 1689fd43cf6eSHans Rosenfeld { 11, { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 1690fd43cf6eSHans Rosenfeld { 6, { 145, 149, 153, 157, 161, 165 } }, 1691fd43cf6eSHans Rosenfeld /* 40MHz channels (primary channels), 2GHz band. */ 1692fd43cf6eSHans Rosenfeld { 7, { 1, 2, 3, 4, 5, 6, 7 } }, 1693fd43cf6eSHans Rosenfeld /* 40MHz channels (primary channels), 5GHz band. */ 1694fd43cf6eSHans Rosenfeld { 11, { 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 } } 1695fd43cf6eSHans Rosenfeld }; 1696fd43cf6eSHans Rosenfeld 1697*b302a200SToomas Soome #define IWN1000_OTP_NBLOCKS 3 1698*b302a200SToomas Soome #define IWN6000_OTP_NBLOCKS 4 1699fd43cf6eSHans Rosenfeld #define IWN6050_OTP_NBLOCKS 7 1700fd43cf6eSHans Rosenfeld 1701fd43cf6eSHans Rosenfeld /* HW rate indices. */ 1702fd43cf6eSHans Rosenfeld #define IWN_RIDX_CCK1 0 1703fd43cf6eSHans Rosenfeld #define IWN_RIDX_OFDM6 4 1704fd43cf6eSHans Rosenfeld 1705fd43cf6eSHans Rosenfeld static const struct iwn_rate { 1706fd43cf6eSHans Rosenfeld uint8_t rate; 1707fd43cf6eSHans Rosenfeld uint8_t plcp; 1708fd43cf6eSHans Rosenfeld uint8_t flags; 1709fd43cf6eSHans Rosenfeld } iwn_rates[IWN_RIDX_MAX + 1] = { 1710fd43cf6eSHans Rosenfeld { 2, 10, IWN_RFLAG_CCK }, 1711fd43cf6eSHans Rosenfeld { 4, 20, IWN_RFLAG_CCK }, 1712fd43cf6eSHans Rosenfeld { 11, 55, IWN_RFLAG_CCK }, 1713fd43cf6eSHans Rosenfeld { 22, 110, IWN_RFLAG_CCK }, 1714fd43cf6eSHans Rosenfeld { 12, 0xd, 0 }, 1715fd43cf6eSHans Rosenfeld { 18, 0xf, 0 }, 1716fd43cf6eSHans Rosenfeld { 24, 0x5, 0 }, 1717fd43cf6eSHans Rosenfeld { 36, 0x7, 0 }, 1718fd43cf6eSHans Rosenfeld { 48, 0x9, 0 }, 1719fd43cf6eSHans Rosenfeld { 72, 0xb, 0 }, 1720fd43cf6eSHans Rosenfeld { 96, 0x1, 0 }, 1721fd43cf6eSHans Rosenfeld { 108, 0x3, 0 }, 1722fd43cf6eSHans Rosenfeld { 120, 0x3, 0 } 1723fd43cf6eSHans Rosenfeld }; 1724fd43cf6eSHans Rosenfeld 1725fd43cf6eSHans Rosenfeld #define IWN4965_MAX_PWR_INDEX 107 1726fd43cf6eSHans Rosenfeld 1727fd43cf6eSHans Rosenfeld /* 1728fd43cf6eSHans Rosenfeld * RF Tx gain values from highest to lowest power (values obtained from 1729fd43cf6eSHans Rosenfeld * the reference driver.) 1730fd43cf6eSHans Rosenfeld */ 1731fd43cf6eSHans Rosenfeld static const uint8_t iwn4965_rf_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1732fd43cf6eSHans Rosenfeld 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 1733fd43cf6eSHans Rosenfeld 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 0x39, 0x38, 1734fd43cf6eSHans Rosenfeld 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 0x35, 0x35, 1735fd43cf6eSHans Rosenfeld 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x31, 0x31, 1736fd43cf6eSHans Rosenfeld 0x31, 0x30, 0x30, 0x30, 0x06, 0x06, 0x06, 0x05, 0x05, 0x05, 0x04, 1737fd43cf6eSHans Rosenfeld 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 1738fd43cf6eSHans Rosenfeld 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1739fd43cf6eSHans Rosenfeld 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1740fd43cf6eSHans Rosenfeld 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1741fd43cf6eSHans Rosenfeld 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1742fd43cf6eSHans Rosenfeld }; 1743fd43cf6eSHans Rosenfeld 1744fd43cf6eSHans Rosenfeld static const uint8_t iwn4965_rf_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1745fd43cf6eSHans Rosenfeld 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 1746fd43cf6eSHans Rosenfeld 0x3c, 0x3c, 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 1747fd43cf6eSHans Rosenfeld 0x39, 0x38, 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 1748fd43cf6eSHans Rosenfeld 0x35, 0x35, 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 1749fd43cf6eSHans Rosenfeld 0x31, 0x31, 0x31, 0x30, 0x30, 0x30, 0x25, 0x25, 0x25, 0x24, 0x24, 1750fd43cf6eSHans Rosenfeld 0x24, 0x23, 0x23, 0x23, 0x22, 0x18, 0x18, 0x17, 0x17, 0x17, 0x16, 1751fd43cf6eSHans Rosenfeld 0x16, 0x16, 0x15, 0x15, 0x15, 0x14, 0x14, 0x14, 0x13, 0x13, 0x13, 1752fd43cf6eSHans Rosenfeld 0x12, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x06, 0x05, 0x05, 1753fd43cf6eSHans Rosenfeld 0x05, 0x04, 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 1754fd43cf6eSHans Rosenfeld 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1755fd43cf6eSHans Rosenfeld }; 1756fd43cf6eSHans Rosenfeld 1757fd43cf6eSHans Rosenfeld /* 1758fd43cf6eSHans Rosenfeld * DSP pre-DAC gain values from highest to lowest power (values obtained 1759fd43cf6eSHans Rosenfeld * from the reference driver.) 1760fd43cf6eSHans Rosenfeld */ 1761fd43cf6eSHans Rosenfeld static const uint8_t iwn4965_dsp_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1762fd43cf6eSHans Rosenfeld 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1763fd43cf6eSHans Rosenfeld 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1764fd43cf6eSHans Rosenfeld 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1765fd43cf6eSHans Rosenfeld 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1766fd43cf6eSHans Rosenfeld 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1767fd43cf6eSHans Rosenfeld 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1768fd43cf6eSHans Rosenfeld 0x6e, 0x68, 0x62, 0x61, 0x60, 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a, 1769fd43cf6eSHans Rosenfeld 0x59, 0x58, 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50, 0x4f, 1770fd43cf6eSHans Rosenfeld 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44, 1771fd43cf6eSHans Rosenfeld 0x43, 0x42, 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b 1772fd43cf6eSHans Rosenfeld }; 1773fd43cf6eSHans Rosenfeld 1774fd43cf6eSHans Rosenfeld static const uint8_t iwn4965_dsp_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1775fd43cf6eSHans Rosenfeld 0x7b, 0x75, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1776fd43cf6eSHans Rosenfeld 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1777fd43cf6eSHans Rosenfeld 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1778fd43cf6eSHans Rosenfeld 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1779fd43cf6eSHans Rosenfeld 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1780fd43cf6eSHans Rosenfeld 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1781fd43cf6eSHans Rosenfeld 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1782fd43cf6eSHans Rosenfeld 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1783fd43cf6eSHans Rosenfeld 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1784fd43cf6eSHans Rosenfeld 0x68, 0x62, 0x6e, 0x68, 0x62, 0x5d, 0x58, 0x53, 0x4e 1785fd43cf6eSHans Rosenfeld }; 1786fd43cf6eSHans Rosenfeld 1787fd43cf6eSHans Rosenfeld /* 1788fd43cf6eSHans Rosenfeld * Power saving settings (values obtained from the reference driver.) 1789fd43cf6eSHans Rosenfeld */ 1790fd43cf6eSHans Rosenfeld #define IWN_NDTIMRANGES 3 1791fd43cf6eSHans Rosenfeld #define IWN_NPOWERLEVELS 6 1792fd43cf6eSHans Rosenfeld static const struct iwn_pmgt { 1793fd43cf6eSHans Rosenfeld uint32_t rxtimeout; 1794fd43cf6eSHans Rosenfeld uint32_t txtimeout; 1795fd43cf6eSHans Rosenfeld int32_t intval[5]; 1796fd43cf6eSHans Rosenfeld int skip_dtim; 1797fd43cf6eSHans Rosenfeld } iwn_pmgt[IWN_NDTIMRANGES][IWN_NPOWERLEVELS] = { 1798fd43cf6eSHans Rosenfeld /* DTIM <= 2 */ 1799fd43cf6eSHans Rosenfeld { 1800fd43cf6eSHans Rosenfeld { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1801fd43cf6eSHans Rosenfeld { 200, 500, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 1 */ 1802fd43cf6eSHans Rosenfeld { 200, 300, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 2 */ 1803fd43cf6eSHans Rosenfeld { 50, 100, { 2, 2, 2, 2, -1 }, 0 }, /* PS level 3 */ 1804fd43cf6eSHans Rosenfeld { 50, 25, { 2, 2, 4, 4, -1 }, 1 }, /* PS level 4 */ 1805fd43cf6eSHans Rosenfeld { 25, 25, { 2, 2, 4, 6, -1 }, 2 } /* PS level 5 */ 1806fd43cf6eSHans Rosenfeld }, 1807fd43cf6eSHans Rosenfeld /* 3 <= DTIM <= 10 */ 1808fd43cf6eSHans Rosenfeld { 1809fd43cf6eSHans Rosenfeld { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1810fd43cf6eSHans Rosenfeld { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */ 1811fd43cf6eSHans Rosenfeld { 200, 300, { 1, 2, 3, 4, 7 }, 0 }, /* PS level 2 */ 1812fd43cf6eSHans Rosenfeld { 50, 100, { 2, 4, 6, 7, 9 }, 0 }, /* PS level 3 */ 1813fd43cf6eSHans Rosenfeld { 50, 25, { 2, 4, 6, 9, 10 }, 1 }, /* PS level 4 */ 1814fd43cf6eSHans Rosenfeld { 25, 25, { 2, 4, 7, 10, 10 }, 2 } /* PS level 5 */ 1815fd43cf6eSHans Rosenfeld }, 1816fd43cf6eSHans Rosenfeld /* DTIM >= 11 */ 1817fd43cf6eSHans Rosenfeld { 1818fd43cf6eSHans Rosenfeld { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1819fd43cf6eSHans Rosenfeld { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */ 1820fd43cf6eSHans Rosenfeld { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */ 1821fd43cf6eSHans Rosenfeld { 50, 100, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 3 */ 1822fd43cf6eSHans Rosenfeld { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */ 1823fd43cf6eSHans Rosenfeld { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */ 1824fd43cf6eSHans Rosenfeld } 1825fd43cf6eSHans Rosenfeld }; 1826fd43cf6eSHans Rosenfeld 1827fd43cf6eSHans Rosenfeld struct iwn_sensitivity_limits { 1828fd43cf6eSHans Rosenfeld uint32_t min_ofdm_x1; 1829fd43cf6eSHans Rosenfeld uint32_t max_ofdm_x1; 1830fd43cf6eSHans Rosenfeld uint32_t min_ofdm_mrc_x1; 1831fd43cf6eSHans Rosenfeld uint32_t max_ofdm_mrc_x1; 1832fd43cf6eSHans Rosenfeld uint32_t min_ofdm_x4; 1833fd43cf6eSHans Rosenfeld uint32_t max_ofdm_x4; 1834fd43cf6eSHans Rosenfeld uint32_t min_ofdm_mrc_x4; 1835fd43cf6eSHans Rosenfeld uint32_t max_ofdm_mrc_x4; 1836fd43cf6eSHans Rosenfeld uint32_t min_cck_x4; 1837fd43cf6eSHans Rosenfeld uint32_t max_cck_x4; 1838fd43cf6eSHans Rosenfeld uint32_t min_cck_mrc_x4; 1839fd43cf6eSHans Rosenfeld uint32_t max_cck_mrc_x4; 1840fd43cf6eSHans Rosenfeld uint32_t min_energy_cck; 1841fd43cf6eSHans Rosenfeld uint32_t energy_cck; 1842fd43cf6eSHans Rosenfeld uint32_t energy_ofdm; 1843fd43cf6eSHans Rosenfeld }; 1844fd43cf6eSHans Rosenfeld 1845fd43cf6eSHans Rosenfeld /* 1846fd43cf6eSHans Rosenfeld * RX sensitivity limits (values obtained from the reference driver.) 1847fd43cf6eSHans Rosenfeld */ 1848fd43cf6eSHans Rosenfeld static const struct iwn_sensitivity_limits iwn4965_sensitivity_limits = { 1849fd43cf6eSHans Rosenfeld 105, 140, 1850fd43cf6eSHans Rosenfeld 220, 270, 1851fd43cf6eSHans Rosenfeld 85, 120, 1852fd43cf6eSHans Rosenfeld 170, 210, 1853fd43cf6eSHans Rosenfeld 125, 200, 1854fd43cf6eSHans Rosenfeld 200, 400, 1855fd43cf6eSHans Rosenfeld 97, 1856fd43cf6eSHans Rosenfeld 100, 1857fd43cf6eSHans Rosenfeld 100 1858fd43cf6eSHans Rosenfeld }; 1859fd43cf6eSHans Rosenfeld 1860fd43cf6eSHans Rosenfeld static const struct iwn_sensitivity_limits iwn5000_sensitivity_limits = { 1861fd43cf6eSHans Rosenfeld 120, 120, /* min = max for performance bug in DSP. */ 1862fd43cf6eSHans Rosenfeld 240, 240, /* min = max for performance bug in DSP. */ 1863fd43cf6eSHans Rosenfeld 90, 120, 1864fd43cf6eSHans Rosenfeld 170, 210, 1865fd43cf6eSHans Rosenfeld 125, 200, 1866fd43cf6eSHans Rosenfeld 170, 400, 1867fd43cf6eSHans Rosenfeld 95, 1868fd43cf6eSHans Rosenfeld 95, 1869fd43cf6eSHans Rosenfeld 95 1870fd43cf6eSHans Rosenfeld }; 1871fd43cf6eSHans Rosenfeld 1872fd43cf6eSHans Rosenfeld static const struct iwn_sensitivity_limits iwn5150_sensitivity_limits = { 1873fd43cf6eSHans Rosenfeld 105, 105, /* min = max for performance bug in DSP. */ 1874fd43cf6eSHans Rosenfeld 220, 220, /* min = max for performance bug in DSP. */ 1875fd43cf6eSHans Rosenfeld 90, 120, 1876fd43cf6eSHans Rosenfeld 170, 210, 1877fd43cf6eSHans Rosenfeld 125, 200, 1878fd43cf6eSHans Rosenfeld 170, 400, 1879fd43cf6eSHans Rosenfeld 95, 1880fd43cf6eSHans Rosenfeld 95, 1881fd43cf6eSHans Rosenfeld 95 1882fd43cf6eSHans Rosenfeld }; 1883fd43cf6eSHans Rosenfeld 1884fd43cf6eSHans Rosenfeld static const struct iwn_sensitivity_limits iwn1000_sensitivity_limits = { 1885fd43cf6eSHans Rosenfeld 120, 155, 1886fd43cf6eSHans Rosenfeld 240, 290, 1887fd43cf6eSHans Rosenfeld 90, 120, 1888fd43cf6eSHans Rosenfeld 170, 210, 1889fd43cf6eSHans Rosenfeld 125, 200, 1890fd43cf6eSHans Rosenfeld 170, 400, 1891fd43cf6eSHans Rosenfeld 95, 1892fd43cf6eSHans Rosenfeld 95, 1893fd43cf6eSHans Rosenfeld 95 1894fd43cf6eSHans Rosenfeld }; 1895fd43cf6eSHans Rosenfeld 1896fd43cf6eSHans Rosenfeld static const struct iwn_sensitivity_limits iwn6000_sensitivity_limits = { 1897fd43cf6eSHans Rosenfeld 105, 110, 1898fd43cf6eSHans Rosenfeld 192, 232, 1899fd43cf6eSHans Rosenfeld 80, 145, 1900fd43cf6eSHans Rosenfeld 128, 232, 1901fd43cf6eSHans Rosenfeld 125, 175, 1902fd43cf6eSHans Rosenfeld 160, 310, 1903fd43cf6eSHans Rosenfeld 97, 1904fd43cf6eSHans Rosenfeld 97, 1905fd43cf6eSHans Rosenfeld 100 1906fd43cf6eSHans Rosenfeld }; 1907fd43cf6eSHans Rosenfeld 1908fd43cf6eSHans Rosenfeld static const struct iwn_sensitivity_limits iwn2000_sensitivity_limits = { 1909fd43cf6eSHans Rosenfeld 105, 110, 1910fd43cf6eSHans Rosenfeld 192, 232, 1911fd43cf6eSHans Rosenfeld 80, 145, 1912fd43cf6eSHans Rosenfeld 128, 232, 1913fd43cf6eSHans Rosenfeld 125, 175, 1914fd43cf6eSHans Rosenfeld 160, 310, 1915fd43cf6eSHans Rosenfeld 97, 1916fd43cf6eSHans Rosenfeld 97, 1917fd43cf6eSHans Rosenfeld 100 1918fd43cf6eSHans Rosenfeld }; 1919fd43cf6eSHans Rosenfeld 1920fd43cf6eSHans Rosenfeld #ifndef IEEE80211_NO_HT 1921fd43cf6eSHans Rosenfeld /* Map TID to TX scheduler's FIFO. */ 1922fd43cf6eSHans Rosenfeld static const uint8_t iwn_tid2fifo[] = { 1923fd43cf6eSHans Rosenfeld 1, 0, 0, 1, 2, 2, 3, 3, 7, 7, 7, 7, 7, 7, 7, 7, 3 1924fd43cf6eSHans Rosenfeld }; 1925fd43cf6eSHans Rosenfeld #endif 1926fd43cf6eSHans Rosenfeld 1927fd43cf6eSHans Rosenfeld #ifdef notyet 1928fd43cf6eSHans Rosenfeld /* WiFi/WiMAX coexist event priority table for 6050. */ 1929fd43cf6eSHans Rosenfeld static const struct iwn5000_wimax_event iwn6050_wimax_events[] = { 1930fd43cf6eSHans Rosenfeld { 0x04, 0x03, 0x00, 0x00 }, 1931fd43cf6eSHans Rosenfeld { 0x04, 0x03, 0x00, 0x03 }, 1932fd43cf6eSHans Rosenfeld { 0x04, 0x03, 0x00, 0x03 }, 1933fd43cf6eSHans Rosenfeld { 0x04, 0x03, 0x00, 0x03 }, 1934fd43cf6eSHans Rosenfeld { 0x04, 0x03, 0x00, 0x00 }, 1935fd43cf6eSHans Rosenfeld { 0x04, 0x03, 0x00, 0x07 }, 1936fd43cf6eSHans Rosenfeld { 0x04, 0x03, 0x00, 0x00 }, 1937fd43cf6eSHans Rosenfeld { 0x04, 0x03, 0x00, 0x03 }, 1938fd43cf6eSHans Rosenfeld { 0x04, 0x03, 0x00, 0x03 }, 1939fd43cf6eSHans Rosenfeld { 0x04, 0x03, 0x00, 0x00 }, 1940fd43cf6eSHans Rosenfeld { 0x06, 0x03, 0x00, 0x07 }, 1941fd43cf6eSHans Rosenfeld { 0x04, 0x03, 0x00, 0x00 }, 1942fd43cf6eSHans Rosenfeld { 0x06, 0x06, 0x00, 0x03 }, 1943fd43cf6eSHans Rosenfeld { 0x04, 0x03, 0x00, 0x07 }, 1944fd43cf6eSHans Rosenfeld { 0x04, 0x03, 0x00, 0x00 }, 1945fd43cf6eSHans Rosenfeld { 0x04, 0x03, 0x00, 0x00 } 1946fd43cf6eSHans Rosenfeld }; 1947fd43cf6eSHans Rosenfeld #endif 1948fd43cf6eSHans Rosenfeld 1949fd43cf6eSHans Rosenfeld /* Firmware errors. */ 1950fd43cf6eSHans Rosenfeld static const char * const iwn_fw_errmsg[] = { 1951fd43cf6eSHans Rosenfeld "OK", 1952fd43cf6eSHans Rosenfeld "FAIL", 1953fd43cf6eSHans Rosenfeld "BAD_PARAM", 1954fd43cf6eSHans Rosenfeld "BAD_CHECKSUM", 1955fd43cf6eSHans Rosenfeld "NMI_INTERRUPT_WDG", 1956fd43cf6eSHans Rosenfeld "SYSASSERT", 1957fd43cf6eSHans Rosenfeld "FATAL_ERROR", 1958fd43cf6eSHans Rosenfeld "BAD_COMMAND", 1959fd43cf6eSHans Rosenfeld "HW_ERROR_TUNE_LOCK", 1960fd43cf6eSHans Rosenfeld "HW_ERROR_TEMPERATURE", 1961fd43cf6eSHans Rosenfeld "ILLEGAL_CHAN_FREQ", 1962fd43cf6eSHans Rosenfeld "VCC_NOT_STABLE", 1963fd43cf6eSHans Rosenfeld "FH_ERROR", 1964fd43cf6eSHans Rosenfeld "NMI_INTERRUPT_HOST", 1965fd43cf6eSHans Rosenfeld "NMI_INTERRUPT_ACTION_PT", 1966fd43cf6eSHans Rosenfeld "NMI_INTERRUPT_UNKNOWN", 1967fd43cf6eSHans Rosenfeld "UCODE_VERSION_MISMATCH", 1968fd43cf6eSHans Rosenfeld "HW_ERROR_ABS_LOCK", 1969fd43cf6eSHans Rosenfeld "HW_ERROR_CAL_LOCK_FAIL", 1970fd43cf6eSHans Rosenfeld "NMI_INTERRUPT_INST_ACTION_PT", 1971fd43cf6eSHans Rosenfeld "NMI_INTERRUPT_DATA_ACTION_PT", 1972fd43cf6eSHans Rosenfeld "NMI_TRM_HW_ER", 1973fd43cf6eSHans Rosenfeld "NMI_INTERRUPT_TRM", 1974*b302a200SToomas Soome "NMI_INTERRUPT_BREAKPOINT", 1975fd43cf6eSHans Rosenfeld "DEBUG_0", 1976fd43cf6eSHans Rosenfeld "DEBUG_1", 1977fd43cf6eSHans Rosenfeld "DEBUG_2", 1978fd43cf6eSHans Rosenfeld "DEBUG_3", 1979fd43cf6eSHans Rosenfeld "ADVANCED_SYSASSERT" 1980fd43cf6eSHans Rosenfeld }; 1981fd43cf6eSHans Rosenfeld 1982fd43cf6eSHans Rosenfeld /* Find least significant bit that is set. */ 1983fd43cf6eSHans Rosenfeld #define IWN_LSB(x) ((((x) - 1) & (x)) ^ (x)) 1984fd43cf6eSHans Rosenfeld 1985fd43cf6eSHans Rosenfeld #define IWN_READ(sc, reg) \ 1986fd43cf6eSHans Rosenfeld iwn_read(sc, reg) 1987fd43cf6eSHans Rosenfeld 1988fd43cf6eSHans Rosenfeld #define IWN_WRITE(sc, reg, val) \ 1989fd43cf6eSHans Rosenfeld iwn_write(sc, reg, val) 1990fd43cf6eSHans Rosenfeld 1991fd43cf6eSHans Rosenfeld #define IWN_WRITE_1(sc, reg, val) \ 1992fd43cf6eSHans Rosenfeld iwn_write_1(sc, reg, val) 1993fd43cf6eSHans Rosenfeld 1994fd43cf6eSHans Rosenfeld #define IWN_SETBITS(sc, reg, mask) \ 1995fd43cf6eSHans Rosenfeld IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask)) 1996fd43cf6eSHans Rosenfeld 1997fd43cf6eSHans Rosenfeld #define IWN_CLRBITS(sc, reg, mask) \ 1998fd43cf6eSHans Rosenfeld IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask)) 1999fd43cf6eSHans Rosenfeld 2000fd43cf6eSHans Rosenfeld #define IWN_BARRIER_WRITE(sc) \ 2001fd43cf6eSHans Rosenfeld membar_producer() 2002fd43cf6eSHans Rosenfeld 2003fd43cf6eSHans Rosenfeld #define IWN_BARRIER_READ_WRITE(sc) \ 2004fd43cf6eSHans Rosenfeld (membar_producer(), membar_consumer()) 2005fd43cf6eSHans Rosenfeld 2006fd43cf6eSHans Rosenfeld #endif /* _IF_IWNREG_H */ 2007