1*6bbbd442SRobert Mustacchi /*- 2*6bbbd442SRobert Mustacchi * Copyright 2021 Intel Corp 3*6bbbd442SRobert Mustacchi * Copyright 2021 Rubicon Communications, LLC (Netgate) 4*6bbbd442SRobert Mustacchi * SPDX-License-Identifier: BSD-3-Clause 5*6bbbd442SRobert Mustacchi */ 6*6bbbd442SRobert Mustacchi 7*6bbbd442SRobert Mustacchi #ifndef _IGC_DEFINES_H_ 8*6bbbd442SRobert Mustacchi #define _IGC_DEFINES_H_ 9*6bbbd442SRobert Mustacchi 10*6bbbd442SRobert Mustacchi /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 11*6bbbd442SRobert Mustacchi #define REQ_TX_DESCRIPTOR_MULTIPLE 8 12*6bbbd442SRobert Mustacchi #define REQ_RX_DESCRIPTOR_MULTIPLE 8 13*6bbbd442SRobert Mustacchi 14*6bbbd442SRobert Mustacchi /* Definitions for power management and wakeup registers */ 15*6bbbd442SRobert Mustacchi /* Wake Up Control */ 16*6bbbd442SRobert Mustacchi #define IGC_WUC_APME 0x00000001 /* APM Enable */ 17*6bbbd442SRobert Mustacchi #define IGC_WUC_PME_EN 0x00000002 /* PME Enable */ 18*6bbbd442SRobert Mustacchi #define IGC_WUC_PME_STATUS 0x00000004 /* PME Status */ 19*6bbbd442SRobert Mustacchi #define IGC_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ 20*6bbbd442SRobert Mustacchi #define IGC_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */ 21*6bbbd442SRobert Mustacchi 22*6bbbd442SRobert Mustacchi /* Wake Up Filter Control */ 23*6bbbd442SRobert Mustacchi #define IGC_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 24*6bbbd442SRobert Mustacchi #define IGC_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 25*6bbbd442SRobert Mustacchi #define IGC_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 26*6bbbd442SRobert Mustacchi #define IGC_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 27*6bbbd442SRobert Mustacchi #define IGC_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 28*6bbbd442SRobert Mustacchi #define IGC_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 29*6bbbd442SRobert Mustacchi #define IGC_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ 30*6bbbd442SRobert Mustacchi 31*6bbbd442SRobert Mustacchi /* Wake Up Status */ 32*6bbbd442SRobert Mustacchi #define IGC_WUS_LNKC IGC_WUFC_LNKC 33*6bbbd442SRobert Mustacchi #define IGC_WUS_MAG IGC_WUFC_MAG 34*6bbbd442SRobert Mustacchi #define IGC_WUS_EX IGC_WUFC_EX 35*6bbbd442SRobert Mustacchi #define IGC_WUS_MC IGC_WUFC_MC 36*6bbbd442SRobert Mustacchi #define IGC_WUS_BC IGC_WUFC_BC 37*6bbbd442SRobert Mustacchi 38*6bbbd442SRobert Mustacchi /* Packet types that are enabled for wake packet delivery */ 39*6bbbd442SRobert Mustacchi #define WAKE_PKT_WUS ( \ 40*6bbbd442SRobert Mustacchi IGC_WUS_EX | \ 41*6bbbd442SRobert Mustacchi IGC_WUS_ARPD | \ 42*6bbbd442SRobert Mustacchi IGC_WUS_IPV4 | \ 43*6bbbd442SRobert Mustacchi IGC_WUS_IPV6 | \ 44*6bbbd442SRobert Mustacchi IGC_WUS_NSD) 45*6bbbd442SRobert Mustacchi 46*6bbbd442SRobert Mustacchi /* Wake Up Packet Length */ 47*6bbbd442SRobert Mustacchi #define IGC_WUPL_MASK 0x00000FFF 48*6bbbd442SRobert Mustacchi 49*6bbbd442SRobert Mustacchi /* Wake Up Packet Memory stores the first 128 bytes of the wake up packet */ 50*6bbbd442SRobert Mustacchi #define IGC_WUPM_BYTES 128 51*6bbbd442SRobert Mustacchi 52*6bbbd442SRobert Mustacchi #define IGC_WUS_ARPD 0x00000020 /* Directed ARP Request */ 53*6bbbd442SRobert Mustacchi #define IGC_WUS_IPV4 0x00000040 /* Directed IPv4 */ 54*6bbbd442SRobert Mustacchi #define IGC_WUS_IPV6 0x00000080 /* Directed IPv6 */ 55*6bbbd442SRobert Mustacchi #define IGC_WUS_NSD 0x00000400 /* Directed IPv6 Neighbor Solicitation */ 56*6bbbd442SRobert Mustacchi 57*6bbbd442SRobert Mustacchi /* Extended Device Control */ 58*6bbbd442SRobert Mustacchi #define IGC_CTRL_EXT_LPCD 0x00000004 /* LCD Power Cycle Done */ 59*6bbbd442SRobert Mustacchi #define IGC_CTRL_EXT_SDP4_DATA 0x00000010 /* SW Definable Pin 4 data */ 60*6bbbd442SRobert Mustacchi #define IGC_CTRL_EXT_SDP6_DATA 0x00000040 /* SW Definable Pin 6 data */ 61*6bbbd442SRobert Mustacchi #define IGC_CTRL_EXT_SDP3_DATA 0x00000080 /* SW Definable Pin 3 data */ 62*6bbbd442SRobert Mustacchi #define IGC_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */ 63*6bbbd442SRobert Mustacchi #define IGC_CTRL_EXT_SDP3_DIR 0x00000800 /* Direction of SDP3 0=in 1=out */ 64*6bbbd442SRobert Mustacchi #define IGC_CTRL_EXT_FORCE_SMBUS 0x00000800 /* Force SMBus mode */ 65*6bbbd442SRobert Mustacchi #define IGC_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ 66*6bbbd442SRobert Mustacchi #define IGC_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ 67*6bbbd442SRobert Mustacchi #define IGC_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 68*6bbbd442SRobert Mustacchi #define IGC_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clk Gating */ 69*6bbbd442SRobert Mustacchi #define IGC_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 70*6bbbd442SRobert Mustacchi #define IGC_CTRL_EXT_EIAME 0x01000000 71*6bbbd442SRobert Mustacchi #define IGC_CTRL_EXT_DRV_LOAD 0x10000000 /* Drv loaded bit for FW */ 72*6bbbd442SRobert Mustacchi #define IGC_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */ 73*6bbbd442SRobert Mustacchi #define IGC_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ 74*6bbbd442SRobert Mustacchi #define IGC_CTRL_EXT_PHYPDEN 0x00100000 75*6bbbd442SRobert Mustacchi #define IGC_IVAR_VALID 0x80 76*6bbbd442SRobert Mustacchi #define IGC_GPIE_NSICR 0x00000001 77*6bbbd442SRobert Mustacchi #define IGC_GPIE_MSIX_MODE 0x00000010 78*6bbbd442SRobert Mustacchi #define IGC_GPIE_EIAME 0x40000000 79*6bbbd442SRobert Mustacchi #define IGC_GPIE_PBA 0x80000000 80*6bbbd442SRobert Mustacchi 81*6bbbd442SRobert Mustacchi /* Receive Descriptor bit definitions */ 82*6bbbd442SRobert Mustacchi #define IGC_RXD_STAT_DD 0x01 /* Descriptor Done */ 83*6bbbd442SRobert Mustacchi #define IGC_RXD_STAT_EOP 0x02 /* End of Packet */ 84*6bbbd442SRobert Mustacchi #define IGC_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 85*6bbbd442SRobert Mustacchi #define IGC_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 86*6bbbd442SRobert Mustacchi #define IGC_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 87*6bbbd442SRobert Mustacchi #define IGC_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 88*6bbbd442SRobert Mustacchi #define IGC_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 89*6bbbd442SRobert Mustacchi #define IGC_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 90*6bbbd442SRobert Mustacchi #define IGC_RXD_STAT_IPIDV 0x200 /* IP identification valid */ 91*6bbbd442SRobert Mustacchi #define IGC_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ 92*6bbbd442SRobert Mustacchi #define IGC_RXD_ERR_CE 0x01 /* CRC Error */ 93*6bbbd442SRobert Mustacchi #define IGC_RXD_ERR_SE 0x02 /* Symbol Error */ 94*6bbbd442SRobert Mustacchi #define IGC_RXD_ERR_SEQ 0x04 /* Sequence Error */ 95*6bbbd442SRobert Mustacchi #define IGC_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ 96*6bbbd442SRobert Mustacchi #define IGC_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ 97*6bbbd442SRobert Mustacchi #define IGC_RXD_ERR_IPE 0x40 /* IP Checksum Error */ 98*6bbbd442SRobert Mustacchi #define IGC_RXD_ERR_RXE 0x80 /* Rx Data Error */ 99*6bbbd442SRobert Mustacchi #define IGC_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 100*6bbbd442SRobert Mustacchi 101*6bbbd442SRobert Mustacchi #define IGC_RXDEXT_STATERR_TST 0x00000100 /* Time Stamp taken */ 102*6bbbd442SRobert Mustacchi #define IGC_RXDEXT_STATERR_LB 0x00040000 103*6bbbd442SRobert Mustacchi #define IGC_RXDEXT_STATERR_L4E 0x20000000 104*6bbbd442SRobert Mustacchi #define IGC_RXDEXT_STATERR_IPE 0x40000000 105*6bbbd442SRobert Mustacchi #define IGC_RXDEXT_STATERR_RXE 0x80000000 106*6bbbd442SRobert Mustacchi 107*6bbbd442SRobert Mustacchi /* Same mask, but for extended and packet split descriptors */ 108*6bbbd442SRobert Mustacchi #define IGC_RXDEXT_ERR_FRAME_ERR_MASK ( \ 109*6bbbd442SRobert Mustacchi IGC_RXDEXT_STATERR_CE | \ 110*6bbbd442SRobert Mustacchi IGC_RXDEXT_STATERR_SE | \ 111*6bbbd442SRobert Mustacchi IGC_RXDEXT_STATERR_SEQ | \ 112*6bbbd442SRobert Mustacchi IGC_RXDEXT_STATERR_CXE | \ 113*6bbbd442SRobert Mustacchi IGC_RXDEXT_STATERR_RXE) 114*6bbbd442SRobert Mustacchi 115*6bbbd442SRobert Mustacchi #if !defined(EXTERNAL_RELEASE) || defined(IGCE_MQ) 116*6bbbd442SRobert Mustacchi #define IGC_MRQC_ENABLE_RSS_2Q 0x00000001 117*6bbbd442SRobert Mustacchi #endif /* !EXTERNAL_RELEASE || IGCE_MQ */ 118*6bbbd442SRobert Mustacchi #define IGC_MRQC_RSS_FIELD_MASK 0xFFFF0000 119*6bbbd442SRobert Mustacchi #define IGC_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 120*6bbbd442SRobert Mustacchi #define IGC_MRQC_RSS_FIELD_IPV4 0x00020000 121*6bbbd442SRobert Mustacchi #define IGC_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000 122*6bbbd442SRobert Mustacchi #define IGC_MRQC_RSS_FIELD_IPV6 0x00100000 123*6bbbd442SRobert Mustacchi #define IGC_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 124*6bbbd442SRobert Mustacchi 125*6bbbd442SRobert Mustacchi #define IGC_RXDPS_HDRSTAT_HDRSP 0x00008000 126*6bbbd442SRobert Mustacchi 127*6bbbd442SRobert Mustacchi /* Management Control */ 128*6bbbd442SRobert Mustacchi #define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 129*6bbbd442SRobert Mustacchi #define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 130*6bbbd442SRobert Mustacchi #define IGC_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ 131*6bbbd442SRobert Mustacchi #define IGC_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 132*6bbbd442SRobert Mustacchi #define IGC_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ 133*6bbbd442SRobert Mustacchi /* Enable MAC address filtering */ 134*6bbbd442SRobert Mustacchi #define IGC_MANC_EN_MAC_ADDR_FILTER 0x00100000 135*6bbbd442SRobert Mustacchi /* Enable MNG packets to host memory */ 136*6bbbd442SRobert Mustacchi #define IGC_MANC_EN_MNG2HOST 0x00200000 137*6bbbd442SRobert Mustacchi 138*6bbbd442SRobert Mustacchi #define IGC_MANC2H_PORT_623 0x00000020 /* Port 0x26f */ 139*6bbbd442SRobert Mustacchi #define IGC_MANC2H_PORT_664 0x00000040 /* Port 0x298 */ 140*6bbbd442SRobert Mustacchi #define IGC_MDEF_PORT_623 0x00000800 /* Port 0x26f */ 141*6bbbd442SRobert Mustacchi #define IGC_MDEF_PORT_664 0x00000400 /* Port 0x298 */ 142*6bbbd442SRobert Mustacchi 143*6bbbd442SRobert Mustacchi /* Receive Control */ 144*6bbbd442SRobert Mustacchi #define IGC_RCTL_RST 0x00000001 /* Software reset */ 145*6bbbd442SRobert Mustacchi #define IGC_RCTL_EN 0x00000002 /* enable */ 146*6bbbd442SRobert Mustacchi #define IGC_RCTL_SBP 0x00000004 /* store bad packet */ 147*6bbbd442SRobert Mustacchi #define IGC_RCTL_UPE 0x00000008 /* unicast promisc enable */ 148*6bbbd442SRobert Mustacchi #define IGC_RCTL_MPE 0x00000010 /* multicast promisc enable */ 149*6bbbd442SRobert Mustacchi #define IGC_RCTL_LPE 0x00000020 /* long packet enable */ 150*6bbbd442SRobert Mustacchi #define IGC_RCTL_LBM_NO 0x00000000 /* no loopback mode */ 151*6bbbd442SRobert Mustacchi #define IGC_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 152*6bbbd442SRobert Mustacchi #define IGC_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 153*6bbbd442SRobert Mustacchi #define IGC_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ 154*6bbbd442SRobert Mustacchi #define IGC_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */ 155*6bbbd442SRobert Mustacchi #define IGC_RCTL_RDMTS_HEX 0x00010000 156*6bbbd442SRobert Mustacchi #define IGC_RCTL_RDMTS1_HEX IGC_RCTL_RDMTS_HEX 157*6bbbd442SRobert Mustacchi #define IGC_RCTL_MO_SHIFT 12 /* multicast offset shift */ 158*6bbbd442SRobert Mustacchi #define IGC_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ 159*6bbbd442SRobert Mustacchi #define IGC_RCTL_BAM 0x00008000 /* broadcast enable */ 160*6bbbd442SRobert Mustacchi /* these buffer sizes are valid if IGC_RCTL_BSEX is 0 */ 161*6bbbd442SRobert Mustacchi #define IGC_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */ 162*6bbbd442SRobert Mustacchi #define IGC_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */ 163*6bbbd442SRobert Mustacchi #define IGC_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */ 164*6bbbd442SRobert Mustacchi #define IGC_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */ 165*6bbbd442SRobert Mustacchi /* these buffer sizes are valid if IGC_RCTL_BSEX is 1 */ 166*6bbbd442SRobert Mustacchi #define IGC_RCTL_SZ_16384 0x00010000 /* Rx buffer size 16384 */ 167*6bbbd442SRobert Mustacchi #define IGC_RCTL_SZ_8192 0x00020000 /* Rx buffer size 8192 */ 168*6bbbd442SRobert Mustacchi #define IGC_RCTL_SZ_4096 0x00030000 /* Rx buffer size 4096 */ 169*6bbbd442SRobert Mustacchi #define IGC_RCTL_VFE 0x00040000 /* vlan filter enable */ 170*6bbbd442SRobert Mustacchi #define IGC_RCTL_CFIEN 0x00080000 /* canonical form enable */ 171*6bbbd442SRobert Mustacchi #define IGC_RCTL_CFI 0x00100000 /* canonical form indicator */ 172*6bbbd442SRobert Mustacchi #define IGC_RCTL_DPF 0x00400000 /* discard pause frames */ 173*6bbbd442SRobert Mustacchi #define IGC_RCTL_PMCF 0x00800000 /* pass MAC control frames */ 174*6bbbd442SRobert Mustacchi #define IGC_RCTL_BSEX 0x02000000 /* Buffer size extension */ 175*6bbbd442SRobert Mustacchi #define IGC_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ 176*6bbbd442SRobert Mustacchi 177*6bbbd442SRobert Mustacchi /* Use byte values for the following shift parameters 178*6bbbd442SRobert Mustacchi * Usage: 179*6bbbd442SRobert Mustacchi * psrctl |= (((ROUNDUP(value0, 128) >> IGC_PSRCTL_BSIZE0_SHIFT) & 180*6bbbd442SRobert Mustacchi * IGC_PSRCTL_BSIZE0_MASK) | 181*6bbbd442SRobert Mustacchi * ((ROUNDUP(value1, 1024) >> IGC_PSRCTL_BSIZE1_SHIFT) & 182*6bbbd442SRobert Mustacchi * IGC_PSRCTL_BSIZE1_MASK) | 183*6bbbd442SRobert Mustacchi * ((ROUNDUP(value2, 1024) << IGC_PSRCTL_BSIZE2_SHIFT) & 184*6bbbd442SRobert Mustacchi * IGC_PSRCTL_BSIZE2_MASK) | 185*6bbbd442SRobert Mustacchi * ((ROUNDUP(value3, 1024) << IGC_PSRCTL_BSIZE3_SHIFT) |; 186*6bbbd442SRobert Mustacchi * IGC_PSRCTL_BSIZE3_MASK)) 187*6bbbd442SRobert Mustacchi * where value0 = [128..16256], default=256 188*6bbbd442SRobert Mustacchi * value1 = [1024..64512], default=4096 189*6bbbd442SRobert Mustacchi * value2 = [0..64512], default=4096 190*6bbbd442SRobert Mustacchi * value3 = [0..64512], default=0 191*6bbbd442SRobert Mustacchi */ 192*6bbbd442SRobert Mustacchi 193*6bbbd442SRobert Mustacchi #define IGC_PSRCTL_BSIZE0_MASK 0x0000007F 194*6bbbd442SRobert Mustacchi #define IGC_PSRCTL_BSIZE1_MASK 0x00003F00 195*6bbbd442SRobert Mustacchi #define IGC_PSRCTL_BSIZE2_MASK 0x003F0000 196*6bbbd442SRobert Mustacchi #define IGC_PSRCTL_BSIZE3_MASK 0x3F000000 197*6bbbd442SRobert Mustacchi 198*6bbbd442SRobert Mustacchi #define IGC_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ 199*6bbbd442SRobert Mustacchi #define IGC_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ 200*6bbbd442SRobert Mustacchi #define IGC_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ 201*6bbbd442SRobert Mustacchi #define IGC_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ 202*6bbbd442SRobert Mustacchi 203*6bbbd442SRobert Mustacchi /* SWFW_SYNC Definitions */ 204*6bbbd442SRobert Mustacchi #define IGC_SWFW_EEP_SM 0x01 205*6bbbd442SRobert Mustacchi #define IGC_SWFW_PHY0_SM 0x02 206*6bbbd442SRobert Mustacchi #define IGC_SWFW_PHY1_SM 0x04 207*6bbbd442SRobert Mustacchi #define IGC_SWFW_CSR_SM 0x08 208*6bbbd442SRobert Mustacchi #define IGC_SWFW_SW_MNG_SM 0x400 209*6bbbd442SRobert Mustacchi 210*6bbbd442SRobert Mustacchi /* Device Control */ 211*6bbbd442SRobert Mustacchi #define IGC_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 212*6bbbd442SRobert Mustacchi #define IGC_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ 213*6bbbd442SRobert Mustacchi #define IGC_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master reqs */ 214*6bbbd442SRobert Mustacchi #define IGC_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ 215*6bbbd442SRobert Mustacchi #define IGC_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ 216*6bbbd442SRobert Mustacchi #define IGC_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 217*6bbbd442SRobert Mustacchi #define IGC_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ 218*6bbbd442SRobert Mustacchi #define IGC_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ 219*6bbbd442SRobert Mustacchi #define IGC_CTRL_SPD_10 0x00000000 /* Force 10Mb */ 220*6bbbd442SRobert Mustacchi #define IGC_CTRL_SPD_100 0x00000100 /* Force 100Mb */ 221*6bbbd442SRobert Mustacchi #define IGC_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ 222*6bbbd442SRobert Mustacchi #define IGC_CTRL_FRCSPD 0x00000800 /* Force Speed */ 223*6bbbd442SRobert Mustacchi #define IGC_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 224*6bbbd442SRobert Mustacchi #define IGC_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ 225*6bbbd442SRobert Mustacchi #define IGC_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ 226*6bbbd442SRobert Mustacchi #define IGC_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ 227*6bbbd442SRobert Mustacchi #define IGC_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */ 228*6bbbd442SRobert Mustacchi #define IGC_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ 229*6bbbd442SRobert Mustacchi #define IGC_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ 230*6bbbd442SRobert Mustacchi #define IGC_CTRL_DEV_RST 0x20000000 /* Device reset */ 231*6bbbd442SRobert Mustacchi #define IGC_CTRL_RST 0x04000000 /* Global reset */ 232*6bbbd442SRobert Mustacchi #define IGC_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ 233*6bbbd442SRobert Mustacchi #define IGC_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ 234*6bbbd442SRobert Mustacchi #define IGC_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 235*6bbbd442SRobert Mustacchi #define IGC_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 236*6bbbd442SRobert Mustacchi 237*6bbbd442SRobert Mustacchi 238*6bbbd442SRobert Mustacchi #define IGC_CONNSW_AUTOSENSE_EN 0x1 239*6bbbd442SRobert Mustacchi #define IGC_PCS_LCTL_FORCE_FCTRL 0x80 240*6bbbd442SRobert Mustacchi 241*6bbbd442SRobert Mustacchi #define IGC_PCS_LSTS_AN_COMPLETE 0x10000 242*6bbbd442SRobert Mustacchi 243*6bbbd442SRobert Mustacchi /* Device Status */ 244*6bbbd442SRobert Mustacchi #define IGC_STATUS_FD 0x00000001 /* Duplex 0=half 1=full */ 245*6bbbd442SRobert Mustacchi #define IGC_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 246*6bbbd442SRobert Mustacchi #define IGC_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ 247*6bbbd442SRobert Mustacchi #define IGC_STATUS_FUNC_SHIFT 2 248*6bbbd442SRobert Mustacchi #define IGC_STATUS_FUNC_1 0x00000004 /* Function 1 */ 249*6bbbd442SRobert Mustacchi #define IGC_STATUS_TXOFF 0x00000010 /* transmission paused */ 250*6bbbd442SRobert Mustacchi #define IGC_STATUS_SPEED_MASK 0x000000C0 251*6bbbd442SRobert Mustacchi #define IGC_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ 252*6bbbd442SRobert Mustacchi #define IGC_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 253*6bbbd442SRobert Mustacchi #define IGC_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 254*6bbbd442SRobert Mustacchi #define IGC_STATUS_SPEED_2500 0x00400000 /* Speed 2.5Gb/s indication for I225 */ 255*6bbbd442SRobert Mustacchi #define IGC_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Compltn by NVM */ 256*6bbbd442SRobert Mustacchi #define IGC_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */ 257*6bbbd442SRobert Mustacchi #define IGC_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master request status */ 258*6bbbd442SRobert Mustacchi #define IGC_STATUS_2P5_SKU 0x00001000 /* Val of 2.5GBE SKU strap */ 259*6bbbd442SRobert Mustacchi #define IGC_STATUS_2P5_SKU_OVER 0x00002000 /* Val of 2.5GBE SKU Over */ 260*6bbbd442SRobert Mustacchi #define IGC_STATUS_PCIM_STATE 0x40000000 /* PCIm function state */ 261*6bbbd442SRobert Mustacchi 262*6bbbd442SRobert Mustacchi #define SPEED_10 10 263*6bbbd442SRobert Mustacchi #define SPEED_100 100 264*6bbbd442SRobert Mustacchi #define SPEED_1000 1000 265*6bbbd442SRobert Mustacchi #define SPEED_2500 2500 266*6bbbd442SRobert Mustacchi #define HALF_DUPLEX 1 267*6bbbd442SRobert Mustacchi #define FULL_DUPLEX 2 268*6bbbd442SRobert Mustacchi 269*6bbbd442SRobert Mustacchi 270*6bbbd442SRobert Mustacchi #define ADVERTISE_10_HALF 0x0001 271*6bbbd442SRobert Mustacchi #define ADVERTISE_10_FULL 0x0002 272*6bbbd442SRobert Mustacchi #define ADVERTISE_100_HALF 0x0004 273*6bbbd442SRobert Mustacchi #define ADVERTISE_100_FULL 0x0008 274*6bbbd442SRobert Mustacchi #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ 275*6bbbd442SRobert Mustacchi #define ADVERTISE_1000_FULL 0x0020 276*6bbbd442SRobert Mustacchi #define ADVERTISE_2500_HALF 0x0040 /* NOT used, just FYI */ 277*6bbbd442SRobert Mustacchi #define ADVERTISE_2500_FULL 0x0080 278*6bbbd442SRobert Mustacchi 279*6bbbd442SRobert Mustacchi /* 1000/H is not supported, nor spec-compliant. */ 280*6bbbd442SRobert Mustacchi #define IGC_ALL_SPEED_DUPLEX ( \ 281*6bbbd442SRobert Mustacchi ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \ 282*6bbbd442SRobert Mustacchi ADVERTISE_100_FULL | ADVERTISE_1000_FULL) 283*6bbbd442SRobert Mustacchi #define IGC_ALL_SPEED_DUPLEX_2500 ( \ 284*6bbbd442SRobert Mustacchi ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \ 285*6bbbd442SRobert Mustacchi ADVERTISE_100_FULL | ADVERTISE_1000_FULL | ADVERTISE_2500_FULL) 286*6bbbd442SRobert Mustacchi #define IGC_ALL_NOT_GIG ( \ 287*6bbbd442SRobert Mustacchi ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \ 288*6bbbd442SRobert Mustacchi ADVERTISE_100_FULL) 289*6bbbd442SRobert Mustacchi #define IGC_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) 290*6bbbd442SRobert Mustacchi #define IGC_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) 291*6bbbd442SRobert Mustacchi #define IGC_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) 292*6bbbd442SRobert Mustacchi 293*6bbbd442SRobert Mustacchi #define AUTONEG_ADVERTISE_SPEED_DEFAULT IGC_ALL_SPEED_DUPLEX 294*6bbbd442SRobert Mustacchi #define AUTONEG_ADVERTISE_SPEED_DEFAULT_2500 IGC_ALL_SPEED_DUPLEX_2500 295*6bbbd442SRobert Mustacchi 296*6bbbd442SRobert Mustacchi /* LED Control */ 297*6bbbd442SRobert Mustacchi #define IGC_LEDCTL_LED0_MODE_MASK 0x0000000F 298*6bbbd442SRobert Mustacchi #define IGC_LEDCTL_LED0_MODE_SHIFT 0 299*6bbbd442SRobert Mustacchi #define IGC_LEDCTL_LED0_IVRT 0x00000040 300*6bbbd442SRobert Mustacchi #define IGC_LEDCTL_LED0_BLINK 0x00000080 301*6bbbd442SRobert Mustacchi 302*6bbbd442SRobert Mustacchi #define IGC_LEDCTL_MODE_LED_ON 0xE 303*6bbbd442SRobert Mustacchi #define IGC_LEDCTL_MODE_LED_OFF 0xF 304*6bbbd442SRobert Mustacchi 305*6bbbd442SRobert Mustacchi /* Transmit Descriptor bit definitions */ 306*6bbbd442SRobert Mustacchi #define IGC_TXD_DTYP_D 0x00100000 /* Data Descriptor */ 307*6bbbd442SRobert Mustacchi #define IGC_TXD_DTYP_C 0x00000000 /* Context Descriptor */ 308*6bbbd442SRobert Mustacchi #define IGC_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 309*6bbbd442SRobert Mustacchi #define IGC_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 310*6bbbd442SRobert Mustacchi #define IGC_TXD_CMD_EOP 0x01000000 /* End of Packet */ 311*6bbbd442SRobert Mustacchi #define IGC_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 312*6bbbd442SRobert Mustacchi #define IGC_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 313*6bbbd442SRobert Mustacchi #define IGC_TXD_CMD_RS 0x08000000 /* Report Status */ 314*6bbbd442SRobert Mustacchi #define IGC_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ 315*6bbbd442SRobert Mustacchi #define IGC_TXD_CMD_DEXT 0x20000000 /* Desc extension (0 = legacy) */ 316*6bbbd442SRobert Mustacchi #define IGC_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 317*6bbbd442SRobert Mustacchi #define IGC_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ 318*6bbbd442SRobert Mustacchi #define IGC_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 319*6bbbd442SRobert Mustacchi #define IGC_TXD_CMD_TCP 0x01000000 /* TCP packet */ 320*6bbbd442SRobert Mustacchi #define IGC_TXD_CMD_IP 0x02000000 /* IP packet */ 321*6bbbd442SRobert Mustacchi #define IGC_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 322*6bbbd442SRobert Mustacchi #define IGC_TXD_EXTCMD_TSTAMP 0x00000010 /* IEEE1588 Timestamp packet */ 323*6bbbd442SRobert Mustacchi 324*6bbbd442SRobert Mustacchi /* Transmit Control */ 325*6bbbd442SRobert Mustacchi #define IGC_TCTL_EN 0x00000002 /* enable Tx */ 326*6bbbd442SRobert Mustacchi #define IGC_TCTL_PSP 0x00000008 /* pad short packets */ 327*6bbbd442SRobert Mustacchi #define IGC_TCTL_CT 0x00000ff0 /* collision threshold */ 328*6bbbd442SRobert Mustacchi #define IGC_TCTL_COLD 0x003ff000 /* collision distance */ 329*6bbbd442SRobert Mustacchi #define IGC_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 330*6bbbd442SRobert Mustacchi #define IGC_TCTL_MULR 0x10000000 /* Multiple request support */ 331*6bbbd442SRobert Mustacchi 332*6bbbd442SRobert Mustacchi /* Transmit Arbitration Count */ 333*6bbbd442SRobert Mustacchi #define IGC_TARC0_ENABLE 0x00000400 /* Enable Tx Queue 0 */ 334*6bbbd442SRobert Mustacchi 335*6bbbd442SRobert Mustacchi /* SerDes Control */ 336*6bbbd442SRobert Mustacchi #define IGC_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 337*6bbbd442SRobert Mustacchi #define IGC_SCTL_ENABLE_SERDES_LOOPBACK 0x0410 338*6bbbd442SRobert Mustacchi 339*6bbbd442SRobert Mustacchi /* Receive Checksum Control */ 340*6bbbd442SRobert Mustacchi #define IGC_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ 341*6bbbd442SRobert Mustacchi #define IGC_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ 342*6bbbd442SRobert Mustacchi #define IGC_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */ 343*6bbbd442SRobert Mustacchi #define IGC_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ 344*6bbbd442SRobert Mustacchi #define IGC_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 345*6bbbd442SRobert Mustacchi 346*6bbbd442SRobert Mustacchi /* GPY211 - I225 defines */ 347*6bbbd442SRobert Mustacchi #define GPY_MMD_MASK 0xFFFF0000 348*6bbbd442SRobert Mustacchi #define GPY_MMD_SHIFT 16 349*6bbbd442SRobert Mustacchi #define GPY_REG_MASK 0x0000FFFF 350*6bbbd442SRobert Mustacchi /* Header split receive */ 351*6bbbd442SRobert Mustacchi #define IGC_RFCTL_NFSW_DIS 0x00000040 352*6bbbd442SRobert Mustacchi #define IGC_RFCTL_NFSR_DIS 0x00000080 353*6bbbd442SRobert Mustacchi #define IGC_RFCTL_ACK_DIS 0x00001000 354*6bbbd442SRobert Mustacchi #define IGC_RFCTL_EXTEN 0x00008000 355*6bbbd442SRobert Mustacchi #define IGC_RFCTL_IPV6_EX_DIS 0x00010000 356*6bbbd442SRobert Mustacchi #define IGC_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 357*6bbbd442SRobert Mustacchi #define IGC_RFCTL_LEF 0x00040000 358*6bbbd442SRobert Mustacchi 359*6bbbd442SRobert Mustacchi /* Collision related configuration parameters */ 360*6bbbd442SRobert Mustacchi #define IGC_CT_SHIFT 4 361*6bbbd442SRobert Mustacchi #define IGC_COLLISION_THRESHOLD 15 362*6bbbd442SRobert Mustacchi #define IGC_COLLISION_DISTANCE 63 363*6bbbd442SRobert Mustacchi #define IGC_COLD_SHIFT 12 364*6bbbd442SRobert Mustacchi 365*6bbbd442SRobert Mustacchi /* Default values for the transmit IPG register */ 366*6bbbd442SRobert Mustacchi #define DEFAULT_82543_TIPG_IPGT_FIBER 9 367*6bbbd442SRobert Mustacchi #define DEFAULT_82543_TIPG_IPGT_COPPER 8 368*6bbbd442SRobert Mustacchi 369*6bbbd442SRobert Mustacchi #define IGC_TIPG_IPGT_MASK 0x000003FF 370*6bbbd442SRobert Mustacchi 371*6bbbd442SRobert Mustacchi #define DEFAULT_82543_TIPG_IPGR1 8 372*6bbbd442SRobert Mustacchi #define IGC_TIPG_IPGR1_SHIFT 10 373*6bbbd442SRobert Mustacchi 374*6bbbd442SRobert Mustacchi #define DEFAULT_82543_TIPG_IPGR2 6 375*6bbbd442SRobert Mustacchi #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7 376*6bbbd442SRobert Mustacchi #define IGC_TIPG_IPGR2_SHIFT 20 377*6bbbd442SRobert Mustacchi 378*6bbbd442SRobert Mustacchi /* Ethertype field values */ 379*6bbbd442SRobert Mustacchi #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ 380*6bbbd442SRobert Mustacchi 381*6bbbd442SRobert Mustacchi #define ETHERNET_FCS_SIZE 4 382*6bbbd442SRobert Mustacchi #define MAX_JUMBO_FRAME_SIZE MJUM9BYTES 383*6bbbd442SRobert Mustacchi #define IGC_TX_PTR_GAP 0x1F 384*6bbbd442SRobert Mustacchi 385*6bbbd442SRobert Mustacchi /* Extended Configuration Control and Size */ 386*6bbbd442SRobert Mustacchi #define IGC_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 387*6bbbd442SRobert Mustacchi #define IGC_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001 388*6bbbd442SRobert Mustacchi #define IGC_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008 389*6bbbd442SRobert Mustacchi #define IGC_EXTCNF_CTRL_SWFLAG 0x00000020 390*6bbbd442SRobert Mustacchi #define IGC_EXTCNF_CTRL_GATE_PHY_CFG 0x00000080 391*6bbbd442SRobert Mustacchi #define IGC_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000 392*6bbbd442SRobert Mustacchi #define IGC_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16 393*6bbbd442SRobert Mustacchi #define IGC_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000 394*6bbbd442SRobert Mustacchi #define IGC_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16 395*6bbbd442SRobert Mustacchi 396*6bbbd442SRobert Mustacchi #define IGC_PHY_CTRL_D0A_LPLU 0x00000002 397*6bbbd442SRobert Mustacchi #define IGC_PHY_CTRL_NOND0A_LPLU 0x00000004 398*6bbbd442SRobert Mustacchi #define IGC_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008 399*6bbbd442SRobert Mustacchi #define IGC_PHY_CTRL_GBE_DISABLE 0x00000040 400*6bbbd442SRobert Mustacchi 401*6bbbd442SRobert Mustacchi #define IGC_KABGTXD_BGSQLBIAS 0x00050000 402*6bbbd442SRobert Mustacchi 403*6bbbd442SRobert Mustacchi /* PBA constants */ 404*6bbbd442SRobert Mustacchi #define IGC_PBA_8K 0x0008 /* 8KB */ 405*6bbbd442SRobert Mustacchi #define IGC_PBA_10K 0x000A /* 10KB */ 406*6bbbd442SRobert Mustacchi #define IGC_PBA_12K 0x000C /* 12KB */ 407*6bbbd442SRobert Mustacchi #define IGC_PBA_14K 0x000E /* 14KB */ 408*6bbbd442SRobert Mustacchi #define IGC_PBA_16K 0x0010 /* 16KB */ 409*6bbbd442SRobert Mustacchi #define IGC_PBA_18K 0x0012 410*6bbbd442SRobert Mustacchi #define IGC_PBA_20K 0x0014 411*6bbbd442SRobert Mustacchi #define IGC_PBA_22K 0x0016 412*6bbbd442SRobert Mustacchi #define IGC_PBA_24K 0x0018 413*6bbbd442SRobert Mustacchi #define IGC_PBA_26K 0x001A 414*6bbbd442SRobert Mustacchi #define IGC_PBA_30K 0x001E 415*6bbbd442SRobert Mustacchi #define IGC_PBA_32K 0x0020 416*6bbbd442SRobert Mustacchi #define IGC_PBA_34K 0x0022 417*6bbbd442SRobert Mustacchi #define IGC_PBA_35K 0x0023 418*6bbbd442SRobert Mustacchi #define IGC_PBA_38K 0x0026 419*6bbbd442SRobert Mustacchi #define IGC_PBA_40K 0x0028 420*6bbbd442SRobert Mustacchi #define IGC_PBA_48K 0x0030 /* 48KB */ 421*6bbbd442SRobert Mustacchi #define IGC_PBA_64K 0x0040 /* 64KB */ 422*6bbbd442SRobert Mustacchi 423*6bbbd442SRobert Mustacchi #define IGC_PBA_RXA_MASK 0xFFFF 424*6bbbd442SRobert Mustacchi 425*6bbbd442SRobert Mustacchi #define IGC_PBS_16K IGC_PBA_16K 426*6bbbd442SRobert Mustacchi 427*6bbbd442SRobert Mustacchi /* Uncorrectable/correctable ECC Error counts and enable bits */ 428*6bbbd442SRobert Mustacchi #define IGC_PBECCSTS_CORR_ERR_CNT_MASK 0x000000FF 429*6bbbd442SRobert Mustacchi #define IGC_PBECCSTS_UNCORR_ERR_CNT_MASK 0x0000FF00 430*6bbbd442SRobert Mustacchi #define IGC_PBECCSTS_UNCORR_ERR_CNT_SHIFT 8 431*6bbbd442SRobert Mustacchi #define IGC_PBECCSTS_ECC_ENABLE 0x00010000 432*6bbbd442SRobert Mustacchi 433*6bbbd442SRobert Mustacchi #define IFS_MAX 80 434*6bbbd442SRobert Mustacchi #define IFS_MIN 40 435*6bbbd442SRobert Mustacchi #define IFS_RATIO 4 436*6bbbd442SRobert Mustacchi #define IFS_STEP 10 437*6bbbd442SRobert Mustacchi #define MIN_NUM_XMITS 1000 438*6bbbd442SRobert Mustacchi 439*6bbbd442SRobert Mustacchi /* SW Semaphore Register */ 440*6bbbd442SRobert Mustacchi #define IGC_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 441*6bbbd442SRobert Mustacchi #define IGC_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 442*6bbbd442SRobert Mustacchi #define IGC_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ 443*6bbbd442SRobert Mustacchi 444*6bbbd442SRobert Mustacchi #define IGC_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */ 445*6bbbd442SRobert Mustacchi 446*6bbbd442SRobert Mustacchi /* Interrupt Cause Read */ 447*6bbbd442SRobert Mustacchi #define IGC_ICR_TXDW 0x00000001 /* Transmit desc written back */ 448*6bbbd442SRobert Mustacchi #define IGC_ICR_TXQE 0x00000002 /* Transmit Queue empty */ 449*6bbbd442SRobert Mustacchi #define IGC_ICR_LSC 0x00000004 /* Link Status Change */ 450*6bbbd442SRobert Mustacchi #define IGC_ICR_RXSEQ 0x00000008 /* Rx sequence error */ 451*6bbbd442SRobert Mustacchi #define IGC_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */ 452*6bbbd442SRobert Mustacchi #define IGC_ICR_RXO 0x00000040 /* Rx overrun */ 453*6bbbd442SRobert Mustacchi #define IGC_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */ 454*6bbbd442SRobert Mustacchi #define IGC_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */ 455*6bbbd442SRobert Mustacchi #define IGC_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ 456*6bbbd442SRobert Mustacchi #define IGC_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ 457*6bbbd442SRobert Mustacchi #define IGC_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ 458*6bbbd442SRobert Mustacchi #define IGC_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ 459*6bbbd442SRobert Mustacchi #define IGC_ICR_TXD_LOW 0x00008000 460*6bbbd442SRobert Mustacchi #define IGC_ICR_ECCER 0x00400000 /* Uncorrectable ECC Error */ 461*6bbbd442SRobert Mustacchi #define IGC_ICR_TS 0x00080000 /* Time Sync Interrupt */ 462*6bbbd442SRobert Mustacchi #define IGC_ICR_DRSTA 0x40000000 /* Device Reset Asserted */ 463*6bbbd442SRobert Mustacchi /* If this bit asserted, the driver should claim the interrupt */ 464*6bbbd442SRobert Mustacchi #define IGC_ICR_INT_ASSERTED 0x80000000 465*6bbbd442SRobert Mustacchi #define IGC_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */ 466*6bbbd442SRobert Mustacchi #define IGC_ICR_FER 0x00400000 /* Fatal Error */ 467*6bbbd442SRobert Mustacchi 468*6bbbd442SRobert Mustacchi 469*6bbbd442SRobert Mustacchi 470*6bbbd442SRobert Mustacchi /* Extended Interrupt Cause Read */ 471*6bbbd442SRobert Mustacchi #define IGC_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */ 472*6bbbd442SRobert Mustacchi #define IGC_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */ 473*6bbbd442SRobert Mustacchi #define IGC_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */ 474*6bbbd442SRobert Mustacchi #define IGC_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */ 475*6bbbd442SRobert Mustacchi #define IGC_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */ 476*6bbbd442SRobert Mustacchi #define IGC_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */ 477*6bbbd442SRobert Mustacchi #define IGC_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */ 478*6bbbd442SRobert Mustacchi #define IGC_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */ 479*6bbbd442SRobert Mustacchi #define IGC_EICR_TCP_TIMER 0x40000000 /* TCP Timer */ 480*6bbbd442SRobert Mustacchi #define IGC_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ 481*6bbbd442SRobert Mustacchi /* TCP Timer */ 482*6bbbd442SRobert Mustacchi #define IGC_TCPTIMER_KS 0x00000100 /* KickStart */ 483*6bbbd442SRobert Mustacchi #define IGC_TCPTIMER_COUNT_ENABLE 0x00000200 /* Count Enable */ 484*6bbbd442SRobert Mustacchi #define IGC_TCPTIMER_COUNT_FINISH 0x00000400 /* Count finish */ 485*6bbbd442SRobert Mustacchi #define IGC_TCPTIMER_LOOP 0x00000800 /* Loop */ 486*6bbbd442SRobert Mustacchi 487*6bbbd442SRobert Mustacchi /* This defines the bits that are set in the Interrupt Mask 488*6bbbd442SRobert Mustacchi * Set/Read Register. Each bit is documented below: 489*6bbbd442SRobert Mustacchi * o RXT0 = Receiver Timer Interrupt (ring 0) 490*6bbbd442SRobert Mustacchi * o TXDW = Transmit Descriptor Written Back 491*6bbbd442SRobert Mustacchi * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 492*6bbbd442SRobert Mustacchi * o RXSEQ = Receive Sequence Error 493*6bbbd442SRobert Mustacchi * o LSC = Link Status Change 494*6bbbd442SRobert Mustacchi */ 495*6bbbd442SRobert Mustacchi #define IMS_ENABLE_MASK ( \ 496*6bbbd442SRobert Mustacchi IGC_IMS_RXT0 | \ 497*6bbbd442SRobert Mustacchi IGC_IMS_TXDW | \ 498*6bbbd442SRobert Mustacchi IGC_IMS_RXDMT0 | \ 499*6bbbd442SRobert Mustacchi IGC_IMS_RXSEQ | \ 500*6bbbd442SRobert Mustacchi IGC_IMS_LSC) 501*6bbbd442SRobert Mustacchi 502*6bbbd442SRobert Mustacchi /* Interrupt Mask Set */ 503*6bbbd442SRobert Mustacchi #define IGC_IMS_TXDW IGC_ICR_TXDW /* Tx desc written back */ 504*6bbbd442SRobert Mustacchi #define IGC_IMS_LSC IGC_ICR_LSC /* Link Status Change */ 505*6bbbd442SRobert Mustacchi #define IGC_IMS_RXSEQ IGC_ICR_RXSEQ /* Rx sequence error */ 506*6bbbd442SRobert Mustacchi #define IGC_IMS_RXDMT0 IGC_ICR_RXDMT0 /* Rx desc min. threshold */ 507*6bbbd442SRobert Mustacchi #define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */ 508*6bbbd442SRobert Mustacchi #define IGC_ITR_VAL_MASK 0x04 /* ITR value mask */ 509*6bbbd442SRobert Mustacchi #define IGC_IMS_RXO IGC_ICR_RXO /* Rx overrun */ 510*6bbbd442SRobert Mustacchi #define IGC_IMS_RXT0 IGC_ICR_RXT0 /* Rx timer intr */ 511*6bbbd442SRobert Mustacchi #define IGC_IMS_TXD_LOW IGC_ICR_TXD_LOW 512*6bbbd442SRobert Mustacchi #define IGC_IMS_ECCER IGC_ICR_ECCER /* Uncorrectable ECC Error */ 513*6bbbd442SRobert Mustacchi #define IGC_IMS_TS IGC_ICR_TS /* Time Sync Interrupt */ 514*6bbbd442SRobert Mustacchi #define IGC_IMS_DRSTA IGC_ICR_DRSTA /* Device Reset Asserted */ 515*6bbbd442SRobert Mustacchi #define IGC_IMS_DOUTSYNC IGC_ICR_DOUTSYNC /* NIC DMA out of sync */ 516*6bbbd442SRobert Mustacchi #define IGC_IMS_FER IGC_ICR_FER /* Fatal Error */ 517*6bbbd442SRobert Mustacchi 518*6bbbd442SRobert Mustacchi #define IGC_IMS_THS IGC_ICR_THS /* ICR.TS: Thermal Sensor Event*/ 519*6bbbd442SRobert Mustacchi #define IGC_IMS_MDDET IGC_ICR_MDDET /* Malicious Driver Detect */ 520*6bbbd442SRobert Mustacchi /* Extended Interrupt Mask Set */ 521*6bbbd442SRobert Mustacchi #define IGC_EIMS_RX_QUEUE0 IGC_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */ 522*6bbbd442SRobert Mustacchi #define IGC_EIMS_RX_QUEUE1 IGC_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */ 523*6bbbd442SRobert Mustacchi #define IGC_EIMS_RX_QUEUE2 IGC_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */ 524*6bbbd442SRobert Mustacchi #define IGC_EIMS_RX_QUEUE3 IGC_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */ 525*6bbbd442SRobert Mustacchi #define IGC_EIMS_TX_QUEUE0 IGC_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */ 526*6bbbd442SRobert Mustacchi #define IGC_EIMS_TX_QUEUE1 IGC_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */ 527*6bbbd442SRobert Mustacchi #define IGC_EIMS_TX_QUEUE2 IGC_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */ 528*6bbbd442SRobert Mustacchi #define IGC_EIMS_TX_QUEUE3 IGC_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */ 529*6bbbd442SRobert Mustacchi #define IGC_EIMS_TCP_TIMER IGC_EICR_TCP_TIMER /* TCP Timer */ 530*6bbbd442SRobert Mustacchi #define IGC_EIMS_OTHER IGC_EICR_OTHER /* Interrupt Cause Active */ 531*6bbbd442SRobert Mustacchi 532*6bbbd442SRobert Mustacchi /* Interrupt Cause Set */ 533*6bbbd442SRobert Mustacchi #define IGC_ICS_LSC IGC_ICR_LSC /* Link Status Change */ 534*6bbbd442SRobert Mustacchi #define IGC_ICS_RXSEQ IGC_ICR_RXSEQ /* Rx sequence error */ 535*6bbbd442SRobert Mustacchi #define IGC_ICS_RXDMT0 IGC_ICR_RXDMT0 /* Rx desc min. threshold */ 536*6bbbd442SRobert Mustacchi 537*6bbbd442SRobert Mustacchi /* Extended Interrupt Cause Set */ 538*6bbbd442SRobert Mustacchi #define IGC_EICS_RX_QUEUE0 IGC_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */ 539*6bbbd442SRobert Mustacchi #define IGC_EICS_RX_QUEUE1 IGC_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */ 540*6bbbd442SRobert Mustacchi #define IGC_EICS_RX_QUEUE2 IGC_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */ 541*6bbbd442SRobert Mustacchi #define IGC_EICS_RX_QUEUE3 IGC_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */ 542*6bbbd442SRobert Mustacchi #define IGC_EICS_TX_QUEUE0 IGC_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */ 543*6bbbd442SRobert Mustacchi #define IGC_EICS_TX_QUEUE1 IGC_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */ 544*6bbbd442SRobert Mustacchi #define IGC_EICS_TX_QUEUE2 IGC_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */ 545*6bbbd442SRobert Mustacchi #define IGC_EICS_TX_QUEUE3 IGC_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */ 546*6bbbd442SRobert Mustacchi #define IGC_EICS_TCP_TIMER IGC_EICR_TCP_TIMER /* TCP Timer */ 547*6bbbd442SRobert Mustacchi #define IGC_EICS_OTHER IGC_EICR_OTHER /* Interrupt Cause Active */ 548*6bbbd442SRobert Mustacchi 549*6bbbd442SRobert Mustacchi #define IGC_EITR_ITR_INT_MASK 0x0000FFFF 550*6bbbd442SRobert Mustacchi #define IGC_EITR_INTERVAL 0x00007FFC 551*6bbbd442SRobert Mustacchi /* IGC_EITR_CNT_IGNR is only for 82576 and newer */ 552*6bbbd442SRobert Mustacchi #define IGC_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */ 553*6bbbd442SRobert Mustacchi 554*6bbbd442SRobert Mustacchi /* Transmit Descriptor Control */ 555*6bbbd442SRobert Mustacchi #define IGC_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */ 556*6bbbd442SRobert Mustacchi #define IGC_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */ 557*6bbbd442SRobert Mustacchi #define IGC_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ 558*6bbbd442SRobert Mustacchi #define IGC_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ 559*6bbbd442SRobert Mustacchi #define IGC_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ 560*6bbbd442SRobert Mustacchi #define IGC_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */ 561*6bbbd442SRobert Mustacchi /* Enable the counting of descriptors still to be processed. */ 562*6bbbd442SRobert Mustacchi #define IGC_TXDCTL_COUNT_DESC 0x00400000 563*6bbbd442SRobert Mustacchi 564*6bbbd442SRobert Mustacchi /* Flow Control Constants */ 565*6bbbd442SRobert Mustacchi #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 566*6bbbd442SRobert Mustacchi #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 567*6bbbd442SRobert Mustacchi #define FLOW_CONTROL_TYPE 0x8808 568*6bbbd442SRobert Mustacchi 569*6bbbd442SRobert Mustacchi /* 802.1q VLAN Packet Size */ 570*6bbbd442SRobert Mustacchi #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */ 571*6bbbd442SRobert Mustacchi #define IGC_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 572*6bbbd442SRobert Mustacchi 573*6bbbd442SRobert Mustacchi /* Receive Address 574*6bbbd442SRobert Mustacchi * Number of high/low register pairs in the RAR. The RAR (Receive Address 575*6bbbd442SRobert Mustacchi * Registers) holds the directed and multicast addresses that we monitor. 576*6bbbd442SRobert Mustacchi * Technically, we have 16 spots. However, we reserve one of these spots 577*6bbbd442SRobert Mustacchi * (RAR[15]) for our directed address used by controllers with 578*6bbbd442SRobert Mustacchi * manageability enabled, allowing us room for 15 multicast addresses. 579*6bbbd442SRobert Mustacchi */ 580*6bbbd442SRobert Mustacchi #define IGC_RAR_ENTRIES 15 581*6bbbd442SRobert Mustacchi #define IGC_RAH_AV 0x80000000 /* Receive descriptor valid */ 582*6bbbd442SRobert Mustacchi #define IGC_RAL_MAC_ADDR_LEN 4 583*6bbbd442SRobert Mustacchi #define IGC_RAH_MAC_ADDR_LEN 2 584*6bbbd442SRobert Mustacchi 585*6bbbd442SRobert Mustacchi /* Error Codes */ 586*6bbbd442SRobert Mustacchi #define IGC_SUCCESS 0 587*6bbbd442SRobert Mustacchi #define IGC_ERR_NVM 1 588*6bbbd442SRobert Mustacchi #define IGC_ERR_PHY 2 589*6bbbd442SRobert Mustacchi #define IGC_ERR_CONFIG 3 590*6bbbd442SRobert Mustacchi #define IGC_ERR_PARAM 4 591*6bbbd442SRobert Mustacchi #define IGC_ERR_MAC_INIT 5 592*6bbbd442SRobert Mustacchi #define IGC_ERR_PHY_TYPE 6 593*6bbbd442SRobert Mustacchi #define IGC_ERR_RESET 9 594*6bbbd442SRobert Mustacchi #define IGC_ERR_MASTER_REQUESTS_PENDING 10 595*6bbbd442SRobert Mustacchi #define IGC_ERR_HOST_INTERFACE_COMMAND 11 596*6bbbd442SRobert Mustacchi #define IGC_BLK_PHY_RESET 12 597*6bbbd442SRobert Mustacchi #define IGC_ERR_SWFW_SYNC 13 598*6bbbd442SRobert Mustacchi #define IGC_NOT_IMPLEMENTED 14 599*6bbbd442SRobert Mustacchi #define IGC_ERR_MBX 15 600*6bbbd442SRobert Mustacchi #define IGC_ERR_INVALID_ARGUMENT 16 601*6bbbd442SRobert Mustacchi #define IGC_ERR_NO_SPACE 17 602*6bbbd442SRobert Mustacchi #define IGC_ERR_NVM_PBA_SECTION 18 603*6bbbd442SRobert Mustacchi #define IGC_ERR_INVM_VALUE_NOT_FOUND 20 604*6bbbd442SRobert Mustacchi 605*6bbbd442SRobert Mustacchi /* Loop limit on how long we wait for auto-negotiation to complete */ 606*6bbbd442SRobert Mustacchi #define COPPER_LINK_UP_LIMIT 10 607*6bbbd442SRobert Mustacchi #define PHY_AUTO_NEG_LIMIT 45 608*6bbbd442SRobert Mustacchi /* Number of 100 microseconds we wait for PCI Express master disable */ 609*6bbbd442SRobert Mustacchi #define MASTER_DISABLE_TIMEOUT 800 610*6bbbd442SRobert Mustacchi /* Number of milliseconds we wait for PHY configuration done after MAC reset */ 611*6bbbd442SRobert Mustacchi #define PHY_CFG_TIMEOUT 100 612*6bbbd442SRobert Mustacchi /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */ 613*6bbbd442SRobert Mustacchi #define MDIO_OWNERSHIP_TIMEOUT 10 614*6bbbd442SRobert Mustacchi /* Number of milliseconds for NVM auto read done after MAC reset. */ 615*6bbbd442SRobert Mustacchi #define AUTO_READ_DONE_TIMEOUT 10 616*6bbbd442SRobert Mustacchi 617*6bbbd442SRobert Mustacchi /* Flow Control */ 618*6bbbd442SRobert Mustacchi #define IGC_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ 619*6bbbd442SRobert Mustacchi #define IGC_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ 620*6bbbd442SRobert Mustacchi #define IGC_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 621*6bbbd442SRobert Mustacchi 622*6bbbd442SRobert Mustacchi /* Transmit Configuration Word */ 623*6bbbd442SRobert Mustacchi #define IGC_TXCW_FD 0x00000020 /* TXCW full duplex */ 624*6bbbd442SRobert Mustacchi #define IGC_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ 625*6bbbd442SRobert Mustacchi #define IGC_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ 626*6bbbd442SRobert Mustacchi #define IGC_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ 627*6bbbd442SRobert Mustacchi #define IGC_TXCW_ANE 0x80000000 /* Auto-neg enable */ 628*6bbbd442SRobert Mustacchi 629*6bbbd442SRobert Mustacchi /* Receive Configuration Word */ 630*6bbbd442SRobert Mustacchi #define IGC_RXCW_CW 0x0000ffff /* RxConfigWord mask */ 631*6bbbd442SRobert Mustacchi #define IGC_RXCW_IV 0x08000000 /* Receive config invalid */ 632*6bbbd442SRobert Mustacchi #define IGC_RXCW_C 0x20000000 /* Receive config */ 633*6bbbd442SRobert Mustacchi #define IGC_RXCW_SYNCH 0x40000000 /* Receive config synch */ 634*6bbbd442SRobert Mustacchi 635*6bbbd442SRobert Mustacchi #define IGC_TSYNCTXCTL_TXTT_0 0x00000001 /* Tx timestamp reg 0 valid */ 636*6bbbd442SRobert Mustacchi #define IGC_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */ 637*6bbbd442SRobert Mustacchi 638*6bbbd442SRobert Mustacchi #define IGC_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */ 639*6bbbd442SRobert Mustacchi #define IGC_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */ 640*6bbbd442SRobert Mustacchi #define IGC_TSYNCRXCTL_TYPE_L2_V2 0x00 641*6bbbd442SRobert Mustacchi #define IGC_TSYNCRXCTL_TYPE_L4_V1 0x02 642*6bbbd442SRobert Mustacchi #define IGC_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 643*6bbbd442SRobert Mustacchi #define IGC_TSYNCRXCTL_TYPE_ALL 0x08 644*6bbbd442SRobert Mustacchi #define IGC_TSYNCRXCTL_TYPE_EVENT_V2 0x0A 645*6bbbd442SRobert Mustacchi #define IGC_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */ 646*6bbbd442SRobert Mustacchi #define IGC_TSYNCRXCTL_SYSCFI 0x00000020 /* Sys clock frequency */ 647*6bbbd442SRobert Mustacchi 648*6bbbd442SRobert Mustacchi #define IGC_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF 649*6bbbd442SRobert Mustacchi #define IGC_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00 650*6bbbd442SRobert Mustacchi #define IGC_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE 0x01 651*6bbbd442SRobert Mustacchi #define IGC_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE 0x02 652*6bbbd442SRobert Mustacchi #define IGC_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE 0x03 653*6bbbd442SRobert Mustacchi #define IGC_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE 0x04 654*6bbbd442SRobert Mustacchi 655*6bbbd442SRobert Mustacchi #define IGC_TSYNCRXCFG_PTP_V2_MSGID_MASK 0x00000F00 656*6bbbd442SRobert Mustacchi #define IGC_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE 0x0000 657*6bbbd442SRobert Mustacchi #define IGC_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE 0x0100 658*6bbbd442SRobert Mustacchi #define IGC_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE 0x0200 659*6bbbd442SRobert Mustacchi #define IGC_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE 0x0300 660*6bbbd442SRobert Mustacchi #define IGC_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE 0x0800 661*6bbbd442SRobert Mustacchi #define IGC_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE 0x0900 662*6bbbd442SRobert Mustacchi #define IGC_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE 0x0A00 663*6bbbd442SRobert Mustacchi #define IGC_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE 0x0B00 664*6bbbd442SRobert Mustacchi #define IGC_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE 0x0C00 665*6bbbd442SRobert Mustacchi #define IGC_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE 0x0D00 666*6bbbd442SRobert Mustacchi 667*6bbbd442SRobert Mustacchi #define IGC_TIMINCA_16NS_SHIFT 24 668*6bbbd442SRobert Mustacchi #define IGC_TIMINCA_INCPERIOD_SHIFT 24 669*6bbbd442SRobert Mustacchi #define IGC_TIMINCA_INCVALUE_MASK 0x00FFFFFF 670*6bbbd442SRobert Mustacchi 671*6bbbd442SRobert Mustacchi /* Time Sync Interrupt Cause/Mask Register Bits */ 672*6bbbd442SRobert Mustacchi #define TSINTR_SYS_WRAP (1 << 0) /* SYSTIM Wrap around. */ 673*6bbbd442SRobert Mustacchi #define TSINTR_TXTS (1 << 1) /* Transmit Timestamp. */ 674*6bbbd442SRobert Mustacchi #define TSINTR_TT0 (1 << 3) /* Target Time 0 Trigger. */ 675*6bbbd442SRobert Mustacchi #define TSINTR_TT1 (1 << 4) /* Target Time 1 Trigger. */ 676*6bbbd442SRobert Mustacchi #define TSINTR_AUTT0 (1 << 5) /* Auxiliary Timestamp 0 Taken. */ 677*6bbbd442SRobert Mustacchi #define TSINTR_AUTT1 (1 << 6) /* Auxiliary Timestamp 1 Taken. */ 678*6bbbd442SRobert Mustacchi 679*6bbbd442SRobert Mustacchi #define TSYNC_INTERRUPTS TSINTR_TXTS 680*6bbbd442SRobert Mustacchi 681*6bbbd442SRobert Mustacchi /* TSAUXC Configuration Bits */ 682*6bbbd442SRobert Mustacchi #define TSAUXC_EN_TT0 (1 << 0) /* Enable target time 0. */ 683*6bbbd442SRobert Mustacchi #define TSAUXC_EN_TT1 (1 << 1) /* Enable target time 1. */ 684*6bbbd442SRobert Mustacchi #define TSAUXC_EN_CLK0 (1 << 2) /* Enable Configurable Frequency Clock 0. */ 685*6bbbd442SRobert Mustacchi #define TSAUXC_ST0 (1 << 4) /* Start Clock 0 Toggle on Target Time 0. */ 686*6bbbd442SRobert Mustacchi #define TSAUXC_EN_CLK1 (1 << 5) /* Enable Configurable Frequency Clock 1. */ 687*6bbbd442SRobert Mustacchi #define TSAUXC_ST1 (1 << 7) /* Start Clock 1 Toggle on Target Time 1. */ 688*6bbbd442SRobert Mustacchi #define TSAUXC_EN_TS0 (1 << 8) /* Enable hardware timestamp 0. */ 689*6bbbd442SRobert Mustacchi #define TSAUXC_EN_TS1 (1 << 10) /* Enable hardware timestamp 0. */ 690*6bbbd442SRobert Mustacchi 691*6bbbd442SRobert Mustacchi /* SDP Configuration Bits */ 692*6bbbd442SRobert Mustacchi #define AUX0_SEL_SDP0 (0u << 0) /* Assign SDP0 to auxiliary time stamp 0. */ 693*6bbbd442SRobert Mustacchi #define AUX0_SEL_SDP1 (1u << 0) /* Assign SDP1 to auxiliary time stamp 0. */ 694*6bbbd442SRobert Mustacchi #define AUX0_SEL_SDP2 (2u << 0) /* Assign SDP2 to auxiliary time stamp 0. */ 695*6bbbd442SRobert Mustacchi #define AUX0_SEL_SDP3 (3u << 0) /* Assign SDP3 to auxiliary time stamp 0. */ 696*6bbbd442SRobert Mustacchi #define AUX0_TS_SDP_EN (1u << 2) /* Enable auxiliary time stamp trigger 0. */ 697*6bbbd442SRobert Mustacchi #define AUX1_SEL_SDP0 (0u << 3) /* Assign SDP0 to auxiliary time stamp 1. */ 698*6bbbd442SRobert Mustacchi #define AUX1_SEL_SDP1 (1u << 3) /* Assign SDP1 to auxiliary time stamp 1. */ 699*6bbbd442SRobert Mustacchi #define AUX1_SEL_SDP2 (2u << 3) /* Assign SDP2 to auxiliary time stamp 1. */ 700*6bbbd442SRobert Mustacchi #define AUX1_SEL_SDP3 (3u << 3) /* Assign SDP3 to auxiliary time stamp 1. */ 701*6bbbd442SRobert Mustacchi #define AUX1_TS_SDP_EN (1u << 5) /* Enable auxiliary time stamp trigger 1. */ 702*6bbbd442SRobert Mustacchi #define TS_SDP0_EN (1u << 8) /* SDP0 is assigned to Tsync. */ 703*6bbbd442SRobert Mustacchi #define TS_SDP1_EN (1u << 11) /* SDP1 is assigned to Tsync. */ 704*6bbbd442SRobert Mustacchi #define TS_SDP2_EN (1u << 14) /* SDP2 is assigned to Tsync. */ 705*6bbbd442SRobert Mustacchi #define TS_SDP3_EN (1u << 17) /* SDP3 is assigned to Tsync. */ 706*6bbbd442SRobert Mustacchi #define TS_SDP0_SEL_TT0 (0u << 6) /* Target time 0 is output on SDP0. */ 707*6bbbd442SRobert Mustacchi #define TS_SDP0_SEL_TT1 (1u << 6) /* Target time 1 is output on SDP0. */ 708*6bbbd442SRobert Mustacchi #define TS_SDP1_SEL_TT0 (0u << 9) /* Target time 0 is output on SDP1. */ 709*6bbbd442SRobert Mustacchi #define TS_SDP1_SEL_TT1 (1u << 9) /* Target time 1 is output on SDP1. */ 710*6bbbd442SRobert Mustacchi #define TS_SDP0_SEL_FC0 (2u << 6) /* Freq clock 0 is output on SDP0. */ 711*6bbbd442SRobert Mustacchi #define TS_SDP0_SEL_FC1 (3u << 6) /* Freq clock 1 is output on SDP0. */ 712*6bbbd442SRobert Mustacchi #define TS_SDP1_SEL_FC0 (2u << 9) /* Freq clock 0 is output on SDP1. */ 713*6bbbd442SRobert Mustacchi #define TS_SDP1_SEL_FC1 (3u << 9) /* Freq clock 1 is output on SDP1. */ 714*6bbbd442SRobert Mustacchi #define TS_SDP2_SEL_TT0 (0u << 12) /* Target time 0 is output on SDP2. */ 715*6bbbd442SRobert Mustacchi #define TS_SDP2_SEL_TT1 (1u << 12) /* Target time 1 is output on SDP2. */ 716*6bbbd442SRobert Mustacchi #define TS_SDP2_SEL_FC0 (2u << 12) /* Freq clock 0 is output on SDP2. */ 717*6bbbd442SRobert Mustacchi #define TS_SDP2_SEL_FC1 (3u << 12) /* Freq clock 1 is output on SDP2. */ 718*6bbbd442SRobert Mustacchi #define TS_SDP3_SEL_TT0 (0u << 15) /* Target time 0 is output on SDP3. */ 719*6bbbd442SRobert Mustacchi #define TS_SDP3_SEL_TT1 (1u << 15) /* Target time 1 is output on SDP3. */ 720*6bbbd442SRobert Mustacchi #define TS_SDP3_SEL_FC0 (2u << 15) /* Freq clock 0 is output on SDP3. */ 721*6bbbd442SRobert Mustacchi #define TS_SDP3_SEL_FC1 (3u << 15) /* Freq clock 1 is output on SDP3. */ 722*6bbbd442SRobert Mustacchi 723*6bbbd442SRobert Mustacchi #define IGC_CTRL_SDP0_DIR 0x00400000 /* SDP0 Data direction */ 724*6bbbd442SRobert Mustacchi #define IGC_CTRL_SDP1_DIR 0x00800000 /* SDP1 Data direction */ 725*6bbbd442SRobert Mustacchi 726*6bbbd442SRobert Mustacchi /* Extended Device Control */ 727*6bbbd442SRobert Mustacchi #define IGC_CTRL_EXT_SDP2_DIR 0x00000400 /* SDP2 Data direction */ 728*6bbbd442SRobert Mustacchi 729*6bbbd442SRobert Mustacchi /* ETQF register bit definitions */ 730*6bbbd442SRobert Mustacchi #define IGC_ETQF_1588 (1 << 30) 731*6bbbd442SRobert Mustacchi #define IGC_FTQF_VF_BP 0x00008000 732*6bbbd442SRobert Mustacchi #define IGC_FTQF_1588_TIME_STAMP 0x08000000 733*6bbbd442SRobert Mustacchi #define IGC_FTQF_MASK 0xF0000000 734*6bbbd442SRobert Mustacchi #define IGC_FTQF_MASK_PROTO_BP 0x10000000 735*6bbbd442SRobert Mustacchi /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */ 736*6bbbd442SRobert Mustacchi #define IGC_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of ctrl bits */ 737*6bbbd442SRobert Mustacchi #define IGC_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */ 738*6bbbd442SRobert Mustacchi 739*6bbbd442SRobert Mustacchi #define IGC_RXDADV_STAT_TSIP 0x08000 /* timestamp in packet */ 740*6bbbd442SRobert Mustacchi #define IGC_TSICR_TXTS 0x00000002 741*6bbbd442SRobert Mustacchi #define IGC_TSIM_TXTS 0x00000002 742*6bbbd442SRobert Mustacchi /* TUPLE Filtering Configuration */ 743*6bbbd442SRobert Mustacchi #define IGC_TTQF_DISABLE_MASK 0xF0008000 /* TTQF Disable Mask */ 744*6bbbd442SRobert Mustacchi #define IGC_TTQF_QUEUE_ENABLE 0x100 /* TTQF Queue Enable Bit */ 745*6bbbd442SRobert Mustacchi #define IGC_TTQF_PROTOCOL_MASK 0xFF /* TTQF Protocol Mask */ 746*6bbbd442SRobert Mustacchi /* TTQF TCP Bit, shift with IGC_TTQF_PROTOCOL SHIFT */ 747*6bbbd442SRobert Mustacchi #define IGC_TTQF_PROTOCOL_TCP 0x0 748*6bbbd442SRobert Mustacchi /* TTQF UDP Bit, shift with IGC_TTQF_PROTOCOL_SHIFT */ 749*6bbbd442SRobert Mustacchi #define IGC_TTQF_PROTOCOL_UDP 0x1 750*6bbbd442SRobert Mustacchi /* TTQF SCTP Bit, shift with IGC_TTQF_PROTOCOL_SHIFT */ 751*6bbbd442SRobert Mustacchi #define IGC_TTQF_PROTOCOL_SCTP 0x2 752*6bbbd442SRobert Mustacchi #define IGC_TTQF_PROTOCOL_SHIFT 5 /* TTQF Protocol Shift */ 753*6bbbd442SRobert Mustacchi #define IGC_TTQF_QUEUE_SHIFT 16 /* TTQF Queue Shfit */ 754*6bbbd442SRobert Mustacchi #define IGC_TTQF_RX_QUEUE_MASK 0x70000 /* TTQF Queue Mask */ 755*6bbbd442SRobert Mustacchi #define IGC_TTQF_MASK_ENABLE 0x10000000 /* TTQF Mask Enable Bit */ 756*6bbbd442SRobert Mustacchi #define IGC_IMIR_CLEAR_MASK 0xF001FFFF /* IMIR Reg Clear Mask */ 757*6bbbd442SRobert Mustacchi #define IGC_IMIR_PORT_BYPASS 0x20000 /* IMIR Port Bypass Bit */ 758*6bbbd442SRobert Mustacchi #define IGC_IMIR_PRIORITY_SHIFT 29 /* IMIR Priority Shift */ 759*6bbbd442SRobert Mustacchi #define IGC_IMIREXT_CLEAR_MASK 0x7FFFF /* IMIREXT Reg Clear Mask */ 760*6bbbd442SRobert Mustacchi 761*6bbbd442SRobert Mustacchi #define IGC_MDICNFG_EXT_MDIO 0x80000000 /* MDI ext/int destination */ 762*6bbbd442SRobert Mustacchi #define IGC_MDICNFG_COM_MDIO 0x40000000 /* MDI shared w/ lan 0 */ 763*6bbbd442SRobert Mustacchi #define IGC_MDICNFG_PHY_MASK 0x03E00000 764*6bbbd442SRobert Mustacchi #define IGC_MDICNFG_PHY_SHIFT 21 765*6bbbd442SRobert Mustacchi 766*6bbbd442SRobert Mustacchi #define IGC_MEDIA_PORT_COPPER 1 767*6bbbd442SRobert Mustacchi #define IGC_MEDIA_PORT_OTHER 2 768*6bbbd442SRobert Mustacchi #define IGC_M88E1112_AUTO_COPPER_SGMII 0x2 769*6bbbd442SRobert Mustacchi #define IGC_M88E1112_AUTO_COPPER_BASEX 0x3 770*6bbbd442SRobert Mustacchi #define IGC_M88E1112_STATUS_LINK 0x0004 /* Interface Link Bit */ 771*6bbbd442SRobert Mustacchi #define IGC_M88E1112_MAC_CTRL_1 0x10 772*6bbbd442SRobert Mustacchi #define IGC_M88E1112_MAC_CTRL_1_MODE_MASK 0x0380 /* Mode Select */ 773*6bbbd442SRobert Mustacchi #define IGC_M88E1112_MAC_CTRL_1_MODE_SHIFT 7 774*6bbbd442SRobert Mustacchi #define IGC_M88E1112_PAGE_ADDR 0x16 775*6bbbd442SRobert Mustacchi #define IGC_M88E1112_STATUS 0x01 776*6bbbd442SRobert Mustacchi 777*6bbbd442SRobert Mustacchi #define IGC_THSTAT_LOW_EVENT 0x20000000 /* Low thermal threshold */ 778*6bbbd442SRobert Mustacchi #define IGC_THSTAT_MID_EVENT 0x00200000 /* Mid thermal threshold */ 779*6bbbd442SRobert Mustacchi #define IGC_THSTAT_HIGH_EVENT 0x00002000 /* High thermal threshold */ 780*6bbbd442SRobert Mustacchi #define IGC_THSTAT_PWR_DOWN 0x00000001 /* Power Down Event */ 781*6bbbd442SRobert Mustacchi #define IGC_THSTAT_LINK_THROTTLE 0x00000002 /* Link Spd Throttle Event */ 782*6bbbd442SRobert Mustacchi 783*6bbbd442SRobert Mustacchi /* EEE defines */ 784*6bbbd442SRobert Mustacchi #define IGC_IPCNFG_EEE_2_5G_AN 0x00000010 /* IPCNFG EEE Ena 2.5G AN */ 785*6bbbd442SRobert Mustacchi #define IGC_IPCNFG_EEE_1G_AN 0x00000008 /* IPCNFG EEE Ena 1G AN */ 786*6bbbd442SRobert Mustacchi #define IGC_IPCNFG_EEE_100M_AN 0x00000004 /* IPCNFG EEE Ena 100M AN */ 787*6bbbd442SRobert Mustacchi #define IGC_EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */ 788*6bbbd442SRobert Mustacchi #define IGC_EEER_RX_LPI_EN 0x00020000 /* EEER Rx LPI Enable */ 789*6bbbd442SRobert Mustacchi #define IGC_EEER_LPI_FC 0x00040000 /* EEER Ena on Flow Cntrl */ 790*6bbbd442SRobert Mustacchi /* EEE status */ 791*6bbbd442SRobert Mustacchi #define IGC_EEER_EEE_NEG 0x20000000 /* EEE capability nego */ 792*6bbbd442SRobert Mustacchi #define IGC_EEER_RX_LPI_STATUS 0x40000000 /* Rx in LPI state */ 793*6bbbd442SRobert Mustacchi #define IGC_EEER_TX_LPI_STATUS 0x80000000 /* Tx in LPI state */ 794*6bbbd442SRobert Mustacchi #define IGC_EEE_LP_ADV_ADDR_I350 0x040F /* EEE LP Advertisement */ 795*6bbbd442SRobert Mustacchi #define IGC_M88E1543_PAGE_ADDR 0x16 /* Page Offset Register */ 796*6bbbd442SRobert Mustacchi #define IGC_M88E1543_EEE_CTRL_1 0x0 797*6bbbd442SRobert Mustacchi #define IGC_M88E1543_EEE_CTRL_1_MS 0x0001 /* EEE Master/Slave */ 798*6bbbd442SRobert Mustacchi #define IGC_M88E1543_FIBER_CTRL 0x0 /* Fiber Control Register */ 799*6bbbd442SRobert Mustacchi #define IGC_EEE_ADV_DEV_I354 7 800*6bbbd442SRobert Mustacchi #define IGC_EEE_ADV_ADDR_I354 60 801*6bbbd442SRobert Mustacchi #define IGC_EEE_ADV_100_SUPPORTED (1 << 1) /* 100BaseTx EEE Supported */ 802*6bbbd442SRobert Mustacchi #define IGC_EEE_ADV_1000_SUPPORTED (1 << 2) /* 1000BaseT EEE Supported */ 803*6bbbd442SRobert Mustacchi #define IGC_PCS_STATUS_DEV_I354 3 804*6bbbd442SRobert Mustacchi #define IGC_PCS_STATUS_ADDR_I354 1 805*6bbbd442SRobert Mustacchi #define IGC_PCS_STATUS_RX_LPI_RCVD 0x0400 806*6bbbd442SRobert Mustacchi #define IGC_PCS_STATUS_TX_LPI_RCVD 0x0800 807*6bbbd442SRobert Mustacchi #define IGC_M88E1512_CFG_REG_1 0x0010 808*6bbbd442SRobert Mustacchi #define IGC_M88E1512_CFG_REG_2 0x0011 809*6bbbd442SRobert Mustacchi #define IGC_M88E1512_CFG_REG_3 0x0007 810*6bbbd442SRobert Mustacchi #define IGC_M88E1512_MODE 0x0014 811*6bbbd442SRobert Mustacchi #define IGC_EEE_SU_LPI_CLK_STP 0x00800000 /* EEE LPI Clock Stop */ 812*6bbbd442SRobert Mustacchi #define IGC_EEE_LP_ADV_DEV_I225 7 /* EEE LP Adv Device */ 813*6bbbd442SRobert Mustacchi #define IGC_EEE_LP_ADV_ADDR_I225 61 /* EEE LP Adv Register */ 814*6bbbd442SRobert Mustacchi 815*6bbbd442SRobert Mustacchi #define IGC_MMDAC_FUNC_DATA 0x4000 /* Data, no post increment */ 816*6bbbd442SRobert Mustacchi 817*6bbbd442SRobert Mustacchi /* PHY Control Register */ 818*6bbbd442SRobert Mustacchi #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ 819*6bbbd442SRobert Mustacchi #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ 820*6bbbd442SRobert Mustacchi #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 821*6bbbd442SRobert Mustacchi #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 822*6bbbd442SRobert Mustacchi #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ 823*6bbbd442SRobert Mustacchi #define MII_CR_POWER_DOWN 0x0800 /* Power down */ 824*6bbbd442SRobert Mustacchi #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 825*6bbbd442SRobert Mustacchi #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ 826*6bbbd442SRobert Mustacchi #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ 827*6bbbd442SRobert Mustacchi #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ 828*6bbbd442SRobert Mustacchi #define MII_CR_SPEED_1000 0x0040 829*6bbbd442SRobert Mustacchi #define MII_CR_SPEED_100 0x2000 830*6bbbd442SRobert Mustacchi #define MII_CR_SPEED_10 0x0000 831*6bbbd442SRobert Mustacchi 832*6bbbd442SRobert Mustacchi /* PHY Status Register */ 833*6bbbd442SRobert Mustacchi #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ 834*6bbbd442SRobert Mustacchi #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ 835*6bbbd442SRobert Mustacchi #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ 836*6bbbd442SRobert Mustacchi #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ 837*6bbbd442SRobert Mustacchi #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ 838*6bbbd442SRobert Mustacchi #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ 839*6bbbd442SRobert Mustacchi #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ 840*6bbbd442SRobert Mustacchi #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ 841*6bbbd442SRobert Mustacchi #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ 842*6bbbd442SRobert Mustacchi #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ 843*6bbbd442SRobert Mustacchi #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ 844*6bbbd442SRobert Mustacchi #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ 845*6bbbd442SRobert Mustacchi #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ 846*6bbbd442SRobert Mustacchi #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ 847*6bbbd442SRobert Mustacchi #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ 848*6bbbd442SRobert Mustacchi 849*6bbbd442SRobert Mustacchi /* Autoneg Advertisement Register */ 850*6bbbd442SRobert Mustacchi #define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ 851*6bbbd442SRobert Mustacchi #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ 852*6bbbd442SRobert Mustacchi #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ 853*6bbbd442SRobert Mustacchi #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ 854*6bbbd442SRobert Mustacchi #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ 855*6bbbd442SRobert Mustacchi #define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ 856*6bbbd442SRobert Mustacchi #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ 857*6bbbd442SRobert Mustacchi #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ 858*6bbbd442SRobert Mustacchi #define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ 859*6bbbd442SRobert Mustacchi #define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */ 860*6bbbd442SRobert Mustacchi 861*6bbbd442SRobert Mustacchi /* Link Partner Ability Register (Base Page) */ 862*6bbbd442SRobert Mustacchi #define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */ 863*6bbbd442SRobert Mustacchi #define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP 10T Half Dplx Capable */ 864*6bbbd442SRobert Mustacchi #define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP 10T Full Dplx Capable */ 865*6bbbd442SRobert Mustacchi #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP 100TX Half Dplx Capable */ 866*6bbbd442SRobert Mustacchi #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP 100TX Full Dplx Capable */ 867*6bbbd442SRobert Mustacchi #define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */ 868*6bbbd442SRobert Mustacchi #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ 869*6bbbd442SRobert Mustacchi #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asym Pause Direction bit */ 870*6bbbd442SRobert Mustacchi #define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP detected Remote Fault */ 871*6bbbd442SRobert Mustacchi #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP rx'd link code word */ 872*6bbbd442SRobert Mustacchi #define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */ 873*6bbbd442SRobert Mustacchi 874*6bbbd442SRobert Mustacchi /* Autoneg Expansion Register */ 875*6bbbd442SRobert Mustacchi #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ 876*6bbbd442SRobert Mustacchi #define NWAY_ER_PAGE_RXD 0x0002 /* LP 10T Half Dplx Capable */ 877*6bbbd442SRobert Mustacchi #define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP 10T Full Dplx Capable */ 878*6bbbd442SRobert Mustacchi #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP 100TX Half Dplx Capable */ 879*6bbbd442SRobert Mustacchi #define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP 100TX Full Dplx Capable */ 880*6bbbd442SRobert Mustacchi 881*6bbbd442SRobert Mustacchi /* 1000BASE-T Control Register */ 882*6bbbd442SRobert Mustacchi #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */ 883*6bbbd442SRobert Mustacchi #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ 884*6bbbd442SRobert Mustacchi #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ 885*6bbbd442SRobert Mustacchi /* 1=Repeater/switch device port 0=DTE device */ 886*6bbbd442SRobert Mustacchi #define CR_1000T_REPEATER_DTE 0x0400 887*6bbbd442SRobert Mustacchi /* 1=Configure PHY as Master 0=Configure PHY as Slave */ 888*6bbbd442SRobert Mustacchi #define CR_1000T_MS_VALUE 0x0800 889*6bbbd442SRobert Mustacchi /* 1=Master/Slave manual config value 0=Automatic Master/Slave config */ 890*6bbbd442SRobert Mustacchi #define CR_1000T_MS_ENABLE 0x1000 891*6bbbd442SRobert Mustacchi #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ 892*6bbbd442SRobert Mustacchi #define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ 893*6bbbd442SRobert Mustacchi #define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ 894*6bbbd442SRobert Mustacchi #define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ 895*6bbbd442SRobert Mustacchi #define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ 896*6bbbd442SRobert Mustacchi 897*6bbbd442SRobert Mustacchi /* 1000BASE-T Status Register */ 898*6bbbd442SRobert Mustacchi #define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle err since last rd */ 899*6bbbd442SRobert Mustacchi #define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asym pause direction bit */ 900*6bbbd442SRobert Mustacchi #define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ 901*6bbbd442SRobert Mustacchi #define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ 902*6bbbd442SRobert Mustacchi #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ 903*6bbbd442SRobert Mustacchi #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ 904*6bbbd442SRobert Mustacchi #define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local Tx Master, 0=Slave */ 905*6bbbd442SRobert Mustacchi #define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ 906*6bbbd442SRobert Mustacchi 907*6bbbd442SRobert Mustacchi #define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5 908*6bbbd442SRobert Mustacchi 909*6bbbd442SRobert Mustacchi /* PHY 1000 MII Register/Bit Definitions */ 910*6bbbd442SRobert Mustacchi /* PHY Registers defined by IEEE */ 911*6bbbd442SRobert Mustacchi #define PHY_CONTROL 0x00 /* Control Register */ 912*6bbbd442SRobert Mustacchi #define PHY_STATUS 0x01 /* Status Register */ 913*6bbbd442SRobert Mustacchi #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ 914*6bbbd442SRobert Mustacchi #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ 915*6bbbd442SRobert Mustacchi #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ 916*6bbbd442SRobert Mustacchi #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ 917*6bbbd442SRobert Mustacchi #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ 918*6bbbd442SRobert Mustacchi #define PHY_NEXT_PAGE_TX 0x07 /* Next Page Tx */ 919*6bbbd442SRobert Mustacchi #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ 920*6bbbd442SRobert Mustacchi #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ 921*6bbbd442SRobert Mustacchi #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ 922*6bbbd442SRobert Mustacchi #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ 923*6bbbd442SRobert Mustacchi 924*6bbbd442SRobert Mustacchi /* PHY GPY 211 registers */ 925*6bbbd442SRobert Mustacchi #define STANDARD_AN_REG_MASK 0x0007 /* MMD */ 926*6bbbd442SRobert Mustacchi #define ANEG_MULTIGBT_AN_CTRL 0x0020 /* MULTI GBT AN Control Register */ 927*6bbbd442SRobert Mustacchi #define MMD_DEVADDR_SHIFT 16 /* Shift MMD to higher bits */ 928*6bbbd442SRobert Mustacchi #define CR_2500T_FD_CAPS 0x0080 /* Advertise 2500T FD capability */ 929*6bbbd442SRobert Mustacchi 930*6bbbd442SRobert Mustacchi #define PHY_CONTROL_LB 0x4000 /* PHY Loopback bit */ 931*6bbbd442SRobert Mustacchi 932*6bbbd442SRobert Mustacchi /* NVM Control */ 933*6bbbd442SRobert Mustacchi #define IGC_EECD_SK 0x00000001 /* NVM Clock */ 934*6bbbd442SRobert Mustacchi #define IGC_EECD_CS 0x00000002 /* NVM Chip Select */ 935*6bbbd442SRobert Mustacchi #define IGC_EECD_DI 0x00000004 /* NVM Data In */ 936*6bbbd442SRobert Mustacchi #define IGC_EECD_DO 0x00000008 /* NVM Data Out */ 937*6bbbd442SRobert Mustacchi #define IGC_EECD_REQ 0x00000040 /* NVM Access Request */ 938*6bbbd442SRobert Mustacchi #define IGC_EECD_GNT 0x00000080 /* NVM Access Grant */ 939*6bbbd442SRobert Mustacchi #define IGC_EECD_PRES 0x00000100 /* NVM Present */ 940*6bbbd442SRobert Mustacchi #define IGC_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */ 941*6bbbd442SRobert Mustacchi /* NVM Addressing bits based on type 0=small, 1=large */ 942*6bbbd442SRobert Mustacchi #define IGC_EECD_ADDR_BITS 0x00000400 943*6bbbd442SRobert Mustacchi #define IGC_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ 944*6bbbd442SRobert Mustacchi #define IGC_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ 945*6bbbd442SRobert Mustacchi #define IGC_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ 946*6bbbd442SRobert Mustacchi #define IGC_EECD_SIZE_EX_SHIFT 11 947*6bbbd442SRobert Mustacchi #define IGC_EECD_FLUPD 0x00080000 /* Update FLASH */ 948*6bbbd442SRobert Mustacchi #define IGC_EECD_AUPDEN 0x00100000 /* Ena Auto FLASH update */ 949*6bbbd442SRobert Mustacchi #define IGC_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ 950*6bbbd442SRobert Mustacchi #define IGC_EECD_SEC1VAL_VALID_MASK (IGC_EECD_AUTO_RD | IGC_EECD_PRES) 951*6bbbd442SRobert Mustacchi 952*6bbbd442SRobert Mustacchi #define IGC_EECD_FLUPD_I225 0x00800000 /* Update FLASH */ 953*6bbbd442SRobert Mustacchi #define IGC_EECD_FLUDONE_I225 0x04000000 /* Update FLASH done */ 954*6bbbd442SRobert Mustacchi #define IGC_EECD_FLASH_DETECTED_I225 0x00080000 /* FLASH detected */ 955*6bbbd442SRobert Mustacchi #define IGC_FLUDONE_ATTEMPTS 20000 956*6bbbd442SRobert Mustacchi #define IGC_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */ 957*6bbbd442SRobert Mustacchi #define IGC_EECD_SEC1VAL_I225 0x02000000 /* Sector One Valid */ 958*6bbbd442SRobert Mustacchi #define IGC_FLSECU_BLK_SW_ACCESS_I225 0x00000004 /* Block SW access */ 959*6bbbd442SRobert Mustacchi #define IGC_FWSM_FW_VALID_I225 0x8000 /* FW valid bit */ 960*6bbbd442SRobert Mustacchi 961*6bbbd442SRobert Mustacchi #define IGC_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write regs */ 962*6bbbd442SRobert Mustacchi #define IGC_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ 963*6bbbd442SRobert Mustacchi #define IGC_NVM_RW_REG_START 1 /* Start operation */ 964*6bbbd442SRobert Mustacchi #define IGC_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 965*6bbbd442SRobert Mustacchi #define IGC_NVM_POLL_WRITE 1 /* Flag for polling for write complete */ 966*6bbbd442SRobert Mustacchi #define IGC_NVM_POLL_READ 0 /* Flag for polling for read complete */ 967*6bbbd442SRobert Mustacchi #define IGC_FLASH_UPDATES 2000 968*6bbbd442SRobert Mustacchi 969*6bbbd442SRobert Mustacchi /* NVM Word Offsets */ 970*6bbbd442SRobert Mustacchi #define NVM_COMPAT 0x0003 971*6bbbd442SRobert Mustacchi #define NVM_ID_LED_SETTINGS 0x0004 972*6bbbd442SRobert Mustacchi #define NVM_FUTURE_INIT_WORD1 0x0019 973*6bbbd442SRobert Mustacchi #define NVM_COMPAT_VALID_CSUM 0x0001 974*6bbbd442SRobert Mustacchi #define NVM_FUTURE_INIT_WORD1_VALID_CSUM 0x0040 975*6bbbd442SRobert Mustacchi 976*6bbbd442SRobert Mustacchi #define NVM_INIT_CONTROL2_REG 0x000F 977*6bbbd442SRobert Mustacchi #define NVM_INIT_CONTROL3_PORT_B 0x0014 978*6bbbd442SRobert Mustacchi #define NVM_INIT_3GIO_3 0x001A 979*6bbbd442SRobert Mustacchi #define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020 980*6bbbd442SRobert Mustacchi #define NVM_INIT_CONTROL3_PORT_A 0x0024 981*6bbbd442SRobert Mustacchi #define NVM_CFG 0x0012 982*6bbbd442SRobert Mustacchi #define NVM_ALT_MAC_ADDR_PTR 0x0037 983*6bbbd442SRobert Mustacchi #define NVM_CHECKSUM_REG 0x003F 984*6bbbd442SRobert Mustacchi 985*6bbbd442SRobert Mustacchi #define IGC_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */ 986*6bbbd442SRobert Mustacchi #define IGC_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */ 987*6bbbd442SRobert Mustacchi 988*6bbbd442SRobert Mustacchi /* Mask bits for fields in Word 0x0f of the NVM */ 989*6bbbd442SRobert Mustacchi #define NVM_WORD0F_PAUSE_MASK 0x3000 990*6bbbd442SRobert Mustacchi #define NVM_WORD0F_PAUSE 0x1000 991*6bbbd442SRobert Mustacchi #define NVM_WORD0F_ASM_DIR 0x2000 992*6bbbd442SRobert Mustacchi 993*6bbbd442SRobert Mustacchi /* Mask bits for fields in Word 0x1a of the NVM */ 994*6bbbd442SRobert Mustacchi #define NVM_WORD1A_ASPM_MASK 0x000C 995*6bbbd442SRobert Mustacchi 996*6bbbd442SRobert Mustacchi /* Mask bits for fields in Word 0x03 of the EEPROM */ 997*6bbbd442SRobert Mustacchi #define NVM_COMPAT_LOM 0x0800 998*6bbbd442SRobert Mustacchi 999*6bbbd442SRobert Mustacchi /* length of string needed to store PBA number */ 1000*6bbbd442SRobert Mustacchi #define IGC_PBANUM_LENGTH 11 1001*6bbbd442SRobert Mustacchi 1002*6bbbd442SRobert Mustacchi /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ 1003*6bbbd442SRobert Mustacchi #define NVM_SUM 0xBABA 1004*6bbbd442SRobert Mustacchi 1005*6bbbd442SRobert Mustacchi /* PBA (printed board assembly) number words */ 1006*6bbbd442SRobert Mustacchi #define NVM_PBA_OFFSET_0 8 1007*6bbbd442SRobert Mustacchi #define NVM_PBA_OFFSET_1 9 1008*6bbbd442SRobert Mustacchi #define NVM_PBA_PTR_GUARD 0xFAFA 1009*6bbbd442SRobert Mustacchi #define NVM_WORD_SIZE_BASE_SHIFT 6 1010*6bbbd442SRobert Mustacchi 1011*6bbbd442SRobert Mustacchi /* NVM Commands - Microwire */ 1012*6bbbd442SRobert Mustacchi #define NVM_READ_OPCODE_MICROWIRE 0x6 /* NVM read opcode */ 1013*6bbbd442SRobert Mustacchi #define NVM_WRITE_OPCODE_MICROWIRE 0x5 /* NVM write opcode */ 1014*6bbbd442SRobert Mustacchi #define NVM_ERASE_OPCODE_MICROWIRE 0x7 /* NVM erase opcode */ 1015*6bbbd442SRobert Mustacchi #define NVM_EWEN_OPCODE_MICROWIRE 0x13 /* NVM erase/write enable */ 1016*6bbbd442SRobert Mustacchi #define NVM_EWDS_OPCODE_MICROWIRE 0x10 /* NVM erase/write disable */ 1017*6bbbd442SRobert Mustacchi 1018*6bbbd442SRobert Mustacchi /* NVM Commands - SPI */ 1019*6bbbd442SRobert Mustacchi #define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ 1020*6bbbd442SRobert Mustacchi #define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */ 1021*6bbbd442SRobert Mustacchi #define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */ 1022*6bbbd442SRobert Mustacchi #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ 1023*6bbbd442SRobert Mustacchi #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */ 1024*6bbbd442SRobert Mustacchi #define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */ 1025*6bbbd442SRobert Mustacchi 1026*6bbbd442SRobert Mustacchi /* SPI NVM Status Register */ 1027*6bbbd442SRobert Mustacchi #define NVM_STATUS_RDY_SPI 0x01 1028*6bbbd442SRobert Mustacchi 1029*6bbbd442SRobert Mustacchi /* Word definitions for ID LED Settings */ 1030*6bbbd442SRobert Mustacchi #define ID_LED_RESERVED_0000 0x0000 1031*6bbbd442SRobert Mustacchi #define ID_LED_RESERVED_FFFF 0xFFFF 1032*6bbbd442SRobert Mustacchi #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ 1033*6bbbd442SRobert Mustacchi (ID_LED_OFF1_OFF2 << 8) | \ 1034*6bbbd442SRobert Mustacchi (ID_LED_DEF1_DEF2 << 4) | \ 1035*6bbbd442SRobert Mustacchi (ID_LED_DEF1_DEF2)) 1036*6bbbd442SRobert Mustacchi #define ID_LED_DEF1_DEF2 0x1 1037*6bbbd442SRobert Mustacchi #define ID_LED_DEF1_ON2 0x2 1038*6bbbd442SRobert Mustacchi #define ID_LED_DEF1_OFF2 0x3 1039*6bbbd442SRobert Mustacchi #define ID_LED_ON1_DEF2 0x4 1040*6bbbd442SRobert Mustacchi #define ID_LED_ON1_ON2 0x5 1041*6bbbd442SRobert Mustacchi #define ID_LED_ON1_OFF2 0x6 1042*6bbbd442SRobert Mustacchi #define ID_LED_OFF1_DEF2 0x7 1043*6bbbd442SRobert Mustacchi #define ID_LED_OFF1_ON2 0x8 1044*6bbbd442SRobert Mustacchi #define ID_LED_OFF1_OFF2 0x9 1045*6bbbd442SRobert Mustacchi 1046*6bbbd442SRobert Mustacchi #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF 1047*6bbbd442SRobert Mustacchi #define IGP_ACTIVITY_LED_ENABLE 0x0300 1048*6bbbd442SRobert Mustacchi #define IGP_LED3_MODE 0x07000000 1049*6bbbd442SRobert Mustacchi 1050*6bbbd442SRobert Mustacchi /* PCI/PCI-X/PCI-EX Config space */ 1051*6bbbd442SRobert Mustacchi #define PCIX_COMMAND_REGISTER 0xE6 1052*6bbbd442SRobert Mustacchi #define PCIX_STATUS_REGISTER_LO 0xE8 1053*6bbbd442SRobert Mustacchi #define PCIX_STATUS_REGISTER_HI 0xEA 1054*6bbbd442SRobert Mustacchi #define PCI_HEADER_TYPE_REGISTER 0x0E 1055*6bbbd442SRobert Mustacchi #define PCIE_LINK_STATUS 0x12 1056*6bbbd442SRobert Mustacchi 1057*6bbbd442SRobert Mustacchi #define PCIX_COMMAND_MMRBC_MASK 0x000C 1058*6bbbd442SRobert Mustacchi #define PCIX_COMMAND_MMRBC_SHIFT 0x2 1059*6bbbd442SRobert Mustacchi #define PCIX_STATUS_HI_MMRBC_MASK 0x0060 1060*6bbbd442SRobert Mustacchi #define PCIX_STATUS_HI_MMRBC_SHIFT 0x5 1061*6bbbd442SRobert Mustacchi #define PCIX_STATUS_HI_MMRBC_4K 0x3 1062*6bbbd442SRobert Mustacchi #define PCIX_STATUS_HI_MMRBC_2K 0x2 1063*6bbbd442SRobert Mustacchi #define PCIX_STATUS_LO_FUNC_MASK 0x7 1064*6bbbd442SRobert Mustacchi #define PCI_HEADER_TYPE_MULTIFUNC 0x80 1065*6bbbd442SRobert Mustacchi #define PCIE_LINK_WIDTH_MASK 0x3F0 1066*6bbbd442SRobert Mustacchi #define PCIE_LINK_WIDTH_SHIFT 4 1067*6bbbd442SRobert Mustacchi #define PCIE_LINK_SPEED_MASK 0x0F 1068*6bbbd442SRobert Mustacchi #define PCIE_LINK_SPEED_2500 0x01 1069*6bbbd442SRobert Mustacchi #define PCIE_LINK_SPEED_5000 0x02 1070*6bbbd442SRobert Mustacchi 1071*6bbbd442SRobert Mustacchi #ifndef ETH_ADDR_LEN 1072*6bbbd442SRobert Mustacchi #define ETH_ADDR_LEN 6 1073*6bbbd442SRobert Mustacchi #endif 1074*6bbbd442SRobert Mustacchi 1075*6bbbd442SRobert Mustacchi #define PHY_REVISION_MASK 0xFFFFFFF0 1076*6bbbd442SRobert Mustacchi #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 1077*6bbbd442SRobert Mustacchi #define MAX_PHY_MULTI_PAGE_REG 0xF 1078*6bbbd442SRobert Mustacchi 1079*6bbbd442SRobert Mustacchi /* Bit definitions for valid PHY IDs. 1080*6bbbd442SRobert Mustacchi * I = Integrated 1081*6bbbd442SRobert Mustacchi * E = External 1082*6bbbd442SRobert Mustacchi */ 1083*6bbbd442SRobert Mustacchi #define M88IGC_E_PHY_ID 0x01410C50 1084*6bbbd442SRobert Mustacchi #define M88IGC_I_PHY_ID 0x01410C30 1085*6bbbd442SRobert Mustacchi #define M88E1011_I_PHY_ID 0x01410C20 1086*6bbbd442SRobert Mustacchi #define IGP01IGC_I_PHY_ID 0x02A80380 1087*6bbbd442SRobert Mustacchi #define M88E1111_I_PHY_ID 0x01410CC0 1088*6bbbd442SRobert Mustacchi #define GG82563_E_PHY_ID 0x01410CA0 1089*6bbbd442SRobert Mustacchi #define IGP03IGC_E_PHY_ID 0x02A80390 1090*6bbbd442SRobert Mustacchi #define IFE_E_PHY_ID 0x02A80330 1091*6bbbd442SRobert Mustacchi #define IFE_PLUS_E_PHY_ID 0x02A80320 1092*6bbbd442SRobert Mustacchi #define IFE_C_E_PHY_ID 0x02A80310 1093*6bbbd442SRobert Mustacchi #define I225_I_PHY_ID 0x67C9DC00 1094*6bbbd442SRobert Mustacchi 1095*6bbbd442SRobert Mustacchi /* M88IGC Specific Registers */ 1096*6bbbd442SRobert Mustacchi #define M88IGC_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Reg */ 1097*6bbbd442SRobert Mustacchi #define M88IGC_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Reg */ 1098*6bbbd442SRobert Mustacchi #define M88IGC_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Cntrl */ 1099*6bbbd442SRobert Mustacchi #define M88IGC_RX_ERR_CNTR 0x15 /* Receive Error Counter */ 1100*6bbbd442SRobert Mustacchi 1101*6bbbd442SRobert Mustacchi #define M88IGC_PHY_PAGE_SELECT 0x1D /* Reg 29 for pg number setting */ 1102*6bbbd442SRobert Mustacchi #define M88IGC_PHY_GEN_CONTROL 0x1E /* meaning depends on reg 29 */ 1103*6bbbd442SRobert Mustacchi 1104*6bbbd442SRobert Mustacchi /* M88IGC PHY Specific Control Register */ 1105*6bbbd442SRobert Mustacchi #define M88IGC_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reverse enabled */ 1106*6bbbd442SRobert Mustacchi /* MDI Crossover Mode bits 6:5 Manual MDI configuration */ 1107*6bbbd442SRobert Mustacchi #define M88IGC_PSCR_MDI_MANUAL_MODE 0x0000 1108*6bbbd442SRobert Mustacchi #define M88IGC_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ 1109*6bbbd442SRobert Mustacchi /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ 1110*6bbbd442SRobert Mustacchi #define M88IGC_PSCR_AUTO_X_1000T 0x0040 1111*6bbbd442SRobert Mustacchi /* Auto crossover enabled all speeds */ 1112*6bbbd442SRobert Mustacchi #define M88IGC_PSCR_AUTO_X_MODE 0x0060 1113*6bbbd442SRobert Mustacchi #define M88IGC_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Tx */ 1114*6bbbd442SRobert Mustacchi 1115*6bbbd442SRobert Mustacchi /* M88IGC PHY Specific Status Register */ 1116*6bbbd442SRobert Mustacchi #define M88IGC_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ 1117*6bbbd442SRobert Mustacchi #define M88IGC_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ 1118*6bbbd442SRobert Mustacchi #define M88IGC_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ 1119*6bbbd442SRobert Mustacchi /* 0 = <50M 1120*6bbbd442SRobert Mustacchi * 1 = 50-80M 1121*6bbbd442SRobert Mustacchi * 2 = 80-110M 1122*6bbbd442SRobert Mustacchi * 3 = 110-140M 1123*6bbbd442SRobert Mustacchi * 4 = >140M 1124*6bbbd442SRobert Mustacchi */ 1125*6bbbd442SRobert Mustacchi #define M88IGC_PSSR_CABLE_LENGTH 0x0380 1126*6bbbd442SRobert Mustacchi #define M88IGC_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */ 1127*6bbbd442SRobert Mustacchi #define M88IGC_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ 1128*6bbbd442SRobert Mustacchi #define M88IGC_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ 1129*6bbbd442SRobert Mustacchi #define M88IGC_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ 1130*6bbbd442SRobert Mustacchi 1131*6bbbd442SRobert Mustacchi #define M88IGC_PSSR_CABLE_LENGTH_SHIFT 7 1132*6bbbd442SRobert Mustacchi 1133*6bbbd442SRobert Mustacchi /* Number of times we will attempt to autonegotiate before downshifting if we 1134*6bbbd442SRobert Mustacchi * are the master 1135*6bbbd442SRobert Mustacchi */ 1136*6bbbd442SRobert Mustacchi #define M88IGC_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 1137*6bbbd442SRobert Mustacchi #define M88IGC_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 1138*6bbbd442SRobert Mustacchi /* Number of times we will attempt to autonegotiate before downshifting if we 1139*6bbbd442SRobert Mustacchi * are the slave 1140*6bbbd442SRobert Mustacchi */ 1141*6bbbd442SRobert Mustacchi #define M88IGC_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 1142*6bbbd442SRobert Mustacchi #define M88IGC_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 1143*6bbbd442SRobert Mustacchi #define M88IGC_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ 1144*6bbbd442SRobert Mustacchi 1145*6bbbd442SRobert Mustacchi 1146*6bbbd442SRobert Mustacchi /* M88EC018 Rev 2 specific DownShift settings */ 1147*6bbbd442SRobert Mustacchi #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 1148*6bbbd442SRobert Mustacchi #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 1149*6bbbd442SRobert Mustacchi 1150*6bbbd442SRobert Mustacchi /* Bits... 1151*6bbbd442SRobert Mustacchi * 15-5: page 1152*6bbbd442SRobert Mustacchi * 4-0: register offset 1153*6bbbd442SRobert Mustacchi */ 1154*6bbbd442SRobert Mustacchi #define GG82563_PAGE_SHIFT 5 1155*6bbbd442SRobert Mustacchi #define GG82563_REG(page, reg) \ 1156*6bbbd442SRobert Mustacchi (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) 1157*6bbbd442SRobert Mustacchi #define GG82563_MIN_ALT_REG 30 1158*6bbbd442SRobert Mustacchi 1159*6bbbd442SRobert Mustacchi /* GG82563 Specific Registers */ 1160*6bbbd442SRobert Mustacchi #define GG82563_PHY_SPEC_CTRL GG82563_REG(0, 16) /* PHY Spec Cntrl */ 1161*6bbbd442SRobert Mustacchi #define GG82563_PHY_PAGE_SELECT GG82563_REG(0, 22) /* Page Select */ 1162*6bbbd442SRobert Mustacchi #define GG82563_PHY_SPEC_CTRL_2 GG82563_REG(0, 26) /* PHY Spec Cntrl2 */ 1163*6bbbd442SRobert Mustacchi #define GG82563_PHY_PAGE_SELECT_ALT GG82563_REG(0, 29) /* Alt Page Select */ 1164*6bbbd442SRobert Mustacchi 1165*6bbbd442SRobert Mustacchi /* MAC Specific Control Register */ 1166*6bbbd442SRobert Mustacchi #define GG82563_PHY_MAC_SPEC_CTRL GG82563_REG(2, 21) 1167*6bbbd442SRobert Mustacchi 1168*6bbbd442SRobert Mustacchi #define GG82563_PHY_DSP_DISTANCE GG82563_REG(5, 26) /* DSP Distance */ 1169*6bbbd442SRobert Mustacchi 1170*6bbbd442SRobert Mustacchi /* Page 193 - Port Control Registers */ 1171*6bbbd442SRobert Mustacchi /* Kumeran Mode Control */ 1172*6bbbd442SRobert Mustacchi #define GG82563_PHY_KMRN_MODE_CTRL GG82563_REG(193, 16) 1173*6bbbd442SRobert Mustacchi #define GG82563_PHY_PWR_MGMT_CTRL GG82563_REG(193, 20) /* Pwr Mgt Ctrl */ 1174*6bbbd442SRobert Mustacchi 1175*6bbbd442SRobert Mustacchi /* Page 194 - KMRN Registers */ 1176*6bbbd442SRobert Mustacchi #define GG82563_PHY_INBAND_CTRL GG82563_REG(194, 18) /* Inband Ctrl */ 1177*6bbbd442SRobert Mustacchi 1178*6bbbd442SRobert Mustacchi /* MDI Control */ 1179*6bbbd442SRobert Mustacchi #define IGC_MDIC_DATA_MASK 0x0000FFFF 1180*6bbbd442SRobert Mustacchi #define IGC_MDIC_INT_EN 0x20000000 1181*6bbbd442SRobert Mustacchi #define IGC_MDIC_REG_MASK 0x001F0000 1182*6bbbd442SRobert Mustacchi #define IGC_MDIC_REG_SHIFT 16 1183*6bbbd442SRobert Mustacchi #define IGC_MDIC_PHY_SHIFT 21 1184*6bbbd442SRobert Mustacchi #define IGC_MDIC_OP_WRITE 0x04000000 1185*6bbbd442SRobert Mustacchi #define IGC_MDIC_OP_READ 0x08000000 1186*6bbbd442SRobert Mustacchi #define IGC_MDIC_READY 0x10000000 1187*6bbbd442SRobert Mustacchi #define IGC_MDIC_ERROR 0x40000000 1188*6bbbd442SRobert Mustacchi 1189*6bbbd442SRobert Mustacchi #define IGC_N0_QUEUE -1 1190*6bbbd442SRobert Mustacchi 1191*6bbbd442SRobert Mustacchi #define IGC_MAX_MAC_HDR_LEN 127 1192*6bbbd442SRobert Mustacchi #define IGC_MAX_NETWORK_HDR_LEN 511 1193*6bbbd442SRobert Mustacchi 1194*6bbbd442SRobert Mustacchi #define IGC_VLANPQF_QUEUE_SEL(_n, q_idx) ((q_idx) << ((_n) * 4)) 1195*6bbbd442SRobert Mustacchi #define IGC_VLANPQF_P_VALID(_n) (0x1 << (3 + (_n) * 4)) 1196*6bbbd442SRobert Mustacchi #define IGC_VLANPQF_QUEUE_MASK 0x03 1197*6bbbd442SRobert Mustacchi #define IGC_VFTA_BLOCK_SIZE 8 1198*6bbbd442SRobert Mustacchi /* SerDes Control */ 1199*6bbbd442SRobert Mustacchi #define IGC_GEN_POLL_TIMEOUT 640 1200*6bbbd442SRobert Mustacchi 1201*6bbbd442SRobert Mustacchi /* DMA Coalescing register fields */ 1202*6bbbd442SRobert Mustacchi /* DMA Coalescing Watchdog Timer */ 1203*6bbbd442SRobert Mustacchi #define IGC_DMACR_DMACWT_MASK 0x00003FFF 1204*6bbbd442SRobert Mustacchi /* DMA Coalescing Rx Threshold */ 1205*6bbbd442SRobert Mustacchi #define IGC_DMACR_DMACTHR_MASK 0x00FF0000 1206*6bbbd442SRobert Mustacchi #define IGC_DMACR_DMACTHR_SHIFT 16 1207*6bbbd442SRobert Mustacchi /* Lx when no PCIe transactions */ 1208*6bbbd442SRobert Mustacchi #define IGC_DMACR_DMAC_LX_MASK 0x30000000 1209*6bbbd442SRobert Mustacchi #define IGC_DMACR_DMAC_LX_SHIFT 28 1210*6bbbd442SRobert Mustacchi #define IGC_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */ 1211*6bbbd442SRobert Mustacchi /* DMA Coalescing BMC-to-OS Watchdog Enable */ 1212*6bbbd442SRobert Mustacchi #define IGC_DMACR_DC_BMC2OSW_EN 0x00008000 1213*6bbbd442SRobert Mustacchi 1214*6bbbd442SRobert Mustacchi /* DMA Coalescing Transmit Threshold */ 1215*6bbbd442SRobert Mustacchi #define IGC_DMCTXTH_DMCTTHR_MASK 0x00000FFF 1216*6bbbd442SRobert Mustacchi 1217*6bbbd442SRobert Mustacchi #define IGC_DMCTLX_TTLX_MASK 0x00000FFF /* Time to LX request */ 1218*6bbbd442SRobert Mustacchi 1219*6bbbd442SRobert Mustacchi /* Rx Traffic Rate Threshold */ 1220*6bbbd442SRobert Mustacchi #define IGC_DMCRTRH_UTRESH_MASK 0x0007FFFF 1221*6bbbd442SRobert Mustacchi /* Rx packet rate in current window */ 1222*6bbbd442SRobert Mustacchi #define IGC_DMCRTRH_LRPRCW 0x80000000 1223*6bbbd442SRobert Mustacchi 1224*6bbbd442SRobert Mustacchi /* DMA Coal Rx Traffic Current Count */ 1225*6bbbd442SRobert Mustacchi #define IGC_DMCCNT_CCOUNT_MASK 0x01FFFFFF 1226*6bbbd442SRobert Mustacchi 1227*6bbbd442SRobert Mustacchi /* Flow ctrl Rx Threshold High val */ 1228*6bbbd442SRobert Mustacchi #define IGC_FCRTC_RTH_COAL_MASK 0x0003FFF0 1229*6bbbd442SRobert Mustacchi #define IGC_FCRTC_RTH_COAL_SHIFT 4 1230*6bbbd442SRobert Mustacchi /* Lx power decision based on DMA coal */ 1231*6bbbd442SRobert Mustacchi #define IGC_PCIEMISC_LX_DECISION 0x00000080 1232*6bbbd442SRobert Mustacchi 1233*6bbbd442SRobert Mustacchi #define IGC_RXPBS_CFG_TS_EN 0x80000000 /* Timestamp in Rx buffer */ 1234*6bbbd442SRobert Mustacchi #define IGC_RXPBS_SIZE_I210_MASK 0x0000003F /* Rx packet buffer size */ 1235*6bbbd442SRobert Mustacchi #define IGC_TXPB0S_SIZE_I210_MASK 0x0000003F /* Tx packet buffer 0 size */ 1236*6bbbd442SRobert Mustacchi #define I210_RXPBSIZE_DEFAULT 0x000000A2 /* RXPBSIZE default */ 1237*6bbbd442SRobert Mustacchi #define I210_TXPBSIZE_DEFAULT 0x04000014 /* TXPBSIZE default */ 1238*6bbbd442SRobert Mustacchi 1239*6bbbd442SRobert Mustacchi #define IGC_LTRC_EEEMS_EN 0x00000020 /* Enable EEE LTR max send */ 1240*6bbbd442SRobert Mustacchi /* Minimum time for 1000BASE-T where no data will be transmit following move out 1241*6bbbd442SRobert Mustacchi * of EEE LPI Tx state 1242*6bbbd442SRobert Mustacchi */ 1243*6bbbd442SRobert Mustacchi #define IGC_TW_SYSTEM_1000_MASK 0x000000FF 1244*6bbbd442SRobert Mustacchi /* Minimum time for 100BASE-T where no data will be transmit following move out 1245*6bbbd442SRobert Mustacchi * of EEE LPI Tx state 1246*6bbbd442SRobert Mustacchi */ 1247*6bbbd442SRobert Mustacchi #define IGC_TW_SYSTEM_100_MASK 0x0000FF00 1248*6bbbd442SRobert Mustacchi #define IGC_TW_SYSTEM_100_SHIFT 8 1249*6bbbd442SRobert Mustacchi #define IGC_LTRMINV_LTRV_MASK 0x000003FF /* LTR minimum value */ 1250*6bbbd442SRobert Mustacchi #define IGC_LTRMAXV_LTRV_MASK 0x000003FF /* LTR maximum value */ 1251*6bbbd442SRobert Mustacchi #define IGC_LTRMINV_SCALE_MASK 0x00001C00 /* LTR minimum scale */ 1252*6bbbd442SRobert Mustacchi #define IGC_LTRMINV_SCALE_SHIFT 10 1253*6bbbd442SRobert Mustacchi /* Reg val to set scale to 1024 nsec */ 1254*6bbbd442SRobert Mustacchi #define IGC_LTRMINV_SCALE_1024 2 1255*6bbbd442SRobert Mustacchi /* Reg val to set scale to 32768 nsec */ 1256*6bbbd442SRobert Mustacchi #define IGC_LTRMINV_SCALE_32768 3 1257*6bbbd442SRobert Mustacchi #define IGC_LTRMINV_LSNP_REQ 0x00008000 /* LTR Snoop Requirement */ 1258*6bbbd442SRobert Mustacchi #define IGC_LTRMAXV_SCALE_MASK 0x00001C00 /* LTR maximum scale */ 1259*6bbbd442SRobert Mustacchi #define IGC_LTRMAXV_SCALE_SHIFT 10 1260*6bbbd442SRobert Mustacchi /* Reg val to set scale to 1024 nsec */ 1261*6bbbd442SRobert Mustacchi #define IGC_LTRMAXV_SCALE_1024 2 1262*6bbbd442SRobert Mustacchi /* Reg val to set scale to 32768 nsec */ 1263*6bbbd442SRobert Mustacchi #define IGC_LTRMAXV_SCALE_32768 3 1264*6bbbd442SRobert Mustacchi #define IGC_LTRMAXV_LSNP_REQ 0x00008000 /* LTR Snoop Requirement */ 1265*6bbbd442SRobert Mustacchi 1266*6bbbd442SRobert Mustacchi #define I225_RXPBSIZE_DEFAULT 0x000000A2 /* RXPBSIZE default */ 1267*6bbbd442SRobert Mustacchi #define I225_TXPBSIZE_DEFAULT 0x04000014 /* TXPBSIZE default */ 1268*6bbbd442SRobert Mustacchi #define IGC_RXPBS_SIZE_I225_MASK 0x0000003F /* Rx packet buffer size */ 1269*6bbbd442SRobert Mustacchi #define IGC_TXPB0S_SIZE_I225_MASK 0x0000003F /* Tx packet buffer 0 size */ 1270*6bbbd442SRobert Mustacchi #define IGC_STM_OPCODE 0xDB00 1271*6bbbd442SRobert Mustacchi #define IGC_EEPROM_FLASH_SIZE_WORD 0x11 1272*6bbbd442SRobert Mustacchi #define INVM_DWORD_TO_RECORD_TYPE(invm_dword) \ 1273*6bbbd442SRobert Mustacchi (u8)((invm_dword) & 0x7) 1274*6bbbd442SRobert Mustacchi #define INVM_DWORD_TO_WORD_ADDRESS(invm_dword) \ 1275*6bbbd442SRobert Mustacchi (u8)(((invm_dword) & 0x0000FE00) >> 9) 1276*6bbbd442SRobert Mustacchi #define INVM_DWORD_TO_WORD_DATA(invm_dword) \ 1277*6bbbd442SRobert Mustacchi (u16)(((invm_dword) & 0xFFFF0000) >> 16) 1278*6bbbd442SRobert Mustacchi #define IGC_INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS 8 1279*6bbbd442SRobert Mustacchi #define IGC_INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS 1 1280*6bbbd442SRobert Mustacchi #define IGC_INVM_ULT_BYTES_SIZE 8 1281*6bbbd442SRobert Mustacchi #define IGC_INVM_RECORD_SIZE_IN_BYTES 4 1282*6bbbd442SRobert Mustacchi #define IGC_INVM_VER_FIELD_ONE 0x1FF8 1283*6bbbd442SRobert Mustacchi #define IGC_INVM_VER_FIELD_TWO 0x7FE000 1284*6bbbd442SRobert Mustacchi #define IGC_INVM_IMGTYPE_FIELD 0x1F800000 1285*6bbbd442SRobert Mustacchi 1286*6bbbd442SRobert Mustacchi #define IGC_INVM_MAJOR_MASK 0x3F0 1287*6bbbd442SRobert Mustacchi #define IGC_INVM_MINOR_MASK 0xF 1288*6bbbd442SRobert Mustacchi #define IGC_INVM_MAJOR_SHIFT 4 1289*6bbbd442SRobert Mustacchi 1290*6bbbd442SRobert Mustacchi /* PLL Defines */ 1291*6bbbd442SRobert Mustacchi #define IGC_PCI_PMCSR 0x44 1292*6bbbd442SRobert Mustacchi #define IGC_PCI_PMCSR_D3 0x03 1293*6bbbd442SRobert Mustacchi #define IGC_MAX_PLL_TRIES 5 1294*6bbbd442SRobert Mustacchi #define IGC_PHY_PLL_UNCONF 0xFF 1295*6bbbd442SRobert Mustacchi #define IGC_PHY_PLL_FREQ_PAGE 0xFC0000 1296*6bbbd442SRobert Mustacchi #define IGC_PHY_PLL_FREQ_REG 0x000E 1297*6bbbd442SRobert Mustacchi #define IGC_INVM_DEFAULT_AL 0x202F 1298*6bbbd442SRobert Mustacchi #define IGC_INVM_AUTOLOAD 0x0A 1299*6bbbd442SRobert Mustacchi #define IGC_INVM_PLL_WO_VAL 0x0010 1300*6bbbd442SRobert Mustacchi 1301*6bbbd442SRobert Mustacchi /* Proxy Filter Control Extended */ 1302*6bbbd442SRobert Mustacchi #define IGC_PROXYFCEX_MDNS 0x00000001 /* mDNS */ 1303*6bbbd442SRobert Mustacchi #define IGC_PROXYFCEX_MDNS_M 0x00000002 /* mDNS Multicast */ 1304*6bbbd442SRobert Mustacchi #define IGC_PROXYFCEX_MDNS_U 0x00000004 /* mDNS Unicast */ 1305*6bbbd442SRobert Mustacchi #define IGC_PROXYFCEX_IPV4_M 0x00000008 /* IPv4 Multicast */ 1306*6bbbd442SRobert Mustacchi #define IGC_PROXYFCEX_IPV6_M 0x00000010 /* IPv6 Multicast */ 1307*6bbbd442SRobert Mustacchi #define IGC_PROXYFCEX_IGMP 0x00000020 /* IGMP */ 1308*6bbbd442SRobert Mustacchi #define IGC_PROXYFCEX_IGMP_M 0x00000040 /* IGMP Multicast */ 1309*6bbbd442SRobert Mustacchi #define IGC_PROXYFCEX_ARPRES 0x00000080 /* ARP Response */ 1310*6bbbd442SRobert Mustacchi #define IGC_PROXYFCEX_ARPRES_D 0x00000100 /* ARP Response Directed */ 1311*6bbbd442SRobert Mustacchi #define IGC_PROXYFCEX_ICMPV4 0x00000200 /* ICMPv4 */ 1312*6bbbd442SRobert Mustacchi #define IGC_PROXYFCEX_ICMPV4_D 0x00000400 /* ICMPv4 Directed */ 1313*6bbbd442SRobert Mustacchi #define IGC_PROXYFCEX_ICMPV6 0x00000800 /* ICMPv6 */ 1314*6bbbd442SRobert Mustacchi #define IGC_PROXYFCEX_ICMPV6_D 0x00001000 /* ICMPv6 Directed */ 1315*6bbbd442SRobert Mustacchi #define IGC_PROXYFCEX_DNS 0x00002000 /* DNS */ 1316*6bbbd442SRobert Mustacchi 1317*6bbbd442SRobert Mustacchi /* Proxy Filter Control */ 1318*6bbbd442SRobert Mustacchi #define IGC_PROXYFC_D0 0x00000001 /* Enable offload in D0 */ 1319*6bbbd442SRobert Mustacchi #define IGC_PROXYFC_EX 0x00000004 /* Directed exact proxy */ 1320*6bbbd442SRobert Mustacchi #define IGC_PROXYFC_MC 0x00000008 /* Directed MC Proxy */ 1321*6bbbd442SRobert Mustacchi #define IGC_PROXYFC_BC 0x00000010 /* Broadcast Proxy Enable */ 1322*6bbbd442SRobert Mustacchi #define IGC_PROXYFC_ARP_DIRECTED 0x00000020 /* Directed ARP Proxy Ena */ 1323*6bbbd442SRobert Mustacchi #define IGC_PROXYFC_IPV4 0x00000040 /* Directed IPv4 Enable */ 1324*6bbbd442SRobert Mustacchi #define IGC_PROXYFC_IPV6 0x00000080 /* Directed IPv6 Enable */ 1325*6bbbd442SRobert Mustacchi #define IGC_PROXYFC_NS 0x00000200 /* IPv6 Neighbor Solicitation */ 1326*6bbbd442SRobert Mustacchi #define IGC_PROXYFC_NS_DIRECTED 0x00000400 /* Directed NS Proxy Ena */ 1327*6bbbd442SRobert Mustacchi #define IGC_PROXYFC_ARP 0x00000800 /* ARP Request Proxy Ena */ 1328*6bbbd442SRobert Mustacchi /* Proxy Status */ 1329*6bbbd442SRobert Mustacchi #define IGC_PROXYS_CLEAR 0xFFFFFFFF /* Clear */ 1330*6bbbd442SRobert Mustacchi 1331*6bbbd442SRobert Mustacchi /* Firmware Status */ 1332*6bbbd442SRobert Mustacchi #define IGC_FWSTS_FWRI 0x80000000 /* FW Reset Indication */ 1333*6bbbd442SRobert Mustacchi /* VF Control */ 1334*6bbbd442SRobert Mustacchi #define IGC_VTCTRL_RST 0x04000000 /* Reset VF */ 1335*6bbbd442SRobert Mustacchi 1336*6bbbd442SRobert Mustacchi #define IGC_STATUS_LAN_ID_MASK 0x00000000C /* Mask for Lan ID field */ 1337*6bbbd442SRobert Mustacchi /* Lan ID bit field offset in status register */ 1338*6bbbd442SRobert Mustacchi #define IGC_STATUS_LAN_ID_OFFSET 2 1339*6bbbd442SRobert Mustacchi #define IGC_VFTA_ENTRIES 128 1340*6bbbd442SRobert Mustacchi 1341*6bbbd442SRobert Mustacchi #define IGC_UNUSEDARG 1342*6bbbd442SRobert Mustacchi #ifndef ERROR_REPORT 1343*6bbbd442SRobert Mustacchi #define ERROR_REPORT(fmt) do { } while (0) 1344*6bbbd442SRobert Mustacchi #endif /* ERROR_REPORT */ 1345*6bbbd442SRobert Mustacchi #endif /* _IGC_DEFINES_H_ */ 1346