xref: /illumos-gate/usr/src/uts/common/io/igb/igb_sw.h (revision 2509632a)
1c869993eSxy /*
2c869993eSxy  * CDDL HEADER START
3c869993eSxy  *
4c869993eSxy  * The contents of this file are subject to the terms of the
5c869993eSxy  * Common Development and Distribution License (the "License").
6c869993eSxy  * You may not use this file except in compliance with the License.
7c869993eSxy  *
80dc2366fSVenugopal Iyer  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
90dc2366fSVenugopal Iyer  * or http://www.opensolaris.org/os/licensing.
10c869993eSxy  * See the License for the specific language governing permissions
11c869993eSxy  * and limitations under the License.
12c869993eSxy  *
130dc2366fSVenugopal Iyer  * When distributing Covered Code, include this CDDL HEADER in each
140dc2366fSVenugopal Iyer  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15c869993eSxy  * If applicable, add the following below this CDDL HEADER, with the
16c869993eSxy  * fields enclosed by brackets "[]" replaced with your own identifying
17c869993eSxy  * information: Portions Copyright [yyyy] [name of copyright owner]
18c869993eSxy  *
19c869993eSxy  * CDDL HEADER END
20c869993eSxy  */
21c869993eSxy 
22da14cebeSEric Cheng /*
2308a0f9b0Schenlu chen - Sun Microsystems - Beijing China  * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
2408a0f9b0Schenlu chen - Sun Microsystems - Beijing China  */
2508a0f9b0Schenlu chen - Sun Microsystems - Beijing China 
2608a0f9b0Schenlu chen - Sun Microsystems - Beijing China /*
2708a0f9b0Schenlu chen - Sun Microsystems - Beijing China  * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
2813485e69SGarrett D'Amore  * Copyright 2014 Pluribus Networks Inc.
29c1e9c696SRobert Mustacchi  * Copyright (c) 2017, Joyent, Inc.
308d55b806SRobert Mustacchi  * Copyright 2020 Oxide Computer Company
31c869993eSxy  */
32c869993eSxy 
33c869993eSxy #ifndef	_IGB_SW_H
34c869993eSxy #define	_IGB_SW_H
35c869993eSxy 
36c869993eSxy #ifdef __cplusplus
37c869993eSxy extern "C" {
38c869993eSxy #endif
39c869993eSxy 
40c869993eSxy #include <sys/types.h>
41c869993eSxy #include <sys/conf.h>
42c869993eSxy #include <sys/debug.h>
43c869993eSxy #include <sys/stropts.h>
44c869993eSxy #include <sys/stream.h>
45c869993eSxy #include <sys/strsun.h>
46c869993eSxy #include <sys/strlog.h>
47c869993eSxy #include <sys/kmem.h>
48c869993eSxy #include <sys/stat.h>
49c869993eSxy #include <sys/kstat.h>
50c869993eSxy #include <sys/modctl.h>
51c869993eSxy #include <sys/errno.h>
52c869993eSxy #include <sys/dlpi.h>
53da14cebeSEric Cheng #include <sys/mac_provider.h>
54c869993eSxy #include <sys/mac_ether.h>
55c869993eSxy #include <sys/vlan.h>
56c869993eSxy #include <sys/ddi.h>
57c869993eSxy #include <sys/sunddi.h>
58c869993eSxy #include <sys/pci.h>
59c869993eSxy #include <sys/pcie.h>
60c869993eSxy #include <sys/sdt.h>
61c869993eSxy #include <sys/ethernet.h>
62c869993eSxy #include <sys/pattr.h>
63c869993eSxy #include <sys/strsubr.h>
64c869993eSxy #include <sys/netlb.h>
65c869993eSxy #include <sys/random.h>
66c869993eSxy #include <inet/common.h>
67d11274aaSPaul Guo #include <inet/tcp.h>
68c869993eSxy #include <inet/ip.h>
69c869993eSxy #include <inet/mi.h>
70c869993eSxy #include <inet/nd.h>
718bb4b220Sgl #include <sys/ddifm.h>
728bb4b220Sgl #include <sys/fm/protocol.h>
738bb4b220Sgl #include <sys/fm/util.h>
748bb4b220Sgl #include <sys/fm/io/ddi.h>
758d55b806SRobert Mustacchi #include <sys/ddi_ufm.h>
7675eba5b6SRobert Mustacchi #include "e1000_api.h"
7775eba5b6SRobert Mustacchi #include "e1000_82575.h"
78c869993eSxy 
79c869993eSxy 
80c869993eSxy #define	MODULE_NAME			"igb"	/* module name */
81c869993eSxy 
82c869993eSxy #define	IGB_SUCCESS			DDI_SUCCESS
83c869993eSxy #define	IGB_FAILURE			DDI_FAILURE
84c869993eSxy 
85c869993eSxy #define	IGB_UNKNOWN			0x00
86c869993eSxy #define	IGB_INITIALIZED			0x01
87c869993eSxy #define	IGB_STARTED			0x02
88c869993eSxy #define	IGB_SUSPENDED			0x04
893f7e60a6Szhefeng xu - Sun Microsystems - Beijing China #define	IGB_STALL			0x08
90cf8dcc9bSzhefeng xu - Sun Microsystems - Beijing China #define	IGB_ERROR			0x80
91c869993eSxy 
92ac7f5757Schenlu chen - Sun Microsystems - Beijing China #define	IGB_RX_STOPPED			0x1
93ac7f5757Schenlu chen - Sun Microsystems - Beijing China 
94c869993eSxy #define	IGB_INTR_NONE			0
95c869993eSxy #define	IGB_INTR_MSIX			1
96c869993eSxy #define	IGB_INTR_MSI			2
97c869993eSxy #define	IGB_INTR_LEGACY			3
98c869993eSxy 
9980a11ad2Schenlu chen - Sun Microsystems - Beijing China #define	IGB_ADAPTER_REGSET		1	/* mapping adapter registers */
10080a11ad2Schenlu chen - Sun Microsystems - Beijing China #define	IGB_ADAPTER_MSIXTAB		4	/* mapping msi-x table */
10180a11ad2Schenlu chen - Sun Microsystems - Beijing China 
102da14cebeSEric Cheng #define	IGB_NO_POLL			-1
103da14cebeSEric Cheng #define	IGB_NO_FREE_SLOT		-1
104da14cebeSEric Cheng 
105c869993eSxy #define	MAX_NUM_UNICAST_ADDRESSES	E1000_RAR_ENTRIES
1066ca163a1Svitezslav batrla - Sun Microsystems - Prague Czech Republic #define	MCAST_ALLOC_COUNT		256
107d11274aaSPaul Guo #define	MAX_COOKIE			18
108c869993eSxy #define	MIN_NUM_TX_DESC			2
109c869993eSxy 
11080a11ad2Schenlu chen - Sun Microsystems - Beijing China /*
11180a11ad2Schenlu chen - Sun Microsystems - Beijing China  * Number of settings for interrupt throttle rate (ITR).  There is one of
11280a11ad2Schenlu chen - Sun Microsystems - Beijing China  * these per msi-x vector and it needs to be the maximum of all silicon
11380a11ad2Schenlu chen - Sun Microsystems - Beijing China  * types supported by this driver.
11480a11ad2Schenlu chen - Sun Microsystems - Beijing China  */
11580a11ad2Schenlu chen - Sun Microsystems - Beijing China #define	MAX_NUM_EITR			25
11680a11ad2Schenlu chen - Sun Microsystems - Beijing China 
117c869993eSxy /*
118c869993eSxy  * Maximum values for user configurable parameters
119c869993eSxy  */
120c869993eSxy #define	MAX_TX_RING_SIZE		4096
121c869993eSxy #define	MAX_RX_RING_SIZE		4096
122da14cebeSEric Cheng #define	MAX_RX_GROUP_NUM		4
123c869993eSxy 
124c869993eSxy #define	MAX_MTU				9000
125c869993eSxy #define	MAX_RX_LIMIT_PER_INTR		4096
126c869993eSxy 
127c869993eSxy #define	MAX_RX_COPY_THRESHOLD		9216
128c869993eSxy #define	MAX_TX_COPY_THRESHOLD		9216
129c869993eSxy #define	MAX_TX_RECYCLE_THRESHOLD	DEFAULT_TX_RING_SIZE
130c869993eSxy #define	MAX_TX_OVERLOAD_THRESHOLD	DEFAULT_TX_RING_SIZE
131c869993eSxy #define	MAX_TX_RESCHED_THRESHOLD	DEFAULT_TX_RING_SIZE
1326ca163a1Svitezslav batrla - Sun Microsystems - Prague Czech Republic #define	MAX_MCAST_NUM			8192
133c869993eSxy 
134c869993eSxy /*
135c869993eSxy  * Minimum values for user configurable parameters
136c869993eSxy  */
137c869993eSxy #define	MIN_TX_RING_SIZE		64
138c869993eSxy #define	MIN_RX_RING_SIZE		64
139da14cebeSEric Cheng #define	MIN_RX_GROUP_NUM		1
140c869993eSxy 
141c869993eSxy #define	MIN_MTU				ETHERMIN
142c869993eSxy #define	MIN_RX_LIMIT_PER_INTR		16
1433f7e60a6Szhefeng xu - Sun Microsystems - Beijing China 
144c869993eSxy #define	MIN_RX_COPY_THRESHOLD		0
145c869993eSxy #define	MIN_TX_COPY_THRESHOLD		0
146c869993eSxy #define	MIN_TX_RECYCLE_THRESHOLD	MIN_NUM_TX_DESC
147c869993eSxy #define	MIN_TX_OVERLOAD_THRESHOLD	MIN_NUM_TX_DESC
148c869993eSxy #define	MIN_TX_RESCHED_THRESHOLD	MIN_NUM_TX_DESC
1496ca163a1Svitezslav batrla - Sun Microsystems - Prague Czech Republic #define	MIN_MCAST_NUM			8
150c869993eSxy 
151c869993eSxy /*
152c869993eSxy  * Default values for user configurable parameters
153c869993eSxy  */
154c869993eSxy #define	DEFAULT_TX_RING_SIZE		512
155c869993eSxy #define	DEFAULT_RX_RING_SIZE		512
156da14cebeSEric Cheng #define	DEFAULT_RX_GROUP_NUM		1
157c869993eSxy 
158c869993eSxy #define	DEFAULT_MTU			ETHERMTU
159c869993eSxy #define	DEFAULT_RX_LIMIT_PER_INTR	256
1603f7e60a6Szhefeng xu - Sun Microsystems - Beijing China 
161c869993eSxy #define	DEFAULT_RX_COPY_THRESHOLD	128
162c869993eSxy #define	DEFAULT_TX_COPY_THRESHOLD	512
163d11274aaSPaul Guo #define	DEFAULT_TX_RECYCLE_THRESHOLD	(MAX_COOKIE + 1)
164c869993eSxy #define	DEFAULT_TX_OVERLOAD_THRESHOLD	MIN_NUM_TX_DESC
165c869993eSxy #define	DEFAULT_TX_RESCHED_THRESHOLD	128
16669b2d733SGuoqing Zhu #define	DEFAULT_TX_RESCHED_THRESHOLD_LOW	32
1676ca163a1Svitezslav batrla - Sun Microsystems - Prague Czech Republic #define	DEFAULT_MCAST_NUM		4096
168c869993eSxy 
169d11274aaSPaul Guo #define	IGB_LSO_MAXLEN			65535
170d11274aaSPaul Guo 
171c869993eSxy #define	TX_DRAIN_TIME			200
172c869993eSxy #define	RX_DRAIN_TIME			200
173c869993eSxy 
174c869993eSxy #define	STALL_WATCHDOG_TIMEOUT		8	/* 8 seconds */
175c869993eSxy 
176c869993eSxy /*
177c869993eSxy  * Defined for IP header alignment.
178c869993eSxy  */
179c869993eSxy #define	IPHDR_ALIGN_ROOM		2
180c869993eSxy 
181c869993eSxy /*
182c869993eSxy  * Bit flags for attach_progress
183c869993eSxy  */
184c869993eSxy #define	ATTACH_PROGRESS_PCI_CONFIG	0x0001	/* PCI config setup */
185c869993eSxy #define	ATTACH_PROGRESS_REGS_MAP	0x0002	/* Registers mapped */
186c869993eSxy #define	ATTACH_PROGRESS_PROPS		0x0004	/* Properties initialized */
187c869993eSxy #define	ATTACH_PROGRESS_ALLOC_INTR	0x0008	/* Interrupts allocated */
188c869993eSxy #define	ATTACH_PROGRESS_ALLOC_RINGS	0x0010	/* Rings allocated */
189c869993eSxy #define	ATTACH_PROGRESS_ADD_INTR	0x0020	/* Intr handlers added */
190c869993eSxy #define	ATTACH_PROGRESS_LOCKS		0x0040	/* Locks initialized */
191b8d0a377Schenlu chen - Sun Microsystems - Beijing China #define	ATTACH_PROGRESS_INIT_ADAPTER	0x0080	/* Adapter initialized */
192c869993eSxy #define	ATTACH_PROGRESS_STATS		0x0200	/* Kstats created */
193c869993eSxy #define	ATTACH_PROGRESS_MAC		0x0800	/* MAC registered */
194c869993eSxy #define	ATTACH_PROGRESS_ENABLE_INTR	0x1000	/* DDI interrupts enabled */
1958bb4b220Sgl #define	ATTACH_PROGRESS_FMINIT		0x2000	/* FMA initialized */
1968d55b806SRobert Mustacchi #define	ATTACH_PROGRESS_UFM		0x4000	/* UFM enabled */
197c869993eSxy 
198c869993eSxy #define	PROP_ADV_AUTONEG_CAP		"adv_autoneg_cap"
199c869993eSxy #define	PROP_ADV_1000FDX_CAP		"adv_1000fdx_cap"
200c869993eSxy #define	PROP_ADV_1000HDX_CAP		"adv_1000hdx_cap"
201c869993eSxy #define	PROP_ADV_100FDX_CAP		"adv_100fdx_cap"
202c869993eSxy #define	PROP_ADV_100HDX_CAP		"adv_100hdx_cap"
203c869993eSxy #define	PROP_ADV_10FDX_CAP		"adv_10fdx_cap"
204c869993eSxy #define	PROP_ADV_10HDX_CAP		"adv_10hdx_cap"
205c869993eSxy #define	PROP_DEFAULT_MTU		"default_mtu"
206c869993eSxy #define	PROP_FLOW_CONTROL		"flow_control"
207c869993eSxy #define	PROP_TX_RING_SIZE		"tx_ring_size"
208c869993eSxy #define	PROP_RX_RING_SIZE		"rx_ring_size"
209da14cebeSEric Cheng #define	PROP_MR_ENABLE			"mr_enable"
210da14cebeSEric Cheng #define	PROP_RX_GROUP_NUM		"rx_group_number"
211c869993eSxy 
212c869993eSxy #define	PROP_INTR_FORCE			"intr_force"
213c869993eSxy #define	PROP_TX_HCKSUM_ENABLE		"tx_hcksum_enable"
214c869993eSxy #define	PROP_RX_HCKSUM_ENABLE		"rx_hcksum_enable"
215c869993eSxy #define	PROP_LSO_ENABLE			"lso_enable"
216c869993eSxy #define	PROP_TX_HEAD_WB_ENABLE		"tx_head_wb_enable"
217c869993eSxy #define	PROP_TX_COPY_THRESHOLD		"tx_copy_threshold"
218c869993eSxy #define	PROP_TX_RECYCLE_THRESHOLD	"tx_recycle_threshold"
219c869993eSxy #define	PROP_TX_OVERLOAD_THRESHOLD	"tx_overload_threshold"
220c869993eSxy #define	PROP_TX_RESCHED_THRESHOLD	"tx_resched_threshold"
221c869993eSxy #define	PROP_RX_COPY_THRESHOLD		"rx_copy_threshold"
222c869993eSxy #define	PROP_RX_LIMIT_PER_INTR		"rx_limit_per_intr"
223c869993eSxy #define	PROP_INTR_THROTTLING		"intr_throttling"
2246ca163a1Svitezslav batrla - Sun Microsystems - Prague Czech Republic #define	PROP_MCAST_MAX_NUM		"mcast_max_num"
225c869993eSxy 
226c869993eSxy #define	IGB_LB_NONE			0
227c869993eSxy #define	IGB_LB_EXTERNAL			1
228c869993eSxy #define	IGB_LB_INTERNAL_PHY		3
229c869993eSxy #define	IGB_LB_INTERNAL_SERDES		4
230c869993eSxy 
231c869993eSxy enum ioc_reply {
232c869993eSxy 	IOC_INVAL = -1,	/* bad, NAK with EINVAL */
23385f496faSRobert Mustacchi 	IOC_DONE,	/* OK, reply sent */
234c869993eSxy 	IOC_ACK,	/* OK, just send ACK */
235c869993eSxy 	IOC_REPLY	/* OK, just send reply */
236c869993eSxy };
237c869993eSxy 
238d11274aaSPaul Guo /*
239d11274aaSPaul Guo  * For s/w context extraction from a tx frame
240d11274aaSPaul Guo  */
241d11274aaSPaul Guo #define	TX_CXT_SUCCESS		0
242d11274aaSPaul Guo #define	TX_CXT_E_LSO_CSUM	(-1)
243d11274aaSPaul Guo #define	TX_CXT_E_ETHER_TYPE	(-2)
244c869993eSxy 
245c869993eSxy #define	DMA_SYNC(area, flag)	((void) ddi_dma_sync((area)->dma_handle, \
246c869993eSxy 				    0, 0, (flag)))
247c869993eSxy 
248c869993eSxy /*
249c869993eSxy  * Defined for ring index operations
250c869993eSxy  * ASSERT(index < limit)
251c869993eSxy  * ASSERT(step < limit)
252c869993eSxy  * ASSERT(index1 < limit)
253c869993eSxy  * ASSERT(index2 < limit)
254c869993eSxy  */
255c869993eSxy #define	NEXT_INDEX(index, step, limit)	(((index) + (step)) < (limit) ? \
256c869993eSxy 	(index) + (step) : (index) + (step) - (limit))
257c869993eSxy #define	PREV_INDEX(index, step, limit)	((index) >= (step) ? \
258c869993eSxy 	(index) - (step) : (index) + (limit) - (step))
259c869993eSxy #define	OFFSET(index1, index2, limit)	((index1) <= (index2) ? \
260c869993eSxy 	(index2) - (index1) : (index2) + (limit) - (index1))
261c869993eSxy 
262c869993eSxy #define	LINK_LIST_INIT(_LH)	\
263c869993eSxy 	(_LH)->head = (_LH)->tail = NULL
264c869993eSxy 
265c869993eSxy #define	LIST_GET_HEAD(_LH)	((single_link_t *)((_LH)->head))
266c869993eSxy 
267c869993eSxy #define	LIST_POP_HEAD(_LH)	\
268c869993eSxy 	(single_link_t *)(_LH)->head; \
269c869993eSxy 	{ \
270c869993eSxy 		if ((_LH)->head != NULL) { \
271c869993eSxy 			(_LH)->head = (_LH)->head->link; \
272c869993eSxy 			if ((_LH)->head == NULL) \
273c869993eSxy 				(_LH)->tail = NULL; \
274c869993eSxy 		} \
275c869993eSxy 	}
276c869993eSxy 
277c869993eSxy #define	LIST_GET_TAIL(_LH)	((single_link_t *)((_LH)->tail))
278c869993eSxy 
279c869993eSxy #define	LIST_PUSH_TAIL(_LH, _E)	\
280c869993eSxy 	if ((_LH)->tail != NULL) { \
281c869993eSxy 		(_LH)->tail->link = (single_link_t *)(_E); \
282c869993eSxy 		(_LH)->tail = (single_link_t *)(_E); \
283c869993eSxy 	} else { \
284c869993eSxy 		(_LH)->head = (_LH)->tail = (single_link_t *)(_E); \
285c869993eSxy 	} \
286c869993eSxy 	(_E)->link = NULL;
287c869993eSxy 
288c869993eSxy #define	LIST_GET_NEXT(_LH, _E)		\
289c869993eSxy 	(((_LH)->tail == (single_link_t *)(_E)) ? \
290c869993eSxy 	NULL : ((single_link_t *)(_E))->link)
291c869993eSxy 
292c869993eSxy 
293c869993eSxy typedef struct single_link {
294c869993eSxy 	struct single_link	*link;
295c869993eSxy } single_link_t;
296c869993eSxy 
297c869993eSxy typedef struct link_list {
298c869993eSxy 	single_link_t		*head;
299c869993eSxy 	single_link_t		*tail;
300c869993eSxy } link_list_t;
301c869993eSxy 
302c869993eSxy /*
303c869993eSxy  * Property lookups
304c869993eSxy  */
305c869993eSxy #define	IGB_PROP_EXISTS(d, n)	ddi_prop_exists(DDI_DEV_T_ANY, (d), \
306c869993eSxy 				    DDI_PROP_DONTPASS, (n))
307c869993eSxy #define	IGB_PROP_GET_INT(d, n)	ddi_prop_get_int(DDI_DEV_T_ANY, (d), \
308c869993eSxy 				    DDI_PROP_DONTPASS, (n), -1)
309c869993eSxy 
310c869993eSxy 
31180a11ad2Schenlu chen - Sun Microsystems - Beijing China /* capability/feature flags */
31280a11ad2Schenlu chen - Sun Microsystems - Beijing China #define	IGB_FLAG_HAS_DCA	(1 << 0) /* has Direct Cache Access */
31380a11ad2Schenlu chen - Sun Microsystems - Beijing China #define	IGB_FLAG_VMDQ_POOL	(1 << 1) /* has vmdq capability */
31480a11ad2Schenlu chen - Sun Microsystems - Beijing China #define	IGB_FLAG_NEED_CTX_IDX	(1 << 2) /* context descriptor needs index */
31580a11ad2Schenlu chen - Sun Microsystems - Beijing China 
31680a11ad2Schenlu chen - Sun Microsystems - Beijing China /* function pointer for nic-specific functions */
31780a11ad2Schenlu chen - Sun Microsystems - Beijing China typedef void (*igb_nic_func_t)(struct igb *);
31880a11ad2Schenlu chen - Sun Microsystems - Beijing China 
31980a11ad2Schenlu chen - Sun Microsystems - Beijing China /* adapter-specific info for each supported device type */
32080a11ad2Schenlu chen - Sun Microsystems - Beijing China typedef struct adapter_info {
32180a11ad2Schenlu chen - Sun Microsystems - Beijing China 	/* limits */
32280a11ad2Schenlu chen - Sun Microsystems - Beijing China 	uint32_t	max_rx_que_num;	/* maximum number of rx queues */
32380a11ad2Schenlu chen - Sun Microsystems - Beijing China 	uint32_t	min_rx_que_num;	/* minimum number of rx queues */
32480a11ad2Schenlu chen - Sun Microsystems - Beijing China 	uint32_t	def_rx_que_num;	/* default number of rx queues */
32580a11ad2Schenlu chen - Sun Microsystems - Beijing China 	uint32_t	max_tx_que_num;	/* maximum number of tx queues */
32680a11ad2Schenlu chen - Sun Microsystems - Beijing China 	uint32_t	min_tx_que_num;	/* minimum number of tx queues */
32780a11ad2Schenlu chen - Sun Microsystems - Beijing China 	uint32_t	def_tx_que_num;	/* default number of tx queues */
32880a11ad2Schenlu chen - Sun Microsystems - Beijing China 	uint32_t	max_intr_throttle; /* maximum interrupt throttle */
32980a11ad2Schenlu chen - Sun Microsystems - Beijing China 	uint32_t	min_intr_throttle; /* minimum interrupt throttle */
33080a11ad2Schenlu chen - Sun Microsystems - Beijing China 	uint32_t	def_intr_throttle; /* default interrupt throttle */
33180a11ad2Schenlu chen - Sun Microsystems - Beijing China 	/* function pointers */
33280a11ad2Schenlu chen - Sun Microsystems - Beijing China 	igb_nic_func_t	enable_intr;	/* enable adapter interrupts */
33380a11ad2Schenlu chen - Sun Microsystems - Beijing China 	igb_nic_func_t	setup_msix;	/* set up msi-x vectors */
33480a11ad2Schenlu chen - Sun Microsystems - Beijing China 	/* capabilities */
33580a11ad2Schenlu chen - Sun Microsystems - Beijing China 	uint32_t	flags;		/* capability flags */
336b8d0a377Schenlu chen - Sun Microsystems - Beijing China 	uint32_t	rxdctl_mask;	/* mask for RXDCTL register */
33780a11ad2Schenlu chen - Sun Microsystems - Beijing China } adapter_info_t;
33880a11ad2Schenlu chen - Sun Microsystems - Beijing China 
339c869993eSxy typedef union igb_ether_addr {
340c869993eSxy 	struct {
341c869993eSxy 		uint32_t	high;
342c869993eSxy 		uint32_t	low;
343c869993eSxy 	} reg;
344c869993eSxy 	struct {
345c869993eSxy 		uint8_t		set;
346da14cebeSEric Cheng 		uint8_t		group_index;
347c869993eSxy 		uint8_t		addr[ETHERADDRL];
348c869993eSxy 	} mac;
349c869993eSxy } igb_ether_addr_t;
350c869993eSxy 
351c869993eSxy typedef enum {
352c869993eSxy 	USE_NONE,
353c869993eSxy 	USE_COPY,
354c869993eSxy 	USE_DMA
355c869993eSxy } tx_type_t;
356c869993eSxy 
357d11274aaSPaul Guo typedef struct tx_context {
358c869993eSxy 	uint32_t		hcksum_flags;
359c869993eSxy 	uint32_t		ip_hdr_len;
360c869993eSxy 	uint32_t		mac_hdr_len;
36185f496faSRobert Mustacchi 	uint32_t		l3_proto;
362c869993eSxy 	uint32_t		l4_proto;
363d11274aaSPaul Guo 	uint32_t		mss;
364d11274aaSPaul Guo 	uint32_t		l4_hdr_len;
365d11274aaSPaul Guo 	boolean_t		lso_flag;
366d11274aaSPaul Guo } tx_context_t;
367c869993eSxy 
368c869993eSxy /* Hold address/length of each DMA segment */
369c869993eSxy typedef struct sw_desc {
370c869993eSxy 	uint64_t		address;
371c869993eSxy 	size_t			length;
372c869993eSxy } sw_desc_t;
373c869993eSxy 
374c869993eSxy /* Handles and addresses of DMA buffer */
375c869993eSxy typedef struct dma_buffer {
376c869993eSxy 	caddr_t			address;	/* Virtual address */
377c869993eSxy 	uint64_t		dma_address;	/* DMA (Hardware) address */
378c869993eSxy 	ddi_acc_handle_t	acc_handle;	/* Data access handle */
379c869993eSxy 	ddi_dma_handle_t	dma_handle;	/* DMA handle */
380c869993eSxy 	size_t			size;		/* Buffer size */
381c869993eSxy 	size_t			len;		/* Data length in the buffer */
382c869993eSxy } dma_buffer_t;
383c869993eSxy 
384c869993eSxy /*
385c869993eSxy  * Tx Control Block
386c869993eSxy  */
387c869993eSxy typedef struct tx_control_block {
388c869993eSxy 	single_link_t		link;
38969b2d733SGuoqing Zhu 	uint32_t		last_index;
390c869993eSxy 	uint32_t		frag_num;
391c869993eSxy 	uint32_t		desc_num;
392c869993eSxy 	mblk_t			*mp;
393c869993eSxy 	tx_type_t		tx_type;
394c869993eSxy 	ddi_dma_handle_t	tx_dma_handle;
395c869993eSxy 	dma_buffer_t		tx_buf;
396c869993eSxy 	sw_desc_t		desc[MAX_COOKIE];
397c869993eSxy } tx_control_block_t;
398c869993eSxy 
399c869993eSxy /*
400c869993eSxy  * RX Control Block
401c869993eSxy  */
402c869993eSxy typedef struct rx_control_block {
403c869993eSxy 	mblk_t			*mp;
404ac7f5757Schenlu chen - Sun Microsystems - Beijing China 	uint32_t		ref_cnt;
405c869993eSxy 	dma_buffer_t		rx_buf;
406c869993eSxy 	frtn_t			free_rtn;
407ac7f5757Schenlu chen - Sun Microsystems - Beijing China 	struct igb_rx_data	*rx_data;
408c869993eSxy } rx_control_block_t;
409c869993eSxy 
410c869993eSxy /*
411c869993eSxy  * Software Data Structure for Tx Ring
412c869993eSxy  */
413c869993eSxy typedef struct igb_tx_ring {
414c869993eSxy 	uint32_t		index;	/* Ring index */
415da14cebeSEric Cheng 	uint32_t		intr_vector;	/* Interrupt vector index */
416c869993eSxy 
417c869993eSxy 	/*
418c869993eSxy 	 * Mutexes
419c869993eSxy 	 */
420c869993eSxy 	kmutex_t		tx_lock;
421c869993eSxy 	kmutex_t		recycle_lock;
422c869993eSxy 	kmutex_t		tcb_head_lock;
423c869993eSxy 	kmutex_t		tcb_tail_lock;
424c869993eSxy 
425c869993eSxy 	/*
426c869993eSxy 	 * Tx descriptor ring definitions
427c869993eSxy 	 */
428c869993eSxy 	dma_buffer_t		tbd_area;
429c869993eSxy 	union e1000_adv_tx_desc	*tbd_ring;
430c869993eSxy 	uint32_t		tbd_head; /* Index of next tbd to recycle */
431c869993eSxy 	uint32_t		tbd_tail; /* Index of next tbd to transmit */
432c869993eSxy 	uint32_t		tbd_free; /* Number of free tbd */
433c869993eSxy 
434c869993eSxy 	/*
435c869993eSxy 	 * Tx control block list definitions
436c869993eSxy 	 */
437c869993eSxy 	tx_control_block_t	*tcb_area;
438c869993eSxy 	tx_control_block_t	**work_list;
439c869993eSxy 	tx_control_block_t	**free_list;
440c869993eSxy 	uint32_t		tcb_head; /* Head index of free list */
441c869993eSxy 	uint32_t		tcb_tail; /* Tail index of free list */
442c869993eSxy 	uint32_t		tcb_free; /* Number of free tcb in free list */
443c869993eSxy 
444c869993eSxy 	uint32_t		*tbd_head_wb; /* Head write-back */
445c869993eSxy 	uint32_t		(*tx_recycle)(struct igb_tx_ring *);
446c869993eSxy 
447c869993eSxy 	/*
448d11274aaSPaul Guo 	 * s/w context structure for TCP/UDP checksum offload and LSO.
449c869993eSxy 	 */
450d11274aaSPaul Guo 	tx_context_t		tx_context;
451c869993eSxy 
452c869993eSxy 	/*
453c869993eSxy 	 * Tx ring settings and status
454c869993eSxy 	 */
455c869993eSxy 	uint32_t		ring_size; /* Tx descriptor ring size */
456c869993eSxy 	uint32_t		free_list_size;	/* Tx free list size */
457c869993eSxy 
458c869993eSxy 	boolean_t		reschedule;
459c869993eSxy 	uint32_t		recycle_fail;
460c869993eSxy 	uint32_t		stall_watchdog;
461c869993eSxy 
4620dc2366fSVenugopal Iyer 	/*
4630dc2366fSVenugopal Iyer 	 * Per-ring statistics
4640dc2366fSVenugopal Iyer 	 */
4650dc2366fSVenugopal Iyer 	uint64_t		tx_pkts;	/* Packets Transmitted Count */
4660dc2366fSVenugopal Iyer 	uint64_t		tx_bytes;	/* Bytes Transmitted Count */
4670dc2366fSVenugopal Iyer 
468c869993eSxy #ifdef IGB_DEBUG
469c869993eSxy 	/*
470c869993eSxy 	 * Debug statistics
471c869993eSxy 	 */
472c869993eSxy 	uint32_t		stat_overload;
473c869993eSxy 	uint32_t		stat_fail_no_tbd;
474c869993eSxy 	uint32_t		stat_fail_no_tcb;
475c869993eSxy 	uint32_t		stat_fail_dma_bind;
476c869993eSxy 	uint32_t		stat_reschedule;
477da14cebeSEric Cheng 	uint32_t		stat_pkt_cnt;
478c869993eSxy #endif
479c869993eSxy 
480c869993eSxy 	/*
481c869993eSxy 	 * Pointer to the igb struct
482c869993eSxy 	 */
483c869993eSxy 	struct igb		*igb;
484da14cebeSEric Cheng 	mac_ring_handle_t	ring_handle;	/* call back ring handle */
485c869993eSxy } igb_tx_ring_t;
486c869993eSxy 
487c869993eSxy /*
488c869993eSxy  * Software Receive Ring
489c869993eSxy  */
490ac7f5757Schenlu chen - Sun Microsystems - Beijing China typedef struct igb_rx_data {
491c869993eSxy 	kmutex_t		recycle_lock;	/* Recycle lock, for rcb_tail */
492c869993eSxy 
493c869993eSxy 	/*
494c869993eSxy 	 * Rx descriptor ring definitions
495c869993eSxy 	 */
496c869993eSxy 	dma_buffer_t		rbd_area;	/* DMA buffer of rx desc ring */
497c869993eSxy 	union e1000_adv_rx_desc	*rbd_ring;	/* Rx desc ring */
498c869993eSxy 	uint32_t		rbd_next;	/* Index of next rx desc */
499c869993eSxy 
500c869993eSxy 	/*
501c869993eSxy 	 * Rx control block list definitions
502c869993eSxy 	 */
503c869993eSxy 	rx_control_block_t	*rcb_area;
504c869993eSxy 	rx_control_block_t	**work_list;	/* Work list of rcbs */
505c869993eSxy 	rx_control_block_t	**free_list;	/* Free list of rcbs */
506c869993eSxy 	uint32_t		rcb_head;	/* Index of next free rcb */
507c869993eSxy 	uint32_t		rcb_tail;	/* Index to put recycled rcb */
508c869993eSxy 	uint32_t		rcb_free;	/* Number of free rcbs */
509c869993eSxy 
510c869993eSxy 	/*
511ac7f5757Schenlu chen - Sun Microsystems - Beijing China 	 * Rx sw ring settings and status
512c869993eSxy 	 */
513c869993eSxy 	uint32_t		ring_size;	/* Rx descriptor ring size */
514c869993eSxy 	uint32_t		free_list_size;	/* Rx free list size */
515ac7f5757Schenlu chen - Sun Microsystems - Beijing China 
516ac7f5757Schenlu chen - Sun Microsystems - Beijing China 	uint32_t		rcb_pending;
517ac7f5757Schenlu chen - Sun Microsystems - Beijing China 	uint32_t		flag;
518ac7f5757Schenlu chen - Sun Microsystems - Beijing China 
519ac7f5757Schenlu chen - Sun Microsystems - Beijing China 	struct igb_rx_ring	*rx_ring;	/* Pointer to rx ring */
520ac7f5757Schenlu chen - Sun Microsystems - Beijing China } igb_rx_data_t;
521ac7f5757Schenlu chen - Sun Microsystems - Beijing China 
522ac7f5757Schenlu chen - Sun Microsystems - Beijing China /*
523ac7f5757Schenlu chen - Sun Microsystems - Beijing China  * Software Data Structure for Rx Ring
524ac7f5757Schenlu chen - Sun Microsystems - Beijing China  */
525ac7f5757Schenlu chen - Sun Microsystems - Beijing China typedef struct igb_rx_ring {
526ac7f5757Schenlu chen - Sun Microsystems - Beijing China 	uint32_t		index;		/* Ring index */
527ac7f5757Schenlu chen - Sun Microsystems - Beijing China 	uint32_t		intr_vector;	/* Interrupt vector index */
528ac7f5757Schenlu chen - Sun Microsystems - Beijing China 
529ac7f5757Schenlu chen - Sun Microsystems - Beijing China 	igb_rx_data_t		*rx_data;	/* Rx software ring */
530ac7f5757Schenlu chen - Sun Microsystems - Beijing China 
531ac7f5757Schenlu chen - Sun Microsystems - Beijing China 	kmutex_t		rx_lock;	/* Rx access lock */
532c869993eSxy 
5330dc2366fSVenugopal Iyer 	/*
5340dc2366fSVenugopal Iyer 	 * Per-ring statistics
5350dc2366fSVenugopal Iyer 	 */
5360dc2366fSVenugopal Iyer 	uint64_t		rx_pkts;	/* Packets Received Count */
5370dc2366fSVenugopal Iyer 	uint64_t		rx_bytes;	/* Bytes Received Count */
5380dc2366fSVenugopal Iyer 
539c869993eSxy #ifdef IGB_DEBUG
540c869993eSxy 	/*
541c869993eSxy 	 * Debug statistics
542c869993eSxy 	 */
543c869993eSxy 	uint32_t		stat_frame_error;
544c869993eSxy 	uint32_t		stat_cksum_error;
545c869993eSxy 	uint32_t		stat_exceed_pkt;
546da14cebeSEric Cheng 	uint32_t		stat_pkt_cnt;
547c869993eSxy #endif
548c869993eSxy 
549c869993eSxy 	struct igb		*igb;		/* Pointer to igb struct */
550b8d0a377Schenlu chen - Sun Microsystems - Beijing China 	mac_ring_handle_t	ring_handle;	/* call back ring handle */
551da14cebeSEric Cheng 	uint32_t		group_index;	/* group index */
552da14cebeSEric Cheng 	uint64_t		ring_gen_num;
553c869993eSxy } igb_rx_ring_t;
554c869993eSxy 
555da14cebeSEric Cheng /*
556da14cebeSEric Cheng  * Software Receive Ring Group
557da14cebeSEric Cheng  */
558da14cebeSEric Cheng typedef struct igb_rx_group {
559da14cebeSEric Cheng 	uint32_t		index;		/* Group index */
560da14cebeSEric Cheng 	mac_group_handle_t	group_handle;   /* call back group handle */
561da14cebeSEric Cheng 	struct igb		*igb;		/* Pointer to igb struct */
562da14cebeSEric Cheng } igb_rx_group_t;
563da14cebeSEric Cheng 
564*2509632aSRobert Mustacchi typedef enum {
565*2509632aSRobert Mustacchi 	IGB_ETS_INDEX_INTERNAL		= 0,
566*2509632aSRobert Mustacchi 	IGB_ETS_INDEX_EXTERNAL_1	= 1,
567*2509632aSRobert Mustacchi 	IGB_ETS_INDEX_EXTERNAL_2	= 2,
568*2509632aSRobert Mustacchi 	IGB_ETS_INDEX_EXTERNAL_3	= 3
569*2509632aSRobert Mustacchi } igb_ets_index_t;
570*2509632aSRobert Mustacchi 
571*2509632aSRobert Mustacchi typedef enum {
572*2509632aSRobert Mustacchi 	IGB_ETS_LOC_NA		= 0,
573*2509632aSRobert Mustacchi 	IGB_ETS_LOC_HOT_SPOT	= 2,
574*2509632aSRobert Mustacchi 	IGB_ETS_LOC_PCIE	= 3,
575*2509632aSRobert Mustacchi 	IGB_ETS_LOC_BULKHEAD	= 4,
576*2509632aSRobert Mustacchi 	IGB_ETS_LOC_BOARD	= 5,
577*2509632aSRobert Mustacchi 	IGB_ETS_LOC_INLET	= 7
578*2509632aSRobert Mustacchi } igb_ets_loc_t;
579*2509632aSRobert Mustacchi 
580*2509632aSRobert Mustacchi /*
581*2509632aSRobert Mustacchi  * Sensor data
582*2509632aSRobert Mustacchi  */
583*2509632aSRobert Mustacchi typedef struct igb_ets {
584*2509632aSRobert Mustacchi 	igb_ets_index_t	iet_index;
585*2509632aSRobert Mustacchi 	igb_ets_loc_t	iet_loc;
586*2509632aSRobert Mustacchi 	uint8_t		iet_thresh;
587*2509632aSRobert Mustacchi 	id_t		iet_ksensor;
588*2509632aSRobert Mustacchi } igb_ets_t;
589*2509632aSRobert Mustacchi 
590*2509632aSRobert Mustacchi /*
591*2509632aSRobert Mustacchi  * There are only four words defined for sensors.
592*2509632aSRobert Mustacchi  */
593*2509632aSRobert Mustacchi #define	IGB_ETS_MAX	4
594*2509632aSRobert Mustacchi 
595*2509632aSRobert Mustacchi typedef struct igb_sensors {
596*2509632aSRobert Mustacchi 	boolean_t isn_valid;
597*2509632aSRobert Mustacchi 	id_t isn_reg_ksensor;
598*2509632aSRobert Mustacchi 	uint_t isn_nents;
599*2509632aSRobert Mustacchi 	igb_ets_t isn_ets[IGB_ETS_MAX];
600*2509632aSRobert Mustacchi } igb_sensors_t;
601*2509632aSRobert Mustacchi 
602c869993eSxy typedef struct igb {
60385f496faSRobert Mustacchi 	int			instance;
604c869993eSxy 	mac_handle_t		mac_hdl;
605c869993eSxy 	dev_info_t		*dip;
606c869993eSxy 	struct e1000_hw		hw;
607c869993eSxy 	struct igb_osdep	osdep;
608c869993eSxy 
60980a11ad2Schenlu chen - Sun Microsystems - Beijing China 	adapter_info_t		*capab;		/* adapter capabilities */
61080a11ad2Schenlu chen - Sun Microsystems - Beijing China 
611c869993eSxy 	uint32_t		igb_state;
612c869993eSxy 	link_state_t		link_state;
613c869993eSxy 	uint32_t		link_speed;
614c869993eSxy 	uint32_t		link_duplex;
615cf8dcc9bSzhefeng xu - Sun Microsystems - Beijing China 	boolean_t		link_complete;
616cf8dcc9bSzhefeng xu - Sun Microsystems - Beijing China 	timeout_id_t		link_tid;
617c869993eSxy 
618c869993eSxy 	uint32_t		reset_count;
619c869993eSxy 	uint32_t		attach_progress;
620c869993eSxy 	uint32_t		loopback_mode;
621ac7f5757Schenlu chen - Sun Microsystems - Beijing China 	uint32_t		default_mtu;
622c869993eSxy 	uint32_t		max_frame_size;
623b8d0a377Schenlu chen - Sun Microsystems - Beijing China 	uint32_t		dout_sync;
624c869993eSxy 
625ac7f5757Schenlu chen - Sun Microsystems - Beijing China 	uint32_t		rcb_pending;
626ac7f5757Schenlu chen - Sun Microsystems - Beijing China 
627da14cebeSEric Cheng 	uint32_t		mr_enable;	/* Enable multiple rings */
628da14cebeSEric Cheng 	uint32_t		vmdq_mode;	/* Mode of VMDq */
629da14cebeSEric Cheng 
630c869993eSxy 	/*
631da14cebeSEric Cheng 	 * Receive Rings and Groups
632c869993eSxy 	 */
633c869993eSxy 	igb_rx_ring_t		*rx_rings;	/* Array of rx rings */
634c869993eSxy 	uint32_t		num_rx_rings;	/* Number of rx rings in use */
635c869993eSxy 	uint32_t		rx_ring_size;	/* Rx descriptor ring size */
636c869993eSxy 	uint32_t		rx_buf_size;	/* Rx buffer size */
637da14cebeSEric Cheng 	igb_rx_group_t		*rx_groups;	/* Array of rx groups */
638da14cebeSEric Cheng 	uint32_t		num_rx_groups;	/* Number of rx groups in use */
639c869993eSxy 
640c869993eSxy 	/*
641c869993eSxy 	 * Transmit Rings
642c869993eSxy 	 */
643c869993eSxy 	igb_tx_ring_t		*tx_rings;	/* Array of tx rings */
644c869993eSxy 	uint32_t		num_tx_rings;	/* Number of tx rings in use */
645c869993eSxy 	uint32_t		tx_ring_size;	/* Tx descriptor ring size */
646c869993eSxy 	uint32_t		tx_buf_size;	/* Tx buffer size */
647c869993eSxy 
648ac7f5757Schenlu chen - Sun Microsystems - Beijing China 	boolean_t		tx_ring_init;
649c869993eSxy 	boolean_t		tx_head_wb_enable; /* Tx head wrtie-back */
650c869993eSxy 	boolean_t		tx_hcksum_enable; /* Tx h/w cksum offload */
65185f496faSRobert Mustacchi 	boolean_t		lso_enable;	/* Large Segment Offload */
652c869993eSxy 	uint32_t		tx_copy_thresh;	/* Tx copy threshold */
653c869993eSxy 	uint32_t		tx_recycle_thresh; /* Tx recycle threshold */
654c869993eSxy 	uint32_t		tx_overload_thresh; /* Tx overload threshold */
655c869993eSxy 	uint32_t		tx_resched_thresh; /* Tx reschedule threshold */
656c869993eSxy 	boolean_t		rx_hcksum_enable; /* Rx h/w cksum offload */
657c869993eSxy 	uint32_t		rx_copy_thresh; /* Rx copy threshold */
658c869993eSxy 	uint32_t		rx_limit_per_intr; /* Rx pkts per interrupt */
659b8d0a377Schenlu chen - Sun Microsystems - Beijing China 
660c869993eSxy 	uint32_t		intr_throttling[MAX_NUM_EITR];
661c869993eSxy 	uint32_t		intr_force;
662c869993eSxy 
663c869993eSxy 	int			intr_type;
664c869993eSxy 	int			intr_cnt;
665c869993eSxy 	int			intr_cap;
666c869993eSxy 	size_t			intr_size;
667c869993eSxy 	uint_t			intr_pri;
668c869993eSxy 	ddi_intr_handle_t	*htable;
669c869993eSxy 	uint32_t		eims_mask;
670da14cebeSEric Cheng 	uint32_t		ims_mask;
671c869993eSxy 
672c869993eSxy 	kmutex_t		gen_lock; /* General lock for device access */
673c869993eSxy 	kmutex_t		watchdog_lock;
674cf8dcc9bSzhefeng xu - Sun Microsystems - Beijing China 	kmutex_t		link_lock;
675ac7f5757Schenlu chen - Sun Microsystems - Beijing China 	kmutex_t		rx_pending_lock;
676c869993eSxy 
677c869993eSxy 	boolean_t		watchdog_enable;
678c869993eSxy 	boolean_t		watchdog_start;
679c869993eSxy 	timeout_id_t		watchdog_tid;
680c869993eSxy 
681c869993eSxy 	boolean_t		unicst_init;
682c869993eSxy 	uint32_t		unicst_avail;
683c869993eSxy 	uint32_t		unicst_total;
684c869993eSxy 	igb_ether_addr_t	unicst_addr[MAX_NUM_UNICAST_ADDRESSES];
685c869993eSxy 	uint32_t		mcast_count;
6866ca163a1Svitezslav batrla - Sun Microsystems - Prague Czech Republic 	uint32_t		mcast_alloc_count;
6876ca163a1Svitezslav batrla - Sun Microsystems - Prague Czech Republic 	uint32_t		mcast_max_num;
6886ca163a1Svitezslav batrla - Sun Microsystems - Prague Czech Republic 	struct ether_addr	*mcast_table;
689c869993eSxy 
690c1e9c696SRobert Mustacchi 	/*
691c1e9c696SRobert Mustacchi 	 * LED related functions
692c1e9c696SRobert Mustacchi 	 */
693c1e9c696SRobert Mustacchi 	boolean_t		igb_led_setup;
694c1e9c696SRobert Mustacchi 
695c869993eSxy 	/*
696c869993eSxy 	 * Kstat definitions
697c869993eSxy 	 */
698c869993eSxy 	kstat_t			*igb_ks;
699c869993eSxy 
70013485e69SGarrett D'Amore 	/*
70113485e69SGarrett D'Amore 	 * Backing store for MAC stats.  These are reported via GLDv3, instead
70213485e69SGarrett D'Amore 	 * of via our private kstat structure.
70313485e69SGarrett D'Amore 	 */
70413485e69SGarrett D'Amore 	uint64_t		stat_tor;	/* rbytes */
70513485e69SGarrett D'Amore 	uint64_t		stat_tpr;	/* rpackets */
70613485e69SGarrett D'Amore 	uint64_t		stat_tot;	/* obytes */
70713485e69SGarrett D'Amore 	uint64_t		stat_tpt;	/* opackets */
70813485e69SGarrett D'Amore 	uint64_t		stat_colc;	/* collisions */
70913485e69SGarrett D'Amore 	uint64_t		stat_mcc;	/* multi colls */
71013485e69SGarrett D'Amore 	uint64_t		stat_scc;	/* single colls */
71113485e69SGarrett D'Amore 	uint64_t		stat_ecol;	/* excessive colls */
71213485e69SGarrett D'Amore 	uint64_t		stat_latecol;	/* late colls */
71313485e69SGarrett D'Amore 	uint64_t		stat_bptc;	/* xmit bcast */
71413485e69SGarrett D'Amore 	uint64_t		stat_mptc;	/* xmit bcast */
71513485e69SGarrett D'Amore 	uint64_t		stat_bprc;	/* recv bcast */
71613485e69SGarrett D'Amore 	uint64_t		stat_mprc;	/* recv mcast */
71713485e69SGarrett D'Amore 	uint64_t		stat_rnbc;	/* recv nobuf */
71813485e69SGarrett D'Amore 	uint64_t		stat_roc;	/* recv toolong */
71913485e69SGarrett D'Amore 	uint64_t		stat_sec;	/* sqe errors */
72013485e69SGarrett D'Amore 	uint64_t		stat_dc;	/* defer */
72113485e69SGarrett D'Amore 	uint64_t		stat_algnerrc;	/* align errors */
72213485e69SGarrett D'Amore 	uint64_t		stat_crcerrs;	/* crc errors */
72313485e69SGarrett D'Amore 	uint64_t		stat_cexterr;	/* carrier extension errors */
72413485e69SGarrett D'Amore 	uint64_t		stat_ruc;	/* recv tooshort */
72513485e69SGarrett D'Amore 	uint64_t		stat_rjc;	/* recv jabber */
72613485e69SGarrett D'Amore 	uint64_t		stat_rxerrc;	/* recv errors */
72713485e69SGarrett D'Amore 
728ac7f5757Schenlu chen - Sun Microsystems - Beijing China 	uint32_t		param_en_1000fdx_cap:1,
729ac7f5757Schenlu chen - Sun Microsystems - Beijing China 				param_en_1000hdx_cap:1,
730ac7f5757Schenlu chen - Sun Microsystems - Beijing China 				param_en_100t4_cap:1,
731ac7f5757Schenlu chen - Sun Microsystems - Beijing China 				param_en_100fdx_cap:1,
732ac7f5757Schenlu chen - Sun Microsystems - Beijing China 				param_en_100hdx_cap:1,
733ac7f5757Schenlu chen - Sun Microsystems - Beijing China 				param_en_10fdx_cap:1,
734ac7f5757Schenlu chen - Sun Microsystems - Beijing China 				param_en_10hdx_cap:1,
735ac7f5757Schenlu chen - Sun Microsystems - Beijing China 				param_1000fdx_cap:1,
736ac7f5757Schenlu chen - Sun Microsystems - Beijing China 				param_1000hdx_cap:1,
737ac7f5757Schenlu chen - Sun Microsystems - Beijing China 				param_100t4_cap:1,
738ac7f5757Schenlu chen - Sun Microsystems - Beijing China 				param_100fdx_cap:1,
739ac7f5757Schenlu chen - Sun Microsystems - Beijing China 				param_100hdx_cap:1,
740ac7f5757Schenlu chen - Sun Microsystems - Beijing China 				param_10fdx_cap:1,
741ac7f5757Schenlu chen - Sun Microsystems - Beijing China 				param_10hdx_cap:1,
742ac7f5757Schenlu chen - Sun Microsystems - Beijing China 				param_autoneg_cap:1,
743ac7f5757Schenlu chen - Sun Microsystems - Beijing China 				param_pause_cap:1,
744ac7f5757Schenlu chen - Sun Microsystems - Beijing China 				param_asym_pause_cap:1,
745ac7f5757Schenlu chen - Sun Microsystems - Beijing China 				param_rem_fault:1,
746ac7f5757Schenlu chen - Sun Microsystems - Beijing China 				param_adv_1000fdx_cap:1,
747ac7f5757Schenlu chen - Sun Microsystems - Beijing China 				param_adv_1000hdx_cap:1,
748ac7f5757Schenlu chen - Sun Microsystems - Beijing China 				param_adv_100t4_cap:1,
749ac7f5757Schenlu chen - Sun Microsystems - Beijing China 				param_adv_100fdx_cap:1,
750ac7f5757Schenlu chen - Sun Microsystems - Beijing China 				param_adv_100hdx_cap:1,
751ac7f5757Schenlu chen - Sun Microsystems - Beijing China 				param_adv_10fdx_cap:1,
752ac7f5757Schenlu chen - Sun Microsystems - Beijing China 				param_adv_10hdx_cap:1,
753ac7f5757Schenlu chen - Sun Microsystems - Beijing China 				param_adv_autoneg_cap:1,
754ac7f5757Schenlu chen - Sun Microsystems - Beijing China 				param_adv_pause_cap:1,
755ac7f5757Schenlu chen - Sun Microsystems - Beijing China 				param_adv_asym_pause_cap:1,
756ac7f5757Schenlu chen - Sun Microsystems - Beijing China 				param_adv_rem_fault:1,
757ac7f5757Schenlu chen - Sun Microsystems - Beijing China 				param_lp_1000fdx_cap:1,
758ac7f5757Schenlu chen - Sun Microsystems - Beijing China 				param_lp_1000hdx_cap:1,
759ac7f5757Schenlu chen - Sun Microsystems - Beijing China 				param_lp_100t4_cap:1;
760ac7f5757Schenlu chen - Sun Microsystems - Beijing China 
761ac7f5757Schenlu chen - Sun Microsystems - Beijing China 	uint32_t		param_lp_100fdx_cap:1,
762ac7f5757Schenlu chen - Sun Microsystems - Beijing China 				param_lp_100hdx_cap:1,
763ac7f5757Schenlu chen - Sun Microsystems - Beijing China 				param_lp_10fdx_cap:1,
764ac7f5757Schenlu chen - Sun Microsystems - Beijing China 				param_lp_10hdx_cap:1,
765ac7f5757Schenlu chen - Sun Microsystems - Beijing China 				param_lp_autoneg_cap:1,
766ac7f5757Schenlu chen - Sun Microsystems - Beijing China 				param_lp_pause_cap:1,
767ac7f5757Schenlu chen - Sun Microsystems - Beijing China 				param_lp_asym_pause_cap:1,
768ac7f5757Schenlu chen - Sun Microsystems - Beijing China 				param_lp_rem_fault:1,
769ac7f5757Schenlu chen - Sun Microsystems - Beijing China 				param_pad_to_32:24;
770c869993eSxy 
7718bb4b220Sgl 	/*
7728bb4b220Sgl 	 * FMA capabilities
7738bb4b220Sgl 	 */
7748bb4b220Sgl 	int			fm_capabilities;
7758bb4b220Sgl 
776d11274aaSPaul Guo 	ulong_t			page_size;
7778d55b806SRobert Mustacchi 	ddi_ufm_handle_t	*igb_ufmh;
778*2509632aSRobert Mustacchi 	igb_sensors_t		igb_sensors;
779c869993eSxy } igb_t;
780c869993eSxy 
781c869993eSxy typedef struct igb_stat {
782c869993eSxy 
783c869993eSxy 	kstat_named_t reset_count;	/* Reset Count */
784b8d0a377Schenlu chen - Sun Microsystems - Beijing China 	kstat_named_t dout_sync;	/* DMA out of sync */
785b8d0a377Schenlu chen - Sun Microsystems - Beijing China #ifdef IGB_DEBUG
786c869993eSxy 	kstat_named_t rx_frame_error;	/* Rx Error in Packet */
787