1c869993eSxy /* 2c869993eSxy * CDDL HEADER START 3c869993eSxy * 480a11ad2Schenlu chen - Sun Microsystems - Beijing China * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5c869993eSxy * The contents of this file are subject to the terms of the 6c869993eSxy * Common Development and Distribution License (the "License"). 7c869993eSxy * You may not use this file except in compliance with the License. 8c869993eSxy * 980a11ad2Schenlu chen - Sun Microsystems - Beijing China * You can obtain a copy of the license at: 1080a11ad2Schenlu chen - Sun Microsystems - Beijing China * http://www.opensolaris.org/os/licensing. 11c869993eSxy * See the License for the specific language governing permissions 12c869993eSxy * and limitations under the License. 13c869993eSxy * 1480a11ad2Schenlu chen - Sun Microsystems - Beijing China * When using or redistributing this file, you may do so under the 1580a11ad2Schenlu chen - Sun Microsystems - Beijing China * License only. No other modification of this header is permitted. 1680a11ad2Schenlu chen - Sun Microsystems - Beijing China * 17c869993eSxy * If applicable, add the following below this CDDL HEADER, with the 18c869993eSxy * fields enclosed by brackets "[]" replaced with your own identifying 19c869993eSxy * information: Portions Copyright [yyyy] [name of copyright owner] 20c869993eSxy * 21c869993eSxy * CDDL HEADER END 22c869993eSxy */ 23c869993eSxy 24da14cebeSEric Cheng /* 2580a11ad2Schenlu chen - Sun Microsystems - Beijing China * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 26*d11274aaSPaul Guo * Use is subject to license terms. 27c869993eSxy */ 28c869993eSxy 29c869993eSxy #ifndef _IGB_SW_H 30c869993eSxy #define _IGB_SW_H 31c869993eSxy 32c869993eSxy #ifdef __cplusplus 33c869993eSxy extern "C" { 34c869993eSxy #endif 35c869993eSxy 36c869993eSxy #include <sys/types.h> 37c869993eSxy #include <sys/conf.h> 38c869993eSxy #include <sys/debug.h> 39c869993eSxy #include <sys/stropts.h> 40c869993eSxy #include <sys/stream.h> 41c869993eSxy #include <sys/strsun.h> 42c869993eSxy #include <sys/strlog.h> 43c869993eSxy #include <sys/kmem.h> 44c869993eSxy #include <sys/stat.h> 45c869993eSxy #include <sys/kstat.h> 46c869993eSxy #include <sys/modctl.h> 47c869993eSxy #include <sys/errno.h> 48c869993eSxy #include <sys/dlpi.h> 49da14cebeSEric Cheng #include <sys/mac_provider.h> 50c869993eSxy #include <sys/mac_ether.h> 51c869993eSxy #include <sys/vlan.h> 52c869993eSxy #include <sys/ddi.h> 53c869993eSxy #include <sys/sunddi.h> 54c869993eSxy #include <sys/pci.h> 55c869993eSxy #include <sys/pcie.h> 56c869993eSxy #include <sys/sdt.h> 57c869993eSxy #include <sys/ethernet.h> 58c869993eSxy #include <sys/pattr.h> 59c869993eSxy #include <sys/strsubr.h> 60c869993eSxy #include <sys/netlb.h> 61c869993eSxy #include <sys/random.h> 62c869993eSxy #include <inet/common.h> 63*d11274aaSPaul Guo #include <inet/tcp.h> 64c869993eSxy #include <inet/ip.h> 65c869993eSxy #include <inet/mi.h> 66c869993eSxy #include <inet/nd.h> 678bb4b220Sgl #include <sys/ddifm.h> 688bb4b220Sgl #include <sys/fm/protocol.h> 698bb4b220Sgl #include <sys/fm/util.h> 708bb4b220Sgl #include <sys/fm/io/ddi.h> 71c869993eSxy #include "igb_api.h" 72c869993eSxy #include "igb_82575.h" 73c869993eSxy 74c869993eSxy 75c869993eSxy #define MODULE_NAME "igb" /* module name */ 76c869993eSxy 77c869993eSxy #define IGB_SUCCESS DDI_SUCCESS 78c869993eSxy #define IGB_FAILURE DDI_FAILURE 79c869993eSxy 80c869993eSxy #define IGB_UNKNOWN 0x00 81c869993eSxy #define IGB_INITIALIZED 0x01 82c869993eSxy #define IGB_STARTED 0x02 83c869993eSxy #define IGB_SUSPENDED 0x04 84c869993eSxy 85c869993eSxy #define IGB_INTR_NONE 0 86c869993eSxy #define IGB_INTR_MSIX 1 87c869993eSxy #define IGB_INTR_MSI 2 88c869993eSxy #define IGB_INTR_LEGACY 3 89c869993eSxy 9080a11ad2Schenlu chen - Sun Microsystems - Beijing China #define IGB_ADAPTER_REGSET 1 /* mapping adapter registers */ 9180a11ad2Schenlu chen - Sun Microsystems - Beijing China #define IGB_ADAPTER_MSIXTAB 4 /* mapping msi-x table */ 9280a11ad2Schenlu chen - Sun Microsystems - Beijing China 93da14cebeSEric Cheng #define IGB_NO_POLL -1 94da14cebeSEric Cheng #define IGB_NO_FREE_SLOT -1 95da14cebeSEric Cheng 96c869993eSxy #define MAX_NUM_UNICAST_ADDRESSES E1000_RAR_ENTRIES 97c869993eSxy #define MAX_NUM_MULTICAST_ADDRESSES 256 98*d11274aaSPaul Guo #define MAX_COOKIE 18 99c869993eSxy #define MIN_NUM_TX_DESC 2 100c869993eSxy 10180a11ad2Schenlu chen - Sun Microsystems - Beijing China /* 10280a11ad2Schenlu chen - Sun Microsystems - Beijing China * Number of settings for interrupt throttle rate (ITR). There is one of 10380a11ad2Schenlu chen - Sun Microsystems - Beijing China * these per msi-x vector and it needs to be the maximum of all silicon 10480a11ad2Schenlu chen - Sun Microsystems - Beijing China * types supported by this driver. 10580a11ad2Schenlu chen - Sun Microsystems - Beijing China */ 10680a11ad2Schenlu chen - Sun Microsystems - Beijing China #define MAX_NUM_EITR 25 10780a11ad2Schenlu chen - Sun Microsystems - Beijing China 108c869993eSxy /* 109c869993eSxy * Maximum values for user configurable parameters 110c869993eSxy */ 111c869993eSxy #define MAX_TX_RING_SIZE 4096 112c869993eSxy #define MAX_RX_RING_SIZE 4096 113da14cebeSEric Cheng #define MAX_RX_GROUP_NUM 4 114c869993eSxy 115c869993eSxy #define MAX_MTU 9000 116c869993eSxy #define MAX_RX_LIMIT_PER_INTR 4096 117c869993eSxy #define MAX_RX_INTR_DELAY 65535 118c869993eSxy #define MAX_RX_INTR_ABS_DELAY 65535 119c869993eSxy #define MAX_TX_INTR_DELAY 65535 120c869993eSxy #define MAX_TX_INTR_ABS_DELAY 65535 121c869993eSxy 122c869993eSxy #define MAX_RX_COPY_THRESHOLD 9216 123c869993eSxy #define MAX_TX_COPY_THRESHOLD 9216 124c869993eSxy #define MAX_TX_RECYCLE_THRESHOLD DEFAULT_TX_RING_SIZE 125c869993eSxy #define MAX_TX_OVERLOAD_THRESHOLD DEFAULT_TX_RING_SIZE 126c869993eSxy #define MAX_TX_RESCHED_THRESHOLD DEFAULT_TX_RING_SIZE 127c869993eSxy 128c869993eSxy /* 129c869993eSxy * Minimum values for user configurable parameters 130c869993eSxy */ 131c869993eSxy #define MIN_TX_RING_SIZE 64 132c869993eSxy #define MIN_RX_RING_SIZE 64 133da14cebeSEric Cheng #define MIN_RX_GROUP_NUM 1 134c869993eSxy 135c869993eSxy #define MIN_MTU ETHERMIN 136c869993eSxy #define MIN_RX_LIMIT_PER_INTR 16 137c869993eSxy #define MIN_RX_INTR_DELAY 0 138c869993eSxy #define MIN_RX_INTR_ABS_DELAY 0 139c869993eSxy #define MIN_TX_INTR_DELAY 0 140c869993eSxy #define MIN_TX_INTR_ABS_DELAY 0 141c869993eSxy #define MIN_RX_COPY_THRESHOLD 0 142c869993eSxy #define MIN_TX_COPY_THRESHOLD 0 143c869993eSxy #define MIN_TX_RECYCLE_THRESHOLD MIN_NUM_TX_DESC 144c869993eSxy #define MIN_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 145c869993eSxy #define MIN_TX_RESCHED_THRESHOLD MIN_NUM_TX_DESC 146c869993eSxy 147c869993eSxy /* 148c869993eSxy * Default values for user configurable parameters 149c869993eSxy */ 150c869993eSxy #define DEFAULT_TX_RING_SIZE 512 151c869993eSxy #define DEFAULT_RX_RING_SIZE 512 152da14cebeSEric Cheng #define DEFAULT_RX_GROUP_NUM 1 153c869993eSxy 154c869993eSxy #define DEFAULT_MTU ETHERMTU 155c869993eSxy #define DEFAULT_RX_LIMIT_PER_INTR 256 156c869993eSxy #define DEFAULT_RX_INTR_DELAY 0 157c869993eSxy #define DEFAULT_RX_INTR_ABS_DELAY 0 158c869993eSxy #define DEFAULT_TX_INTR_DELAY 300 159c869993eSxy #define DEFAULT_TX_INTR_ABS_DELAY 0 160c869993eSxy #define DEFAULT_RX_COPY_THRESHOLD 128 161c869993eSxy #define DEFAULT_TX_COPY_THRESHOLD 512 162*d11274aaSPaul Guo #define DEFAULT_TX_RECYCLE_THRESHOLD (MAX_COOKIE + 1) 163c869993eSxy #define DEFAULT_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 164c869993eSxy #define DEFAULT_TX_RESCHED_THRESHOLD 128 165c869993eSxy 166*d11274aaSPaul Guo #define IGB_LSO_MAXLEN 65535 167*d11274aaSPaul Guo 168c869993eSxy #define TX_DRAIN_TIME 200 169c869993eSxy #define RX_DRAIN_TIME 200 170c869993eSxy 171c869993eSxy #define STALL_WATCHDOG_TIMEOUT 8 /* 8 seconds */ 172c869993eSxy #define MAX_LINK_DOWN_TIMEOUT 8 /* 8 seconds */ 173c869993eSxy 174c869993eSxy /* 175c869993eSxy * Defined for IP header alignment. 176c869993eSxy */ 177c869993eSxy #define IPHDR_ALIGN_ROOM 2 178c869993eSxy 179c869993eSxy /* 180c869993eSxy * Bit flags for attach_progress 181c869993eSxy */ 182c869993eSxy #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 183c869993eSxy #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 184c869993eSxy #define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */ 185c869993eSxy #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */ 186c869993eSxy #define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */ 187c869993eSxy #define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */ 188c869993eSxy #define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */ 189b8d0a377Schenlu chen - Sun Microsystems - Beijing China #define ATTACH_PROGRESS_INIT_ADAPTER 0x0080 /* Adapter initialized */ 190b8d0a377Schenlu chen - Sun Microsystems - Beijing China #define ATTACH_PROGRESS_ALLOC_DMA 0x0100 /* DMA resources allocated */ 191c869993eSxy #define ATTACH_PROGRESS_STATS 0x0200 /* Kstats created */ 192c869993eSxy #define ATTACH_PROGRESS_NDD 0x0400 /* NDD initialized */ 193c869993eSxy #define ATTACH_PROGRESS_MAC 0x0800 /* MAC registered */ 194c869993eSxy #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */ 1958bb4b220Sgl #define ATTACH_PROGRESS_FMINIT 0x2000 /* FMA initialized */ 196c869993eSxy 197c869993eSxy #define PROP_ADV_AUTONEG_CAP "adv_autoneg_cap" 198c869993eSxy #define PROP_ADV_1000FDX_CAP "adv_1000fdx_cap" 199c869993eSxy #define PROP_ADV_1000HDX_CAP "adv_1000hdx_cap" 200c869993eSxy #define PROP_ADV_100FDX_CAP "adv_100fdx_cap" 201c869993eSxy #define PROP_ADV_100HDX_CAP "adv_100hdx_cap" 202c869993eSxy #define PROP_ADV_10FDX_CAP "adv_10fdx_cap" 203c869993eSxy #define PROP_ADV_10HDX_CAP "adv_10hdx_cap" 204c869993eSxy #define PROP_DEFAULT_MTU "default_mtu" 205c869993eSxy #define PROP_FLOW_CONTROL "flow_control" 206c869993eSxy #define PROP_TX_RING_SIZE "tx_ring_size" 207c869993eSxy #define PROP_RX_RING_SIZE "rx_ring_size" 208da14cebeSEric Cheng #define PROP_MR_ENABLE "mr_enable" 209da14cebeSEric Cheng #define PROP_RX_GROUP_NUM "rx_group_number" 210c869993eSxy 211c869993eSxy #define PROP_INTR_FORCE "intr_force" 212c869993eSxy #define PROP_TX_HCKSUM_ENABLE "tx_hcksum_enable" 213c869993eSxy #define PROP_RX_HCKSUM_ENABLE "rx_hcksum_enable" 214c869993eSxy #define PROP_LSO_ENABLE "lso_enable" 215c869993eSxy #define PROP_TX_HEAD_WB_ENABLE "tx_head_wb_enable" 216c869993eSxy #define PROP_TX_COPY_THRESHOLD "tx_copy_threshold" 217c869993eSxy #define PROP_TX_RECYCLE_THRESHOLD "tx_recycle_threshold" 218c869993eSxy #define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold" 219c869993eSxy #define PROP_TX_RESCHED_THRESHOLD "tx_resched_threshold" 220c869993eSxy #define PROP_RX_COPY_THRESHOLD "rx_copy_threshold" 221c869993eSxy #define PROP_RX_LIMIT_PER_INTR "rx_limit_per_intr" 222c869993eSxy #define PROP_INTR_THROTTLING "intr_throttling" 223c869993eSxy 224c869993eSxy #define IGB_LB_NONE 0 225c869993eSxy #define IGB_LB_EXTERNAL 1 226c869993eSxy #define IGB_LB_INTERNAL_MAC 2 227c869993eSxy #define IGB_LB_INTERNAL_PHY 3 228c869993eSxy #define IGB_LB_INTERNAL_SERDES 4 229c869993eSxy 230c869993eSxy /* 231c869993eSxy * Shorthand for the NDD parameters 232c869993eSxy */ 233c869993eSxy #define param_autoneg_cap nd_params[PARAM_AUTONEG_CAP].val 234c869993eSxy #define param_pause_cap nd_params[PARAM_PAUSE_CAP].val 235c869993eSxy #define param_asym_pause_cap nd_params[PARAM_ASYM_PAUSE_CAP].val 236c869993eSxy #define param_1000fdx_cap nd_params[PARAM_1000FDX_CAP].val 237c869993eSxy #define param_1000hdx_cap nd_params[PARAM_1000HDX_CAP].val 238c869993eSxy #define param_100t4_cap nd_params[PARAM_100T4_CAP].val 239c869993eSxy #define param_100fdx_cap nd_params[PARAM_100FDX_CAP].val 240c869993eSxy #define param_100hdx_cap nd_params[PARAM_100HDX_CAP].val 241c869993eSxy #define param_10fdx_cap nd_params[PARAM_10FDX_CAP].val 242c869993eSxy #define param_10hdx_cap nd_params[PARAM_10HDX_CAP].val 243c869993eSxy #define param_rem_fault nd_params[PARAM_REM_FAULT].val 244c869993eSxy 245c869993eSxy #define param_adv_autoneg_cap nd_params[PARAM_ADV_AUTONEG_CAP].val 246c869993eSxy #define param_adv_pause_cap nd_params[PARAM_ADV_PAUSE_CAP].val 247c869993eSxy #define param_adv_asym_pause_cap nd_params[PARAM_ADV_ASYM_PAUSE_CAP].val 248c869993eSxy #define param_adv_1000fdx_cap nd_params[PARAM_ADV_1000FDX_CAP].val 249c869993eSxy #define param_adv_1000hdx_cap nd_params[PARAM_ADV_1000HDX_CAP].val 250c869993eSxy #define param_adv_100t4_cap nd_params[PARAM_ADV_100T4_CAP].val 251c869993eSxy #define param_adv_100fdx_cap nd_params[PARAM_ADV_100FDX_CAP].val 252c869993eSxy #define param_adv_100hdx_cap nd_params[PARAM_ADV_100HDX_CAP].val 253c869993eSxy #define param_adv_10fdx_cap nd_params[PARAM_ADV_10FDX_CAP].val 254c869993eSxy #define param_adv_10hdx_cap nd_params[PARAM_ADV_10HDX_CAP].val 255c869993eSxy #define param_adv_rem_fault nd_params[PARAM_ADV_REM_FAULT].val 256c869993eSxy 257c869993eSxy #define param_lp_autoneg_cap nd_params[PARAM_LP_AUTONEG_CAP].val 258c869993eSxy #define param_lp_pause_cap nd_params[PARAM_LP_PAUSE_CAP].val 259c869993eSxy #define param_lp_asym_pause_cap nd_params[PARAM_LP_ASYM_PAUSE_CAP].val 260c869993eSxy #define param_lp_1000fdx_cap nd_params[PARAM_LP_1000FDX_CAP].val 261c869993eSxy #define param_lp_1000hdx_cap nd_params[PARAM_LP_1000HDX_CAP].val 262c869993eSxy #define param_lp_100t4_cap nd_params[PARAM_LP_100T4_CAP].val 263c869993eSxy #define param_lp_100fdx_cap nd_params[PARAM_LP_100FDX_CAP].val 264c869993eSxy #define param_lp_100hdx_cap nd_params[PARAM_LP_100HDX_CAP].val 265c869993eSxy #define param_lp_10fdx_cap nd_params[PARAM_LP_10FDX_CAP].val 266c869993eSxy #define param_lp_10hdx_cap nd_params[PARAM_LP_10HDX_CAP].val 267c869993eSxy #define param_lp_rem_fault nd_params[PARAM_LP_REM_FAULT].val 268c869993eSxy 269c869993eSxy enum ioc_reply { 270c869993eSxy IOC_INVAL = -1, /* bad, NAK with EINVAL */ 271c869993eSxy IOC_DONE, /* OK, reply sent */ 272c869993eSxy IOC_ACK, /* OK, just send ACK */ 273c869993eSxy IOC_REPLY /* OK, just send reply */ 274c869993eSxy }; 275c869993eSxy 276*d11274aaSPaul Guo /* 277*d11274aaSPaul Guo * For s/w context extraction from a tx frame 278*d11274aaSPaul Guo */ 279*d11274aaSPaul Guo #define TX_CXT_SUCCESS 0 280*d11274aaSPaul Guo #define TX_CXT_E_LSO_CSUM (-1) 281*d11274aaSPaul Guo #define TX_CXT_E_ETHER_TYPE (-2) 282c869993eSxy 283c869993eSxy #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area)->dma_handle, \ 284c869993eSxy 0, 0, (flag))) 285c869993eSxy 286c869993eSxy /* 287c869993eSxy * Defined for ring index operations 288c869993eSxy * ASSERT(index < limit) 289c869993eSxy * ASSERT(step < limit) 290c869993eSxy * ASSERT(index1 < limit) 291c869993eSxy * ASSERT(index2 < limit) 292c869993eSxy */ 293c869993eSxy #define NEXT_INDEX(index, step, limit) (((index) + (step)) < (limit) ? \ 294c869993eSxy (index) + (step) : (index) + (step) - (limit)) 295c869993eSxy #define PREV_INDEX(index, step, limit) ((index) >= (step) ? \ 296c869993eSxy (index) - (step) : (index) + (limit) - (step)) 297c869993eSxy #define OFFSET(index1, index2, limit) ((index1) <= (index2) ? \ 298c869993eSxy (index2) - (index1) : (index2) + (limit) - (index1)) 299c869993eSxy 300c869993eSxy #define LINK_LIST_INIT(_LH) \ 301c869993eSxy (_LH)->head = (_LH)->tail = NULL 302c869993eSxy 303c869993eSxy #define LIST_GET_HEAD(_LH) ((single_link_t *)((_LH)->head)) 304c869993eSxy 305c869993eSxy #define LIST_POP_HEAD(_LH) \ 306c869993eSxy (single_link_t *)(_LH)->head; \ 307c869993eSxy { \ 308c869993eSxy if ((_LH)->head != NULL) { \ 309c869993eSxy (_LH)->head = (_LH)->head->link; \ 310c869993eSxy if ((_LH)->head == NULL) \ 311c869993eSxy (_LH)->tail = NULL; \ 312c869993eSxy } \ 313c869993eSxy } 314c869993eSxy 315c869993eSxy #define LIST_GET_TAIL(_LH) ((single_link_t *)((_LH)->tail)) 316c869993eSxy 317c869993eSxy #define LIST_PUSH_TAIL(_LH, _E) \ 318c869993eSxy if ((_LH)->tail != NULL) { \ 319c869993eSxy (_LH)->tail->link = (single_link_t *)(_E); \ 320c869993eSxy (_LH)->tail = (single_link_t *)(_E); \ 321c869993eSxy } else { \ 322c869993eSxy (_LH)->head = (_LH)->tail = (single_link_t *)(_E); \ 323c869993eSxy } \ 324c869993eSxy (_E)->link = NULL; 325c869993eSxy 326c869993eSxy #define LIST_GET_NEXT(_LH, _E) \ 327c869993eSxy (((_LH)->tail == (single_link_t *)(_E)) ? \ 328c869993eSxy NULL : ((single_link_t *)(_E))->link) 329c869993eSxy 330c869993eSxy 331c869993eSxy typedef struct single_link { 332c869993eSxy struct single_link *link; 333c869993eSxy } single_link_t; 334c869993eSxy 335c869993eSxy typedef struct link_list { 336c869993eSxy single_link_t *head; 337c869993eSxy single_link_t *tail; 338c869993eSxy } link_list_t; 339c869993eSxy 340c869993eSxy /* 341c869993eSxy * Property lookups 342c869993eSxy */ 343c869993eSxy #define IGB_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 344c869993eSxy DDI_PROP_DONTPASS, (n)) 345c869993eSxy #define IGB_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 346c869993eSxy DDI_PROP_DONTPASS, (n), -1) 347c869993eSxy 348c869993eSxy 34980a11ad2Schenlu chen - Sun Microsystems - Beijing China /* capability/feature flags */ 35080a11ad2Schenlu chen - Sun Microsystems - Beijing China #define IGB_FLAG_HAS_DCA (1 << 0) /* has Direct Cache Access */ 35180a11ad2Schenlu chen - Sun Microsystems - Beijing China #define IGB_FLAG_VMDQ_POOL (1 << 1) /* has vmdq capability */ 35280a11ad2Schenlu chen - Sun Microsystems - Beijing China #define IGB_FLAG_NEED_CTX_IDX (1 << 2) /* context descriptor needs index */ 35380a11ad2Schenlu chen - Sun Microsystems - Beijing China 35480a11ad2Schenlu chen - Sun Microsystems - Beijing China /* function pointer for nic-specific functions */ 35580a11ad2Schenlu chen - Sun Microsystems - Beijing China typedef void (*igb_nic_func_t)(struct igb *); 35680a11ad2Schenlu chen - Sun Microsystems - Beijing China 35780a11ad2Schenlu chen - Sun Microsystems - Beijing China /* adapter-specific info for each supported device type */ 35880a11ad2Schenlu chen - Sun Microsystems - Beijing China typedef struct adapter_info { 35980a11ad2Schenlu chen - Sun Microsystems - Beijing China /* limits */ 36080a11ad2Schenlu chen - Sun Microsystems - Beijing China uint32_t max_rx_que_num; /* maximum number of rx queues */ 36180a11ad2Schenlu chen - Sun Microsystems - Beijing China uint32_t min_rx_que_num; /* minimum number of rx queues */ 36280a11ad2Schenlu chen - Sun Microsystems - Beijing China uint32_t def_rx_que_num; /* default number of rx queues */ 36380a11ad2Schenlu chen - Sun Microsystems - Beijing China uint32_t max_tx_que_num; /* maximum number of tx queues */ 36480a11ad2Schenlu chen - Sun Microsystems - Beijing China uint32_t min_tx_que_num; /* minimum number of tx queues */ 36580a11ad2Schenlu chen - Sun Microsystems - Beijing China uint32_t def_tx_que_num; /* default number of tx queues */ 36680a11ad2Schenlu chen - Sun Microsystems - Beijing China uint32_t max_intr_throttle; /* maximum interrupt throttle */ 36780a11ad2Schenlu chen - Sun Microsystems - Beijing China uint32_t min_intr_throttle; /* minimum interrupt throttle */ 36880a11ad2Schenlu chen - Sun Microsystems - Beijing China uint32_t def_intr_throttle; /* default interrupt throttle */ 36980a11ad2Schenlu chen - Sun Microsystems - Beijing China /* function pointers */ 37080a11ad2Schenlu chen - Sun Microsystems - Beijing China igb_nic_func_t enable_intr; /* enable adapter interrupts */ 37180a11ad2Schenlu chen - Sun Microsystems - Beijing China igb_nic_func_t setup_msix; /* set up msi-x vectors */ 37280a11ad2Schenlu chen - Sun Microsystems - Beijing China /* capabilities */ 37380a11ad2Schenlu chen - Sun Microsystems - Beijing China uint32_t flags; /* capability flags */ 374b8d0a377Schenlu chen - Sun Microsystems - Beijing China uint32_t rxdctl_mask; /* mask for RXDCTL register */ 37580a11ad2Schenlu chen - Sun Microsystems - Beijing China } adapter_info_t; 37680a11ad2Schenlu chen - Sun Microsystems - Beijing China 377c869993eSxy /* 378c869993eSxy * Named Data (ND) Parameter Management Structure 379c869993eSxy */ 380c869993eSxy typedef struct { 381c869993eSxy struct igb *private; 382c869993eSxy uint32_t info; 383c869993eSxy uint32_t min; 384c869993eSxy uint32_t max; 385c869993eSxy uint32_t val; 386c869993eSxy char *name; 387c869993eSxy } nd_param_t; 388c869993eSxy 389c869993eSxy /* 390c869993eSxy * NDD parameter indexes, divided into: 391c869993eSxy * 392c869993eSxy * read-only parameters describing the hardware's capabilities 393c869993eSxy * read-write parameters controlling the advertised capabilities 394c869993eSxy * read-only parameters describing the partner's capabilities 395c869993eSxy * read-write parameters controlling the force speed and duplex 396c869993eSxy * read-only parameters describing the link state 397c869993eSxy * read-only parameters describing the driver properties 398c869993eSxy * read-write parameters controlling the driver properties 399c869993eSxy */ 400c869993eSxy enum { 401c869993eSxy PARAM_AUTONEG_CAP, 402c869993eSxy PARAM_PAUSE_CAP, 403c869993eSxy PARAM_ASYM_PAUSE_CAP, 404c869993eSxy PARAM_1000FDX_CAP, 405c869993eSxy PARAM_1000HDX_CAP, 406c869993eSxy PARAM_100T4_CAP, 407c869993eSxy PARAM_100FDX_CAP, 408c869993eSxy PARAM_100HDX_CAP, 409c869993eSxy PARAM_10FDX_CAP, 410c869993eSxy PARAM_10HDX_CAP, 411c869993eSxy PARAM_REM_FAULT, 412c869993eSxy 413c869993eSxy PARAM_ADV_AUTONEG_CAP, 414c869993eSxy PARAM_ADV_PAUSE_CAP, 415c869993eSxy PARAM_ADV_ASYM_PAUSE_CAP, 416c869993eSxy PARAM_ADV_1000FDX_CAP, 417c869993eSxy PARAM_ADV_1000HDX_CAP, 418c869993eSxy PARAM_ADV_100T4_CAP, 419c869993eSxy PARAM_ADV_100FDX_CAP, 420c869993eSxy PARAM_ADV_100HDX_CAP, 421c869993eSxy PARAM_ADV_10FDX_CAP, 422c869993eSxy PARAM_ADV_10HDX_CAP, 423c869993eSxy PARAM_ADV_REM_FAULT, 424c869993eSxy 425c869993eSxy PARAM_LP_AUTONEG_CAP, 426c869993eSxy PARAM_LP_PAUSE_CAP, 427c869993eSxy PARAM_LP_ASYM_PAUSE_CAP, 428c869993eSxy PARAM_LP_1000FDX_CAP, 429c869993eSxy PARAM_LP_1000HDX_CAP, 430c869993eSxy PARAM_LP_100T4_CAP, 431c869993eSxy PARAM_LP_100FDX_CAP, 432c869993eSxy PARAM_LP_100HDX_CAP, 433c869993eSxy PARAM_LP_10FDX_CAP, 434c869993eSxy PARAM_LP_10HDX_CAP, 435c869993eSxy PARAM_LP_REM_FAULT, 436c869993eSxy 437c869993eSxy PARAM_LINK_STATUS, 438c869993eSxy PARAM_LINK_SPEED, 439c869993eSxy PARAM_LINK_DUPLEX, 440c869993eSxy 441c869993eSxy PARAM_COUNT 442c869993eSxy }; 443c869993eSxy 444c869993eSxy typedef union igb_ether_addr { 445c869993eSxy struct { 446c869993eSxy uint32_t high; 447c869993eSxy uint32_t low; 448c869993eSxy } reg; 449c869993eSxy struct { 450c869993eSxy uint8_t set; 451da14cebeSEric Cheng uint8_t group_index; 452c869993eSxy uint8_t addr[ETHERADDRL]; 453c869993eSxy } mac; 454c869993eSxy } igb_ether_addr_t; 455c869993eSxy 456c869993eSxy typedef enum { 457c869993eSxy USE_NONE, 458c869993eSxy USE_COPY, 459c869993eSxy USE_DMA 460c869993eSxy } tx_type_t; 461c869993eSxy 462c869993eSxy typedef enum { 463c869993eSxy RCB_FREE, 464c869993eSxy RCB_SENDUP 465c869993eSxy } rcb_state_t; 466c869993eSxy 467*d11274aaSPaul Guo typedef struct tx_context { 468c869993eSxy uint32_t hcksum_flags; 469c869993eSxy uint32_t ip_hdr_len; 470c869993eSxy uint32_t mac_hdr_len; 471c869993eSxy uint32_t l4_proto; 472*d11274aaSPaul Guo uint32_t mss; 473*d11274aaSPaul Guo uint32_t l4_hdr_len; 474*d11274aaSPaul Guo boolean_t lso_flag; 475*d11274aaSPaul Guo } tx_context_t; 476c869993eSxy 477c869993eSxy /* Hold address/length of each DMA segment */ 478c869993eSxy typedef struct sw_desc { 479c869993eSxy uint64_t address; 480c869993eSxy size_t length; 481c869993eSxy } sw_desc_t; 482c869993eSxy 483c869993eSxy /* Handles and addresses of DMA buffer */ 484c869993eSxy typedef struct dma_buffer { 485c869993eSxy caddr_t address; /* Virtual address */ 486c869993eSxy uint64_t dma_address; /* DMA (Hardware) address */ 487c869993eSxy ddi_acc_handle_t acc_handle; /* Data access handle */ 488c869993eSxy ddi_dma_handle_t dma_handle; /* DMA handle */ 489c869993eSxy size_t size; /* Buffer size */ 490c869993eSxy size_t len; /* Data length in the buffer */ 491c869993eSxy } dma_buffer_t; 492c869993eSxy 493c869993eSxy /* 494c869993eSxy * Tx Control Block 495c869993eSxy */ 496c869993eSxy typedef struct tx_control_block { 497c869993eSxy single_link_t link; 498c869993eSxy uint32_t frag_num; 499c869993eSxy uint32_t desc_num; 500c869993eSxy mblk_t *mp; 501c869993eSxy tx_type_t tx_type; 502c869993eSxy ddi_dma_handle_t tx_dma_handle; 503c869993eSxy dma_buffer_t tx_buf; 504c869993eSxy sw_desc_t desc[MAX_COOKIE]; 505c869993eSxy } tx_control_block_t; 506c869993eSxy 507c869993eSxy /* 508c869993eSxy * RX Control Block 509c869993eSxy */ 510c869993eSxy typedef struct rx_control_block { 511c869993eSxy mblk_t *mp; 512c869993eSxy rcb_state_t state; 513c869993eSxy dma_buffer_t rx_buf; 514c869993eSxy frtn_t free_rtn; 515c869993eSxy struct igb_rx_ring *rx_ring; 516c869993eSxy } rx_control_block_t; 517c869993eSxy 518c869993eSxy /* 519c869993eSxy * Software Data Structure for Tx Ring 520c869993eSxy */ 521c869993eSxy typedef struct igb_tx_ring { 522c869993eSxy uint32_t index; /* Ring index */ 523da14cebeSEric Cheng uint32_t intr_vector; /* Interrupt vector index */ 524c869993eSxy 525c869993eSxy /* 526c869993eSxy * Mutexes 527c869993eSxy */ 528c869993eSxy kmutex_t tx_lock; 529c869993eSxy kmutex_t recycle_lock; 530c869993eSxy kmutex_t tcb_head_lock; 531c869993eSxy kmutex_t tcb_tail_lock; 532c869993eSxy 533c869993eSxy /* 534c869993eSxy * Tx descriptor ring definitions 535c869993eSxy */ 536c869993eSxy dma_buffer_t tbd_area; 537c869993eSxy union e1000_adv_tx_desc *tbd_ring; 538c869993eSxy uint32_t tbd_head; /* Index of next tbd to recycle */ 539c869993eSxy uint32_t tbd_tail; /* Index of next tbd to transmit */ 540c869993eSxy uint32_t tbd_free; /* Number of free tbd */ 541c869993eSxy 542c869993eSxy /* 543c869993eSxy * Tx control block list definitions 544c869993eSxy */ 545c869993eSxy tx_control_block_t *tcb_area; 546c869993eSxy tx_control_block_t **work_list; 547c869993eSxy tx_control_block_t **free_list; 548c869993eSxy uint32_t tcb_head; /* Head index of free list */ 549c869993eSxy uint32_t tcb_tail; /* Tail index of free list */ 550c869993eSxy uint32_t tcb_free; /* Number of free tcb in free list */ 551c869993eSxy 552c869993eSxy uint32_t *tbd_head_wb; /* Head write-back */ 553c869993eSxy uint32_t (*tx_recycle)(struct igb_tx_ring *); 554c869993eSxy 555c869993eSxy /* 556*d11274aaSPaul Guo * s/w context structure for TCP/UDP checksum offload and LSO. 557c869993eSxy */ 558*d11274aaSPaul Guo tx_context_t tx_context; 559c869993eSxy 560c869993eSxy /* 561c869993eSxy * Tx ring settings and status 562c869993eSxy */ 563c869993eSxy uint32_t ring_size; /* Tx descriptor ring size */ 564c869993eSxy uint32_t free_list_size; /* Tx free list size */ 565c869993eSxy uint32_t copy_thresh; 566c869993eSxy uint32_t recycle_thresh; 567c869993eSxy uint32_t overload_thresh; 568c869993eSxy uint32_t resched_thresh; 569c869993eSxy 570c869993eSxy boolean_t reschedule; 571c869993eSxy uint32_t recycle_fail; 572c869993eSxy uint32_t stall_watchdog; 573c869993eSxy 574c869993eSxy #ifdef IGB_DEBUG 575c869993eSxy /* 576c869993eSxy * Debug statistics 577c869993eSxy */ 578c869993eSxy uint32_t stat_overload; 579c869993eSxy uint32_t stat_fail_no_tbd; 580c869993eSxy uint32_t stat_fail_no_tcb; 581c869993eSxy uint32_t stat_fail_dma_bind; 582c869993eSxy uint32_t stat_reschedule; 583da14cebeSEric Cheng uint32_t stat_pkt_cnt; 584c869993eSxy #endif 585c869993eSxy 586c869993eSxy /* 587c869993eSxy * Pointer to the igb struct 588c869993eSxy */ 589c869993eSxy struct igb *igb; 590da14cebeSEric Cheng mac_ring_handle_t ring_handle; /* call back ring handle */ 591c869993eSxy } igb_tx_ring_t; 592c869993eSxy 593c869993eSxy /* 594c869993eSxy * Software Receive Ring 595c869993eSxy */ 596c869993eSxy typedef struct igb_rx_ring { 597c869993eSxy uint32_t index; /* Ring index */ 598c869993eSxy uint32_t intr_vector; /* Interrupt vector index */ 599c869993eSxy 600c869993eSxy /* 601c869993eSxy * Mutexes 602c869993eSxy */ 603c869993eSxy kmutex_t rx_lock; /* Rx access lock */ 604c869993eSxy kmutex_t recycle_lock; /* Recycle lock, for rcb_tail */ 605c869993eSxy 606c869993eSxy /* 607c869993eSxy * Rx descriptor ring definitions 608c869993eSxy */ 609c869993eSxy dma_buffer_t rbd_area; /* DMA buffer of rx desc ring */ 610c869993eSxy union e1000_adv_rx_desc *rbd_ring; /* Rx desc ring */ 611c869993eSxy uint32_t rbd_next; /* Index of next rx desc */ 612c869993eSxy 613c869993eSxy /* 614c869993eSxy * Rx control block list definitions 615c869993eSxy */ 616c869993eSxy rx_control_block_t *rcb_area; 617c869993eSxy rx_control_block_t **work_list; /* Work list of rcbs */ 618c869993eSxy rx_control_block_t **free_list; /* Free list of rcbs */ 619c869993eSxy uint32_t rcb_head; /* Index of next free rcb */ 620c869993eSxy uint32_t rcb_tail; /* Index to put recycled rcb */ 621c869993eSxy uint32_t rcb_free; /* Number of free rcbs */ 622c869993eSxy 623c869993eSxy /* 624c869993eSxy * Rx ring settings and status 625c869993eSxy */ 626c869993eSxy uint32_t ring_size; /* Rx descriptor ring size */ 627c869993eSxy uint32_t free_list_size; /* Rx free list size */ 628c869993eSxy uint32_t limit_per_intr; /* Max packets per interrupt */ 629c869993eSxy uint32_t copy_thresh; 630c869993eSxy 631c869993eSxy #ifdef IGB_DEBUG 632c869993eSxy /* 633c869993eSxy * Debug statistics 634c869993eSxy */ 635c869993eSxy uint32_t stat_frame_error; 636c869993eSxy uint32_t stat_cksum_error; 637c869993eSxy uint32_t stat_exceed_pkt; 638da14cebeSEric Cheng uint32_t stat_pkt_cnt; 639c869993eSxy #endif 640c869993eSxy 641c869993eSxy struct igb *igb; /* Pointer to igb struct */ 642b8d0a377Schenlu chen - Sun Microsystems - Beijing China mac_ring_handle_t ring_handle; /* call back ring handle */ 643da14cebeSEric Cheng uint32_t group_index; /* group index */ 644da14cebeSEric Cheng uint64_t ring_gen_num; 645c869993eSxy } igb_rx_ring_t; 646c869993eSxy 647da14cebeSEric Cheng /* 648da14cebeSEric Cheng * Software Receive Ring Group 649da14cebeSEric Cheng */ 650da14cebeSEric Cheng typedef struct igb_rx_group { 651da14cebeSEric Cheng uint32_t index; /* Group index */ 652da14cebeSEric Cheng mac_group_handle_t group_handle; /* call back group handle */ 653da14cebeSEric Cheng struct igb *igb; /* Pointer to igb struct */ 654da14cebeSEric Cheng } igb_rx_group_t; 655da14cebeSEric Cheng 656c869993eSxy typedef struct igb { 657c869993eSxy int instance; 658c869993eSxy mac_handle_t mac_hdl; 659c869993eSxy dev_info_t *dip; 660c869993eSxy struct e1000_hw hw; 661c869993eSxy struct igb_osdep osdep; 662c869993eSxy 66380a11ad2Schenlu chen - Sun Microsystems - Beijing China adapter_info_t *capab; /* adapter capabilities */ 66480a11ad2Schenlu chen - Sun Microsystems - Beijing China 665c869993eSxy uint32_t igb_state; 666c869993eSxy link_state_t link_state; 667c869993eSxy uint32_t link_speed; 668c869993eSxy uint32_t link_duplex; 669c869993eSxy uint32_t link_down_timeout; 670c869993eSxy 671c869993eSxy uint32_t reset_count; 672c869993eSxy uint32_t attach_progress; 673c869993eSxy uint32_t loopback_mode; 674c869993eSxy uint32_t max_frame_size; 675b8d0a377Schenlu chen - Sun Microsystems - Beijing China uint32_t dout_sync; 676c869993eSxy 677da14cebeSEric Cheng uint32_t mr_enable; /* Enable multiple rings */ 678da14cebeSEric Cheng uint32_t vmdq_mode; /* Mode of VMDq */ 679da14cebeSEric Cheng 680c869993eSxy /* 681da14cebeSEric Cheng * Receive Rings and Groups 682c869993eSxy */ 683c869993eSxy igb_rx_ring_t *rx_rings; /* Array of rx rings */ 684c869993eSxy uint32_t num_rx_rings; /* Number of rx rings in use */ 685c869993eSxy uint32_t rx_ring_size; /* Rx descriptor ring size */ 686c869993eSxy uint32_t rx_buf_size; /* Rx buffer size */ 687da14cebeSEric Cheng igb_rx_group_t *rx_groups; /* Array of rx groups */ 688da14cebeSEric Cheng uint32_t num_rx_groups; /* Number of rx groups in use */ 689c869993eSxy 690c869993eSxy /* 691c869993eSxy * Transmit Rings 692c869993eSxy */ 693c869993eSxy igb_tx_ring_t *tx_rings; /* Array of tx rings */ 694c869993eSxy uint32_t num_tx_rings; /* Number of tx rings in use */ 695c869993eSxy uint32_t tx_ring_size; /* Tx descriptor ring size */ 696c869993eSxy uint32_t tx_buf_size; /* Tx buffer size */ 697c869993eSxy 698c869993eSxy boolean_t tx_head_wb_enable; /* Tx head wrtie-back */ 699c869993eSxy boolean_t tx_hcksum_enable; /* Tx h/w cksum offload */ 700c869993eSxy boolean_t lso_enable; /* Large Segment Offload */ 701c869993eSxy uint32_t tx_copy_thresh; /* Tx copy threshold */ 702c869993eSxy uint32_t tx_recycle_thresh; /* Tx recycle threshold */ 703c869993eSxy uint32_t tx_overload_thresh; /* Tx overload threshold */ 704c869993eSxy uint32_t tx_resched_thresh; /* Tx reschedule threshold */ 705c869993eSxy boolean_t rx_hcksum_enable; /* Rx h/w cksum offload */ 706c869993eSxy uint32_t rx_copy_thresh; /* Rx copy threshold */ 707c869993eSxy uint32_t rx_limit_per_intr; /* Rx pkts per interrupt */ 708b8d0a377Schenlu chen - Sun Microsystems - Beijing China 709c869993eSxy uint32_t intr_throttling[MAX_NUM_EITR]; 710c869993eSxy uint32_t intr_force; 711c869993eSxy 712c869993eSxy int intr_type; 713c869993eSxy int intr_cnt; 714c869993eSxy int intr_cap; 715c869993eSxy size_t intr_size; 716c869993eSxy uint_t intr_pri; 717c869993eSxy ddi_intr_handle_t *htable; 718c869993eSxy uint32_t eims_mask; 719da14cebeSEric Cheng uint32_t ims_mask; 720c869993eSxy 721c869993eSxy kmutex_t gen_lock; /* General lock for device access */ 722c869993eSxy kmutex_t watchdog_lock; 723c869993eSxy 724c869993eSxy boolean_t watchdog_enable; 725c869993eSxy boolean_t watchdog_start; 726c869993eSxy timeout_id_t watchdog_tid; 727c869993eSxy 728c869993eSxy boolean_t unicst_init; 729c869993eSxy uint32_t unicst_avail; 730c869993eSxy uint32_t unicst_total; 731c869993eSxy igb_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 732c869993eSxy uint32_t mcast_count; 733c869993eSxy struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES]; 734c869993eSxy 735c869993eSxy /* 736c869993eSxy * Kstat definitions 737c869993eSxy */ 738c869993eSxy kstat_t *igb_ks; 739c869993eSxy 740c869993eSxy /* 741c869993eSxy * NDD definitions 742c869993eSxy */ 743c869993eSxy caddr_t nd_data; 744c869993eSxy nd_param_t nd_params[PARAM_COUNT]; 745c869993eSxy 7468bb4b220Sgl /* 7478bb4b220Sgl * FMA capabilities 7488bb4b220Sgl */ 7498bb4b220Sgl int fm_capabilities; 7508bb4b220Sgl 751*d11274aaSPaul Guo ulong_t page_size; 752c869993eSxy } igb_t; 753c869993eSxy 754c869993eSxy typedef struct igb_stat { 755c869993eSxy 756c869993eSxy kstat_named_t link_speed; /* Link Speed */ 757c869993eSxy kstat_named_t reset_count; /* Reset Count */ 758b8d0a377Schenlu chen - Sun Microsystems - Beijing China kstat_named_t dout_sync; /* DMA out of sync */ 759b8d0a377Schenlu chen - Sun Microsystems - Beijing China #ifdef IGB_DEBUG 760c869993eSxy kstat_named_t rx_frame_error; /* Rx Error in Packet */ 761c869993eSxy kstat_named_t rx_cksum_error; /* Rx Checksum Error */ 762c869993eSxy kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */ 763c869993eSxy 764c869993eSxy kstat_named_t tx_overload; /* Tx Desc Ring Overload */ 765c869993eSxy kstat_named_t tx_fail_no_tcb; /* Tx Fail Freelist Empty */ 766c869993eSxy kstat_named_t tx_fail_no_tbd; /* Tx Fail Desc Ring Empty */ 767c869993eSxy kstat_named_t tx_fail_dma_bind; /* Tx Fail DMA bind */ 768c869993eSxy kstat_named_t tx_reschedule; /* Tx Reschedule */ 769c869993eSxy 770c869993eSxy kstat_named_t gprc; /* Good Packets Received Count */ 771c869993eSxy kstat_named_t gptc; /* Good Packets Xmitted Count */ 772c869993eSxy kstat_named_t gor; /* Good Octets Received Count */ 773c869993eSxy kstat_named_t got; /* Good Octets Xmitd Count */ 774c869993eSxy kstat_named_t prc64; /* Packets Received - 64b */ 775c869993eSxy kstat_named_t prc127; /* Packets Received - 65-127b */ 776c869993eSxy kstat_named_t prc255; /* Packets Received - 127-255b */ 777c869993eSxy kstat_named_t prc511; /* Packets Received - 256-511b */ 778c869993eSxy kstat_named_t prc1023; /* Packets Received - 511-1023b */ 779c869993eSxy kstat_named_t prc1522; /* Packets Received - 1024-1522b */ 780c869993eSxy kstat_named_t ptc64; /* Packets Xmitted (64b) */ 781c869993eSxy kstat_named_t ptc127; /* Packets Xmitted (64-127b) */ 782c869993eSxy kstat_named_t ptc255; /* Packets Xmitted (128-255b) */ 783c869993eSxy kstat_named_t ptc511; /* Packets Xmitted (255-511b) */ 784c869993eSxy kstat_named_t ptc1023; /* Packets Xmitted (512-1023b) */ 785c869993eSxy kstat_named_t ptc1522; /* Packets Xmitted (1024-1522b */ 786c869993eSxy #endif 787c869993eSxy kstat_named_t crcerrs; /* CRC Error Count */ 788c869993eSxy kstat_named_t symerrs; /* Symbol Error Count */ 789c869993eSxy kstat_named_t mpc; /* Missed Packet Count */ 790c869993eSxy kstat_named_t scc; /* Single Collision Count */ 791c869993eSxy kstat_named_t ecol; /* Excessive Collision Count */ 792c869993eSxy kstat_named_t mcc; /* Multiple Collision Count */ 793c869993eSxy kstat_named_t latecol; /* Late Collision Count */ 794c869993eSxy kstat_named_t colc; /* Collision Count */ 795c869993eSxy kstat_named_t dc; /* Defer Count */ 796c869993eSxy kstat_named_t sec; /* Sequence Error Count */ 797c869993eSxy kstat_named_t rlec; /* Receive Length Error Count */ 798c869993eSxy kstat_named_t xonrxc; /* XON Received Count */ 799c869993eSxy kstat_named_t xontxc; /* XON Xmitted Count */ 800c869993eSxy kstat_named_t xoffrxc; /* XOFF Received Count */ 801c869993eSxy kstat_named_t xofftxc; /* Xoff Xmitted Count */ 802c869993eSxy kstat_named_t fcruc; /* Unknown Flow Conrol Packet Rcvd Count */ 803c869993eSxy kstat_named_t bprc; /* Broadcasts Pkts Received Count */ 804c869993eSxy kstat_named_t mprc; /* Multicast Pkts Received Count */ 805c869993eSxy kstat_named_t rnbc; /* Receive No Buffers Count */ 806c869993eSxy kstat_named_t ruc; /* Receive Undersize Count */ 807c869993eSxy kstat_named_t rfc; /* Receive Frag Count */ 808c869993eSxy kstat_named_t roc; /* Receive Oversize Count */ 809c869993eSxy kstat_named_t rjc; /* Receive Jabber Count */ 810c869993eSxy kstat_named_t tor; /* Total Octets Recvd Count */ 811c869993eSxy kstat_named_t tot; /* Total Octets Xmted Count */ 812c869993eSxy kstat_named_t tpr; /* Total Packets Received */ 813c869993eSxy kstat_named_t tpt; /* Total Packets Xmitted */ 814c869993eSxy kstat_named_t mptc; /* Multicast Packets Xmited Count */ 815c869993eSxy kstat_named_t bptc; /* Broadcast Packets Xmited Count */ 816c869993eSxy kstat_named_t algnerrc; /* Alignment Error count */ 817c869993eSxy kstat_named_t rxerrc; /* Rx Error Count */ 818c869993eSxy kstat_named_t tncrs; /* Transmit with no CRS */ 819c869993eSxy kstat_named_t cexterr; /* Carrier Extension Error count */ 820c869993eSxy kstat_named_t tsctc; /* TCP seg contexts xmit count */ 821c869993eSxy kstat_named_t tsctfc; /* TCP seg contexts xmit fail count */ 822c869993eSxy } igb_stat_t; 823c869993eSxy 824c869993eSxy /* 825c869993eSxy * Function prototypes in e1000_osdep.c 826c869993eSxy */ 82780a11ad2Schenlu chen - Sun Microsystems - Beijing China void e1000_rar_clear(struct e1000_hw *hw, uint32_t); 82880a11ad2Schenlu chen - Sun Microsystems - Beijing China void e1000_rar_set_vmdq(struct e1000_hw *hw, const uint8_t *, uint32_t, 82980a11ad2Schenlu chen - Sun Microsystems - Beijing China uint32_t, uint8_t); 830c869993eSxy 831c869993eSxy /* 832c869993eSxy * Function prototypes in igb_buf.c 833c869993eSxy */ 834c869993eSxy int igb_alloc_dma(igb_t *); 835c869993eSxy void igb_free_dma(igb_t *); 836c869993eSxy 837c869993eSxy /* 838c869993eSxy * Function prototypes in igb_main.c 839c869993eSxy */ 840c869993eSxy int igb_start(igb_t *); 841c869993eSxy void igb_stop(igb_t *); 842c869993eSxy int igb_setup_link(igb_t *, boolean_t); 843da14cebeSEric Cheng int igb_unicst_find(igb_t *, const uint8_t *); 844da14cebeSEric Cheng int igb_unicst_set(igb_t *, const uint8_t *, int); 845c869993eSxy int igb_multicst_add(igb_t *, const uint8_t *); 846c869993eSxy int igb_multicst_remove(igb_t *, const uint8_t *); 847c869993eSxy enum ioc_reply igb_loopback_ioctl(igb_t *, struct iocblk *, mblk_t *); 848c869993eSxy void igb_enable_watchdog_timer(igb_t *); 849c869993eSxy void igb_disable_watchdog_timer(igb_t *); 850c869993eSxy int igb_atomic_reserve(uint32_t *, uint32_t); 8518bb4b220Sgl int igb_check_acc_handle(ddi_acc_handle_t); 8528bb4b220Sgl int igb_check_dma_handle(ddi_dma_handle_t); 8538bb4b220Sgl void igb_fm_ereport(igb_t *, char *); 8548bb4b220Sgl void igb_set_fma_flags(int, int); 855c869993eSxy 856c869993eSxy /* 857c869993eSxy * Function prototypes in igb_gld.c 858c869993eSxy */ 859c869993eSxy int igb_m_start(void *); 860c869993eSxy void igb_m_stop(void *); 861c869993eSxy int igb_m_promisc(void *, boolean_t); 862c869993eSxy int igb_m_multicst(void *, boolean_t, const uint8_t *); 863c869993eSxy int igb_m_unicst(void *, const uint8_t *); 864c869993eSxy int igb_m_stat(void *, uint_t, uint64_t *); 865c869993eSxy void igb_m_resources(void *); 866c869993eSxy void igb_m_ioctl(void *, queue_t *, mblk_t *); 867c869993eSxy boolean_t igb_m_getcapab(void *, mac_capab_t, void *); 868da14cebeSEric Cheng void igb_fill_ring(void *, mac_ring_type_t, const int, const int, 869da14cebeSEric Cheng mac_ring_info_t *, mac_ring_handle_t); 870da14cebeSEric Cheng void igb_fill_group(void *arg, mac_ring_type_t, const int, 871da14cebeSEric Cheng mac_group_info_t *, mac_group_handle_t); 872da14cebeSEric Cheng int igb_rx_ring_intr_enable(mac_intr_handle_t); 873da14cebeSEric Cheng int igb_rx_ring_intr_disable(mac_intr_handle_t); 874c869993eSxy 875c869993eSxy /* 876c869993eSxy * Function prototypes in igb_rx.c 877c869993eSxy */ 878da14cebeSEric Cheng mblk_t *igb_rx(igb_rx_ring_t *, int); 879c869993eSxy void igb_rx_recycle(caddr_t arg); 880c869993eSxy 881c869993eSxy /* 882c869993eSxy * Function prototypes in igb_tx.c 883c869993eSxy */ 884c869993eSxy void igb_free_tcb(tx_control_block_t *); 885c869993eSxy void igb_put_free_list(igb_tx_ring_t *, link_list_t *); 886c869993eSxy uint32_t igb_tx_recycle_legacy(igb_tx_ring_t *); 887c869993eSxy uint32_t igb_tx_recycle_head_wb(igb_tx_ring_t *); 888c869993eSxy 889c869993eSxy /* 890c869993eSxy * Function prototypes in igb_log.c 891c869993eSxy */ 892c869993eSxy void igb_notice(void *, const char *, ...); 893c869993eSxy void igb_log(void *, const char *, ...); 894c869993eSxy void igb_error(void *, const char *, ...); 895c869993eSxy 896c869993eSxy /* 897c869993eSxy * Function prototypes in igb_ndd.c 898c869993eSxy */ 899c869993eSxy int igb_nd_init(igb_t *); 900c869993eSxy void igb_nd_cleanup(igb_t *); 901c869993eSxy enum ioc_reply igb_nd_ioctl(igb_t *, queue_t *, mblk_t *, struct iocblk *); 902c869993eSxy 903c869993eSxy /* 904c869993eSxy * Function prototypes in igb_stat.c 905c869993eSxy */ 906c869993eSxy int igb_init_stats(igb_t *); 907c869993eSxy 908da14cebeSEric Cheng mblk_t *igb_rx_ring_poll(void *, int); 909da14cebeSEric Cheng mblk_t *igb_tx_ring_send(void *, mblk_t *); 910c869993eSxy 911c869993eSxy #ifdef __cplusplus 912c869993eSxy } 913c869993eSxy #endif 914c869993eSxy 915c869993eSxy #endif /* _IGB_SW_H */ 916