1*c869993eSxy /* 2*c869993eSxy * CDDL HEADER START 3*c869993eSxy * 4*c869993eSxy * Copyright(c) 2007-2008 Intel Corporation. All rights reserved. 5*c869993eSxy * The contents of this file are subject to the terms of the 6*c869993eSxy * Common Development and Distribution License (the "License"). 7*c869993eSxy * You may not use this file except in compliance with the License. 8*c869993eSxy * 9*c869993eSxy * You can obtain a copy of the license at: 10*c869993eSxy * http://www.opensolaris.org/os/licensing. 11*c869993eSxy * See the License for the specific language governing permissions 12*c869993eSxy * and limitations under the License. 13*c869993eSxy * 14*c869993eSxy * When using or redistributing this file, you may do so under the 15*c869993eSxy * License only. No other modification of this header is permitted. 16*c869993eSxy * 17*c869993eSxy * If applicable, add the following below this CDDL HEADER, with the 18*c869993eSxy * fields enclosed by brackets "[]" replaced with your own identifying 19*c869993eSxy * information: Portions Copyright [yyyy] [name of copyright owner] 20*c869993eSxy * 21*c869993eSxy * CDDL HEADER END 22*c869993eSxy */ 23*c869993eSxy 24*c869993eSxy /* 25*c869993eSxy * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 26*c869993eSxy * Use is subject to license terms of the CDDL. 27*c869993eSxy */ 28*c869993eSxy 29*c869993eSxy #ifndef _IGB_SW_H 30*c869993eSxy #define _IGB_SW_H 31*c869993eSxy 32*c869993eSxy #pragma ident "%Z%%M% %I% %E% SMI" 33*c869993eSxy 34*c869993eSxy #ifdef __cplusplus 35*c869993eSxy extern "C" { 36*c869993eSxy #endif 37*c869993eSxy 38*c869993eSxy #include <sys/types.h> 39*c869993eSxy #include <sys/conf.h> 40*c869993eSxy #include <sys/debug.h> 41*c869993eSxy #include <sys/stropts.h> 42*c869993eSxy #include <sys/stream.h> 43*c869993eSxy #include <sys/strsun.h> 44*c869993eSxy #include <sys/strlog.h> 45*c869993eSxy #include <sys/kmem.h> 46*c869993eSxy #include <sys/stat.h> 47*c869993eSxy #include <sys/kstat.h> 48*c869993eSxy #include <sys/modctl.h> 49*c869993eSxy #include <sys/errno.h> 50*c869993eSxy #include <sys/dlpi.h> 51*c869993eSxy #include <sys/mac.h> 52*c869993eSxy #include <sys/mac_ether.h> 53*c869993eSxy #include <sys/vlan.h> 54*c869993eSxy #include <sys/ddi.h> 55*c869993eSxy #include <sys/sunddi.h> 56*c869993eSxy #include <sys/pci.h> 57*c869993eSxy #include <sys/pcie.h> 58*c869993eSxy #include <sys/sdt.h> 59*c869993eSxy #include <sys/ethernet.h> 60*c869993eSxy #include <sys/pattr.h> 61*c869993eSxy #include <sys/strsubr.h> 62*c869993eSxy #include <sys/netlb.h> 63*c869993eSxy #include <sys/random.h> 64*c869993eSxy #include <inet/common.h> 65*c869993eSxy #include <inet/ip.h> 66*c869993eSxy #include <inet/mi.h> 67*c869993eSxy #include <inet/nd.h> 68*c869993eSxy #include "igb_api.h" 69*c869993eSxy #include "igb_82575.h" 70*c869993eSxy 71*c869993eSxy 72*c869993eSxy #define MODULE_NAME "igb" /* module name */ 73*c869993eSxy 74*c869993eSxy #define IGB_SUCCESS DDI_SUCCESS 75*c869993eSxy #define IGB_FAILURE DDI_FAILURE 76*c869993eSxy 77*c869993eSxy #define IGB_UNKNOWN 0x00 78*c869993eSxy #define IGB_INITIALIZED 0x01 79*c869993eSxy #define IGB_STARTED 0x02 80*c869993eSxy #define IGB_SUSPENDED 0x04 81*c869993eSxy 82*c869993eSxy #define IGB_INTR_NONE 0 83*c869993eSxy #define IGB_INTR_MSIX 1 84*c869993eSxy #define IGB_INTR_MSI 2 85*c869993eSxy #define IGB_INTR_LEGACY 3 86*c869993eSxy 87*c869993eSxy #define MAX_NUM_UNICAST_ADDRESSES E1000_RAR_ENTRIES 88*c869993eSxy #define MAX_NUM_MULTICAST_ADDRESSES 256 89*c869993eSxy #define MAX_NUM_EITR 10 90*c869993eSxy #define MAX_COOKIE 16 91*c869993eSxy #define MIN_NUM_TX_DESC 2 92*c869993eSxy 93*c869993eSxy /* 94*c869993eSxy * Maximum values for user configurable parameters 95*c869993eSxy */ 96*c869993eSxy #define MAX_TX_QUEUE_NUM 4 97*c869993eSxy #define MAX_RX_QUEUE_NUM 4 98*c869993eSxy #define MAX_TX_RING_SIZE 4096 99*c869993eSxy #define MAX_RX_RING_SIZE 4096 100*c869993eSxy 101*c869993eSxy #define MAX_MTU 9000 102*c869993eSxy #define MAX_RX_LIMIT_PER_INTR 4096 103*c869993eSxy #define MAX_RX_INTR_DELAY 65535 104*c869993eSxy #define MAX_RX_INTR_ABS_DELAY 65535 105*c869993eSxy #define MAX_TX_INTR_DELAY 65535 106*c869993eSxy #define MAX_TX_INTR_ABS_DELAY 65535 107*c869993eSxy #define MAX_INTR_THROTTLING 65535 108*c869993eSxy 109*c869993eSxy #define MAX_RX_COPY_THRESHOLD 9216 110*c869993eSxy #define MAX_TX_COPY_THRESHOLD 9216 111*c869993eSxy #define MAX_TX_RECYCLE_THRESHOLD DEFAULT_TX_RING_SIZE 112*c869993eSxy #define MAX_TX_OVERLOAD_THRESHOLD DEFAULT_TX_RING_SIZE 113*c869993eSxy #define MAX_TX_RESCHED_THRESHOLD DEFAULT_TX_RING_SIZE 114*c869993eSxy 115*c869993eSxy /* 116*c869993eSxy * Minimum values for user configurable parameters 117*c869993eSxy */ 118*c869993eSxy #define MIN_TX_QUEUE_NUM 1 119*c869993eSxy #define MIN_RX_QUEUE_NUM 1 120*c869993eSxy #define MIN_TX_RING_SIZE 64 121*c869993eSxy #define MIN_RX_RING_SIZE 64 122*c869993eSxy 123*c869993eSxy #define MIN_MTU ETHERMIN 124*c869993eSxy #define MIN_RX_LIMIT_PER_INTR 16 125*c869993eSxy #define MIN_RX_INTR_DELAY 0 126*c869993eSxy #define MIN_RX_INTR_ABS_DELAY 0 127*c869993eSxy #define MIN_TX_INTR_DELAY 0 128*c869993eSxy #define MIN_TX_INTR_ABS_DELAY 0 129*c869993eSxy #define MIN_INTR_THROTTLING 0 130*c869993eSxy #define MIN_RX_COPY_THRESHOLD 0 131*c869993eSxy #define MIN_TX_COPY_THRESHOLD 0 132*c869993eSxy #define MIN_TX_RECYCLE_THRESHOLD MIN_NUM_TX_DESC 133*c869993eSxy #define MIN_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 134*c869993eSxy #define MIN_TX_RESCHED_THRESHOLD MIN_NUM_TX_DESC 135*c869993eSxy 136*c869993eSxy /* 137*c869993eSxy * Default values for user configurable parameters 138*c869993eSxy */ 139*c869993eSxy #define DEFAULT_TX_QUEUE_NUM 1 140*c869993eSxy #define DEFAULT_RX_QUEUE_NUM 1 141*c869993eSxy #define DEFAULT_TX_RING_SIZE 512 142*c869993eSxy #define DEFAULT_RX_RING_SIZE 512 143*c869993eSxy 144*c869993eSxy #define DEFAULT_MTU ETHERMTU 145*c869993eSxy #define DEFAULT_RX_LIMIT_PER_INTR 256 146*c869993eSxy #define DEFAULT_RX_INTR_DELAY 0 147*c869993eSxy #define DEFAULT_RX_INTR_ABS_DELAY 0 148*c869993eSxy #define DEFAULT_TX_INTR_DELAY 300 149*c869993eSxy #define DEFAULT_TX_INTR_ABS_DELAY 0 150*c869993eSxy #define DEFAULT_INTR_THROTTLING 200 /* In unit of 256 nsec */ 151*c869993eSxy #define DEFAULT_RX_COPY_THRESHOLD 128 152*c869993eSxy #define DEFAULT_TX_COPY_THRESHOLD 512 153*c869993eSxy #define DEFAULT_TX_RECYCLE_THRESHOLD MAX_COOKIE 154*c869993eSxy #define DEFAULT_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 155*c869993eSxy #define DEFAULT_TX_RESCHED_THRESHOLD 128 156*c869993eSxy 157*c869993eSxy #define TX_DRAIN_TIME 200 158*c869993eSxy #define RX_DRAIN_TIME 200 159*c869993eSxy 160*c869993eSxy #define STALL_WATCHDOG_TIMEOUT 8 /* 8 seconds */ 161*c869993eSxy #define MAX_LINK_DOWN_TIMEOUT 8 /* 8 seconds */ 162*c869993eSxy 163*c869993eSxy /* 164*c869993eSxy * Defined for IP header alignment. 165*c869993eSxy */ 166*c869993eSxy #define IPHDR_ALIGN_ROOM 2 167*c869993eSxy 168*c869993eSxy /* 169*c869993eSxy * Bit flags for attach_progress 170*c869993eSxy */ 171*c869993eSxy #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 172*c869993eSxy #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 173*c869993eSxy #define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */ 174*c869993eSxy #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */ 175*c869993eSxy #define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */ 176*c869993eSxy #define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */ 177*c869993eSxy #define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */ 178*c869993eSxy #define ATTACH_PROGRESS_INIT 0x0080 /* Device initialized */ 179*c869993eSxy #define ATTACH_PROGRESS_INIT_RINGS 0x0100 /* Rings initialized */ 180*c869993eSxy #define ATTACH_PROGRESS_STATS 0x0200 /* Kstats created */ 181*c869993eSxy #define ATTACH_PROGRESS_NDD 0x0400 /* NDD initialized */ 182*c869993eSxy #define ATTACH_PROGRESS_MAC 0x0800 /* MAC registered */ 183*c869993eSxy #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */ 184*c869993eSxy 185*c869993eSxy 186*c869993eSxy #define PROP_ADV_AUTONEG_CAP "adv_autoneg_cap" 187*c869993eSxy #define PROP_ADV_1000FDX_CAP "adv_1000fdx_cap" 188*c869993eSxy #define PROP_ADV_1000HDX_CAP "adv_1000hdx_cap" 189*c869993eSxy #define PROP_ADV_100FDX_CAP "adv_100fdx_cap" 190*c869993eSxy #define PROP_ADV_100HDX_CAP "adv_100hdx_cap" 191*c869993eSxy #define PROP_ADV_10FDX_CAP "adv_10fdx_cap" 192*c869993eSxy #define PROP_ADV_10HDX_CAP "adv_10hdx_cap" 193*c869993eSxy #define PROP_DEFAULT_MTU "default_mtu" 194*c869993eSxy #define PROP_FLOW_CONTROL "flow_control" 195*c869993eSxy #define PROP_TX_QUEUE_NUM "tx_queue_number" 196*c869993eSxy #define PROP_TX_RING_SIZE "tx_ring_size" 197*c869993eSxy #define PROP_RX_QUEUE_NUM "rx_queue_number" 198*c869993eSxy #define PROP_RX_RING_SIZE "rx_ring_size" 199*c869993eSxy 200*c869993eSxy #define PROP_INTR_FORCE "intr_force" 201*c869993eSxy #define PROP_TX_HCKSUM_ENABLE "tx_hcksum_enable" 202*c869993eSxy #define PROP_RX_HCKSUM_ENABLE "rx_hcksum_enable" 203*c869993eSxy #define PROP_LSO_ENABLE "lso_enable" 204*c869993eSxy #define PROP_TX_HEAD_WB_ENABLE "tx_head_wb_enable" 205*c869993eSxy #define PROP_TX_COPY_THRESHOLD "tx_copy_threshold" 206*c869993eSxy #define PROP_TX_RECYCLE_THRESHOLD "tx_recycle_threshold" 207*c869993eSxy #define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold" 208*c869993eSxy #define PROP_TX_RESCHED_THRESHOLD "tx_resched_threshold" 209*c869993eSxy #define PROP_RX_COPY_THRESHOLD "rx_copy_threshold" 210*c869993eSxy #define PROP_RX_LIMIT_PER_INTR "rx_limit_per_intr" 211*c869993eSxy #define PROP_INTR_THROTTLING "intr_throttling" 212*c869993eSxy 213*c869993eSxy #define IGB_LB_NONE 0 214*c869993eSxy #define IGB_LB_EXTERNAL 1 215*c869993eSxy #define IGB_LB_INTERNAL_MAC 2 216*c869993eSxy #define IGB_LB_INTERNAL_PHY 3 217*c869993eSxy #define IGB_LB_INTERNAL_SERDES 4 218*c869993eSxy 219*c869993eSxy /* 220*c869993eSxy * Shorthand for the NDD parameters 221*c869993eSxy */ 222*c869993eSxy #define param_autoneg_cap nd_params[PARAM_AUTONEG_CAP].val 223*c869993eSxy #define param_pause_cap nd_params[PARAM_PAUSE_CAP].val 224*c869993eSxy #define param_asym_pause_cap nd_params[PARAM_ASYM_PAUSE_CAP].val 225*c869993eSxy #define param_1000fdx_cap nd_params[PARAM_1000FDX_CAP].val 226*c869993eSxy #define param_1000hdx_cap nd_params[PARAM_1000HDX_CAP].val 227*c869993eSxy #define param_100t4_cap nd_params[PARAM_100T4_CAP].val 228*c869993eSxy #define param_100fdx_cap nd_params[PARAM_100FDX_CAP].val 229*c869993eSxy #define param_100hdx_cap nd_params[PARAM_100HDX_CAP].val 230*c869993eSxy #define param_10fdx_cap nd_params[PARAM_10FDX_CAP].val 231*c869993eSxy #define param_10hdx_cap nd_params[PARAM_10HDX_CAP].val 232*c869993eSxy #define param_rem_fault nd_params[PARAM_REM_FAULT].val 233*c869993eSxy 234*c869993eSxy #define param_adv_autoneg_cap nd_params[PARAM_ADV_AUTONEG_CAP].val 235*c869993eSxy #define param_adv_pause_cap nd_params[PARAM_ADV_PAUSE_CAP].val 236*c869993eSxy #define param_adv_asym_pause_cap nd_params[PARAM_ADV_ASYM_PAUSE_CAP].val 237*c869993eSxy #define param_adv_1000fdx_cap nd_params[PARAM_ADV_1000FDX_CAP].val 238*c869993eSxy #define param_adv_1000hdx_cap nd_params[PARAM_ADV_1000HDX_CAP].val 239*c869993eSxy #define param_adv_100t4_cap nd_params[PARAM_ADV_100T4_CAP].val 240*c869993eSxy #define param_adv_100fdx_cap nd_params[PARAM_ADV_100FDX_CAP].val 241*c869993eSxy #define param_adv_100hdx_cap nd_params[PARAM_ADV_100HDX_CAP].val 242*c869993eSxy #define param_adv_10fdx_cap nd_params[PARAM_ADV_10FDX_CAP].val 243*c869993eSxy #define param_adv_10hdx_cap nd_params[PARAM_ADV_10HDX_CAP].val 244*c869993eSxy #define param_adv_rem_fault nd_params[PARAM_ADV_REM_FAULT].val 245*c869993eSxy 246*c869993eSxy #define param_lp_autoneg_cap nd_params[PARAM_LP_AUTONEG_CAP].val 247*c869993eSxy #define param_lp_pause_cap nd_params[PARAM_LP_PAUSE_CAP].val 248*c869993eSxy #define param_lp_asym_pause_cap nd_params[PARAM_LP_ASYM_PAUSE_CAP].val 249*c869993eSxy #define param_lp_1000fdx_cap nd_params[PARAM_LP_1000FDX_CAP].val 250*c869993eSxy #define param_lp_1000hdx_cap nd_params[PARAM_LP_1000HDX_CAP].val 251*c869993eSxy #define param_lp_100t4_cap nd_params[PARAM_LP_100T4_CAP].val 252*c869993eSxy #define param_lp_100fdx_cap nd_params[PARAM_LP_100FDX_CAP].val 253*c869993eSxy #define param_lp_100hdx_cap nd_params[PARAM_LP_100HDX_CAP].val 254*c869993eSxy #define param_lp_10fdx_cap nd_params[PARAM_LP_10FDX_CAP].val 255*c869993eSxy #define param_lp_10hdx_cap nd_params[PARAM_LP_10HDX_CAP].val 256*c869993eSxy #define param_lp_rem_fault nd_params[PARAM_LP_REM_FAULT].val 257*c869993eSxy 258*c869993eSxy enum ioc_reply { 259*c869993eSxy IOC_INVAL = -1, /* bad, NAK with EINVAL */ 260*c869993eSxy IOC_DONE, /* OK, reply sent */ 261*c869993eSxy IOC_ACK, /* OK, just send ACK */ 262*c869993eSxy IOC_REPLY /* OK, just send reply */ 263*c869993eSxy }; 264*c869993eSxy 265*c869993eSxy #define MBLK_LEN(mp) ((uintptr_t)(mp)->b_wptr - \ 266*c869993eSxy (uintptr_t)(mp)->b_rptr) 267*c869993eSxy 268*c869993eSxy #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area)->dma_handle, \ 269*c869993eSxy 0, 0, (flag))) 270*c869993eSxy 271*c869993eSxy /* 272*c869993eSxy * Defined for ring index operations 273*c869993eSxy * ASSERT(index < limit) 274*c869993eSxy * ASSERT(step < limit) 275*c869993eSxy * ASSERT(index1 < limit) 276*c869993eSxy * ASSERT(index2 < limit) 277*c869993eSxy */ 278*c869993eSxy #define NEXT_INDEX(index, step, limit) (((index) + (step)) < (limit) ? \ 279*c869993eSxy (index) + (step) : (index) + (step) - (limit)) 280*c869993eSxy #define PREV_INDEX(index, step, limit) ((index) >= (step) ? \ 281*c869993eSxy (index) - (step) : (index) + (limit) - (step)) 282*c869993eSxy #define OFFSET(index1, index2, limit) ((index1) <= (index2) ? \ 283*c869993eSxy (index2) - (index1) : (index2) + (limit) - (index1)) 284*c869993eSxy 285*c869993eSxy #define LINK_LIST_INIT(_LH) \ 286*c869993eSxy (_LH)->head = (_LH)->tail = NULL 287*c869993eSxy 288*c869993eSxy #define LIST_GET_HEAD(_LH) ((single_link_t *)((_LH)->head)) 289*c869993eSxy 290*c869993eSxy #define LIST_POP_HEAD(_LH) \ 291*c869993eSxy (single_link_t *)(_LH)->head; \ 292*c869993eSxy { \ 293*c869993eSxy if ((_LH)->head != NULL) { \ 294*c869993eSxy (_LH)->head = (_LH)->head->link; \ 295*c869993eSxy if ((_LH)->head == NULL) \ 296*c869993eSxy (_LH)->tail = NULL; \ 297*c869993eSxy } \ 298*c869993eSxy } 299*c869993eSxy 300*c869993eSxy #define LIST_GET_TAIL(_LH) ((single_link_t *)((_LH)->tail)) 301*c869993eSxy 302*c869993eSxy #define LIST_PUSH_TAIL(_LH, _E) \ 303*c869993eSxy if ((_LH)->tail != NULL) { \ 304*c869993eSxy (_LH)->tail->link = (single_link_t *)(_E); \ 305*c869993eSxy (_LH)->tail = (single_link_t *)(_E); \ 306*c869993eSxy } else { \ 307*c869993eSxy (_LH)->head = (_LH)->tail = (single_link_t *)(_E); \ 308*c869993eSxy } \ 309*c869993eSxy (_E)->link = NULL; 310*c869993eSxy 311*c869993eSxy #define LIST_GET_NEXT(_LH, _E) \ 312*c869993eSxy (((_LH)->tail == (single_link_t *)(_E)) ? \ 313*c869993eSxy NULL : ((single_link_t *)(_E))->link) 314*c869993eSxy 315*c869993eSxy 316*c869993eSxy typedef struct single_link { 317*c869993eSxy struct single_link *link; 318*c869993eSxy } single_link_t; 319*c869993eSxy 320*c869993eSxy typedef struct link_list { 321*c869993eSxy single_link_t *head; 322*c869993eSxy single_link_t *tail; 323*c869993eSxy } link_list_t; 324*c869993eSxy 325*c869993eSxy /* 326*c869993eSxy * Property lookups 327*c869993eSxy */ 328*c869993eSxy #define IGB_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 329*c869993eSxy DDI_PROP_DONTPASS, (n)) 330*c869993eSxy #define IGB_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 331*c869993eSxy DDI_PROP_DONTPASS, (n), -1) 332*c869993eSxy 333*c869993eSxy 334*c869993eSxy /* 335*c869993eSxy * Named Data (ND) Parameter Management Structure 336*c869993eSxy */ 337*c869993eSxy typedef struct { 338*c869993eSxy struct igb *private; 339*c869993eSxy uint32_t info; 340*c869993eSxy uint32_t min; 341*c869993eSxy uint32_t max; 342*c869993eSxy uint32_t val; 343*c869993eSxy char *name; 344*c869993eSxy } nd_param_t; 345*c869993eSxy 346*c869993eSxy /* 347*c869993eSxy * NDD parameter indexes, divided into: 348*c869993eSxy * 349*c869993eSxy * read-only parameters describing the hardware's capabilities 350*c869993eSxy * read-write parameters controlling the advertised capabilities 351*c869993eSxy * read-only parameters describing the partner's capabilities 352*c869993eSxy * read-write parameters controlling the force speed and duplex 353*c869993eSxy * read-only parameters describing the link state 354*c869993eSxy * read-only parameters describing the driver properties 355*c869993eSxy * read-write parameters controlling the driver properties 356*c869993eSxy */ 357*c869993eSxy enum { 358*c869993eSxy PARAM_AUTONEG_CAP, 359*c869993eSxy PARAM_PAUSE_CAP, 360*c869993eSxy PARAM_ASYM_PAUSE_CAP, 361*c869993eSxy PARAM_1000FDX_CAP, 362*c869993eSxy PARAM_1000HDX_CAP, 363*c869993eSxy PARAM_100T4_CAP, 364*c869993eSxy PARAM_100FDX_CAP, 365*c869993eSxy PARAM_100HDX_CAP, 366*c869993eSxy PARAM_10FDX_CAP, 367*c869993eSxy PARAM_10HDX_CAP, 368*c869993eSxy PARAM_REM_FAULT, 369*c869993eSxy 370*c869993eSxy PARAM_ADV_AUTONEG_CAP, 371*c869993eSxy PARAM_ADV_PAUSE_CAP, 372*c869993eSxy PARAM_ADV_ASYM_PAUSE_CAP, 373*c869993eSxy PARAM_ADV_1000FDX_CAP, 374*c869993eSxy PARAM_ADV_1000HDX_CAP, 375*c869993eSxy PARAM_ADV_100T4_CAP, 376*c869993eSxy PARAM_ADV_100FDX_CAP, 377*c869993eSxy PARAM_ADV_100HDX_CAP, 378*c869993eSxy PARAM_ADV_10FDX_CAP, 379*c869993eSxy PARAM_ADV_10HDX_CAP, 380*c869993eSxy PARAM_ADV_REM_FAULT, 381*c869993eSxy 382*c869993eSxy PARAM_LP_AUTONEG_CAP, 383*c869993eSxy PARAM_LP_PAUSE_CAP, 384*c869993eSxy PARAM_LP_ASYM_PAUSE_CAP, 385*c869993eSxy PARAM_LP_1000FDX_CAP, 386*c869993eSxy PARAM_LP_1000HDX_CAP, 387*c869993eSxy PARAM_LP_100T4_CAP, 388*c869993eSxy PARAM_LP_100FDX_CAP, 389*c869993eSxy PARAM_LP_100HDX_CAP, 390*c869993eSxy PARAM_LP_10FDX_CAP, 391*c869993eSxy PARAM_LP_10HDX_CAP, 392*c869993eSxy PARAM_LP_REM_FAULT, 393*c869993eSxy 394*c869993eSxy PARAM_LINK_STATUS, 395*c869993eSxy PARAM_LINK_SPEED, 396*c869993eSxy PARAM_LINK_DUPLEX, 397*c869993eSxy 398*c869993eSxy PARAM_COUNT 399*c869993eSxy }; 400*c869993eSxy 401*c869993eSxy typedef union igb_ether_addr { 402*c869993eSxy struct { 403*c869993eSxy uint32_t high; 404*c869993eSxy uint32_t low; 405*c869993eSxy } reg; 406*c869993eSxy struct { 407*c869993eSxy uint8_t set; 408*c869993eSxy uint8_t redundant; 409*c869993eSxy uint8_t addr[ETHERADDRL]; 410*c869993eSxy } mac; 411*c869993eSxy } igb_ether_addr_t; 412*c869993eSxy 413*c869993eSxy typedef enum { 414*c869993eSxy USE_NONE, 415*c869993eSxy USE_COPY, 416*c869993eSxy USE_DMA 417*c869993eSxy } tx_type_t; 418*c869993eSxy 419*c869993eSxy typedef enum { 420*c869993eSxy RCB_FREE, 421*c869993eSxy RCB_SENDUP 422*c869993eSxy } rcb_state_t; 423*c869993eSxy 424*c869993eSxy typedef struct hcksum_context { 425*c869993eSxy uint32_t hcksum_flags; 426*c869993eSxy uint32_t ip_hdr_len; 427*c869993eSxy uint32_t mac_hdr_len; 428*c869993eSxy uint32_t l4_proto; 429*c869993eSxy } hcksum_context_t; 430*c869993eSxy 431*c869993eSxy /* Hold address/length of each DMA segment */ 432*c869993eSxy typedef struct sw_desc { 433*c869993eSxy uint64_t address; 434*c869993eSxy size_t length; 435*c869993eSxy } sw_desc_t; 436*c869993eSxy 437*c869993eSxy /* Handles and addresses of DMA buffer */ 438*c869993eSxy typedef struct dma_buffer { 439*c869993eSxy caddr_t address; /* Virtual address */ 440*c869993eSxy uint64_t dma_address; /* DMA (Hardware) address */ 441*c869993eSxy ddi_acc_handle_t acc_handle; /* Data access handle */ 442*c869993eSxy ddi_dma_handle_t dma_handle; /* DMA handle */ 443*c869993eSxy size_t size; /* Buffer size */ 444*c869993eSxy size_t len; /* Data length in the buffer */ 445*c869993eSxy } dma_buffer_t; 446*c869993eSxy 447*c869993eSxy /* 448*c869993eSxy * Tx Control Block 449*c869993eSxy */ 450*c869993eSxy typedef struct tx_control_block { 451*c869993eSxy single_link_t link; 452*c869993eSxy uint32_t frag_num; 453*c869993eSxy uint32_t desc_num; 454*c869993eSxy mblk_t *mp; 455*c869993eSxy tx_type_t tx_type; 456*c869993eSxy ddi_dma_handle_t tx_dma_handle; 457*c869993eSxy dma_buffer_t tx_buf; 458*c869993eSxy sw_desc_t desc[MAX_COOKIE]; 459*c869993eSxy } tx_control_block_t; 460*c869993eSxy 461*c869993eSxy /* 462*c869993eSxy * RX Control Block 463*c869993eSxy */ 464*c869993eSxy typedef struct rx_control_block { 465*c869993eSxy mblk_t *mp; 466*c869993eSxy rcb_state_t state; 467*c869993eSxy dma_buffer_t rx_buf; 468*c869993eSxy frtn_t free_rtn; 469*c869993eSxy struct igb_rx_ring *rx_ring; 470*c869993eSxy } rx_control_block_t; 471*c869993eSxy 472*c869993eSxy /* 473*c869993eSxy * Software Data Structure for Tx Ring 474*c869993eSxy */ 475*c869993eSxy typedef struct igb_tx_ring { 476*c869993eSxy uint32_t index; /* Ring index */ 477*c869993eSxy 478*c869993eSxy /* 479*c869993eSxy * Mutexes 480*c869993eSxy */ 481*c869993eSxy kmutex_t tx_lock; 482*c869993eSxy kmutex_t recycle_lock; 483*c869993eSxy kmutex_t tcb_head_lock; 484*c869993eSxy kmutex_t tcb_tail_lock; 485*c869993eSxy 486*c869993eSxy /* 487*c869993eSxy * Tx descriptor ring definitions 488*c869993eSxy */ 489*c869993eSxy dma_buffer_t tbd_area; 490*c869993eSxy union e1000_adv_tx_desc *tbd_ring; 491*c869993eSxy uint32_t tbd_head; /* Index of next tbd to recycle */ 492*c869993eSxy uint32_t tbd_tail; /* Index of next tbd to transmit */ 493*c869993eSxy uint32_t tbd_free; /* Number of free tbd */ 494*c869993eSxy 495*c869993eSxy /* 496*c869993eSxy * Tx control block list definitions 497*c869993eSxy */ 498*c869993eSxy tx_control_block_t *tcb_area; 499*c869993eSxy tx_control_block_t **work_list; 500*c869993eSxy tx_control_block_t **free_list; 501*c869993eSxy uint32_t tcb_head; /* Head index of free list */ 502*c869993eSxy uint32_t tcb_tail; /* Tail index of free list */ 503*c869993eSxy uint32_t tcb_free; /* Number of free tcb in free list */ 504*c869993eSxy 505*c869993eSxy uint32_t *tbd_head_wb; /* Head write-back */ 506*c869993eSxy uint32_t (*tx_recycle)(struct igb_tx_ring *); 507*c869993eSxy 508*c869993eSxy /* 509*c869993eSxy * TCP/UDP checksum offload 510*c869993eSxy */ 511*c869993eSxy hcksum_context_t hcksum_context; 512*c869993eSxy 513*c869993eSxy /* 514*c869993eSxy * Tx ring settings and status 515*c869993eSxy */ 516*c869993eSxy uint32_t ring_size; /* Tx descriptor ring size */ 517*c869993eSxy uint32_t free_list_size; /* Tx free list size */ 518*c869993eSxy uint32_t copy_thresh; 519*c869993eSxy uint32_t recycle_thresh; 520*c869993eSxy uint32_t overload_thresh; 521*c869993eSxy uint32_t resched_thresh; 522*c869993eSxy 523*c869993eSxy boolean_t reschedule; 524*c869993eSxy uint32_t recycle_fail; 525*c869993eSxy uint32_t stall_watchdog; 526*c869993eSxy 527*c869993eSxy #ifdef IGB_DEBUG 528*c869993eSxy /* 529*c869993eSxy * Debug statistics 530*c869993eSxy */ 531*c869993eSxy uint32_t stat_overload; 532*c869993eSxy uint32_t stat_fail_no_tbd; 533*c869993eSxy uint32_t stat_fail_no_tcb; 534*c869993eSxy uint32_t stat_fail_dma_bind; 535*c869993eSxy uint32_t stat_reschedule; 536*c869993eSxy #endif 537*c869993eSxy 538*c869993eSxy /* 539*c869993eSxy * Pointer to the igb struct 540*c869993eSxy */ 541*c869993eSxy struct igb *igb; 542*c869993eSxy 543*c869993eSxy } igb_tx_ring_t; 544*c869993eSxy 545*c869993eSxy /* 546*c869993eSxy * Software Receive Ring 547*c869993eSxy */ 548*c869993eSxy typedef struct igb_rx_ring { 549*c869993eSxy uint32_t index; /* Ring index */ 550*c869993eSxy uint32_t intr_vector; /* Interrupt vector index */ 551*c869993eSxy 552*c869993eSxy /* 553*c869993eSxy * Mutexes 554*c869993eSxy */ 555*c869993eSxy kmutex_t rx_lock; /* Rx access lock */ 556*c869993eSxy kmutex_t recycle_lock; /* Recycle lock, for rcb_tail */ 557*c869993eSxy 558*c869993eSxy /* 559*c869993eSxy * Rx descriptor ring definitions 560*c869993eSxy */ 561*c869993eSxy dma_buffer_t rbd_area; /* DMA buffer of rx desc ring */ 562*c869993eSxy union e1000_adv_rx_desc *rbd_ring; /* Rx desc ring */ 563*c869993eSxy uint32_t rbd_next; /* Index of next rx desc */ 564*c869993eSxy 565*c869993eSxy /* 566*c869993eSxy * Rx control block list definitions 567*c869993eSxy */ 568*c869993eSxy rx_control_block_t *rcb_area; 569*c869993eSxy rx_control_block_t **work_list; /* Work list of rcbs */ 570*c869993eSxy rx_control_block_t **free_list; /* Free list of rcbs */ 571*c869993eSxy uint32_t rcb_head; /* Index of next free rcb */ 572*c869993eSxy uint32_t rcb_tail; /* Index to put recycled rcb */ 573*c869993eSxy uint32_t rcb_free; /* Number of free rcbs */ 574*c869993eSxy 575*c869993eSxy /* 576*c869993eSxy * Rx ring settings and status 577*c869993eSxy */ 578*c869993eSxy uint32_t ring_size; /* Rx descriptor ring size */ 579*c869993eSxy uint32_t free_list_size; /* Rx free list size */ 580*c869993eSxy uint32_t limit_per_intr; /* Max packets per interrupt */ 581*c869993eSxy uint32_t copy_thresh; 582*c869993eSxy 583*c869993eSxy #ifdef IGB_DEBUG 584*c869993eSxy /* 585*c869993eSxy * Debug statistics 586*c869993eSxy */ 587*c869993eSxy uint32_t stat_frame_error; 588*c869993eSxy uint32_t stat_cksum_error; 589*c869993eSxy uint32_t stat_exceed_pkt; 590*c869993eSxy #endif 591*c869993eSxy 592*c869993eSxy struct igb *igb; /* Pointer to igb struct */ 593*c869993eSxy 594*c869993eSxy } igb_rx_ring_t; 595*c869993eSxy 596*c869993eSxy typedef struct igb { 597*c869993eSxy int instance; 598*c869993eSxy mac_handle_t mac_hdl; 599*c869993eSxy dev_info_t *dip; 600*c869993eSxy struct e1000_hw hw; 601*c869993eSxy struct igb_osdep osdep; 602*c869993eSxy 603*c869993eSxy uint32_t igb_state; 604*c869993eSxy link_state_t link_state; 605*c869993eSxy uint32_t link_speed; 606*c869993eSxy uint32_t link_duplex; 607*c869993eSxy uint32_t link_down_timeout; 608*c869993eSxy 609*c869993eSxy uint32_t reset_count; 610*c869993eSxy uint32_t attach_progress; 611*c869993eSxy uint32_t loopback_mode; 612*c869993eSxy uint32_t max_frame_size; 613*c869993eSxy 614*c869993eSxy /* 615*c869993eSxy * Receive Rings 616*c869993eSxy */ 617*c869993eSxy igb_rx_ring_t *rx_rings; /* Array of rx rings */ 618*c869993eSxy uint32_t num_rx_rings; /* Number of rx rings in use */ 619*c869993eSxy uint32_t rx_ring_size; /* Rx descriptor ring size */ 620*c869993eSxy uint32_t rx_buf_size; /* Rx buffer size */ 621*c869993eSxy 622*c869993eSxy /* 623*c869993eSxy * Transmit Rings 624*c869993eSxy */ 625*c869993eSxy igb_tx_ring_t *tx_rings; /* Array of tx rings */ 626*c869993eSxy uint32_t num_tx_rings; /* Number of tx rings in use */ 627*c869993eSxy uint32_t tx_ring_size; /* Tx descriptor ring size */ 628*c869993eSxy uint32_t tx_buf_size; /* Tx buffer size */ 629*c869993eSxy 630*c869993eSxy boolean_t tx_head_wb_enable; /* Tx head wrtie-back */ 631*c869993eSxy boolean_t tx_hcksum_enable; /* Tx h/w cksum offload */ 632*c869993eSxy boolean_t lso_enable; /* Large Segment Offload */ 633*c869993eSxy uint32_t tx_copy_thresh; /* Tx copy threshold */ 634*c869993eSxy uint32_t tx_recycle_thresh; /* Tx recycle threshold */ 635*c869993eSxy uint32_t tx_overload_thresh; /* Tx overload threshold */ 636*c869993eSxy uint32_t tx_resched_thresh; /* Tx reschedule threshold */ 637*c869993eSxy boolean_t rx_hcksum_enable; /* Rx h/w cksum offload */ 638*c869993eSxy uint32_t rx_copy_thresh; /* Rx copy threshold */ 639*c869993eSxy uint32_t rx_limit_per_intr; /* Rx pkts per interrupt */ 640*c869993eSxy uint32_t intr_throttling[MAX_NUM_EITR]; 641*c869993eSxy uint32_t intr_force; 642*c869993eSxy 643*c869993eSxy int intr_type; 644*c869993eSxy int intr_cnt; 645*c869993eSxy int intr_cap; 646*c869993eSxy size_t intr_size; 647*c869993eSxy uint_t intr_pri; 648*c869993eSxy ddi_intr_handle_t *htable; 649*c869993eSxy uint32_t eims_mask; 650*c869993eSxy 651*c869993eSxy kmutex_t gen_lock; /* General lock for device access */ 652*c869993eSxy kmutex_t watchdog_lock; 653*c869993eSxy 654*c869993eSxy boolean_t watchdog_enable; 655*c869993eSxy boolean_t watchdog_start; 656*c869993eSxy timeout_id_t watchdog_tid; 657*c869993eSxy 658*c869993eSxy boolean_t unicst_init; 659*c869993eSxy uint32_t unicst_avail; 660*c869993eSxy uint32_t unicst_total; 661*c869993eSxy igb_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 662*c869993eSxy uint32_t mcast_count; 663*c869993eSxy struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES]; 664*c869993eSxy 665*c869993eSxy /* 666*c869993eSxy * Kstat definitions 667*c869993eSxy */ 668*c869993eSxy kstat_t *igb_ks; 669*c869993eSxy 670*c869993eSxy /* 671*c869993eSxy * NDD definitions 672*c869993eSxy */ 673*c869993eSxy caddr_t nd_data; 674*c869993eSxy nd_param_t nd_params[PARAM_COUNT]; 675*c869993eSxy 676*c869993eSxy } igb_t; 677*c869993eSxy 678*c869993eSxy typedef struct igb_stat { 679*c869993eSxy 680*c869993eSxy kstat_named_t link_speed; /* Link Speed */ 681*c869993eSxy #ifdef IGB_DEBUG 682*c869993eSxy kstat_named_t reset_count; /* Reset Count */ 683*c869993eSxy 684*c869993eSxy kstat_named_t rx_frame_error; /* Rx Error in Packet */ 685*c869993eSxy kstat_named_t rx_cksum_error; /* Rx Checksum Error */ 686*c869993eSxy kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */ 687*c869993eSxy 688*c869993eSxy kstat_named_t tx_overload; /* Tx Desc Ring Overload */ 689*c869993eSxy kstat_named_t tx_fail_no_tcb; /* Tx Fail Freelist Empty */ 690*c869993eSxy kstat_named_t tx_fail_no_tbd; /* Tx Fail Desc Ring Empty */ 691*c869993eSxy kstat_named_t tx_fail_dma_bind; /* Tx Fail DMA bind */ 692*c869993eSxy kstat_named_t tx_reschedule; /* Tx Reschedule */ 693*c869993eSxy 694*c869993eSxy kstat_named_t gprc; /* Good Packets Received Count */ 695*c869993eSxy kstat_named_t gptc; /* Good Packets Xmitted Count */ 696*c869993eSxy kstat_named_t gor; /* Good Octets Received Count */ 697*c869993eSxy kstat_named_t got; /* Good Octets Xmitd Count */ 698*c869993eSxy kstat_named_t prc64; /* Packets Received - 64b */ 699*c869993eSxy kstat_named_t prc127; /* Packets Received - 65-127b */ 700*c869993eSxy kstat_named_t prc255; /* Packets Received - 127-255b */ 701*c869993eSxy kstat_named_t prc511; /* Packets Received - 256-511b */ 702*c869993eSxy kstat_named_t prc1023; /* Packets Received - 511-1023b */ 703*c869993eSxy kstat_named_t prc1522; /* Packets Received - 1024-1522b */ 704*c869993eSxy kstat_named_t ptc64; /* Packets Xmitted (64b) */ 705*c869993eSxy kstat_named_t ptc127; /* Packets Xmitted (64-127b) */ 706*c869993eSxy kstat_named_t ptc255; /* Packets Xmitted (128-255b) */ 707*c869993eSxy kstat_named_t ptc511; /* Packets Xmitted (255-511b) */ 708*c869993eSxy kstat_named_t ptc1023; /* Packets Xmitted (512-1023b) */ 709*c869993eSxy kstat_named_t ptc1522; /* Packets Xmitted (1024-1522b */ 710*c869993eSxy #endif 711*c869993eSxy kstat_named_t crcerrs; /* CRC Error Count */ 712*c869993eSxy kstat_named_t symerrs; /* Symbol Error Count */ 713*c869993eSxy kstat_named_t mpc; /* Missed Packet Count */ 714*c869993eSxy kstat_named_t scc; /* Single Collision Count */ 715*c869993eSxy kstat_named_t ecol; /* Excessive Collision Count */ 716*c869993eSxy kstat_named_t mcc; /* Multiple Collision Count */ 717*c869993eSxy kstat_named_t latecol; /* Late Collision Count */ 718*c869993eSxy kstat_named_t colc; /* Collision Count */ 719*c869993eSxy kstat_named_t dc; /* Defer Count */ 720*c869993eSxy kstat_named_t sec; /* Sequence Error Count */ 721*c869993eSxy kstat_named_t rlec; /* Receive Length Error Count */ 722*c869993eSxy kstat_named_t xonrxc; /* XON Received Count */ 723*c869993eSxy kstat_named_t xontxc; /* XON Xmitted Count */ 724*c869993eSxy kstat_named_t xoffrxc; /* XOFF Received Count */ 725*c869993eSxy kstat_named_t xofftxc; /* Xoff Xmitted Count */ 726*c869993eSxy kstat_named_t fcruc; /* Unknown Flow Conrol Packet Rcvd Count */ 727*c869993eSxy kstat_named_t bprc; /* Broadcasts Pkts Received Count */ 728*c869993eSxy kstat_named_t mprc; /* Multicast Pkts Received Count */ 729*c869993eSxy kstat_named_t rnbc; /* Receive No Buffers Count */ 730*c869993eSxy kstat_named_t ruc; /* Receive Undersize Count */ 731*c869993eSxy kstat_named_t rfc; /* Receive Frag Count */ 732*c869993eSxy kstat_named_t roc; /* Receive Oversize Count */ 733*c869993eSxy kstat_named_t rjc; /* Receive Jabber Count */ 734*c869993eSxy kstat_named_t tor; /* Total Octets Recvd Count */ 735*c869993eSxy kstat_named_t tot; /* Total Octets Xmted Count */ 736*c869993eSxy kstat_named_t tpr; /* Total Packets Received */ 737*c869993eSxy kstat_named_t tpt; /* Total Packets Xmitted */ 738*c869993eSxy kstat_named_t mptc; /* Multicast Packets Xmited Count */ 739*c869993eSxy kstat_named_t bptc; /* Broadcast Packets Xmited Count */ 740*c869993eSxy kstat_named_t algnerrc; /* Alignment Error count */ 741*c869993eSxy kstat_named_t rxerrc; /* Rx Error Count */ 742*c869993eSxy kstat_named_t tncrs; /* Transmit with no CRS */ 743*c869993eSxy kstat_named_t cexterr; /* Carrier Extension Error count */ 744*c869993eSxy kstat_named_t tsctc; /* TCP seg contexts xmit count */ 745*c869993eSxy kstat_named_t tsctfc; /* TCP seg contexts xmit fail count */ 746*c869993eSxy } igb_stat_t; 747*c869993eSxy 748*c869993eSxy /* 749*c869993eSxy * Function prototypes in e1000_osdep.c 750*c869993eSxy */ 751*c869993eSxy void e1000_enable_pciex_master(struct e1000_hw *); 752*c869993eSxy 753*c869993eSxy /* 754*c869993eSxy * Function prototypes in igb_buf.c 755*c869993eSxy */ 756*c869993eSxy int igb_alloc_dma(igb_t *); 757*c869993eSxy void igb_free_dma(igb_t *); 758*c869993eSxy 759*c869993eSxy /* 760*c869993eSxy * Function prototypes in igb_main.c 761*c869993eSxy */ 762*c869993eSxy int igb_start(igb_t *); 763*c869993eSxy void igb_stop(igb_t *); 764*c869993eSxy int igb_setup_link(igb_t *, boolean_t); 765*c869993eSxy int igb_unicst_set(igb_t *, const uint8_t *, mac_addr_slot_t); 766*c869993eSxy int igb_multicst_add(igb_t *, const uint8_t *); 767*c869993eSxy int igb_multicst_remove(igb_t *, const uint8_t *); 768*c869993eSxy enum ioc_reply igb_loopback_ioctl(igb_t *, struct iocblk *, mblk_t *); 769*c869993eSxy void igb_enable_watchdog_timer(igb_t *); 770*c869993eSxy void igb_disable_watchdog_timer(igb_t *); 771*c869993eSxy int igb_atomic_reserve(uint32_t *, uint32_t); 772*c869993eSxy 773*c869993eSxy /* 774*c869993eSxy * Function prototypes in igb_gld.c 775*c869993eSxy */ 776*c869993eSxy int igb_m_start(void *); 777*c869993eSxy void igb_m_stop(void *); 778*c869993eSxy int igb_m_promisc(void *, boolean_t); 779*c869993eSxy int igb_m_multicst(void *, boolean_t, const uint8_t *); 780*c869993eSxy int igb_m_unicst(void *, const uint8_t *); 781*c869993eSxy int igb_m_stat(void *, uint_t, uint64_t *); 782*c869993eSxy void igb_m_resources(void *); 783*c869993eSxy void igb_m_ioctl(void *, queue_t *, mblk_t *); 784*c869993eSxy int igb_m_unicst_add(void *, mac_multi_addr_t *); 785*c869993eSxy int igb_m_unicst_remove(void *, mac_addr_slot_t); 786*c869993eSxy int igb_m_unicst_modify(void *, mac_multi_addr_t *); 787*c869993eSxy int igb_m_unicst_get(void *, mac_multi_addr_t *); 788*c869993eSxy boolean_t igb_m_getcapab(void *, mac_capab_t, void *); 789*c869993eSxy 790*c869993eSxy /* 791*c869993eSxy * Function prototypes in igb_rx.c 792*c869993eSxy */ 793*c869993eSxy mblk_t *igb_rx(igb_rx_ring_t *); 794*c869993eSxy void igb_rx_recycle(caddr_t arg); 795*c869993eSxy 796*c869993eSxy /* 797*c869993eSxy * Function prototypes in igb_tx.c 798*c869993eSxy */ 799*c869993eSxy mblk_t *igb_m_tx(void *, mblk_t *); 800*c869993eSxy void igb_free_tcb(tx_control_block_t *); 801*c869993eSxy void igb_put_free_list(igb_tx_ring_t *, link_list_t *); 802*c869993eSxy uint32_t igb_tx_recycle_legacy(igb_tx_ring_t *); 803*c869993eSxy uint32_t igb_tx_recycle_head_wb(igb_tx_ring_t *); 804*c869993eSxy 805*c869993eSxy /* 806*c869993eSxy * Function prototypes in igb_log.c 807*c869993eSxy */ 808*c869993eSxy void igb_notice(void *, const char *, ...); 809*c869993eSxy void igb_log(void *, const char *, ...); 810*c869993eSxy void igb_error(void *, const char *, ...); 811*c869993eSxy 812*c869993eSxy /* 813*c869993eSxy * Function prototypes in igb_ndd.c 814*c869993eSxy */ 815*c869993eSxy int igb_nd_init(igb_t *); 816*c869993eSxy void igb_nd_cleanup(igb_t *); 817*c869993eSxy enum ioc_reply igb_nd_ioctl(igb_t *, queue_t *, mblk_t *, struct iocblk *); 818*c869993eSxy 819*c869993eSxy /* 820*c869993eSxy * Function prototypes in igb_stat.c 821*c869993eSxy */ 822*c869993eSxy int igb_init_stats(igb_t *); 823*c869993eSxy 824*c869993eSxy 825*c869993eSxy #ifdef __cplusplus 826*c869993eSxy } 827*c869993eSxy #endif 828*c869993eSxy 829*c869993eSxy #endif /* _IGB_SW_H */ 830