1c869993eSxy /* 2c869993eSxy * CDDL HEADER START 3c869993eSxy * 4c869993eSxy * The contents of this file are subject to the terms of the 5c869993eSxy * Common Development and Distribution License (the "License"). 6c869993eSxy * You may not use this file except in compliance with the License. 7c869993eSxy * 80dc2366fSVenugopal Iyer * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 90dc2366fSVenugopal Iyer * or http://www.opensolaris.org/os/licensing. 10c869993eSxy * See the License for the specific language governing permissions 11c869993eSxy * and limitations under the License. 12c869993eSxy * 130dc2366fSVenugopal Iyer * When distributing Covered Code, include this CDDL HEADER in each 140dc2366fSVenugopal Iyer * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15c869993eSxy * If applicable, add the following below this CDDL HEADER, with the 16c869993eSxy * fields enclosed by brackets "[]" replaced with your own identifying 17c869993eSxy * information: Portions Copyright [yyyy] [name of copyright owner] 18c869993eSxy * 19c869993eSxy * CDDL HEADER END 20c869993eSxy */ 21c869993eSxy 22da14cebeSEric Cheng /* 2308a0f9b0Schenlu chen - Sun Microsystems - Beijing China * Copyright(c) 2007-2010 Intel Corporation. All rights reserved. 2408a0f9b0Schenlu chen - Sun Microsystems - Beijing China */ 2508a0f9b0Schenlu chen - Sun Microsystems - Beijing China 2608a0f9b0Schenlu chen - Sun Microsystems - Beijing China /* 2708a0f9b0Schenlu chen - Sun Microsystems - Beijing China * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. 28c869993eSxy */ 29c869993eSxy 30c869993eSxy #ifndef _IGB_SW_H 31c869993eSxy #define _IGB_SW_H 32c869993eSxy 33c869993eSxy #ifdef __cplusplus 34c869993eSxy extern "C" { 35c869993eSxy #endif 36c869993eSxy 37c869993eSxy #include <sys/types.h> 38c869993eSxy #include <sys/conf.h> 39c869993eSxy #include <sys/debug.h> 40c869993eSxy #include <sys/stropts.h> 41c869993eSxy #include <sys/stream.h> 42c869993eSxy #include <sys/strsun.h> 43c869993eSxy #include <sys/strlog.h> 44c869993eSxy #include <sys/kmem.h> 45c869993eSxy #include <sys/stat.h> 46c869993eSxy #include <sys/kstat.h> 47c869993eSxy #include <sys/modctl.h> 48c869993eSxy #include <sys/errno.h> 49c869993eSxy #include <sys/dlpi.h> 50da14cebeSEric Cheng #include <sys/mac_provider.h> 51c869993eSxy #include <sys/mac_ether.h> 52c869993eSxy #include <sys/vlan.h> 53c869993eSxy #include <sys/ddi.h> 54c869993eSxy #include <sys/sunddi.h> 55c869993eSxy #include <sys/pci.h> 56c869993eSxy #include <sys/pcie.h> 57c869993eSxy #include <sys/sdt.h> 58c869993eSxy #include <sys/ethernet.h> 59c869993eSxy #include <sys/pattr.h> 60c869993eSxy #include <sys/strsubr.h> 61c869993eSxy #include <sys/netlb.h> 62c869993eSxy #include <sys/random.h> 63c869993eSxy #include <inet/common.h> 64d11274aaSPaul Guo #include <inet/tcp.h> 65c869993eSxy #include <inet/ip.h> 66c869993eSxy #include <inet/mi.h> 67c869993eSxy #include <inet/nd.h> 688bb4b220Sgl #include <sys/ddifm.h> 698bb4b220Sgl #include <sys/fm/protocol.h> 708bb4b220Sgl #include <sys/fm/util.h> 718bb4b220Sgl #include <sys/fm/io/ddi.h> 72*75eba5b6SRobert Mustacchi #include "e1000_api.h" 73*75eba5b6SRobert Mustacchi #include "e1000_82575.h" 74c869993eSxy 75c869993eSxy 76c869993eSxy #define MODULE_NAME "igb" /* module name */ 77c869993eSxy 78c869993eSxy #define IGB_SUCCESS DDI_SUCCESS 79c869993eSxy #define IGB_FAILURE DDI_FAILURE 80c869993eSxy 81c869993eSxy #define IGB_UNKNOWN 0x00 82c869993eSxy #define IGB_INITIALIZED 0x01 83c869993eSxy #define IGB_STARTED 0x02 84c869993eSxy #define IGB_SUSPENDED 0x04 853f7e60a6Szhefeng xu - Sun Microsystems - Beijing China #define IGB_STALL 0x08 86cf8dcc9bSzhefeng xu - Sun Microsystems - Beijing China #define IGB_ERROR 0x80 87c869993eSxy 88ac7f5757Schenlu chen - Sun Microsystems - Beijing China #define IGB_RX_STOPPED 0x1 89ac7f5757Schenlu chen - Sun Microsystems - Beijing China 90c869993eSxy #define IGB_INTR_NONE 0 91c869993eSxy #define IGB_INTR_MSIX 1 92c869993eSxy #define IGB_INTR_MSI 2 93c869993eSxy #define IGB_INTR_LEGACY 3 94c869993eSxy 9580a11ad2Schenlu chen - Sun Microsystems - Beijing China #define IGB_ADAPTER_REGSET 1 /* mapping adapter registers */ 9680a11ad2Schenlu chen - Sun Microsystems - Beijing China #define IGB_ADAPTER_MSIXTAB 4 /* mapping msi-x table */ 9780a11ad2Schenlu chen - Sun Microsystems - Beijing China 98da14cebeSEric Cheng #define IGB_NO_POLL -1 99da14cebeSEric Cheng #define IGB_NO_FREE_SLOT -1 100da14cebeSEric Cheng 101c869993eSxy #define MAX_NUM_UNICAST_ADDRESSES E1000_RAR_ENTRIES 1026ca163a1Svitezslav batrla - Sun Microsystems - Prague Czech Republic #define MCAST_ALLOC_COUNT 256 103d11274aaSPaul Guo #define MAX_COOKIE 18 104c869993eSxy #define MIN_NUM_TX_DESC 2 105c869993eSxy 10680a11ad2Schenlu chen - Sun Microsystems - Beijing China /* 10780a11ad2Schenlu chen - Sun Microsystems - Beijing China * Number of settings for interrupt throttle rate (ITR). There is one of 10880a11ad2Schenlu chen - Sun Microsystems - Beijing China * these per msi-x vector and it needs to be the maximum of all silicon 10980a11ad2Schenlu chen - Sun Microsystems - Beijing China * types supported by this driver. 11080a11ad2Schenlu chen - Sun Microsystems - Beijing China */ 11180a11ad2Schenlu chen - Sun Microsystems - Beijing China #define MAX_NUM_EITR 25 11280a11ad2Schenlu chen - Sun Microsystems - Beijing China 113c869993eSxy /* 114c869993eSxy * Maximum values for user configurable parameters 115c869993eSxy */ 116c869993eSxy #define MAX_TX_RING_SIZE 4096 117c869993eSxy #define MAX_RX_RING_SIZE 4096 118da14cebeSEric Cheng #define MAX_RX_GROUP_NUM 4 119c869993eSxy 120c869993eSxy #define MAX_MTU 9000 121c869993eSxy #define MAX_RX_LIMIT_PER_INTR 4096 122c869993eSxy 123c869993eSxy #define MAX_RX_COPY_THRESHOLD 9216 124c869993eSxy #define MAX_TX_COPY_THRESHOLD 9216 125c869993eSxy #define MAX_TX_RECYCLE_THRESHOLD DEFAULT_TX_RING_SIZE 126c869993eSxy #define MAX_TX_OVERLOAD_THRESHOLD DEFAULT_TX_RING_SIZE 127c869993eSxy #define MAX_TX_RESCHED_THRESHOLD DEFAULT_TX_RING_SIZE 1286ca163a1Svitezslav batrla - Sun Microsystems - Prague Czech Republic #define MAX_MCAST_NUM 8192 129c869993eSxy 130c869993eSxy /* 131c869993eSxy * Minimum values for user configurable parameters 132c869993eSxy */ 133c869993eSxy #define MIN_TX_RING_SIZE 64 134c869993eSxy #define MIN_RX_RING_SIZE 64 135da14cebeSEric Cheng #define MIN_RX_GROUP_NUM 1 136c869993eSxy 137c869993eSxy #define MIN_MTU ETHERMIN 138c869993eSxy #define MIN_RX_LIMIT_PER_INTR 16 1393f7e60a6Szhefeng xu - Sun Microsystems - Beijing China 140c869993eSxy #define MIN_RX_COPY_THRESHOLD 0 141c869993eSxy #define MIN_TX_COPY_THRESHOLD 0 142c869993eSxy #define MIN_TX_RECYCLE_THRESHOLD MIN_NUM_TX_DESC 143c869993eSxy #define MIN_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 144c869993eSxy #define MIN_TX_RESCHED_THRESHOLD MIN_NUM_TX_DESC 1456ca163a1Svitezslav batrla - Sun Microsystems - Prague Czech Republic #define MIN_MCAST_NUM 8 146c869993eSxy 147c869993eSxy /* 148c869993eSxy * Default values for user configurable parameters 149c869993eSxy */ 150c869993eSxy #define DEFAULT_TX_RING_SIZE 512 151c869993eSxy #define DEFAULT_RX_RING_SIZE 512 152da14cebeSEric Cheng #define DEFAULT_RX_GROUP_NUM 1 153c869993eSxy 154c869993eSxy #define DEFAULT_MTU ETHERMTU 155c869993eSxy #define DEFAULT_RX_LIMIT_PER_INTR 256 1563f7e60a6Szhefeng xu - Sun Microsystems - Beijing China 157c869993eSxy #define DEFAULT_RX_COPY_THRESHOLD 128 158c869993eSxy #define DEFAULT_TX_COPY_THRESHOLD 512 159d11274aaSPaul Guo #define DEFAULT_TX_RECYCLE_THRESHOLD (MAX_COOKIE + 1) 160c869993eSxy #define DEFAULT_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 161c869993eSxy #define DEFAULT_TX_RESCHED_THRESHOLD 128 16269b2d733SGuoqing Zhu #define DEFAULT_TX_RESCHED_THRESHOLD_LOW 32 1636ca163a1Svitezslav batrla - Sun Microsystems - Prague Czech Republic #define DEFAULT_MCAST_NUM 4096 164c869993eSxy 165d11274aaSPaul Guo #define IGB_LSO_MAXLEN 65535 166d11274aaSPaul Guo 167c869993eSxy #define TX_DRAIN_TIME 200 168c869993eSxy #define RX_DRAIN_TIME 200 169c869993eSxy 170c869993eSxy #define STALL_WATCHDOG_TIMEOUT 8 /* 8 seconds */ 171c869993eSxy 172c869993eSxy /* 173c869993eSxy * Defined for IP header alignment. 174c869993eSxy */ 175c869993eSxy #define IPHDR_ALIGN_ROOM 2 176c869993eSxy 177c869993eSxy /* 178c869993eSxy * Bit flags for attach_progress 179c869993eSxy */ 180c869993eSxy #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 181c869993eSxy #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 182c869993eSxy #define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */ 183c869993eSxy #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */ 184c869993eSxy #define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */ 185c869993eSxy #define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */ 186c869993eSxy #define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */ 187b8d0a377Schenlu chen - Sun Microsystems - Beijing China #define ATTACH_PROGRESS_INIT_ADAPTER 0x0080 /* Adapter initialized */ 188c869993eSxy #define ATTACH_PROGRESS_STATS 0x0200 /* Kstats created */ 189c869993eSxy #define ATTACH_PROGRESS_MAC 0x0800 /* MAC registered */ 190c869993eSxy #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */ 1918bb4b220Sgl #define ATTACH_PROGRESS_FMINIT 0x2000 /* FMA initialized */ 192c869993eSxy 193c869993eSxy #define PROP_ADV_AUTONEG_CAP "adv_autoneg_cap" 194c869993eSxy #define PROP_ADV_1000FDX_CAP "adv_1000fdx_cap" 195c869993eSxy #define PROP_ADV_1000HDX_CAP "adv_1000hdx_cap" 196c869993eSxy #define PROP_ADV_100FDX_CAP "adv_100fdx_cap" 197c869993eSxy #define PROP_ADV_100HDX_CAP "adv_100hdx_cap" 198c869993eSxy #define PROP_ADV_10FDX_CAP "adv_10fdx_cap" 199c869993eSxy #define PROP_ADV_10HDX_CAP "adv_10hdx_cap" 200c869993eSxy #define PROP_DEFAULT_MTU "default_mtu" 201c869993eSxy #define PROP_FLOW_CONTROL "flow_control" 202c869993eSxy #define PROP_TX_RING_SIZE "tx_ring_size" 203c869993eSxy #define PROP_RX_RING_SIZE "rx_ring_size" 204da14cebeSEric Cheng #define PROP_MR_ENABLE "mr_enable" 205da14cebeSEric Cheng #define PROP_RX_GROUP_NUM "rx_group_number" 206c869993eSxy 207c869993eSxy #define PROP_INTR_FORCE "intr_force" 208c869993eSxy #define PROP_TX_HCKSUM_ENABLE "tx_hcksum_enable" 209c869993eSxy #define PROP_RX_HCKSUM_ENABLE "rx_hcksum_enable" 210c869993eSxy #define PROP_LSO_ENABLE "lso_enable" 211c869993eSxy #define PROP_TX_HEAD_WB_ENABLE "tx_head_wb_enable" 212c869993eSxy #define PROP_TX_COPY_THRESHOLD "tx_copy_threshold" 213c869993eSxy #define PROP_TX_RECYCLE_THRESHOLD "tx_recycle_threshold" 214c869993eSxy #define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold" 215c869993eSxy #define PROP_TX_RESCHED_THRESHOLD "tx_resched_threshold" 216c869993eSxy #define PROP_RX_COPY_THRESHOLD "rx_copy_threshold" 217c869993eSxy #define PROP_RX_LIMIT_PER_INTR "rx_limit_per_intr" 218c869993eSxy #define PROP_INTR_THROTTLING "intr_throttling" 2196ca163a1Svitezslav batrla - Sun Microsystems - Prague Czech Republic #define PROP_MCAST_MAX_NUM "mcast_max_num" 220c869993eSxy 221c869993eSxy #define IGB_LB_NONE 0 222c869993eSxy #define IGB_LB_EXTERNAL 1 223c869993eSxy #define IGB_LB_INTERNAL_PHY 3 224c869993eSxy #define IGB_LB_INTERNAL_SERDES 4 225c869993eSxy 226c869993eSxy enum ioc_reply { 227c869993eSxy IOC_INVAL = -1, /* bad, NAK with EINVAL */ 228c869993eSxy IOC_DONE, /* OK, reply sent */ 229c869993eSxy IOC_ACK, /* OK, just send ACK */ 230c869993eSxy IOC_REPLY /* OK, just send reply */ 231c869993eSxy }; 232c869993eSxy 233d11274aaSPaul Guo /* 234d11274aaSPaul Guo * For s/w context extraction from a tx frame 235d11274aaSPaul Guo */ 236d11274aaSPaul Guo #define TX_CXT_SUCCESS 0 237d11274aaSPaul Guo #define TX_CXT_E_LSO_CSUM (-1) 238d11274aaSPaul Guo #define TX_CXT_E_ETHER_TYPE (-2) 239c869993eSxy 240c869993eSxy #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area)->dma_handle, \ 241c869993eSxy 0, 0, (flag))) 242c869993eSxy 243c869993eSxy /* 244c869993eSxy * Defined for ring index operations 245c869993eSxy * ASSERT(index < limit) 246c869993eSxy * ASSERT(step < limit) 247c869993eSxy * ASSERT(index1 < limit) 248c869993eSxy * ASSERT(index2 < limit) 249c869993eSxy */ 250c869993eSxy #define NEXT_INDEX(index, step, limit) (((index) + (step)) < (limit) ? \ 251c869993eSxy (index) + (step) : (index) + (step) - (limit)) 252c869993eSxy #define PREV_INDEX(index, step, limit) ((index) >= (step) ? \ 253c869993eSxy (index) - (step) : (index) + (limit) - (step)) 254c869993eSxy #define OFFSET(index1, index2, limit) ((index1) <= (index2) ? \ 255c869993eSxy (index2) - (index1) : (index2) + (limit) - (index1)) 256c869993eSxy 257c869993eSxy #define LINK_LIST_INIT(_LH) \ 258c869993eSxy (_LH)->head = (_LH)->tail = NULL 259c869993eSxy 260c869993eSxy #define LIST_GET_HEAD(_LH) ((single_link_t *)((_LH)->head)) 261c869993eSxy 262c869993eSxy #define LIST_POP_HEAD(_LH) \ 263c869993eSxy (single_link_t *)(_LH)->head; \ 264c869993eSxy { \ 265c869993eSxy if ((_LH)->head != NULL) { \ 266c869993eSxy (_LH)->head = (_LH)->head->link; \ 267c869993eSxy if ((_LH)->head == NULL) \ 268c869993eSxy (_LH)->tail = NULL; \ 269c869993eSxy } \ 270c869993eSxy } 271c869993eSxy 272c869993eSxy #define LIST_GET_TAIL(_LH) ((single_link_t *)((_LH)->tail)) 273c869993eSxy 274c869993eSxy #define LIST_PUSH_TAIL(_LH, _E) \ 275c869993eSxy if ((_LH)->tail != NULL) { \ 276c869993eSxy (_LH)->tail->link = (single_link_t *)(_E); \ 277c869993eSxy (_LH)->tail = (single_link_t *)(_E); \ 278c869993eSxy } else { \ 279c869993eSxy (_LH)->head = (_LH)->tail = (single_link_t *)(_E); \ 280c869993eSxy } \ 281c869993eSxy (_E)->link = NULL; 282c869993eSxy 283c869993eSxy #define LIST_GET_NEXT(_LH, _E) \ 284c869993eSxy (((_LH)->tail == (single_link_t *)(_E)) ? \ 285c869993eSxy NULL : ((single_link_t *)(_E))->link) 286c869993eSxy 287c869993eSxy 288c869993eSxy typedef struct single_link { 289c869993eSxy struct single_link *link; 290c869993eSxy } single_link_t; 291c869993eSxy 292c869993eSxy typedef struct link_list { 293c869993eSxy single_link_t *head; 294c869993eSxy single_link_t *tail; 295c869993eSxy } link_list_t; 296c869993eSxy 297c869993eSxy /* 298c869993eSxy * Property lookups 299c869993eSxy */ 300c869993eSxy #define IGB_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 301c869993eSxy DDI_PROP_DONTPASS, (n)) 302c869993eSxy #define IGB_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 303c869993eSxy DDI_PROP_DONTPASS, (n), -1) 304c869993eSxy 305c869993eSxy 30680a11ad2Schenlu chen - Sun Microsystems - Beijing China /* capability/feature flags */ 30780a11ad2Schenlu chen - Sun Microsystems - Beijing China #define IGB_FLAG_HAS_DCA (1 << 0) /* has Direct Cache Access */ 30880a11ad2Schenlu chen - Sun Microsystems - Beijing China #define IGB_FLAG_VMDQ_POOL (1 << 1) /* has vmdq capability */ 30980a11ad2Schenlu chen - Sun Microsystems - Beijing China #define IGB_FLAG_NEED_CTX_IDX (1 << 2) /* context descriptor needs index */ 31080a11ad2Schenlu chen - Sun Microsystems - Beijing China 31180a11ad2Schenlu chen - Sun Microsystems - Beijing China /* function pointer for nic-specific functions */ 31280a11ad2Schenlu chen - Sun Microsystems - Beijing China typedef void (*igb_nic_func_t)(struct igb *); 31380a11ad2Schenlu chen - Sun Microsystems - Beijing China 31480a11ad2Schenlu chen - Sun Microsystems - Beijing China /* adapter-specific info for each supported device type */ 31580a11ad2Schenlu chen - Sun Microsystems - Beijing China typedef struct adapter_info { 31680a11ad2Schenlu chen - Sun Microsystems - Beijing China /* limits */ 31780a11ad2Schenlu chen - Sun Microsystems - Beijing China uint32_t max_rx_que_num; /* maximum number of rx queues */ 31880a11ad2Schenlu chen - Sun Microsystems - Beijing China uint32_t min_rx_que_num; /* minimum number of rx queues */ 31980a11ad2Schenlu chen - Sun Microsystems - Beijing China uint32_t def_rx_que_num; /* default number of rx queues */ 32080a11ad2Schenlu chen - Sun Microsystems - Beijing China uint32_t max_tx_que_num; /* maximum number of tx queues */ 32180a11ad2Schenlu chen - Sun Microsystems - Beijing China uint32_t min_tx_que_num; /* minimum number of tx queues */ 32280a11ad2Schenlu chen - Sun Microsystems - Beijing China uint32_t def_tx_que_num; /* default number of tx queues */ 32380a11ad2Schenlu chen - Sun Microsystems - Beijing China uint32_t max_intr_throttle; /* maximum interrupt throttle */ 32480a11ad2Schenlu chen - Sun Microsystems - Beijing China uint32_t min_intr_throttle; /* minimum interrupt throttle */ 32580a11ad2Schenlu chen - Sun Microsystems - Beijing China uint32_t def_intr_throttle; /* default interrupt throttle */ 32680a11ad2Schenlu chen - Sun Microsystems - Beijing China /* function pointers */ 32780a11ad2Schenlu chen - Sun Microsystems - Beijing China igb_nic_func_t enable_intr; /* enable adapter interrupts */ 32880a11ad2Schenlu chen - Sun Microsystems - Beijing China igb_nic_func_t setup_msix; /* set up msi-x vectors */ 32980a11ad2Schenlu chen - Sun Microsystems - Beijing China /* capabilities */ 33080a11ad2Schenlu chen - Sun Microsystems - Beijing China uint32_t flags; /* capability flags */ 331b8d0a377Schenlu chen - Sun Microsystems - Beijing China uint32_t rxdctl_mask; /* mask for RXDCTL register */ 33280a11ad2Schenlu chen - Sun Microsystems - Beijing China } adapter_info_t; 33380a11ad2Schenlu chen - Sun Microsystems - Beijing China 334c869993eSxy typedef union igb_ether_addr { 335c869993eSxy struct { 336c869993eSxy uint32_t high; 337c869993eSxy uint32_t low; 338c869993eSxy } reg; 339c869993eSxy struct { 340c869993eSxy uint8_t set; 341da14cebeSEric Cheng uint8_t group_index; 342c869993eSxy uint8_t addr[ETHERADDRL]; 343c869993eSxy } mac; 344c869993eSxy } igb_ether_addr_t; 345c869993eSxy 346c869993eSxy typedef enum { 347c869993eSxy USE_NONE, 348c869993eSxy USE_COPY, 349c869993eSxy USE_DMA 350c869993eSxy } tx_type_t; 351c869993eSxy 352d11274aaSPaul Guo typedef struct tx_context { 353c869993eSxy uint32_t hcksum_flags; 354c869993eSxy uint32_t ip_hdr_len; 355c869993eSxy uint32_t mac_hdr_len; 356c869993eSxy uint32_t l4_proto; 357d11274aaSPaul Guo uint32_t mss; 358d11274aaSPaul Guo uint32_t l4_hdr_len; 359d11274aaSPaul Guo boolean_t lso_flag; 360d11274aaSPaul Guo } tx_context_t; 361c869993eSxy 362c869993eSxy /* Hold address/length of each DMA segment */ 363c869993eSxy typedef struct sw_desc { 364c869993eSxy uint64_t address; 365c869993eSxy size_t length; 366c869993eSxy } sw_desc_t; 367c869993eSxy 368c869993eSxy /* Handles and addresses of DMA buffer */ 369c869993eSxy typedef struct dma_buffer { 370c869993eSxy caddr_t address; /* Virtual address */ 371c869993eSxy uint64_t dma_address; /* DMA (Hardware) address */ 372c869993eSxy ddi_acc_handle_t acc_handle; /* Data access handle */ 373c869993eSxy ddi_dma_handle_t dma_handle; /* DMA handle */ 374c869993eSxy size_t size; /* Buffer size */ 375c869993eSxy size_t len; /* Data length in the buffer */ 376c869993eSxy } dma_buffer_t; 377c869993eSxy 378c869993eSxy /* 379c869993eSxy * Tx Control Block 380c869993eSxy */ 381c869993eSxy typedef struct tx_control_block { 382c869993eSxy single_link_t link; 38369b2d733SGuoqing Zhu uint32_t last_index; 384c869993eSxy uint32_t frag_num; 385c869993eSxy uint32_t desc_num; 386c869993eSxy mblk_t *mp; 387c869993eSxy tx_type_t tx_type; 388c869993eSxy ddi_dma_handle_t tx_dma_handle; 389c869993eSxy dma_buffer_t tx_buf; 390c869993eSxy sw_desc_t desc[MAX_COOKIE]; 391c869993eSxy } tx_control_block_t; 392c869993eSxy 393c869993eSxy /* 394c869993eSxy * RX Control Block 395c869993eSxy */ 396c869993eSxy typedef struct rx_control_block { 397c869993eSxy mblk_t *mp; 398ac7f5757Schenlu chen - Sun Microsystems - Beijing China uint32_t ref_cnt; 399c869993eSxy dma_buffer_t rx_buf; 400c869993eSxy frtn_t free_rtn; 401ac7f5757Schenlu chen - Sun Microsystems - Beijing China struct igb_rx_data *rx_data; 402c869993eSxy } rx_control_block_t; 403c869993eSxy 404c869993eSxy /* 405c869993eSxy * Software Data Structure for Tx Ring 406c869993eSxy */ 407c869993eSxy typedef struct igb_tx_ring { 408c869993eSxy uint32_t index; /* Ring index */ 409da14cebeSEric Cheng uint32_t intr_vector; /* Interrupt vector index */ 410c869993eSxy 411c869993eSxy /* 412c869993eSxy * Mutexes 413c869993eSxy */ 414c869993eSxy kmutex_t tx_lock; 415c869993eSxy kmutex_t recycle_lock; 416c869993eSxy kmutex_t tcb_head_lock; 417c869993eSxy kmutex_t tcb_tail_lock; 418c869993eSxy 419c869993eSxy /* 420c869993eSxy * Tx descriptor ring definitions 421c869993eSxy */ 422c869993eSxy dma_buffer_t tbd_area; 423c869993eSxy union e1000_adv_tx_desc *tbd_ring; 424c869993eSxy uint32_t tbd_head; /* Index of next tbd to recycle */ 425c869993eSxy uint32_t tbd_tail; /* Index of next tbd to transmit */ 426c869993eSxy uint32_t tbd_free; /* Number of free tbd */ 427c869993eSxy 428c869993eSxy /* 429c869993eSxy * Tx control block list definitions 430c869993eSxy */ 431c869993eSxy tx_control_block_t *tcb_area; 432c869993eSxy tx_control_block_t **work_list; 433c869993eSxy tx_control_block_t **free_list; 434c869993eSxy uint32_t tcb_head; /* Head index of free list */ 435c869993eSxy uint32_t tcb_tail; /* Tail index of free list */ 436c869993eSxy uint32_t tcb_free; /* Number of free tcb in free list */ 437c869993eSxy 438c869993eSxy uint32_t *tbd_head_wb; /* Head write-back */ 439c869993eSxy uint32_t (*tx_recycle)(struct igb_tx_ring *); 440c869993eSxy 441c869993eSxy /* 442d11274aaSPaul Guo * s/w context structure for TCP/UDP checksum offload and LSO. 443c869993eSxy */ 444d11274aaSPaul Guo tx_context_t tx_context; 445c869993eSxy 446c869993eSxy /* 447c869993eSxy * Tx ring settings and status 448c869993eSxy */ 449c869993eSxy uint32_t ring_size; /* Tx descriptor ring size */ 450c869993eSxy uint32_t free_list_size; /* Tx free list size */ 451c869993eSxy 452c869993eSxy boolean_t reschedule; 453c869993eSxy uint32_t recycle_fail; 454c869993eSxy uint32_t stall_watchdog; 455c869993eSxy 4560dc2366fSVenugopal Iyer /* 4570dc2366fSVenugopal Iyer * Per-ring statistics 4580dc2366fSVenugopal Iyer */ 4590dc2366fSVenugopal Iyer uint64_t tx_pkts; /* Packets Transmitted Count */ 4600dc2366fSVenugopal Iyer uint64_t tx_bytes; /* Bytes Transmitted Count */ 4610dc2366fSVenugopal Iyer 462c869993eSxy #ifdef IGB_DEBUG 463c869993eSxy /* 464c869993eSxy * Debug statistics 465c869993eSxy */ 466c869993eSxy uint32_t stat_overload; 467c869993eSxy uint32_t stat_fail_no_tbd; 468c869993eSxy uint32_t stat_fail_no_tcb; 469c869993eSxy uint32_t stat_fail_dma_bind; 470c869993eSxy uint32_t stat_reschedule; 471da14cebeSEric Cheng uint32_t stat_pkt_cnt; 472c869993eSxy #endif 473c869993eSxy 474c869993eSxy /* 475c869993eSxy * Pointer to the igb struct 476c869993eSxy */ 477c869993eSxy struct igb *igb; 478da14cebeSEric Cheng mac_ring_handle_t ring_handle; /* call back ring handle */ 479c869993eSxy } igb_tx_ring_t; 480c869993eSxy 481c869993eSxy /* 482c869993eSxy * Software Receive Ring 483c869993eSxy */ 484ac7f5757Schenlu chen - Sun Microsystems - Beijing China typedef struct igb_rx_data { 485c869993eSxy kmutex_t recycle_lock; /* Recycle lock, for rcb_tail */ 486c869993eSxy 487c869993eSxy /* 488c869993eSxy * Rx descriptor ring definitions 489c869993eSxy */ 490c869993eSxy dma_buffer_t rbd_area; /* DMA buffer of rx desc ring */ 491c869993eSxy union e1000_adv_rx_desc *rbd_ring; /* Rx desc ring */ 492c869993eSxy uint32_t rbd_next; /* Index of next rx desc */ 493c869993eSxy 494c869993eSxy /* 495c869993eSxy * Rx control block list definitions 496c869993eSxy */ 497c869993eSxy rx_control_block_t *rcb_area; 498c869993eSxy rx_control_block_t **work_list; /* Work list of rcbs */ 499c869993eSxy rx_control_block_t **free_list; /* Free list of rcbs */ 500c869993eSxy uint32_t rcb_head; /* Index of next free rcb */ 501c869993eSxy uint32_t rcb_tail; /* Index to put recycled rcb */ 502c869993eSxy uint32_t rcb_free; /* Number of free rcbs */ 503c869993eSxy 504c869993eSxy /* 505ac7f5757Schenlu chen - Sun Microsystems - Beijing China * Rx sw ring settings and status 506c869993eSxy */ 507c869993eSxy uint32_t ring_size; /* Rx descriptor ring size */ 508c869993eSxy uint32_t free_list_size; /* Rx free list size */ 509ac7f5757Schenlu chen - Sun Microsystems - Beijing China 510ac7f5757Schenlu chen - Sun Microsystems - Beijing China uint32_t rcb_pending; 511ac7f5757Schenlu chen - Sun Microsystems - Beijing China uint32_t flag; 512ac7f5757Schenlu chen - Sun Microsystems - Beijing China 513ac7f5757Schenlu chen - Sun Microsystems - Beijing China struct igb_rx_ring *rx_ring; /* Pointer to rx ring */ 514ac7f5757Schenlu chen - Sun Microsystems - Beijing China } igb_rx_data_t; 515ac7f5757Schenlu chen - Sun Microsystems - Beijing China 516ac7f5757Schenlu chen - Sun Microsystems - Beijing China /* 517ac7f5757Schenlu chen - Sun Microsystems - Beijing China * Software Data Structure for Rx Ring 518ac7f5757Schenlu chen - Sun Microsystems - Beijing China */ 519ac7f5757Schenlu chen - Sun Microsystems - Beijing China typedef struct igb_rx_ring { 520ac7f5757Schenlu chen - Sun Microsystems - Beijing China uint32_t index; /* Ring index */ 521ac7f5757Schenlu chen - Sun Microsystems - Beijing China uint32_t intr_vector; /* Interrupt vector index */ 522ac7f5757Schenlu chen - Sun Microsystems - Beijing China 523ac7f5757Schenlu chen - Sun Microsystems - Beijing China igb_rx_data_t *rx_data; /* Rx software ring */ 524ac7f5757Schenlu chen - Sun Microsystems - Beijing China 525ac7f5757Schenlu chen - Sun Microsystems - Beijing China kmutex_t rx_lock; /* Rx access lock */ 526c869993eSxy 5270dc2366fSVenugopal Iyer /* 5280dc2366fSVenugopal Iyer * Per-ring statistics 5290dc2366fSVenugopal Iyer */ 5300dc2366fSVenugopal Iyer uint64_t rx_pkts; /* Packets Received Count */ 5310dc2366fSVenugopal Iyer uint64_t rx_bytes; /* Bytes Received Count */ 5320dc2366fSVenugopal Iyer 533c869993eSxy #ifdef IGB_DEBUG 534c869993eSxy /* 535c869993eSxy * Debug statistics 536c869993eSxy */ 537c869993eSxy uint32_t stat_frame_error; 538c869993eSxy uint32_t stat_cksum_error; 539c869993eSxy uint32_t stat_exceed_pkt; 540da14cebeSEric Cheng uint32_t stat_pkt_cnt; 541c869993eSxy #endif 542c869993eSxy 543c869993eSxy struct igb *igb; /* Pointer to igb struct */ 544b8d0a377Schenlu chen - Sun Microsystems - Beijing China mac_ring_handle_t ring_handle; /* call back ring handle */ 545da14cebeSEric Cheng uint32_t group_index; /* group index */ 546da14cebeSEric Cheng uint64_t ring_gen_num; 547c869993eSxy } igb_rx_ring_t; 548c869993eSxy 549da14cebeSEric Cheng /* 550da14cebeSEric Cheng * Software Receive Ring Group 551da14cebeSEric Cheng */ 552da14cebeSEric Cheng typedef struct igb_rx_group { 553da14cebeSEric Cheng uint32_t index; /* Group index */ 554da14cebeSEric Cheng mac_group_handle_t group_handle; /* call back group handle */ 555da14cebeSEric Cheng struct igb *igb; /* Pointer to igb struct */ 556da14cebeSEric Cheng } igb_rx_group_t; 557da14cebeSEric Cheng 558c869993eSxy typedef struct igb { 559c869993eSxy int instance; 560c869993eSxy mac_handle_t mac_hdl; 561c869993eSxy dev_info_t *dip; 562c869993eSxy struct e1000_hw hw; 563c869993eSxy struct igb_osdep osdep; 564c869993eSxy 56580a11ad2Schenlu chen - Sun Microsystems - Beijing China adapter_info_t *capab; /* adapter capabilities */ 56680a11ad2Schenlu chen - Sun Microsystems - Beijing China 567c869993eSxy uint32_t igb_state; 568c869993eSxy link_state_t link_state; 569c869993eSxy uint32_t link_speed; 570c869993eSxy uint32_t link_duplex; 571cf8dcc9bSzhefeng xu - Sun Microsystems - Beijing China boolean_t link_complete; 572cf8dcc9bSzhefeng xu - Sun Microsystems - Beijing China timeout_id_t link_tid; 573c869993eSxy 574c869993eSxy uint32_t reset_count; 575c869993eSxy uint32_t attach_progress; 576c869993eSxy uint32_t loopback_mode; 577ac7f5757Schenlu chen - Sun Microsystems - Beijing China uint32_t default_mtu; 578c869993eSxy uint32_t max_frame_size; 579b8d0a377Schenlu chen - Sun Microsystems - Beijing China uint32_t dout_sync; 580c869993eSxy 581ac7f5757Schenlu chen - Sun Microsystems - Beijing China uint32_t rcb_pending; 582ac7f5757Schenlu chen - Sun Microsystems - Beijing China 583da14cebeSEric Cheng uint32_t mr_enable; /* Enable multiple rings */ 584da14cebeSEric Cheng uint32_t vmdq_mode; /* Mode of VMDq */ 585da14cebeSEric Cheng 586c869993eSxy /* 587da14cebeSEric Cheng * Receive Rings and Groups 588c869993eSxy */ 589c869993eSxy igb_rx_ring_t *rx_rings; /* Array of rx rings */ 590c869993eSxy uint32_t num_rx_rings; /* Number of rx rings in use */ 591c869993eSxy uint32_t rx_ring_size; /* Rx descriptor ring size */ 592c869993eSxy uint32_t rx_buf_size; /* Rx buffer size */ 593da14cebeSEric Cheng igb_rx_group_t *rx_groups; /* Array of rx groups */ 594da14cebeSEric Cheng uint32_t num_rx_groups; /* Number of rx groups in use */ 595c869993eSxy 596c869993eSxy /* 597c869993eSxy * Transmit Rings 598c869993eSxy */ 599c869993eSxy igb_tx_ring_t *tx_rings; /* Array of tx rings */ 600c869993eSxy uint32_t num_tx_rings; /* Number of tx rings in use */ 601c869993eSxy uint32_t tx_ring_size; /* Tx descriptor ring size */ 602c869993eSxy uint32_t tx_buf_size; /* Tx buffer size */ 603c869993eSxy 604ac7f5757Schenlu chen - Sun Microsystems - Beijing China boolean_t tx_ring_init; 605c869993eSxy boolean_t tx_head_wb_enable; /* Tx head wrtie-back */ 606c869993eSxy boolean_t tx_hcksum_enable; /* Tx h/w cksum offload */ 607c869993eSxy boolean_t lso_enable; /* Large Segment Offload */ 608c869993eSxy uint32_t tx_copy_thresh; /* Tx copy threshold */ 609c869993eSxy uint32_t tx_recycle_thresh; /* Tx recycle threshold */ 610c869993eSxy uint32_t tx_overload_thresh; /* Tx overload threshold */ 611c869993eSxy uint32_t tx_resched_thresh; /* Tx reschedule threshold */ 612c869993eSxy boolean_t rx_hcksum_enable; /* Rx h/w cksum offload */ 613c869993eSxy uint32_t rx_copy_thresh; /* Rx copy threshold */ 614c869993eSxy uint32_t rx_limit_per_intr; /* Rx pkts per interrupt */ 615b8d0a377Schenlu chen - Sun Microsystems - Beijing China 616c869993eSxy uint32_t intr_throttling[MAX_NUM_EITR]; 617c869993eSxy uint32_t intr_force; 618c869993eSxy 619c869993eSxy int intr_type; 620c869993eSxy int intr_cnt; 621c869993eSxy int intr_cap; 622c869993eSxy size_t intr_size; 623c869993eSxy uint_t intr_pri; 624c869993eSxy ddi_intr_handle_t *htable; 625c869993eSxy uint32_t eims_mask; 626da14cebeSEric Cheng uint32_t ims_mask; 627c869993eSxy 628c869993eSxy kmutex_t gen_lock; /* General lock for device access */ 629c869993eSxy kmutex_t watchdog_lock; 630cf8dcc9bSzhefeng xu - Sun Microsystems - Beijing China kmutex_t link_lock; 631ac7f5757Schenlu chen - Sun Microsystems - Beijing China kmutex_t rx_pending_lock; 632c869993eSxy 633c869993eSxy boolean_t watchdog_enable; 634c869993eSxy boolean_t watchdog_start; 635c869993eSxy timeout_id_t watchdog_tid; 636c869993eSxy 637c869993eSxy boolean_t unicst_init; 638c869993eSxy uint32_t unicst_avail; 639c869993eSxy uint32_t unicst_total; 640c869993eSxy igb_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 641c869993eSxy uint32_t mcast_count; 6426ca163a1Svitezslav batrla - Sun Microsystems - Prague Czech Republic uint32_t mcast_alloc_count; 6436ca163a1Svitezslav batrla - Sun Microsystems - Prague Czech Republic uint32_t mcast_max_num; 6446ca163a1Svitezslav batrla - Sun Microsystems - Prague Czech Republic struct ether_addr *mcast_table; 645c869993eSxy 646c869993eSxy /* 647c869993eSxy * Kstat definitions 648c869993eSxy */ 649c869993eSxy kstat_t *igb_ks; 650c869993eSxy 651ac7f5757Schenlu chen - Sun Microsystems - Beijing China uint32_t param_en_1000fdx_cap:1, 652ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_en_1000hdx_cap:1, 653ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_en_100t4_cap:1, 654ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_en_100fdx_cap:1, 655ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_en_100hdx_cap:1, 656ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_en_10fdx_cap:1, 657ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_en_10hdx_cap:1, 658ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_1000fdx_cap:1, 659ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_1000hdx_cap:1, 660ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_100t4_cap:1, 661ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_100fdx_cap:1, 662ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_100hdx_cap:1, 663ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_10fdx_cap:1, 664ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_10hdx_cap:1, 665ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_autoneg_cap:1, 666ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_pause_cap:1, 667ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_asym_pause_cap:1, 668ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_rem_fault:1, 669ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_adv_1000fdx_cap:1, 670ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_adv_1000hdx_cap:1, 671ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_adv_100t4_cap:1, 672ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_adv_100fdx_cap:1, 673ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_adv_100hdx_cap:1, 674ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_adv_10fdx_cap:1, 675ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_adv_10hdx_cap:1, 676ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_adv_autoneg_cap:1, 677ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_adv_pause_cap:1, 678ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_adv_asym_pause_cap:1, 679ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_adv_rem_fault:1, 680ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_lp_1000fdx_cap:1, 681ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_lp_1000hdx_cap:1, 682ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_lp_100t4_cap:1; 683ac7f5757Schenlu chen - Sun Microsystems - Beijing China 684ac7f5757Schenlu chen - Sun Microsystems - Beijing China uint32_t param_lp_100fdx_cap:1, 685ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_lp_100hdx_cap:1, 686ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_lp_10fdx_cap:1, 687ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_lp_10hdx_cap:1, 688ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_lp_autoneg_cap:1, 689ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_lp_pause_cap:1, 690ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_lp_asym_pause_cap:1, 691ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_lp_rem_fault:1, 692ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_pad_to_32:24; 693c869993eSxy 6948bb4b220Sgl /* 6958bb4b220Sgl * FMA capabilities 6968bb4b220Sgl */ 6978bb4b220Sgl int fm_capabilities; 6988bb4b220Sgl 699d11274aaSPaul Guo ulong_t page_size; 700c869993eSxy } igb_t; 701c869993eSxy 702c869993eSxy typedef struct igb_stat { 703c869993eSxy 704c869993eSxy kstat_named_t link_speed; /* Link Speed */ 705c869993eSxy kstat_named_t reset_count; /* Reset Count */ 706b8d0a377Schenlu chen - Sun Microsystems - Beijing China kstat_named_t dout_sync; /* DMA out of sync */ 707b8d0a377Schenlu chen - Sun Microsystems - Beijing China #ifdef IGB_DEBUG 708c869993eSxy kstat_named_t rx_frame_error; /* Rx Error in Packet */ 709c869993eSxy kstat_named_t rx_cksum_error; /* Rx Checksum Error */ 710c869993eSxy kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */ 711c869993eSxy 712c869993eSxy kstat_named_t tx_overload; /* Tx Desc Ring Overload */ 713c869993eSxy kstat_named_t tx_fail_no_tcb; /* Tx Fail Freelist Empty */ 714c869993eSxy kstat_named_t tx_fail_no_tbd; /* Tx Fail Desc Ring Empty */ 715c869993eSxy kstat_named_t tx_fail_dma_bind; /* Tx Fail DMA bind */ 716c869993eSxy kstat_named_t tx_reschedule; /* Tx Reschedule */ 717c869993eSxy 718c869993eSxy kstat_named_t gprc; /* Good Packets Received Count */ 719c869993eSxy kstat_named_t gptc; /* Good Packets Xmitted Count */ 720c869993eSxy kstat_named_t gor; /* Good Octets Received Count */ 721c869993eSxy kstat_named_t got; /* Good Octets Xmitd Count */ 722c869993eSxy kstat_named_t prc64; /* Packets Received - 64b */ 723c869993eSxy kstat_named_t prc127; /* Packets Received - 65-127b */ 724c869993eSxy kstat_named_t prc255; /* Packets Received - 127-255b */ 725c869993eSxy kstat_named_t prc511; /* Packets Received - 256-511b */ 726c869993eSxy kstat_named_t prc1023; /* Packets Received - 511-1023b */ 727c869993eSxy kstat_named_t prc1522; /* Packets Received - 1024-1522b */ 728c869993eSxy kstat_named_t ptc64; /* Packets Xmitted (64b) */ 729c869993eSxy kstat_named_t ptc127; /* Packets Xmitted (64-127b) */ 730c869993eSxy kstat_named_t ptc255; /* Packets Xmitted (128-255b) */ 731c869993eSxy kstat_named_t ptc511; /* Packets Xmitted (255-511b) */ 732c869993eSxy kstat_named_t ptc1023; /* Packets Xmitted (512-1023b) */ 733c869993eSxy kstat_named_t ptc1522; /* Packets Xmitted (1024-1522b */ 734c869993eSxy #endif 735c869993eSxy kstat_named_t crcerrs; /* CRC Error Count */ 736c869993eSxy kstat_named_t symerrs; /* Symbol Error Count */ 737c869993eSxy kstat_named_t mpc; /* Missed Packet Count */ 738c869993eSxy kstat_named_t scc; /* Single Collision Count */ 739c869993eSxy kstat_named_t ecol; /* Excessive Collision Count */ 740c869993eSxy kstat_named_t mcc; /* Multiple Collision Count */ 741c869993eSxy kstat_named_t latecol; /* Late Collision Count */ 742c869993eSxy kstat_named_t colc; /* Collision Count */ 743c869993eSxy kstat_named_t dc; /* Defer Count */ 744c869993eSxy kstat_named_t sec; /* Sequence Error Count */ 745c869993eSxy kstat_named_t rlec; /* Receive Length Error Count */ 746c869993eSxy kstat_named_t xonrxc; /* XON Received Count */ 747c869993eSxy kstat_named_t xontxc; /* XON Xmitted Count */ 748c869993eSxy kstat_named_t xoffrxc; /* XOFF Received Count */ 749c869993eSxy kstat_named_t xofftxc; /* Xoff Xmitted Count */ 750c869993eSxy kstat_named_t fcruc; /* Unknown Flow Conrol Packet Rcvd Count */ 751c869993eSxy kstat_named_t bprc; /* Broadcasts Pkts Received Count */ 752c869993eSxy kstat_named_t mprc; /* Multicast Pkts Received Count */ 753c869993eSxy kstat_named_t rnbc; /* Receive No Buffers Count */ 754c869993eSxy kstat_named_t ruc; /* Receive Undersize Count */ 755c869993eSxy kstat_named_t rfc; /* Receive Frag Count */ 756c869993eSxy kstat_named_t roc; /* Receive Oversize Count */ 757c869993eSxy kstat_named_t rjc; /* Receive Jabber Count */ 758c869993eSxy kstat_named_t tor; /* Total Octets Recvd Count */ 759c869993eSxy kstat_named_t tot; /* Total Octets Xmted Count */ 760c869993eSxy kstat_named_t tpr; /* Total Packets Received */ 761c869993eSxy kstat_named_t tpt; /* Total Packets Xmitted */ 762c869993eSxy kstat_named_t mptc; /* Multicast Packets Xmited Count */ 763c869993eSxy kstat_named_t bptc; /* Broadcast Packets Xmited Count */ 764c869993eSxy kstat_named_t algnerrc; /* Alignment Error count */ 765c869993eSxy kstat_named_t rxerrc; /* Rx Error Count */ 766c869993eSxy kstat_named_t tncrs; /* Transmit with no CRS */ 767c869993eSxy kstat_named_t cexterr; /* Carrier Extension Error count */ 768c869993eSxy kstat_named_t tsctc; /* TCP seg contexts xmit count */ 769c869993eSxy kstat_named_t tsctfc; /* TCP seg contexts xmit fail count */ 770c869993eSxy } igb_stat_t; 771c869993eSxy 772c869993eSxy /* 773c869993eSxy * Function prototypes in e1000_osdep.c 774c869993eSxy */ 7757d46e7adSzhefeng xu - Sun Microsystems - Beijing China void e1000_write_pci_cfg(struct e1000_hw *, uint32_t, uint16_t *); 7767d46e7adSzhefeng xu - Sun Microsystems - Beijing China void e1000_read_pci_cfg(struct e1000_hw *, uint32_t, uint16_t *); 7777d46e7adSzhefeng xu - Sun Microsystems - Beijing China int32_t e1000_read_pcie_cap_reg(struct e1000_hw *, uint32_t, uint16_t *); 7787d46e7adSzhefeng xu - Sun Microsystems - Beijing China int32_t e1000_write_pcie_cap_reg(struct e1000_hw *, uint32_t, uint16_t *); 7793f7e60a6Szhefeng xu - Sun Microsystems - Beijing China void e1000_rar_clear(struct e1000_hw *, uint32_t); 7803f7e60a6Szhefeng xu - Sun Microsystems - Beijing China void e1000_rar_set_vmdq(struct e1000_hw *, const uint8_t *, uint32_t, 78180a11ad2Schenlu chen - Sun Microsystems - Beijing China uint32_t, uint8_t); 782c869993eSxy 783c869993eSxy /* 784c869993eSxy * Function prototypes in igb_buf.c 785c869993eSxy */ 786c869993eSxy int igb_alloc_dma(igb_t *); 787c869993eSxy void igb_free_dma(igb_t *); 788ac7f5757Schenlu chen - Sun Microsystems - Beijing China void igb_free_dma_buffer(dma_buffer_t *); 789ac7f5757Schenlu chen - Sun Microsystems - Beijing China int igb_alloc_rx_ring_data(igb_rx_ring_t *rx_ring); 790ac7f5757Schenlu chen - Sun Microsystems - Beijing China void igb_free_rx_ring_data(igb_rx_data_t *rx_data); 791c869993eSxy 792c869993eSxy /* 793c869993eSxy * Function prototypes in igb_main.c 794c869993eSxy */ 795ac7f5757Schenlu chen - Sun Microsystems - Beijing China int igb_start(igb_t *, boolean_t); 796ac7f5757Schenlu chen - Sun Microsystems - Beijing China void igb_stop(igb_t *, boolean_t); 797c869993eSxy int igb_setup_link(igb_t *, boolean_t); 798da14cebeSEric Cheng int igb_unicst_find(igb_t *, const uint8_t *); 799da14cebeSEric Cheng int igb_unicst_set(igb_t *, const uint8_t *, int); 800c869993eSxy int igb_multicst_add(igb_t *, const uint8_t *); 801c869993eSxy int igb_multicst_remove(igb_t *, const uint8_t *); 802c869993eSxy enum ioc_reply igb_loopback_ioctl(igb_t *, struct iocblk *, mblk_t *); 803c869993eSxy void igb_enable_watchdog_timer(igb_t *); 804c869993eSxy void igb_disable_watchdog_timer(igb_t *); 805c869993eSxy int igb_atomic_reserve(uint32_t *, uint32_t); 8068bb4b220Sgl int igb_check_acc_handle(ddi_acc_handle_t); 8078bb4b220Sgl int igb_check_dma_handle(ddi_dma_handle_t); 8088bb4b220Sgl void igb_fm_ereport(igb_t *, char *); 809837c1ac4SStephen Hanson void igb_set_fma_flags(int); 810c869993eSxy 811c869993eSxy /* 812c869993eSxy * Function prototypes in igb_gld.c 813c869993eSxy */ 814c869993eSxy int igb_m_start(void *); 815c869993eSxy void igb_m_stop(void *); 816c869993eSxy int igb_m_promisc(void *, boolean_t); 817c869993eSxy int igb_m_multicst(void *, boolean_t, const uint8_t *); 818c869993eSxy int igb_m_unicst(void *, const uint8_t *); 819c869993eSxy int igb_m_stat(void *, uint_t, uint64_t *); 820c869993eSxy void igb_m_resources(void *); 821c869993eSxy void igb_m_ioctl(void *, queue_t *, mblk_t *); 822c869993eSxy boolean_t igb_m_getcapab(void *, mac_capab_t, void *); 823da14cebeSEric Cheng void igb_fill_ring(void *, mac_ring_type_t, const int, const int, 824da14cebeSEric Cheng mac_ring_info_t *, mac_ring_handle_t); 825ac7f5757Schenlu chen - Sun Microsystems - Beijing China int igb_m_setprop(void *, const char *, mac_prop_id_t, uint_t, const void *); 8260dc2366fSVenugopal Iyer int igb_m_getprop(void *, const char *, mac_prop_id_t, uint_t, void *); 8270dc2366fSVenugopal Iyer void igb_m_propinfo(void *, const char *, mac_prop_id_t, 8280dc2366fSVenugopal Iyer mac_prop_info_handle_t); 829ac7f5757Schenlu chen - Sun Microsystems - Beijing China int igb_set_priv_prop(igb_t *, const char *, uint_t, const void *); 8300dc2366fSVenugopal Iyer int igb_get_priv_prop(igb_t *, const char *, uint_t, void *); 8310dc2366fSVenugopal Iyer void igb_priv_prop_info(igb_t *, const char *, mac_prop_info_handle_t); 832ac7f5757Schenlu chen - Sun Microsystems - Beijing China boolean_t igb_param_locked(mac_prop_id_t); 833da14cebeSEric Cheng void igb_fill_group(void *arg, mac_ring_type_t, const int, 834da14cebeSEric Cheng mac_group_info_t *, mac_group_handle_t); 835da14cebeSEric Cheng int igb_rx_ring_intr_enable(mac_intr_handle_t); 836da14cebeSEric Cheng int igb_rx_ring_intr_disable(mac_intr_handle_t); 837ac7f5757Schenlu chen - Sun Microsystems - Beijing China int igb_get_def_val(igb_t *, mac_prop_id_t, uint_t, void *); 838c869993eSxy 839c869993eSxy /* 840c869993eSxy * Function prototypes in igb_rx.c 841c869993eSxy */ 842da14cebeSEric Cheng mblk_t *igb_rx(igb_rx_ring_t *, int); 843c869993eSxy void igb_rx_recycle(caddr_t arg); 844c869993eSxy 845c869993eSxy /* 846c869993eSxy * Function prototypes in igb_tx.c 847c869993eSxy */ 848c869993eSxy void igb_free_tcb(tx_control_block_t *); 849c869993eSxy void igb_put_free_list(igb_tx_ring_t *, link_list_t *); 850c869993eSxy uint32_t igb_tx_recycle_legacy(igb_tx_ring_t *); 851c869993eSxy uint32_t igb_tx_recycle_head_wb(igb_tx_ring_t *); 852c869993eSxy 853c869993eSxy /* 854c869993eSxy * Function prototypes in igb_log.c 855c869993eSxy */ 856c869993eSxy void igb_notice(void *, const char *, ...); 857c869993eSxy void igb_log(void *, const char *, ...); 858c869993eSxy void igb_error(void *, const char *, ...); 859c869993eSxy 860c869993eSxy /* 861c869993eSxy * Function prototypes in igb_stat.c 862c869993eSxy */ 863c869993eSxy int igb_init_stats(igb_t *); 864c869993eSxy 865da14cebeSEric Cheng mblk_t *igb_rx_ring_poll(void *, int); 866da14cebeSEric Cheng mblk_t *igb_tx_ring_send(void *, mblk_t *); 8670dc2366fSVenugopal Iyer int igb_rx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 8680dc2366fSVenugopal Iyer int igb_tx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 869c869993eSxy 870c869993eSxy #ifdef __cplusplus 871c869993eSxy } 872c869993eSxy #endif 873c869993eSxy 874c869993eSxy #endif /* _IGB_SW_H */ 875