1c869993eSxy /* 2c869993eSxy * CDDL HEADER START 3c869993eSxy * 4c869993eSxy * The contents of this file are subject to the terms of the 5c869993eSxy * Common Development and Distribution License (the "License"). 6c869993eSxy * You may not use this file except in compliance with the License. 7c869993eSxy * 80dc2366fSVenugopal Iyer * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 90dc2366fSVenugopal Iyer * or http://www.opensolaris.org/os/licensing. 10c869993eSxy * See the License for the specific language governing permissions 11c869993eSxy * and limitations under the License. 12c869993eSxy * 130dc2366fSVenugopal Iyer * When distributing Covered Code, include this CDDL HEADER in each 140dc2366fSVenugopal Iyer * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15c869993eSxy * If applicable, add the following below this CDDL HEADER, with the 16c869993eSxy * fields enclosed by brackets "[]" replaced with your own identifying 17c869993eSxy * information: Portions Copyright [yyyy] [name of copyright owner] 18c869993eSxy * 19c869993eSxy * CDDL HEADER END 20c869993eSxy */ 21c869993eSxy 22da14cebeSEric Cheng /* 2308a0f9b0Schenlu chen - Sun Microsystems - Beijing China * Copyright(c) 2007-2010 Intel Corporation. All rights reserved. 2408a0f9b0Schenlu chen - Sun Microsystems - Beijing China */ 2508a0f9b0Schenlu chen - Sun Microsystems - Beijing China 2608a0f9b0Schenlu chen - Sun Microsystems - Beijing China /* 2708a0f9b0Schenlu chen - Sun Microsystems - Beijing China * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. 28*13485e69SGarrett D'Amore * Copyright 2014 Pluribus Networks Inc. 29c869993eSxy */ 30c869993eSxy 31c869993eSxy #ifndef _IGB_SW_H 32c869993eSxy #define _IGB_SW_H 33c869993eSxy 34c869993eSxy #ifdef __cplusplus 35c869993eSxy extern "C" { 36c869993eSxy #endif 37c869993eSxy 38c869993eSxy #include <sys/types.h> 39c869993eSxy #include <sys/conf.h> 40c869993eSxy #include <sys/debug.h> 41c869993eSxy #include <sys/stropts.h> 42c869993eSxy #include <sys/stream.h> 43c869993eSxy #include <sys/strsun.h> 44c869993eSxy #include <sys/strlog.h> 45c869993eSxy #include <sys/kmem.h> 46c869993eSxy #include <sys/stat.h> 47c869993eSxy #include <sys/kstat.h> 48c869993eSxy #include <sys/modctl.h> 49c869993eSxy #include <sys/errno.h> 50c869993eSxy #include <sys/dlpi.h> 51da14cebeSEric Cheng #include <sys/mac_provider.h> 52c869993eSxy #include <sys/mac_ether.h> 53c869993eSxy #include <sys/vlan.h> 54c869993eSxy #include <sys/ddi.h> 55c869993eSxy #include <sys/sunddi.h> 56c869993eSxy #include <sys/pci.h> 57c869993eSxy #include <sys/pcie.h> 58c869993eSxy #include <sys/sdt.h> 59c869993eSxy #include <sys/ethernet.h> 60c869993eSxy #include <sys/pattr.h> 61c869993eSxy #include <sys/strsubr.h> 62c869993eSxy #include <sys/netlb.h> 63c869993eSxy #include <sys/random.h> 64c869993eSxy #include <inet/common.h> 65d11274aaSPaul Guo #include <inet/tcp.h> 66c869993eSxy #include <inet/ip.h> 67c869993eSxy #include <inet/mi.h> 68c869993eSxy #include <inet/nd.h> 698bb4b220Sgl #include <sys/ddifm.h> 708bb4b220Sgl #include <sys/fm/protocol.h> 718bb4b220Sgl #include <sys/fm/util.h> 728bb4b220Sgl #include <sys/fm/io/ddi.h> 7375eba5b6SRobert Mustacchi #include "e1000_api.h" 7475eba5b6SRobert Mustacchi #include "e1000_82575.h" 75c869993eSxy 76c869993eSxy 77c869993eSxy #define MODULE_NAME "igb" /* module name */ 78c869993eSxy 79c869993eSxy #define IGB_SUCCESS DDI_SUCCESS 80c869993eSxy #define IGB_FAILURE DDI_FAILURE 81c869993eSxy 82c869993eSxy #define IGB_UNKNOWN 0x00 83c869993eSxy #define IGB_INITIALIZED 0x01 84c869993eSxy #define IGB_STARTED 0x02 85c869993eSxy #define IGB_SUSPENDED 0x04 863f7e60a6Szhefeng xu - Sun Microsystems - Beijing China #define IGB_STALL 0x08 87cf8dcc9bSzhefeng xu - Sun Microsystems - Beijing China #define IGB_ERROR 0x80 88c869993eSxy 89ac7f5757Schenlu chen - Sun Microsystems - Beijing China #define IGB_RX_STOPPED 0x1 90ac7f5757Schenlu chen - Sun Microsystems - Beijing China 91c869993eSxy #define IGB_INTR_NONE 0 92c869993eSxy #define IGB_INTR_MSIX 1 93c869993eSxy #define IGB_INTR_MSI 2 94c869993eSxy #define IGB_INTR_LEGACY 3 95c869993eSxy 9680a11ad2Schenlu chen - Sun Microsystems - Beijing China #define IGB_ADAPTER_REGSET 1 /* mapping adapter registers */ 9780a11ad2Schenlu chen - Sun Microsystems - Beijing China #define IGB_ADAPTER_MSIXTAB 4 /* mapping msi-x table */ 9880a11ad2Schenlu chen - Sun Microsystems - Beijing China 99da14cebeSEric Cheng #define IGB_NO_POLL -1 100da14cebeSEric Cheng #define IGB_NO_FREE_SLOT -1 101da14cebeSEric Cheng 102c869993eSxy #define MAX_NUM_UNICAST_ADDRESSES E1000_RAR_ENTRIES 1036ca163a1Svitezslav batrla - Sun Microsystems - Prague Czech Republic #define MCAST_ALLOC_COUNT 256 104d11274aaSPaul Guo #define MAX_COOKIE 18 105c869993eSxy #define MIN_NUM_TX_DESC 2 106c869993eSxy 10780a11ad2Schenlu chen - Sun Microsystems - Beijing China /* 10880a11ad2Schenlu chen - Sun Microsystems - Beijing China * Number of settings for interrupt throttle rate (ITR). There is one of 10980a11ad2Schenlu chen - Sun Microsystems - Beijing China * these per msi-x vector and it needs to be the maximum of all silicon 11080a11ad2Schenlu chen - Sun Microsystems - Beijing China * types supported by this driver. 11180a11ad2Schenlu chen - Sun Microsystems - Beijing China */ 11280a11ad2Schenlu chen - Sun Microsystems - Beijing China #define MAX_NUM_EITR 25 11380a11ad2Schenlu chen - Sun Microsystems - Beijing China 114c869993eSxy /* 115c869993eSxy * Maximum values for user configurable parameters 116c869993eSxy */ 117c869993eSxy #define MAX_TX_RING_SIZE 4096 118c869993eSxy #define MAX_RX_RING_SIZE 4096 119da14cebeSEric Cheng #define MAX_RX_GROUP_NUM 4 120c869993eSxy 121c869993eSxy #define MAX_MTU 9000 122c869993eSxy #define MAX_RX_LIMIT_PER_INTR 4096 123c869993eSxy 124c869993eSxy #define MAX_RX_COPY_THRESHOLD 9216 125c869993eSxy #define MAX_TX_COPY_THRESHOLD 9216 126c869993eSxy #define MAX_TX_RECYCLE_THRESHOLD DEFAULT_TX_RING_SIZE 127c869993eSxy #define MAX_TX_OVERLOAD_THRESHOLD DEFAULT_TX_RING_SIZE 128c869993eSxy #define MAX_TX_RESCHED_THRESHOLD DEFAULT_TX_RING_SIZE 1296ca163a1Svitezslav batrla - Sun Microsystems - Prague Czech Republic #define MAX_MCAST_NUM 8192 130c869993eSxy 131c869993eSxy /* 132c869993eSxy * Minimum values for user configurable parameters 133c869993eSxy */ 134c869993eSxy #define MIN_TX_RING_SIZE 64 135c869993eSxy #define MIN_RX_RING_SIZE 64 136da14cebeSEric Cheng #define MIN_RX_GROUP_NUM 1 137c869993eSxy 138c869993eSxy #define MIN_MTU ETHERMIN 139c869993eSxy #define MIN_RX_LIMIT_PER_INTR 16 1403f7e60a6Szhefeng xu - Sun Microsystems - Beijing China 141c869993eSxy #define MIN_RX_COPY_THRESHOLD 0 142c869993eSxy #define MIN_TX_COPY_THRESHOLD 0 143c869993eSxy #define MIN_TX_RECYCLE_THRESHOLD MIN_NUM_TX_DESC 144c869993eSxy #define MIN_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 145c869993eSxy #define MIN_TX_RESCHED_THRESHOLD MIN_NUM_TX_DESC 1466ca163a1Svitezslav batrla - Sun Microsystems - Prague Czech Republic #define MIN_MCAST_NUM 8 147c869993eSxy 148c869993eSxy /* 149c869993eSxy * Default values for user configurable parameters 150c869993eSxy */ 151c869993eSxy #define DEFAULT_TX_RING_SIZE 512 152c869993eSxy #define DEFAULT_RX_RING_SIZE 512 153da14cebeSEric Cheng #define DEFAULT_RX_GROUP_NUM 1 154c869993eSxy 155c869993eSxy #define DEFAULT_MTU ETHERMTU 156c869993eSxy #define DEFAULT_RX_LIMIT_PER_INTR 256 1573f7e60a6Szhefeng xu - Sun Microsystems - Beijing China 158c869993eSxy #define DEFAULT_RX_COPY_THRESHOLD 128 159c869993eSxy #define DEFAULT_TX_COPY_THRESHOLD 512 160d11274aaSPaul Guo #define DEFAULT_TX_RECYCLE_THRESHOLD (MAX_COOKIE + 1) 161c869993eSxy #define DEFAULT_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 162c869993eSxy #define DEFAULT_TX_RESCHED_THRESHOLD 128 16369b2d733SGuoqing Zhu #define DEFAULT_TX_RESCHED_THRESHOLD_LOW 32 1646ca163a1Svitezslav batrla - Sun Microsystems - Prague Czech Republic #define DEFAULT_MCAST_NUM 4096 165c869993eSxy 166d11274aaSPaul Guo #define IGB_LSO_MAXLEN 65535 167d11274aaSPaul Guo 168c869993eSxy #define TX_DRAIN_TIME 200 169c869993eSxy #define RX_DRAIN_TIME 200 170c869993eSxy 171c869993eSxy #define STALL_WATCHDOG_TIMEOUT 8 /* 8 seconds */ 172c869993eSxy 173c869993eSxy /* 174c869993eSxy * Defined for IP header alignment. 175c869993eSxy */ 176c869993eSxy #define IPHDR_ALIGN_ROOM 2 177c869993eSxy 178c869993eSxy /* 179c869993eSxy * Bit flags for attach_progress 180c869993eSxy */ 181c869993eSxy #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 182c869993eSxy #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 183c869993eSxy #define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */ 184c869993eSxy #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */ 185c869993eSxy #define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */ 186c869993eSxy #define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */ 187c869993eSxy #define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */ 188b8d0a377Schenlu chen - Sun Microsystems - Beijing China #define ATTACH_PROGRESS_INIT_ADAPTER 0x0080 /* Adapter initialized */ 189c869993eSxy #define ATTACH_PROGRESS_STATS 0x0200 /* Kstats created */ 190c869993eSxy #define ATTACH_PROGRESS_MAC 0x0800 /* MAC registered */ 191c869993eSxy #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */ 1928bb4b220Sgl #define ATTACH_PROGRESS_FMINIT 0x2000 /* FMA initialized */ 193c869993eSxy 194c869993eSxy #define PROP_ADV_AUTONEG_CAP "adv_autoneg_cap" 195c869993eSxy #define PROP_ADV_1000FDX_CAP "adv_1000fdx_cap" 196c869993eSxy #define PROP_ADV_1000HDX_CAP "adv_1000hdx_cap" 197c869993eSxy #define PROP_ADV_100FDX_CAP "adv_100fdx_cap" 198c869993eSxy #define PROP_ADV_100HDX_CAP "adv_100hdx_cap" 199c869993eSxy #define PROP_ADV_10FDX_CAP "adv_10fdx_cap" 200c869993eSxy #define PROP_ADV_10HDX_CAP "adv_10hdx_cap" 201c869993eSxy #define PROP_DEFAULT_MTU "default_mtu" 202c869993eSxy #define PROP_FLOW_CONTROL "flow_control" 203c869993eSxy #define PROP_TX_RING_SIZE "tx_ring_size" 204c869993eSxy #define PROP_RX_RING_SIZE "rx_ring_size" 205da14cebeSEric Cheng #define PROP_MR_ENABLE "mr_enable" 206da14cebeSEric Cheng #define PROP_RX_GROUP_NUM "rx_group_number" 207c869993eSxy 208c869993eSxy #define PROP_INTR_FORCE "intr_force" 209c869993eSxy #define PROP_TX_HCKSUM_ENABLE "tx_hcksum_enable" 210c869993eSxy #define PROP_RX_HCKSUM_ENABLE "rx_hcksum_enable" 211c869993eSxy #define PROP_LSO_ENABLE "lso_enable" 212c869993eSxy #define PROP_TX_HEAD_WB_ENABLE "tx_head_wb_enable" 213c869993eSxy #define PROP_TX_COPY_THRESHOLD "tx_copy_threshold" 214c869993eSxy #define PROP_TX_RECYCLE_THRESHOLD "tx_recycle_threshold" 215c869993eSxy #define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold" 216c869993eSxy #define PROP_TX_RESCHED_THRESHOLD "tx_resched_threshold" 217c869993eSxy #define PROP_RX_COPY_THRESHOLD "rx_copy_threshold" 218c869993eSxy #define PROP_RX_LIMIT_PER_INTR "rx_limit_per_intr" 219c869993eSxy #define PROP_INTR_THROTTLING "intr_throttling" 2206ca163a1Svitezslav batrla - Sun Microsystems - Prague Czech Republic #define PROP_MCAST_MAX_NUM "mcast_max_num" 221c869993eSxy 222c869993eSxy #define IGB_LB_NONE 0 223c869993eSxy #define IGB_LB_EXTERNAL 1 224c869993eSxy #define IGB_LB_INTERNAL_PHY 3 225c869993eSxy #define IGB_LB_INTERNAL_SERDES 4 226c869993eSxy 227c869993eSxy enum ioc_reply { 228c869993eSxy IOC_INVAL = -1, /* bad, NAK with EINVAL */ 229c869993eSxy IOC_DONE, /* OK, reply sent */ 230c869993eSxy IOC_ACK, /* OK, just send ACK */ 231c869993eSxy IOC_REPLY /* OK, just send reply */ 232c869993eSxy }; 233c869993eSxy 234d11274aaSPaul Guo /* 235d11274aaSPaul Guo * For s/w context extraction from a tx frame 236d11274aaSPaul Guo */ 237d11274aaSPaul Guo #define TX_CXT_SUCCESS 0 238d11274aaSPaul Guo #define TX_CXT_E_LSO_CSUM (-1) 239d11274aaSPaul Guo #define TX_CXT_E_ETHER_TYPE (-2) 240c869993eSxy 241c869993eSxy #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area)->dma_handle, \ 242c869993eSxy 0, 0, (flag))) 243c869993eSxy 244c869993eSxy /* 245c869993eSxy * Defined for ring index operations 246c869993eSxy * ASSERT(index < limit) 247c869993eSxy * ASSERT(step < limit) 248c869993eSxy * ASSERT(index1 < limit) 249c869993eSxy * ASSERT(index2 < limit) 250c869993eSxy */ 251c869993eSxy #define NEXT_INDEX(index, step, limit) (((index) + (step)) < (limit) ? \ 252c869993eSxy (index) + (step) : (index) + (step) - (limit)) 253c869993eSxy #define PREV_INDEX(index, step, limit) ((index) >= (step) ? \ 254c869993eSxy (index) - (step) : (index) + (limit) - (step)) 255c869993eSxy #define OFFSET(index1, index2, limit) ((index1) <= (index2) ? \ 256c869993eSxy (index2) - (index1) : (index2) + (limit) - (index1)) 257c869993eSxy 258c869993eSxy #define LINK_LIST_INIT(_LH) \ 259c869993eSxy (_LH)->head = (_LH)->tail = NULL 260c869993eSxy 261c869993eSxy #define LIST_GET_HEAD(_LH) ((single_link_t *)((_LH)->head)) 262c869993eSxy 263c869993eSxy #define LIST_POP_HEAD(_LH) \ 264c869993eSxy (single_link_t *)(_LH)->head; \ 265c869993eSxy { \ 266c869993eSxy if ((_LH)->head != NULL) { \ 267c869993eSxy (_LH)->head = (_LH)->head->link; \ 268c869993eSxy if ((_LH)->head == NULL) \ 269c869993eSxy (_LH)->tail = NULL; \ 270c869993eSxy } \ 271c869993eSxy } 272c869993eSxy 273c869993eSxy #define LIST_GET_TAIL(_LH) ((single_link_t *)((_LH)->tail)) 274c869993eSxy 275c869993eSxy #define LIST_PUSH_TAIL(_LH, _E) \ 276c869993eSxy if ((_LH)->tail != NULL) { \ 277c869993eSxy (_LH)->tail->link = (single_link_t *)(_E); \ 278c869993eSxy (_LH)->tail = (single_link_t *)(_E); \ 279c869993eSxy } else { \ 280c869993eSxy (_LH)->head = (_LH)->tail = (single_link_t *)(_E); \ 281c869993eSxy } \ 282c869993eSxy (_E)->link = NULL; 283c869993eSxy 284c869993eSxy #define LIST_GET_NEXT(_LH, _E) \ 285c869993eSxy (((_LH)->tail == (single_link_t *)(_E)) ? \ 286c869993eSxy NULL : ((single_link_t *)(_E))->link) 287c869993eSxy 288c869993eSxy 289c869993eSxy typedef struct single_link { 290c869993eSxy struct single_link *link; 291c869993eSxy } single_link_t; 292c869993eSxy 293c869993eSxy typedef struct link_list { 294c869993eSxy single_link_t *head; 295c869993eSxy single_link_t *tail; 296c869993eSxy } link_list_t; 297c869993eSxy 298c869993eSxy /* 299c869993eSxy * Property lookups 300c869993eSxy */ 301c869993eSxy #define IGB_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 302c869993eSxy DDI_PROP_DONTPASS, (n)) 303c869993eSxy #define IGB_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 304c869993eSxy DDI_PROP_DONTPASS, (n), -1) 305c869993eSxy 306c869993eSxy 30780a11ad2Schenlu chen - Sun Microsystems - Beijing China /* capability/feature flags */ 30880a11ad2Schenlu chen - Sun Microsystems - Beijing China #define IGB_FLAG_HAS_DCA (1 << 0) /* has Direct Cache Access */ 30980a11ad2Schenlu chen - Sun Microsystems - Beijing China #define IGB_FLAG_VMDQ_POOL (1 << 1) /* has vmdq capability */ 31080a11ad2Schenlu chen - Sun Microsystems - Beijing China #define IGB_FLAG_NEED_CTX_IDX (1 << 2) /* context descriptor needs index */ 31180a11ad2Schenlu chen - Sun Microsystems - Beijing China 31280a11ad2Schenlu chen - Sun Microsystems - Beijing China /* function pointer for nic-specific functions */ 31380a11ad2Schenlu chen - Sun Microsystems - Beijing China typedef void (*igb_nic_func_t)(struct igb *); 31480a11ad2Schenlu chen - Sun Microsystems - Beijing China 31580a11ad2Schenlu chen - Sun Microsystems - Beijing China /* adapter-specific info for each supported device type */ 31680a11ad2Schenlu chen - Sun Microsystems - Beijing China typedef struct adapter_info { 31780a11ad2Schenlu chen - Sun Microsystems - Beijing China /* limits */ 31880a11ad2Schenlu chen - Sun Microsystems - Beijing China uint32_t max_rx_que_num; /* maximum number of rx queues */ 31980a11ad2Schenlu chen - Sun Microsystems - Beijing China uint32_t min_rx_que_num; /* minimum number of rx queues */ 32080a11ad2Schenlu chen - Sun Microsystems - Beijing China uint32_t def_rx_que_num; /* default number of rx queues */ 32180a11ad2Schenlu chen - Sun Microsystems - Beijing China uint32_t max_tx_que_num; /* maximum number of tx queues */ 32280a11ad2Schenlu chen - Sun Microsystems - Beijing China uint32_t min_tx_que_num; /* minimum number of tx queues */ 32380a11ad2Schenlu chen - Sun Microsystems - Beijing China uint32_t def_tx_que_num; /* default number of tx queues */ 32480a11ad2Schenlu chen - Sun Microsystems - Beijing China uint32_t max_intr_throttle; /* maximum interrupt throttle */ 32580a11ad2Schenlu chen - Sun Microsystems - Beijing China uint32_t min_intr_throttle; /* minimum interrupt throttle */ 32680a11ad2Schenlu chen - Sun Microsystems - Beijing China uint32_t def_intr_throttle; /* default interrupt throttle */ 32780a11ad2Schenlu chen - Sun Microsystems - Beijing China /* function pointers */ 32880a11ad2Schenlu chen - Sun Microsystems - Beijing China igb_nic_func_t enable_intr; /* enable adapter interrupts */ 32980a11ad2Schenlu chen - Sun Microsystems - Beijing China igb_nic_func_t setup_msix; /* set up msi-x vectors */ 33080a11ad2Schenlu chen - Sun Microsystems - Beijing China /* capabilities */ 33180a11ad2Schenlu chen - Sun Microsystems - Beijing China uint32_t flags; /* capability flags */ 332b8d0a377Schenlu chen - Sun Microsystems - Beijing China uint32_t rxdctl_mask; /* mask for RXDCTL register */ 33380a11ad2Schenlu chen - Sun Microsystems - Beijing China } adapter_info_t; 33480a11ad2Schenlu chen - Sun Microsystems - Beijing China 335c869993eSxy typedef union igb_ether_addr { 336c869993eSxy struct { 337c869993eSxy uint32_t high; 338c869993eSxy uint32_t low; 339c869993eSxy } reg; 340c869993eSxy struct { 341c869993eSxy uint8_t set; 342da14cebeSEric Cheng uint8_t group_index; 343c869993eSxy uint8_t addr[ETHERADDRL]; 344c869993eSxy } mac; 345c869993eSxy } igb_ether_addr_t; 346c869993eSxy 347c869993eSxy typedef enum { 348c869993eSxy USE_NONE, 349c869993eSxy USE_COPY, 350c869993eSxy USE_DMA 351c869993eSxy } tx_type_t; 352c869993eSxy 353d11274aaSPaul Guo typedef struct tx_context { 354c869993eSxy uint32_t hcksum_flags; 355c869993eSxy uint32_t ip_hdr_len; 356c869993eSxy uint32_t mac_hdr_len; 357c869993eSxy uint32_t l4_proto; 358d11274aaSPaul Guo uint32_t mss; 359d11274aaSPaul Guo uint32_t l4_hdr_len; 360d11274aaSPaul Guo boolean_t lso_flag; 361d11274aaSPaul Guo } tx_context_t; 362c869993eSxy 363c869993eSxy /* Hold address/length of each DMA segment */ 364c869993eSxy typedef struct sw_desc { 365c869993eSxy uint64_t address; 366c869993eSxy size_t length; 367c869993eSxy } sw_desc_t; 368c869993eSxy 369c869993eSxy /* Handles and addresses of DMA buffer */ 370c869993eSxy typedef struct dma_buffer { 371c869993eSxy caddr_t address; /* Virtual address */ 372c869993eSxy uint64_t dma_address; /* DMA (Hardware) address */ 373c869993eSxy ddi_acc_handle_t acc_handle; /* Data access handle */ 374c869993eSxy ddi_dma_handle_t dma_handle; /* DMA handle */ 375c869993eSxy size_t size; /* Buffer size */ 376c869993eSxy size_t len; /* Data length in the buffer */ 377c869993eSxy } dma_buffer_t; 378c869993eSxy 379c869993eSxy /* 380c869993eSxy * Tx Control Block 381c869993eSxy */ 382c869993eSxy typedef struct tx_control_block { 383c869993eSxy single_link_t link; 38469b2d733SGuoqing Zhu uint32_t last_index; 385c869993eSxy uint32_t frag_num; 386c869993eSxy uint32_t desc_num; 387c869993eSxy mblk_t *mp; 388c869993eSxy tx_type_t tx_type; 389c869993eSxy ddi_dma_handle_t tx_dma_handle; 390c869993eSxy dma_buffer_t tx_buf; 391c869993eSxy sw_desc_t desc[MAX_COOKIE]; 392c869993eSxy } tx_control_block_t; 393c869993eSxy 394c869993eSxy /* 395c869993eSxy * RX Control Block 396c869993eSxy */ 397c869993eSxy typedef struct rx_control_block { 398c869993eSxy mblk_t *mp; 399ac7f5757Schenlu chen - Sun Microsystems - Beijing China uint32_t ref_cnt; 400c869993eSxy dma_buffer_t rx_buf; 401c869993eSxy frtn_t free_rtn; 402ac7f5757Schenlu chen - Sun Microsystems - Beijing China struct igb_rx_data *rx_data; 403c869993eSxy } rx_control_block_t; 404c869993eSxy 405c869993eSxy /* 406c869993eSxy * Software Data Structure for Tx Ring 407c869993eSxy */ 408c869993eSxy typedef struct igb_tx_ring { 409c869993eSxy uint32_t index; /* Ring index */ 410da14cebeSEric Cheng uint32_t intr_vector; /* Interrupt vector index */ 411c869993eSxy 412c869993eSxy /* 413c869993eSxy * Mutexes 414c869993eSxy */ 415c869993eSxy kmutex_t tx_lock; 416c869993eSxy kmutex_t recycle_lock; 417c869993eSxy kmutex_t tcb_head_lock; 418c869993eSxy kmutex_t tcb_tail_lock; 419c869993eSxy 420c869993eSxy /* 421c869993eSxy * Tx descriptor ring definitions 422c869993eSxy */ 423c869993eSxy dma_buffer_t tbd_area; 424c869993eSxy union e1000_adv_tx_desc *tbd_ring; 425c869993eSxy uint32_t tbd_head; /* Index of next tbd to recycle */ 426c869993eSxy uint32_t tbd_tail; /* Index of next tbd to transmit */ 427c869993eSxy uint32_t tbd_free; /* Number of free tbd */ 428c869993eSxy 429c869993eSxy /* 430c869993eSxy * Tx control block list definitions 431c869993eSxy */ 432c869993eSxy tx_control_block_t *tcb_area; 433c869993eSxy tx_control_block_t **work_list; 434c869993eSxy tx_control_block_t **free_list; 435c869993eSxy uint32_t tcb_head; /* Head index of free list */ 436c869993eSxy uint32_t tcb_tail; /* Tail index of free list */ 437c869993eSxy uint32_t tcb_free; /* Number of free tcb in free list */ 438c869993eSxy 439c869993eSxy uint32_t *tbd_head_wb; /* Head write-back */ 440c869993eSxy uint32_t (*tx_recycle)(struct igb_tx_ring *); 441c869993eSxy 442c869993eSxy /* 443d11274aaSPaul Guo * s/w context structure for TCP/UDP checksum offload and LSO. 444c869993eSxy */ 445d11274aaSPaul Guo tx_context_t tx_context; 446c869993eSxy 447c869993eSxy /* 448c869993eSxy * Tx ring settings and status 449c869993eSxy */ 450c869993eSxy uint32_t ring_size; /* Tx descriptor ring size */ 451c869993eSxy uint32_t free_list_size; /* Tx free list size */ 452c869993eSxy 453c869993eSxy boolean_t reschedule; 454c869993eSxy uint32_t recycle_fail; 455c869993eSxy uint32_t stall_watchdog; 456c869993eSxy 4570dc2366fSVenugopal Iyer /* 4580dc2366fSVenugopal Iyer * Per-ring statistics 4590dc2366fSVenugopal Iyer */ 4600dc2366fSVenugopal Iyer uint64_t tx_pkts; /* Packets Transmitted Count */ 4610dc2366fSVenugopal Iyer uint64_t tx_bytes; /* Bytes Transmitted Count */ 4620dc2366fSVenugopal Iyer 463c869993eSxy #ifdef IGB_DEBUG 464c869993eSxy /* 465c869993eSxy * Debug statistics 466c869993eSxy */ 467c869993eSxy uint32_t stat_overload; 468c869993eSxy uint32_t stat_fail_no_tbd; 469c869993eSxy uint32_t stat_fail_no_tcb; 470c869993eSxy uint32_t stat_fail_dma_bind; 471c869993eSxy uint32_t stat_reschedule; 472da14cebeSEric Cheng uint32_t stat_pkt_cnt; 473c869993eSxy #endif 474c869993eSxy 475c869993eSxy /* 476c869993eSxy * Pointer to the igb struct 477c869993eSxy */ 478c869993eSxy struct igb *igb; 479da14cebeSEric Cheng mac_ring_handle_t ring_handle; /* call back ring handle */ 480c869993eSxy } igb_tx_ring_t; 481c869993eSxy 482c869993eSxy /* 483c869993eSxy * Software Receive Ring 484c869993eSxy */ 485ac7f5757Schenlu chen - Sun Microsystems - Beijing China typedef struct igb_rx_data { 486c869993eSxy kmutex_t recycle_lock; /* Recycle lock, for rcb_tail */ 487c869993eSxy 488c869993eSxy /* 489c869993eSxy * Rx descriptor ring definitions 490c869993eSxy */ 491c869993eSxy dma_buffer_t rbd_area; /* DMA buffer of rx desc ring */ 492c869993eSxy union e1000_adv_rx_desc *rbd_ring; /* Rx desc ring */ 493c869993eSxy uint32_t rbd_next; /* Index of next rx desc */ 494c869993eSxy 495c869993eSxy /* 496c869993eSxy * Rx control block list definitions 497c869993eSxy */ 498c869993eSxy rx_control_block_t *rcb_area; 499c869993eSxy rx_control_block_t **work_list; /* Work list of rcbs */ 500c869993eSxy rx_control_block_t **free_list; /* Free list of rcbs */ 501c869993eSxy uint32_t rcb_head; /* Index of next free rcb */ 502c869993eSxy uint32_t rcb_tail; /* Index to put recycled rcb */ 503c869993eSxy uint32_t rcb_free; /* Number of free rcbs */ 504c869993eSxy 505c869993eSxy /* 506ac7f5757Schenlu chen - Sun Microsystems - Beijing China * Rx sw ring settings and status 507c869993eSxy */ 508c869993eSxy uint32_t ring_size; /* Rx descriptor ring size */ 509c869993eSxy uint32_t free_list_size; /* Rx free list size */ 510ac7f5757Schenlu chen - Sun Microsystems - Beijing China 511ac7f5757Schenlu chen - Sun Microsystems - Beijing China uint32_t rcb_pending; 512ac7f5757Schenlu chen - Sun Microsystems - Beijing China uint32_t flag; 513ac7f5757Schenlu chen - Sun Microsystems - Beijing China 514ac7f5757Schenlu chen - Sun Microsystems - Beijing China struct igb_rx_ring *rx_ring; /* Pointer to rx ring */ 515ac7f5757Schenlu chen - Sun Microsystems - Beijing China } igb_rx_data_t; 516ac7f5757Schenlu chen - Sun Microsystems - Beijing China 517ac7f5757Schenlu chen - Sun Microsystems - Beijing China /* 518ac7f5757Schenlu chen - Sun Microsystems - Beijing China * Software Data Structure for Rx Ring 519ac7f5757Schenlu chen - Sun Microsystems - Beijing China */ 520ac7f5757Schenlu chen - Sun Microsystems - Beijing China typedef struct igb_rx_ring { 521ac7f5757Schenlu chen - Sun Microsystems - Beijing China uint32_t index; /* Ring index */ 522ac7f5757Schenlu chen - Sun Microsystems - Beijing China uint32_t intr_vector; /* Interrupt vector index */ 523ac7f5757Schenlu chen - Sun Microsystems - Beijing China 524ac7f5757Schenlu chen - Sun Microsystems - Beijing China igb_rx_data_t *rx_data; /* Rx software ring */ 525ac7f5757Schenlu chen - Sun Microsystems - Beijing China 526ac7f5757Schenlu chen - Sun Microsystems - Beijing China kmutex_t rx_lock; /* Rx access lock */ 527c869993eSxy 5280dc2366fSVenugopal Iyer /* 5290dc2366fSVenugopal Iyer * Per-ring statistics 5300dc2366fSVenugopal Iyer */ 5310dc2366fSVenugopal Iyer uint64_t rx_pkts; /* Packets Received Count */ 5320dc2366fSVenugopal Iyer uint64_t rx_bytes; /* Bytes Received Count */ 5330dc2366fSVenugopal Iyer 534c869993eSxy #ifdef IGB_DEBUG 535c869993eSxy /* 536c869993eSxy * Debug statistics 537c869993eSxy */ 538c869993eSxy uint32_t stat_frame_error; 539c869993eSxy uint32_t stat_cksum_error; 540c869993eSxy uint32_t stat_exceed_pkt; 541da14cebeSEric Cheng uint32_t stat_pkt_cnt; 542c869993eSxy #endif 543c869993eSxy 544c869993eSxy struct igb *igb; /* Pointer to igb struct */ 545b8d0a377Schenlu chen - Sun Microsystems - Beijing China mac_ring_handle_t ring_handle; /* call back ring handle */ 546da14cebeSEric Cheng uint32_t group_index; /* group index */ 547da14cebeSEric Cheng uint64_t ring_gen_num; 548c869993eSxy } igb_rx_ring_t; 549c869993eSxy 550da14cebeSEric Cheng /* 551da14cebeSEric Cheng * Software Receive Ring Group 552da14cebeSEric Cheng */ 553da14cebeSEric Cheng typedef struct igb_rx_group { 554da14cebeSEric Cheng uint32_t index; /* Group index */ 555da14cebeSEric Cheng mac_group_handle_t group_handle; /* call back group handle */ 556da14cebeSEric Cheng struct igb *igb; /* Pointer to igb struct */ 557da14cebeSEric Cheng } igb_rx_group_t; 558da14cebeSEric Cheng 559c869993eSxy typedef struct igb { 560c869993eSxy int instance; 561c869993eSxy mac_handle_t mac_hdl; 562c869993eSxy dev_info_t *dip; 563c869993eSxy struct e1000_hw hw; 564c869993eSxy struct igb_osdep osdep; 565c869993eSxy 56680a11ad2Schenlu chen - Sun Microsystems - Beijing China adapter_info_t *capab; /* adapter capabilities */ 56780a11ad2Schenlu chen - Sun Microsystems - Beijing China 568c869993eSxy uint32_t igb_state; 569c869993eSxy link_state_t link_state; 570c869993eSxy uint32_t link_speed; 571c869993eSxy uint32_t link_duplex; 572cf8dcc9bSzhefeng xu - Sun Microsystems - Beijing China boolean_t link_complete; 573cf8dcc9bSzhefeng xu - Sun Microsystems - Beijing China timeout_id_t link_tid; 574c869993eSxy 575c869993eSxy uint32_t reset_count; 576c869993eSxy uint32_t attach_progress; 577c869993eSxy uint32_t loopback_mode; 578ac7f5757Schenlu chen - Sun Microsystems - Beijing China uint32_t default_mtu; 579c869993eSxy uint32_t max_frame_size; 580b8d0a377Schenlu chen - Sun Microsystems - Beijing China uint32_t dout_sync; 581c869993eSxy 582ac7f5757Schenlu chen - Sun Microsystems - Beijing China uint32_t rcb_pending; 583ac7f5757Schenlu chen - Sun Microsystems - Beijing China 584da14cebeSEric Cheng uint32_t mr_enable; /* Enable multiple rings */ 585da14cebeSEric Cheng uint32_t vmdq_mode; /* Mode of VMDq */ 586da14cebeSEric Cheng 587c869993eSxy /* 588da14cebeSEric Cheng * Receive Rings and Groups 589c869993eSxy */ 590c869993eSxy igb_rx_ring_t *rx_rings; /* Array of rx rings */ 591c869993eSxy uint32_t num_rx_rings; /* Number of rx rings in use */ 592c869993eSxy uint32_t rx_ring_size; /* Rx descriptor ring size */ 593c869993eSxy uint32_t rx_buf_size; /* Rx buffer size */ 594da14cebeSEric Cheng igb_rx_group_t *rx_groups; /* Array of rx groups */ 595da14cebeSEric Cheng uint32_t num_rx_groups; /* Number of rx groups in use */ 596c869993eSxy 597c869993eSxy /* 598c869993eSxy * Transmit Rings 599c869993eSxy */ 600c869993eSxy igb_tx_ring_t *tx_rings; /* Array of tx rings */ 601c869993eSxy uint32_t num_tx_rings; /* Number of tx rings in use */ 602c869993eSxy uint32_t tx_ring_size; /* Tx descriptor ring size */ 603c869993eSxy uint32_t tx_buf_size; /* Tx buffer size */ 604c869993eSxy 605ac7f5757Schenlu chen - Sun Microsystems - Beijing China boolean_t tx_ring_init; 606c869993eSxy boolean_t tx_head_wb_enable; /* Tx head wrtie-back */ 607c869993eSxy boolean_t tx_hcksum_enable; /* Tx h/w cksum offload */ 608c869993eSxy boolean_t lso_enable; /* Large Segment Offload */ 609c869993eSxy uint32_t tx_copy_thresh; /* Tx copy threshold */ 610c869993eSxy uint32_t tx_recycle_thresh; /* Tx recycle threshold */ 611c869993eSxy uint32_t tx_overload_thresh; /* Tx overload threshold */ 612c869993eSxy uint32_t tx_resched_thresh; /* Tx reschedule threshold */ 613c869993eSxy boolean_t rx_hcksum_enable; /* Rx h/w cksum offload */ 614c869993eSxy uint32_t rx_copy_thresh; /* Rx copy threshold */ 615c869993eSxy uint32_t rx_limit_per_intr; /* Rx pkts per interrupt */ 616b8d0a377Schenlu chen - Sun Microsystems - Beijing China 617c869993eSxy uint32_t intr_throttling[MAX_NUM_EITR]; 618c869993eSxy uint32_t intr_force; 619c869993eSxy 620c869993eSxy int intr_type; 621c869993eSxy int intr_cnt; 622c869993eSxy int intr_cap; 623c869993eSxy size_t intr_size; 624c869993eSxy uint_t intr_pri; 625c869993eSxy ddi_intr_handle_t *htable; 626c869993eSxy uint32_t eims_mask; 627da14cebeSEric Cheng uint32_t ims_mask; 628c869993eSxy 629c869993eSxy kmutex_t gen_lock; /* General lock for device access */ 630c869993eSxy kmutex_t watchdog_lock; 631cf8dcc9bSzhefeng xu - Sun Microsystems - Beijing China kmutex_t link_lock; 632ac7f5757Schenlu chen - Sun Microsystems - Beijing China kmutex_t rx_pending_lock; 633c869993eSxy 634c869993eSxy boolean_t watchdog_enable; 635c869993eSxy boolean_t watchdog_start; 636c869993eSxy timeout_id_t watchdog_tid; 637c869993eSxy 638c869993eSxy boolean_t unicst_init; 639c869993eSxy uint32_t unicst_avail; 640c869993eSxy uint32_t unicst_total; 641c869993eSxy igb_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 642c869993eSxy uint32_t mcast_count; 6436ca163a1Svitezslav batrla - Sun Microsystems - Prague Czech Republic uint32_t mcast_alloc_count; 6446ca163a1Svitezslav batrla - Sun Microsystems - Prague Czech Republic uint32_t mcast_max_num; 6456ca163a1Svitezslav batrla - Sun Microsystems - Prague Czech Republic struct ether_addr *mcast_table; 646c869993eSxy 647c869993eSxy /* 648c869993eSxy * Kstat definitions 649c869993eSxy */ 650c869993eSxy kstat_t *igb_ks; 651c869993eSxy 652*13485e69SGarrett D'Amore /* 653*13485e69SGarrett D'Amore * Backing store for MAC stats. These are reported via GLDv3, instead 654*13485e69SGarrett D'Amore * of via our private kstat structure. 655*13485e69SGarrett D'Amore */ 656*13485e69SGarrett D'Amore uint64_t stat_tor; /* rbytes */ 657*13485e69SGarrett D'Amore uint64_t stat_tpr; /* rpackets */ 658*13485e69SGarrett D'Amore uint64_t stat_tot; /* obytes */ 659*13485e69SGarrett D'Amore uint64_t stat_tpt; /* opackets */ 660*13485e69SGarrett D'Amore uint64_t stat_colc; /* collisions */ 661*13485e69SGarrett D'Amore uint64_t stat_mcc; /* multi colls */ 662*13485e69SGarrett D'Amore uint64_t stat_scc; /* single colls */ 663*13485e69SGarrett D'Amore uint64_t stat_ecol; /* excessive colls */ 664*13485e69SGarrett D'Amore uint64_t stat_latecol; /* late colls */ 665*13485e69SGarrett D'Amore uint64_t stat_bptc; /* xmit bcast */ 666*13485e69SGarrett D'Amore uint64_t stat_mptc; /* xmit bcast */ 667*13485e69SGarrett D'Amore uint64_t stat_bprc; /* recv bcast */ 668*13485e69SGarrett D'Amore uint64_t stat_mprc; /* recv mcast */ 669*13485e69SGarrett D'Amore uint64_t stat_rnbc; /* recv nobuf */ 670*13485e69SGarrett D'Amore uint64_t stat_roc; /* recv toolong */ 671*13485e69SGarrett D'Amore uint64_t stat_sec; /* sqe errors */ 672*13485e69SGarrett D'Amore uint64_t stat_dc; /* defer */ 673*13485e69SGarrett D'Amore uint64_t stat_algnerrc; /* align errors */ 674*13485e69SGarrett D'Amore uint64_t stat_crcerrs; /* crc errors */ 675*13485e69SGarrett D'Amore uint64_t stat_cexterr; /* carrier extension errors */ 676*13485e69SGarrett D'Amore uint64_t stat_ruc; /* recv tooshort */ 677*13485e69SGarrett D'Amore uint64_t stat_rjc; /* recv jabber */ 678*13485e69SGarrett D'Amore uint64_t stat_rxerrc; /* recv errors */ 679*13485e69SGarrett D'Amore 680ac7f5757Schenlu chen - Sun Microsystems - Beijing China uint32_t param_en_1000fdx_cap:1, 681ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_en_1000hdx_cap:1, 682ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_en_100t4_cap:1, 683ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_en_100fdx_cap:1, 684ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_en_100hdx_cap:1, 685ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_en_10fdx_cap:1, 686ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_en_10hdx_cap:1, 687ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_1000fdx_cap:1, 688ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_1000hdx_cap:1, 689ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_100t4_cap:1, 690ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_100fdx_cap:1, 691ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_100hdx_cap:1, 692ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_10fdx_cap:1, 693ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_10hdx_cap:1, 694ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_autoneg_cap:1, 695ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_pause_cap:1, 696ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_asym_pause_cap:1, 697ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_rem_fault:1, 698ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_adv_1000fdx_cap:1, 699ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_adv_1000hdx_cap:1, 700ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_adv_100t4_cap:1, 701ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_adv_100fdx_cap:1, 702ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_adv_100hdx_cap:1, 703ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_adv_10fdx_cap:1, 704ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_adv_10hdx_cap:1, 705ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_adv_autoneg_cap:1, 706ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_adv_pause_cap:1, 707ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_adv_asym_pause_cap:1, 708ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_adv_rem_fault:1, 709ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_lp_1000fdx_cap:1, 710ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_lp_1000hdx_cap:1, 711ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_lp_100t4_cap:1; 712ac7f5757Schenlu chen - Sun Microsystems - Beijing China 713ac7f5757Schenlu chen - Sun Microsystems - Beijing China uint32_t param_lp_100fdx_cap:1, 714ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_lp_100hdx_cap:1, 715ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_lp_10fdx_cap:1, 716ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_lp_10hdx_cap:1, 717ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_lp_autoneg_cap:1, 718ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_lp_pause_cap:1, 719ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_lp_asym_pause_cap:1, 720ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_lp_rem_fault:1, 721ac7f5757Schenlu chen - Sun Microsystems - Beijing China param_pad_to_32:24; 722c869993eSxy 7238bb4b220Sgl /* 7248bb4b220Sgl * FMA capabilities 7258bb4b220Sgl */ 7268bb4b220Sgl int fm_capabilities; 7278bb4b220Sgl 728d11274aaSPaul Guo ulong_t page_size; 729c869993eSxy } igb_t; 730c869993eSxy 731c869993eSxy typedef struct igb_stat { 732c869993eSxy 733c869993eSxy kstat_named_t reset_count; /* Reset Count */ 734b8d0a377Schenlu chen - Sun Microsystems - Beijing China kstat_named_t dout_sync; /* DMA out of sync */ 735b8d0a377Schenlu chen - Sun Microsystems - Beijing China #ifdef IGB_DEBUG 736c869993eSxy kstat_named_t rx_frame_error; /* Rx Error in Packet */ 737c869993eSxy kstat_named_t rx_cksum_error; /* Rx Checksum Error */ 738c869993eSxy kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */ 739c869993eSxy 740c869993eSxy kstat_named_t tx_overload; /* Tx Desc Ring Overload */ 741c869993eSxy kstat_named_t tx_fail_no_tcb; /* Tx Fail Freelist Empty */ 742c869993eSxy kstat_named_t tx_fail_no_tbd; /* Tx Fail Desc Ring Empty */ 743c869993eSxy kstat_named_t tx_fail_dma_bind; /* Tx Fail DMA bind */ 744c869993eSxy kstat_named_t tx_reschedule; /* Tx Reschedule */ 745c869993eSxy 746c869993eSxy kstat_named_t gprc; /* Good Packets Received Count */ 747c869993eSxy kstat_named_t gptc; /* Good Packets Xmitted Count */ 748c869993eSxy kstat_named_t gor; /* Good Octets Received Count */ 749c869993eSxy kstat_named_t got; /* Good Octets Xmitd Count */ 750c869993eSxy kstat_named_t prc64; /* Packets Received - 64b */ 751c869993eSxy kstat_named_t prc127; /* Packets Received - 65-127b */ 752c869993eSxy kstat_named_t prc255; /* Packets Received - 127-255b */ 753c869993eSxy kstat_named_t prc511; /* Packets Received - 256-511b */ 754c869993eSxy kstat_named_t prc1023; /* Packets Received - 511-1023b */ 755c869993eSxy kstat_named_t prc1522; /* Packets Received - 1024-1522b */ 756c869993eSxy kstat_named_t ptc64; /* Packets Xmitted (64b) */ 757c869993eSxy kstat_named_t ptc127; /* Packets Xmitted (64-127b) */ 758c869993eSxy kstat_named_t ptc255; /* Packets Xmitted (128-255b) */ 759c869993eSxy kstat_named_t ptc511; /* Packets Xmitted (255-511b) */ 760c869993eSxy kstat_named_t ptc1023; /* Packets Xmitted (512-1023b) */ 761c869993eSxy kstat_named_t ptc1522; /* Packets Xmitted (1024-1522b */ 762c869993eSxy #endif 763c869993eSxy kstat_named_t symerrs; /* Symbol Error Count */ 764c869993eSxy kstat_named_t mpc; /* Missed Packet Count */ 765c869993eSxy kstat_named_t rlec; /* Receive Length Error Count */ 766c869993eSxy kstat_named_t xonrxc; /* XON Received Count */ 767c869993eSxy kstat_named_t xontxc; /* XON Xmitted Count */ 768c869993eSxy kstat_named_t xoffrxc; /* XOFF Received Count */ 769c869993eSxy kstat_named_t xofftxc; /* Xoff Xmitted Count */ 770c869993eSxy kstat_named_t fcruc; /* Unknown Flow Conrol Packet Rcvd Count */ 771c869993eSxy kstat_named_t rfc; /* Receive Frag Count */ 772c869993eSxy kstat_named_t tncrs; /* Transmit with no CRS */ 773c869993eSxy kstat_named_t tsctc; /* TCP seg contexts xmit count */ 774c869993eSxy kstat_named_t tsctfc; /* TCP seg contexts xmit fail count */ 775c869993eSxy } igb_stat_t; 776c869993eSxy 777c869993eSxy /* 778c869993eSxy * Function prototypes in e1000_osdep.c 779c869993eSxy */ 7807d46e7adSzhefeng xu - Sun Microsystems - Beijing China void e1000_write_pci_cfg(struct e1000_hw *, uint32_t, uint16_t *); 7817d46e7adSzhefeng xu - Sun Microsystems - Beijing China void e1000_read_pci_cfg(struct e1000_hw *, uint32_t, uint16_t *); 7827d46e7adSzhefeng xu - Sun Microsystems - Beijing China int32_t e1000_read_pcie_cap_reg(struct e1000_hw *, uint32_t, uint16_t *); 7837d46e7adSzhefeng xu - Sun Microsystems - Beijing China int32_t e1000_write_pcie_cap_reg(struct e1000_hw *, uint32_t, uint16_t *); 7843f7e60a6Szhefeng xu - Sun Microsystems - Beijing China void e1000_rar_clear(struct e1000_hw *, uint32_t); 7853f7e60a6Szhefeng xu - Sun Microsystems - Beijing China void e1000_rar_set_vmdq(struct e1000_hw *, const uint8_t *, uint32_t, 78680a11ad2Schenlu chen - Sun Microsystems - Beijing China uint32_t, uint8_t); 787c869993eSxy 788c869993eSxy /* 789c869993eSxy * Function prototypes in igb_buf.c 790c869993eSxy */ 791c869993eSxy int igb_alloc_dma(igb_t *); 792c869993eSxy void igb_free_dma(igb_t *); 793ac7f5757Schenlu chen - Sun Microsystems - Beijing China void igb_free_dma_buffer(dma_buffer_t *); 794ac7f5757Schenlu chen - Sun Microsystems - Beijing China int igb_alloc_rx_ring_data(igb_rx_ring_t *rx_ring); 795ac7f5757Schenlu chen - Sun Microsystems - Beijing China void igb_free_rx_ring_data(igb_rx_data_t *rx_data); 796c869993eSxy 797c869993eSxy /* 798c869993eSxy * Function prototypes in igb_main.c 799c869993eSxy */ 800ac7f5757Schenlu chen - Sun Microsystems - Beijing China int igb_start(igb_t *, boolean_t); 801ac7f5757Schenlu chen - Sun Microsystems - Beijing China void igb_stop(igb_t *, boolean_t); 802c869993eSxy int igb_setup_link(igb_t *, boolean_t); 803da14cebeSEric Cheng int igb_unicst_find(igb_t *, const uint8_t *); 804da14cebeSEric Cheng int igb_unicst_set(igb_t *, const uint8_t *, int); 805c869993eSxy int igb_multicst_add(igb_t *, const uint8_t *); 806c869993eSxy int igb_multicst_remove(igb_t *, const uint8_t *); 807c869993eSxy enum ioc_reply igb_loopback_ioctl(igb_t *, struct iocblk *, mblk_t *); 808c869993eSxy void igb_enable_watchdog_timer(igb_t *); 809c869993eSxy void igb_disable_watchdog_timer(igb_t *); 810c869993eSxy int igb_atomic_reserve(uint32_t *, uint32_t); 8118bb4b220Sgl int igb_check_acc_handle(ddi_acc_handle_t); 8128bb4b220Sgl int igb_check_dma_handle(ddi_dma_handle_t); 8138bb4b220Sgl void igb_fm_ereport(igb_t *, char *); 814837c1ac4SStephen Hanson void igb_set_fma_flags(int); 815c869993eSxy 816c869993eSxy /* 817c869993eSxy * Function prototypes in igb_gld.c 818c869993eSxy */ 819c869993eSxy int igb_m_start(void *); 820c869993eSxy void igb_m_stop(void *); 821c869993eSxy int igb_m_promisc(void *, boolean_t); 822c869993eSxy int igb_m_multicst(void *, boolean_t, const uint8_t *); 823c869993eSxy int igb_m_unicst(void *, const uint8_t *); 824c869993eSxy int igb_m_stat(void *, uint_t, uint64_t *); 825c869993eSxy void igb_m_resources(void *); 826c869993eSxy void igb_m_ioctl(void *, queue_t *, mblk_t *); 827c869993eSxy boolean_t igb_m_getcapab(void *, mac_capab_t, void *); 828da14cebeSEric Cheng void igb_fill_ring(void *, mac_ring_type_t, const int, const int, 829da14cebeSEric Cheng mac_ring_info_t *, mac_ring_handle_t); 830ac7f5757Schenlu chen - Sun Microsystems - Beijing China int igb_m_setprop(void *, const char *, mac_prop_id_t, uint_t, const void *); 8310dc2366fSVenugopal Iyer int igb_m_getprop(void *, const char *, mac_prop_id_t, uint_t, void *); 8320dc2366fSVenugopal Iyer void igb_m_propinfo(void *, const char *, mac_prop_id_t, 8330dc2366fSVenugopal Iyer mac_prop_info_handle_t); 834ac7f5757Schenlu chen - Sun Microsystems - Beijing China int igb_set_priv_prop(igb_t *, const char *, uint_t, const void *); 8350dc2366fSVenugopal Iyer int igb_get_priv_prop(igb_t *, const char *, uint_t, void *); 8360dc2366fSVenugopal Iyer void igb_priv_prop_info(igb_t *, const char *, mac_prop_info_handle_t); 837ac7f5757Schenlu chen - Sun Microsystems - Beijing China boolean_t igb_param_locked(mac_prop_id_t); 838da14cebeSEric Cheng void igb_fill_group(void *arg, mac_ring_type_t, const int, 839da14cebeSEric Cheng mac_group_info_t *, mac_group_handle_t); 840da14cebeSEric Cheng int igb_rx_ring_intr_enable(mac_intr_handle_t); 841da14cebeSEric Cheng int igb_rx_ring_intr_disable(mac_intr_handle_t); 842ac7f5757Schenlu chen - Sun Microsystems - Beijing China int igb_get_def_val(igb_t *, mac_prop_id_t, uint_t, void *); 843c869993eSxy 844c869993eSxy /* 845c869993eSxy * Function prototypes in igb_rx.c 846c869993eSxy */ 847da14cebeSEric Cheng mblk_t *igb_rx(igb_rx_ring_t *, int); 848c869993eSxy void igb_rx_recycle(caddr_t arg); 849c869993eSxy 850c869993eSxy /* 851c869993eSxy * Function prototypes in igb_tx.c 852c869993eSxy */ 853c869993eSxy void igb_free_tcb(tx_control_block_t *); 854c869993eSxy void igb_put_free_list(igb_tx_ring_t *, link_list_t *); 855c869993eSxy uint32_t igb_tx_recycle_legacy(igb_tx_ring_t *); 856c869993eSxy uint32_t igb_tx_recycle_head_wb(igb_tx_ring_t *); 857c869993eSxy 858c869993eSxy /* 859c869993eSxy * Function prototypes in igb_log.c 860c869993eSxy */ 861c869993eSxy void igb_notice(void *, const char *, ...); 862c869993eSxy void igb_log(void *, const char *, ...); 863c869993eSxy void igb_error(void *, const char *, ...); 864c869993eSxy 865c869993eSxy /* 866c869993eSxy * Function prototypes in igb_stat.c 867c869993eSxy */ 868c869993eSxy int igb_init_stats(igb_t *); 869c869993eSxy 870da14cebeSEric Cheng mblk_t *igb_rx_ring_poll(void *, int); 871da14cebeSEric Cheng mblk_t *igb_tx_ring_send(void *, mblk_t *); 8720dc2366fSVenugopal Iyer int igb_rx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 8730dc2366fSVenugopal Iyer int igb_tx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 874c869993eSxy 875c869993eSxy #ifdef __cplusplus 876c869993eSxy } 877c869993eSxy #endif 878c869993eSxy 879c869993eSxy #endif /* _IGB_SW_H */ 880