1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2015 OmniTI Computer Consulting, Inc. All rights reserved. 14 * Copyright 2019 Joyent, Inc. 15 * Copyright 2017 Tegile Systems, Inc. All rights reserved. 16 * Copyright 2020 Ryan Zezeski 17 */ 18 19 /* 20 * Please see i40e_main.c for an introduction to the device driver, its layout, 21 * and more. 22 */ 23 24 #ifndef _I40E_SW_H 25 #define _I40E_SW_H 26 27 #ifdef __cplusplus 28 extern "C" { 29 #endif 30 31 #include <sys/types.h> 32 #include <sys/conf.h> 33 #include <sys/debug.h> 34 #include <sys/stropts.h> 35 #include <sys/stream.h> 36 #include <sys/strsun.h> 37 #include <sys/strlog.h> 38 #include <sys/kmem.h> 39 #include <sys/stat.h> 40 #include <sys/kstat.h> 41 #include <sys/modctl.h> 42 #include <sys/errno.h> 43 #include <sys/dlpi.h> 44 #include <sys/mac_provider.h> 45 #include <sys/mac_ether.h> 46 #include <sys/vlan.h> 47 #include <sys/ddi.h> 48 #include <sys/sunddi.h> 49 #include <sys/pci.h> 50 #include <sys/pcie.h> 51 #include <sys/sdt.h> 52 #include <sys/ethernet.h> 53 #include <sys/pattr.h> 54 #include <sys/strsubr.h> 55 #include <sys/netlb.h> 56 #include <sys/random.h> 57 #include <inet/common.h> 58 #include <inet/tcp.h> 59 #include <inet/ip.h> 60 #include <inet/mi.h> 61 #include <inet/nd.h> 62 #include <netinet/udp.h> 63 #include <netinet/sctp.h> 64 #include <sys/bitmap.h> 65 #include <sys/cpuvar.h> 66 #include <sys/ddifm.h> 67 #include <sys/fm/protocol.h> 68 #include <sys/fm/util.h> 69 #include <sys/disp.h> 70 #include <sys/fm/io/ddi.h> 71 #include <sys/list.h> 72 #include <sys/debug.h> 73 #include <sys/sdt.h> 74 #include <sys/ddi_ufm.h> 75 #include "i40e_type.h" 76 #include "i40e_osdep.h" 77 #include "i40e_prototype.h" 78 #include "i40e_xregs.h" 79 80 #define I40E_MODULE_NAME "i40e" 81 82 #define I40E_ADAPTER_REGSET 1 83 84 /* 85 * Configuration constants. Note that the hardware defines a minimum bound of 32 86 * descriptors and requires that the programming of the descriptor lengths be 87 * aligned in units of 32 descriptors. 88 */ 89 #define I40E_MIN_TX_RING_SIZE 64 90 #define I40E_MAX_TX_RING_SIZE 4096 91 #define I40E_DEF_TX_RING_SIZE 1024 92 93 /* 94 * Place an artificial limit on the max number of groups. The X710 95 * series supports up to 384 VSIs to be partitioned across PFs as the 96 * driver sees fit. But until we support more interrupts this seems 97 * like a good place to start. 98 */ 99 #define I40E_MIN_NUM_RX_GROUPS 1 100 #define I40E_MAX_NUM_RX_GROUPS 32 101 #define I40E_DEF_NUM_RX_GROUPS 16 102 103 #define I40E_MIN_RX_RING_SIZE 64 104 #define I40E_MAX_RX_RING_SIZE 4096 105 #define I40E_DEF_RX_RING_SIZE 1024 106 107 #define I40E_DESC_ALIGN 32 108 109 /* 110 * Sizes used for asynchronous processing of the adminq. We allocate a fixed 111 * size buffer for each instance of the device during attach time, rather than 112 * allocating and freeing one during interrupt processing. 113 * 114 * We also define the descriptor size of the admin queue here. 115 */ 116 #define I40E_ADMINQ_BUFSZ 4096 117 #define I40E_MAX_ADMINQ_SIZE 1024 118 #define I40E_DEF_ADMINQ_SIZE 256 119 120 /* 121 * Note, while the min and maximum values are based upon the sizing of the ring 122 * itself, the default is taken from ixgbe without much thought. It's basically 123 * been cargo culted. See i40e_transceiver.c for a bit more information. 124 */ 125 #define I40E_MIN_RX_LIMIT_PER_INTR 16 126 #define I40E_MAX_RX_LIMIT_PER_INTR 4096 127 #define I40E_DEF_RX_LIMIT_PER_INTR 256 128 129 /* 130 * Valid MTU ranges. Note that the XL710's maximum payload is actually 9728. 131 * However, we need to adjust for the ETHERFCSL (4 bytes) and the Ethernet VLAN 132 * header size (18 bytes) to get the actual maximum frame we can use. If 133 * different adapters end up with different sizes, we should make this value a 134 * bit more dynamic. 135 */ 136 #define I40E_MAX_MTU 9706 137 #define I40E_MIN_MTU ETHERMIN 138 #define I40E_DEF_MTU ETHERMTU 139 140 /* 141 * Interrupt throttling related values. Interrupt throttling values are defined 142 * in two microsecond increments. Note that a value of zero basically says do no 143 * ITR activity. A helpful way to think about these is that setting the ITR to a 144 * value will allow a certain number of interrupts per second. 145 * 146 * Our default values for RX allow 20k interrupts per second while our default 147 * values for TX allow for 5k interrupts per second. For other class interrupts, 148 * we limit ourselves to a rate of 2k/s. 149 */ 150 #define I40E_MIN_ITR 0x0000 151 #define I40E_MAX_ITR 0x0FF0 152 #define I40E_DEF_RX_ITR 0x0019 153 #define I40E_DEF_TX_ITR 0x0064 154 #define I40E_DEF_OTHER_ITR 0x00FA 155 156 /* 157 * Indexes into the three ITR registers that we have. 158 */ 159 typedef enum i40e_itr_index { 160 I40E_ITR_INDEX_RX = 0x0, 161 I40E_ITR_INDEX_TX = 0x1, 162 I40E_ITR_INDEX_OTHER = 0x2, 163 I40E_ITR_INDEX_NONE = 0x3 164 } i40e_itr_index_t; 165 166 /* 167 * The hardware claims to support LSO up to 256 KB, but due to the limitations 168 * imposed by the IP header for non-jumbo frames, we cap it at 64 KB. 169 */ 170 #define I40E_LSO_MAXLEN (64 * 1024) 171 172 #define I40E_CYCLIC_PERIOD NANOSEC /* 1 second */ 173 #define I40E_DRAIN_RX_WAIT (500 * MILLISEC) /* In us */ 174 175 /* 176 * All the other queue types for are defined by the common code. However, this 177 * is the constant to indicate that it's terminated. 178 */ 179 #define I40E_QUEUE_TYPE_EOL 0x7FF 180 181 /* 182 * See the comments in i40e_transceiver.c as to the purpose of this value and 183 * how it's used to ensure that the IP header is eventually aligned when it's 184 * received by the OS. 185 */ 186 #define I40E_BUF_IPHDR_ALIGNMENT 2 187 188 /* 189 * The XL710 controller has a total of eight buffers available for the 190 * transmission of any single frame. This is defined in 8.4.1 - Transmit 191 * Packet in System Memory. 192 */ 193 #define I40E_TX_MAX_COOKIE 8 194 195 /* 196 * An LSO frame can be as large as 64KB, so we allow a DMA bind to span more 197 * cookies than a non-LSO frame. The key here to is to select a value such 198 * that once the HW has chunked up the LSO frame into MSS-sized segments that no 199 * single segment spans more than 8 cookies (see comments for 200 * I40E_TX_MAX_COOKIE) 201 */ 202 #define I40E_TX_LSO_MAX_COOKIE 32 203 204 /* 205 * Sizing to determine the amount of available descriptors at which we'll 206 * consider ourselves blocked. Also, when we have these available, we'll then 207 * consider ourselves available to transmit to MAC again. Strictly speaking, the 208 * MAX is based on the ring size. The default sizing is based on ixgbe. 209 */ 210 #define I40E_MIN_TX_BLOCK_THRESH I40E_TX_MAX_COOKIE 211 #define I40E_DEF_TX_BLOCK_THRESH I40E_MIN_TX_BLOCK_THRESH 212 213 /* 214 * Sizing for DMA thresholds. These are used to indicate whether or not we 215 * should perform a bcopy or a DMA binding of a given message block. The range 216 * allows for setting things such that we'll always do a bcopy (a high value) or 217 * always perform a DMA binding (a low value). 218 */ 219 #define I40E_MIN_RX_DMA_THRESH 0 220 #define I40E_DEF_RX_DMA_THRESH 256 221 #define I40E_MAX_RX_DMA_THRESH INT32_MAX 222 223 #define I40E_MIN_TX_DMA_THRESH 0 224 #define I40E_DEF_TX_DMA_THRESH 256 225 #define I40E_MAX_TX_DMA_THRESH INT32_MAX 226 227 /* 228 * The max size of each individual tx buffer is 16KB - 1. 229 * See table 8-17 230 */ 231 #define I40E_MAX_TX_BUFSZ 0x0000000000003FFFull 232 233 /* 234 * Resource sizing counts. There are various aspects of hardware where we may 235 * have some variable number of elements that we need to handle. Such as the 236 * hardware capabilities and switch capacities. We cannot know a priori how many 237 * elements to do, so instead we take a starting guess and then will grow it up 238 * to an upper bound on a number of elements, to limit memory consumption in 239 * case of a hardware bug. 240 */ 241 #define I40E_HW_CAP_DEFAULT 40 242 #define I40E_SWITCH_CAP_DEFAULT 25 243 244 /* 245 * Host Memory Context related constants. 246 */ 247 #define I40E_HMC_RX_CTX_UNIT 128 248 #define I40E_HMC_RX_DBUFF_MIN 1024 249 #define I40E_HMC_RX_DBUFF_MAX (16 * 1024 - 128) 250 #define I40E_HMC_RX_DTYPE_NOSPLIT 0 251 #define I40E_HMC_RX_DSIZE_32BYTE 1 252 #define I40E_HMC_RX_CRCSTRIP_ENABLE 1 253 #define I40E_HMC_RX_FC_DISABLE 0 254 #define I40E_HMC_RX_L2TAGORDER 1 255 #define I40E_HMC_RX_HDRSPLIT_DISABLE 0 256 #define I40E_HMC_RX_INVLAN_DONTSTRIP 0 257 #define I40E_HMC_RX_TPH_DISABLE 0 258 #define I40E_HMC_RX_LOWRXQ_NOINTR 0 259 #define I40E_HMC_RX_PREFENA 1 260 261 #define I40E_HMC_TX_CTX_UNIT 128 262 #define I40E_HMC_TX_NEW_CONTEXT 1 263 #define I40E_HMC_TX_FC_DISABLE 0 264 #define I40E_HMC_TX_TS_DISABLE 0 265 #define I40E_HMC_TX_FD_DISABLE 0 266 #define I40E_HMC_TX_ALT_VLAN_DISABLE 0 267 #define I40E_HMC_TX_WB_ENABLE 1 268 #define I40E_HMC_TX_TPH_DISABLE 0 269 270 /* 271 * This defines the error mask that we care about from rx descriptors. Currently 272 * we're only concerned with the general errors and oversize errors. 273 */ 274 #define I40E_RX_ERR_BITS ((1 << I40E_RX_DESC_ERROR_RXE_SHIFT) | \ 275 (1 << I40E_RX_DESC_ERROR_OVERSIZE_SHIFT)) 276 277 /* 278 * Property sizing macros for firmware versions, etc. They need to be large 279 * enough to hold 32-bit quantities transformed to strings as %d.%d or %x. 280 */ 281 #define I40E_DDI_PROP_LEN 64 282 283 #define I40E_GROUP_NOMSIX 1 284 #define I40E_TRQPAIR_NOMSIX 1 285 286 /* 287 * It seems reasonable to cast this to void because the only reason that we 288 * should be getting a DDI_FAILURE is due to the fact that we specify addresses 289 * out of range. Because we specify no offset or address, it shouldn't happen. 290 */ 291 #ifdef DEBUG 292 #define I40E_DMA_SYNC(handle, flag) ASSERT0(ddi_dma_sync( \ 293 (handle)->dmab_dma_handle, 0, 0, \ 294 (flag))) 295 #else /* !DEBUG */ 296 #define I40E_DMA_SYNC(handle, flag) ((void) ddi_dma_sync( \ 297 (handle)->dmab_dma_handle, 0, 0, \ 298 (flag))) 299 #endif /* DEBUG */ 300 301 /* 302 * Constants related to ring startup and teardown. These refer to the amount of 303 * time that we're willing to wait for a ring to spin up and spin down. 304 */ 305 #define I40E_RING_WAIT_NTRIES 10 306 #define I40E_RING_WAIT_PAUSE 10 /* ms */ 307 308 /* 309 * Printed Board Assembly (PBA) length. These are derived from Table 6-2. 310 */ 311 #define I40E_PBANUM_LENGTH 12 312 #define I40E_PBANUM_STRLEN 13 313 314 /* 315 * Define the maximum number of queues for a traffic class. These values come 316 * from the 'Number and offset of queue pairs per TCs' section of the 'Add VSI 317 * Command Buffer' table. For the 710 controller family this is table 7-62 318 * (r2.5) and for the 722 this is table 38-216 (r2.0). 319 */ 320 #define I40E_710_MAX_TC_QUEUES 64 321 #define I40E_722_MAX_TC_QUEUES 128 322 323 /* 324 * Define the size of the HLUT table size. The HLUT table can either be 128 or 325 * 512 bytes. We always set the table size to be 512 bytes in i40e_chip_start(). 326 * Note, this should not be confused with the common code's macro 327 * I40E_HASH_LUT_SIZE_512 which is the bit pattern needed to tell the card to 328 * use a 512 byte HLUT. 329 */ 330 #define I40E_HLUT_TABLE_SIZE 512 331 332 /* 333 * Bit flags for attach_progress 334 */ 335 typedef enum i40e_attach_state { 336 I40E_ATTACH_PCI_CONFIG = 0x0001, /* PCI config setup */ 337 I40E_ATTACH_REGS_MAP = 0x0002, /* Registers mapped */ 338 I40E_ATTACH_PROPS = 0x0004, /* Properties initialized */ 339 I40E_ATTACH_ALLOC_INTR = 0x0008, /* Interrupts allocated */ 340 I40E_ATTACH_ALLOC_RINGSLOCKS = 0x0010, /* Rings & locks allocated */ 341 I40E_ATTACH_ADD_INTR = 0x0020, /* Intr handlers added */ 342 I40E_ATTACH_COMMON_CODE = 0x0040, /* Intel code initialized */ 343 I40E_ATTACH_INIT = 0x0080, /* Device initialized */ 344 I40E_ATTACH_STATS = 0x0200, /* Kstats created */ 345 I40E_ATTACH_MAC = 0x0800, /* MAC registered */ 346 I40E_ATTACH_ENABLE_INTR = 0x1000, /* DDI interrupts enabled */ 347 I40E_ATTACH_FM_INIT = 0x2000, /* FMA initialized */ 348 I40E_ATTACH_LINK_TIMER = 0x4000, /* link check timer */ 349 I40E_ATTACH_UFM_INIT = 0x8000, /* DDI UFM initialized */ 350 } i40e_attach_state_t; 351 352 353 /* 354 * State flags that what's going on in in the device. Some of these state flags 355 * indicate some aspirational work that needs to happen in the driver. 356 * 357 * I40E_UNKNOWN: The device has yet to be started. 358 * I40E_INITIALIZED: The device has been fully attached. 359 * I40E_STARTED: The device has come out of the GLDV3 start routine. 360 * I40E_SUSPENDED: The device is suspended and I/O among other things 361 * should not occur. This happens because of an actual 362 * DDI_SUSPEND or interrupt adjustments. 363 * I40E_STALL: The tx stall detection logic has found a stall. 364 * I40E_OVERTEMP: The device has encountered a temperature alarm. 365 * I40E_INTR_ADJUST: Our interrupts are being manipulated and therefore we 366 * shouldn't be manipulating their state. 367 * I40E_ERROR: We've detected an FM error and degraded the device. 368 */ 369 typedef enum i40e_state { 370 I40E_UNKNOWN = 0x00, 371 I40E_INITIALIZED = 0x01, 372 I40E_STARTED = 0x02, 373 I40E_SUSPENDED = 0x04, 374 I40E_STALL = 0x08, 375 I40E_OVERTEMP = 0x20, 376 I40E_INTR_ADJUST = 0x40, 377 I40E_ERROR = 0x80 378 } i40e_state_t; 379 380 381 /* 382 * Definitions for common Intel things that we use and some slightly more usable 383 * names. 384 */ 385 typedef struct i40e_hw i40e_hw_t; 386 typedef struct i40e_aqc_switch_resource_alloc_element_resp i40e_switch_rsrc_t; 387 388 /* 389 * Handles and addresses of DMA buffers. 390 */ 391 typedef struct i40e_dma_buffer { 392 caddr_t dmab_address; /* Virtual address */ 393 uint64_t dmab_dma_address; /* DMA (Hardware) address */ 394 ddi_acc_handle_t dmab_acc_handle; /* Data access handle */ 395 ddi_dma_handle_t dmab_dma_handle; /* DMA handle */ 396 size_t dmab_size; /* Buffer size */ 397 size_t dmab_len; /* Data length in the buffer */ 398 } i40e_dma_buffer_t; 399 400 /* 401 * RX Control Block 402 */ 403 typedef struct i40e_rx_control_block { 404 mblk_t *rcb_mp; 405 uint32_t rcb_ref; 406 i40e_dma_buffer_t rcb_dma; 407 frtn_t rcb_free_rtn; 408 struct i40e_rx_data *rcb_rxd; 409 } i40e_rx_control_block_t; 410 411 typedef enum { 412 I40E_TX_NONE, 413 I40E_TX_COPY, 414 I40E_TX_DMA, 415 I40E_TX_DESC, 416 } i40e_tx_type_t; 417 418 typedef struct i40e_tx_desc i40e_tx_desc_t; 419 typedef struct i40e_tx_context_desc i40e_tx_context_desc_t; 420 typedef union i40e_32byte_rx_desc i40e_rx_desc_t; 421 422 struct i40e_dma_bind_info { 423 caddr_t dbi_paddr; 424 size_t dbi_len; 425 }; 426 427 typedef struct i40e_tx_control_block { 428 struct i40e_tx_control_block *tcb_next; 429 mblk_t *tcb_mp; 430 i40e_tx_type_t tcb_type; 431 ddi_dma_handle_t tcb_dma_handle; 432 ddi_dma_handle_t tcb_lso_dma_handle; 433 i40e_dma_buffer_t tcb_dma; 434 struct i40e_dma_bind_info *tcb_bind_info; 435 uint_t tcb_bind_ncookies; 436 boolean_t tcb_used_lso; 437 } i40e_tx_control_block_t; 438 439 /* 440 * Receive ring data (used below). 441 */ 442 typedef struct i40e_rx_data { 443 struct i40e *rxd_i40e; 444 445 /* 446 * RX descriptor ring definitions 447 */ 448 i40e_dma_buffer_t rxd_desc_area; /* DMA buffer of rx desc ring */ 449 i40e_rx_desc_t *rxd_desc_ring; /* Rx desc ring */ 450 uint32_t rxd_desc_next; /* Index of next rx desc */ 451 452 /* 453 * RX control block list definitions 454 */ 455 kmutex_t rxd_free_lock; /* Lock to protect free data */ 456 i40e_rx_control_block_t *rxd_rcb_area; /* Array of control blocks */ 457 i40e_rx_control_block_t **rxd_work_list; /* Work list of rcbs */ 458 i40e_rx_control_block_t **rxd_free_list; /* Free list of rcbs */ 459 uint32_t rxd_rcb_free; /* Number of free rcbs */ 460 461 /* 462 * RX software ring settings 463 */ 464 uint32_t rxd_ring_size; /* Rx descriptor ring size */ 465 uint32_t rxd_free_list_size; /* Rx free list size */ 466 467 /* 468 * RX outstanding data. This is used to keep track of outstanding loaned 469 * descriptors after we've shut down receiving information. Note these 470 * are protected by the i40e_t`i40e_rx_pending_lock. 471 */ 472 uint32_t rxd_rcb_pending; 473 boolean_t rxd_shutdown; 474 } i40e_rx_data_t; 475 476 /* 477 * Structures for unicast and multicast addresses. Note that we keep the VSI id 478 * around for unicast addresses, since they may belong to different VSIs. 479 * However, since all multicast addresses belong to the default VSI, we don't 480 * duplicate that information. 481 */ 482 typedef struct i40e_uaddr { 483 uint8_t iua_mac[ETHERADDRL]; 484 int iua_vsi; 485 } i40e_uaddr_t; 486 487 typedef struct i40e_maddr { 488 uint8_t ima_mac[ETHERADDRL]; 489 } i40e_maddr_t; 490 491 /* 492 * Collection of RX statistics on a given queue. 493 */ 494 typedef struct i40e_rxq_stat { 495 /* 496 * The i40e hardware does not maintain statistics on a per-ring basis, 497 * only on a per-PF and per-VSI level. As such, to satisfy the GLDv3, we 498 * need to maintain our own stats for packets and bytes. 499 */ 500 kstat_named_t irxs_bytes; /* Bytes in on queue */ 501 kstat_named_t irxs_packets; /* Packets in on queue */ 502 503 /* 504 * The following set of stats cover non-checksum data path issues. 505 */ 506 kstat_named_t irxs_rx_desc_error; /* Error bit set on desc */ 507 kstat_named_t irxs_rx_copy_nomem; /* allocb failure for copy */ 508 kstat_named_t irxs_rx_intr_limit; /* Hit i40e_rx_limit_per_intr */ 509 kstat_named_t irxs_rx_bind_norcb; /* No replacement rcb free */ 510 kstat_named_t irxs_rx_bind_nomp; /* No mblk_t in bind rcb */ 511 512 /* 513 * The following set of statistics covers rx checksum related activity. 514 * These are all primarily set in i40e_rx_hcksum. If rx checksum 515 * activity is disabled, then these should all be zero. 516 */ 517 kstat_named_t irxs_hck_v4hdrok; /* Valid IPv4 Header */ 518 kstat_named_t irxs_hck_l4hdrok; /* Valid L4 Header */ 519 kstat_named_t irxs_hck_unknown; /* !pinfo.known */ 520 kstat_named_t irxs_hck_nol3l4p; /* Missing L3L4P bit in desc */ 521 kstat_named_t irxs_hck_iperr; /* IPE error bit set */ 522 kstat_named_t irxs_hck_eiperr; /* EIPE error bit set */ 523 kstat_named_t irxs_hck_l4err; /* L4E error bit set */ 524 kstat_named_t irxs_hck_v6skip; /* IPv6 case hw fails on */ 525 kstat_named_t irxs_hck_set; /* Total times we set cksum */ 526 kstat_named_t irxs_hck_miss; /* Times with zero cksum bits */ 527 } i40e_rxq_stat_t; 528 529 /* 530 * Collection of TX Statistics on a given queue 531 */ 532 typedef struct i40e_txq_stat { 533 kstat_named_t itxs_bytes; /* Bytes out on queue */ 534 kstat_named_t itxs_packets; /* Packets out on queue */ 535 kstat_named_t itxs_descriptors; /* Descriptors issued */ 536 kstat_named_t itxs_recycled; /* Descriptors reclaimed */ 537 kstat_named_t itxs_force_copy; /* non-TSO force copy */ 538 kstat_named_t itxs_tso_force_copy; /* TSO force copy */ 539 /* 540 * Various failure conditions. 541 */ 542 kstat_named_t itxs_hck_meoifail; /* ether offload failures */ 543 kstat_named_t itxs_hck_nol2info; /* Missing l2 info */ 544 kstat_named_t itxs_hck_nol3info; /* Missing l3 info */ 545 kstat_named_t itxs_hck_nol4info; /* Missing l4 info */ 546 kstat_named_t itxs_hck_badl3; /* Not IPv4/IPv6 */ 547 kstat_named_t itxs_hck_badl4; /* Bad L4 Paylaod */ 548 kstat_named_t itxs_lso_nohck; /* Missing offloads for LSO */ 549 kstat_named_t itxs_bind_fails; /* DMA bind failures */ 550 kstat_named_t itxs_tx_short; /* Tx chain too short */ 551 552 kstat_named_t itxs_err_notcb; /* No tcb's available */ 553 kstat_named_t itxs_err_nodescs; /* No tcb's available */ 554 kstat_named_t itxs_err_context; /* Total context failures */ 555 556 kstat_named_t itxs_num_unblocked; /* Number of MAC unblocks */ 557 } i40e_txq_stat_t; 558 559 /* 560 * An instance of an XL710 transmit/receive queue pair. This currently 561 * represents a combination of both a transmit and receive ring, though they 562 * should really be split apart into separate logical structures. Unfortunately, 563 * during initial work we mistakenly joined them together. 564 */ 565 typedef struct i40e_trqpair { 566 struct i40e *itrq_i40e; 567 568 /* Receive-side structures. */ 569 kmutex_t itrq_rx_lock; 570 mac_ring_handle_t itrq_macrxring; /* Receive ring handle. */ 571 i40e_rx_data_t *itrq_rxdata; /* Receive ring rx data. */ 572 uint64_t itrq_rxgen; /* Generation number for mac/GLDv3. */ 573 uint32_t itrq_index; /* Queue index in the PF */ 574 uint32_t itrq_rx_intrvec; /* Receive interrupt vector. */ 575 boolean_t itrq_intr_poll; /* True when polling */ 576 577 /* Receive-side stats. */ 578 i40e_rxq_stat_t itrq_rxstat; 579 kstat_t *itrq_rxkstat; 580 581 /* Transmit-side structures. */ 582 kmutex_t itrq_tx_lock; 583 mac_ring_handle_t itrq_mactxring; /* Transmit ring handle. */ 584 uint32_t itrq_tx_intrvec; /* Transmit interrupt vector. */ 585 boolean_t itrq_tx_blocked; /* Does MAC think we're blocked? */ 586 587 /* 588 * TX data sizing 589 */ 590 uint32_t itrq_tx_ring_size; 591 uint32_t itrq_tx_free_list_size; 592 593 /* 594 * TX descriptor ring data 595 */ 596 i40e_dma_buffer_t itrq_desc_area; /* DMA buffer of tx desc ring */ 597 i40e_tx_desc_t *itrq_desc_ring; /* TX Desc ring */ 598 volatile uint32_t *itrq_desc_wbhead; /* TX write-back index */ 599 uint32_t itrq_desc_head; /* Last index hw freed */ 600 uint32_t itrq_desc_tail; /* Index of next free desc */ 601 uint32_t itrq_desc_free; /* Number of free descriptors */ 602 603 /* 604 * TX control block (tcb) data 605 */ 606 kmutex_t itrq_tcb_lock; 607 i40e_tx_control_block_t *itrq_tcb_area; /* Array of control blocks */ 608 i40e_tx_control_block_t **itrq_tcb_work_list; /* In use tcb */ 609 i40e_tx_control_block_t **itrq_tcb_free_list; /* Available tcb */ 610 uint32_t itrq_tcb_free; /* Count of free tcb */ 611 612 /* Transmit-side stats. */ 613 i40e_txq_stat_t itrq_txstat; 614 kstat_t *itrq_txkstat; 615 616 } i40e_trqpair_t; 617 618 /* 619 * VSI statistics. 620 * 621 * This mirrors the i40e_eth_stats structure but transforms it into a kstat. 622 * Note that the stock statistic structure also includes entries for tx 623 * discards. However, this is not actually implemented for the VSI (see Table 624 * 7-221), hence why we don't include the member which would always have a value 625 * of zero. This choice was made to minimize confusion to someone looking at 626 * these, as a value of zero does not necessarily equate to the fact that it's 627 * not implemented. 628 */ 629 typedef struct i40e_vsi_stats { 630 uint64_t ivs_rx_bytes; /* gorc */ 631 uint64_t ivs_rx_unicast; /* uprc */ 632 uint64_t ivs_rx_multicast; /* mprc */ 633 uint64_t ivs_rx_broadcast; /* bprc */ 634 uint64_t ivs_rx_discards; /* rdpc */ 635 uint64_t ivs_rx_unknown_protocol; /* rupp */ 636 uint64_t ivs_tx_bytes; /* gotc */ 637 uint64_t ivs_tx_unicast; /* uptc */ 638 uint64_t ivs_tx_multicast; /* mptc */ 639 uint64_t ivs_tx_broadcast; /* bptc */ 640 uint64_t ivs_tx_errors; /* tepc */ 641 } i40e_vsi_stats_t; 642 643 typedef struct i40e_vsi_kstats { 644 kstat_named_t ivk_rx_bytes; 645 kstat_named_t ivk_rx_unicast; 646 kstat_named_t ivk_rx_multicast; 647 kstat_named_t ivk_rx_broadcast; 648 kstat_named_t ivk_rx_discards; 649 kstat_named_t ivk_rx_unknown_protocol; 650 kstat_named_t ivk_tx_bytes; 651 kstat_named_t ivk_tx_unicast; 652 kstat_named_t ivk_tx_multicast; 653 kstat_named_t ivk_tx_broadcast; 654 kstat_named_t ivk_tx_errors; 655 } i40e_vsi_kstats_t; 656 657 /* 658 * For pf statistics, we opt not to use the standard statistics as defined by 659 * the Intel common code. This also currently combines statistics that are 660 * global across the entire device. 661 */ 662 typedef struct i40e_pf_stats { 663 uint64_t ips_rx_bytes; /* gorc */ 664 uint64_t ips_rx_unicast; /* uprc */ 665 uint64_t ips_rx_multicast; /* mprc */ 666 uint64_t ips_rx_broadcast; /* bprc */ 667 uint64_t ips_tx_bytes; /* gotc */ 668 uint64_t ips_tx_unicast; /* uptc */ 669 uint64_t ips_tx_multicast; /* mptc */ 670 uint64_t ips_tx_broadcast; /* bptc */ 671 672 uint64_t ips_rx_size_64; /* prc64 */ 673 uint64_t ips_rx_size_127; /* prc127 */ 674 uint64_t ips_rx_size_255; /* prc255 */ 675 uint64_t ips_rx_size_511; /* prc511 */ 676 uint64_t ips_rx_size_1023; /* prc1023 */ 677 uint64_t ips_rx_size_1522; /* prc1522 */ 678 uint64_t ips_rx_size_9522; /* prc9522 */ 679 680 uint64_t ips_tx_size_64; /* ptc64 */ 681 uint64_t ips_tx_size_127; /* ptc127 */ 682 uint64_t ips_tx_size_255; /* ptc255 */ 683 uint64_t ips_tx_size_511; /* ptc511 */ 684 uint64_t ips_tx_size_1023; /* ptc1023 */ 685 uint64_t ips_tx_size_1522; /* ptc1522 */ 686 uint64_t ips_tx_size_9522; /* ptc9522 */ 687 688 uint64_t ips_link_xon_rx; /* lxonrxc */ 689 uint64_t ips_link_xoff_rx; /* lxoffrxc */ 690 uint64_t ips_link_xon_tx; /* lxontxc */ 691 uint64_t ips_link_xoff_tx; /* lxofftxc */ 692 uint64_t ips_priority_xon_rx[8]; /* pxonrxc[8] */ 693 uint64_t ips_priority_xoff_rx[8]; /* pxoffrxc[8] */ 694 uint64_t ips_priority_xon_tx[8]; /* pxontxc[8] */ 695 uint64_t ips_priority_xoff_tx[8]; /* pxofftxc[8] */ 696 uint64_t ips_priority_xon_2_xoff[8]; /* rxon2offcnt[8] */ 697 698 uint64_t ips_crc_errors; /* crcerrs */ 699 uint64_t ips_illegal_bytes; /* illerrc */ 700 uint64_t ips_mac_local_faults; /* mlfc */ 701 uint64_t ips_mac_remote_faults; /* mrfc */ 702 uint64_t ips_rx_length_errors; /* rlec */ 703 uint64_t ips_rx_undersize; /* ruc */ 704 uint64_t ips_rx_fragments; /* rfc */ 705 uint64_t ips_rx_oversize; /* roc */ 706 uint64_t ips_rx_jabber; /* rjc */ 707 uint64_t ips_rx_discards; /* rdpc */ 708 uint64_t ips_rx_vm_discards; /* ldpc */ 709 uint64_t ips_rx_short_discards; /* mspdc */ 710 uint64_t ips_tx_dropped_link_down; /* tdold */ 711 uint64_t ips_rx_unknown_protocol; /* rupp */ 712 uint64_t ips_rx_err1; /* rxerr1 */ 713 uint64_t ips_rx_err2; /* rxerr2 */ 714 } i40e_pf_stats_t; 715 716 typedef struct i40e_pf_kstats { 717 kstat_named_t ipk_rx_bytes; /* gorc */ 718 kstat_named_t ipk_rx_unicast; /* uprc */ 719 kstat_named_t ipk_rx_multicast; /* mprc */ 720 kstat_named_t ipk_rx_broadcast; /* bprc */ 721 kstat_named_t ipk_tx_bytes; /* gotc */ 722 kstat_named_t ipk_tx_unicast; /* uptc */ 723 kstat_named_t ipk_tx_multicast; /* mptc */ 724 kstat_named_t ipk_tx_broadcast; /* bptc */ 725 726 kstat_named_t ipk_rx_size_64; /* prc64 */ 727 kstat_named_t ipk_rx_size_127; /* prc127 */ 728 kstat_named_t ipk_rx_size_255; /* prc255 */ 729 kstat_named_t ipk_rx_size_511; /* prc511 */ 730 kstat_named_t ipk_rx_size_1023; /* prc1023 */ 731 kstat_named_t ipk_rx_size_1522; /* prc1522 */ 732 kstat_named_t ipk_rx_size_9522; /* prc9522 */ 733 734 kstat_named_t ipk_tx_size_64; /* ptc64 */ 735 kstat_named_t ipk_tx_size_127; /* ptc127 */ 736 kstat_named_t ipk_tx_size_255; /* ptc255 */ 737 kstat_named_t ipk_tx_size_511; /* ptc511 */ 738 kstat_named_t ipk_tx_size_1023; /* ptc1023 */ 739 kstat_named_t ipk_tx_size_1522; /* ptc1522 */ 740 kstat_named_t ipk_tx_size_9522; /* ptc9522 */ 741 742 kstat_named_t ipk_link_xon_rx; /* lxonrxc */ 743 kstat_named_t ipk_link_xoff_rx; /* lxoffrxc */ 744 kstat_named_t ipk_link_xon_tx; /* lxontxc */ 745 kstat_named_t ipk_link_xoff_tx; /* lxofftxc */ 746 kstat_named_t ipk_priority_xon_rx[8]; /* pxonrxc[8] */ 747 kstat_named_t ipk_priority_xoff_rx[8]; /* pxoffrxc[8] */ 748 kstat_named_t ipk_priority_xon_tx[8]; /* pxontxc[8] */ 749 kstat_named_t ipk_priority_xoff_tx[8]; /* pxofftxc[8] */ 750 kstat_named_t ipk_priority_xon_2_xoff[8]; /* rxon2offcnt[8] */ 751 752 kstat_named_t ipk_crc_errors; /* crcerrs */ 753 kstat_named_t ipk_illegal_bytes; /* illerrc */ 754 kstat_named_t ipk_mac_local_faults; /* mlfc */ 755 kstat_named_t ipk_mac_remote_faults; /* mrfc */ 756 kstat_named_t ipk_rx_length_errors; /* rlec */ 757 kstat_named_t ipk_rx_undersize; /* ruc */ 758 kstat_named_t ipk_rx_fragments; /* rfc */ 759 kstat_named_t ipk_rx_oversize; /* roc */ 760 kstat_named_t ipk_rx_jabber; /* rjc */ 761 kstat_named_t ipk_rx_discards; /* rdpc */ 762 kstat_named_t ipk_rx_vm_discards; /* ldpc */ 763 kstat_named_t ipk_rx_short_discards; /* mspdc */ 764 kstat_named_t ipk_tx_dropped_link_down; /* tdold */ 765 kstat_named_t ipk_rx_unknown_protocol; /* rupp */ 766 kstat_named_t ipk_rx_err1; /* rxerr1 */ 767 kstat_named_t ipk_rx_err2; /* rxerr2 */ 768 } i40e_pf_kstats_t; 769 770 /* 771 * Resources that are pooled and specific to a given i40e_t. 772 */ 773 typedef struct i40e_func_rsrc { 774 uint_t ifr_nrx_queue; 775 uint_t ifr_nrx_queue_used; 776 uint_t ifr_ntx_queue; 777 uint_t ifr_trx_queue_used; 778 uint_t ifr_nvsis; 779 uint_t ifr_nvsis_used; 780 uint_t ifr_nmacfilt; 781 uint_t ifr_nmacfilt_used; 782 uint_t ifr_nmcastfilt; 783 uint_t ifr_nmcastfilt_used; 784 } i40e_func_rsrc_t; 785 786 typedef struct i40e_vsi { 787 uint16_t iv_seid; 788 uint16_t iv_number; 789 kstat_t *iv_kstats; 790 i40e_vsi_stats_t iv_stats; 791 uint16_t iv_stats_id; 792 } i40e_vsi_t; 793 794 /* 795 * While irg_index and irg_grp_hdl aren't used anywhere, they are 796 * still useful for debugging. 797 */ 798 typedef struct i40e_rx_group { 799 uint32_t irg_index; /* index in i40e_rx_groups[] */ 800 uint16_t irg_vsi_seid; /* SEID of VSI for this group */ 801 mac_group_handle_t irg_grp_hdl; /* handle to mac_group_t */ 802 struct i40e *irg_i40e; /* ref to i40e_t */ 803 } i40e_rx_group_t; 804 805 /* 806 * Main i40e per-instance state. 807 */ 808 typedef struct i40e { 809 list_node_t i40e_glink; /* Global list link */ 810 list_node_t i40e_dlink; /* Device list link */ 811 kmutex_t i40e_general_lock; /* General device lock */ 812 813 /* 814 * General Data and management 815 */ 816 dev_info_t *i40e_dip; 817 int i40e_instance; 818 int i40e_fm_capabilities; 819 uint_t i40e_state; 820 i40e_attach_state_t i40e_attach_progress; 821 mac_handle_t i40e_mac_hdl; 822 ddi_periodic_t i40e_periodic_id; 823 824 /* 825 * Pointers to common code data structures and memory for the common 826 * code. 827 */ 828 struct i40e_hw i40e_hw_space; 829 struct i40e_osdep i40e_osdep_space; 830 struct i40e_aq_get_phy_abilities_resp i40e_phy; 831 void *i40e_aqbuf; 832 833 #define I40E_DEF_VSI_IDX 0 834 #define I40E_DEF_VSI(i40e) ((i40e)->i40e_vsis[I40E_DEF_VSI_IDX]) 835 #define I40E_DEF_VSI_SEID(i40e) (I40E_DEF_VSI(i40e).iv_seid) 836 837 /* 838 * Device state, switch information, and resources. 839 */ 840 i40e_vsi_t i40e_vsis[I40E_MAX_NUM_RX_GROUPS]; 841 uint16_t i40e_mac_seid; /* SEID of physical MAC */ 842 uint16_t i40e_veb_seid; /* switch atop MAC (SEID) */ 843 uint16_t i40e_vsi_avail; /* VSIs avail to this PF */ 844 uint16_t i40e_vsi_used; /* VSIs used by this PF */ 845 struct i40e_device *i40e_device; 846 i40e_func_rsrc_t i40e_resources; 847 uint16_t i40e_switch_rsrc_alloc; 848 uint16_t i40e_switch_rsrc_actual; 849 i40e_switch_rsrc_t *i40e_switch_rsrcs; 850 i40e_uaddr_t *i40e_uaddrs; 851 i40e_maddr_t *i40e_maddrs; 852 int i40e_mcast_promisc_count; 853 boolean_t i40e_promisc_on; 854 link_state_t i40e_link_state; 855 uint32_t i40e_link_speed; /* In Mbps */ 856 link_duplex_t i40e_link_duplex; 857 uint_t i40e_sdu; 858 uint_t i40e_frame_max; 859 860 /* 861 * Transmit and receive information, tunables, and MAC info. 862 */ 863 i40e_trqpair_t *i40e_trqpairs; 864 boolean_t i40e_mr_enable; 865 uint_t i40e_num_trqpairs; /* total TRQPs (per PF) */ 866 uint_t i40e_num_trqpairs_per_vsi; /* TRQPs per VSI */ 867 uint_t i40e_other_itr; 868 869 i40e_rx_group_t *i40e_rx_groups; 870 uint_t i40e_num_rx_groups; 871 int i40e_num_rx_descs; 872 uint32_t i40e_rx_ring_size; 873 uint32_t i40e_rx_buf_size; 874 boolean_t i40e_rx_hcksum_enable; 875 uint32_t i40e_rx_dma_min; 876 uint32_t i40e_rx_limit_per_intr; 877 uint_t i40e_rx_itr; 878 879 int i40e_num_tx_descs; 880 uint32_t i40e_tx_ring_size; 881 uint32_t i40e_tx_buf_size; 882 uint32_t i40e_tx_block_thresh; 883 boolean_t i40e_tx_hcksum_enable; 884 boolean_t i40e_tx_lso_enable; 885 uint32_t i40e_tx_dma_min; 886 uint_t i40e_tx_itr; 887 888 /* 889 * Interrupt state 890 */ 891 uint_t i40e_intr_pri; 892 uint_t i40e_intr_force; 893 uint_t i40e_intr_type; 894 int i40e_intr_cap; 895 uint32_t i40e_intr_count; 896 uint32_t i40e_intr_count_max; 897 uint32_t i40e_intr_count_min; 898 size_t i40e_intr_size; 899 ddi_intr_handle_t *i40e_intr_handles; 900 ddi_cb_handle_t i40e_callback_handle; 901 902 /* 903 * DMA attributes. See i40e_transceiver.c for why we have copies of them 904 * in the i40e_t. 905 */ 906 ddi_dma_attr_t i40e_static_dma_attr; 907 ddi_dma_attr_t i40e_txbind_dma_attr; 908 ddi_dma_attr_t i40e_txbind_lso_dma_attr; 909 ddi_device_acc_attr_t i40e_desc_acc_attr; 910 ddi_device_acc_attr_t i40e_buf_acc_attr; 911 912 /* 913 * The following two fields are used to protect and keep track of 914 * outstanding, loaned buffers to MAC. If we have these, we can't 915 * detach as we have active DMA memory outstanding. 916 */ 917 kmutex_t i40e_rx_pending_lock; 918 kcondvar_t i40e_rx_pending_cv; 919 uint32_t i40e_rx_pending; 920 921 /* 922 * PF statistics and VSI statistics. 923 */ 924 kmutex_t i40e_stat_lock; 925 kstat_t *i40e_pf_kstat; 926 i40e_pf_stats_t i40e_pf_stat; 927 928 /* 929 * Misc. stats and counters that should maybe one day be kstats. 930 */ 931 uint64_t i40e_s_link_status_errs; 932 uint32_t i40e_s_link_status_lasterr; 933 934 /* 935 * LED information. Note this state is only modified in 936 * i40e_gld_set_led() which is protected by MAC's serializer lock. 937 */ 938 uint32_t i40e_led_status; 939 boolean_t i40e_led_saved; 940 941 /* DDI UFM handle */ 942 ddi_ufm_handle_t *i40e_ufmh; 943 } i40e_t; 944 945 /* 946 * The i40e_device represents a PCI device which encapsulates multiple physical 947 * functions which are represented as an i40e_t. This is used to track the use 948 * of pooled resources throughout all of the various devices. 949 */ 950 typedef struct i40e_device { 951 list_node_t id_link; 952 dev_info_t *id_parent; 953 uint_t id_pci_bus; 954 uint_t id_pci_device; 955 uint_t id_nfuncs; /* Total number of functions */ 956 uint_t id_nreg; /* Total number present */ 957 list_t id_i40e_list; /* List of i40e_t's registered */ 958 i40e_switch_rsrc_t *id_rsrcs; /* Switch resources for this PF */ 959 uint_t id_rsrcs_alloc; /* Total allocated resources */ 960 uint_t id_rsrcs_act; /* Actual number of resources */ 961 } i40e_device_t; 962 963 /* Values for the interrupt forcing on the NIC. */ 964 #define I40E_INTR_NONE 0 965 #define I40E_INTR_MSIX 1 966 #define I40E_INTR_MSI 2 967 #define I40E_INTR_LEGACY 3 968 969 /* Hint that we don't want to do any polling... */ 970 #define I40E_POLL_NULL -1 971 972 /* 973 * Logging functions. 974 */ 975 /*PRINTFLIKE2*/ 976 extern void i40e_error(i40e_t *, const char *, ...) __KPRINTFLIKE(2); 977 /*PRINTFLIKE2*/ 978 extern void i40e_notice(i40e_t *, const char *, ...) __KPRINTFLIKE(2); 979 /*PRINTFLIKE2*/ 980 extern void i40e_log(i40e_t *, const char *, ...) __KPRINTFLIKE(2); 981 982 /* 983 * General link handling functions. 984 */ 985 extern void i40e_link_check(i40e_t *); 986 extern void i40e_update_mtu(i40e_t *); 987 988 /* 989 * FMA functions. 990 */ 991 extern int i40e_check_acc_handle(ddi_acc_handle_t); 992 extern int i40e_check_dma_handle(ddi_dma_handle_t); 993 extern void i40e_fm_ereport(i40e_t *, char *); 994 995 /* 996 * Interrupt handlers and interrupt handler setup. 997 */ 998 extern void i40e_intr_chip_init(i40e_t *); 999 extern void i40e_intr_chip_fini(i40e_t *); 1000 extern uint_t i40e_intr_msix(void *, void *); 1001 extern uint_t i40e_intr_msi(void *, void *); 1002 extern uint_t i40e_intr_legacy(void *, void *); 1003 extern void i40e_intr_io_enable_all(i40e_t *); 1004 extern void i40e_intr_io_disable_all(i40e_t *); 1005 extern void i40e_intr_io_clear_cause(i40e_t *); 1006 extern void i40e_intr_rx_queue_disable(i40e_trqpair_t *); 1007 extern void i40e_intr_rx_queue_enable(i40e_trqpair_t *); 1008 extern void i40e_intr_set_itr(i40e_t *, i40e_itr_index_t, uint_t); 1009 1010 /* 1011 * Receive-side functions 1012 */ 1013 extern mblk_t *i40e_ring_rx(i40e_trqpair_t *, int); 1014 extern mblk_t *i40e_ring_rx_poll(void *, int); 1015 extern void i40e_rx_recycle(caddr_t); 1016 1017 /* 1018 * Transmit-side functions 1019 */ 1020 mblk_t *i40e_ring_tx(void *, mblk_t *); 1021 extern void i40e_tx_recycle_ring(i40e_trqpair_t *); 1022 extern void i40e_tx_cleanup_ring(i40e_trqpair_t *); 1023 1024 /* 1025 * Statistics functions. 1026 */ 1027 extern boolean_t i40e_stats_init(i40e_t *); 1028 extern void i40e_stats_fini(i40e_t *); 1029 extern boolean_t i40e_stat_vsi_init(i40e_t *, uint_t); 1030 extern void i40e_stat_vsi_fini(i40e_t *, uint_t); 1031 extern boolean_t i40e_stats_trqpair_init(i40e_trqpair_t *); 1032 extern void i40e_stats_trqpair_fini(i40e_trqpair_t *); 1033 extern int i40e_m_stat(void *, uint_t, uint64_t *); 1034 extern int i40e_rx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 1035 extern int i40e_tx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 1036 1037 /* 1038 * MAC/GLDv3 functions, and functions called by MAC/GLDv3 support code. 1039 */ 1040 extern boolean_t i40e_register_mac(i40e_t *); 1041 extern boolean_t i40e_start(i40e_t *, boolean_t); 1042 extern void i40e_stop(i40e_t *, boolean_t); 1043 1044 /* 1045 * DMA & buffer functions and attributes 1046 */ 1047 extern void i40e_init_dma_attrs(i40e_t *, boolean_t); 1048 extern boolean_t i40e_alloc_ring_mem(i40e_t *); 1049 extern void i40e_free_ring_mem(i40e_t *, boolean_t); 1050 1051 #ifdef __cplusplus 1052 } 1053 #endif 1054 1055 #endif /* _I40E_SW_H */ 1056