1 /****************************************************************************** 2 3 Copyright (c) 2013-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD: head/sys/dev/ixl/i40e_adminq_cmd.h 284049 2015-06-05 22:52:42Z jfv $*/ 34 35 #ifndef _I40E_ADMINQ_CMD_H_ 36 #define _I40E_ADMINQ_CMD_H_ 37 38 /* This header file defines the i40e Admin Queue commands and is shared between 39 * i40e Firmware and Software. 40 * 41 * This file needs to comply with the Linux Kernel coding style. 42 */ 43 44 #define I40E_FW_API_VERSION_MAJOR 0x0001 45 #ifdef X722_SUPPORT 46 #define I40E_FW_API_VERSION_MINOR 0x0003 47 #else 48 #define I40E_FW_API_VERSION_MINOR 0x0004 49 #endif 50 51 struct i40e_aq_desc { 52 __le16 flags; 53 __le16 opcode; 54 __le16 datalen; 55 __le16 retval; 56 __le32 cookie_high; 57 __le32 cookie_low; 58 union { 59 struct { 60 __le32 param0; 61 __le32 param1; 62 __le32 param2; 63 __le32 param3; 64 } internal; 65 struct { 66 __le32 param0; 67 __le32 param1; 68 __le32 addr_high; 69 __le32 addr_low; 70 } external; 71 u8 raw[16]; 72 } params; 73 }; 74 75 /* Flags sub-structure 76 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 77 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 78 */ 79 80 /* command flags and offsets*/ 81 #define I40E_AQ_FLAG_DD_SHIFT 0 82 #define I40E_AQ_FLAG_CMP_SHIFT 1 83 #define I40E_AQ_FLAG_ERR_SHIFT 2 84 #define I40E_AQ_FLAG_VFE_SHIFT 3 85 #define I40E_AQ_FLAG_LB_SHIFT 9 86 #define I40E_AQ_FLAG_RD_SHIFT 10 87 #define I40E_AQ_FLAG_VFC_SHIFT 11 88 #define I40E_AQ_FLAG_BUF_SHIFT 12 89 #define I40E_AQ_FLAG_SI_SHIFT 13 90 #define I40E_AQ_FLAG_EI_SHIFT 14 91 #define I40E_AQ_FLAG_FE_SHIFT 15 92 93 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 94 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 95 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 96 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 97 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 98 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 99 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 100 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 101 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 102 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 103 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 104 105 /* error codes */ 106 enum i40e_admin_queue_err { 107 I40E_AQ_RC_OK = 0, /* success */ 108 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 109 I40E_AQ_RC_ENOENT = 2, /* No such element */ 110 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 111 I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 112 I40E_AQ_RC_EIO = 5, /* I/O error */ 113 I40E_AQ_RC_ENXIO = 6, /* No such resource */ 114 I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 115 I40E_AQ_RC_EAGAIN = 8, /* Try again */ 116 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 117 I40E_AQ_RC_EACCES = 10, /* Permission denied */ 118 I40E_AQ_RC_EFAULT = 11, /* Bad address */ 119 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 120 I40E_AQ_RC_EEXIST = 13, /* object already exists */ 121 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 122 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 123 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 124 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 125 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 126 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 127 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 128 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 129 I40E_AQ_RC_EFBIG = 22, /* File too large */ 130 }; 131 132 /* Admin Queue command opcodes */ 133 enum i40e_admin_queue_opc { 134 /* aq commands */ 135 i40e_aqc_opc_get_version = 0x0001, 136 i40e_aqc_opc_driver_version = 0x0002, 137 i40e_aqc_opc_queue_shutdown = 0x0003, 138 i40e_aqc_opc_set_pf_context = 0x0004, 139 140 /* resource ownership */ 141 i40e_aqc_opc_request_resource = 0x0008, 142 i40e_aqc_opc_release_resource = 0x0009, 143 144 i40e_aqc_opc_list_func_capabilities = 0x000A, 145 i40e_aqc_opc_list_dev_capabilities = 0x000B, 146 147 /* LAA */ 148 i40e_aqc_opc_mac_address_read = 0x0107, 149 i40e_aqc_opc_mac_address_write = 0x0108, 150 151 /* PXE */ 152 i40e_aqc_opc_clear_pxe_mode = 0x0110, 153 154 /* internal switch commands */ 155 i40e_aqc_opc_get_switch_config = 0x0200, 156 i40e_aqc_opc_add_statistics = 0x0201, 157 i40e_aqc_opc_remove_statistics = 0x0202, 158 i40e_aqc_opc_set_port_parameters = 0x0203, 159 i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 160 161 i40e_aqc_opc_rx_ctl_reg_read = 0x0206, 162 i40e_aqc_opc_rx_ctl_reg_write = 0x0207, 163 164 i40e_aqc_opc_add_vsi = 0x0210, 165 i40e_aqc_opc_update_vsi_parameters = 0x0211, 166 i40e_aqc_opc_get_vsi_parameters = 0x0212, 167 168 i40e_aqc_opc_add_pv = 0x0220, 169 i40e_aqc_opc_update_pv_parameters = 0x0221, 170 i40e_aqc_opc_get_pv_parameters = 0x0222, 171 172 i40e_aqc_opc_add_veb = 0x0230, 173 i40e_aqc_opc_update_veb_parameters = 0x0231, 174 i40e_aqc_opc_get_veb_parameters = 0x0232, 175 176 i40e_aqc_opc_delete_element = 0x0243, 177 178 i40e_aqc_opc_add_macvlan = 0x0250, 179 i40e_aqc_opc_remove_macvlan = 0x0251, 180 i40e_aqc_opc_add_vlan = 0x0252, 181 i40e_aqc_opc_remove_vlan = 0x0253, 182 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 183 i40e_aqc_opc_add_tag = 0x0255, 184 i40e_aqc_opc_remove_tag = 0x0256, 185 i40e_aqc_opc_add_multicast_etag = 0x0257, 186 i40e_aqc_opc_remove_multicast_etag = 0x0258, 187 i40e_aqc_opc_update_tag = 0x0259, 188 i40e_aqc_opc_add_control_packet_filter = 0x025A, 189 i40e_aqc_opc_remove_control_packet_filter = 0x025B, 190 i40e_aqc_opc_add_cloud_filters = 0x025C, 191 i40e_aqc_opc_remove_cloud_filters = 0x025D, 192 193 i40e_aqc_opc_add_mirror_rule = 0x0260, 194 i40e_aqc_opc_delete_mirror_rule = 0x0261, 195 196 /* DCB commands */ 197 i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 198 i40e_aqc_opc_dcb_updated = 0x0302, 199 200 /* TX scheduler */ 201 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 202 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 203 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 204 i40e_aqc_opc_query_vsi_bw_config = 0x0408, 205 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 206 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 207 208 i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 209 i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 210 i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 211 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 212 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 213 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 214 i40e_aqc_opc_query_port_ets_config = 0x0419, 215 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 216 i40e_aqc_opc_suspend_port_tx = 0x041B, 217 i40e_aqc_opc_resume_port_tx = 0x041C, 218 i40e_aqc_opc_configure_partition_bw = 0x041D, 219 220 /* hmc */ 221 i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 222 i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 223 224 /* phy commands*/ 225 i40e_aqc_opc_get_phy_abilities = 0x0600, 226 i40e_aqc_opc_set_phy_config = 0x0601, 227 i40e_aqc_opc_set_mac_config = 0x0603, 228 i40e_aqc_opc_set_link_restart_an = 0x0605, 229 i40e_aqc_opc_get_link_status = 0x0607, 230 i40e_aqc_opc_set_phy_int_mask = 0x0613, 231 i40e_aqc_opc_get_local_advt_reg = 0x0614, 232 i40e_aqc_opc_set_local_advt_reg = 0x0615, 233 i40e_aqc_opc_get_partner_advt = 0x0616, 234 i40e_aqc_opc_set_lb_modes = 0x0618, 235 i40e_aqc_opc_get_phy_wol_caps = 0x0621, 236 i40e_aqc_opc_set_phy_debug = 0x0622, 237 i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 238 239 /* NVM commands */ 240 i40e_aqc_opc_nvm_read = 0x0701, 241 i40e_aqc_opc_nvm_erase = 0x0702, 242 i40e_aqc_opc_nvm_update = 0x0703, 243 i40e_aqc_opc_nvm_config_read = 0x0704, 244 i40e_aqc_opc_nvm_config_write = 0x0705, 245 i40e_aqc_opc_oem_post_update = 0x0720, 246 247 /* virtualization commands */ 248 i40e_aqc_opc_send_msg_to_pf = 0x0801, 249 i40e_aqc_opc_send_msg_to_vf = 0x0802, 250 i40e_aqc_opc_send_msg_to_peer = 0x0803, 251 252 /* alternate structure */ 253 i40e_aqc_opc_alternate_write = 0x0900, 254 i40e_aqc_opc_alternate_write_indirect = 0x0901, 255 i40e_aqc_opc_alternate_read = 0x0902, 256 i40e_aqc_opc_alternate_read_indirect = 0x0903, 257 i40e_aqc_opc_alternate_write_done = 0x0904, 258 i40e_aqc_opc_alternate_set_mode = 0x0905, 259 i40e_aqc_opc_alternate_clear_port = 0x0906, 260 261 /* LLDP commands */ 262 i40e_aqc_opc_lldp_get_mib = 0x0A00, 263 i40e_aqc_opc_lldp_update_mib = 0x0A01, 264 i40e_aqc_opc_lldp_add_tlv = 0x0A02, 265 i40e_aqc_opc_lldp_update_tlv = 0x0A03, 266 i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 267 i40e_aqc_opc_lldp_stop = 0x0A05, 268 i40e_aqc_opc_lldp_start = 0x0A06, 269 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, 270 i40e_aqc_opc_lldp_set_local_mib = 0x0A08, 271 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, 272 273 /* Tunnel commands */ 274 i40e_aqc_opc_add_udp_tunnel = 0x0B00, 275 i40e_aqc_opc_del_udp_tunnel = 0x0B01, 276 #ifdef X722_SUPPORT 277 i40e_aqc_opc_set_rss_key = 0x0B02, 278 i40e_aqc_opc_set_rss_lut = 0x0B03, 279 i40e_aqc_opc_get_rss_key = 0x0B04, 280 i40e_aqc_opc_get_rss_lut = 0x0B05, 281 #endif 282 283 /* Async Events */ 284 i40e_aqc_opc_event_lan_overflow = 0x1001, 285 286 /* OEM commands */ 287 i40e_aqc_opc_oem_parameter_change = 0xFE00, 288 i40e_aqc_opc_oem_device_status_change = 0xFE01, 289 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, 290 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, 291 292 /* debug commands */ 293 i40e_aqc_opc_debug_read_reg = 0xFF03, 294 i40e_aqc_opc_debug_write_reg = 0xFF04, 295 i40e_aqc_opc_debug_modify_reg = 0xFF07, 296 i40e_aqc_opc_debug_dump_internals = 0xFF08, 297 }; 298 299 /* command structures and indirect data structures */ 300 301 /* Structure naming conventions: 302 * - no suffix for direct command descriptor structures 303 * - _data for indirect sent data 304 * - _resp for indirect return data (data which is both will use _data) 305 * - _completion for direct return data 306 * - _element_ for repeated elements (may also be _data or _resp) 307 * 308 * Command structures are expected to overlay the params.raw member of the basic 309 * descriptor, and as such cannot exceed 16 bytes in length. 310 */ 311 312 /* This macro is used to generate a compilation error if a structure 313 * is not exactly the correct length. It gives a divide by zero error if the 314 * structure is not of the correct size, otherwise it creates an enum that is 315 * never used. 316 */ 317 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 318 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 319 320 /* This macro is used extensively to ensure that command structures are 16 321 * bytes in length as they have to map to the raw array of that size. 322 */ 323 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 324 325 /* internal (0x00XX) commands */ 326 327 /* Get version (direct 0x0001) */ 328 struct i40e_aqc_get_version { 329 __le32 rom_ver; 330 __le32 fw_build; 331 __le16 fw_major; 332 __le16 fw_minor; 333 __le16 api_major; 334 __le16 api_minor; 335 }; 336 337 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 338 339 /* Send driver version (indirect 0x0002) */ 340 struct i40e_aqc_driver_version { 341 u8 driver_major_ver; 342 u8 driver_minor_ver; 343 u8 driver_build_ver; 344 u8 driver_subbuild_ver; 345 u8 reserved[4]; 346 __le32 address_high; 347 __le32 address_low; 348 }; 349 350 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 351 352 /* Queue Shutdown (direct 0x0003) */ 353 struct i40e_aqc_queue_shutdown { 354 __le32 driver_unloading; 355 #define I40E_AQ_DRIVER_UNLOADING 0x1 356 u8 reserved[12]; 357 }; 358 359 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 360 361 /* Set PF context (0x0004, direct) */ 362 struct i40e_aqc_set_pf_context { 363 u8 pf_id; 364 u8 reserved[15]; 365 }; 366 367 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 368 369 /* Request resource ownership (direct 0x0008) 370 * Release resource ownership (direct 0x0009) 371 */ 372 #define I40E_AQ_RESOURCE_NVM 1 373 #define I40E_AQ_RESOURCE_SDP 2 374 #define I40E_AQ_RESOURCE_ACCESS_READ 1 375 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2 376 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 377 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 378 379 struct i40e_aqc_request_resource { 380 __le16 resource_id; 381 __le16 access_type; 382 __le32 timeout; 383 __le32 resource_number; 384 u8 reserved[4]; 385 }; 386 387 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 388 389 /* Get function capabilities (indirect 0x000A) 390 * Get device capabilities (indirect 0x000B) 391 */ 392 struct i40e_aqc_list_capabilites { 393 u8 command_flags; 394 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 395 u8 pf_index; 396 u8 reserved[2]; 397 __le32 count; 398 __le32 addr_high; 399 __le32 addr_low; 400 }; 401 402 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 403 404 struct i40e_aqc_list_capabilities_element_resp { 405 __le16 id; 406 u8 major_rev; 407 u8 minor_rev; 408 __le32 number; 409 __le32 logical_id; 410 __le32 phys_id; 411 u8 reserved[16]; 412 }; 413 414 /* list of caps */ 415 416 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 417 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002 418 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 419 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 420 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 421 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 422 #define I40E_AQ_CAP_ID_SRIOV 0x0012 423 #define I40E_AQ_CAP_ID_VF 0x0013 424 #define I40E_AQ_CAP_ID_VMDQ 0x0014 425 #define I40E_AQ_CAP_ID_8021QBG 0x0015 426 #define I40E_AQ_CAP_ID_8021QBR 0x0016 427 #define I40E_AQ_CAP_ID_VSI 0x0017 428 #define I40E_AQ_CAP_ID_DCB 0x0018 429 #define I40E_AQ_CAP_ID_FCOE 0x0021 430 #define I40E_AQ_CAP_ID_ISCSI 0x0022 431 #define I40E_AQ_CAP_ID_RSS 0x0040 432 #define I40E_AQ_CAP_ID_RXQ 0x0041 433 #define I40E_AQ_CAP_ID_TXQ 0x0042 434 #define I40E_AQ_CAP_ID_MSIX 0x0043 435 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044 436 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 437 #define I40E_AQ_CAP_ID_1588 0x0046 438 #define I40E_AQ_CAP_ID_IWARP 0x0051 439 #define I40E_AQ_CAP_ID_LED 0x0061 440 #define I40E_AQ_CAP_ID_SDP 0x0062 441 #define I40E_AQ_CAP_ID_MDIO 0x0063 442 #define I40E_AQ_CAP_ID_FLEX10 0x00F1 443 #define I40E_AQ_CAP_ID_CEM 0x00F2 444 445 /* Set CPPM Configuration (direct 0x0103) */ 446 struct i40e_aqc_cppm_configuration { 447 __le16 command_flags; 448 #define I40E_AQ_CPPM_EN_LTRC 0x0800 449 #define I40E_AQ_CPPM_EN_DMCTH 0x1000 450 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000 451 #define I40E_AQ_CPPM_EN_HPTC 0x4000 452 #define I40E_AQ_CPPM_EN_DMARC 0x8000 453 __le16 ttlx; 454 __le32 dmacr; 455 __le16 dmcth; 456 u8 hptc; 457 u8 reserved; 458 __le32 pfltrc; 459 }; 460 461 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 462 463 /* Set ARP Proxy command / response (indirect 0x0104) */ 464 struct i40e_aqc_arp_proxy_data { 465 __le16 command_flags; 466 #define I40E_AQ_ARP_INIT_IPV4 0x0008 467 #define I40E_AQ_ARP_UNSUP_CTL 0x0010 468 #define I40E_AQ_ARP_ENA 0x0020 469 #define I40E_AQ_ARP_ADD_IPV4 0x0040 470 #define I40E_AQ_ARP_DEL_IPV4 0x0080 471 __le16 table_id; 472 __le32 pfpm_proxyfc; 473 __le32 ip_addr; 474 u8 mac_addr[6]; 475 u8 reserved[2]; 476 }; 477 478 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); 479 480 /* Set NS Proxy Table Entry Command (indirect 0x0105) */ 481 struct i40e_aqc_ns_proxy_data { 482 __le16 table_idx_mac_addr_0; 483 __le16 table_idx_mac_addr_1; 484 __le16 table_idx_ipv6_0; 485 __le16 table_idx_ipv6_1; 486 __le16 control; 487 #define I40E_AQ_NS_PROXY_ADD_0 0x0100 488 #define I40E_AQ_NS_PROXY_DEL_0 0x0200 489 #define I40E_AQ_NS_PROXY_ADD_1 0x0400 490 #define I40E_AQ_NS_PROXY_DEL_1 0x0800 491 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000 492 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000 493 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000 494 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000 495 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001 496 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002 497 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004 498 u8 mac_addr_0[6]; 499 u8 mac_addr_1[6]; 500 u8 local_mac_addr[6]; 501 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 502 u8 ipv6_addr_1[16]; 503 }; 504 505 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); 506 507 /* Manage LAA Command (0x0106) - obsolete */ 508 struct i40e_aqc_mng_laa { 509 __le16 command_flags; 510 #define I40E_AQ_LAA_FLAG_WR 0x8000 511 u8 reserved[2]; 512 __le32 sal; 513 __le16 sah; 514 u8 reserved2[6]; 515 }; 516 517 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); 518 519 /* Manage MAC Address Read Command (indirect 0x0107) */ 520 struct i40e_aqc_mac_address_read { 521 __le16 command_flags; 522 #define I40E_AQC_LAN_ADDR_VALID 0x10 523 #define I40E_AQC_SAN_ADDR_VALID 0x20 524 #define I40E_AQC_PORT_ADDR_VALID 0x40 525 #define I40E_AQC_WOL_ADDR_VALID 0x80 526 #define I40E_AQC_MC_MAG_EN_VALID 0x100 527 #define I40E_AQC_ADDR_VALID_MASK 0x1F0 528 u8 reserved[6]; 529 __le32 addr_high; 530 __le32 addr_low; 531 }; 532 533 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 534 535 struct i40e_aqc_mac_address_read_data { 536 u8 pf_lan_mac[6]; 537 u8 pf_san_mac[6]; 538 u8 port_mac[6]; 539 u8 pf_wol_mac[6]; 540 }; 541 542 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 543 544 /* Manage MAC Address Write Command (0x0108) */ 545 struct i40e_aqc_mac_address_write { 546 __le16 command_flags; 547 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 548 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 549 #define I40E_AQC_WRITE_TYPE_PORT 0x8000 550 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 551 #define I40E_AQC_WRITE_TYPE_MASK 0xC000 552 553 __le16 mac_sah; 554 __le32 mac_sal; 555 u8 reserved[8]; 556 }; 557 558 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 559 560 /* PXE commands (0x011x) */ 561 562 /* Clear PXE Command and response (direct 0x0110) */ 563 struct i40e_aqc_clear_pxe { 564 u8 rx_cnt; 565 u8 reserved[15]; 566 }; 567 568 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 569 570 /* Switch configuration commands (0x02xx) */ 571 572 /* Used by many indirect commands that only pass an seid and a buffer in the 573 * command 574 */ 575 struct i40e_aqc_switch_seid { 576 __le16 seid; 577 u8 reserved[6]; 578 __le32 addr_high; 579 __le32 addr_low; 580 }; 581 582 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 583 584 /* Get Switch Configuration command (indirect 0x0200) 585 * uses i40e_aqc_switch_seid for the descriptor 586 */ 587 struct i40e_aqc_get_switch_config_header_resp { 588 __le16 num_reported; 589 __le16 num_total; 590 u8 reserved[12]; 591 }; 592 593 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); 594 595 struct i40e_aqc_switch_config_element_resp { 596 u8 element_type; 597 #define I40E_AQ_SW_ELEM_TYPE_MAC 1 598 #define I40E_AQ_SW_ELEM_TYPE_PF 2 599 #define I40E_AQ_SW_ELEM_TYPE_VF 3 600 #define I40E_AQ_SW_ELEM_TYPE_EMP 4 601 #define I40E_AQ_SW_ELEM_TYPE_BMC 5 602 #define I40E_AQ_SW_ELEM_TYPE_PV 16 603 #define I40E_AQ_SW_ELEM_TYPE_VEB 17 604 #define I40E_AQ_SW_ELEM_TYPE_PA 18 605 #define I40E_AQ_SW_ELEM_TYPE_VSI 19 606 u8 revision; 607 #define I40E_AQ_SW_ELEM_REV_1 1 608 __le16 seid; 609 __le16 uplink_seid; 610 __le16 downlink_seid; 611 u8 reserved[3]; 612 u8 connection_type; 613 #define I40E_AQ_CONN_TYPE_REGULAR 0x1 614 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2 615 #define I40E_AQ_CONN_TYPE_CASCADED 0x3 616 __le16 scheduler_id; 617 __le16 element_info; 618 }; 619 620 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); 621 622 /* Get Switch Configuration (indirect 0x0200) 623 * an array of elements are returned in the response buffer 624 * the first in the array is the header, remainder are elements 625 */ 626 struct i40e_aqc_get_switch_config_resp { 627 struct i40e_aqc_get_switch_config_header_resp header; 628 struct i40e_aqc_switch_config_element_resp element[1]; 629 }; 630 631 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); 632 633 /* Add Statistics (direct 0x0201) 634 * Remove Statistics (direct 0x0202) 635 */ 636 struct i40e_aqc_add_remove_statistics { 637 __le16 seid; 638 __le16 vlan; 639 __le16 stat_index; 640 u8 reserved[10]; 641 }; 642 643 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 644 645 /* Set Port Parameters command (direct 0x0203) */ 646 struct i40e_aqc_set_port_parameters { 647 __le16 command_flags; 648 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 649 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 650 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 651 __le16 bad_frame_vsi; 652 __le16 default_seid; /* reserved for command */ 653 u8 reserved[10]; 654 }; 655 656 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 657 658 /* Get Switch Resource Allocation (indirect 0x0204) */ 659 struct i40e_aqc_get_switch_resource_alloc { 660 u8 num_entries; /* reserved for command */ 661 u8 reserved[7]; 662 __le32 addr_high; 663 __le32 addr_low; 664 }; 665 666 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 667 668 /* expect an array of these structs in the response buffer */ 669 struct i40e_aqc_switch_resource_alloc_element_resp { 670 u8 resource_type; 671 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0 672 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1 673 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 674 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3 675 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 676 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 677 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 678 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 679 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 680 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 681 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 682 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 683 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 684 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 685 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 686 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 687 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 688 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 689 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 690 u8 reserved1; 691 __le16 guaranteed; 692 __le16 total; 693 __le16 used; 694 __le16 total_unalloced; 695 u8 reserved2[6]; 696 }; 697 698 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); 699 700 /* Read Receive control registers (direct 0x0206) 701 * Write Receive control registers (direct 0x0207) 702 * used for accessing Rx control registers that can be 703 * slow and need special handling when under high Rx load 704 */ 705 struct i40e_aqc_rx_ctl_reg_read_write { 706 __le32 reserved1; 707 __le32 address; 708 __le32 reserved2; 709 __le32 value; 710 }; 711 712 I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write); 713 714 /* Add VSI (indirect 0x0210) 715 * this indirect command uses struct i40e_aqc_vsi_properties_data 716 * as the indirect buffer (128 bytes) 717 * 718 * Update VSI (indirect 0x211) 719 * uses the same data structure as Add VSI 720 * 721 * Get VSI (indirect 0x0212) 722 * uses the same completion and data structure as Add VSI 723 */ 724 struct i40e_aqc_add_get_update_vsi { 725 __le16 uplink_seid; 726 u8 connection_type; 727 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 728 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 729 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 730 u8 reserved1; 731 u8 vf_id; 732 u8 reserved2; 733 __le16 vsi_flags; 734 #define I40E_AQ_VSI_TYPE_SHIFT 0x0 735 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 736 #define I40E_AQ_VSI_TYPE_VF 0x0 737 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1 738 #define I40E_AQ_VSI_TYPE_PF 0x2 739 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 740 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 741 __le32 addr_high; 742 __le32 addr_low; 743 }; 744 745 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 746 747 struct i40e_aqc_add_get_update_vsi_completion { 748 __le16 seid; 749 __le16 vsi_number; 750 __le16 vsi_used; 751 __le16 vsi_free; 752 __le32 addr_high; 753 __le32 addr_low; 754 }; 755 756 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 757 758 struct i40e_aqc_vsi_properties_data { 759 /* first 96 byte are written by SW */ 760 __le16 valid_sections; 761 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 762 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 763 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 764 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 765 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 766 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 767 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 768 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 769 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 770 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 771 /* switch section */ 772 __le16 switch_id; /* 12bit id combined with flags below */ 773 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 774 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 775 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 776 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 777 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 778 u8 sw_reserved[2]; 779 /* security section */ 780 u8 sec_flags; 781 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 782 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 783 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 784 u8 sec_reserved; 785 /* VLAN section */ 786 __le16 pvid; /* VLANS include priority bits */ 787 __le16 fcoe_pvid; 788 u8 port_vlan_flags; 789 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 790 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 791 I40E_AQ_VSI_PVLAN_MODE_SHIFT) 792 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 793 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 794 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 795 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 796 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 797 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 798 I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 799 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 800 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 801 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 802 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 803 u8 pvlan_reserved[3]; 804 /* ingress egress up sections */ 805 __le32 ingress_table; /* bitmap, 3 bits per up */ 806 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 807 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 808 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 809 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 810 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 811 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 812 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 813 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 814 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 815 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 816 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 817 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 818 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 819 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 820 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 821 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 822 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 823 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 824 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 825 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 826 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 827 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 828 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 829 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 830 __le32 egress_table; /* same defines as for ingress table */ 831 /* cascaded PV section */ 832 __le16 cas_pv_tag; 833 u8 cas_pv_flags; 834 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 835 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 836 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 837 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 838 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 839 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 840 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 841 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 842 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 843 u8 cas_pv_reserved; 844 /* queue mapping section */ 845 __le16 mapping_flags; 846 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 847 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 848 __le16 queue_mapping[16]; 849 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0 850 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 851 __le16 tc_mapping[8]; 852 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 853 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 854 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 855 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 856 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 857 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 858 #define I40E_AQ_VSI_TC_QUE_SIZE_MAX (1 << 0x6) 859 /* queueing option section */ 860 u8 queueing_opt_flags; 861 #ifdef X722_SUPPORT 862 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04 863 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08 864 #endif 865 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 866 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 867 #ifdef X722_SUPPORT 868 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00 869 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40 870 #endif 871 u8 queueing_opt_reserved[3]; 872 /* scheduler section */ 873 u8 up_enable_bits; 874 u8 sched_reserved; 875 /* outer up section */ 876 __le32 outer_up_table; /* same structure and defines as ingress table */ 877 u8 cmd_reserved[8]; 878 /* last 32 bytes are written by FW */ 879 __le16 qs_handle[8]; 880 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 881 __le16 stat_counter_idx; 882 __le16 sched_id; 883 u8 resp_reserved[12]; 884 }; 885 886 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 887 888 /* Add Port Virtualizer (direct 0x0220) 889 * also used for update PV (direct 0x0221) but only flags are used 890 * (IS_CTRL_PORT only works on add PV) 891 */ 892 struct i40e_aqc_add_update_pv { 893 __le16 command_flags; 894 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1 895 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 896 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 897 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 898 __le16 uplink_seid; 899 __le16 connected_seid; 900 u8 reserved[10]; 901 }; 902 903 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 904 905 struct i40e_aqc_add_update_pv_completion { 906 /* reserved for update; for add also encodes error if rc == ENOSPC */ 907 __le16 pv_seid; 908 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 909 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 910 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 911 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 912 u8 reserved[14]; 913 }; 914 915 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 916 917 /* Get PV Params (direct 0x0222) 918 * uses i40e_aqc_switch_seid for the descriptor 919 */ 920 921 struct i40e_aqc_get_pv_params_completion { 922 __le16 seid; 923 __le16 default_stag; 924 __le16 pv_flags; /* same flags as add_pv */ 925 #define I40E_AQC_GET_PV_PV_TYPE 0x1 926 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 927 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 928 u8 reserved[8]; 929 __le16 default_port_seid; 930 }; 931 932 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 933 934 /* Add VEB (direct 0x0230) */ 935 struct i40e_aqc_add_veb { 936 __le16 uplink_seid; 937 __le16 downlink_seid; 938 __le16 veb_flags; 939 #define I40E_AQC_ADD_VEB_FLOATING 0x1 940 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 941 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 942 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 943 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 944 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 945 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 946 u8 enable_tcs; 947 u8 reserved[9]; 948 }; 949 950 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 951 952 struct i40e_aqc_add_veb_completion { 953 u8 reserved[6]; 954 __le16 switch_seid; 955 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 956 __le16 veb_seid; 957 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 958 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 959 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 960 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 961 __le16 statistic_index; 962 __le16 vebs_used; 963 __le16 vebs_free; 964 }; 965 966 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 967 968 /* Get VEB Parameters (direct 0x0232) 969 * uses i40e_aqc_switch_seid for the descriptor 970 */ 971 struct i40e_aqc_get_veb_parameters_completion { 972 __le16 seid; 973 __le16 switch_id; 974 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 975 __le16 statistic_index; 976 __le16 vebs_used; 977 __le16 vebs_free; 978 u8 reserved[4]; 979 }; 980 981 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 982 983 /* Delete Element (direct 0x0243) 984 * uses the generic i40e_aqc_switch_seid 985 */ 986 987 /* Add MAC-VLAN (indirect 0x0250) */ 988 989 /* used for the command for most vlan commands */ 990 struct i40e_aqc_macvlan { 991 __le16 num_addresses; 992 __le16 seid[3]; 993 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 994 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 995 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 996 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 997 __le32 addr_high; 998 __le32 addr_low; 999 }; 1000 1001 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 1002 1003 /* indirect data for command and response */ 1004 struct i40e_aqc_add_macvlan_element_data { 1005 u8 mac_addr[6]; 1006 __le16 vlan_tag; 1007 __le16 flags; 1008 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 1009 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 1010 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 1011 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 1012 __le16 queue_number; 1013 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 1014 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 1015 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1016 /* response section */ 1017 u8 match_method; 1018 #define I40E_AQC_MM_PERFECT_MATCH 0x01 1019 #define I40E_AQC_MM_HASH_MATCH 0x02 1020 #define I40E_AQC_MM_ERR_NO_RES 0xFF 1021 u8 reserved1[3]; 1022 }; 1023 1024 struct i40e_aqc_add_remove_macvlan_completion { 1025 __le16 perfect_mac_used; 1026 __le16 perfect_mac_free; 1027 __le16 unicast_hash_free; 1028 __le16 multicast_hash_free; 1029 __le32 addr_high; 1030 __le32 addr_low; 1031 }; 1032 1033 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 1034 1035 /* Remove MAC-VLAN (indirect 0x0251) 1036 * uses i40e_aqc_macvlan for the descriptor 1037 * data points to an array of num_addresses of elements 1038 */ 1039 1040 struct i40e_aqc_remove_macvlan_element_data { 1041 u8 mac_addr[6]; 1042 __le16 vlan_tag; 1043 u8 flags; 1044 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 1045 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 1046 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 1047 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 1048 u8 reserved[3]; 1049 /* reply section */ 1050 u8 error_code; 1051 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 1052 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 1053 u8 reply_reserved[3]; 1054 }; 1055 1056 /* Add VLAN (indirect 0x0252) 1057 * Remove VLAN (indirect 0x0253) 1058 * use the generic i40e_aqc_macvlan for the command 1059 */ 1060 struct i40e_aqc_add_remove_vlan_element_data { 1061 __le16 vlan_tag; 1062 u8 vlan_flags; 1063 /* flags for add VLAN */ 1064 #define I40E_AQC_ADD_VLAN_LOCAL 0x1 1065 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1066 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1067 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1068 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1069 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1070 #define I40E_AQC_VLAN_PTYPE_SHIFT 3 1071 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1072 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1073 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1074 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1075 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1076 /* flags for remove VLAN */ 1077 #define I40E_AQC_REMOVE_VLAN_ALL 0x1 1078 u8 reserved; 1079 u8 result; 1080 /* flags for add VLAN */ 1081 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1082 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1083 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1084 /* flags for remove VLAN */ 1085 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1086 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1087 u8 reserved1[3]; 1088 }; 1089 1090 struct i40e_aqc_add_remove_vlan_completion { 1091 u8 reserved[4]; 1092 __le16 vlans_used; 1093 __le16 vlans_free; 1094 __le32 addr_high; 1095 __le32 addr_low; 1096 }; 1097 1098 /* Set VSI Promiscuous Modes (direct 0x0254) */ 1099 struct i40e_aqc_set_vsi_promiscuous_modes { 1100 __le16 promiscuous_flags; 1101 __le16 valid_flags; 1102 /* flags used for both fields above */ 1103 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1104 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1105 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1106 #define I40E_AQC_SET_VSI_DEFAULT 0x08 1107 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1108 __le16 seid; 1109 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1110 __le16 vlan_tag; 1111 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF 1112 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1113 u8 reserved[8]; 1114 }; 1115 1116 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1117 1118 /* Add S/E-tag command (direct 0x0255) 1119 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1120 */ 1121 struct i40e_aqc_add_tag { 1122 __le16 flags; 1123 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1124 __le16 seid; 1125 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1126 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1127 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1128 __le16 tag; 1129 __le16 queue_number; 1130 u8 reserved[8]; 1131 }; 1132 1133 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1134 1135 struct i40e_aqc_add_remove_tag_completion { 1136 u8 reserved[12]; 1137 __le16 tags_used; 1138 __le16 tags_free; 1139 }; 1140 1141 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1142 1143 /* Remove S/E-tag command (direct 0x0256) 1144 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1145 */ 1146 struct i40e_aqc_remove_tag { 1147 __le16 seid; 1148 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1149 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1150 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1151 __le16 tag; 1152 u8 reserved[12]; 1153 }; 1154 1155 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); 1156 1157 /* Add multicast E-Tag (direct 0x0257) 1158 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1159 * and no external data 1160 */ 1161 struct i40e_aqc_add_remove_mcast_etag { 1162 __le16 pv_seid; 1163 __le16 etag; 1164 u8 num_unicast_etags; 1165 u8 reserved[3]; 1166 __le32 addr_high; /* address of array of 2-byte s-tags */ 1167 __le32 addr_low; 1168 }; 1169 1170 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1171 1172 struct i40e_aqc_add_remove_mcast_etag_completion { 1173 u8 reserved[4]; 1174 __le16 mcast_etags_used; 1175 __le16 mcast_etags_free; 1176 __le32 addr_high; 1177 __le32 addr_low; 1178 1179 }; 1180 1181 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1182 1183 /* Update S/E-Tag (direct 0x0259) */ 1184 struct i40e_aqc_update_tag { 1185 __le16 seid; 1186 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1187 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1188 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1189 __le16 old_tag; 1190 __le16 new_tag; 1191 u8 reserved[10]; 1192 }; 1193 1194 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1195 1196 struct i40e_aqc_update_tag_completion { 1197 u8 reserved[12]; 1198 __le16 tags_used; 1199 __le16 tags_free; 1200 }; 1201 1202 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1203 1204 /* Add Control Packet filter (direct 0x025A) 1205 * Remove Control Packet filter (direct 0x025B) 1206 * uses the i40e_aqc_add_oveb_cloud, 1207 * and the generic direct completion structure 1208 */ 1209 struct i40e_aqc_add_remove_control_packet_filter { 1210 u8 mac[6]; 1211 __le16 etype; 1212 __le16 flags; 1213 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1214 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1215 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1216 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1217 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1218 __le16 seid; 1219 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1220 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1221 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1222 __le16 queue; 1223 u8 reserved[2]; 1224 }; 1225 1226 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1227 1228 struct i40e_aqc_add_remove_control_packet_filter_completion { 1229 __le16 mac_etype_used; 1230 __le16 etype_used; 1231 __le16 mac_etype_free; 1232 __le16 etype_free; 1233 u8 reserved[8]; 1234 }; 1235 1236 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1237 1238 /* Add Cloud filters (indirect 0x025C) 1239 * Remove Cloud filters (indirect 0x025D) 1240 * uses the i40e_aqc_add_remove_cloud_filters, 1241 * and the generic indirect completion structure 1242 */ 1243 struct i40e_aqc_add_remove_cloud_filters { 1244 u8 num_filters; 1245 u8 reserved; 1246 __le16 seid; 1247 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1248 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1249 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1250 u8 reserved2[4]; 1251 __le32 addr_high; 1252 __le32 addr_low; 1253 }; 1254 1255 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1256 1257 struct i40e_aqc_add_remove_cloud_filters_element_data { 1258 u8 outer_mac[6]; 1259 u8 inner_mac[6]; 1260 __le16 inner_vlan; 1261 union { 1262 struct { 1263 u8 reserved[12]; 1264 u8 data[4]; 1265 } v4; 1266 struct { 1267 u8 data[16]; 1268 } v6; 1269 } ipaddr; 1270 __le16 flags; 1271 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1272 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1273 I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1274 /* 0x0000 reserved */ 1275 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 1276 /* 0x0002 reserved */ 1277 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1278 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1279 /* 0x0005 reserved */ 1280 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1281 /* 0x0007 reserved */ 1282 /* 0x0008 reserved */ 1283 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1284 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1285 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1286 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1287 1288 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1289 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1290 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1291 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1292 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1293 1294 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1295 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1296 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN 0 1297 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1298 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NGE 2 1299 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1300 1301 __le32 tenant_id; 1302 u8 reserved[4]; 1303 __le16 queue_number; 1304 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1305 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 1306 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1307 u8 reserved2[14]; 1308 /* response section */ 1309 u8 allocation_result; 1310 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1311 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1312 u8 response_reserved[7]; 1313 }; 1314 1315 struct i40e_aqc_remove_cloud_filters_completion { 1316 __le16 perfect_ovlan_used; 1317 __le16 perfect_ovlan_free; 1318 __le16 vlan_used; 1319 __le16 vlan_free; 1320 __le32 addr_high; 1321 __le32 addr_low; 1322 }; 1323 1324 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1325 1326 /* Add Mirror Rule (indirect or direct 0x0260) 1327 * Delete Mirror Rule (indirect or direct 0x0261) 1328 * note: some rule types (4,5) do not use an external buffer. 1329 * take care to set the flags correctly. 1330 */ 1331 struct i40e_aqc_add_delete_mirror_rule { 1332 __le16 seid; 1333 __le16 rule_type; 1334 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1335 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1336 I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1337 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1338 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1339 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1340 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1341 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1342 __le16 num_entries; 1343 __le16 destination; /* VSI for add, rule id for delete */ 1344 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1345 __le32 addr_low; 1346 }; 1347 1348 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1349 1350 struct i40e_aqc_add_delete_mirror_rule_completion { 1351 u8 reserved[2]; 1352 __le16 rule_id; /* only used on add */ 1353 __le16 mirror_rules_used; 1354 __le16 mirror_rules_free; 1355 __le32 addr_high; 1356 __le32 addr_low; 1357 }; 1358 1359 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1360 1361 /* DCB 0x03xx*/ 1362 1363 /* PFC Ignore (direct 0x0301) 1364 * the command and response use the same descriptor structure 1365 */ 1366 struct i40e_aqc_pfc_ignore { 1367 u8 tc_bitmap; 1368 u8 command_flags; /* unused on response */ 1369 #define I40E_AQC_PFC_IGNORE_SET 0x80 1370 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1371 u8 reserved[14]; 1372 }; 1373 1374 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1375 1376 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1377 * with no parameters 1378 */ 1379 1380 /* TX scheduler 0x04xx */ 1381 1382 /* Almost all the indirect commands use 1383 * this generic struct to pass the SEID in param0 1384 */ 1385 struct i40e_aqc_tx_sched_ind { 1386 __le16 vsi_seid; 1387 u8 reserved[6]; 1388 __le32 addr_high; 1389 __le32 addr_low; 1390 }; 1391 1392 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1393 1394 /* Several commands respond with a set of queue set handles */ 1395 struct i40e_aqc_qs_handles_resp { 1396 __le16 qs_handles[8]; 1397 }; 1398 1399 /* Configure VSI BW limits (direct 0x0400) */ 1400 struct i40e_aqc_configure_vsi_bw_limit { 1401 __le16 vsi_seid; 1402 u8 reserved[2]; 1403 __le16 credit; 1404 u8 reserved1[2]; 1405 u8 max_credit; /* 0-3, limit = 2^max */ 1406 u8 reserved2[7]; 1407 }; 1408 1409 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1410 1411 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1412 * responds with i40e_aqc_qs_handles_resp 1413 */ 1414 struct i40e_aqc_configure_vsi_ets_sla_bw_data { 1415 u8 tc_valid_bits; 1416 u8 reserved[15]; 1417 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1418 1419 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1420 __le16 tc_bw_max[2]; 1421 u8 reserved1[28]; 1422 }; 1423 1424 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); 1425 1426 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1427 * responds with i40e_aqc_qs_handles_resp 1428 */ 1429 struct i40e_aqc_configure_vsi_tc_bw_data { 1430 u8 tc_valid_bits; 1431 u8 reserved[3]; 1432 u8 tc_bw_credits[8]; 1433 u8 reserved1[4]; 1434 __le16 qs_handles[8]; 1435 }; 1436 1437 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); 1438 1439 /* Query vsi bw configuration (indirect 0x0408) */ 1440 struct i40e_aqc_query_vsi_bw_config_resp { 1441 u8 tc_valid_bits; 1442 u8 tc_suspended_bits; 1443 u8 reserved[14]; 1444 __le16 qs_handles[8]; 1445 u8 reserved1[4]; 1446 __le16 port_bw_limit; 1447 u8 reserved2[2]; 1448 u8 max_bw; /* 0-3, limit = 2^max */ 1449 u8 reserved3[23]; 1450 }; 1451 1452 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); 1453 1454 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1455 struct i40e_aqc_query_vsi_ets_sla_config_resp { 1456 u8 tc_valid_bits; 1457 u8 reserved[3]; 1458 u8 share_credits[8]; 1459 __le16 credits[8]; 1460 1461 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1462 __le16 tc_bw_max[2]; 1463 }; 1464 1465 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); 1466 1467 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1468 struct i40e_aqc_configure_switching_comp_bw_limit { 1469 __le16 seid; 1470 u8 reserved[2]; 1471 __le16 credit; 1472 u8 reserved1[2]; 1473 u8 max_bw; /* 0-3, limit = 2^max */ 1474 u8 reserved2[7]; 1475 }; 1476 1477 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1478 1479 /* Enable Physical Port ETS (indirect 0x0413) 1480 * Modify Physical Port ETS (indirect 0x0414) 1481 * Disable Physical Port ETS (indirect 0x0415) 1482 */ 1483 struct i40e_aqc_configure_switching_comp_ets_data { 1484 u8 reserved[4]; 1485 u8 tc_valid_bits; 1486 u8 seepage; 1487 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1488 u8 tc_strict_priority_flags; 1489 u8 reserved1[17]; 1490 u8 tc_bw_share_credits[8]; 1491 u8 reserved2[96]; 1492 }; 1493 1494 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); 1495 1496 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1497 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1498 u8 tc_valid_bits; 1499 u8 reserved[15]; 1500 __le16 tc_bw_credit[8]; 1501 1502 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1503 __le16 tc_bw_max[2]; 1504 u8 reserved1[28]; 1505 }; 1506 1507 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_switching_comp_ets_bw_limit_data); 1508 1509 /* Configure Switching Component Bandwidth Allocation per Tc 1510 * (indirect 0x0417) 1511 */ 1512 struct i40e_aqc_configure_switching_comp_bw_config_data { 1513 u8 tc_valid_bits; 1514 u8 reserved[2]; 1515 u8 absolute_credits; /* bool */ 1516 u8 tc_bw_share_credits[8]; 1517 u8 reserved1[20]; 1518 }; 1519 1520 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); 1521 1522 /* Query Switching Component Configuration (indirect 0x0418) */ 1523 struct i40e_aqc_query_switching_comp_ets_config_resp { 1524 u8 tc_valid_bits; 1525 u8 reserved[35]; 1526 __le16 port_bw_limit; 1527 u8 reserved1[2]; 1528 u8 tc_bw_max; /* 0-3, limit = 2^max */ 1529 u8 reserved2[23]; 1530 }; 1531 1532 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); 1533 1534 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1535 struct i40e_aqc_query_port_ets_config_resp { 1536 u8 reserved[4]; 1537 u8 tc_valid_bits; 1538 u8 reserved1; 1539 u8 tc_strict_priority_bits; 1540 u8 reserved2; 1541 u8 tc_bw_share_credits[8]; 1542 __le16 tc_bw_limits[8]; 1543 1544 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1545 __le16 tc_bw_max[2]; 1546 u8 reserved3[32]; 1547 }; 1548 1549 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); 1550 1551 /* Query Switching Component Bandwidth Allocation per Traffic Type 1552 * (indirect 0x041A) 1553 */ 1554 struct i40e_aqc_query_switching_comp_bw_config_resp { 1555 u8 tc_valid_bits; 1556 u8 reserved[2]; 1557 u8 absolute_credits_enable; /* bool */ 1558 u8 tc_bw_share_credits[8]; 1559 __le16 tc_bw_limits[8]; 1560 1561 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1562 __le16 tc_bw_max[2]; 1563 }; 1564 1565 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); 1566 1567 /* Suspend/resume port TX traffic 1568 * (direct 0x041B and 0x041C) uses the generic SEID struct 1569 */ 1570 1571 /* Configure partition BW 1572 * (indirect 0x041D) 1573 */ 1574 struct i40e_aqc_configure_partition_bw_data { 1575 __le16 pf_valid_bits; 1576 u8 min_bw[16]; /* guaranteed bandwidth */ 1577 u8 max_bw[16]; /* bandwidth limit */ 1578 }; 1579 1580 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); 1581 1582 /* Get and set the active HMC resource profile and status. 1583 * (direct 0x0500) and (direct 0x0501) 1584 */ 1585 struct i40e_aq_get_set_hmc_resource_profile { 1586 u8 pm_profile; 1587 u8 pe_vf_enabled; 1588 u8 reserved[14]; 1589 }; 1590 1591 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1592 1593 enum i40e_aq_hmc_profile { 1594 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1595 I40E_HMC_PROFILE_DEFAULT = 1, 1596 I40E_HMC_PROFILE_FAVOR_VF = 2, 1597 I40E_HMC_PROFILE_EQUAL = 3, 1598 }; 1599 1600 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF 1601 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F 1602 1603 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1604 1605 /* set in param0 for get phy abilities to report qualified modules */ 1606 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1607 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1608 1609 enum i40e_aq_phy_type { 1610 I40E_PHY_TYPE_SGMII = 0x0, 1611 I40E_PHY_TYPE_1000BASE_KX = 0x1, 1612 I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1613 I40E_PHY_TYPE_10GBASE_KR = 0x3, 1614 I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1615 I40E_PHY_TYPE_XAUI = 0x5, 1616 I40E_PHY_TYPE_XFI = 0x6, 1617 I40E_PHY_TYPE_SFI = 0x7, 1618 I40E_PHY_TYPE_XLAUI = 0x8, 1619 I40E_PHY_TYPE_XLPPI = 0x9, 1620 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1621 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1622 I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1623 I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1624 I40E_PHY_TYPE_100BASE_TX = 0x11, 1625 I40E_PHY_TYPE_1000BASE_T = 0x12, 1626 I40E_PHY_TYPE_10GBASE_T = 0x13, 1627 I40E_PHY_TYPE_10GBASE_SR = 0x14, 1628 I40E_PHY_TYPE_10GBASE_LR = 0x15, 1629 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1630 I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1631 I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1632 I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1633 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1634 I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1635 I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1636 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1637 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1638 I40E_PHY_TYPE_MAX 1639 }; 1640 1641 #define I40E_LINK_SPEED_100MB_SHIFT 0x1 1642 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2 1643 #define I40E_LINK_SPEED_10GB_SHIFT 0x3 1644 #define I40E_LINK_SPEED_40GB_SHIFT 0x4 1645 #define I40E_LINK_SPEED_20GB_SHIFT 0x5 1646 1647 enum i40e_aq_link_speed { 1648 I40E_LINK_SPEED_UNKNOWN = 0, 1649 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), 1650 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), 1651 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), 1652 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), 1653 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT) 1654 }; 1655 1656 struct i40e_aqc_module_desc { 1657 u8 oui[3]; 1658 u8 reserved1; 1659 u8 part_number[16]; 1660 u8 revision[4]; 1661 u8 reserved2[8]; 1662 }; 1663 1664 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); 1665 1666 struct i40e_aq_get_phy_abilities_resp { 1667 __le32 phy_type; /* bitmap using the above enum for offsets */ 1668 u8 link_speed; /* bitmap using the above enum bit patterns */ 1669 u8 abilities; 1670 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 1671 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 1672 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 1673 #define I40E_AQ_PHY_LINK_ENABLED 0x08 1674 #define I40E_AQ_PHY_AN_ENABLED 0x10 1675 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1676 __le16 eee_capability; 1677 #define I40E_AQ_EEE_100BASE_TX 0x0002 1678 #define I40E_AQ_EEE_1000BASE_T 0x0004 1679 #define I40E_AQ_EEE_10GBASE_T 0x0008 1680 #define I40E_AQ_EEE_1000BASE_KX 0x0010 1681 #define I40E_AQ_EEE_10GBASE_KX4 0x0020 1682 #define I40E_AQ_EEE_10GBASE_KR 0x0040 1683 __le32 eeer_val; 1684 u8 d3_lpan; 1685 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 1686 u8 reserved[3]; 1687 u8 phy_id[4]; 1688 u8 module_type[3]; 1689 u8 qualified_module_count; 1690 #define I40E_AQ_PHY_MAX_QMS 16 1691 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 1692 }; 1693 1694 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); 1695 1696 /* Set PHY Config (direct 0x0601) */ 1697 struct i40e_aq_set_phy_config { /* same bits as above in all */ 1698 __le32 phy_type; 1699 u8 link_speed; 1700 u8 abilities; 1701 /* bits 0-2 use the values from get_phy_abilities_resp */ 1702 #define I40E_AQ_PHY_ENABLE_LINK 0x08 1703 #define I40E_AQ_PHY_ENABLE_AN 0x10 1704 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 1705 __le16 eee_capability; 1706 __le32 eeer; 1707 u8 low_power_ctrl; 1708 u8 reserved[3]; 1709 }; 1710 1711 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 1712 1713 /* Set MAC Config command data structure (direct 0x0603) */ 1714 struct i40e_aq_set_mac_config { 1715 __le16 max_frame_size; 1716 u8 params; 1717 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 1718 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 1719 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 1720 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 1721 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 1722 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 1723 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 1724 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 1725 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 1726 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 1727 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 1728 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 1729 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 1730 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 1731 u8 tx_timer_priority; /* bitmap */ 1732 __le16 tx_timer_value; 1733 __le16 fc_refresh_threshold; 1734 u8 reserved[8]; 1735 }; 1736 1737 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 1738 1739 /* Restart Auto-Negotiation (direct 0x605) */ 1740 struct i40e_aqc_set_link_restart_an { 1741 u8 command; 1742 #define I40E_AQ_PHY_RESTART_AN 0x02 1743 #define I40E_AQ_PHY_LINK_ENABLE 0x04 1744 u8 reserved[15]; 1745 }; 1746 1747 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 1748 1749 /* Get Link Status cmd & response data structure (direct 0x0607) */ 1750 struct i40e_aqc_get_link_status { 1751 __le16 command_flags; /* only field set on command */ 1752 #define I40E_AQ_LSE_MASK 0x3 1753 #define I40E_AQ_LSE_NOP 0x0 1754 #define I40E_AQ_LSE_DISABLE 0x2 1755 #define I40E_AQ_LSE_ENABLE 0x3 1756 /* only response uses this flag */ 1757 #define I40E_AQ_LSE_IS_ENABLED 0x1 1758 u8 phy_type; /* i40e_aq_phy_type */ 1759 u8 link_speed; /* i40e_aq_link_speed */ 1760 u8 link_info; 1761 #define I40E_AQ_LINK_UP 0x01 /* obsolete */ 1762 #define I40E_AQ_LINK_UP_FUNCTION 0x01 1763 #define I40E_AQ_LINK_FAULT 0x02 1764 #define I40E_AQ_LINK_FAULT_TX 0x04 1765 #define I40E_AQ_LINK_FAULT_RX 0x08 1766 #define I40E_AQ_LINK_FAULT_REMOTE 0x10 1767 #define I40E_AQ_LINK_UP_PORT 0x20 1768 #define I40E_AQ_MEDIA_AVAILABLE 0x40 1769 #define I40E_AQ_SIGNAL_DETECT 0x80 1770 u8 an_info; 1771 #define I40E_AQ_AN_COMPLETED 0x01 1772 #define I40E_AQ_LP_AN_ABILITY 0x02 1773 #define I40E_AQ_PD_FAULT 0x04 1774 #define I40E_AQ_FEC_EN 0x08 1775 #define I40E_AQ_PHY_LOW_POWER 0x10 1776 #define I40E_AQ_LINK_PAUSE_TX 0x20 1777 #define I40E_AQ_LINK_PAUSE_RX 0x40 1778 #define I40E_AQ_QUALIFIED_MODULE 0x80 1779 u8 ext_info; 1780 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 1781 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 1782 #define I40E_AQ_LINK_TX_SHIFT 0x02 1783 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 1784 #define I40E_AQ_LINK_TX_ACTIVE 0x00 1785 #define I40E_AQ_LINK_TX_DRAINED 0x01 1786 #define I40E_AQ_LINK_TX_FLUSHED 0x03 1787 #define I40E_AQ_LINK_FORCED_40G 0x10 1788 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 1789 __le16 max_frame_size; 1790 u8 config; 1791 #define I40E_AQ_CONFIG_CRC_ENA 0x04 1792 #define I40E_AQ_CONFIG_PACING_MASK 0x78 1793 u8 reserved[5]; 1794 }; 1795 1796 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 1797 1798 /* Set event mask command (direct 0x613) */ 1799 struct i40e_aqc_set_phy_int_mask { 1800 u8 reserved[8]; 1801 __le16 event_mask; 1802 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 1803 #define I40E_AQ_EVENT_MEDIA_NA 0x0004 1804 #define I40E_AQ_EVENT_LINK_FAULT 0x0008 1805 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 1806 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 1807 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 1808 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080 1809 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 1810 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 1811 u8 reserved1[6]; 1812 }; 1813 1814 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 1815 1816 /* Get Local AN advt register (direct 0x0614) 1817 * Set Local AN advt register (direct 0x0615) 1818 * Get Link Partner AN advt register (direct 0x0616) 1819 */ 1820 struct i40e_aqc_an_advt_reg { 1821 __le32 local_an_reg0; 1822 __le16 local_an_reg1; 1823 u8 reserved[10]; 1824 }; 1825 1826 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 1827 1828 /* Set Loopback mode (0x0618) */ 1829 struct i40e_aqc_set_lb_mode { 1830 __le16 lb_mode; 1831 #define I40E_AQ_LB_PHY_LOCAL 0x01 1832 #define I40E_AQ_LB_PHY_REMOTE 0x02 1833 #define I40E_AQ_LB_MAC_LOCAL 0x04 1834 u8 reserved[14]; 1835 }; 1836 1837 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 1838 1839 /* Set PHY Debug command (0x0622) */ 1840 struct i40e_aqc_set_phy_debug { 1841 u8 command_flags; 1842 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 1843 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 1844 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 1845 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 1846 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 1847 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 1848 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 1849 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 1850 u8 reserved[15]; 1851 }; 1852 1853 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 1854 1855 enum i40e_aq_phy_reg_type { 1856 I40E_AQC_PHY_REG_INTERNAL = 0x1, 1857 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 1858 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 1859 }; 1860 1861 /* NVM Read command (indirect 0x0701) 1862 * NVM Erase commands (direct 0x0702) 1863 * NVM Update commands (indirect 0x0703) 1864 */ 1865 struct i40e_aqc_nvm_update { 1866 u8 command_flags; 1867 #define I40E_AQ_NVM_LAST_CMD 0x01 1868 #define I40E_AQ_NVM_FLASH_ONLY 0x80 1869 u8 module_pointer; 1870 __le16 length; 1871 __le32 offset; 1872 __le32 addr_high; 1873 __le32 addr_low; 1874 }; 1875 1876 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 1877 1878 /* NVM Config Read (indirect 0x0704) */ 1879 struct i40e_aqc_nvm_config_read { 1880 __le16 cmd_flags; 1881 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 1882 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 1883 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 1884 __le16 element_count; 1885 __le16 element_id; /* Feature/field ID */ 1886 __le16 element_id_msw; /* MSWord of field ID */ 1887 __le32 address_high; 1888 __le32 address_low; 1889 }; 1890 1891 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 1892 1893 /* NVM Config Write (indirect 0x0705) */ 1894 struct i40e_aqc_nvm_config_write { 1895 __le16 cmd_flags; 1896 __le16 element_count; 1897 u8 reserved[4]; 1898 __le32 address_high; 1899 __le32 address_low; 1900 }; 1901 1902 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 1903 1904 /* Used for 0x0704 as well as for 0x0705 commands */ 1905 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 1906 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 1907 #define I40E_AQ_ANVM_FEATURE 0 1908 #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT) 1909 struct i40e_aqc_nvm_config_data_feature { 1910 __le16 feature_id; 1911 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 1912 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 1913 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 1914 __le16 feature_options; 1915 __le16 feature_selection; 1916 }; 1917 1918 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); 1919 1920 struct i40e_aqc_nvm_config_data_immediate_field { 1921 __le32 field_id; 1922 __le32 field_value; 1923 __le16 field_options; 1924 __le16 reserved; 1925 }; 1926 1927 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); 1928 1929 /* OEM Post Update (indirect 0x0720) 1930 * no command data struct used 1931 */ 1932 struct i40e_aqc_nvm_oem_post_update { 1933 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01 1934 u8 sel_data; 1935 u8 reserved[7]; 1936 }; 1937 1938 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update); 1939 1940 struct i40e_aqc_nvm_oem_post_update_buffer { 1941 u8 str_len; 1942 u8 dev_addr; 1943 __le16 eeprom_addr; 1944 u8 data[36]; 1945 }; 1946 1947 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer); 1948 1949 /* Send to PF command (indirect 0x0801) id is only used by PF 1950 * Send to VF command (indirect 0x0802) id is only used by PF 1951 * Send to Peer PF command (indirect 0x0803) 1952 */ 1953 struct i40e_aqc_pf_vf_message { 1954 __le32 id; 1955 u8 reserved[4]; 1956 __le32 addr_high; 1957 __le32 addr_low; 1958 }; 1959 1960 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 1961 1962 /* Alternate structure */ 1963 1964 /* Direct write (direct 0x0900) 1965 * Direct read (direct 0x0902) 1966 */ 1967 struct i40e_aqc_alternate_write { 1968 __le32 address0; 1969 __le32 data0; 1970 __le32 address1; 1971 __le32 data1; 1972 }; 1973 1974 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 1975 1976 /* Indirect write (indirect 0x0901) 1977 * Indirect read (indirect 0x0903) 1978 */ 1979 1980 struct i40e_aqc_alternate_ind_write { 1981 __le32 address; 1982 __le32 length; 1983 __le32 addr_high; 1984 __le32 addr_low; 1985 }; 1986 1987 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 1988 1989 /* Done alternate write (direct 0x0904) 1990 * uses i40e_aq_desc 1991 */ 1992 struct i40e_aqc_alternate_write_done { 1993 __le16 cmd_flags; 1994 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 1995 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 1996 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 1997 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2 1998 u8 reserved[14]; 1999 }; 2000 2001 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 2002 2003 /* Set OEM mode (direct 0x0905) */ 2004 struct i40e_aqc_alternate_set_mode { 2005 __le32 mode; 2006 #define I40E_AQ_ALTERNATE_MODE_NONE 0 2007 #define I40E_AQ_ALTERNATE_MODE_OEM 1 2008 u8 reserved[12]; 2009 }; 2010 2011 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 2012 2013 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 2014 2015 /* async events 0x10xx */ 2016 2017 /* Lan Queue Overflow Event (direct, 0x1001) */ 2018 struct i40e_aqc_lan_overflow { 2019 __le32 prtdcb_rupto; 2020 __le32 otx_ctl; 2021 u8 reserved[8]; 2022 }; 2023 2024 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 2025 2026 /* Get LLDP MIB (indirect 0x0A00) */ 2027 struct i40e_aqc_lldp_get_mib { 2028 u8 type; 2029 u8 reserved1; 2030 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 2031 #define I40E_AQ_LLDP_MIB_LOCAL 0x0 2032 #define I40E_AQ_LLDP_MIB_REMOTE 0x1 2033 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 2034 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 2035 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 2036 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 2037 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 2038 #define I40E_AQ_LLDP_TX_SHIFT 0x4 2039 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 2040 /* TX pause flags use I40E_AQ_LINK_TX_* above */ 2041 __le16 local_len; 2042 __le16 remote_len; 2043 u8 reserved2[2]; 2044 __le32 addr_high; 2045 __le32 addr_low; 2046 }; 2047 2048 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 2049 2050 /* Configure LLDP MIB Change Event (direct 0x0A01) 2051 * also used for the event (with type in the command field) 2052 */ 2053 struct i40e_aqc_lldp_update_mib { 2054 u8 command; 2055 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2056 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 2057 u8 reserved[7]; 2058 __le32 addr_high; 2059 __le32 addr_low; 2060 }; 2061 2062 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 2063 2064 /* Add LLDP TLV (indirect 0x0A02) 2065 * Delete LLDP TLV (indirect 0x0A04) 2066 */ 2067 struct i40e_aqc_lldp_add_tlv { 2068 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2069 u8 reserved1[1]; 2070 __le16 len; 2071 u8 reserved2[4]; 2072 __le32 addr_high; 2073 __le32 addr_low; 2074 }; 2075 2076 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 2077 2078 /* Update LLDP TLV (indirect 0x0A03) */ 2079 struct i40e_aqc_lldp_update_tlv { 2080 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2081 u8 reserved; 2082 __le16 old_len; 2083 __le16 new_offset; 2084 __le16 new_len; 2085 __le32 addr_high; 2086 __le32 addr_low; 2087 }; 2088 2089 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 2090 2091 /* Stop LLDP (direct 0x0A05) */ 2092 struct i40e_aqc_lldp_stop { 2093 u8 command; 2094 #define I40E_AQ_LLDP_AGENT_STOP 0x0 2095 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 2096 u8 reserved[15]; 2097 }; 2098 2099 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 2100 2101 /* Start LLDP (direct 0x0A06) */ 2102 2103 struct i40e_aqc_lldp_start { 2104 u8 command; 2105 #define I40E_AQ_LLDP_AGENT_START 0x1 2106 u8 reserved[15]; 2107 }; 2108 2109 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 2110 2111 /* Get CEE DCBX Oper Config (0x0A07) 2112 * uses the generic descriptor struct 2113 * returns below as indirect response 2114 */ 2115 2116 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2117 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2118 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2119 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2120 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2121 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2122 2123 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2124 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2125 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2126 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2127 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2128 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2129 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8 2130 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT) 2131 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB 2132 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT) 2133 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10 2134 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT) 2135 2136 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with 2137 * word boundary layout issues, which the Linux compilers silently deal 2138 * with by adding padding, making the actual struct larger than designed. 2139 * However, the FW compiler for the NIC is less lenient and complains 2140 * about the struct. Hence, the struct defined here has an extra byte in 2141 * fields reserved3 and reserved4 to directly acknowledge that padding, 2142 * and the new length is used in the length check macro. 2143 */ 2144 struct i40e_aqc_get_cee_dcb_cfg_v1_resp { 2145 u8 reserved1; 2146 u8 oper_num_tc; 2147 u8 oper_prio_tc[4]; 2148 u8 reserved2; 2149 u8 oper_tc_bw[8]; 2150 u8 oper_pfc_en; 2151 u8 reserved3[2]; 2152 __le16 oper_app_prio; 2153 u8 reserved4[2]; 2154 __le16 tlv_status; 2155 }; 2156 2157 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp); 2158 2159 struct i40e_aqc_get_cee_dcb_cfg_resp { 2160 u8 oper_num_tc; 2161 u8 oper_prio_tc[4]; 2162 u8 oper_tc_bw[8]; 2163 u8 oper_pfc_en; 2164 __le16 oper_app_prio; 2165 __le32 tlv_status; 2166 u8 reserved[12]; 2167 }; 2168 2169 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp); 2170 2171 /* Set Local LLDP MIB (indirect 0x0A08) 2172 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx 2173 */ 2174 struct i40e_aqc_lldp_set_local_mib { 2175 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0 2176 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) 2177 u8 type; 2178 u8 reserved0; 2179 __le16 length; 2180 u8 reserved1[4]; 2181 __le32 address_high; 2182 __le32 address_low; 2183 }; 2184 2185 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib); 2186 2187 /* Stop/Start LLDP Agent (direct 0x0A09) 2188 * Used for stopping/starting specific LLDP agent. e.g. DCBx 2189 */ 2190 struct i40e_aqc_lldp_stop_start_specific_agent { 2191 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0 2192 #define I40E_AQC_START_SPECIFIC_AGENT_MASK (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT) 2193 u8 command; 2194 u8 reserved[15]; 2195 }; 2196 2197 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent); 2198 2199 /* Add Udp Tunnel command and completion (direct 0x0B00) */ 2200 struct i40e_aqc_add_udp_tunnel { 2201 __le16 udp_port; 2202 u8 reserved0[3]; 2203 u8 protocol_type; 2204 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2205 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2206 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2207 u8 reserved1[10]; 2208 }; 2209 2210 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2211 2212 struct i40e_aqc_add_udp_tunnel_completion { 2213 __le16 udp_port; 2214 u8 filter_entry_index; 2215 u8 multiple_pfs; 2216 #define I40E_AQC_SINGLE_PF 0x0 2217 #define I40E_AQC_MULTIPLE_PFS 0x1 2218 u8 total_filters; 2219 u8 reserved[11]; 2220 }; 2221 2222 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2223 2224 /* remove UDP Tunnel command (0x0B01) */ 2225 struct i40e_aqc_remove_udp_tunnel { 2226 u8 reserved[2]; 2227 u8 index; /* 0 to 15 */ 2228 u8 reserved2[13]; 2229 }; 2230 2231 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2232 2233 struct i40e_aqc_del_udp_tunnel_completion { 2234 __le16 udp_port; 2235 u8 index; /* 0 to 15 */ 2236 u8 multiple_pfs; 2237 u8 total_filters_used; 2238 u8 reserved1[11]; 2239 }; 2240 2241 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2242 #ifdef X722_SUPPORT 2243 2244 struct i40e_aqc_get_set_rss_key { 2245 #define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15) 2246 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0 2247 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \ 2248 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) 2249 __le16 vsi_id; 2250 u8 reserved[6]; 2251 __le32 addr_high; 2252 __le32 addr_low; 2253 }; 2254 2255 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key); 2256 2257 struct i40e_aqc_get_set_rss_key_data { 2258 u8 standard_rss_key[0x28]; 2259 u8 extended_hash_key[0xc]; 2260 }; 2261 2262 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data); 2263 2264 struct i40e_aqc_get_set_rss_lut { 2265 #define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15) 2266 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0 2267 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \ 2268 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) 2269 __le16 vsi_id; 2270 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 2271 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \ 2272 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) 2273 2274 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0 2275 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1 2276 __le16 flags; 2277 u8 reserved[4]; 2278 __le32 addr_high; 2279 __le32 addr_low; 2280 }; 2281 2282 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut); 2283 #endif 2284 2285 /* tunnel key structure 0x0B10 */ 2286 2287 struct i40e_aqc_tunnel_key_structure { 2288 u8 key1_off; 2289 u8 key2_off; 2290 u8 key1_len; /* 0 to 15 */ 2291 u8 key2_len; /* 0 to 15 */ 2292 u8 flags; 2293 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2294 /* response flags */ 2295 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2296 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2297 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2298 u8 network_key_index; 2299 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2300 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2301 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2302 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2303 u8 reserved[10]; 2304 }; 2305 2306 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2307 2308 /* OEM mode commands (direct 0xFE0x) */ 2309 struct i40e_aqc_oem_param_change { 2310 __le32 param_type; 2311 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2312 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2313 #define I40E_AQ_OEM_PARAM_MAC 2 2314 __le32 param_value1; 2315 __le16 param_value2; 2316 u8 reserved[6]; 2317 }; 2318 2319 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2320 2321 struct i40e_aqc_oem_state_change { 2322 __le32 state; 2323 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2324 #define I40E_AQ_OEM_STATE_LINK_UP 0x1 2325 u8 reserved[12]; 2326 }; 2327 2328 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2329 2330 /* Initialize OCSD (0xFE02, direct) */ 2331 struct i40e_aqc_opc_oem_ocsd_initialize { 2332 u8 type_status; 2333 u8 reserved1[3]; 2334 __le32 ocsd_memory_block_addr_high; 2335 __le32 ocsd_memory_block_addr_low; 2336 __le32 requested_update_interval; 2337 }; 2338 2339 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); 2340 2341 /* Initialize OCBB (0xFE03, direct) */ 2342 struct i40e_aqc_opc_oem_ocbb_initialize { 2343 u8 type_status; 2344 u8 reserved1[3]; 2345 __le32 ocbb_memory_block_addr_high; 2346 __le32 ocbb_memory_block_addr_low; 2347 u8 reserved2[4]; 2348 }; 2349 2350 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); 2351 2352 /* debug commands */ 2353 2354 /* get device id (0xFF00) uses the generic structure */ 2355 2356 /* set test more (0xFF01, internal) */ 2357 2358 struct i40e_acq_set_test_mode { 2359 u8 mode; 2360 #define I40E_AQ_TEST_PARTIAL 0 2361 #define I40E_AQ_TEST_FULL 1 2362 #define I40E_AQ_TEST_NVM 2 2363 u8 reserved[3]; 2364 u8 command; 2365 #define I40E_AQ_TEST_OPEN 0 2366 #define I40E_AQ_TEST_CLOSE 1 2367 #define I40E_AQ_TEST_INC 2 2368 u8 reserved2[3]; 2369 __le32 address_high; 2370 __le32 address_low; 2371 }; 2372 2373 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2374 2375 /* Debug Read Register command (0xFF03) 2376 * Debug Write Register command (0xFF04) 2377 */ 2378 struct i40e_aqc_debug_reg_read_write { 2379 __le32 reserved; 2380 __le32 address; 2381 __le32 value_high; 2382 __le32 value_low; 2383 }; 2384 2385 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2386 2387 /* Scatter/gather Reg Read (indirect 0xFF05) 2388 * Scatter/gather Reg Write (indirect 0xFF06) 2389 */ 2390 2391 /* i40e_aq_desc is used for the command */ 2392 struct i40e_aqc_debug_reg_sg_element_data { 2393 __le32 address; 2394 __le32 value; 2395 }; 2396 2397 /* Debug Modify register (direct 0xFF07) */ 2398 struct i40e_aqc_debug_modify_reg { 2399 __le32 address; 2400 __le32 value; 2401 __le32 clear_mask; 2402 __le32 set_mask; 2403 }; 2404 2405 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2406 2407 /* dump internal data (0xFF08, indirect) */ 2408 2409 #define I40E_AQ_CLUSTER_ID_AUX 0 2410 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2411 #define I40E_AQ_CLUSTER_ID_TXSCHED 2 2412 #define I40E_AQ_CLUSTER_ID_HMC 3 2413 #define I40E_AQ_CLUSTER_ID_MAC0 4 2414 #define I40E_AQ_CLUSTER_ID_MAC1 5 2415 #define I40E_AQ_CLUSTER_ID_MAC2 6 2416 #define I40E_AQ_CLUSTER_ID_MAC3 7 2417 #define I40E_AQ_CLUSTER_ID_DCB 8 2418 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2419 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2420 #define I40E_AQ_CLUSTER_ID_ALTRAM 11 2421 2422 struct i40e_aqc_debug_dump_internals { 2423 u8 cluster_id; 2424 u8 table_id; 2425 __le16 data_size; 2426 __le32 idx; 2427 __le32 address_high; 2428 __le32 address_low; 2429 }; 2430 2431 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 2432 2433 struct i40e_aqc_debug_modify_internals { 2434 u8 cluster_id; 2435 u8 cluster_specific_params[7]; 2436 __le32 address_high; 2437 __le32 address_low; 2438 }; 2439 2440 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 2441 2442 #endif 2443